Revision Date: Jul. 09
,
2004
16 H8/38086R Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8 Family / H8/300H Super Low Power Series
H8/38086RF
H8/38086R
H8/38085R
H8/38084R
H8/38083R
Rev.1.00
REJ09B0182-0100Z
Rev. 1.00, 07/04, page ii of xxxiv
Rev. 1.00, 07/04, page iii of xxxiv
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-
party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Renesas
Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must
be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Keep safety first in your circuit designs!
Notes regarding these materials
Rev. 1.00, 07/04, page iv of xxxiv
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass-
through current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product's state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system's
operation is not guaranteed if they are accessed.
Rev. 1.00, 07/04, page v of xxxiv
Configuration of This Manual
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 1.00, 07/04, page vi of xxxiv
Preface
H8/38086R Group is single-chip microcomputers made up of the high-speed H8/300H CPU
employing Renesas Technology original architecture as their cores, and the peripheral functions
required to configure a system. The H8/300H CPU has an instruction set that is compatible with
the H8/300 CPU.
Target Users: This manual was written for users who will be using the H8/38086R Group in the
design of application systems. Target users are expected to understand the
fundamentals of electrical circuits, logical circuits, and microcomputers.
Objective: This manual was written to explain the hardware functions and electrical
characteristics of the H8/38086R Group to the target users.
Refer to the H8/300H Series Programming Manual for a detailed description of the
instruction set.
Notes on reading this manual:
• In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions, and electrical characteristics.
• In order to understand the details of the CPU's functions
Read the H8/300H Series Programming Manual.
• In order to understand the details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 24,
List of Registers.
Example: Register name: The following notation is used for cases when the same or a
similar function, e.g. serial communication interface, is
implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
Bit order: The MSB is on the left and the LSB is on the right.
Rev. 1.00, 07/04, page vii of xxxiv
Notes:
When using an on-chip emulator (E7) for H8/38086R program development and debugging, the
following restrictions must be noted.
1. The NMI pin is reserved for the E7, and cannot be used.
2. Pins P16, P36, and P37 cannot be used. In order to use these pins, additional hardware must be
provided on the user board.
3. Area H'C000 to H'CFFF is used by the E7, and is not available to the user.
4. Area H′F380 to H′F77F must on no account be accessed.
5. When the E7 is used, address breaks can be set as either available to the user or for use by the
E7. If address breaks are set as being used by the E7, the address break control registers must
not be accessed.
6. When the E7 is used, NMI is an input pin, P16 and P36 are input pins, and P37 is an output
pin.
Related Manuals: The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/eng/
H8/38086R Group manuals:
Document Title Document No.
H8/38086R Group Hardware Manual This manual
H8/300H Series Programming Manual ADE-602-053
User's manuals for development tools:
Document Title Document No.
H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor
User's Manual
REJ10B0058
Microcomputer Development, Environment System H8S H8/300 Series
Simulator/Debugger User's Manual
ADE-702-282
H8S, H8/300 Series High-performance Embedded Workshop 3 Tutorial REJ10B0024
H8S, H8/300 Series High-performance Embedded Workshop 3
User's Manual
REJ10B0026
Application notes:
Document Title Document No.
F-ZTAT Micro Computer Single Power Supply F-ZTATTM On-Board
Programming
ADE-502-055
Rev. 1.00, 07/04, page viii of xxxiv
Rev. 1.00, 07/04, page ix of xxxiv
Contents
Section 1 Overview............................................................................................1
1.1 Features............................................................................................................................. 1
1.2 Internal Block Diagram..................................................................................................... 3
1.3 Pin Assignment ................................................................................................................. 4
1.4 Pin Functions .................................................................................................................... 13
Section 2 CPU....................................................................................................19
2.1 Address Space and Memory Map ..................................................................................... 20
2.2 Register Configuration...................................................................................................... 21
2.2.1 General Registers................................................................................................. 22
2.2.2 Program Counter (PC) ......................................................................................... 23
2.2.3 Condition-Code Register (CCR).......................................................................... 23
2.3 Data Formats..................................................................................................................... 25
2.3.1 General Register Data Formats ............................................................................ 25
2.3.2 Memory Data Formats ......................................................................................... 27
2.4 Instruction Set................................................................................................................... 28
2.4.1 Table of Instructions Classified by Function ....................................................... 28
2.4.2 Basic Instruction Formats .................................................................................... 38
2.5 Addressing Modes and Effective Address Calculation..................................................... 39
2.5.1 Addressing Modes ............................................................................................... 39
2.5.2 Effective Address Calculation ............................................................................. 42
2.6 Basic Bus Cycle ................................................................................................................ 44
2.6.1 Access to On-Chip Memory (RAM, ROM)......................................................... 44
2.6.2 On-Chip Peripheral Modules ............................................................................... 45
2.7 CPU States ........................................................................................................................ 46
2.8 Usage Notes ...................................................................................................................... 47
2.8.1 Notes on Data Access to Empty Areas ................................................................ 47
2.8.2 EEPMOV Instruction........................................................................................... 47
2.8.3 Bit-Manipulation Instruction ............................................................................... 48
Section 3 Exception Handling ...........................................................................53
3.1 Exception Sources and Vector Address ............................................................................ 54
3.2 Reset ................................................................................................................................. 55
3.2.1 Reset Exception Handling.................................................................................... 55
3.2.2 Interrupt Immediately after Reset ........................................................................ 56
3.3 Interrupts........................................................................................................................... 57
3.4 Stack Status after Exception Handling.............................................................................. 58
3.4.1 Interrupt Response Time...................................................................................... 58
3.5 Usage Notes ...................................................................................................................... 59
Rev. 1.00, 07/04, page x of xxxiv
3.5.1 Notes on Stack Area Use ..................................................................................... 59
3.5.2 Notes on Rewriting Port Mode Registers ............................................................ 60
3.5.3 Method for Clearing Interrupt Request Flags ...................................................... 63
Section 4 Interrupt Controller............................................................................65
4.1 Features............................................................................................................................. 65
4.2 Input/Output Pins.............................................................................................................. 66
4.3 Register Descriptions........................................................................................................ 66
4.3.1 Interrupt Edge Select Register (IEGR) ................................................................ 67
4.3.2 Wakeup Edge Select Register (WEGR)............................................................... 68
4.3.3 Interrupt Enable Register 1 (IENR1) ................................................................... 69
4.3.4 Interrupt Enable Register 2 (IENR2) ................................................................... 70
4.3.5 Interrupt Request Register 1 (IRR1) .................................................................... 71
4.3.6 Interrupt Request Register 2 (IRR2) .................................................................... 72
4.3.7 Wakeup Interrupt Request Register (IWPR) ....................................................... 73
4.3.8 Interrupt Priority Registers A to E (IPRA to IPRE)............................................. 75
4.3.9 Interrupt Mask Register (INTM) ......................................................................... 76
4.4 Interrupt Sources...............................................................................................................76
4.4.1 External Interrupts ............................................................................................... 76
4.4.2 Internal Interrupts ................................................................................................ 77
4.5 Interrupt Exception Handling Vector Table...................................................................... 78
4.6 Operation .......................................................................................................................... 80
4.6.1 Interrupt Exception Handling Sequence .............................................................. 81
4.6.2 Interrupt Response Times .................................................................................... 83
4.7 Usage Notes...................................................................................................................... 84
4.7.1 Contention between Interrupt Generation and Disabling..................................... 84
4.7.2 Instructions that Disable Interrupts...................................................................... 85
4.7.3 Interrupts during Execution of EEPMOV Instruction ......................................... 85
4.7.4 IENR Clearing ..................................................................................................... 85
Section 5 Clock Pulse Generators .....................................................................87
5.1 Register Description ......................................................................................................... 88
5.1.1 SUB32k Control Register (SUB32CR) ............................................................... 88
5.1.2 Oscillator Control Register (OSCCR) ................................................................. 89
5.2 System Clock Generator ................................................................................................... 90
5.2.1 Connecting Crystal Resonator ............................................................................. 90
5.2.2 Connecting Ceramic Resonator ........................................................................... 91
5.2.3 External Clock Input Method .............................................................................. 91
5.2.4 On-Chip Oscillator Selection Method
(Supported only by the Masked ROM Version) .................................................. 92
5.3 Subclock Generator........................................................................................................... 93
5.3.1 Connecting 32.768-kHz/38.4-kHz Crystal Resonator ......................................... 93
5.3.2 Pin Connection when not Using Subclock........................................................... 94
Rev. 1.00, 07/04, page xi of xxxiv
5.3.3 External Clock Input............................................................................................ 94
5.4 Prescalers .......................................................................................................................... 95
5.4.1 Prescaler S ........................................................................................................... 95
5.5 Usage Notes ...................................................................................................................... 96
5.5.1 Note on Resonators.............................................................................................. 96
5.5.2 Notes on Board Design ........................................................................................ 98
5.5.3 Definition of Oscillation Stabilization Wait Time ............................................... 98
5.5.4 Note on Subclock Stop State................................................................................ 100
5.5.5 Note on Using Resonator..................................................................................... 100
5.5.6 Note on Using Power-On Reset...........................................................................101
Section 6 Power-Down Modes ..........................................................................103
6.1 Register Descriptions ........................................................................................................ 104
6.1.1 System Control Register 1 (SYSCR1) ................................................................. 104
6.1.2 System Control Register 2 (SYSCR2) ................................................................. 106
6.1.3 Clock Halt Registers 1 and 2 (CKSTPR1 and CKSTPR2) .................................. 107
6.2 Mode Transitions and States of LSI.................................................................................. 109
6.2.1 Sleep Mode .......................................................................................................... 113
6.2.2 Standby Mode......................................................................................................113
6.2.3 Watch Mode......................................................................................................... 114
6.2.4 Subsleep Mode..................................................................................................... 114
6.2.5 Subactive Mode ................................................................................................... 115
6.2.6 Active (Medium-Speed) Mode ............................................................................ 115
6.3 Direct Transition ...............................................................................................................116
6.3.1 Direct Transition from Active (High-Speed) Mode to Active
(Medium-Speed) Mode ........................................................................................ 117
6.3.2 Direct Transition from Active (Medium-Speed) Mode to Active
(High-Speed) Mode..............................................................................................117
6.3.3 Direct Transition from Subactive Mode to Active (High-Speed) Mode.............. 118
6.3.4 Direct Transition from Subactive Mode to Active (Medium-Speed) Mode ........ 118
6.3.5 Notes on External Input Signal Changes before/after Direct Transition.............. 119
6.4 Module Standby Function................................................................................................. 119
6.5 Usage Notes ...................................................................................................................... 120
6.5.1 Standby Mode Transition and Pin States ............................................................. 120
6.5.2 Notes on External Input Signal Changes before/after Standby Mode.................. 120
Section 7 ROM ..................................................................................................123
7.1 Block Configuration.......................................................................................................... 124
7.2 Register Descriptions ........................................................................................................ 125
7.2.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 125
7.2.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 126
7.2.3 Erase Block Register 1 (EBR1) ........................................................................... 127
7.2.4 Flash Memory Power Control Register (FLPWCR) ............................................ 128
Rev. 1.00, 07/04, page xii of xxxiv
7.2.5 Flash Memory Enable Register (FENR).............................................................. 128
7.3 On-Board Programming Modes........................................................................................ 129
7.3.1 Boot Mode ........................................................................................................... 130
7.3.2 Programming/Erasing in User Program Mode..................................................... 132
7.4 Flash Memory Programming/Erasing............................................................................... 133
7.4.1 Program/Program-Verify ..................................................................................... 133
7.4.2 Erase/Erase-Verify............................................................................................... 136
7.4.3 Interrupt Handling when Programming/Erasing Flash Memory.......................... 136
7.5 Program/Erase Protection ................................................................................................. 138
7.5.1 Hardware Protection ............................................................................................ 138
7.5.2 Software Protection ............................................................................................. 138
7.5.3 Error Protection ................................................................................................... 138
7.6 Programmer Mode ............................................................................................................ 139
7.7 Power-Down States for Flash Memory............................................................................. 139
7.8 Notes on Setting Module Standby Mode .......................................................................... 140
Section 8 RAM ..................................................................................................141
Section 9 I/O Ports.............................................................................................143
9.1 Port 1................................................................................................................................. 143
9.1.1 Port Data Register 1 (PDR1) ............................................................................... 144
9.1.2 Port Control Register 1 (PCR1) ........................................................................... 144
9.1.3 Port Pull-Up Control Register 1 (PUCR1)........................................................... 145
9.1.4 Port Mode Register 1 (PMR1) ............................................................................. 145
9.1.5 Pin Functions ....................................................................................................... 146
9.1.6 Input Pull-Up MOS.............................................................................................. 150
9.2 Port 3................................................................................................................................. 151
9.2.1 Port Data Register 3 (PDR3) ............................................................................... 151
9.2.2 Port Control Register 3 (PCR3) ........................................................................... 152
9.2.3 Port Pull-Up Control Register 3 (PUCR3)........................................................... 152
9.2.4 Port Mode Register 3 (PMR3) ............................................................................. 153
9.2.5 Pin Functions ....................................................................................................... 153
9.2.6 Input Pull-Up MOS.............................................................................................. 155
9.3 Port 4................................................................................................................................. 155
9.3.1 Port Data Register 4 (PDR4) ............................................................................... 156
9.3.2 Port Control Register 4 (PCR4) ........................................................................... 156
9.3.3 Port Mode Register 4 (PMR4) ............................................................................. 157
9.3.4 Pin Functions ....................................................................................................... 157
9.4 Port 5................................................................................................................................. 159
9.4.1 Port Data Register 5 (PDR5) ............................................................................... 159
9.4.2 Port Control Register 5 (PCR5) ........................................................................... 160
9.4.3 Port Pull-Up Control Register 5 (PUCR5)........................................................... 160
9.4.4 Port Mode Register 5 (PMR5) ............................................................................. 161
Rev. 1.00, 07/04, page xiii of xxxiv
9.4.5 Pin Functions ....................................................................................................... 161
9.4.6 Input Pull-Up MOS.............................................................................................. 162
9.5 Port 6................................................................................................................................. 163
9.5.1 Port Data Register 6 (PDR6)................................................................................ 163
9.5.2 Port Control Register 6 (PCR6) ........................................................................... 164
9.5.3 Port Pull-Up Control Register 6 (PUCR6)...........................................................164
9.5.4 Pin Functions ....................................................................................................... 165
9.5.5 Input Pull-Up MOS.............................................................................................. 165
9.6 Port 7................................................................................................................................. 166
9.6.1 Port Data Register 7 (PDR7)................................................................................ 166
9.6.2 Port Control Register 7 (PCR7) ........................................................................... 167
9.6.3 Pin Functions ....................................................................................................... 167
9.7 Port 8................................................................................................................................. 168
9.7.1 Port Data Register 8 (PDR8)................................................................................ 168
9.7.2 Port Control Register 8 (PCR8) ........................................................................... 169
9.7.3 Pin Functions ....................................................................................................... 169
9.8 Port 9................................................................................................................................. 170
9.8.1 Port Data Register 9 (PDR9)................................................................................ 170
9.8.2 Port Control Register 9 (PCR9) ........................................................................... 171
9.8.3 Port Mode Register 9 (PMR9) ............................................................................. 171
9.8.4 Pin Functions ....................................................................................................... 172
9.9 Port A................................................................................................................................ 173
9.9.1 Port Data Register A (PDRA).............................................................................. 173
9.9.2 Port Control Register A (PCRA) ......................................................................... 174
9.9.3 Pin Functions ....................................................................................................... 174
9.10 Port B ................................................................................................................................ 176
9.10.1 Port Data Register B (PDRB) .............................................................................. 176
9.10.2 Port Mode Register B (PMRB)............................................................................ 177
9.10.3 Pin Functions ....................................................................................................... 178
9.11 Input/Output Data Inversion ............................................................................................. 180
9.11.1 Serial Port Control Register (SPCR).................................................................... 180
9.12 Usage Notes ...................................................................................................................... 181
9.12.1 How to Handle Unused Pin.................................................................................. 181
Section 10 Realtime Clock (RTC) .....................................................................183
10.1 Features............................................................................................................................. 183
10.2 Input/Output Pin................................................................................................................184
10.3 Register Descriptions ........................................................................................................ 184
10.3.1 Second Data Register/Free Running Counter Data Register (RSECDR) ............ 185
10.3.2 Minute Data Register (RMINDR)........................................................................ 185
10.3.3 Hour Data Register (RHRDR) ............................................................................. 186
10.3.4 Day-of-Week Data Register (RWKDR) .............................................................. 187
10.3.5 RTC Control Register 1 (RTCCR1).....................................................................188
Rev. 1.00, 07/04, page xiv of xxxiv
10.3.6 RTC Control Register 2 (RTCCR2) .................................................................... 189
10.3.7 Clock Source Select Register (RTCCSR)............................................................ 190
10.3.8 RTC Interrupt Flag Register (RTCFLG) ............................................................. 191
10.4 Operation .......................................................................................................................... 192
10.4.1 Initial Settings of Registers after Power-On ........................................................ 192
10.4.2 Initial Setting Procedure ...................................................................................... 192
10.4.3 Data Reading Procedure ...................................................................................... 193
10.5 Interrupt Sources...............................................................................................................194
10.6 Usage Note........................................................................................................................ 194
10.6.1 Note on Clock Count ........................................................................................... 194
Section 11 Timer F ............................................................................................ 195
11.1 Features............................................................................................................................. 195
11.2 Input/Output Pins.............................................................................................................. 197
11.3 Register Descriptions........................................................................................................ 197
11.3.1 Timer Counters FH and FL (TCFH, TCFL) ........................................................ 197
11.3.2 Output Compare Registers FH and FL (OCRFH, OCRFL)................................. 198
11.3.3 Timer Control Register F (TCR).......................................................................... 199
11.3.4 Timer Control/Status Register F (TCSRF) .......................................................... 200
11.4 Operation .......................................................................................................................... 202
11.4.1 Timer F Operation ............................................................................................... 202
11.4.2 TCF Increment Timing ........................................................................................ 203
11.4.3 TMOFH/TMOFL Output Timing........................................................................ 203
11.4.4 TCF Clear Timing................................................................................................ 204
11.4.5 Timer Overflow Flag (OVF) Set Timing............................................................. 204
11.4.6 Compare Match Flag Set Timing......................................................................... 204
11.5 Timer F Operating States .................................................................................................. 204
11.6 Usage Notes...................................................................................................................... 205
11.6.1 16-Bit Timer Mode .............................................................................................. 205
11.6.2 8-Bit Timer Mode................................................................................................ 205
11.6.3 Flag Clearing ....................................................................................................... 206
11.6.4 Timer Counter (TCF) Read/Write ....................................................................... 208
Section 12 16-Bit Timer Pulse Unit (TPU) .......................................................209
12.1 Features............................................................................................................................. 209
12.2 Input/Output Pins.............................................................................................................. 211
12.3 Register Descriptions........................................................................................................ 212
12.3.1 Timer Control Register (TCR)............................................................................. 213
12.3.2 Timer Mode Register (TMDR)............................................................................ 215
12.3.3 Timer I/O Control Register (TIOR)..................................................................... 216
12.3.4 Timer Interrupt Enable Register (TIER).............................................................. 221
12.3.5 Timer Status Register (TSR)................................................................................ 222
12.3.6 Timer Counter (TCNT)........................................................................................ 223
Rev. 1.00, 07/04, page xv of xxxiv
12.3.7 Timer General Register (TGR) ............................................................................ 223
12.3.8 Timer Start Register (TSTR) ............................................................................... 224
12.3.9 Timer Synchro Register (TSYR) ......................................................................... 225
12.4 Interface to CPU ............................................................................................................... 226
12.4.1 16-Bit Registers ................................................................................................... 226
12.4.2 8-Bit Registers ..................................................................................................... 226
12.5 Operation .......................................................................................................................... 228
12.5.1 Basic Functions.................................................................................................... 228
12.5.2 Synchronous Operation........................................................................................ 233
12.5.3 Operation with Cascaded Connection.................................................................. 235
12.5.4 PWM Modes........................................................................................................ 237
12.6 Interrupt Sources...............................................................................................................241
12.7 Operation Timing.............................................................................................................. 242
12.7.1 Input/Output Timing ............................................................................................ 242
12.7.2 Interrupt Signal Timing........................................................................................245
12.8 Usage Notes ...................................................................................................................... 247
12.8.1 Module Standby Function Setting........................................................................ 247
12.8.2 Input Clock Restrictions ...................................................................................... 247
12.8.3 Caution on Period Setting .................................................................................... 247
12.8.4 Contention between TCNT Write and Clear Operation ...................................... 248
12.8.5 Contention between TCNT Write and Increment Operation ............................... 248
12.8.6 Contention between TGR Write and Compare Match ......................................... 249
12.8.7 Contention between TGR Read and Input Capture.............................................. 250
12.8.8 Contention between TGR Write and Input Capture.............................................250
12.8.9 Contention between Overflow and Counter Clearing .......................................... 251
12.8.10 Contention between TCNT Write and Overflow ................................................. 251
12.8.11 Multiplexing of I/O Pins ...................................................................................... 252
12.8.12 Interrupts when Module Standby Function is Used ............................................. 252
Section 13 Asynchronous Event Counter (AEC) ..............................................253
13.1 Features............................................................................................................................. 253
13.2 Input/Output Pins .............................................................................................................. 254
13.3 Register Descriptions ........................................................................................................ 255
13.3.1 Event Counter PWM Compare Register (ECPWCR) .......................................... 255
13.3.2 Event Counter PWM Data Register (ECPWDR)................................................. 256
13.3.3 Input Pin Edge Select Register (AEGSR)............................................................ 257
13.3.4 Event Counter Control Register (ECCR)............................................................. 258
13.3.5 Event Counter Control/Status Register (ECCSR)................................................ 259
13.3.6 Event Counter H (ECH)....................................................................................... 261
13.3.7 Event Counter L (ECL)........................................................................................ 261
13.4 Operation .......................................................................................................................... 262
13.4.1 16-Bit Counter Operation .................................................................................... 262
13.4.2 8-Bit Counter Operation ...................................................................................... 263
Rev. 1.00, 07/04, page xvi of xxxiv
13.4.3 IRQAEC Operation ............................................................................................. 264
13.4.4 Event Counter PWM Operation........................................................................... 264
13.4.5 Operation of Clock Input Enable/Disable Function............................................. 265
13.5 Operating States of Asynchronous Event Counter............................................................ 266
13.6 Usage Notes...................................................................................................................... 267
Section 14 Watchdog Timer..............................................................................269
14.1 Features............................................................................................................................. 269
14.2 Register Descriptions........................................................................................................ 270
14.2.1 Timer Control/Status Register WD1 (TCSRWD1).............................................. 270
14.2.2 Timer Control/Status Register WD2 (TCSRWD2).............................................. 272
14.2.3 Timer Counter WD (TCWD)............................................................................... 273
14.2.4 Timer Mode Register WD (TMWD) ................................................................... 273
14.3 Operation .......................................................................................................................... 274
14.3.1 Watchdog Timer Mode........................................................................................ 274
14.3.2 Interval Timer Mode............................................................................................ 275
14.3.3 Timing of Overflow Flag (OVF) Setting ............................................................. 275
14.4 Interrupt ............................................................................................................................ 276
14.5 Usage Notes...................................................................................................................... 276
14.5.1 Switching between Watchdog Timer Mode and Interval Timer Mode................ 276
14.5.2 Module Standby Mode Control ........................................................................... 276
Section 15 Serial Communication Interface 3 (SCI3, IrDA) ............................ 277
15.1 Features............................................................................................................................. 277
15.2 Input/Output Pins.............................................................................................................. 281
15.3 Register Descriptions........................................................................................................ 281
15.3.1 Receive Shift Register (RSR) .............................................................................. 282
15.3.2 Receive Data Register (RDR).............................................................................. 282
15.3.3 Transmit Shift Register (TSR)............................................................................. 282
15.3.4 Transmit Data Register (TDR)............................................................................. 282
15.3.5 Serial Mode Register (SMR) ............................................................................... 283
15.3.6 Serial Control Register (SCR) ............................................................................. 285
15.3.7 Serial Status Register (SSR) ................................................................................ 288
15.3.8 Bit Rate Register (BRR) ...................................................................................... 291
15.3.9 Serial Port Control Register (SPCR).................................................................... 297
15.3.10 IrDA Control Register (IrCR).............................................................................. 299
15.4 Operation in Asynchronous Mode .................................................................................... 300
15.4.1 Clock.................................................................................................................... 300
15.4.2 SCI3 Initialization................................................................................................ 304
15.4.3 Data Transmission ............................................................................................... 305
15.4.4 Serial Data Reception .......................................................................................... 307
15.5 Operation in Clocked Synchronous Mode ........................................................................ 311
15.5.1 Clock.................................................................................................................... 311
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15.5.2 SCI3 Initialization................................................................................................ 311
15.5.3 Serial Data Transmission ..................................................................................... 312
15.5.4 Serial Data Reception (Clocked Synchronous Mode).......................................... 314
15.5.5 Simultaneous Serial Data Transmission and Reception....................................... 316
15.6 Multiprocessor Communication Function......................................................................... 317
15.6.1 Multiprocessor Serial Data Transmission ............................................................ 318
15.6.2 Multiprocessor Serial Data Reception ................................................................. 319
15.7 IrDA Operation ................................................................................................................. 322
15.7.1 Transmission........................................................................................................ 322
15.7.2 Reception ............................................................................................................. 323
15.7.3 High-Level Pulse Width Selection....................................................................... 324
15.8 Interrupt Requests ............................................................................................................. 325
15.9 Usage Notes ...................................................................................................................... 328
15.9.1 Break Detection and Processing .......................................................................... 328
15.9.2 Mark State and Break Sending.............................................................................328
15.9.3 Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only)..................................................................... 328
15.9.4 Receive Data Sampling Timing and Reception Margin
in Asynchronous Mode ........................................................................................ 329
15.9.5 Note on Switching SCK31 (SCK32) Pin Function .............................................. 330
15.9.6 Relation between Writing to TDR and Bit TDRE ............................................... 330
15.9.7 Relation between RDR Reading and bit RDRF................................................... 331
15.9.8 Transmit and Receive Operations when Making State Transition....................... 331
15.9.9 Setting in Subactive or Subsleep Mode ............................................................... 331
Section 16 Serial Communication Interface 4 (SCI4) .......................................333
16.1 Features............................................................................................................................. 333
16.2 Input/Output Pins .............................................................................................................. 334
16.3 Register Descriptions ........................................................................................................ 335
16.3.1 Serial Control Register 4 (SCR4)......................................................................... 335
16.3.2 Serial Control/Status Register 4 (SCSR4) ........................................................... 338
16.3.3 Transmit Data Register 4 (TDR4)........................................................................ 341
16.3.4 Receive Data Register 4 (RDR4)......................................................................... 341
16.3.5 Shift Register 4 (SR4).......................................................................................... 341
16.4 Operation .......................................................................................................................... 342
16.4.1 Clock.................................................................................................................... 342
16.4.2 Data Transfer Format........................................................................................... 342
16.4.3 Data Transmission/Reception .............................................................................. 343
16.4.4 Data Transmission ............................................................................................... 344
16.4.5 Data Reception..................................................................................................... 346
16.4.6 Simultaneous Data Transmission and Reception ................................................. 348
16.5 Interrupt Sources...............................................................................................................349
16.6 Usage Notes ...................................................................................................................... 350
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16.6.1 Relationship between Writing to TDR4 and TDRE ............................................ 350
16.6.2 Receive Error Flag and Transmission.................................................................. 350
16.6.3 Relationship between Reading RDR4 and RDRF ............................................... 350
16.6.4 SCK4 Output Waveform when Internal Clock of φ/2 is Selected........................ 351
Section 17 14-Bit PWM ....................................................................................353
17.1 Features............................................................................................................................. 353
17.2 Input/Output Pins.............................................................................................................. 354
17.3 Register Descriptions........................................................................................................ 354
17.3.1 PWM Control Register (PWCR) ......................................................................... 355
17.3.2 PWM Data Register (PWDR).............................................................................. 355
17.4 Operation .......................................................................................................................... 356
17.4.1 Setting for Pulse-Division Type PWM Operation ............................................... 356
17.4.2 Setting for Standard PWM Operation.................................................................. 357
17.4.3 PWM Operating States ........................................................................................ 357
Section 18 A/D Converter ................................................................................. 359
18.1 Features............................................................................................................................. 359
18.2 Input/Output Pins.............................................................................................................. 361
18.3 Register Descriptions........................................................................................................ 361
18.3.1 A/D Result Register (ADRR) .............................................................................. 361
18.3.2 A/D Mode Register (AMR) ................................................................................. 362
18.3.3 A/D Start Register (ADSR) ................................................................................. 363
18.4 Operation .......................................................................................................................... 363
18.4.1 A/D Conversion ................................................................................................... 363
18.4.2 External Trigger Input Timing............................................................................. 364
18.4.3 Operating States of A/D Converter...................................................................... 364
18.5 Example of Use................................................................................................................. 365
18.6 A/D Conversion Accuracy Definitions ............................................................................. 368
18.7 Usage Notes...................................................................................................................... 369
18.7.1 Permissible Signal Source Impedance ................................................................. 369
18.7.2 Influences on Absolute Accuracy ........................................................................ 370
18.7.3 Usage Notes......................................................................................................... 370
Section 19 ∆Σ A/D Converter ........................................................................... 371
19.1 Features............................................................................................................................. 371
19.2 Input/Output Pins.............................................................................................................. 373
19.3 Register Descriptions........................................................................................................ 373
19.3.1 A/D Data Register (ADDR)................................................................................. 373
19.3.2 BGR Control Register (BGRMR)........................................................................ 374
19.3.3 A/D Control Register (ADCR) ............................................................................ 375
19.3.4 A/D Start/Status Register (ADSSR) .................................................................... 377
19.4 Operation .......................................................................................................................... 378
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19.4.1 Wait Mode ........................................................................................................... 378
19.4.2 Continuous Mode................................................................................................. 378
19.4.3 Operating States of ∆Σ A/D Converter ................................................................ 379
19.5 Example of Use................................................................................................................. 379
19.5.1 Wait Mode ........................................................................................................... 379
19.5.2 Continuous Mode................................................................................................. 380
19.6 Usage Notes ...................................................................................................................... 384
19.6.1 Reference Voltage................................................................................................384
19.6.2 Analog Voltage Stabilization Pin (ACOM Pin)................................................... 384
19.6.3 After Clearing Module Standby Mode................................................................. 384
19.6.4 Influences on Accuracy........................................................................................ 384
Section 20 LCD Controller/Driver ....................................................................385
20.1 Features............................................................................................................................. 385
20.2 Input/Output Pins .............................................................................................................. 387
20.3 Register Descriptions ........................................................................................................ 388
20.3.1 LCD Port Control Register (LPCR)..................................................................... 388
20.3.2 LCD Control Register (LCR)............................................................................... 390
20.3.3 LCD Control Register 2 (LCR2).......................................................................... 392
20.3.4 LCD Trimming Register (LTRMR)..................................................................... 393
20.3.5 BGR Control Register (BGRMR)........................................................................ 394
20.4 Operation .......................................................................................................................... 395
20.4.1 Settings up to LCD Display ................................................................................. 395
20.4.2 Relationship between LCD RAM and Display.................................................... 397
20.4.3 3-V Constant-Voltage Power Supply Circuit....................................................... 401
20.4.4 Operation in Power-Down Modes ....................................................................... 402
20.4.5 Boosting LCD Drive Power Supply..................................................................... 403
Section 21 I2C Bus Interface 2 (IIC2) ................................................................405
21.1 Features............................................................................................................................. 405
21.2 Input/Output Pins .............................................................................................................. 407
21.3 Register Descriptions ........................................................................................................ 407
21.3.1 I2C Bus Control Register 1 (ICCR1).................................................................... 408
21.3.2 I2C Bus Control Register 2 (ICCR2).................................................................... 410
21.3.3 I2C Bus Mode Register (ICMR)........................................................................... 411
21.3.4 I2C Bus Interrupt Enable Register (ICIER) .......................................................... 413
21.3.5 I2C Bus Status Register (ICSR)............................................................................ 415
21.3.6 Slave Address Register (SAR)............................................................................. 417
21.3.7 I2C Bus Transmit Data Register (ICDRT)............................................................ 418
21.3.8 I2C Bus Receive Data Register (ICDRR)............................................................. 418
21.3.9 I2C Bus Shift Register (ICDRS)...........................................................................418
21.4 Operation .......................................................................................................................... 419
21.4.1 I2C Bus Format..................................................................................................... 419
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21.4.2 Master Transmit Operation.................................................................................. 420
21.4.3 Master Receive Operation ................................................................................... 422
21.4.4 Slave Transmit Operation .................................................................................... 424
21.4.5 Slave Receive Operation...................................................................................... 425
21.4.6 Clocked Synchronous Serial Format ................................................................... 427
21.4.7 Noise Canceler..................................................................................................... 429
21.4.8 Example of Use.................................................................................................... 430
21.5 Interrupt Request...............................................................................................................434
21.6 Bit Synchronous Circuit.................................................................................................... 435
Section 22 Power-On Reset Circuit................................................................... 437
22.1 Feature .............................................................................................................................. 437
22.2 Operation .......................................................................................................................... 438
22.2.1 Power-On Reset Circuit....................................................................................... 438
Section 23 Address Break .................................................................................439
23.1 Register Descriptions........................................................................................................ 439
23.1.1 Address Break Control Register 2 (ABRKCR2) ................................................. 440
23.1.2 Address Break Status Register 2 (ABRKSR2) .................................................... 441
23.1.3 Break Address Registers 2 (BAR2H, BAR2L).................................................... 442
23.1.4 Break Data Registers 2 (BDR2H, BDR2L) ......................................................... 442
23.2 Operation .......................................................................................................................... 442
23.3 Operating States of Address Break ................................................................................... 444
Section 24 List of Registers...............................................................................445
24.1 Register Addresses (Address Order)................................................................................. 446
24.2 Register Bits...................................................................................................................... 451
24.3 Register States in Each Operating Mode .......................................................................... 457
Section 25 Electrical Characteristics .................................................................463
25.1 Absolute Maximum Ratings for F-ZTAT Version ........................................................... 463
25.2 Electrical Characteristics for F-ZTAT Version................................................................. 464
25.2.1 Power Supply Voltage and Operating Range ...................................................... 464
25.2.2 DC Characteristics ............................................................................................... 467
25.2.3 AC Characteristics ............................................................................................... 473
25.2.4 A/D Converter Characteristics............................................................................. 477
25.2.5 ∆Σ A/D Converter Characteristics ....................................................................... 478
25.2.6 LCD Characteristics............................................................................................. 481
25.2.7 Power-On Reset Circuit Characteristics .............................................................. 482
25.2.8 Watchdog Timer Characteristics.......................................................................... 482
25.2.9 Flash Memory Characteristics Preliminary.................................................. 483
25.3 Absolute Maximum Ratings for Masked ROM Version .................................................. 485
25.4 Electrical Characteristics for Masked ROM Version........................................................ 486
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25.4.1 Power Supply Voltage and Operating Range....................................................... 486
25.4.2 DC Characteristics ............................................................................................... 488
25.4.3 AC Characteristics ............................................................................................... 494
25.4.4 A/D Converter Characteristics ............................................................................. 499
25.4.5 ∆Σ A/D Converter Characteristics ....................................................................... 500
25.4.6 LCD Characteristics............................................................................................. 503
25.4.7 Power-On Reset Circuit Characteristics .............................................................. 504
25.4.8 Watchdog Timer Characteristics.......................................................................... 505
25.5 Operation Timing.............................................................................................................. 506
25.6 Output Load Circuit .......................................................................................................... 508
25.7 Resonator Equivalent Circuit............................................................................................509
25.8 Usage Note........................................................................................................................ 509
Appendix .........................................................................................................511
A. Instruction Set................................................................................................................... 511
A.1 Instruction List..................................................................................................... 511
A.2 Operation Code Map............................................................................................ 526
A.3 Number of Execution States ................................................................................ 529
A.4 Combinations of Instructions and Addressing Modes ......................................... 540
B. I/O Ports............................................................................................................................ 541
B.1 I/O Port Block Diagrams ..................................................................................... 541
B.2 Port States in Each Operating State ..................................................................... 556
C. Product Code Lineup ........................................................................................................ 557
D. Package Dimensions ......................................................................................................... 559
E. Chip Form Specifications..................................................................................................562
F. Bonding Pad Form ............................................................................................................ 563
G. Chip Tray Specifications................................................................................................... 564
Index .........................................................................................................567
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Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram of H8/38086R Group .............................................................. 3
Figure 1.2 Pin Assignment of H8/38086R Group (FP-80A, TFP-80C)..........................................4
Figure 1.3 Pin Assignment of H8/38086R Group (TLP-85V)........................................................ 5
Figure 1.4 Pad Assignment of HCD64F38086R (Top View)......................................................... 9
Section 2 CPU
Figure 2.1 Memory Map............................................................................................................... 20
Figure 2.2 CPU Registers ............................................................................................................. 21
Figure 2.3 Usage of General Registers .........................................................................................22
Figure 2.4 Relationship between Stack Pointer and Stack Area...................................................23
Figure 2.5 General Register Data Formats (1).............................................................................. 25
Figure 2.5 General Register Data Formats (2).............................................................................. 26
Figure 2.6 Memory Data Formats................................................................................................. 27
Figure 2.7 Instruction Formats...................................................................................................... 38
Figure 2.8 Branch Address Specification in Memory Indirect Mode...........................................41
Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 44
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)..................................... 45
Figure 2.11 CPU Operating States................................................................................................ 46
Figure 2.12 State Transitions........................................................................................................ 47
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same Address .. 48
Section 3 Exception Handling
Figure 3.1 Reset Exception Handling Sequence........................................................................... 56
Figure 3.2 Interrupt Sources and their Numbers...........................................................................57
Figure 3.3 Stack Status after Exception Handling ........................................................................ 58
Figure 3.4 Operation when Odd Address is Set in SP .................................................................. 59
Figure 3.5 Port Mode Register (or AEGSR) Setting and Interrupt Request Flag
Clearing Procedure ...................................................................................................... 62
Section 4 Interrupt Controller
Figure 4.1 Block Diagram of Interrupt Controller........................................................................ 65
Figure 4.2 Flowchart of Procedure Up to Interrupt Acceptance ................................................... 81
Figure 4.3 Interrupt Exception Handling Sequence......................................................................82
Figure 4.4 Contention between Interrupt Generation and Disabling ............................................ 84
Section 5 Clock Pulse Generators
Figure 5.1 Block Diagram of Clock Pulse Generators (Flash Memory Version) (1).................... 87
Figure 5.1 Block Diagram of Clock Pulse Generators (Masked ROM Version) (2) .................... 87
Figure 5.2 Typical Connection to Crystal Resonator.................................................................... 90
Figure 5.3 Equivalent Circuit of Crystal Resonator...................................................................... 90
Figure 5.4 Typical Connection to Ceramic Resonator.................................................................. 91
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Figure 5.5 Example of External Clock Input................................................................................ 91
Figure 5.6 Typical Connection to 32.768-kHz/38.4-kHz Crystal Resonator................................ 93
Figure 5.7 Equivalent Circuit of 32.768-kHz/38.4-kHz Crystal Resonator.................................. 93
Figure 5.8 Pin Connection when not Using Subclock .................................................................. 94
Figure 5.9 Pin Connection when Inputting External Clock .......................................................... 94
Figure 5.10 Example of Crystal and Ceramic Resonator Arrangement........................................ 96
Figure 5.11 Negative Resistance Measurement and Circuit Modification Suggestions ............... 97
Figure 5.12 Example of Incorrect Board Design .......................................................................... 98
Figure 5.13 Oscillation Stabilization Wait Time .......................................................................... 99
Section 6 Power-Down Modes
Figure 6.1 Mode Transition Diagram ......................................................................................... 110
Figure 6.2 Standby Mode Transition and Pin States................................................................... 120
Figure 6.3 External Input Signal Capture when Signal Changes before/after Standby
Mode or Watch Mode ............................................................................................... 121
Section 7 ROM
Figure 7.1 Flash Memory Block Configuration.......................................................................... 124
Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode.......................... 132
Figure 7.3 Program/Program-Verify Flowchart ......................................................................... 134
Figure 7.4 Erase/Erase-Verify Flowchart ................................................................................... 137
Figure 7.5 Module Standby Mode Setting.................................................................................. 140
Section 9 I/O Ports
Figure 9.1 Port 1 Pin Configuration............................................................................................ 143
Figure 9.2 Port 3 Pin Configuration............................................................................................ 151
Figure 9.3 Port 4 Pin Configuration............................................................................................ 155
Figure 9.4 Port 5 Pin Configuration............................................................................................ 159
Figure 9.5 Port 6 Pin Configuration............................................................................................ 163
Figure 9.6 Port 7 Pin Configuration............................................................................................ 166
Figure 9.7 Port 8 Pin Configuration............................................................................................ 168
Figure 9.8 Port 9 Pin Configuration............................................................................................ 170
Figure 9.9 Port A Pin Configuration...........................................................................................173
Figure 9.10 Port B Pin Configuration......................................................................................... 176
Figure 9.11 Input/Output Data Inversion Function..................................................................... 180
Section 10 Realtime Clock (RTC)
Figure 10.1 Block Diagram of RTC ........................................................................................... 183
Figure 10.2 Definition of Time Expression ................................................................................ 188
Figure 10.3 Initial Setting Procedure.......................................................................................... 192
Figure 10.4 Example: Reading of Inaccurate Time Data............................................................ 193
Section 11 Timer F
Figure 11.1 Block Diagram of Timer F ...................................................................................... 196
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Figure 11.2 TMOFH/TMOFL Output Timing............................................................................ 203
Figure 11.3 Clear Interrupt Request Flag when Interrupt Source Generation Signal is Valid... 207
Section 12 16-Bit Timer Pulse Unit (TPU)
Figure 12.1 Block Diagram of TPU............................................................................................ 211
Figure 12.2 16-Bit Register Access Operation [CPU ↔ TCNT (16 Bits)]................................. 226
Figure 12.3 8-Bit Register Access Operation [CPU ↔ TCR (Upper 8 Bits)] ............................ 226
Figure 12.4 8-Bit Register Access Operation [CPU ↔ TMDR (Lower 8 Bits)] ........................ 227
Figure 12.5 8-Bit Register Access Operation [CPU ↔ TCR and TMDR (16 Bits)]..................227
Figure 12.6 Example of Counter Operation Setting Procedure .................................................. 228
Figure 12.7 Free-Running Counter Operation ............................................................................ 229
Figure 12.8 Periodic Counter Operation..................................................................................... 229
Figure 12.9 Example of Setting Procedure for Waveform Output by Compare Match.............. 230
Figure 12.10 Example of 0 Output/1 Output Operation ............................................................. 230
Figure 12.11 Example of Toggle Output Operation ................................................................... 231
Figure 12.12 Example of Setting Procedure for Input Capture Operation.................................. 231
Figure 12.13 Example of Input Capture Operation..................................................................... 232
Figure 12.14 Example of Synchronous Operation Setting Procedure ........................................ 233
Figure 12.15 Example of Synchronous Operation...................................................................... 234
Figure 12.16 Setting Procedure for Operation with Cascaded Operation................................... 235
Figure 12.17 Example of Operation with Cascaded Connection................................................ 236
Figure 12.18 Example of PWM Mode Setting Procedure .......................................................... 238
Figure 12.19 Example of PWM Mode Operation (1) ................................................................. 238
Figure 12.20 Example of PWM Mode Operation (2) ................................................................. 239
Figure 12.21 Example of PWM Mode Operation (3) ................................................................. 240
Figure 12.22 Count Timing in Internal Clock Operation............................................................ 242
Figure 12.23 Count Timing in External Clock Operation........................................................... 242
Figure 12.24 Output Compare Output Timing ...........................................................................243
Figure 12.25 Input Capture Input Signal Timing........................................................................ 243
Figure 12.26 Counter Clear Timing (Compare Match) .............................................................. 244
Figure 12.27 Counter Clear Timing (Input Capture) .................................................................. 244
Figure 12.28 TGI Interrupt Timing (Compare Match) ............................................................... 245
Figure 12.29 TGI Interrupt Timing (Input Capture) ................................................................... 245
Figure 12.30 TCIV Interrupt Setting Timing.............................................................................. 246
Figure 12.31 Timing for Status Flag Clearing by CPU .............................................................. 246
Figure 12.32 Contention between TCNT Write and Clear Operation ........................................ 248
Figure 12.33 Contention between TCNT Write and Increment Operation................................. 248
Figure 12.34 Contention between TGR Write and Compare Match...........................................249
Figure 12.35 Contention between TGR Read and Input Capture ............................................... 250
Figure 12.36 Contention between TGR Write and Input Capture .............................................. 250
Figure 12.37 Contention between Overflow and Counter Clearing............................................ 251
Figure 12.38 Contention between TCNT Write and Overflow................................................... 251
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Section 13 Asynchronous Event Counter (AEC)
Figure 13.1 Block Diagram of Asynchronous Event Counter .................................................... 254
Figure 13.2 Software Procedure when Using ECH and ECL as 16-Bit Event Counter.............. 262
Figure 13.3 Software Procedure when Using ECH and ECL as 8-Bit Event Counters .............. 263
Figure 13.4 Event Counter Operation Waveform....................................................................... 264
Figure 13.5 Example of Clock Control Operation...................................................................... 265
Section 14 Watchdog Timer
Figure 14.1 Block Diagram of Watchdog Timer ........................................................................ 269
Figure 14.2 Example of Watchdog Timer Operation ................................................................. 274
Figure 14.3 Interval Timer Mode Operation............................................................................... 275
Figure 14.4 Timing of OVF Flag Setting ................................................................................... 275
Section 15 Serial Communication Interface 3 (SCI3, IrDA)
Figure 15.1 (1) Block Diagram of SCI3_1 ................................................................................. 279
Figure 15.1 (2) Block Diagram of SCI3_2 ................................................................................. 280
Figure 15.2 Data Format in Asynchronous Communication ...................................................... 300
Figure 15.3 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits)............. 300
Figure 15.4 Sample SCI3 Initialization Flowchart ..................................................................... 304
Figure 15.5 Example SCI3 Operation in Transmission in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit) ........................................................................... 305
Figure 15.6 Sample Serial Transmission Flowchart (Asynchronous Mode) .............................. 306
Figure 15.7 Example SCI3 Operation in Reception in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)........................................................................... 308
Figure 15.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (1) ..................... 309
Figure 15.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (2) ..................... 310
Figure 15.9 Data Format in Clocked Synchronous Communication .......................................... 311
Figure 15.10 Example of SCI3 Operation in Transmission in Clocked Synchronous Mode...... 312
Figure 15.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode) ................ 313
Figure 15.12 Example of SCI3 Reception Operation in Clocked Synchronous Mode............... 314
Figure 15.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode)...................... 315
Figure 15.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
(Clocked Synchronous Mode)............................................................................... 316
Figure 15.15 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A) .......................................... 317
Figure 15.16 Sample Multiprocessor Serial Transmission Flowchart ........................................ 318
Figure 15.17 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 319
Figure 15.17 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 320
Figure 15.18 Example of SCI3 Operation in Reception Using Multiprocessor Format
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).............................. 321
Figure 15.19 IrDA Block Diagram............................................................................................. 322
Figure 15.20 IrDA Transmission and Reception ........................................................................ 323
Figure 15.21 (a) RDRF Setting and RXI Interrupt ..................................................................... 327
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Figure 15.21 (b) TDRE Setting and TXI Interrupt ..................................................................... 327
Figure 15.21 (c) TEND Setting and TEI Interrupt...................................................................... 327
Figure 15.22 Receive Data Sampling Timing in Asynchronous Mode ...................................... 329
Figure 15.23 Relation between RDR Read Timing and Data.....................................................331
Section 16 Serial Communication Interface 4 (SCI4)
Figure 16.1 Block Diagram of SCI4........................................................................................... 334
Figure 16.2 Data Transfer Format ..............................................................................................342
Figure 16.3 Flowchart Example of SCI4 Initialization............................................................... 343
Figure 16.4 Flowchart Example of Data Transmission .............................................................. 344
Figure 16.5 Transmit Operation Example .................................................................................. 345
Figure 16.6 Flowchart Example of Data Reception.................................................................... 346
Figure 16.7 Receive Operation Example .................................................................................... 347
Figure 16.8 Flowchart Example of Simultaneous Transmission and Reception ........................ 348
Figure 16.9 Relationship between Reading RDR4 and RDRF ................................................... 351
Figure 16.10 Transfer Format when Internal Clock of φ/2 is Selected....................................... 351
Section 17 14-Bit PWM
Figure 17.1 Block Diagram of 14-Bit PWM ..............................................................................353
Figure 17.2 Waveform Output by PWM .................................................................................... 357
Section 18 A/D Converter
Figure 18.1 Block Diagram of A/D Converter ........................................................................... 360
Figure 18.2 External Trigger Input Timing ................................................................................ 364
Figure 18.3 Example of A/D Conversion Operation .................................................................. 366
Figure 18.4 Flowchart of Procedure for Using A/D Converter (Polling by Software) ............... 367
Figure 18.5 Flowchart of Procedure for Using A/D Converter (Interrupts Used) ...................... 367
Figure 18.6 A/D Conversion Accuracy Definitions (1).............................................................. 368
Figure 18.7 A/D Conversion Accuracy Definitions (2).............................................................. 369
Figure 18.8 Example of Analog Input Circuit ............................................................................ 370
Section 19 ∆Σ A/D Converter
Figure 19.1 Block Diagram of ∆Σ A/D Converter...................................................................... 372
Figure 19.2 Example of ∆Σ A/D Conversion Operation (Wait Mode) ....................................... 381
Figure 19.3 Flowchart of Procedure for Using ∆Σ A/D Converter (Polling by Software) ......... 382
Figure 19.4 Flowchart of Procedure for Using ∆Σ A/D Converter (Interrupts Used).................382
Figure 19.5 Example of ∆Σ A/D Conversion Operation (Continuous Mode) ............................ 383
Section 20 LCD Controller/Driver
Figure 20.1 Block Diagram of LCD Controller/Driver .............................................................. 386
Figure 20.2 Handling of LCD Drive Power Supply when Using 1/2 Duty ................................ 395
Figure 20.3 LCD RAM Map (1/4 Duty)..................................................................................... 397
Figure 20.4 LCD RAM Map (1/3 Duty)..................................................................................... 397
Figure 20.5 LCD RAM Map (1/2 Duty)..................................................................................... 398
Figure 20.6 LCD RAM Map (Static Mode)................................................................................ 398
Figure 20.7 Output Waveforms for Each Duty Cycle (A Waveform)........................................ 399
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Figure 20.8 Output Waveforms for Each Duty Cycle (B Waveform) ........................................ 400
Figure 20.9 Capacitance Connection when Using 3-V Constant-Voltage
Power Supply Circuit .............................................................................................. 402
Figure 20.10 Connection of External Split Resistor ................................................................... 403
Section 21 I2C Bus Interface 2 (IIC2)
Figure 21.1 Block Diagram of I2C Bus Interface 2..................................................................... 406
Figure 21.2 External Circuit Connections of I/O Pins................................................................ 407
Figure 21.3 I2C Bus Formats ...................................................................................................... 419
Figure 21.4 I2C Bus Timing........................................................................................................ 419
Figure 21.5 Master Transmit Mode Operation Timing (1)......................................................... 421
Figure 21.6 Master Transmit Mode Operation Timing (2)......................................................... 421
Figure 21.7 Master Receive Mode Operation Timing (1) .......................................................... 423
Figure 21.8 Master Receive Mode Operation Timing (2) .......................................................... 423
Figure 21.9 Slave Transmit Mode Operation Timing (1) ........................................................... 424
Figure 21.10 Slave Transmit Mode Operation Timing (2) ......................................................... 425
Figure 21.11 Slave Receive Mode Operation Timing (1)........................................................... 426
Figure 21.12 Slave Receive Mode Operation Timing (2)........................................................... 426
Figure 21.13 Clocked Synchronous Serial Transfer Format....................................................... 427
Figure 21.14 Transmit Mode Operation Timing......................................................................... 428
Figure 21.15 Receive Mode Operation Timing .......................................................................... 429
Figure 21.16 Block Diagram of Noise Conceler ........................................................................ 429
Figure 21.17 Sample Flowchart for Master Transmit Mode ...................................................... 430
Figure 21.18 Sample Flowchart for Master Receive Mode ........................................................ 431
Figure 21.19 Sample Flowchart for Slave Transmit Mode......................................................... 432
Figure 21.20 Sample Flowchart for Slave Receive Mode .......................................................... 433
Figure 21.21 Timing of Bit Synchronous Circuit ....................................................................... 435
Section 22 Power-On Reset Circuit
Figure 22.1 Power-On Reset Circuit........................................................................................... 437
Figure 22.2 Power-On Reset Circuit Operation Timing............................................................. 438
Section 23 Address Break
Figure 23.1 Block Diagram of Address Break............................................................................ 439
Figure 23.2 Address Break Interrupt Operation Example (1)..................................................... 443
Figure 23.2 Address Break Interrupt Operation Example (2)..................................................... 443
Section 25 Electrical Characteristics
Figure 25.1 Power-On Reset Circuit Reset Timing .................................................................... 504
Figure 25.2 Clock Input Timing ................................................................................................. 506
Figure 25.3 RES Low Width Timing.......................................................................................... 506
Figure 25.4 Input Timing............................................................................................................ 506
Figure 25.5 SCK3 Input Clock Timing ...................................................................................... 507
Figure 25.6 SCI3 Input/Output Timing in Clocked Synchronous Mode .................................... 507
Figure 25.7 Clock Input Timing for TCLKA to TCLKC Pins ................................................... 507
Rev. 1.00, 07/04, page xxix of xxxiv
Figure 25.8 I2C Bus Interface Input/Output Timing ................................................................... 508
Figure 25.9 Output Load Condition............................................................................................ 508
Figure 25.10 Resonator Equivalent Circuit ................................................................................509
Appendix
Figure B.1 (a) Port 1 Block Diagram (P16) (F-ZTAT Version) ................................................. 541
Figure B.1 (b) Port 1 Block Diagram (P16) (Masked ROM Version)........................................ 541
Figure B.1 (c) Port 1 Block Diagram (P15 to P12)..................................................................... 542
Figure B.1 (d) Port 1 Block Diagram (P11, P10)........................................................................ 542
Figure B.2 (a) Port 3 Block Diagram (P37) (F-ZTAT Version) ................................................. 543
Figure B.2 (b) Port 3 Block Diagram (P37) (Masked ROM Version)........................................ 543
Figure B.2 (c) Port 3 Block Diagram (P36) (F-ZTAT Version) ................................................. 544
Figure B.2 (d) Port 3 Block Diagram (P36) (Masked ROM Version)........................................ 544
Figure B.2 (e) Port 3 Block Diagram (P32)................................................................................ 545
Figure B.2 (f) Port 3 Block Diagram (P31) ................................................................................ 545
Figure B.2 (g) Port 3 Block Diagram (P30)................................................................................ 546
Figure B.3 (a) Port 4 Block Diagram (P42)................................................................................ 547
Figure B.3 (b) Port 4 Block Diagram (P41)................................................................................ 548
Figure B.3 (c) Port 4 Block Diagram (P40)................................................................................ 549
Figure B.4 Port 5 Block Diagram ...............................................................................................550
Figure B.5 Port 6 Block Diagram ...............................................................................................550
Figure B.6 Port 7 Block Diagram ...............................................................................................551
Figure B.7 Port 8 Block Diagram ...............................................................................................551
Figure B.8 (a) Port 9 Block Diagram (P93)................................................................................ 552
Figure B.8 (b) Port 9 Block Diagram (P92)................................................................................ 552
Figure B.8 (c) Port 9 Block Diagram (P91, P90)........................................................................ 553
Figure B.9 Port A Block Diagram .............................................................................................. 553
Figure B.10 (a) Port B Block Diagram (PB7, PB6).................................................................... 554
Figure B.10 (b) Port B Block Diagram (PB5) ............................................................................ 554
Figure B.10 (c) Port B Block Diagram (PB2 to PB0)................................................................. 555
Figure D.1 Package Dimensions (FP-80A) ................................................................................ 559
Figure D.2 Package Dimensions (TFP-80C) .............................................................................. 560
Figure D.3 Package Dimensions (TLP-85V).............................................................................. 561
Figure E.1 Cross-Sectional View of Chip (HCD64338086R, HCD64338085R,
HCD64338084R, and HCD64338083R) .................................................................. 562
Figure E.2 Cross-Sectional View of Chip (HCD64F38086R).................................................... 562
Figure F.1 Bonding Pad Form (HCD64F38086R, HCD64338086R, HCD64338085R,
HCD64338084R, and HCD64338083R)................................................................... 563
Figure G.1 Chip Tray Specifications (HCD64338086R, HCD64338085R,
HCD64338084R, and HCD64338083R) .................................................................. 564
Figure G.2 Chip Tray Specifications (HCD64F38086R) ........................................................... 565
Rev. 1.00, 07/04, page xxx of xxxiv
Rev. 1.00, 07/04, page xxxi of xxxiv
Tables
Section 1 Overview
Table 1.1 TLP-85V Pin Correspondence.................................................................................. 6
Table 1.2 Pad Coordinate of HCD64F38086R ....................................................................... 10
Table 1.3 Pin Functions .......................................................................................................... 13
Section 2 CPU
Table 2.1 Operation Notation .................................................................................................28
Table 2.2 Data Transfer Instructions.......................................................................................29
Table 2.3 Arithmetic Operations Instructions (1) ................................................................... 30
Table 2.3 Arithmetic Operations Instructions (2) ................................................................... 31
Table 2.4 Logic Operations Instructions................................................................................. 32
Table 2.5 Shift Instructions..................................................................................................... 32
Table 2.6 Bit Manipulation Instructions (1)............................................................................ 33
Table 2.6 Bit Manipulation Instructions (2)............................................................................ 34
Table 2.7 Branch Instructions.................................................................................................35
Table 2.8 System Control Instructions.................................................................................... 36
Table 2.9 Block Data Transfer Instructions ............................................................................ 37
Table 2.10 Addressing Modes .................................................................................................. 39
Table 2.11 Absolute Address Access Ranges...........................................................................40
Table 2.12 Effective Address Calculation (1)........................................................................... 42
Table 2.12 Effective Address Calculation (2)........................................................................... 43
Section 3 Exception Handling
Table 3.1 Exception Sources and Vector Address..................................................................54
Table 3.2 Interrupt Wait States ............................................................................................... 58
Table 3.3 Conditions under which Interrupt Request Flag is Set to 1..................................... 61
Section 4 Interrupt Controller
Table 4.1 Pin Configuration.................................................................................................... 66
Table 4.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities.................................78
Table 4.3 Interrupt Control States........................................................................................... 80
Table 4.4 Interrupt Response Times (States) .......................................................................... 83
Section 5 Clock Pulse Generators
Table 5.1 Selection Method for System Clock Oscillator and On-Chip Oscillator ................92
Section 6 Power-Down Modes
Table 6.1 Operating Frequency and Waiting Time............................................................... 105
Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling ...... 111
Table 6.3 Internal State in Each Operating Mode................................................................. 112
Section 7 ROM
Table 7.1 Setting Programming Modes ................................................................................ 129
Rev. 1.00, 07/04, page xxxii of xxxiv
Table 7.2 Boot Mode Operation ........................................................................................... 131
Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit
Rate is Possible ..................................................................................................... 132
Table 7.4 Reprogram Data Computation Table.................................................................... 135
Table 7.5 Additional-Program Data Computation Table...................................................... 135
Table 7.6 Programming Time............................................................................................... 135
Table 7.7 Flash Memory Operating States............................................................................ 139
Section 10 Realtime Clock (RTC)
Table 10.1 Pin Configuration.................................................................................................. 184
Table 10.2 Interrupt Sources................................................................................................... 194
Section 11 Timer F
Table 11.1 Pin Configuration.................................................................................................. 197
Table 11.2 Timer F Operating States...................................................................................... 204
Section 12 16-Bit Timer Pulse Unit (TPU)
Table 12.1 TPU Functions...................................................................................................... 210
Table 12.2 Pin Configuration.................................................................................................. 211
Table 12.3 CCLR1 and CCLR0 (Channels 1 and 2)............................................................... 213
Table 12.4 TPSC2 to TPSC0 (Channel 1) .............................................................................. 214
Table 12.5 TPSC2 to TPSC0 (Channel 2) .............................................................................. 214
Table 12.6 MD3 to MD0 ........................................................................................................ 215
Table 12.7 TIOR_1 (Channel 1) ............................................................................................. 217
Table 12.8 TIOR_2 (Channel 2) ............................................................................................. 218
Table 12.9 TIOR_1 (Channel 1) ............................................................................................. 219
Table 12.10 TIOR_2 (Channel 2) ......................................................................................... 220
Table 12.11 Counter Combination in Operation with Cascaded Connection ....................... 235
Table 12.12 PWM Output Registers and Output Pins .......................................................... 237
Table 12.13 TPU Interrupts .................................................................................................. 241
Section 13 Asynchronous Event Counter (AEC)
Table 13.1 Pin Configuration.................................................................................................. 254
Table 13.2 Examples of Event Counter PWM Operation....................................................... 265
Table 13.3 Operating States of Asynchronous Event Counter................................................ 266
Table 13.4 Maximum Clock Frequency ................................................................................. 267
Section 15 Serial Communication Interface 3 (SCI3, IrDA)
Table 15.1 SCI3 Channel Configuration ................................................................................ 278
Table 15.2 Pin Configuration.................................................................................................. 281
Table 15.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...... 292
Table 15.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ...... 292
Table 15.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3) ...... 293
Table 15.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (4) ...... 293
Table 15.4 Relation between n and Clock .............................................................................. 294
Table 15.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 294
Rev. 1.00, 07/04, page xxxiii of xxxiv
Table 15.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (1) ............... 295
Table 15.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (2) ............... 296
Table 15.7 Relation between n and Clock .............................................................................. 297
Table 15.8 Data Transfer Formats (Asynchronous Mode)...................................................... 301
Table 15.9 SMR Settings and Corresponding Data Transfer Formats.................................... 302
Table 15.10 SMR and SCR Settings and Clock Source Selection........................................ 303
Table 15.11 SSR Status Flags and Receive Data Handling .................................................. 308
Table 15.12 IrCKS2 to IrCKS0 Bit Settings......................................................................... 324
Table 15.13 SCI3 Interrupt Requests.................................................................................... 325
Table 15.14 Transmit/Receive Interrupts.............................................................................. 326
Section 16 Serial Communication Interface 4 (SCI4)
Table 16.1 Pin Configuration.................................................................................................. 334
Table 16.2 Prescaler Division Ratio and Transfer Clock Cycle (Internal Clock) ................... 340
Table 16.3 SCI4 Interrupt Sources.......................................................................................... 349
Section 17 14-Bit PWM
Table 17.1 Pin Configuration.................................................................................................. 354
Table 17.2 PWM Operating States ......................................................................................... 357
Section 18 A/D Converter
Table 18.1 Pin Configuration.................................................................................................. 361
Table 18.2 Operating States of A/D Converter....................................................................... 364
Section 19 ∆Σ A/D Converter
Table 19.1 Pin Configuration.................................................................................................. 373
Table 19.2 Operating States of ∆Σ A/D Converter ................................................................. 379
Section 20 LCD Controller/Driver
Table 20.1 Pin Configuration.................................................................................................. 387
Table 20.2 Duty Cycle and Common Function Selection....................................................... 389
Table 20.3 Segment Driver Selection ..................................................................................... 389
Table 20.4 Frame Frequency Selection................................................................................... 391
Table 20.5 Output Levels........................................................................................................ 401
Table 20.6 Power-Down Modes and Display Operation ........................................................ 403
Section 21 I2C Bus Interface 2 (IIC2)
Table 21.1 Pin Configuration.................................................................................................. 407
Table 21.2 Transfer Rate ........................................................................................................ 409
Table 21.3 Interrupt Requests ................................................................................................. 434
Table 21.4 Time for Monitoring SCL..................................................................................... 435
Section 23 Address Break
Table 23.1 Access and Data Bus Used ................................................................................... 441
Table 23.2 Operating States of Address Break ....................................................................... 444
Rev. 1.00, 07/04, page xxxiv of xxxiv
Section 25 Electrical Characteristics
Table 25.1 Absolute Maximum Ratings ................................................................................. 463
Table 25.2 DC Characteristics ................................................................................................ 467
Table 25.3 Control Signal Timing .......................................................................................... 473
Table 25.4 Serial Interface Timing ......................................................................................... 475
Table 25.5 I2C Bus Interface Timing...................................................................................... 476
Table 25.6 A/D Converter Characteristics.............................................................................. 477
Table 25.7 ∆Σ A/D Converter Characteristics ........................................................................ 478
Table 25.8 LCD Characteristics.............................................................................................. 481
Table 25.9 Power-On Reset Circuit Characteristics ............................................................... 482
Table 25.10 Watchdog Timer Characteristics....................................................................... 482
Table 25.11 Flash Memory Characteristics .......................................................................... 483
Table 25.12 Absolute Maximum Ratings ............................................................................. 485
Table 25.13 DC Characteristics ............................................................................................ 488
Table 25.14 Control Signal Timing ...................................................................................... 494
Table 25.15 Serial Interface Timing ..................................................................................... 497
Table 25.16 I2C Bus Interface Timing.................................................................................. 498
Table 25.17 A/D Converter Characteristics.......................................................................... 499
Table 25.18 ∆Σ A/D Converter Characteristics .................................................................... 500
Table 25.19 LCD Characteristics.......................................................................................... 503
Table 25.20 Power-On Reset Circuit Characteristics ........................................................... 504
Table 25.21 Watchdog Timer Characteristics....................................................................... 505
Appendix
Table A.1 Instruction Set....................................................................................................... 513
Table A.2 Operation Code Map (1)....................................................................................... 526
Table A.2 Operation Code Map (2)....................................................................................... 527
Table A.2 Operation Code Map (3)....................................................................................... 528
Table A.3 Number of Cycles in Each Instruction.................................................................. 530
Table A.4 Number of Cycles in Each Instruction.................................................................. 531
Table A.5 Combinations of Instructions and Addressing Modes .......................................... 540
Rev. 1.00, 07/04, page 1 of 570
Section 1 Overview
1.1 Features
• High-speed H8/300H central processing unit with an internal 16-bit architecture
Upward-compatible with H8/300 CPU on an object level
Sixteen 16-bit general registers
62 basic instructions
• Various peripheral functions
RTC (can be used as a free-running counter)
Asynchronous event counter (AEC)
LCD controller/driver
Timer F
16-bit timer pulse unit (TPU)
14-bit PWM
Watchdog timer
SCI (Asynchronous or clocked synchronous serial communication interface)
I2C bus interface (conforms to the I2C bus interface format that is advocated by Philips
Electronics)
10-bit A/D converter
14-bit ∆Σ A/D converter
Rev. 1.00, 07/04, page 2 of 570
• On-chip memory
Product Classification Model ROM RAM
Flash memory version
(F-ZTATTM version)
H8/38086RF HD64F38086R 52 kbytes* 2 kbytes
H8/38086R HD64338086R 48 kbytes 2 kbytes
H8/38085R HD64338085R 40 kbytes 2 kbytes
H8/38084R HD64338084R 32 kbytes 1 kbyte
Masked ROM version
H8/38083R HD64338083R 24 kbytes 1 kbyte
Note: F-ZTATTM is a trademark of Renesas Technology Corp.
* 4-kbyte area of 52-kbyte ROM is used for the E7. When the E7 is not used, 52-kbyte
area is available.
• General I/O ports
I/O pins: 55 I/O pins, including 4 large current ports (IOL = 15 mA, @VOL = 1.0 V)
Input-only pins: 8 input pins
• Supports various power-down states
• Compact package
Package Code Body Size Pin Pitch Remarks
QFP-80 FP-80A 14
× 14 mm 0.65 mm
TQFP-80 TFP-80C 12 × 12 mm 0.5 mm
P-TFLGA-85 TLP-85V 7 × 7 mm 0.65 mm
Rev. 1.00, 07/04, page 3 of 570
1.2 Internal Block Diagram
Subclock generator
H8/300H CPU
System clock generator
P10/AEVH
P11/AEVL
P12/TIOCA1/TCLKA
P13/TIOCB1/TCLKB
P14/TIOCA2/TCLKC
P15/TIOCB2
P16/SCK4
DVcc
Vcc
AVcc
Vss
AVss
RES
TEST/ADTRG
NMI
P90/PWM1
P91/PWM2
P92/IRQ4
P93
PA0/COM1
PA1/COM2
PA2/COM3
PA3/COM4
V1
V2
V3
C1
C2
X1
X2
OSC1
OSC2
P50/WKP0/SEG1
P51/WKP1/SEG2
P52/WKP2/SEG3
P53/WKP3/SEG4
P54/WKP4/SEG5
P55/WKP5/SEG6
P56/WKP6/SEG7
P57/WKP7/SEG8
P70/SEG17
P71/SEG18
P72/SEG19
P73/SEG20
P74/SEG21
P75/SEG22
P76/SEG23
P77/SEG24
PB0/AN0/IRQ
0
PB1/AN1/IRQ
1
PB2/AN2/IRQ
3
ACOM
PB5/Vref/REF
PB6/Ain2
PB7/Ain1
P80/SEG25
P81/SEG26
P82/SEG27
P83/SEG28
P84/SEG29
P85/SEG30
P86/SEG31
P87/SEG32
P60/SEG9
P61/SEG10
P62/SEG11
P63/SEG12
P64/SEG13
P65/SEG14
P66/SEG15
P67/SEG16
P30/SCK32/TMOW
P31/RXD32/SDA
P32/TXD32/SCL
P36/SI4
P37/SO4
P40/SCK31/TMIF
P41/RXD31/IrRXD/TMOFL
P42/TXD31/IrTXD/TMOFH
ROM
Port 1Port 3Port 4Port 5Port 6
Port B Port A Port 9 Port 8 Port 7
LCD power
supply
Timer pulse unit
Watchdog timer
14-bit PWM1
10-bit A/D converter
Asynchronous
event counter
I
2
C bus interface
SCI3_1/IrDA
Address break
: Large current port (15 mA)
RAM
Power-on reset circuit
Realtime clock
14-bit PWM2
Timer F
LCD controller/driver
SCI3_2
SCI4*
1
14-bit
∆Σ A/D converter
IRQAEC
*
2
*
1
*
2
*
1
*
2
*
1
*
2
1. The SCI4 pins, such as SCK4, SI4, and SO4, are supported only by the F-ZTAT version.
2. The SCK4, SI4, SO4, and NMI pins are not available when the E7 or on-chip
emulator debugger is used. These pins are not available as ports.
Notes:
Figure 1.1 Internal Block Diagram of H8/38086R Group
Rev. 1.00, 07/04, page 4 of 570
1.3 Pin Assignment
FP-80A, TFP-80C
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P86/SEG31
P87/SEG32
PB7/Ain1
PB6/Ain2
PB5/Vref/REF
ACOM
DVcc
AVss
AVcc
PB2/AN2/IRQ3
PB1/AN1/IRQ1
PB0/AN0/IRQ0
IRQAEC
P90/PWM1
P91/PWM2
P92/IRQ4
P93
P10/AEVH
P11/AEVL
P12/TIOCA1/TCLKA
P13/TIOCB1/TCLKB
P14/TIOCA2/TCLKC
P15/TIOCB2
P16/SCK4
P30/SCK32/TMOW
P31/RXD32/SDA
P32/TXD32/SCL
P36/SI4
P37/SO4
X1
X2
Vss
OSC2
OSC1
TEST/ADTRG
RES
NMI
P40/SCK31/TMIF
P41/RXD31/IrRXD/TMOFL
P42/TXD31/IrTXD/TMOFH
P61/SEG10
P60/SEG9
P57/WKP7/SEG8
P56/WKP6/SEG7
P55/WKP5/SEG6
P54/WKP4/SEG5
P53/WKP3/SEG4
P52/WKP2/SEG3
P51/WKP1/SEG2
P50/WKP0/SEG1
PA3/COM4
PA2/COM3
PA1/COM2
PA0/COM1
V3
V2
V1 (also used with 3-V booster)
C2
C1
Vcc
P85/SEG30
P84/SEG29
P83/SEG28
P82/SEG27
P81/SEG26
P80/SEG25
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
P67/SEG16
P66/SEG15
P65/SEG14
P64/SEG13
P63/SEG12
P62/SEG11
Figure 1.2 Pin Assignment of H 8/3 80 8 6R Group (FP-80A, TFP-80C )
Rev. 1.00, 07/04, page 5 of 570
TLP-85V
(Top view)
Note: For details on pin correspondence, refer to table 1.1.
A10 B10 C10 D10 E10 F10 G10 H10 J10 K10
A9 B9 C9 D9 E9 F9 G9 H9 J9 K9
A8 B8 C8 D8 E8 F8 G8 H8 J8 K8
A7 B7 C7 H7 J7 K7
A6 B6 C6 H6 J6 K6
A5 B5 C5 H5 J5 K5
A4 B4 C4 D4 H4 J4 K4
A3 B3 C3 D3 E3 F3 G3 H3 J3 K3
A2 B2 C2 D2 E2 F2 G2 H2 J2 K2
A1 B1 C1 D1 E1 F1 G1 H1 J1 K1
Figure 1.3 Pin Assignment of H8/3 80 8 6R Grou p (T L P- 85 V )
Rev. 1.00, 07/04, page 6 of 570
Table 1.1 TLP-85V Pin Corresponde nce
Pin Name
H8/38086R Group Pin Symbol (TLP-85V)
P13/TIOCB1/TCLKB B1
P14/TIOCA2/TCLKC C1
P15/TIOCB2 B2
P16/SCK4 C2
P30/SCK32/TMOW D1
P31/RXD32/SDA D3
P32/TXD32/SCL D2
P36/SI4 E1
P37/SO4 E3
X1 F2
X2 E2
Vss F3
OSC2 G3
OSC1 F1
TEST/ADTRG G2
RES H2
NMI G1
P40/SCK31/TMIF H3
P41/RXD31/IrRXD/TMOFL J1
P42/TXD31/IrTXD/TMOFH H1
NC K1
Vcc K2
C1 K3
C2 J2
V1 J3
V2 K4
V3 H4
PA0/COM1 J4
PA1/COM2 K5
PA2/COM3 H5
PA3/COM4 J6
Rev. 1.00, 07/04, page 7 of 570
Pin Name
H8/38086R Group Pin Symbol (TLP-85V)
P50/WKP0/SEG1 J5
P51/WKP1/SEG2 H6
P52/WKP2/SEG3 H7
P53/WKP3/SEG4 K6
P54/WKP4/SEG5 J7
P55/WKP5/SEG6 J8
P56/WKP6/SEG7 K7
P57/WKP7/SEG8 H8
P60/SEG9 K9
P61/SEG10 K8
NC K10
P62/SEG11 J10
P63/SEG12 H10
P64/SEG13 J9
P65/SEG14 H9
P66/SEG15 G10
P67/SEG16 G8
P70/SEG17 G9
P71/SEG18 F10
P72/SEG19 F8
P73/SEG20 E9
P74/SEG21 F9
P75/SEG22 E8
P76/SEG23 D8
P77/SEG24 E10
P80/SEG25 D9
P81/SEG26 C9
P82/SEG27 D10
P83/SEG28 C8
P84/SEG29 B10
P85/SEG30 C10
Rev. 1.00, 07/04, page 8 of 570
Pin Name
H8/38086R Group Pin Symbol (TLP-85V)
NC A10
P86/SEG31 A9
P87/SEG32 A8
PB7/Ain1 B9
PB6/Ain2 B8
PB5/Vref/REF A7
ACOM C7
DVcc B7
AVss A6
AVcc C6
PB2/AN2/IRQ3 B5
PB1/AN1/IRQ1 B6
PB0/AN0/IRQ0 C5
IRQAEC C4
P90/PWM1 A5
P91/PWM2 B4
P92/IRQ4 B3
P93 A4
P10/AEVH C3
P11/AEVL A2
P12/TIOCA1/TCLKA A3
NC A1
NC D4
Rev. 1.00, 07/04, page 9 of 570
Chip size: 4.73mm × 4.73mm
Product model name Model name on chip Voltage level on the back of the chip: GND
(0, 0) X
Y
Model name
: NC pad
HCD64F38086R HD64F38086R
81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
63 62
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
Figure 1.4 Pad Assignmen t of HC D 64 F3 808 6R (T op V i ew)
Rev. 1.00, 07/04, page 10 of 570
Table 1.2 Pad Coordinate of HCD64F38086R
Coordinate
Pad No.
Pad Name X (µm) Y (µm)
1 P13/TIOCB1/TCLKB –2223 1797
2 P14/TIOCA2/TCLKC –2223 1615
3 P15/TIOCB2 –2223 1434
4 P16/SCK4 -2223 1295
5 P30/SCK32/TMOW –2223 1150
6 P31/RXD32/SDA –2223 941
7 P32/TXD32/SCL –2223 732
8 P36/SI4 –2223 523
9 P37/SO4 –2223 314
10 X1 –2223 105
11 X2 –2223 –105
12 Vss –2223 –314
13 Vss –2223 –418
14 OSC2 –2223 –523
15 OSC1 –2223 –732
16 TEST/ADTRG –2223 –941
17 RES –2223 –1150
18 NMI –2223 –1360
19 P40/SCK31/TMIF –2223 –1569
20 P41/RXD31/IrRXD/TMOFL –2223 –1778
21 P42/TXD31/IrTXD/TMOFH –2223 –1987
22 Vcc –1987 –2223
23 C1 –1775 –2223
24 C2 –1569 –2223
25 V1 –1360 –2223
26 V2 –1150 –2223
27 V3 –941 –2223
28 PA0/COM1 –732 –2223
29 PA1/COM2 –523 –2223
30 PA2/COM3 –314 –2223
31 PA3/COM4 –105 –2223
Rev. 1.00, 07/04, page 11 of 570
Coordinate
Pad No.
Pad Name X (µm) Y (µm)
32 P50/WKP0/SEG1 105 –2223
33 P51/WKP1/SEG2 314 –2223
34 P52/WKP2/SEG3 523 –2223
35 P53/WKP3/SEG4 732 –2223
36 P54/WKP4/SEG5 941 –2223
37 P55/WKP5/SEG6 1150 –2223
38 P56/WKP6/SEG7 1360 –2223
39 P57/WKP7/SEG8 1569 –2223
40 P60/SEG9 1778 –2223
41 P61/SEG10 1987 –2223
42 P62/SEG11 2223 –1987
43 P63/SEG12 2223 –1778
44 P64/SEG13 2223 –1569
45 P65/SEG14 2223 –1360
46 P66/SEG15 2223 –1150
47 P67/SEG16 2223 –941
48 P70/SEG17 2223 –732
49 P71/SEG18 2223 –523
50 P72/SEG19 2223 –314
51 P73/SEG20 2223 –105
52 P74/SEG21 2223 105
53 P75/SEG22 2223 314
54 P76/SEG23 2223 523
55 P77/SEG24 2223 660
56 P80/SEG25 2223 941
57 P81/SEG26 2223 1222
58 P82/SEG27 2223 1360
59 P83/SEG28 2223 1569
60 P84/SEG29 2223 1778
61 P85/SEG30 2223 1987
Rev. 1.00, 07/04, page 12 of 570
Coordinate
Pad No.
Pad Name X (µm) Y (µm)
62 P86/SEG31 1987 2223
63 P87/SEG32 1852 2223
64 PB7/Ain1 1483 2223
65 PB6/Ain2 1341 2223
66 PB5/Vref/REF 1150 2223
67 ACOM 941 2223
68 DVcc 732 2223
69 AVss 523 2223
70 AVcc 314 2223
71 PB2/AN2/IRQ3 105 2223
72 PB1/AN1/IRQ1 –105 2223
73 PB0/AN0/IRQ0 –314 2223
74 IRQAEC –523 2223
75 P90/PWM1 –732 2223
76 P91/PWM2 –941 2223
77 P92/IRQ4 –1150 2223
78 P93 –1360 2223
79 P10/AEVH –1569 2223
80 P11/AEVL –1778 2223
81 P12/TIOCA1/TCLKA –1987 2223
Note: The power supply (Vss) pads in pad numbers 12 and 13 must not be open but connected.
When the TEST pad in pad number 16 is not used as the ADTRG pin, it must be connected
to the Vss voltage level. If not, this LSI does not operate correctly.
When the TEST pad is used as the ADTRG pin, the function should be changed to the
ADTRG pin at Vss voltage level during a reset in advance.
Rev. 1.00, 07/04, page 13 of 570
1.4 Pin Functions
Table 1.3 Pin Functions
Pin No.
Type
Symbol FP-80A,
TFP-80C
TLP-85V Pad
No.*1 Pad
No.*2
I/O
Functions
DVcc 67 B7 68 TBD Input Analog power supply pins for the ∆Σ
A/D converter. When the ∆Σ A/D
converter is not used, connect this pin
to the system power supply.
Vcc 21 K2 22 TBD Input Power supply pins. Connect this pin to
the system power supply.
Vss 12 F3 12, 13 TBD Input Ground pins. Connect this pin to the
system power supply (0 V).
AVcc 69 C6 70 TBD Input Analog power supply pins for the A/D
converter. When the A/D converter is
not used, connect this pin to the
system power supply.
AVss 68
(= Vss)
A6
(= Vss)
69 TBD Input Ground pins for the A/D converter.
Connect this pin to the system power
supply (0 V).
V1 to V3 24 to 26 J3, K4,
H4
25 to 27 TBD Input Power supply pins for the LCD
controller/driver.
C1 22 K3 23 TBD Input Capacitance pins for stepping up the
LCD drive power supply.
Power
supply pins
C2 23 J2 24 TBD Input
Clock pins OSC1 14 F1 15 TBD Input
OSC2 13 G3 14 TBD Output
These pins connect with crystal or
ceramic resonator for the system clock,
or can be used to input an external
clock.
See section 5, Clock Pulse Generators,
for a typical connection.
X1 10 F2 10 TBD Input
X2 11 E2 11 TBD Output
These pins connect with a 32.768- or
38.4-kHz crystal resonator for the
subclock. See section 5, Clock Pulse
Generators, for a typical connection.
System
control
RES 16 H2 17 TBD Input Reset pins. The power-on reset circuit
is incorporated. When externally driven
low, the chip is reset.
Rev. 1.00, 07/04, page 14 of 570
Pin No.
Type
Symbol FP-80A,
TFP-80C
TLP-85V Pad
No.*1 Pad
No.*2
I/O
Functions
System
control
TEST 15 G2 16 TBD Input Test pins. Also used as the ADTRG
pin. When this pin is not used as the
ADTRG pin, users cannot use this
pin. Connect this pin to Vss. When
this pin is used as the ADTRG pin,
see section 18.4.2, External Trigger
Input Timing.
NMI 17 G1 18 TBD Input NMI interrupt request pins.
Non-maskable interrupt request input
pin.
Interrupt
pins
IRQ0 72 C5 73 TBD Input External interrupt request input pins.
Can select the rising or falling edge.
IRQ1 71 B6 72 TBD Input
IRQ3 70 B5 71 TBD Input
IRQ4 76 B3 77 TBD Input
IRQAEC 73 C4 74 TBD Input Interrupt input pins for the
asynchronous event counter.
This pin enables the asynchronous
event input. In the masked ROM
version, this pin controls turning on/off
the on-chip oscillator during a reset.
WKP0 to
WKP7
31 to 38 J5, H6,
H7, K6,
J7, J8,
K7, H8
32 to 39 TBD Input Wakeup interrupt request input pins.
Can select the rising or falling edge.
TIOCA1 80 A3 81 TBD I/O Pins for the TGR1A input capture
input or output compare output, or
PWM output.
TIOCB1 1 B1 1 TBD I/O Pins for the TGR1B input capture
input or output compare output, or
PWM output.
TIOCA2 2 C1 2 TBD I/O Pins for the TGR2A input capture
input or output compare output, or
PWM output.
TIOCB2 3 B2 3 TBD I/O Pins for the TGR2B input capture
input or output compare output, or
PWM output.
TCLKA 80 A3 81 TBD Input External clock input pins.
TCLKB 1 B1 1 TBD Input
16-bit timer
pulse unit
(TPU)
TCLKC 2 C1 2 TBD Input
Rev. 1.00, 07/04, page 15 of 570
Pin No.
Type
Symbol FP-80A,
TFP-80C
TLP-85V Pad
No.*1 Pad
No.*2
I/O
Functions
Timer F TMIF 18 H3 19 TBD Input Event input pins for input to the timer F
counter.
TMOFL 19 J1 20 TBD Output Output pins for waveforms generated
by the timer FL output compare
function.
TMOFH 20 H1 21 TBD Output Output pins for waveforms generated
by the timer FH output compare
function.
AEVL 79 A2 80 TBD Input Event input pins for input to the
asynchronous event counter.
Asynch-
ronous
event
counter
(AEC)
AEVH 78 C3 79 TBD Input
RTC TMOW 5 D1 5 TBD Output Divided clock output pins for the RTC.
14-bit PWM PWM1 74 A5 75 TBD Output
PWM2 75 B4 76 TBD Output
Output pins for waveforms generated
by the 14-bit PWM in PWM channels 1
and 2.
SCK4 4 C2 4 TBD I/O Transfer clock pins for SCI4 data
transmission/reception. When the E7
or on-chip emulator debugger is used,
this pin is not available.
SI4 8 E1 8 TBD Input SCI4 data input pins. When the E7 or
on-chip emulator debugger is used,
this pin is not available.
Serial
commu-
nication
interface 4
(SCI4)
(F-ZTAT
version
only)
SO4 9 E3 9 TBD Output SCI4 data output pins. When the E7 or
on-chip emulator debugger is used,
this pin is not available.
SCK31 18 H3 19 TBD I/O SCI3_1 clock I/O pins.
RXD31/
IrRXD
19 J1 20 TBD Input SCI3_1 data input pins or data input
pins for the IrDA format.
TXD31/
IrTXD
20 H1 21 TBD Output SCI3_1 data output pins or data output
pins for the IrDA format.
SCK32 5 D1 5 TBD I/O SCI3_2 clock I/O pins.
RXD32 6 D3 6 TBD Input SCI3_2 data input pins.
Serial
commu-
nication
interface 3
(SCI3)
TXD32 7 D2 7 TBD Output SCI3_2 data output pins.
Rev. 1.00, 07/04, page 16 of 570
Pin No.
Type
Symbol FP-80A,
TFP-80C
TLP-85V Pad
No.*1 Pad
No.*2
I/O
Functions
A/D
converter
AN0 to
AN2
72 to 70 C5, B6,
B5
73 to 71 TBD Input Analog data input pins for the A/D
converter.
ADTRG 15 G2 16 TBD Input External trigger input pins for the A/D
converter.
ACOM 66 C7 67 TBD Output Pins for stabilizing analog block voltage
of the ∆Σ A/D converter.
A capacitor should be connected
between ∆Σ A/D converter and GND.
REF 65 A7 66 TBD Output Output pins for internal reference
voltage of the ∆Σ A/D converter. These
pins output internal reference voltage.
Vref 65 A7 66 TBD Input External reference voltage pins of the
∆Σ A/D converter. These pins input
reference voltage.
Ain2 64 B8 65 TBD Input Analog input pins for the ∆Σ A/D
converter.
∆Σ A/D
converter
Ain1 63 B9 64 TBD Input Analog input pins for the ∆Σ A/D
converter.
SDA 6 D3 6 TBD I/O IIC data I/O pins. I2C bus
interface 2
(IIC2) SCL 7 D2 7 TBD I/O IIC clock I/O pins.
LCD
controller/
driver
COM1
to
COM4
27 to 30 J4, K5,
H5, J6
28 to 31 TBD Output LCD common output pins.
SEG1 to
SEG8
31 to 38 J5, H6,
H7, K6,
J7, J8,
K7, H8
32 to 39 TBD Output LCD segment output pins.
SEG9 to
SEG16
39 to 46 K9, K8,
J10 H10,
J9, H9,
G8
40 to 47 TBD Output
SEG17
to
SEG24
47 to 54 G9, F10,
F8, E9,
F9, E8,
D8, E10
48 to 55 TBD Output
SEG25
to
SEG32
55 to 62 D9, C9,
D10, C8,
B10,
C10, A9,
A8
56 to 63 TBD Output
Rev. 1.00, 07/04, page 17 of 570
Pin No.
Type
Symbol FP-80A,
TFP-80C
TLP-85V Pad
No.*1 Pad
No.*2
I/O
Functions
I/O ports P10 to
P12
78 to 80 C3, A2,
A3
79 to 81 TBD I/O 7-bit I/O pins. Input or output can be
designated for each bit by means of
the port control register 1 (PCR1).
P13 to
P16
1 to 4 B1, C1,
B2, C2
1 to 4 TBD
P30 to
P32,
P36, P37
5 to 9 D1, D3,
D2, E1,
E3
5 to 9 TBD I/O 5-bit I/O pins. Input or output can be
designated for each bit by means of
the port control register 3 (PCR3).
P40 to
P42
18 to 20 H3, J1,
H1
19 to 21 TBD I/O 3-bit I/O pins. Input or output can be
designated for each bit by means of
the port control register 4 (PCR4).
P50 to
P57
31 to 38 J5, H6,
H7, K6,
J7, J8,
K7, H8
32 to 39 TBD I/O 8-bit I/O pins. Input or output can be
designated for each bit by means of
the port control register 5 (PCR5).
P60 to
P67
39 to 46 K9, K8,
J10, H10,
J9, H9,
G10, G8
40 to 47 TBD I/O 8-bit I/O pins. Input or output can be
designated for each bit by means of
the port control register 6 (PCR6).
P70 to
P77
47 to 54 G9, F10,
F8, E9,
F9, E8,
D8, E10
48 to 55 TBD I/O 8-bit I/O pins. Input or output can be
designated for each bit by means of
the port control register 7 (PCR7).
P80 to
P87
55 to 62 D9, C9,
D10, C8,
B10, C10,
A9, A8
56 to 63 TBD I/O 8-bit I/O pins. Input or output can be
designated for each bit by means of
the port control register 8 (PCR8).
P90 to
P93
74 to 77 A5, B4,
B3, A4
75 to 78 TBD I/O 4-bit I/O pins. Input or output can be
designated for each bit by means of
the port control register 9 (PCR9).
Rev. 1.00, 07/04, page 18 of 570
Pin No.
Type
Symbol FP-80A,
TFP-80C
TLP-85V Pad
No.*1 Pad
No.*2
I/O
Functions
I/O ports PA0 to
PA3
27 to 30 J4, K5,
H5, J6
28 to
31
TBD I/O 4-bit I/O pins. Input or output can be
designated for each bit by means of the
port control register A (PCRA).
6-bit input-only pins
PB0 to
PB2,
PB5 to
PB7
72 to 70,
65 to 63
C5, B6,
B5, A7,
B8, B9
73 to
71, 66
to 64
TBD Input
Notes: 1. Pad no. for the flash memory version.
2. Pad no. for the masked ROM version.
CPU30H2C_000220040500 Rev. 1.00, 07/04, page 19 of 570
Section 2 CPU
This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with
the H8/300 CPU, and supports only normal mode, which has a 64-kbyte address space.
• Upward-compatible with H8/300 CPUs
Can execute H8/300 CPUs object programs
Additional eight 16-bit extended registers
32-bit transfer and arithmetic and logic instructions are added
Signed multiply and divide instructions are added.
• General-register architecture
Sixteen 16-bit general registers also usable as sixteen 8-bit registers and eight 16-bit registers,
or eight 32-bit registers
• Sixty-two basic instructions
8/16/32-bit data transfer and arithmetic and logic instructions
Multiply and divide instructions
Powerful bit-manipulation instructions
• Eight addressing modes
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16,ERn) or @(d:24,ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
Absolute address [@aa:8, @aa:16, @aa:24]
Immediate [#xx:8, #xx:16, or #xx:32]
Program-counter relative [@(d:8,PC) or @(d:16,PC)]
Memory indirect [@@aa:8]
• 64-kbyte address space
• High-speed operation
All frequently-used instructions execute in one or two states
8/16/32-bit register-register add/subtract : 2 state
8 × 8-bit register-register multiply : 14 states
16 ÷ 8-bit register-register divide : 14 states
16 × 16-bit register-register multiply : 22 states
32 ÷ 16-bit register-register divide : 22 states
• Power-down state
Transition to power-down state by SLEEP instruction
Rev. 1.00, 07/04, page 20 of 570
2.1 Address Space and Memory Map
The address space of this LSI is 64 kbytes, which includes the program area and the data area.
Figure 2.1 shows the memory map.
H'0000
H'EFFF
H'F000
H'F09F
H'F0A0
H'F36F
H'F370
H'F37F
H'F380
H'F77F
H'F780
H'FF7F
H'FF80
H'FFFF
Note: Area H'F380 to H'F77F is used by the E7, and is not available to the user.
H'0057
H'0058
HD64F38086R
(Flash memory version)
Internal I/O registers
Not used
User area
Interrupt vector
Not used
Flash memory
On-chip ROM
(52 kbytes)
Internal I/O registers
(128 bytes)
LCD RAM (16 bytes)
On-chip RAM
(3 kbytes)
H'0000
H'BFFF
H'C000
H'BFFF
H'C000
H'CFFF
H'D000
H'F02F
H'F030
H'F09F
H'F0A0
H'F36F
H'F370
H'F37F
H'F380
H'F77F
H'F780
H'FF7F
H'FF80
H'FFFF
H'0057
H'0058
HD64338086R
(Masked ROM version)
Interrupt vector
Not used
Not used
On-chip ROM
(48 kbytes)
Not used
Internal I/O registers
Internal I/O registers
(128 bytes)
LCD RAM (16 bytes)
On-chip RAM
(2 kbytes)
H'0000
H'9FFF
H'A000
H'F02F
H'F030
H'F09F
H'F0A0
H'F36F
H'F370
H'F37F
H'F380
H'F77F
H'F780
H'FF7F
H'FF80
H'FFFF
H'0057
H'0058
HD64338085R
(Masked ROM version)
Interrupt vector
Not used
Not used
On-chip ROM
(40 kbytes)
Not used
Internal I/O registers
Internal I/O registers
(128 bytes)
LCD RAM (16 bytes)
On-chip RAM
(2 kbytes)
H'0000
H'7FFF
H8000
H'F02F
H'F030
H'F09F
H'F0A0
H'F36F
H'F370
H'F37F
H'F380
H'FB7F
H'FB80
H'FF7F
H'FF80
H'FFFF
H'0057
H'0058
HD64338084R
(Masked ROM version)
Interrupt vector
Not used
Not used
On-chip ROM
(32 kbytes)
Not used
Internal I/O registers
Internal I/O registers
(128 bytes)
LCD RAM (16 bytes)
On-chip RAM
(1 kbytes)
H'0000
H'5FFF
H6000
H'F02F
H'F030
H'F09F
H'F0A0
H'F36F
H'F370
H'F37F
H'F380
H'FB7F
H'FB80
H'FF7F
H'FF80
H'FFFF
H'0057
H'0058
HD64338083R
(Masked ROM version)
Interrupt vector
Not used
Not used
On-chip ROM
(24 kbytes)
Not used
Internal I/O registers
Internal I/O registers
(128 bytes)
LCD RAM (16 bytes)
On-chip RAM
(1 kbytes)
Figure 2.1 Memory Map
Rev. 1.00, 07/04, page 21 of 570
2.2 Register Configuration
The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers;
general registers and control registers. The control registers are a 24-bit program counter (PC), and
an 8-bit condition-code register (CCR).
PC
23 0
15 0 7 0 7 0
E0
E1
E2
E3
E4
E5
E6
E7
R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H
R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L
SP:
PC:
CCR:
I:
UI:
Stack pointer
Program counter
Condition-code register
Interrupt mask bit
User bit
Half-carry flag
User bit
Negative flag
Zero flag
Overflow flag
Carry flag
ER0
ER1
ER2
ER3
ER4
ER5
ER6
ER7
IUIHUNZVC
CCR
76543210
H:
U:
N:
Z:
V:
C:
General Registers (ERn)
Control Registers (CR)
[Legend]
(SP)
Figure 2.2 CPU Registers
Rev. 1.00, 07/04, page 22 of 570
2.2.1 General Registers
The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally
identical and can be used as both address registers and data registers. When a general register is
used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates
the usage of the general registers. When the general registers are used as 32-bit registers or address
registers, they are designated by the letters ER (ER0 to ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers divide into 8-bit registers designated by the letters RH (R0H to R7H) and RL (R0L
to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8-bit
registers.
The usage of each register can be selected independently.
• Address registers
• 32-bit registers
• 16-bit registers • 8-bit registers
ER registers
(ER0 to ER7)
E registers (extended registers)
(E0 to E7)
R registers
(R0 to R7)
RH registers
(R0H to R7H)
RL registers
(R0L to R7L)
Figure 2.3 Usage of General Regi ster s
General register ER7 has the function of the stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.4 shows the
relationship between the stack pointer and the stack area.
Rev. 1.00, 07/04, page 23 of 570
SP (ER7)
Empty area
Stack area
Figure 2.4 Relationship between Stack Pointer and Stack Area
2.2.2 Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched, the least significant PC bit is regarded as 0). The PC is initialized when the
start address is loaded by the vector address generated during reset exception-handling sequence.
2.2.3 Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. The I bit is initialized to 1
by reset exception-handling sequence, but other bits are not initialized.
Some instructions leave flag bits unchanged. Operations can be performed on the CCR bits by the
LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching
conditions for conditional branch (Bcc) instructions.
For the action of each instruction on the flag bits, see Appendix A.1, Instruction List.
Rev. 1.00, 07/04, page 24 of 570
Bit Bit Name
Initial
Value R/W Description
7 I 1 R/W Interrupt Mask Bit
Masks interrupts other than NMI when set to 1. NMI is
accepted regardless of the I bit setting. The I bit is set
to 1 at the start of an exception-handling sequence.
6 UI Undefined R/W User Bit
Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions.
5 H Undefined R/W Half-Carry Flag
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B,
or NEG.B instruction is executed, this flag is set to 1 if
there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or
NEG.W instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 11, and cleared to 0
otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L
instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 27, and cleared to 0 otherwise.
4 U Undefined R/W User Bit
Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions.
3 N Undefined R/W Negative Flag
Stores the value of the most significant bit of data as a
sign bit.
2 Z Undefined R/W Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.
1 V Undefined R/W Overflow Flag
Set to 1 when an arithmetic overflow occurs, and
cleared to 0 at other times.
0 C Undefined R/W Carry Flag
Set to 1 when a carry occurs, and cleared to 0
otherwise. Used by:
• Add instructions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift and rotate instructions, to indicate a carry
The carry flag is also used as a bit accumulator by bit
manipulation instructions.
Rev. 1.00, 07/04, page 25 of 570
2.3 Data Formats
The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two
digits of 4-bit BCD data.
2.3.1 General Regis ter Da ta Formats
Figure 2.5 shows the data formats in general registers.
7 0
70
MSB LSB
MSB LSB
704 3
Don't care
Don't care
Don't care
7 04 3
70
Don't care
6543271
0
70
Don't care 65432710
Don't care
RnH
RnL
RnH
RnL
RnH
RnL
Data Type General Register Data Format
Byte data
Byte data
4-bit BCD data
4-bit BCD data
1-bit data
1-bit data
Upper Lower
Upper Lower
Figure 2.5 General Register Data Formats (1)
Rev. 1.00, 07/04, page 26 of 570
15 0
MSB LSB
15 0
MSB LSB
31 16
MSB
15 0
LSB
ERn:
En:
Rn:
RnH:
RnL:
MSB:
LSB:
General register ER
General register E
General register R
General register RH
General register RL
Most significant bit
Least significant bit
Data Type Data FormatGeneral
Register
Word data
Word data
Rn
En
Longword
data
[Legend]
ERn
Figure 2.5 General Register Data Formats (2)
Rev. 1.00, 07/04, page 27 of 570
2.3.2 Memory Data Formats
Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and
longword data in memory, however word or longword data must begin at an even address. If an
attempt is made to access word or longword data at an odd address, an address error does not
occur, however the least significant bit of the address is regarded as 0, so access begins the
preceding address. This also applies to instruction fetches.
When ER7 (SP) is used as an address register to access the stack area, the operand size should be
word or longword.
70
76 543210
MSB LSB
MSB
MSB
LSB
LSB
Data Type Address
1-bit data
Byte data
Word data
Address L
Address L
Address 2M
Address 2M+1
Longword data Address 2N
Address 2N+1
Address 2N+2
Address 2N+3
Data Format
Figure 2.6 Memory Data Formats
Rev. 1.00, 07/04, page 28 of 570
2.4 Instruction Set
2.4.1 Table of Instru ctio ns Cl assified by Function
The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each
functional category. The notation used in tables 2.2 to 2.9 is defined in table 2.1.
Table 2.1 Operation Notation
Symbol Description
Rd General register (destination)*
Rs General register (source)*
Rn General register*
ERn General register (32-bit register or address register)
(EAd) Destination operand
(EAs) Source operand
CCR Condition-code register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (overflow) flag in CCR
C C (carry) flag in CCR
PC Program counter
SP Stack pointer
#IMM Immediate data
disp Displacement
+ Addition
– Subtraction
× Multiplication
÷ Division
∧ Logical AND
∨ Logical OR
⊕ Logical XOR
→ Move
¬ NOT (logical complement)
:3/:8/:16/:24 3-, 8-, 16-, or 24-bit length
Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit registers/address register (ER0 to ER7).
Rev. 1.00, 07/04, page 29 of 570
Table 2.2 Data Transfer Instructions
Instruction Size* Function
MOV B/W/L (EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general register
and memory, or moves immediate data to a general register.
MOVFPE B (EAs) → Rd
Cannot be used in this LSI.
MOVTPE B Rs → (EAs)
Cannot be used in this LSI.
POP W/L @SP+ → Rn
Pops a general register from the stack. POP.W Rn is identical to MOV.W
@SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn.
PUSH W/L Rn → @–SP
Pushes a general register onto the stack. PUSH.W Rn is identical to
MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP.
Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword
Rev. 1.00, 07/04, page 30 of 570
Table 2.3 Arithmetic Operations Instructions (1)
Instruction Size* Function
ADD
SUB
B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd
Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register (immediate byte data
cannot be subtracted from byte data in a general register. Use the SUBX
or ADD instruction.)
ADDX
SUBX
B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry on byte data in two general
registers, or on immediate data and data in a general register.
INC
DEC
B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2. (Byte operands
can be incremented or decremented by 1 only.)
ADDS
SUBS
L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.
DAA
DAS
B Rd (decimal adjust) → Rd
Decimal-adjusts an addition or subtraction result in a general register by
referring to the CCR to produce 4-bit BCD data.
MULXU B/W Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers: either
8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
MULXS B/W Rd × Rs → Rd
Performs signed multiplication on data in two general registers: either 8
bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
DIVXU B/W Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either 16
bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits →
16-bit quotient and 16-bit remainder.
Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword
Rev. 1.00, 07/04, page 31 of 570
Table 2.3 Arithmetic Operations Instructions (2)
Instruction Size* Function
DIVXS B/W Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16 bits ÷
8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder.
CMP B/W/L Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general register
or with immediate data, and sets CCR bits according to the result.
NEG B/W/L 0 – Rd → Rd
Takes the two's complement (arithmetic complement) of data in a
general register.
EXTU W/L Rd (zero extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by padding with zeros on the
left.
EXTS W/L Rd (sign extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by extending the sign bit.
Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword
Rev. 1.00, 07/04, page 32 of 570
Table 2.4 Logic Operations Instructions
Instruction Size* Function
AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT B/W/L ¬ (Rd) → (Rd)
Takes the one's complement (logical complement) of general register
contents.
Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword
Table 2.5 Shift Instructions
Instruction Size* Function
SHAL
SHAR
B/W/L Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
SHLL
SHLR
B/W/L Rd (shift) → Rd
Performs a logical shift on general register contents.
ROTL
ROTR
B/W/L Rd (rotate) → Rd
Rotates general register contents.
ROTXL
ROTXR
B/W/L Rd (rotate) → Rd
Rotates general register contents through the carry flag.
Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword
Rev. 1.00, 07/04, page 33 of 570
Table 2.6 Bit Manipulation Instructions (1)
Instruction Size* Function
BSET B 1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory operand to 1. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BCLR B 0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory operand to 0. The
bit number is specified by 3-bit immediate data or the lower three bits of
a general register.
BNOT B ¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory operand. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BTST B ¬ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory operand and sets or
clears the Z flag accordingly. The bit number is specified by 3-bit
immediate data or the lower three bits of a general register.
BAND
BIAND
B
B
C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
C ∧ ¬ (<bit-No.> of <EAd>) → C
ANDs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BOR
BIOR
B
B
C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
C ∨ ¬ (<bit-No.> of <EAd>) → C
ORs the carry flag with the inverse of a specified bit in a general register
or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
Note: * Refers to the operand size.
B: Byte
Rev. 1.00, 07/04, page 34 of 570
Table 2.6 Bit Manipulation Instructions (2)
Instruction Size* Function
BXOR
BIXOR
B
B
C ⊕ (<bit-No.> of <EAd>) → C
XORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
C ⊕ ¬ (<bit-No.> of <EAd>) → C
XORs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BLD
BILD
B
B
(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to the
carry flag.
¬ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST
BIST
B
B
C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register or
memory operand.
¬ C → (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a general
register or memory operand.
The bit number is specified by 3-bit immediate data.
Note: * Refers to the operand size.
B: Byte
Rev. 1.00, 07/04, page 35 of 570
Table 2.7 Branch Instructions
Instruction Size Function
Bcc* Branches to a specified address if a specified condition is true. The
branching conditions are listed below.
Mnemonic Description Condition
BRA(BT) Always (true) Always
BRN(BF) Never (false) Never
BHI High C ∨ Z = 0
BLS Low or same C ∨ Z = 1
BCC(BHS) Carry clear
(high or same)
C = 0
BCS(BLO) Carry set (low) C = 1
BNE Not equal Z = 0
BEQ Equal Z = 1
BVC Overflow clear V = 0
BVS Overflow set V = 1
BPL Plus N = 0
BMI Minus N = 1
BGE Greater or equal N ⊕ V = 0
BLT Less than N ⊕ V = 1
BGT Greater than Z∨(N ⊕ V) = 0
BLE Less or equal Z∨(N ⊕ V) = 1
JMP Branches unconditionally to a specified address.
BSR Branches to a subroutine at a specified address.
JSR Branches to a subroutine at a specified address.
RTS Returns from a subroutine
Note: * Bcc is the general name for conditional branch instructions.
Rev. 1.00, 07/04, page 36 of 570
Table 2.8 System Control Instructions
Instruction Size* Function
RTE Returns from an exception-handling routine.
SLEEP Causes a transition to a power-down state.
LDC B/W (EAs) → CCR
Moves the source operand contents to the CCR. The CCR size is one
byte, but in transfer from memory, data is read by word access.
STC B/W CCR → (EAd)
Transfers the CCR contents to a destination location. The condition code
register size is one byte, but in transfer to memory, data is written by
word access.
ANDC B CCR ∧ #IMM → CCR
Logically ANDs the CCR with immediate data.
ORC B CCR ∨ #IMM → CCR
Logically ORs the CCR with immediate data.
XORC B CCR ⊕ #IMM → CCR
Logically XORs the CCR with immediate data.
NOP PC + 2 → PC
Only increments the program counter.
Note: * Refers to the operand size.
B: Byte
W: Word
Rev. 1.00, 07/04, page 37 of 570
Table 2.9 Block Data Transfer Instructions
Instruction Size Function
EEPMOV.B if R4L ≠ 0 then
Repeat @ER5+ → @ER6+,
R4L–1 → R4L
Until R4L = 0
else next;
EEPMOV.W if R4 ≠ 0 then
Repeat @ER5+ → @ER6+,
R4–1 → R4
Until R4 = 0
else next;
Transfers a data block. Starting from the address set in ER5, transfers
data for the number of bytes set in R4L or R4 to the address location set
in ER6.
Execution of the next instruction begins as soon as the transfer is
completed.
Rev. 1.00, 07/04, page 38 of 570
2.4.2 Basic Instruction Formats
H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op), a register field (r), an effective address extension (EA), and a condition field
(cc).
Figure 2.7 shows examples of instruction formats.
• Operation Field
Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.
• Register Field
Specifies a general register. Address registers are specified by 3 bits, and data registers by 3
bits or 4 bits. Some instructions have two register fields. Some have no register field.
• Effective Address Extension
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A24-bit
address or displacement is treated as a 32-bit data in which the first 8 bits are 0 (H'00).
• Condition Field
Specifies the branching condition of Bcc instructions.
op
op rn rm
NOP, RTS, etc.
ADD.B Rn, Rm, etc.
MOV.B @(d:16, Rn), Rm
rn rm
op
EA(disp)
op cc EA(disp) BRA d:8
(1) Operation field only
(2) Operation field and register fields
(3) Operation field, register fields, and effective address extension
(4) Operation field, effective address extension, and condition field
Figure 2.7 Instruction Formats
Rev. 1.00, 07/04, page 39 of 570
2.5 Addressing Modes and Effective Address Calculation
The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the
generated 24-bit address, so the effective address is 16 bits.
2.5.1 Addressing Modes
The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses
a subset of these addressing modes. Addressing modes that can be used differ depending on the
instruction. For details, refer to Appendix A.4, Combinations of Instructions and Addressing
Modes.
Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer
instructions can use all addressing modes except program-counter relative and memory indirect.
Bit-manipulation instructions use register direct, register indirect, or the absolute addressing mode
(@aa:8) to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions)
or immediate (3-bit) addressing mode to specify a bit number in the operand.
Table 2.10 Addressing Modes
No. Addressing Mode Symbol
1 Register direct Rn
2 Register indirect @ERn
3 Register indirect with displacement @(d:16,ERn)/@(d:24,ERn)
4 Register indirect with post-increment
Register indirect with pre-decrement
@ERn+
@–ERn
5 Absolute address @aa:8/@aa:16/@aa:24
6 Immediate #xx:8/#xx:16/#xx:32
7 Program-counter relative @(d:8,PC)/@(d:16,PC)
8 Memory indirect @@aa:8
Register DirectRn
The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the
operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7
can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
Register Indirect@ERn
The register field of the instruction code specifies an address register (ERn), the lower 24 bits of
which contain the address of the operand on memory.
Rev. 1.00, 07/04, page 40 of 570
Register Indirect with Displacement@(d:16, ERn) or @(d:24, ERn)
A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn)
specified by the register field of the instruction, and the lower 24 bits of the sum the address of a
memory operand. A 16-bit displacement is sign-extended when added.
Register Indirect with Post-Increment or Pre-Decrement@ERn+ or @-ERn
• Register indirect with post-increment@ERn+
The register field of the instruction code specifies an address register (ERn) the lower 24 bits
of which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is
added to the address register contents (32 bits) and the sum is stored in the address register.
The value added is 1 for byte access, 2 for word access, or 4 for longword access. For the word
or longword access, the register value should be even.
• Register indirect with pre-decrement@-ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field
in the instruction code, and the lower 24 bits of the result is the address of a memory operand.
The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for
word access, or 4 for longword access. For the word or longword access, the register value
should be even.
Absolute Address@aa: 8, @aa : 16, @aa:24
The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24)
For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit
absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the
entire address space.
The access ranges of absolute addresses for this LSI are those shown in table 2.11, because the
upper 8 bits are ignored.
Table 2.11 Absolute Address Access Ranges
Absolute Address Access Range
8 bits (@aa:8) H'FF00 to H'FFFF
16 bits (@aa:16) H'0000 to H'FFFF
24 bits (@aa:24) H'0000 to H'FFFF
Rev. 1.00, 07/04, page 41 of 570
Immediate#xx:8, #xx:16, or #xx:32
The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an
operand.
The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit
number.
Program-Counter Relative@(d:8, PC) or @( d:16, PC)
This mode is used in the BSR instruction. An 8-bit or 16-bit displacement contained in the
instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. The
PC value to which the displacement is added is the address of the first byte of the next instruction,
so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768
bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an
even number.
Memory Indirect@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand. This memory operand contains a branch address.
The memory operand is accessed by longword access. The first byte of the memory operand is
ignored, generating a 24-bit branch address. Figure 2.8 shows how to specify branch address for in
memory indirect mode. The upper bits of the absolute address are all assumed to be 0, so the
address range is 0 to 255 (H'0000 to H'00FF).
Note that the first part of the address range is also the exception vector area.
Specified
by @aa:8
Branch address
Dummy
Figure 2.8 Branch Address Specification in Memory Indirect Mode
Rev. 1.00, 07/04, page 42 of 570
2.5.2 Effective Address Calculation
Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI
the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address.
Table 2.12 Effective Address Calculation (1)
No
1
r
op
31 0
23
2
3Register indirect with displacement
@(d:16,ERn) or @(d:24,ERn)
4
r
opdisp
r
op
rm
op rn
310
0
r
op
230
31 0
disp
31 0
31 0
23 0
23 0
Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)
Register direct(Rn)
General register contents
General register contents
General register contents
General register contents
Sign extension
Register indirect(@ERn)
Register indirect with post-increment or
pre-decrement
•Register indirect with post-increment @ERn+
•Register indirect with pre-decrement @-ERn
1, 2, or 4
1, 2, or 4
Operand is general register contents.
The value to be added or subtracted is 1 when the
operand is byte size, 2 for word size, and 4 for
longword size.
Rev. 1.00, 07/04, page 43 of 570
Table 2.12 Effective Address Calculation (2)
No
5
op
23 0
abs
@aa:8 7
H'FFFF
op
23 0
@aa:16
@aa:24
abs
15
16
23 0
op
abs
6
op IMM
#xx:8/#xx:16/#xx:32
8
Addressing Mode and Instruction Format
Absolute address
Immediate
Effective Address Calculation Effective Address (EA)
Sign extension
Operand is immediate data.
7
Program-counter relative
@(d:8,PC)^@(d:16,PC)
Memory indirect @@aa:8
23 0
disp
0
23 0
disp
op
23
op
8
abs 23 0
abs
H'0000
7
8
0
15 23 0
15
H'00
16
[Legend]
r, rm,rn :
op :
disp :
IMM :
abs :
Register field
Operation field
Displacement
Immediate data
Absolute address
PC contents
Sign
extension
Memory contents
Rev. 1.00, 07/04, page 44 of 570
2.6 Basic Bus Cycle
CPU operation is synchronized by a system clock (φ) or a subclock (φSUB). The period from a rising
edge of φ or φSUB to the next rising edge is called one state. A bus cycle consists of two states or
three states. The cycle differs depending on whether access is to on-chip memory or to on-chip
peripheral modules.
2.6.1 Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access
in byte or word size. Figure 2.9 shows the on-chip memory access cycle.
T1 state
Bus cycle
T2 state
Internal address bus
Internal read signal
Internal data bus
(read access)
Internal write signal
Read data
Address
Write data
Internal data bus
(write access)
SUB
φor φ
Figure 2.9 On-Chip Memory Access Cycle
Rev. 1.00, 07/04, page 45 of 570
2.6.2 On-Chip Peripheral Modules
On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits
or 16 bits depending on the register. For description on the data bus width and number of
accessing states of each register, refer to section 24.1, Register Addresses (Address Order).
Registers with 16-bit data bus width can be accessed by word size only. Registers with 8-bit data
bus width can be accessed by byte or word size. When a register with 8-bit data bus width is
accessed by word size, a bus cycle occurs twice. In two-state access, the operation timing is the
same as that for on-chip memory.
Figure 2.10 shows the operation timing in the case of three-state access to an on-chip peripheral
module.
T
1
state
Bus cycle
Internal
address bus
Internal
read signal
Internal
data bus
(read access)
Internal
write signal
Read data
Address
Internal
data bus
(write access)
T
2
state T
3
state
Write data
SUB
φ or φ
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)
Rev. 1.00, 07/04, page 46 of 570
2.7 CPU States
There are four CPU states: the reset state, program execution state, program halt state, and
exception-handling state. The program execution state includes active (high-speed or medium-
speed) mode and subactive mode. For the program halt state, there are sleep (high-speed or
medium-speed) mode, standby mode, watch mode, and subsleep mode. These states are shown in
figure 2.11. Figure 2.12 shows the state transitions. For details on program execution state and
program halt state, refer to section 6, Power-Down Modes. For details on exception handling, refer
to section 3, Exception Handling.
CPU state Reset state
Program execution state Active (high-speed) mode
Active (medium-speed) mode
Power-down modes
Subactive mode
Sleep (high-speed) mode
Sleep (medium-speed) mode
Standby mode
Watch mode
Subsleep mode
Program halt state
A state in which the CPU
operation is stopped to
reduce power consumption
A transient state in which the CPU changes
the processing flow due to a reset or an interrupt
Exception-handling state
The CPU is initialized
The CPU executes successive program
instructions at high speed,
synchronized by the system clock
The CPU executes successive
program instructions at
reduced speed, synchronized
by the system clock
The CPU executes successive
program instructions at reduced
speed, synchronized by the subclock
Figure 2.11 CPU Operating States
Rev. 1.00, 07/04, page 47 of 570
Reset state
Program halt state
Exception-handling state
Program execution state
Reset cleared
SLEEP instruction executed
Reset
occurs
Interrupt
source
Reset
occurs
Interrupt
source
Exception-
handling
complete
Reset occurs
Figure 2.12 State Transitions
2.8 Usage Notes
2.8.1 Notes on Data Access to Empty Areas
The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip
I/O registers areas available to the user. When data is transferred from CPU to empty areas, the
transferred data will be lost. This action may also cause the CPU to malfunction. When data is
transferred from an empty area to CPU, the contents of the data cannot be guaranteed.
2.8.2 EEPMOV Instruction
EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4L,
which starts from the address indicated by R5, to the address indicated by R6. Set R4L and R6 so
that the end address of the destination address (value of R6 + R4L) does not exceed H'FFFF (the
value of R6 must not change from H'FFFF to H'0000 during execution).
Rev. 1.00, 07/04, page 48 of 570
2.8.3 Bit-Manipulation Instruction
The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in
byte units, manipulate the data of the target bit, and write data to the same address again in byte
units. Special care is required when using these instructions in cases where two registers are
assigned to the same address, or when a bit is directly manipulated for a port or a register
containing a write-only bit, because this may rewrite data of a bit other than the bit to be
manipulated.
Bit manipulation for two registers assigned to the same address
Example 1: Bit manipulation for the timer load register and timer counter
Figure 2.13 shows an example of a timer in which two timer registers are assigned to the same
address. When a bit-manipulation instruction accesses the timer load register and timer counter of
a reloadable timer, since these two registers share the same address, the following operations takes
place.
1. Data is read in byte units.
2. The CPU sets or resets the bit to be manipulated with the bit-manipulation instruction.
3. The written data is written again in byte units to the timer load register.
The timer is counting, so the value read is not necessarily the same as the value in the timer load
register. As a result, bits other than the intended bit in the timer counter may be modified and the
modified value may be written to the timer load register.
Read
Write
Count clock Timer counter
Timer load register
Reload
Internal data bus
Figure 2.13 Example of Timer Con fi gur ation with Two Registers Al l oca ted to Sa me
Address
Rev. 1.00, 07/04, page 49 of 570
Example 2: When the BSET instruction is executed for port 5
P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at
P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level
signal at P50 with a BSET instruction is shown below.
• Prior to executing BSET instruction
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR5 0 0 1 1 1 1 1 1
PDR5 1 0 0 0 0 0 0 0
• BSET instruction executed instruction
BSET #0, @PDR5 The BSET instruction is executed for port 5.
• After executing BSET instruction
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR5 0 0 1 1 1 1 1 1
PDR5 0 1 0 0 0 0 0 1
• Description on operation
1. When the BSET instruction is executed, first the CPU reads port 5.
Since P57 and P56 are input pins, the CPU reads the pin states (low-level and high-level
input).
P55 to P50 are output pins, so the CPU reads the value in PDR5. In this example PDR5 has a
value of H'80, but the value read by the CPU is H'40.
2. Next, the CPU sets bit 0 of the read data to 1, changing the PDR5 data to H'41.
3. Finally, the CPU writes H'41 to PDR5, completing execution of BSET instruction.
As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level
signal. However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem,
store a copy of the PDR5 data in a work area in memory. Perform the bit manipulation on the
data in the work area, then write this data to PDR5.
Rev. 1.00, 07/04, page 50 of 570
• Prior to executing BSET instruction
MOV.B #80, R0L
MOV.B R0L, @RAM0
MOV.B R0L, @PDR5
The PDR5 value (H'80) is written to a work area in
memory (RAM0) as well as to PDR5.
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR5 0 0 1 1 1 1 1 1
PDR5 1 0 0 0 0 0 0 0
RAM0 1 0 0 0 0 0 0 0
• BSET instruction executed
BSET #0, @RAM0 The BSET instruction is executed designating the PDR5
work area (RAM0).
• After executing BSET instruction
MOV.B @RAM0, R0L
MOV.B R0L, @PDR5
The work area (RAM0) value is written to PDR5.
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR5 0 0 1 1 1 1 1 1
PDR5 1 0 0 0 0 0 0 1
RAM0 1 0 0 0 0 0 0 1
Rev. 1.00, 07/04, page 51 of 570
Bit Manipulation in a Register Containing a Write-Only Bit
Example 3: BCLR instruction executed designating port 5 control register PCR5
P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at
P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as
an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be
input to this input pin.
• Prior to executing BCLR instruction
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR5 0 0 1 1 1 1 1 1
PDR5 1 0 0 0 0 0 0 0
• BCLR instruction executed
BCLR #0, @PCR5 The BCLR instruction is executed for PCR5.
• After executing BCLR instruction
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Output Output Output Output Output Output Output Input
Pin state Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR5 1 1 1 1 1 1 1 0
PDR5 1 0 0 0 0 0 0 0
• Description on operation
1. When the BCLR instruction is executed, first the CPU reads PCR5. Since PCR5 is a write-only
register, the CPU reads a value of H'FF, even though the PCR5 value is actually H'3F.
2. Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE.
3. Finally, H'FE is written to PCR5 and BCLR instruction execution ends.
As a result of this operation, bit 0 in PCR5 becomes 0, making P50 an input port. However,
bits 7 and 6 in PCR5 change to 1, so that P57 and P56 change from input pins to output pins.
To prevent this problem, store a copy of the PDR5 data in a work area in memory and
manipulate data of the bit in the work area, then write this data to PDR5.
Rev. 1.00, 07/04, page 52 of 570
• Prior to executing BCLR instruction
MOV.B #3F, R0L
MOV.B R0L, @RAM0
MOV.B R0L, @PCR5
The PCR5 value (H'3F) is written to a work area in
memory (RAM0) as well as to PCR5.
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR5 0 0 1 1 1 1 1 1
PDR5 1 0 0 0 0 0 0 0
RAM0 0 0 1 1 1 1 1 1
• BCLR instruction executed
BCLR #0, @RAM0 The BCLR instructions executed for the PCR5 work area
(RAM0).
• After executing BCLR instruction
MOV.B @RAM0, R0L
MOV.B R0L, @PCR5
The work area (RAM0) value is written to PCR5.
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR5 0 0 1 1 1 1 1 0
PDR5 1 0 0 0 0 0 0 0
RAM0 0 0 1 1 1 1 1 0
Rev. 1.00, 07/04, page 53 of 570
Section 3 Exception Handling
Exception handling may be caused by a reset or interrupts.
• Reset
A reset has the highest exception priority. Exception handling starts as soon as the reset is
cleared by the RES pin. The chip is also reset when the watchdog timer overflows, and
exception handling starts. Exception handling is the same as exception handling by the RES
pin.
• Interrupts
External interrupts other than NMI and internal interrupts other than address break are masked
by the I bit in CCR, and kept masked while the I bit is set to 1. Exception handling starts when
the current instruction or exception handling ends, if an interrupt request has been issued.
Rev. 1.00, 07/04, page 54 of 570
3.1 Exception Sources and Vector Address
Table 3.1 shows the vector addresses and priority of each exception handling. When more than
one interrupt is requested, handling is performed from the interrupt with the highest priority.
Table 3.1 Exception Sources and Vector Address
Source Origin
Exception Sources Vector
Number
Vector Address
Priority
Reset RES, Watchdog Timer 0 H'0000 to H'0001 High
Reserved for system
use
Break instructions 1 H'0002 to H'0003
Reserved for system
use
Break interrupts
(mode transition)
2 H'0004 to H'0005
External interrupt NMI 3 H'0006 to H'0007
Reserved for system
use
Break conditions satisfied 4 H'0008 to H'0009
Address break (user) Break conditions satisfied 5 H'000A to H'000B
External interrupts IRQ0 6 H'000C to H'000D
IRQ1 7 H'000E to H'000F
IRQAEC 8 H'0010 to H'0011
IRQ3 9 H'0012 to H'0013
IRQ4 10 H'0014 to H'0015
WKP0 11 H'0016 to H'0017
WKP1 12 H'0018 to H'0019
WKP2 13 H'001A to H'001B
WKP3 14 H'001C to H'001D
WKP4 15 H'001E to H'001F
WKP5 16 H'0020 to H'0021
WKP6 17 H'0022 to H'0023
WKP7 18 H'0024 to H'0025
Internal interrupts* 19 to 43 H'0026 to H'0056 Low
Note: * For details on the vector table of internal interrupts, refer to section 4.5, Interrupt
Exception Handling Vector Table.
Rev. 1.00, 07/04, page 55 of 570
3.2 Reset
A reset has the highest exception priority.
When the RES pin goes low, all processing halts and this LSI enters the reset. A reset initializes
the internal state of the CPU and the registers of on-chip peripheral modules.
When the RES pin goes high from the low state, this LSI starts reset exception handling.
The chip can also be reset by overflow of the watchdog timer. For details, see section 14,
Watchdog Timer.
3.2.1 Reset Exception Handling
When the RES pin goes low, this LSI enters the reset.
To ensure that this LSI is reset, hold the RES pin low for the oscillation stabilization time of the
clock pulse generator. To reset the chip during operation, hold the RES pin low for at least 20
states.
When the RES pin goes high after being held low for the specified cycle, this LSI starts reset
exception handling as follows. For details on the reset sequence of the power-on reset circuit, see
section 22, Power-On Reset Circuit.
1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized
and the I bit in CCR is set to 1.
2. The reset exception handling vector address (H'0000 and H'0001) is read and transferred to the
PC, and then program execution starts from the address indicated by the PC.
The reset exception handling sequence is shown in figure 3.1.
Rev. 1.00, 07/04, page 56 of 570
Vector fetch
φ
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus (16 bits)
RES
Internal
processing
Initial program
instruction prefetch
(1) Reset exception handling vector address (H'0000)
(2) Program start address
(3) Initial program instruction
(2) (3)
(2)(1)
Reset cleared
Figure 3.1 Reset Exception Handling Sequence
3.2.2 Interrupt Immediately after Rese t
Immediately after a reset, if an interrupt is accepted before the stack pointer (SP) is initialized, PC
and CCR will not be pushed onto the stack correctly, resulting in program runaway. To prevent
this, immediately after reset exception handling all interrupts are masked. For this reason, the
initial program instruction is always executed immediately after a reset. This instruction should
initialize the stack pointer (e.g. MOV.L #xx: 32, SP).
Rev. 1.00, 07/04, page 57 of 570
3.3 Interrupts
The interrupt sources include 14 external interrupts (NMI, IRQ0, IRQ1, IRQ3, IRQ4, IRQAEC,
and WKP7 to WKP0) and 26 internal interrupts (for the flash memory version) or 25 internal
interrupts (for the masked ROM version) from on-chip peripheral modules. Figure 3.2 shows the
interrupt sources and their numbers.
The on-chip peripheral modules which require interrupt sources are the watchdog timer (WDT),
address break, realtime clock (RTC), 16-bit timer pulse unit (TPU), asynchronous event counter
(AEC), timer F, serial communication interface (SCI), ∆Σ A/D converter, and A/D converter.
Interrupt vector addresses are allocated to individual sources.
NMI is an interrupt with the highest priority and accepted at all times. Interrupts are controlled by
the interrupt controller. The interrupt controller sets interrupts other than NMI to three levels of
priorities in order to control multiple interrupts. The interrupt priority registers A to E (IPRA to
IPRE) of the interrupt controller set the interrupt priorities.
For details on interrupts, see section 4, Interrupt Controller.
Interrupts
Notes: ( ) indicates the source number.
1. When the WDT is used as an interval timer, an interrupt request
is generated each time the counter overflows.
2. Available only for the F-ZTAT version.
External interrupts
NMI (1)
IRQ0, IRQ1, IRQ3, IRQ4, and IRQAEC (5)
WKP0 to WKP7 (8)
WDT*
1
(1)
Address break (1)
Realtime clock (8)
Asynchronous event counter (1)
16-bit timer pulse unit (6)
Timer F (2)
SCI3 (2)
SCI4*
2
(1)
∆Σ A/D converter (1)
A/D converter (1)
SLEEP instruction execution (1)
IIC bus (1)
Internal interrupts
Figure 3.2 Interrupt Sources and their Numbers
Rev. 1.00, 07/04, page 58 of 570
3.4 Stack Status after Exception Handling
Figures 3.3 shows the stack after completion of interrupt exception handling.
PC and CCR
saved to stack
SP (R7)
SP – 1
SP – 2
SP – 3
SP – 4
Stack area
SP + 4
SP + 3
SP + 2
SP + 1
SP (R7)
Even address
Prior to start of interrupt
exception handling
After completion of interrupt
exception handling
[Legend]
PC
H
:
PC
L
:
CCR:
SP:
Upper 8 bits of program counter (PC)
Lower 8 bits of program counter (PC)
Condition code register
Stack pointer
Notes:
CCR
CCR*
PCH
PCL
1.
2.
PC shows the address of the first instruction to be executed upon return from the interrupt
handling routine.
Register contents must always be saved and restored by word length, starting from
an even-numbered address.
*Ignored when returning from the interrupt handling routine.
Figure 3.3 Stack Status aft er Excep ti on Han dl i ng
3.4.1 Interrupt Response Time
Table 3.2 shows the number of wait states after an interrupt request flag is set until the first
instruction of the interrupt handling-routine is executed.
Table 3.2 Interrupt Wait States
Item States Total
Waiting time for completion of executing instruction* 1 to 13 15 to 27
Saving of PC and CCR to stack 4
Vector fetch 2
Instruction fetch 4
Internal processing 4
Note: * Excluding EEPMOV instruction.
Rev. 1.00, 07/04, page 59 of 570
3.5 Usage Notes
3.5.1 Notes on Stack Area Use
When word data is accessed in this LSI, the least significant bit of the address is regarded as 0.
Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never
indicate an odd address. Use PUSH Rn (MOV.W Rn, @–SP) or POP Rn (MOV.W @SP+, Rn) to
save or restore register values.
Setting an odd address in SP may cause a program to crash. An example is shown in figure 3.4.
PC
PC
R1L
PC
SP
SP
SP
H'FEFC
H'FEFD
H'FEFF
→
→
→
H
LL
MOV. B R1L, @-R7
SP set to H'FEFF Stack accessed beyond SP
BSR instruction
Contents of PC are lost
H
[Legend]
PC
H
:
PC
L
:
R1L:
SP:
Upper byte of program counter
Lower byte of program counter
General register R1L
Stack pointer
Figure 3.4 Operation when Odd Address is Set in SP
When CCR contents are saved to the stack during interrupt exception handling or restored when
an RTE instruction is executed, this also takes place in word size. Both the upper and lower bytes
of word data are saved to the stack; on return, the even address contents are restored to CCR while
the odd address contents are ignored.
Rev. 1.00, 07/04, page 60 of 570
3.5.2 Notes on Rewr i ti ng Port Mode Registers
When a port mode register is rewritten to switch the functions of external interrupt pins and when
the value of the ECPWME bit in AEGSR is rewritten to switch between selection and non-
selection of IRQAEC, the following points should be observed.
When a pin function is switched by rewriting a port mode register that controls an external
interrupt pin (IRQ4, IRQ3, IRQ1, IRQ0, or WKP7 to WKP0), the interrupt request flag is set to 1
at the time the pin function is switched, even if no valid interrupt is input at the pin. Be sure to
clear the interrupt request flag to 0 after switching the pin function. When the value of the
ECPWME bit in AEGSR that sets selection or non-selection of IRQAEC is rewritten, the interrupt
request flag may be set to 1, even if a valid edge has not arrived on the selected IRQAEC or
IECPWM (PWM output for the asynchronous event counter). Therefore, be sure to clear the
interrupt request flag to 0 after switching the pin function.
Table 3.3 shows the conditions under which interrupt request flags are set to 1 in this way.
Rev. 1.00, 07/04, page 61 of 570
Table 3.3 Conditions under which Interrupt Request Flag is Set to 1
Interrupt Request
Flags Set to 1
Conditions
IRR1 IRRI4 When the IRQ4 bit in PMR9 is changed from 0 to 1 while the IRQ4 pin is
low and the IEG4 bit in IEGR is 0.
When the IRQ4 bit in PMR9 is changed from 1 to 0 while the IRQ4 pin is
low and the IEG4 bit in IEGR is 1.
IRRI3 When the IRQ3 bit in PMRB is changed from 0 to 1 while the IRQ3 pin is
low and the IEG3 bit in IEGR is 0.
When the IRQ3 bit in PMRB is changed from 1 to 0 while the IRQ3 pin is
low and the IEG3 bit in IEGR is 1.
IRREC2
When an edge as designated by the AIEGS1 and AIEGS0 bits in AEGSR
is detected because the values of the IRQAEC pin and of IECPWM at
switching are different (e.g., when the rising edge has been selected and
the ECPWME bit in AEGSR is changed from 1 to 0 while the IRQAEC pin
is low and IECPWM is 1).
IRRI1 When the IRQ1 bit in PMRB is changed from 0 to 1 while the IRQ1 pin is
low and the IEG1 bit in IEGR is 0.
When the IRQ1 bit in PMRB is changed from 1 to 0 while the IRQ1 pin is
low and the IEG1 bit in IEGR is 1.
IRRI0 When the IRQ0 bit in PMRB is changed from 0 to 1 while the IRQ0 pin is
low and the IEG0 bit in IEGR is 0.
When the IRQ0 bit in PMRB is changed from 1 to 0 while the IRQ0 pin is
low and the IEG0 bit in IEGR is 1.
IWPR IWPF7 When the WKP7 bit in PMR5 is changed from 0 to 1 while the WKP7 pin is
low.
IWPF6 When the WKP6 bit in PMR5 is changed from 0 to 1 while the WKP6 pin is
low.
IWPF5 When the WKP5 bit in PMR5 is changed from 0 to 1 while the WKP5 pin is
low.
IWPF4 When the WKP4 bit in PMR5 is changed from 0 to 1 while the WKP4 pin is
low.
IWPF3 When the WKP3 bit in PMR5 is changed from 0 to 1 while the WKP3 pin is
low.
IWPF2 When the WKP2 bit in PMR5 is changed from 0 to 1 while the WKP2 pin is
low.
IWPF1 When the WKP1 bit in PMR5 is changed from 0 to 1 while the WKP1 pin is
low.
IWPF0 When the WKP0 bit in PMR5 is changed from 0 to 1 while the WKP0 pin is
low.
Rev. 1.00, 07/04, page 62 of 570
Figure 3.5 shows the procedure for setting a bit in a port mode register and clearing the interrupt
request flag. This procedure also applies to AEGSR setting.
When switching a pin function, mask the interrupt before setting the bit in the port mode register
(or AEGSR). After accessing the port mode register (or AEGSR), execute at least one instruction
(e.g., NOP), then clear the interrupt request flag from 1 to 0. If the instruction to clear the flag to 0
is executed immediately after the port mode register (or AEGSR) access without executing an
instruction, the flag will not be cleared.
An alternative method is to avoid the setting of interrupt request flags when pin functions are
switched by keeping the pins at the high level so that the conditions in table 3.3 are not satisfied.
However, the procedure in figure 3.5 is recommended because IECPWM is an internal signal and
determining its value is complicated.
I bit in CCR 1
Set port mode register (or AEGSR) bit
Execute NOP instruction
Interrupts masked. (Another possibility
is to disable the relevant interrupt in the
interrupt enable register 1.)
After setting the port mode register
(or AEGSR) bit, first execute at least
one instruction (e.g., NOP), then clear
the interrupt request flag to 0
Interrupt mask cleared
Clear interrupt request flag to 0
←
I bit in CCR 0
←
Figure 3.5 Port Mode Register (or AEGSR) Setting and Interrupt Request Flag
Clearing Procedure
Rev. 1.00, 07/04, page 63 of 570
3.5.3 Method for Clearing Interrupt Request Flags
Use the recommended method given below when clearing the flags in interrupt request registers
(IRR1, IRR2, and IWPR).
• Recommended method
Use a single instruction to clear flags. The bit manipulation instruction and byte-size data
transfer instruction can be used. Two examples of program code for clearing IRRI1 (bit 1 in
IRR1) are given below.
BCLR #1, @IRR1:8
MOV.B R1L, @IRR1:8 (set the value of R1L to B'11111101)
• Example of a malfunction
When flags are cleared with multiple instructions, other flags might be cleared during
execution of the instructions, even though they are currently set, and this will cause a
malfunction.
Here is an example in which IRRI0 is cleared and disabled in the process of clearing IRRI1
(bit 1 in IRR1).
MOV.B @IRR1:8,R1L ......... IRRI0 = 0 at this time
AND.B #B'11111101,R1L ..... Here, IRRI0 = 1
MOV.B R1L,@IRR1:8 ......... IRRI0 is cleared to 0
In the above example, it is assumed that an IRQ0 interrupt is generated while the AND.B
instruction is executing.
The IRQ0 interrupt is disabled because, although the original objective is clearing IRRI1,
IRRI0 is also cleared.
Rev. 1.00, 07/04, page 64 of 570
Rev. 1.00, 07/04, page 65 of 570
Section 4 Interrupt Controller
4.1 Features
This LSI controls interrupts by the interrupt controller. The interrupt controller has the following
features.
• Priorities settable with IPR
An interrupt priority register (IPR) is provided for setting interrupt priorities. Three priority
levels can be set for each module for all interrupts except an NMI and address break.
• Interrupts can be enabled or disabled in three levels by the INTM1 and INTM0 bits in the
interrupt mask register (INTM).
• Fourteen external interrupts
NMI is the highest-priority interrupt, and is accepted at all times. Rising or falling edge
sensing can be selected for NMI. Rising or falling edge sensing can be selected for IRQ0,
IRQ1, IRQ3, IRQ4, and WKP0 to WKP7. Rising, falling, or both edge sensing can be selected
for IRQAEC.
A block diagram of the interrupt controller is shown in figure 4.1.
IENR1
IPR
I
CCR
Priority
determination
NMI/IRQ/
WKP input
IENR1:
IPR:
CCR:
INTM:
IRQ enable register 1
Interrupt priority register
Condition code register
Interrupt mask register
Internal interrupt source
TPU, SCI, etc.
[Legend]
Interrupt request
Vector number
............
INTM
External interrupt
input
Figure 4.1 Block Diagram of Interrupt Controller
Rev. 1.00, 07/04, page 66 of 570
4.2 Input/Output Pins
Table 4.1 shows the pin configuration of the interrupt controller.
Table 4.1 Pin Configuration
Name I/O Function
NMI Input Nonmaskable external interrupt pin
Rising or falling edge can be selected
IRQAEC Input Maskable external interrupt pin
Rising, falling, or both edges can be selected
IRQ4
IRQ3
IRQ1
IRQ0
Input
Input
Input
Input
Maskable external interrupt pins
Rising or falling edge can be selected
WKP7 to WKP0 Input Maskable external interrupt pins
Accepted at a rising or falling edge
4.3 Register Descriptions
The interrupt controller has the following registers.
• Interrupt edge select register (IEGR)
• Wakeup edge select register (WEGR)
• Interrupt enable register 1 (IENR1)
• Interrupt enable register 2 (IENR2)
• Interrupt request register 1 (IRR1)
• Interrupt request register 2 (IRR2)
• Wakeup interrupt request register (IWPR)
• Interrupt priority register A (IPRA)
• Interrupt priority register B (IPRB)
• Interrupt priority register C (IPRC)
• Interrupt priority register D (IPRD)
• Interrupt priority register E (IPRE)
• Interrupt mask register (INTM)
Rev. 1.00, 07/04, page 67 of 570
4.3.1 Interrupt Edge Select Register (IEGR)
IEGR selects the sense of an edge that generates interrupt requests of the NMI, TMIF, ADTRG,
IRQ4, IRQ3, IRQ1, and IRQ0 pins.
Bit Bit Name
Initial
Value R/W Descriptions
7 NMIEG 0 R/W NMI Edge Select
0: Detects a falling edge of the NMI pin input
1: Detects a rising edge of the NMI pin input
6 TMIFEG 0 R/W TMIF Edge Select
0: Detects a falling edge of the TMIF pin input
1: Detects a rising edge of the TMIF pin input
5 ADTRGNEG 0 R/W ADTRG Edge Select
0: Detects a falling edge of the ADTRG pin input
1: Detects a rising edge of the ADTRG pin input
4 IEG4 0 R/W IRQ4 Edge Select
0: Detects a falling edge of the IRQ4 pin input
1: Detects a rising edge of the IRQ4 pin input
3 IEG3 0 R/W IRQ3 Edge Select
0: Detects a falling edge of the IRQ3 pin input
1: Detects a rising edge of the IRQ3 pin input
2 Reserved
1 IEG1 0 R/W IRQ1 Edge Select
0: Detects a falling edge of the IRQ1 pin input
1: Detects a rising edge of the IRQ1 pin input
0 IEG0 0 R/W IRQ0 Edge Select
0: Detects a falling edge of the IRQ0 pin input
1: Detects a rising edge of the IRQ0 pin input
Rev. 1.00, 07/04, page 68 of 570
4.3.2 Wakeup Edge Select Register (WEGR)
WEGR selects the sense of an edge that generates interrupt requests of the WKP7 to WKP0 pins.
Bit Bit Name
Initial
Value R/W Description
7 WKEGS7 0 R/W WKP7 Edge Select
0: Detects a falling edge of the WKP7 pin input
1: Detects a rising edge of the WKP7 pin input
6 WKEGS6 0 R/W WKP6 Edge Select
0: Detects a falling edge of the WKP6 pin input
1: Detects a rising edge of the WKP6 pin input
5 WKEGS5 0 R/W WKP5 Edge Select
0: Detects a falling edge of the WKP5 pin input
1: Detects a rising edge of the WKP5 pin input
4 WKEGS4 0 R/W WKP4 Edge Select
0: Detects a falling edge of the WKP4 pin input
1: Detects a rising edge of the WKP4 pin input
3 WKEGS3 0 R/W WKP3 Edge Select
0: Detects a falling edge of the WKP3 pin input
1: Detects a rising edge of the WKP3 pin input
2 WKEGS2 0 R/W WKP2 Edge Select
0: Detects a falling edge of the WKP2 pin input
1: Detects a rising edge of the WKP2 pin input
1 WKEGS1 0 R/W WKP1 Edge Select
0: Detects a falling edge of the WKP1 pin input
1: Detects a rising edge of the WKP1 pin input
0 WKEGS0 0 R/W WKP0 Edge Select
0: Detects a falling edge of the WKP0 pin input
1: Detects a rising edge of the WKP0 pin input
Rev. 1.00, 07/04, page 69 of 570
4.3.3 Interrupt Enable Register 1 (IENR1)
IENR1 enables the RTC, WKP7 to WKP0, IRQ0, IRQ1, IRQ3, IRQ4, and IRQAEC interrupts.
Bit Bit Name
Initial
Value R/W Description
7 IENRTC 0 R/W RTC Interrupt Request Enable
The RTC interrupt request is enabled when this bit is
set to 1.
6 1 R/W Reserved
This bit is always read as 1.
5 IENWP 0 R/W Wakeup Interrupt Request Enable
The WKP7 to WKP0 interrupt requests are enabled
when this bit is set to 1.
4 IEN4 0 R/W IRQ4 Interrupt Request Enable
The IRQ4 interrupt request is enabled when this bit is
set to 1.
3 IEN3 0 R/W IRQ3 Interrupt Request Enable
The IRQ3 interrupt request is enabled when this bit is
set to 1.
2 IENEC2 0 R/W IRQAEC Interrupt Request Enable
The IRQAEC interrupt request is enabled when this bit
is set to 1.
1 IEN1 0 R/W IRQ1 Interrupt Request Enable
The IRQ1 interrupt request is enabled when this bit is
set to 1.
0 IEN0 0 R/W IRQ0 Interrupt Request Enable
The IRQ0 interrupt request is enabled when this bit is
set to 1.
Rev. 1.00, 07/04, page 70 of 570
4.3.4 Interrupt Enable Register 2 (IENR2)
IENR2 enables the direct transition, A/D converter, timer F, and asynchronous event counter
interrupts.
Bit Bit Name
Initial
Value R/W Description
7 IENDT 0 R/W Direct Transition Interrupt Request Enable
The direct transition interrupt request is enabled when
this bit is set to 1.
6 IENAD 0 R/W A/D Converter Interrupt Request Enable
The A/D converter interrupt request is enabled when
this bit is set to 1.
5 IENSAD 0 R/W ∆Σ A/D Converter Interrupt Request Enable
The ∆Σ A/D converter interrupt request is enabled
when this bit is set to 1.
4 — 1 R/W Reserved
This bit is always read as 1.
3 IENTFH 0 R/W Timer FH Interrupt Request Enable
The timer FH interrupt request is enabled when this bit
is set to 1.
2 IENTFL 0 R/W Timer FL Interrupt Request Enable
The timer FL interrupt request is enabled when this bit
is set to 1.
1 1 R/W Reserved
This bit is always read as 1.
0 IENEC 0 R/W Asynchronous Event Counter Interrupt Request Enable
The asynchronous event counter interrupt request is
enabled when this bit is set to 1.
Rev. 1.00, 07/04, page 71 of 570
4.3.5 Interrupt Request Register 1 (IRR1)
IRR1 indicates the IRQ0, IRQ1, IRQ3, IRQ4, and IRQAEC interrupt request status.
Bit Bit Name
Initial
Value R/W Description
7 to 5 All 1 R/W Reserved
These bits are always read as 1.
4 IRRI4 0
R/(W)* IRQ4 Interrupt Request Flag
[Setting condition]
When the IRQ4 pin is set as the interrupt input pin and
the specified edge is detected
[Clearing condition]
When 0 is written to this bit
3 IRRI3 0
R/(W)* IRQ3 Interrupt Request Flag
[Setting condition]
When the IRQ3 pin is set as the interrupt input pin and
the specified edge is detected
[Clearing condition]
When 0 is written to this bit
2 IRREC2 0
R/(W)* IRQAEC Interrupt Request Flag
[Setting condition]
When the IRQAEC pin is set as the interrupt input pin
and the specified edge is detected
[Clearing condition]
When 0 is written to this bit
1 IRRI1 0
R/(W)* IRQ1 Interrupt Request Flag
[Setting condition]
When the IRQ1 pin is set as the interrupt input pin and
the specified edge is detected
[Clearing condition]
When 0 is written to this bit
0 IRRI0 0
R/(W)* IRQ0 Interrupt Request Flag
[Setting condition]
When the IRQ0 pin is set as the interrupt input pin and
the specified edge is detected
[Clearing condition]
When 0 is written to this bit
Note: * Only a write of 0 for flag clearing is possible.
Rev. 1.00, 07/04, page 72 of 570
4.3.6 Interrupt Request Register 2 (IRR2)
IRR2 indicates the interrupt request status of the direct transition, A/D converter, timer F, and
asynchronous event counter.
Bit Bit Name
Initial
Value R/W Description
7 IRRDT 0 R/(W)* Direct Transition Interrupt Request Flag
[Setting condition]
When the SLEEP instruction is executed and direct
transition is made while the DTON bit in SYSCR2 is set
to 1
[Clearing condition]
When 0 is written to this bit
6 IRRAD 0 R/(W)* A/D Converter Interrupt Request Flag
[Setting condition]
When A/D conversion ends
[Clearing condition]
When 0 is written to this bit
5 IRRSAD 0 R/(W)* ∆Σ A/D Converter Interrupt Request Flag
[Setting condition]
When ∆Σ A/D conversion ends
[Clearing condition]
When 0 is written to this bit
4 1 R/W Reserved
This bit is always read as 1.
3 IRRTFH 0 R/(W)* Timer FH Interrupt Request Flag
[Setting condition]
When the timer FH compare match or overflow occurs
[Clearing condition]
When 0 is written to this bit
2 IRRTFL 0 R/(W)* Timer FL Interrupt Request Flag
[Setting condition]
When the timer FL compare match or overflow occurs
[Clearing condition]
When 0 is written to this bit
Rev. 1.00, 07/04, page 73 of 570
Bit Bit Name
Initial
Value R/W Description
1 1 R/W Reserved
This bit is always read as 1.
0 IRREC 0 R/(W)*Asynchronous Event Counter Interrupt Request Flag
[Setting condition]
When the asynchronous event counter overflows
[Clearing condition]
When 0 is written to this bit
Note: * Only a write of 0 for flag clearing is possible.
4.3.7 Wakeup Interrupt Request Regis ter (IWP R)
IWPR has the WKP7 to WKP0 interrupt request status flags.
Bit Bit Name
Initial
Value R/W Description
7 IWPF7 0 R/W WKP7 Interrupt Request Flag
[Setting condition]
When the WKP7 pin is set as the interrupt input pin and
the specified edge is detected
[Clearing condition]
When 0 is written to this bit
6 IWPF6 0 R/W WKP6 Interrupt Request Flag
[Setting condition]
When the WKP6 pin is set as the interrupt input pin and
the specified edge is detected
[Clearing condition]
When 0 is written to this bit
5 IWPF5 0 R/W WKP5 Interrupt Request Flag
[Setting condition]
When the WKP5 pin is set as the interrupt input pin and
the specified edge is detected
[Clearing condition]
When 0 is written to this bit
Rev. 1.00, 07/04, page 74 of 570
Bit Bit Name
Initial
Value R/W Description
4 IWPF4 0 R/W WKP4 Interrupt Request Flag
[Setting condition]
When the WKP4 pin is set as the interrupt input pin and
the specified edge is detected
[Clearing condition]
When 0 is written to this bit
3 IWPF3 0 R/W WKP3 Interrupt Request Flag
[Setting condition]
When the WKP3 pin is set as the interrupt input pin and
the specified edge is detected
[Clearing condition]
When 0 is written to this bit
2 IWPF2 0 R/W WKP2 Interrupt Request Flag
[Setting condition]
When the WKP2 pin is set as the interrupt input pin and
the specified edge is detected
[Clearing condition]
When 0 is written to this bit
1 IWPF1 0 R/W WKP1 Interrupt Request Flag
[Setting condition]
When the WKP1 pin is set as the interrupt input pin and
the specified edge is detected
[Clearing condition]
When 0 is written to this bit
0 IWPF0 0 R/W WKP0 Interrupt Request Flag
[Setting condition]
When the WKP0 pin is set as the interrupt input pin and
the specified edge is detected
[Clearing condition]
When 0 is written to this bit
Rev. 1.00, 07/04, page 75 of 570
4.3.8 Interrupt Priority Registers A to E (IPRA to IPRE)
IPR sets priorities (levels 2 to 0) for interrupts other than the NMI and address break. The
correspondence between interrupt sources and IPR settings is shown in table 4.2.
Setting a value in the range from H'0 to H'3 in the 2-bit groups of bits 7 and 6, 5 and 4, 3 and 2,
and 1 and 0 sets the priority of the corresponding interrupt. Bits 3 to 0 in IPRE are reserved.
Bit Bit Name
Initial
Value R/W Description
7
6
IPRn7
IPRn6
0
0
R/W
R/W
Set the priority of the corresponding interrupt source.
00: Priority level 0 (Lowest)
01: Priority level 1
1*: Priority level 2 (Highest)
5
4
IPRn5
IPRn4
0
0
R/W
R/W
Set the priority of the corresponding interrupt source.
00: Priority level 0 (Lowest)
01: Priority level 1
1*: Priority level 2 (Highest)
3
2
IPRn3
IPRn2
0
0
R/W
R/W
Set the priority of the corresponding interrupt source.
00: Priority level 0 (Lowest)
01: Priority level 1
1*: Priority level 2 (Highest)
1
0
IPRn1
IPRn0
0
0
R/W
R/W
Set the priority of the corresponding interrupt source.
00: Priority level 0 (Lowest)
01: Priority level 1
1*: Priority level 2 (Highest)
[Legend] *: Don't care.
n = A to E
Rev. 1.00, 07/04, page 76 of 570
4.3.9 Interrupt Mask Register (INTM)
INTM is an 8-bit readable/writable register that controls 3-level interrupt masking depending on
the combination of the INTM0 and INTM1 bits.
Bit Bit Name
Initial
Value R/W Description
7 to 2 All 1 R/W Reserved
These bits are always read as 1.
1
0
INTM1
INTM0
0
0
R/W
R/W
Set the interrupt mask level.
1*: Mask an interrupt with priority level 1 or less
01: Mask an interrupt with priority level 0
00: Accept all interrupts
[Legend] *: Don't care.
4.4 Interrupt Sources
4.4.1 External Interrupts
There are 14 external interrupts: NMI, WKP7 to WKP0, IRQ4, IRQ3, IRQAEC, IRQ1, and IRQ0.
(1) NMI Interrupt
NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the state of
the I bit in CCR. The NMIEG bit in IEGR can be used to select whether an interrupt is requested
at a rising edge or a falling edge on the NMI pin.
(2) WKP7 to WKP0 Interrupts
WKP7 to WKP0 interrupts are requested by the rising or falling edge input signals at the WKP7 to
WKP0 pins.
When the rising or falling edge is input while the WKP7 to WKP0 pin functions are selected by
PMR5, the corresponding bit in IWPR is set to 1 and an interrupt request is generated.
Clearing the IENWP bit in IENR1 to 0 disables the wakeup interrupt request to be accepted.
Setting the I bit in CCR to 1 masks all interrupts.
When exception handling for the WKP7 to WKP0 interrupts is accepted, the I bit in CCR is set to
1. The interrupt priority level can be set by IPR.
Rev. 1.00, 07/04, page 77 of 570
(3) IRQ4, IRQ3, IRQ1, and IRQ0 Interrup ts
IRQ4, IRQ3, IRQ1, and IRQ0 interrupts are requested by input signals at IRQ4, IRQ3, IRQ1, and
IRQ0 pins.
Using the IEG4, IEG3, IEG1, and IEG0 bits in IEGR, it is possible to select whether an interrupt
is generated by a rising or falling edge at IRQ4, IRQ3, IRQ1, and IRQ0 pins.
When the specified edge is input while the IRQ4, IRQ3, IRQ1, and IRQ0 pin functions are
selected by PMRB and PMR9, the corresponding bit in IRR1 is set to 1 and an interrupt request is
generated.
Clearing the IEN4, IEN3, IEN1, and IEN0 bits in IENR1 to 0 disables the interrupt request to be
accepted. Setting the I bit in CCR to 1 masks all interrupts.
The interrupt priority level can be set by IPR.
(4) IRQAEC Interrupts
An IRQAEC interrupt is requested by an input signal at the IRQAEC pin or IECPWM (PWM
output for the asynchronous event counter). When the IRQAEC pin is used as an external interrupt
pin, clear the ECPWME bit in AEGSR to 0.
Using the AIEGS1 and AIEGS0 bits in AEGSR, it is possible to select whether an interrupt is
generated by a rising edge, falling edge, or both edges.
When the IENEC2 bit in IENR1 is set to 1 and the specified edge is input, the corresponding bit in
IRR1 is set to 1 and an interrupt request is generated.
When exception handling for the IRQAEC interrupt is accepted, the I bit in CCR is set to 1.
The interrupt priority level can be set by IPR.
4.4.2 Internal Interrupts
Internal interrupts generated from the on-chip peripheral modules have the following features:
• For each on-chip peripheral module, there are flags that indicate the interrupt request status,
and enable bits that select enabling or disabling of these interrupts. Internal interrupts can be
controlled independently. If an enable bit is set to 1, an interrupt request is sent to the interrupt
controller.
• The interrupt priority level can be set by IPR.
Rev. 1.00, 07/04, page 78 of 570
4.5 Interrupt Exception Handling Vector Table
Table 4.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities.
For default priorities, the lower the vector number, the higher the priority. Modules set at the same
priority will conform to their default priorities. Priorities within a module are fixed. Interrupt
priorities other than NMI and address break can be modified by IPR.
Table 4.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities
Origin of
Interrupt Source Name Vector
Number Vector Address IPR Priority
Reset RES, Watchdog Timer 0 H'0000 High
NMI NMI 3 H'0006
Address break Break conditions satisfied 5 H'000A
External pins IRQ0 6 H'000C IPRA7, IPRA6
IRQ1 7 H'000E IPRA5, IPRA4
IRQAEC 8 H'0010 IPRA3, IPRA2
IRQ3 9 H'0012 IPRA1, IPRA0
IRQ4 10 H'0014
WKP0 11 H'0016 IPRB7, IPRB6
WKP1 12 H'0018
WKP2 13 H'001A
WKP3 14 H'001C
WKP4 15 H'001E
WKP5 16 H'0020
WKP6 17 H'0022
WKP7 18 H'0024
RTC 0.25-second overflow 19 H'0026 IPRB5, IPRB4
0.5-second overflow 20 H'0028
Second periodic overflow 21 H'002A
Minute periodic overflow 22 H'002C
Hour periodic overflow 23 H'002E
Day-of-week periodic
overflow
24 H'0030
Week periodic overflow 25 H'0032
Free-running overflow 26 H'0034 Low
Rev. 1.00, 07/04, page 79 of 570
Origin of
Interrupt Source Name Vector
Number Vector Address IPR Priority
WDT WDT overflow (interval
timer)
27 H'0036 IPRB3, IPRB2 High
AEC AEC overflow 28 H'0038 IPRB1, IPRB0
TPU_1 TG1A (TG1A input
capture/compare match)
29 H'003A IPRC7, IPRC6
TG1B (TG1B input
capture/compare match)
30 H'003C
TCI1V (overflow 1) 31 H'003E
TPU_2 TG2A (TG2A input
capture/compare match)
32 H'0040 IPRC5, IPRC4
TG2B (TG2B input
capture/compare match)
33 H'0042
TCI2V (overflow 2) 34 H'0044
Timer F Timer FL compare match
Timer FL overflow
35 H'0046 IPRC3, IPRC2
Timer FH compare match
Timer FH overflow
36 H'0048
SCI4* Receive data full/transmit
data empty
Transmit end/receive error
37 H'004A IPRC1, IPRC0
SCI3_1 Transmit
completion/transmit data
empty
Receive data full/overrun
error
Framing error/parity error
38 H'004C IPRD7, IPRD6
SCI3_2 Transmit
completion/transmit data
empty
Receive data full/overrun
error
Framing error/parity error
39 H'004E IPRD5, IPRD4
IIC2 Transmit data
empty/transmit end
Receive data full/overrun
error
NACK detection
Arbitration/overrun error
40 H'0050 IPRD3, IPRD2
14-bit ∆Σ A/D
converter
A/D conversion end 41 H'0052 IPRD1, IPRD0
10-bit A/D
converter
A/D conversion end 42 H'0054 IPRE7, IPRE6
(SLEEP instruction
execution)
Direct transition 43 H'0056 IPRE5, IPRE4
Low
Note: * Supported only by the F-ZTAT version.
Rev. 1.00, 07/04, page 80 of 570
4.6 Operation
NMI and address break interrupts are accepted at all times except in the reset state. In the case of
IRQ interrupts, WKP interrupts, and on-chip peripheral module interrupts, an enable bit is
provided for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt
request. Interrupt sources for which the enable bits are set to 1 are controlled by the interrupt
controller.
Table 4.3 shows the interrupt control states. Figure 4.2 shows a flowchart of the interrupt
acceptance operation.
Four-level interrupt masking is controlled according to the combination of the I bit in CCR and the
INTM1 and INTM0 bits in INTM.
Table 4.3 Interrupt Control States
CCR INTM
I INTM1 INTM0 States
1 * * All interrupts other than NMI and address break are masked.
1 * Interrupts with priority level 1 or less are masked.
0 1 Interrupts with priority level 0 are masked.
0
0 0 All interrupts are accepted.
[Legend] *: Don't care.
1. If an interrupt source whose enable bit is set to 1 occurs, an interrupt request is sent to the
interrupt controller.
2. When interrupt requests are sent to the interrupt controller, the interrupt with the highest
priority according to the interrupt priority levels set in IPR is selected, and lower-priority
interrupt requests are held pending. If interrupt requests with the same priority are generated,
the interrupt request with the highest priority according to table 4.2 is selected.
3. In reference to the INTM1 and INTM0 bits in INTM and the I bit in CCR, the interrupt request
is held pending when the I bit is set to 1.
When the I bit is cleared to 0 and INTM1 bit is set to 1, interrupts with priority level 1 or less
are held pending.
When the I bit is cleared to 0, INTM1 bit is cleared to 0, and INTM0 bit is set to 1, interrupt
requests with priority level 0 are held pending.
When the I bit, INTM1 bit, and INTM0 bit are all cleared to 0, all interrupt requests are
accepted.
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
execution of the current instruction has been completed.
5. PC and CCR are saved to the stack area by interrupt exception handling.
Rev. 1.00, 07/04, page 81 of 570
6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI and address break.
7. The CPU generates a vector address for the accepted interrupt and starts interrupt handling by
reading the interrupt routine start address in the vector table.
Program execution state
Save PC and CCR
I 1
Read vector address
Hold pending
Interrupt generated? No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
NMI or address
break?
Level 1 interrupt?
Level 2 interrupt?
I = 0?
INTM1 = 0?
I = 0?
I = 0?
INTM1 = 0?
INTM0 = 0?
Branch to interrupt
handling routine
→
Figure 4.2 Flowchart of Procedure Up to Interrupt Acceptance
4.6.1 Interrupt Exception Handling Sequence
Figure 4.3 shows the interrupt exception handling sequence. The example shown is for the case
where the program area and stack area are in external memory with 16-bit and 2-state access
space.
Rev. 1.00, 07/04, page 82 of 570
Stack
Instruction
prefetch
Interrupt level determination
Wait for end of instruction
(9) (11) (13)(7)(5)
(6) (8) (10) (12) (14)
(3)
(4)
(1)
(2)
Internal
processing
Interrupt accepted Internal
processing
Instruction prefetch
of interrupt handling
routine
Vector fetch
High
(1):
(2)(4):
(3):
(5):
(7):
(6)(8):
Instruction prefetch address (Not executed. This is the contents of the saved PC and the return address.)
Instruction code (Not executed.)
Instruction prefetch address (Not executed.)
SP-2
SP-4
Saved PC and saved CCR
(9)(11):
(10)(12):
(13):
(14):
Vector address
Interrupt handling routine start address (Vector address contents)
Interrupt handling routine start address ((13) = (10)(12))
First instruction of interrupt handling rou
φ
Address
bus
Interrupt
request
signal
RD
HWR, LWR
D15 to D0
Figure 4.3 Interrupt Exception Handling Sequence
Rev. 1.00, 07/04, page 83 of 570
4.6.2 Interrupt Response Times
Table 4.4 shows interrupt response times − the interval between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine.
Table 4.4 Interrupt Response Times (States)
No. Execution Status Internal Memory
1 Interrupt priority determination 2*1
2 Maximum number of wait states until
executing instruction ends
1 to 23
3 PC, CCR stack 4
4 Vector fetch 4
5 Instruction fetch*2 4
6 Internal processing*3 4
Total 19 to 41
Notes: 1. One state in case of an internal interrupt.
2. Prefetch after interrupt acceptance and interrupt handling routine prefetch.
3. Internal processing after interrupt acceptance and internal processing after vector fetch.
Rev. 1.00, 07/04, page 84 of 570
4.7 Usage Notes
4.7.1 Contention between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective
after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction
such as BCLR or MOV, and if an interrupt is generated during execution of the instruction, the
interrupt concerned will still be enabled on completion of the instruction, and so interrupt
exception handling for that interrupt will be executed on completion of the instruction. However,
if there is an interrupt request with higher priority than that interrupt, interrupt exception handling
will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored.
The same also applies when an interrupt source flag is cleared to 0.
Figure 4.4 shows an example in which the TGIEA bit in TIER of the 16-bit timer pulse unit (TPU)
is cleared to 0.
TIER address
φ
TIER write cycle by CPU TGIA exception handling
Internal address
bus
Internal write
signal
TGIEA
TGIA
TGIA interrupt
signal
Figure 4.4 Contention between Interrupt Generation and Disabling
The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while
the interrupt is masked.
Rev. 1.00, 07/04, page 85 of 570
4.7.2 Instructions that Disable Interrupts
The instructions that disable interrupts are LDC, ANDC, ORC, and XORC.
When an interrupt request is generated, an interrupt is requested to the CPU after the interrupt
controller has determined the priority. At that time, if the CPU is executing an instruction that
disables interrupts, the CPU always executes the next instruction after the instruction execution is
completed.
4.7.3 Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during transfer is
not accepted until the transfer is completed.
With the EEPMOV.W instruction, even if an interrupt request other than the NMI is issued during
transfer, the interrupt is not accepted until the transfer is completed. If the NMI interrupt request is
issued, NMI exception handling starts at a break in the transfer cycle. The PC value saved on the
stack in this case is the address of the next instruction.
Therefore, if an NMI interrupt is generated during execution of an EEPMOV.W instruction, the
following coding should be used.
L1: EEPMOV.W
MOV.W R4,R4
BNE L1
4.7.4 IENR Clearing
When an interrupt request is disabled by clearing the interrupt enable register or when the interrupt
request register is cleared, the interrupt request should be masked (I bit = 1). If the above operation
is executed while the I bit is 0 and contention between the instruction execution and the interrupt
request generation occurs, exception handling, which corresponds to the interrupt request
generated after instruction execution of the above operation is completed, is executed.
Rev. 1.00, 07/04, page 86 of 570
CPG0200A_010020040500 Rev. 1.00, 07/04, page 87 of 570
Section 5 Clock Pulse Generators
The clock pulse generator is provided on-chip, including both a system clock pulse generator and
a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator,
system clock divider, and on-chip oscillator (available only for the masked ROM version). The
subclock pulse generator consists of a subclock oscillator and subclock divider. Figure 5.1 (1)
shows a block diagram of the clock pulse generators for the flash memory version and figure 5.1
(2) shows that for the masked ROM version.
System
clock
oscillator
Subclock
oscillator Subclock
divider
System
clock
divider
Prescaler S
(13 bits)
OSC
1
OSC
2
X
1
X
2
System clock pulse generator
φ
OSC
(f
OSC
)
φ
W
(f
W
)
φ
W
/2
φ
W
/4 φ
SUB
φ
w
/2
φ
w
/4
φ
w
φ/2
to
φ/8192
φ
W
/8
φ
φ
OSC
/8
φ
OSC
φ
OSC
/16
φ
OSC
/32
φ
OSC
/64
Subclock pulse generator
Figure 5.1 Block Diagram of Clock Pu lse Generators (Flash Memory Versi o n) ( 1)
System
clock
oscillator
on-chip
oscillator
Subclock
oscillator Subclock
divider
System
clock
divider
Prescaler S
(13 bits)
OSC1
IRQAEC
CLK
OSC2
X1
X2
System clock pulse generator
Subclock pulse generator
φOSC
(fOSC)
φOSC
(fOSC)
fW
(fW)
φW/2
φW/4 φSUB
φ/2
φW/4
φW/2
φ/8192
φW/8
φ
φOSC/8
φOSC
φOSC/16
φOSC/32
φOSC/64
to
φ
w
Figure 5.1 Block Diagram of Clock Pulse Generators (Masked ROM Version) (2)
Rev. 1.00, 07/04, page 88 of 570
The basic clock signals that drive the CPU and on-chip peripheral modules are φ and φSUB. The
system clock is divided by prescaler S to become a clock signal from φ/8192 to φ/2. Both the
system clock and subclock signals are provided to the on-chip peripheral modules.
Since the on-chip oscillator is available for the masked ROM version, the reference clock can be
selected to be output from the on-chip oscillator or system clock oscillator by the input level of the
IRQAEC pin.
5.1 Register Description
• SUB32k control register (SUB32CR)
• Oscillator Control Register (OSCCR)
5.1.1 SUB32k Control Register (SUB32CR)
SUB32CR controls whether the subclock oscillator operates or stops.
Bit Bit Name
Initial
Value R/W Description
7 32KSTOP 0 R/W Subclock Oscillator Operation Control
0: Subclock oscillator operates
1: Subclock oscillator stops
6 0 R/W Reserved
This bit is readable/writable.
5 to 0 All 0 Reserved
These bits cannot be modified.
Rev. 1.00, 07/04, page 89 of 570
5.1.2 Oscillator Control Register (OSCCR)
OSCCR contains a flag indicating the selection status of the system clock oscillator and on-chip
oscillator, indications the input level of the IRQAEC pin during resets (Supported only by the
masked ROM version).
Bit Bit Name
Initial
Value R/W Description
7 to 3 — All 0 R/W Reserved
These bits are readable/writable enable reserves bits.
2 IRQAECF — R IRQAEC flag
This bit indicates the IRQAEC pin input level set during
resets.
0: IRQAEC pin set to GND during resets
1: IRQAEC pin set to Vcc during resets
1 OSCF — R OSC flag
This bit indicates the oscillator operating with the system
clock pulse generator.
0: System clock oscillator operating (on-chip oscillator
stopped)
1: On-chip oscillator operating (system clock oscillator
stopped)
0 — 0 R/W Reserved
Never write 1 to this bit, as it can cause the LSI to
malfunction.
Rev. 1.00, 07/04, page 90 of 570
5.2 System Clock Generator
Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic
resonator, or by providing external clock input.
As shown in figure 5.1 (2), a system clock oscillator and on-chip oscillator are selectable for the
masked ROM version. For the selection method, see section 5.2.4, On-Chip Oscillator Selection
Method (Supported only by the Masked ROM Version).
5.2.1 Connecting Crystal Resonator
Figure 5.2 shows a typical method of connecting a crystal resonator. An AT-cut parallel-resonance
crystal resonator should be used. Figure 5.3 shows the equivalent circuit of a crystal resonator. For
details, refer to section 25, Electrical Characteristics.
1
2
C
1
C
2
OSC
OSC
R1 = 1 MΩ ±20%
R1 Note:
Frequency Manufacturer
4.194 MHz NIHON DEMPA KOGYO.,LTD.
C
1
, C
2
Recommendation Value
12 pF ±20%
Consult with the crystal resonator manufacturer
to determine the circuit constants.
Figure 5.2 Typical Connection to Crystal Resonator
C
S
C
0
R
S
OSC
1
OSC
2
L
S
Figure 5.3 Equivalent Circuit of Crystal Reson at or
Rev. 1.00, 07/04, page 91 of 570
5.2.2 Connecting Ceramic Resonator
Figure 5.4 shows a typical method of connecting a ceramic resonator.
OSC
1
OSC
2
C
1
C
2
Rf = 1 MΩ ±20%
Rf Note: Consult with the crystal resonator manufacturer
to determine the circuit constants.
Frequency Manufacturer
4.194 MHz Murata Manufacturing Co., Ltd.
C1, C2 Recommendation Value
30 pF ±10%
15pF (on-chip)
47pF (on-chip)
Figure 5.4 Typical Connection to Ceramic Resonator
5.2.3 External Clock Input Method
Connect an external clock signal to pin OSC1, and leave pin OSC2 open. Figure 5.5 shows a
typical connection. The duty cycle of the external clock signal must be 45 to 55%.
OSC
1
External clock input
OSC
2
Open
Figure 5.5 Example of External Clock Input
Rev. 1.00, 07/04, page 92 of 570
5.2.4 On-Chip Oscillator Selection Method (Supported only by the Masked ROM
Version)
The on-chip oscillator is selected by the input level of the IRQAEC pin during a reset. The
selection method of the system clock oscillator and the on-chip oscillator is listed in table 5.1. The
input level of the IRQAEC pin during a reset* should be fixed either to Vcc or GND, depending
on the oscillator type to be selected. When the on-chip oscillator is selected, to connect a resonator
to OSC1 or OSC2 is not necessary. In this case, the OSC1 pin should be fixed to Vcc or GND.
Note: * This reset represents an external reset or power-on reset, but not a reset by the
watchdog timer.
Table 5.1 Selection Method for System Clock Oscillator and On-Chip Oscillator
IRQAEC Input Level
(during a reset) 0 1
System clock oscillator Enabled Disabled
On-chip oscillator Disabled Enabled
Rev. 1.00, 07/04, page 93 of 570
5.3 Subclock Generator
5.3.1 Connecting 32.768-kHz/38.4-kHz C ry stal Resonator
Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz or 38.4-kHz
crystal resonator, as shown in figure 5.6. Notes described in section 5.5.2, Notes on Board Design
also apply to this connection.
The 32KSTOP bit in the SUB32CR register can stop the subclock oscillator with the subclock
oscillator program. To stop the subclock oscillator, set the SUB32CR register in active mode.
When restoring from the subclock stopped condition, use the subclock after the oscillation
stabilization time has elapsed, as the same as for the power supply.
X
X
C1
C2
1
2Note: Consult with the crystal resonator manufacturer
to determine the circuit constants.
Frequency Manufacturer
32.768 kHz
38.4 kHz
NIHON DEMPA KOGYO., LTD.
Seiko Instruments Inc.
Products Name
MX73P
VTC-200
C
1
, C
2
Recommendation Value
15 pF
10 pF
Figure 5.6 Typical Connecti on to 32.7 6 8- kHz/ 3 8. 4- kHz Crystal Resona tor
Figure 5.7 shows the equivalent circuit of the crystal resonator.
C
S
C
O
LR
S
X
1
X
2
C = 1.5 pF (typ.)
R = 14 k (typ.)
f = 32.768 kHz/38.4 kHz
O
S
W
Ω
S
Figure 5.7 Equivalent Circ ui t of 3 2. 768 -k H z/38 .4 -kHz Crystal Resonator
Rev. 1.00, 07/04, page 94 of 570
5.3.2 Pin Connection when not Using Subclock
When the subclock is not used, connect the X1 pin to GND and leave the X2 pin open, as shown in
figure 5.8.
X
X
1
2
GND
Open
Figure 5.8 Pin Connection when not Using Subclock
5.3.3 External Clock Input
Connect the external clock to the X1 pin and leave the X2 pin open, as shown in figure 5.9.
X
1
External clock input
X
2
Open
Figure 5.9 Pin Connection when Inputting External Clock
Frequency Subclock (φw)
Duty 45% to 55%
Rev. 1.00, 07/04, page 95 of 570
5.4 Prescalers
This LSI is equipped with an on-chip prescaler (prescaler S).
Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. Its prescaled outputs
provide internal clock signals for on-chip peripheral modules.
5.4.1 Prescaler S
Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. A divided output is
used as an internal clock of an on-chip peripheral module. Prescaler S is initialized to H'0000 at a
reset, and starts counting up on exit from the reset state. In standby mode, watch mode, subactive
mode, and subsleep mode, the system clock pulse generator stops. Prescaler S also stops and is
initialized to H'0000. The CPU cannot read from or write to prescaler S.
The output from prescaler S is shared by the on-chip peripheral modules. The division ratio can be
set separately for each on-chip peripheral function. In active (medium-speed) mode and sleep
mode, the clock input to prescaler S is determined by the division ratio designated by the MA1
and MA0 bits in SYSCR2.
Rev. 1.00, 07/04, page 96 of 570
5.5 Usage Notes
5.5.1 Note on Resonators
Resonator characteristics are closely related to board design and should be carefully evaluated by
the user in the masked ROM version and flash memory version, referring to the examples shown
in this section. Resonator circuit constants will differ depending on a resonator, stray capacitance
in its mounting circuit, and other factors. Suitable constants should be determined in consultation
with the resonator manufacturer. Design the circuit so that the oscillator pin is never applied
voltages exceeding its maximum rating. Figure 5.10 shows an example of crystal and ceramic
resonator arrangement.
(Vss)
P37
X
1
X
2
Vss
OSC
2
OSC
1
TEST
Figure 5.10 Example of Cryst al and Ceramic Resonator Arrangement
Rev. 1.00, 07/04, page 97 of 570
Figure 5.11 (1) shows an example measuring circuit with the negative resistance recommended by
the resonator manufacturer. Note that if the negative resistance of the circuit is less than that
recommended by the resonator manufacturer, it may be difficult to start the main oscillator.
If it is determined that oscillation does not occur because the negative resistance is lower than the
level recommended by the resonator manufacturer, the circuit must be modified as shown in figure
5.11 (2) through (4). Which of the modification suggestions to use and the capacitor capacitance
should be decided based upon evaluation results such as the negative resistance and the frequency
deviation.
(1) Negative Resistance Measuring Circuit (2) Oscillator Circuit Modification Suggestion 1
(3) Oscillator Circuit Modification Suggestion 2 (4) Oscillator Circuit Modification Suggestion 3
C
3
OSC
1
OSC
2
Rf
C
1
C
2
Negative resistance,
addition of -R
OSC
1
OSC
2
Rf
C
1
C
2
Modification
point
Modification
point
Modification
point
OSC
1
OSC
2
Rf
C
1
C
2
OSC
1
OSC
2
Rf
C
1
C
2
Figure 5.11 Negative Resistance Measurement and Circuit Modification Suggesti ons
Rev. 1.00, 07/04, page 98 of 570
5.5.2 Notes on Board Design
When using a crystal resonator (ceramic resonator), place the resonator and its load capacitors as
close as possible to the OSC1 and OSC2 pins. Other signal lines should be routed away from the
resonator circuit to prevent induction from interfering with correct oscillation (see figure 5.12).
OSC1
OSC2
C
1
C
2
Signal A Signal BAvoid
Figure 5.12 Example of Incorrect Board Design
Note: When a crystal resonator or ceramic resonator is connected, consult with the crystal
resonator and ceramic resonator manufacturers to determine the circuit constants because
the constants differ according to the resonator, stray capacitance of the mounting circuit,
and so on.
5.5.3 Definition of Oscillation Stabilization Wait Time
Figure 5.13 shows the oscillation waveform (OSC2), system clock (φ), and microcomputer
operating mode when a transition is made from standby mode, watch mode, or subactive mode, to
active (high-speed/medium-speed) mode, with an resonator connected to the system clock
oscillator.
As shown in figure 5.13, as the system clock oscillator is halted in standby mode, watch mode,
and subactive mode, when a transition is made to active (high-speed/medium-speed) mode, the
sum of the following two times (oscillation stabilization time and wait time) is required.
(1) Oscillation Stabilization Time (trc)
The time from the point at which the system clock oscillator oscillation waveform starts to change
when an interrupt is generated, until the amplitude of the oscillation waveform increases and the
oscillation frequency stabilizes.
Rev. 1.00, 07/04, page 99 of 570
(2) Wait Time
The time required for the CPU and peripheral functions to begin operating after the oscillation
waveform frequency and system clock have stabilized.
The wait time is selected by the STS2 to STS0 bits in SYSCR1.
Oscillation
waveform
(OSC2)
System clock
(φ)
Oscillation
stabilization
time
Operating
mode
Standby mode,
watch mode,
or subactive
mode
Wait time
Oscillation stabilization wait time Active (high-speed) mode or
active (medium-speed) mode
Interrupt accepted
Figure 5.13 Oscillation Stabilization Wait Time
When standby mode, watch mode, or subactive mode is cleared by an interrupt or reset, and a
transition is made to active mode, the oscillation waveform begins to change at the point at which
the interrupt is accepted. Therefore, when a resonator is connected in standby mode, watch mode,
or subactive mode, since the system clock oscillator is halted, the oscillation stabilization time is
required.
The oscillation stabilization time in the case of these state transitions is the same as the oscillation
stabilization time at power-on (the time from the point at which the power supply voltage reaches
the prescribed level until the oscillation stabilizes), specified by "oscillation stabilization time trc"
in the AC characteristics.
Once the system clock has halted, a wait time of at least 8 states is necessary in order for the CPU
and peripheral functions to operate normally.
Rev. 1.00, 07/04, page 100 of 570
Thus, the time required from interrupt generation until operation of the CPU and peripheral
functions is the sum of the above described oscillation stabilization time and wait time. This total
time is called the oscillation stabilization wait time, and is expressed by equation (1) below.
Oscillation stabilization wait time = oscillation stabilization time + wait time
= trc + (8 to 16,384 states) ................. (1)
Therefore, when a transition is made from standby mode, watch mode, or subactive mode, to
active (high-speed/medium-speed) mode, with an resonator connected to the system clock
oscillator, careful evaluation must be carried out on the mounting circuit before deciding the
oscillation stabilization wait time. In particular, since the oscillation stabilization time differs
according to mounting circuit constants, stray capacitance, and so forth, suitable constants should
be determined in consultation with the resonator manufacturer.
5.5.4 Note on Subclock Stop State
To stop the subclock, a state transition should not be made except to mode in which the system
clock operates. If the state transition is made to other mode, it may result in incorrect operation.
5.5.5 Note on Using Resonator
When a microcomputer operates, the internal power supply potential fluctuates slightly in
synchronization with the system clock. Depending on the individual resonator characteristics, the
oscillation waveform amplitude may not be sufficiently large immediately after the oscillation
stabilization wait time, making the oscillation waveform susceptible to influence by fluctuations in
the power supply potential. In this state, the oscillation waveform may be disrupted, leading to an
unstable system clock and incorrect operation of the microcomputer.
If incorrect operation occurs, change the setting of the standby timer select bits 2 to 0 (STS2 to
STS0) (bits 6 to 4 in the system control register 1 (SYSCR1)) to give a longer wait time.
For example, if incorrect operation occurs with a wait time setting of 16 states, check the
operation with a wait time setting of 1,024 states or more.
If the same kind of incorrect operation occurs after a reset as after a state transition, hold the RES
pin low for a longer period.
Rev. 1.00, 07/04, page 101 of 570
5.5.6 Note on Using Power-On Reset
The reset clear time for a power-on reset is determined by the CR time constant. When the power-
on reset is used, the resistance R is fixed to 100 kΩ (on-chip). The external capacitance C should
be adjusted to secure the oscillation stabilization time before reset clearing. For details on the
power-on reset, refer to section 22, Power-On Reset Circuit.
Rev. 1.00, 07/04, page 102 of 570
Rev. 1.00, 07/04, page 103 of 570
Section 6 Power-Down Modes
This LSI has eight modes of operation after a reset. These include a normal active (high-speed)
mode and seven power-down modes, in which power consumption is significantly reduced. The
module standby function reduces power consumption by selectively halting on-chip module
functions.
• Active (medium-speed) mode
The CPU and all on-chip peripheral modules are operable on the system clock. The system
clock frequency can be selected from φosc/8, φosc/16, φosc/32, and φosc/64.
• Subactive mode
The CPU and all on-chip peripheral modules are operable on the subclock. The subclock
frequency can be selected from φw/2, φw/4, and φw/8.
• Sleep (high-speed) mode
The CPU halts. On-chip peripheral modules are operable on the system clock.
• Sleep (medium-speed) mode
The CPU halts. On-chip peripheral modules are operable on the system clock. The system
clock frequency can be selected from φosc/8, φosc/16, φosc/32, and φosc/64.
• Subsleep mode
The CPU halts. The on-chip peripheral modules are operable on the subclock. The subclock
frequency can be selected from φw/2, φw/4, and φw/8.
• Watch mode
The CPU halts. The on-chip peripheral modules are operable on the subclock.
• Standby mode
The CPU and all on-chip peripheral modules halt.
• Module standby function
Independent of the above modes, power consumption can be reduced by halting on-chip
peripheral modules that are not used in module units.
Note: In this manual, active (high-speed) mode and active (medium-speed) mode are collectively
called active mode.
Rev. 1.00, 07/04, page 104 of 570
6.1 Register Descriptions
The registers related to power-down modes are as follows.
• System control register 1 (SYSCR1)
• System control register 2 (SYSCR2)
• Clock halt registers 1 and 2 (CKSTPR1 and CKSTPR2)
6.1.1 System Control Register 1 (SYSCR1)
SYSCR1 controls the power-down modes, as well as SYSCR2.
Bit Bit Name
Initial
Value R/W Description
7 SSBY 0 R/W Software Standby
Selects the mode to transit after the execution of the
SLEEP instruction.
0: A transition is made to sleep mode or subsleep mode.
1: A transition is made to standby mode or watch mode.
For details, see table 6.2.
6
5
4
STS2
STS1
STS0
0
0
0
R/W
R/W
R/W
Standby Timer Select 2 to 0
Designate the time the CPU and peripheral modules
wait for stable clock operation after exiting from standby
mode, subactive mode, subsleep mode, or watch mode
to active mode or sleep mode due to an interrupt. The
designation should be made according to the operating
frequency so that the waiting time is at least equal to the
oscillation stabilization time. The relationship between
the specified value and the number of wait states is
shown in table 6.1.
When an external clock is to be used, the minimum
value (STS2 = 1, STS1 = 0, STS0 = 1) is recommended.
If the setting other than the recommended value is
made, operation may start before the end of the waiting
time.
3 LSON 0 R/W Selects the system clock (φ) or subclock (φSUB) as the
CPU operating clock when watch mode is cleared.
0: The CPU operates on the system clock (φ)
1: The CPU operates on the subclock (φSUB)
2 TMA3 0 R/W Selects the mode to which the transition is made after
the SLEEP instruction is executed with bits SSBY and
LSON in SYSCR1 and bits DTON and MSON in
SYSCR2. For details, see table 6.2.
Rev. 1.00, 07/04, page 105 of 570
Bit Bit Name
Initial
Value R/W Description
1
0
MA1
MA0
1
1
R/W
R/W
Active Mode Clock Select 1 and 0
Select the operating clock frequency in active (medium-
speed) mode and sleep (medium-speed) mode. The
MA1 and MA0 bits should be written to in active (high-
speed) mode or subactive mode.
00: φOSC/8
01: φOSC/16
10: φOSC/32
11: φOSC/64
Table 6.1 Operating Frequency and Waiting Time
Bit Operating Frequency
STS2 STS1 STS0 Waiting Time 5 MHz 2 MHz
0 0 0 8,192 states 1.638 4.1
1 16,384 states 3.277 8.2
1 0 1,024 states 0.205 0.512
1 2,048 states 0.410 1.024
1 0 0 4,096 states 0.819 2.048
1 2 states (external clock input) 0.0004 0.001
1 0 8 states 0.002 0.004
1 16 states 0.003 0.008
Note: Time unit is ms.
When an external clock is input, bits STS2 to STS0 should be set as external clock input
mode before mode transition is executed. When an external clock is not used, these bits
should not be set as external clock input mode.
Rev. 1.00, 07/04, page 106 of 570
6.1.2 System Control Register 2 (SYSCR2)
SYSCR2 controls the power-down modes, as well as SYSCR1.
Bit Bit Name
Initial
Value R/W Description
7 to 5 All 1 Reserved
These bits are always read as 1 and cannot be
modified.
4 NESEL 1 R/W Noise Elimination Sampling Frequency Select
The subclock pulse generator generates the watch clock
signal (φW) and the system clock pulse generator
generates the oscillator clock (φOSC). This bit selects the
sampling frequency of φOSC when φW is sampled. When
φOSC = 2 to 10 MHz, clear this bit to 0.
0: Sampling rate is φOSC/16.
1: Sampling rate is φOSC/4.
3 DTON 0 R/W Direct Transfer on Flag
Selects the mode to which the transition is made after
the SLEEP instruction is executed with bits SSBY,
TMA3, and LSON in SYSCR1 and bit MSON in
SYSCR2. For details, see table 6.2.
2 MSON 0 R/W Medium Speed on Flag
After standby, watch, or sleep mode is cleared, this bit
selects active (high-speed) or active (medium-speed)
mode.
0: Operation in active (high-speed) mode
1: Operation in active (medium-speed) mode
1
0
SA1
SA0
0
0
R/W
R/W
Subactive Mode Clock Select 1 and 0
Select the operating clock frequency in subactive and
subsleep modes. The operating clock frequency
changes to the set frequency after the SLEEP
instruction is executed.
00: φW/8
01: φW/4
1X: φW/2
[Legend] X: Don't care.
Rev. 1.00, 07/04, page 107 of 570
6.1.3 Clock Halt Registers 1 and 2 (CKSTPR1 and CKSTPR2)
CKSTPR1 and CKSTPR2 allow the on-chip peripheral modules to enter the standby state in
module units.
• CKSTPR1
Bit Bit Name
Initial
Value R/W Description
7 S4CKSTP*1 1 R/W*1 SCI4 Module Standby
SCI4 enters standby mode when this bit is cleared to 0.
6 S31CKSTP 1 R/W SCI3 Module Standby*2
SCI31 enters standby mode when this bit is cleared to 0.
5 S32CKSTP 1 R/W SCI3 Module Standby*2
SCI32 enters standby mode when this bit is cleared to
0.*1
4 ADCKSTP 1 R/W A/D Converter Module Standby
A/D converter enters standby mode when this bit is
cleared to 0.
3 DADCKSTP 1 R/W ∆Σ A/D Converter Module Standby
∆Σ A/D converter enters standby mode when this bit is
cleared to 0.
2 TFCKSTP 1 R/W Timer F Module Standby
Timer F enters standby mode when this bit is cleared to
0.
1 FROMCKSTP 1 R/W Flash Memory Module Standby
Flash memory enters standby mode when this bit is
cleared to 0.
0 RTCCKSTP 1 R/W RTC Module Standby
RTC enters standby mode when this bit is cleared to 0.
Rev. 1.00, 07/04, page 108 of 570
• CKSTPR2
Bit Bit Name
Initial
Value R/W Description
7 ADBCKSTP 1 R/W Address Break Module Standby
The address break enters standby mode when this bit is
cleared to 0.
6 TPUCKSTP 1 R/W TPU Module Standby
The TPU enters standby mode when this bit is cleared
to 0.
5 IICCKSTP 1 R/W IIC2 Module Standby
The IIC2 enters standby mode when this bit is cleared to
0.
4 PW2CKSTP 1 R/W PWM2 Module Standby
The PWM2 enters standby mode when this bit is cleared
to 0.
3 AECCKSTP 1 R/W Asynchronous Event Counter Module Standby
The asynchronous event counter enters standby mode
when this bit is cleared to 0.
2 WDCKSTP 1 R/W*3 Watchdog Timer Module Standby
The watchdog timer enters standby mode when this bit
is cleared to 0.
1 PW1CKSTP 1 R/W PWM1 Module Standby
The PWM1 enters standby mode when this bit is cleared
to 0.
0 LDCKSTP 1 R/W LCD Module Standby
The LCD controller/driver enters standby mode when
this bit is cleared to 0.
Notes: 1. This is a reserved bit which is not readable/writable in the masked ROM version.
2. When the SCI module standby is set, all registers in the SCI3 enter the reset state.
3. This bit is valid when the WDON bit in TCSRW is 0. If this bit is cleared to 0 while the
WDON bit is set to 1 (while the watchdog timer is operating), this bit is cleared to 0.
However, the watchdog timer does not enter module standby mode and continues
operating. When the watchdog timer stops operating and the WDON bit is cleared to 0
by software, this bit is valid and the watchdog timer enters module standby mode.
Rev. 1.00, 07/04, page 109 of 570
6.2 Mode Transitions and States of LSI
Figure 6.1 shows the possible transitions among these operating modes. A transition is made from
the program execution state to the program halt state of the program by executing a SLEEP
instruction. Interrupts allow for returning from the program halt state to the program execution
state of the program. A direct transition between active mode and subactive mode, which are both
program execution states, can be made without halting the program. RES input enables transitions
from a mode to the reset state. Table 6.2 shows the transition conditions of each mode after the
SLEEP instruction is executed and a mode to return by an interrupt. Table 6.3 shows the internal
states of the LSI in each mode.
Rev. 1.00, 07/04, page 110 of 570
Reset state
Standby
mode
Watch
mode
Active
(high-speed
mode)
Sleep
(high-speed)
mode
Active
(medium-speed)
mode
Sleep
(medium-speed)
mode
Subactive
mode
Subsleep
mode
Power-down modes: Transition is made after exception handling
is executed.
Program
halt state
Program
execution state
Program
halt state
Note: A transition between different modes cannot be made to occur simply because an interrupt
request is generated. Make sure that interrupt handling is performed after the interrupt is
accepted.
SLEEP
instruction
SLEEP
instruction
SLEEP
instruction
SLEEP
instruction
SLEEP
instruction
SLEEP
instruction
SLEEP
instruction
SLEEP
instruction
SLEEP
instruction
SLEEP
instruction
b
a
d
d
4
3
3
1
1
2
4
f
ga
b
e
e
e
1
j
i
i
c
h
LSON MSON SSBY TMA3 DTON
a 0 0 0 * 0
b 0 1 0 * 0
c 1 * 0 1 0
d 0 * 1 0 0
e * * 1 1 0
f 0 0 0 * 1
g 0 1 0 * 1
h 0 1 1 1 1
i 1 * 1 1 1
j 0 0 1 1 1
Interrupt Sources
RTC, timer F, IRQ0 interrupt, Asynchronous
event counter, WKP7 to WKP0 interrupts
RTC, timer F, TPU, SCI3 interrupt, IRQ4, IRQ3,
IRQ1, IRQ0, IRQAEC interrupts, WKP7 to WKP0
interrupts, Asynchronous event counter
All interrupts
IRQ1, IRQ0, WKP7 to WKP0
interrupts, Asynchronous event counter
* Don't care
Mode Transition Conditions (1) Mode Transition Conditions (2)
SLEEP
instruction
SLEEP
instruction
SLEEP
instruction
SLEEP
instruction
SLEEP
instruction
SLEEP
instruction
1
2
3
4
Figure 6.1 Mode Transiti o n Di agram
Rev. 1.00, 07/04, page 111 of 570
Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling
LSON
MSON
SSBY
TMA3
DTON
Transition Mode after
SLEEP Instruction
Execution
Transition Mode due to
Interrupt
0 0 0 X 0 Sleep (high-speed) mode Active (high-speed) mode
0 1 0 X 0 Sleep (medium-speed)
mode
Active (medium-speed)
mode
1 X 0 1 0 Subsleep mode Subactive mode
0 X 1 0 0 Standby mode Active mode
X X 1 1 0 Watch mode Active mode, subactive
mode
0 0 0 X 1 Active (high-speed) mode
0 1 0 X 1 Active (medium-speed)
mode
0 1 1 1 1 Active (medium-speed)
mode
[Legend] X: Don't care.
Rev. 1.00, 07/04, page 112 of 570
Table 6.3 Internal State in Each Operating Mode
Active Mode Sleep Mode
Function High-speed
Medium-
speed High-speed
Medium-
speed Watch Mode Subactive
Mode Subsleep
Mode Stand-by
Mode
System clock oscillator Functioning Functioning Functioning Functioning Halted Halted Halted Halted
Subclock oscillator Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning
Instructions Halted Halted Halted Halted Halted
RAM
Registers
Retained
CPU
I/O
Functioning Functioning
Retained Retained Retained
Functioning
Retained
Retained*1
IRQ0 Functioning
IRQ1
Functioning
IRQ3
IRQ4
IRQAEC
Retained*4
Retained*4
External
interrupts
WKP7 to WKP0
Functioning Functioning Functioning Functioning
Functioning
Functioning Functioning
Functioning
RTC Functioning/
retained*9
Functioning/
retained*9
Functioning/
retained*9
Functioning/
retained*9
Asynchronous
event counter
Functioning*5Functioning Functioning Functioning*5
Timer F Functioning/
retained*6
Functioning/
retained*6
Functioning/
retained*6
Retained
TPU Retained Retained Retained Retained
WDT Functioning*8/
retained
Functioning*8/
retained*7
Functioning*8/
retained
Functioning*8/
retained
SCI3/IrDA Reset
Functioning/
retained*2
Functioning/
retained*2
Reset
IIC2 Retained Retained Retained Retained
PWM Retained Retained Retained Retained
A/D converter Retained Retained Retained Retained
∆Σ A/D converter Retained Retained Retained Retained
LCD
Functioning Functioning Functioning Functioning
Functioning/
retained*3
Functioning/
retained*3
Functioning/
retained*3
Retained
Notes: 1. Register contents are retained. Output is the high-impedance state.
2. Functioning if φW/2 is selected as an internal clock, or halted and retained otherwise.
3. Functioning if φw, φw/2, or φw/4 is selected as a clock to be used. Halted and retained
otherwise.
4. An external interrupt request is ignored. Contents of the interrupt request register are
not affected.
5. The counter can be incremented.
6. Functioning if φw/4 is selected as an internal clock. Halted and retained otherwise.
7. Functioning if φw/32 is selected as an internal clock. Halted and retained otherwise.
8. Functioning if the on-chip oscillator is selected.
9. Functioning if the internal time keeping time-base function is selected and retained if the
interval timer is selected.
Rev. 1.00, 07/04, page 113 of 570
6.2.1 Sleep Mode
In sleep mode, CPU operation is halted but the system clock oscillator, subclock oscillator, and
on-chip peripheral modules function. In sleep (medium-speed) mode, the on-chip peripheral
modules function at the clock frequency set by the MA1 and MA0 bits in SYSCR1. CPU register
contents are retained.
Sleep mode is cleared by an interrupt. When an interrupt is requested, sleep mode is cleared and
interrupt exception handling starts. Sleep mode is not cleared if the I bit in CCR is set to 1 or the
requested interrupt is disabled by the interrupt enable bit. After sleep mode is cleared, a transition
is made from sleep (high-speed) mode to active (high-speed) mode or from sleep (medium-speed)
mode to active (medium-speed) mode.
When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared. Since an
interrupt request signal is synchronous with the system clock, the maximum time of 2/φ (s) may be
delayed from the point at which an interrupt request signal occurs until the interrupt exception
handling is started.
Furthermore, it sometimes operates with half state early timing at the time of transition to sleep
(medium-speed) mode.
6.2.2 Standby Mode
In standby mode, the system clock oscillator stops, so the CPU and on-chip peripheral modules
stop functioning when the WDT disables the on-chip oscillator operation. However, as long as the
rated voltage is supplied, the contents of CPU registers, on-chip RAM, and some on-chip
peripheral module registers are retained. On-chip RAM contents will be retained as long as the
voltage set by the RAM data retention voltage is provided. The I/O ports go to the high-impedance
state.
Standby mode is cleared by an interrupt. When an interrupt is requested, the system clock pulse
generator starts. After the time set in bits STS2 to STS0 in SYSCR1 has elapsed, standby mode is
cleared and interrupt exception handling starts. After standby mode is cleared, a transition is made
to active (high-speed) or active (medium-speed) mode according to the MSON bit in SYSCR2.
Standby mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled by
the interrupt enable bit.
When the RES pin goes low, the system clock oscillator starts. Since system clock signals are
supplied to the entire chip as soon as the system clock oscillator starts functioning, the RES pin
must be kept low until the system clock oscillator output stabilizes (except when the power-on
reset circuit is used). After the oscillator output has stabilized, the CPU starts reset exception
handling if the RES pin is driven high (except when the power-on reset circuit is used).
Rev. 1.00, 07/04, page 114 of 570
6.2.3 Watch Mode
In watch mode, the system clock oscillator (when the WDT disables the on-chip oscillator
operation) and CPU operation stop and on-chip peripheral modules stop functioning except for the
RTC, timer F, asynchronous event counter, and LCD controller/driver. However, as long as the
rated voltage is supplied, the contents of CPU registers, some on-chip peripheral module registers,
and on-chip RAM are retained. The I/O ports retain their state before the transition.
Watch mode is cleared by an interrupt. When an interrupt is requested, watch mode is cleared and
interrupt exception handling starts. When watch mode is cleared by an interrupt, a transition is
made to active (high-speed) mode, active (medium-speed) mode, or subactive mode depending on
the settings of the LSON bit in SYSCR1 and the MSON bit in SYSCR2. When the transition is
made to active mode, after the time set in bits STS2 to STS0 in SYSCR1 has elapsed, interrupt
exception handling starts. Watch mode is not cleared if the I bit in CCR is set to 1 or the requested
interrupt is disabled by the interrupt enable register.
When the RES pin goes low, the system clock pulse generator starts. Since system clock signals
are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the
RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator
output has stabilized, the CPU starts reset exception handling if the RES pin is driven high.
6.2.4 Subsleep Mode
In subsleep mode, the CPU operation stops but on-chip peripheral modules other than TPU, IIC2,
the ∆Σ A/D converter, the A/D converter and PWM function. As long as a required voltage is
applied, the contents of CPU registers, the on-chip RAM, and some registers of the on-chip
peripheral modules are retained. I/O ports keep the same states as before the transition.
Subsleep mode is cleared by an interrupt. When an interrupt is requested, subsleep mode is cleared
and interrupt exception handling starts. After subsleep mode is cleared, a transition is made to
subactive mode. Subsleep mode is not cleared if the I bit in CCR is set to 1 or the requested
interrupt is disabled by the interrupt enable register.
When the RES pin goes low, the system clock pulse generator starts. Since system clock signals
are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the
RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator
output has stabilized, the CPU starts reset exception handling if the RES pin is driven high.
Rev. 1.00, 07/04, page 115 of 570
6.2.5 Subactive Mode
In subactive mode, the system clock oscillator (when the WDT disables the on-chip oscillator
operation) stops but on-chip peripheral modules other than TPU, IIC2, the ∆Σ A/D converter, the
A/D converter, and PWM function. As long as a required voltage is applied, the contents of some
registers of the on-chip peripheral modules are retained.
Subactive mode is cleared by the SLEEP instruction. When subacitve mode is cleared, a transition
to subsleep mode, active mode, or watch mode is made, depending on the combination of bits
SSBY, LSON, and TMA3 in SYSCR1 and bits MSON and DTON in SYSCR2. Subactive mode is
not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled by the interrupt
enable register.
When the RES pin goes low, the system clock pulse generator starts. Since system clock signals
are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the
RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator
output has stabilized, the CPU starts reset exception handling if the RES pin is driven high.
The operating frequency of subactive mode is selected from φW/2, φW/4, and φW/8 by the SA1 and
SA0 bits in SYSCR2. After the SLEEP instruction is executed, the operating frequency changes to
the frequency which is set before the execution.
6.2.6 Active (Medium-Speed) Mode
In active (medium-speed) mode, the system clock oscillator, subclock oscillator, CPU, and on-
chip peripheral module function.
Active (medium-speed) mode is cleared by the SLEEP instruction. When active (medium-speed)
mode is cleared, a transition to standby mode is made depending on the combination of bits
SSBY, LSON, and TMA3 in SYSCR1, a transition to watch mode is made depending on the
combination of bits SSBY and TMA3 in SYSCR1, or a transition to sleep mode is made
depending on the combination of bits SSBY and LSON in SYSCR1. Moreover, a transition to
active (high-speed) mode or subactive mode is made by a direct transition. Active (medium-sleep)
mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled in the
interrupt enable register. When the RES pin goes low, the CPU goes into the reset state and active
(medium-sleep) mode is cleared.
Furthermore, it sometimes operates with half state early timing at the time of transition to active
(medium-speed) mode.
In active (medium-speed) mode, the on-chip peripheral modules function at the clock frequency
set by the MA1 and MA0 bits in SYSCR1.
Rev. 1.00, 07/04, page 116 of 570
6.3 Direct Transition
The CPU can execute programs in two modes: active and subactive mode. A direct transition is a
transition between these two modes without stopping program execution. A direct transition can
be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1. The direct
transition also enables operating frequency modification in active or subactive mode. After the
mode transition, direct transition interrupt exception handling starts.
If the direct transition interrupt is disabled by IENR2, a transition is made instead to sleep or
watch mode. Note that if a direct transition is attempted while the I bit in CCR is set to 1, sleep or
watch mode will be entered, and the resulting mode cannot be cleared by means of an interrupt.
• Direct transfer from active (high-speed) mode to active (medium-speed) mode
When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and
LSON bits in SYSCR1 are cleared to 0 and the MSON and DTON bits in SYSCR2 are set to
1, a transition is made to active (medium-speed) mode via sleep mode.
• Direct transfer from active (medium-speed) mode to active (high-speed) mode
When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and
LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the
DTON bit in SYSCR2 is set to 1, a transition is made to active (high-speed) mode via sleep
mode.
• Direct transfer from active (high-speed) mode to subactive mode
When a SLEEP instruction is executed in active (high-speed) mode while the SSBY, TMA3,
and LSON bits in SYSCR1 are set to 1 and the DTON bit in SYSCR2 is set to 1, a transition is
made to subactive mode via watch mode.
• Direct transfer from subactive mode to active (high-speed) mode
When a SLEEP instruction is executed in subactive mode while the SSBY and TMA3 bits in
SYSCR1 are set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is
cleared to 0, and the DTON bit in SYSCR2 is set to 1, a transition is made directly to active
(high-speed) mode via watch mode after the waiting time set in bits STS2 to STS0 in SYSCR1
has elapsed.
• Direct transfer from active (medium-speed) mode to subactive mode
When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY,
TMA3, and LSON bits in SYSCR1 are set to 1 and the DTON bit in SYSCR2 is set to 1, a
transition is made to subactive mode via watch mode.
• Direct transfer from subactive mode to active (medium-speed) mode
When a SLEEP instruction is executed in subactive mode while the SSBY and TMA3 bits in
SYSCR1 are set to 1, the LSON bit in SYSCR1 is cleared to 0, and the MSON and DTON bits
in SYSCR2 are set to 1, a transition is made directly to active (medium-speed) mode via watch
mode after the waiting time set in bits STS2 to STS0 in SYSCR1 has elapsed.
Rev. 1.00, 07/04, page 117 of 570
6.3.1 Direct Transition from Active (High-Speed) Mode to Active (Medium-Speed) Mode
The time from the start of SLEEP instruction execution to the end of interrupt exception handling
(the direct transition time) is calculated by equation (1).
Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal
processing states)} × (tcyc before transition) + (Number of interrupt
exception handling execution states) × (tcyc after transition)
…………………(1)
Example: Direct transition time = (2 + 1) × tosc + 14 × 8tosc = 115tosc (when φ/8 is
selected as the CPU operating clock)
[Legend]
tosc: OSC clock cycle time
tcyc: System clock (φ) cycle time
6.3.2 Direct Transition from Active (Medium-Speed) Mode to Active (High-Speed) Mode
The time from the start of SLEEP instruction execution to the end of interrupt exception handling
(the direct transition time) is calculated by equation (2).
Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal
processing states)} × (tcyc before transition) + (Number of interrupt
exception handling execution states) × (tcyc after transition)
………………..(2)
Example: Direct transition time = (2 + 1) × 8tosc + 14 × tosc = 38tosc (when φ/8 is
selected as the CPU operating clock)
[Legend]
tosc: OSC clock cycle time
tcyc: System clock (φ) cycle time
Rev. 1.00, 07/04, page 118 of 570
6.3.3 Direct Transition from Subactive Mode to Active (High-Speed) Mode
The time from the start of SLEEP instruction execution to the end of interrupt exception handling
(the direct transition time) is calculated by equation (3).
Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal
processing states)} × (tsubcyc before transition) + {(Wait time set in bits
STS2 to STS0) + (Number of interrupt exception handling execution
states)} × (tcyc after transition)
………………..(3)
Example: Direct transition time = (2 + 1) × 8tw + (8192 + 14) × tosc = 24tw + 8206tosc
(when φw/8 is selected as the CPU operating clock and wait time = 8192 states)
[Legend]
tosc: OSC clock cycle time
tw: Watch clock cycle time
tcyc: System clock (φ) cycle time
tsubcyc: Subclock (φSUB) cycle time
6.3.4 Direct Transition from Subactive Mode to Active (Medium-Speed) Mode
The time from the start of SLEEP instruction execution to the end of interrupt exception handling
(the direct transition time) is calculated by equation (4).
Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal
processing states)} × (tsubcyc before transition) + {(Wait time set in bits
STS2 to STS0) + (Number of interrupt exception handling execution
states)} × (tcyc after transition)
………………..(4)
Example: Direct transition time = (2 + 1) × 8tw + (8192 + 14) × 8tosc
= 24tw + 65648tosc
(when φw/8 or φ/8 is selected as the CPU operating clock and wait time = 8192
states)
[Legend]
tosc: OSC clock cycle time
tw: Watch clock cycle time
tcyc: System clock (φ) cycle time
tsubcyc: Subclock (φSUB) cycle time
Rev. 1.00, 07/04, page 119 of 570
6.3.5 Notes on External Input Signal Changes before/after Direct Transition
• Direct transition from active (high-speed) mode to subactive mode
Since the mode transition is performed via watch mode, see section 6.5.2, Notes on External
Input Signal Changes before/after Standby Mode.
• Direct transition from active (medium-speed) mode to subactive mode
Since the mode transition is performed via watch mode, see section 6.5.2, Notes on External
Input Signal Changes before/after Standby Mode.
• Direct transition from subactive mode to active (high-speed) mode
Since the mode transition is performed via watch mode, see section 6.5.2, Notes on External
Input Signal Changes before/after Standby Mode.
• Direct transition from subactive mode to active (medium-speed) mode
Since the mode transition is performed via watch mode, see section 6.5.2, Notes on External
Input Signal Changes before/after Standby Mode.
6.4 Module Standby Function
The module-standby function can be set to any peripheral module. In module standby mode, the
clock supply to modules stops to enter the power-down mode. Module standby mode enables each
on-chip peripheral module to enter the standby state by clearing a bit that corresponds to each
module in CKSTPR1 and CKSTPR2 to 0 and cancels the mode by setting the bit to 1. (See section
6.1.3, Clock Halt Registers 1 and 2 (CKSTPR1 and CKSTPR2).)
Rev. 1.00, 07/04, page 120 of 570
6.5 Usage Notes
6.5.1 Standby Mode Transition and Pin States
When a SLEEP instruction is executed in active (high-speed) mode or active (medium-speed)
mode while the SSBY and TMA3 bits in SYSCR1 are set to 1 and the LSON bit in SYSCR1 is
cleared to 0, a transition is made to standby mode. At the same time, pins go to the high-
impedance state (except pins for which the pull-up MOS is designated as on). Figure 6.2 shows
the timing in this case.
SLEEP instruction fetchInternal data bus Next instruction fetch
Port outputPins High-impedance
Active (high-speed) mode or active (medium-speed) mode Standby mode
SLEEP instruction execution Internal processing
φ
Figure 6.2 Standby Mode T ransi tion and Pin States
6.5.2 Notes on External Input Signal Changes before/after Standby Mode
(1) When External Input Signal Changes before/after Standby Mode or Watch Mode
When an external input signal such as IRQ, WKP, or IRQAEC is input, both the high- and low-
level widths of the signal must be at least two cycles of system clock φ or subclock φSUB (referred
to together in this section as the internal clock). As the internal clock stops in standby mode and
watch mode, the width of external input signals requires careful attention when a transition is
made via these operating modes. Ensure that external input signals conform to the conditions
stated in (3), Recommended Timing of External Input Signals, below.
(2) When External Input Signals cannot be Captured because Internal Clock Stops
The case of falling edge capture is shown in figure 6.3.
As shown in the case marked "Capture not possible," when an external input signal falls
immediately after a transition to active mode or subactive mode, after oscillation is started by an
interrupt via a different signal, the external input signal cannot be captured if the high-level width
at that point is less than 2 tcyc or 2 tsubcyc.
Rev. 1.00, 07/04, page 121 of 570
(3) Recommended Timing of External Input Signals
To ensure dependable capture of an external input signal, high- and low-level signal widths of at
least 2 tcyc or 2 tsubcyc are necessary before a transition is made to standby mode or watch mode, as
shown in "Capture possible: case 1."
External input signal capture is also possible with the timing shown in "Capture possible: case 2"
and "Capture possible: case 3," in which a 2 tcyc or 2 tsubcyc level width is secured.
t
cyc
t
subcyc
t
cyc
t
subcyc
t
cyc
t
subcyc
t
cyc
t
subcyc
Capture possible: case 1
Capture possible: case 2
Capture possible: case 3
Capture not possible
φ or φ
SUB
Operating mode
Active (high-speed, medium-speed)
mode or subactive mode
Standby mode or
watch mode
Wait for osc-
illation
stabilization
Active (high-speed, medium-speed)
mode or subactive mode
External input signal
Interrupt by different signal
Figure 6.3 External Input Signal Capture when Signal Changes before/after Standby Mode
or Watch Mode
(4) Input Pins to which these Notes Apply
IRQ4, IRQ3, IRQ1, IRQ0, WKP7 to WKP0, IRQAEC, TMIF, ADTRG, TIOCA1, TIOCB1,
TIOCA2 and TIOCB2.
Rev. 1.00, 07/04, page 122 of 570
ROM3560A_000220040500 Rev. 1.00, 07/04, page 123 of 570
Section 7 ROM
The features of the 52-kbyte flash memory built into the flash memory (F-ZTAT) version are
summarized below.
• Programming/erase methods
The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units.
The flash memory is configured as follows: 1 kbyte × 4 blocks, 28 kbytes × 1 block, 16 kbytes
× 1 block, and 4 kbytes × 1 block. To erase the entire flash memory, each block must be erased
in turn.
• On-board programming
On-board programming/erasing can be done in boot mode, in which the boot program built
into the chip is started to erase or program of the entire flash memory. In normal user program
mode, individual blocks can be erased or programmed.
• Programmer mode
Flash memory can be programmed/erased in programmer mode using a PROM programmer,
as well as in on-board programming mode.
• Automatic bit rate adjustment
For data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match the
transfer bit rate of the host.
• Programming/erasing protection
Sets software protection against flash memory programming/erasing.
• Power-down mode
Operation of the power supply circuit can be partly halted in subactive mode. As a result, flash
memory can be read with low power consumption.
• Module standby mode
Use of module standby mode enables this module to be placed in standby mode independently
when not used. (For details, refer to section 6.4, Module Standby Function.)
Rev. 1.00, 07/04, page 124 of 570
7.1 Block Configuration
Figure 7.1 shows the block configuration of flash memory. The thick lines indicate erasing units,
the narrow lines indicate programming units, and the values are addresses. The 52-kbyte flash
memory is divided into 1 kbyte × 4 blocks, 28 kbytes × 1 block, 16 kbytes × 1 block, and 4 kbytes
× 1 block. Erasing is performed in these units. Programming is performed in 128-byte units
starting from an address with lower eight bits H'00 or H'80.
H'007F
H'0000 H'0001 H'0002
H'00FF
H'0080 H'0081 H'0082
H'03FF
H'0380 H'0381 H'0382
H'047F
H'0400 H'0401 H'0402
H'04FF
H'0480 H'0481 H'0482
H'07FF
H'0780 H'0781 H'0782
H'087F
H'0800 H'0801 H'0802
H'08FF
H'0880 H'0881 H'0882
H'0BFF
H'0B80 H'0B81 H'0B82
H'0C7F
H'0C00 H'0C01 H'0C02
H'0CFF
H'0C80 H'0C81 H'0C82
H'0FFF
H'0F80 H'0F81 H'0F82
H'107F
H'1000 H'1001 H'1002
H'10FF
H'1080 H'1081 H'1082
H'7FFF
H'7F80 H'7F81 H'7F82
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
1 kbyte
Erase unit
1 kbyte
Erase unit
1 kbyte
Erase unit
1 kbyte
Erase unit
28 kbytes
Erase unit
H'807F
H'8000 H'8001 H'8002
H'80FF
H'8080 H'8081 H'8082
H'BFFF
H'BF80 H'BF81 H'BF82
H'C07FH'C000 H'C001 H'C002
H'C0FFH'C080 H'C081 H'C082
H'CFFFH'CF80 H'CF81 H'CF82
Programming unit: 128 bytes
16 kbytes
Erase unit
4 kbytes
Erase unit
Figure 7.1 Flash Memory Bl ock Co nfi g u r ation
Rev. 1.00, 07/04, page 125 of 570
7.2 Register Descriptions
The flash memory has the following registers.
• Flash memory control register 1 (FLMCR1)
• Flash memory control register 2 (FLMCR2)
• Erase block register 1 (EBR1)
• Flash memory power control register (FLPWCR)
• Flash memory enable register (FENR)
7.2.1 Flash Memory Control Register 1 (FLMCR1)
FLMCR1 is a register that makes the flash memory change to program mode, program-verify
mode, erase mode, or erase-verify mode. For details on register setting, refer to section 7.4, Flash
Memory Programming/Erasing.
Bit Bit Name
Initial
Value R/W Description
7 0 Reserved
This bit is always read as 0.
6 SWE 0 R/W Software Write Enable
When this bit is set to 1, flash memory
programming/erasing is enabled. When this bit is
cleared to 0, other FLMCR1 register bits and all EBR1
bits cannot be set.
5 ESU 0 R/W Erase Setup
When this bit is set to 1, the flash memory changes to
the erase setup state. When it is cleared to 0, the
erase setup state is cancelled. Set this bit to 1 before
setting the E bit to 1 in FLMCR1.
4 PSU 0 R/W Program Setup
When this bit is set to 1, the flash memory changes to
the program setup state. When it is cleared to 0, the
program setup state is cancelled. Set this bit to 1
before setting the P bit in FLMCR1.
3 EV 0 R/W Erase-Verify
When this bit is set to 1, the flash memory changes to
erase-verify mode. When it is cleared to 0, erase-verify
mode is cancelled.
Rev. 1.00, 07/04, page 126 of 570
Bit Bit Name
Initial
Value R/W Description
2 PV 0 R/W Program-Verify
When this bit is set to 1, the flash memory changes to
program-verify mode. When it is cleared to 0, program-
verify mode is cancelled.
1 E 0 R/W Erase
When this bit is set to 1 while SWE=1 and ESU=1, the
flash memory changes to erase mode. When it is
cleared to 0, erase mode is cancelled.
0 P 0 R/W Program
When this bit is set to 1 while SWE=1 and PSU=1, the
flash memory changes to program mode. When it is
cleared to 0, program mode is cancelled.
7.2.2 Flash Memory Control Register 2 (FLMCR2)
FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a
read-only register, and should not be written to.
Bit Bit Name
Initial
Value R/W Description
7 FLER 0 R Flash Memory Error
Indicates that an error has occurred during an operation
on flash memory (programming or erasing). When
FLER is set to 1, flash memory goes to the error-
protection state.
See section 7.5.3, Error Protection, for details.
6 to 0 All 0 Reserved
These bits are always read as 0.
Rev. 1.00, 07/04, page 127 of 570
7.2.3 E rase Bl ock Register 1 (EBR1 )
EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit
in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to
be automatically cleared to 0.
Bit Bit Name
Initial
Value R/W Description
7 0 Reserved
This bit is always read as 0.
6 EB6 0 R/W When this bit is set to 1, 4 kbytes of H'C000 to H'CFFF
will be erased.
5 EB5 0 R/W When this bit is set to 1, 16 kbytes of H'8000 to H'BFFF
will be erased.
4 EB4 0 R/W When this bit is set to 1, 28 kbytes of H'1000 to H'7FFF
will be erased.
3 EB3 0 R/W When this bit is set to 1, 1 kbyte of H'0C00 to H'0FFF
will be erased.
2 EB2 0 R/W When this bit is set to 1, 1 kbyte of H'0800 to H'0BFF
will be erased.
1 EB1 0 R/W When this bit is set to 1, 1 kbyte of H'0400 to H'07FF
will be erased.
0 EB0 0 R/W When this bit is set to 1, 1 kbyte of H'0000 to H'03FF
will be erased.
Rev. 1.00, 07/04, page 128 of 570
7.2.4 Flash Memory Power Control Register (FLPWCR)
FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI
switches to subactive mode. There are two modes: mode in which operation of the power supply
circuit of flash memory is partly halted in power-down mode and flash memory can be read, and
mode in which even if a transition is made to subactive mode, operation of the power supply
circuit of flash memory is retained and flash memory can be read.
Bit Bit Name
Initial
Value R/W Description
7 PDWND 0 R/W Power-Down Disable
When this bit is 0 and a transition is made to subactive
mode, the flash memory enters the power-down mode.
When this bit is 1, the flash memory remains in the
normal mode even after a transition is made to
subactive mode.
6 to 0 All 0 Reserved
These bits are always read as 0.
7.2.5 Flash Memory En abl e Register (FENR)
Bit 7 (FLSHE) in FENR enables or disables the CPU access to the flash memory control registers,
FLMCR1, FLMCR2, EBR1, and FLPWCR.
Bit Bit Name
Initial
Value R/W Description
7 FLSHE 0 R/W Flash Memory Control Register Enable
Flash memory control registers can be accessed when
this bit is set to 1. Flash memory control registers
cannot be accessed when this bit is set to 0.
6 to 0 All 0 Reserved
These bits are always read as 0.
Rev. 1.00, 07/04, page 129 of 570
7.3 On-Board Programming Modes
There are two modes for programming/erasing of the flash memory; boot mode, which enables on-
board programming/erasing, and programmer mode, in which programming/erasing is performed
with a PROM programmer. On-board programming/erasing can also be performed in user
program mode. At reset-start in reset mode, this LSI changes to a mode depending on the TEST
pin settings, NMI pin settings, and input level of each port, as shown in table 7.1. The input level
of each pin must be defined four states before the reset ends.
When changing to boot mode, the boot program built into this LSI is initiated. The boot program
transfers the programming control program from the externally-connected host to on-chip RAM
via SCI3 (channel 1). After erasing the entire flash memory, the programming control program is
executed. This can be used for programming initial values in the on-board state or for a forcible
return when programming/erasing can no longer be done in user program mode. In user program
mode, individual blocks can be erased and programmed by branching to the user program/erase
control program prepared by the user.
Table 7.1 Setting Programming Modes
TEST NMI P36 PB0 PB1 PB2 LSI State after Reset End
0 1 X X X X User Mode
0 0 1 X X X Boot Mode
1 X X 0 0 0 Programmer Mode
[Legend] X: Don't care.
Rev. 1.00, 07/04, page 130 of 570
7.3.1 Boot Mode
Table 7.2 shows the boot mode operations between reset end and branching to the programming
control program.
1. When boot mode is used, the flash memory programming control program must be prepared in
the host beforehand. Prepare a programming control program in accordance with the
description in section 7.4, Flash Memory Programming/Erasing.
2. SCI3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop
bit, and no parity. The inversion function of TXD and RXD pins by SPCR is set to “Not to be
inverted,” so do not put the circuit for inverting a value between the host and this LSI.
3. When the boot program is initiated, the chip measures the low-level period of asynchronous
SCI communication data (H'00) transmitted continuously from the host. The chip then
calculates the bit rate of transmission from the host, and adjusts the SCI3 bit rate to match that
of the host. The reset should end with the RXD pin high. The RXD and TXD pins should be
pulled up on the board if necessary. After the reset is complete, it takes approximately 100
states before the chip is ready to measure the low-level period.
4. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the
completion of bit rate adjustment. The host should confirm that this adjustment end indication
(H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could
not be performed normally, initiate boot mode again by a reset. Depending on the host's
transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between
the bit rates of the host and the chip. To operate the SCI properly, set the host's transfer bit rate
and system clock frequency of this LSI within the ranges listed in table 7.3.
5. In boot mode, a part of the on-chip RAM area is used by the boot program. The area H'F780 to
H'FEEF is the area to which the programming control program is transferred from the host.
The boot program area cannot be used until the execution state in boot mode switches to the
programming control program.
6. Before branching to the programming control program, the chip terminates transfer operations
by SCI3 (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value
remains set in BRR. Therefore, the programming control program can still use it for transfer of
program data or verify data with the host. The TXD pin is high (PCR42 = 1, P42 = 1). The
contents of the CPU general registers are undefined immediately after branching to the
programming control program. These registers must be initialized at the beginning of the
programming control program, as the stack pointer (SP), in particular, is used implicitly in
subroutine calls, etc.
7. Boot mode can be cleared by a reset. End the reset after driving the reset pin low, waiting at
least 20 states, and then setting the NMI pin. Boot mode is also cleared when a WDT overflow
occurs.
8. Do not change the TEST pin and NMI pin input levels in boot mode.
Rev. 1.00, 07/04, page 131 of 570
Table 7.2 Boot Mode Operation
Communication Contents
Processing Contents
Host Operation LSI Operation
Processing Contents
Continuously transmits data H'00
at specified bit rate.
Branches to boot program at reset-start.
Boot program initiation
H'00, H'00 . . . H'00
H'00
H'55
Transmits data H'55 when data H'00
is received error-free.
H'XX
Transmits number of bytes (N) of
programming control program to be
transferred as 2-byte data
(low-order byte following high-order
byte)
Transmits 1-byte of programming
control program (repeated for N times)
H'AA reception
H'AA reception
Upper bytes, lower bytes
Echoback
Echoback
H'AA
H'AA
Branches to programming control program
transferred to on-chip RAM and starts
execution.
Transmits data H'AA to host.
Checks flash memory data, erases all flash
memory blocks in case of written data
existing, and transmits data H'AA to host.
(If erase could not be done, transmits data
H'FF to host and aborts operation.)
H'FF
Boot program
erase error
Item
Boot mode initiation
• Measures low-level period of receive data
H'00.
• Calculates bit rate and sets BRR in SCI3.
• Transmits data H'00 to host as adjustment
end indication.
H'55 reception.
Bit rate adjustment
Echobacks the 2-byte data
received to host.
Echobacks received data to host and also
transfers it to RAM.
(repeated for N times)
Transfer of number of bytes of
programming control program Flash memory erase
Rev. 1.00, 07/04, page 132 of 570
Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is
Possible
Host Bit Rate System Clock Frequency Range of LSI
9,600 bps 8 to 10 MHz
4,800 bps 4 to 10 MHz
2,400 bps 2 to 10 MHz
7.3.2 Programming/Erasing in User Program Mode
On-board programming/erasing of an individual flash memory block can also be performed in user
program mode by branching to a user program/erase control program. The user must set branching
conditions and provide on-board means of supplying programming data. The flash memory must
contain the user program/erase control program or a program that provides the user program/erase
control program from external memory. As the flash memory itself cannot be read during
programming/erasing, transfer the user program/erase control program to on-chip RAM, as in boot
mode. Figure 7.2 shows a sample procedure for programming/erasing in user program mode.
Prepare a user program/erase control program in accordance with the description in section 7.4,
Flash Memory Programming/Erasing.
Ye s
No
Program/erase?
Transfer user program/erase control
program to RAM
Reset-start
Branch to user program/erase control
program in RAM
Execute user program/erase control
program (flash memory rewrite)
Branch to flash memory application
program
Branch to flash memory application
program
Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode
Rev. 1.00, 07/04, page 133 of 570
7.4 Flash Memory Programming/Erasing
A software method using the CPU is employed to program and erase flash memory in the on-
board programming modes. Depending on the FLMCR1 setting, the flash memory operates in one
of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify
mode. The programming control program in boot mode and the user program/erase control
program in user program mode use these operating modes in combination to perform
programming/erasing. Flash memory programming and erasing should be performed in
accordance with the descriptions in section 7.4.1, Program/Program-Verify and section 7.4.2,
Erase/Erase-Verify, respectively.
7.4.1 Program/Program-Verify
When writing data or programs to the flash memory, the program/program-verify flowchart shown
in figure 7.3 should be followed. Performing programming operations according to this flowchart
will enable data or programs to be written to the flash memory without subjecting the chip to
voltage stress or sacrificing program data reliability.
1. Programming must be done to an empty address. Do not reprogram an address to which
programming has already been performed.
2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be
performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the
extra addresses.
3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128-
byte reprogramming data area, and a 128-byte additional-programming data area. Perform
reprogramming data computation according to table 7.4, and additional programming data
computation according to table 7.5.
4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or
additional-programming data area to the flash memory. The program address and 128-byte
data are latched in the flash memory. The lower 8 bits of the start address in the flash memory
destination area must be H'00 or H'80.
5. The time during which the P bit is set to 1 is the programming time. Table 7.6 shows the
allowable programming times.
6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
An overflow cycle of approximately 6.6 ms is allowed.
7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 2
bits are B'00. Verify data can be read in words or in longwords from the address to which a
dummy write was performed.
8. The maximum number of repetitions of the program/program-verify sequence of the same bit
is 1,000.
Rev. 1.00, 07/04, page 134 of 570
START
End of programming
Note: *The RTS instruction must not be used during the following 1. and 2. periods.
1. A period between 128-byte data programming to flash memory and the P bit clearing
2. A period between dummy writing of H'FF to a verify address and verify data reading
Set SWE bit in FLMCR1
Write pulse application subroutine
Wait 1 µs
Apply Write Pulse
*
End Sub
Set PSU bit in FLMCR1
WDT enable
Disable WDT
Wait 50 µs
Set P bit in FLMCR1
Wait (Wait time=programming time)
Clear P bit in FLMCR1
Wait 5 µs
Clear PSU bit in FLMCR1
Wait 5 µs
n= 1
m= 0
No
No
No Yes
Yes
Yes
Yes
Wait 4 µs
Wait 2 µs
Wait 2 µs
Apply
Write pulse
Set PV bit in FLMCR1
Set block start address as
verify address
H'FF dummy write to verify address
Read verify data
Verify data =
write data?
Reprogram data computation
Additional-programming data computation
Clear PV bit in FLMCR1
Clear SWE bit in FLMCR1
m = 1
m= 0 ?
Increment address
Programming failure
No
Clear SWE bit in FLMCR1
Wait 100 µs
No
Yes
n
≤
6?
No
Yes
n
≤
6 ?
Wait 100 µs
n ≤ 1000 ?
n ← n + 1
Write 128-byte data in RAM reprogram
data area consecutively to flash memory
Store 128-byte program data in program
data area and reprogram data area
Apply Write Pulse
Sub-Routine-Call
128-byte
data verification completed?
Successively write 128-byte data from additional-
programming data area in RAM to flash memory
*
Figure 7.3 Program/Program-Verify Flowchart
Rev. 1.00, 07/04, page 135 of 570
Table 7.4 Reprogram Data Computat i on Tabl e
Program Data Verify Data Reprogram Data Comments
0 0 1 Programming completed
0 1 0 Reprogram bit
1 0 1
1 1 1 Remains in erased state
Table 7.5 Additional-Progr am Data Computation T able
Reprogram Data
Verify Data Additional-Program
Data
Comments
0 0 0 Additional-program bit
0 1 1 No additional programming
1 0 1 No additional programming
1 1 1 No additional programming
Table 7.6 Programming Time
n
(Number of Writes) Programming
Time In Addition al
Programming
Comments
1 to 6 30 10
7 to 1,000 200
Note: Time shown in µs.
Rev. 1.00, 07/04, page 136 of 570
7.4.2 Erase/Erase-Verify
When erasing flash memory, the erase/erase-verify flowchart shown in figure 7.4 should be
followed.
1. Prewriting (setting erase block data to all 0s) is not necessary.
2. Erasing is performed in block units. Make only a single-bit specification in the erase block
register (EBR1). To erase multiple blocks, each block must be erased in turn.
3. The time during which the E bit is set to 1 is the flash memory erase time.
4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. An
overflow cycle of approximately 19.8 ms is allowed.
5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two
bits are B'00. Verify data can be read in longwords from the address to which a dummy write
was performed.
6. If the read data is not erased successfully, set erase mode again, and repeat the erase/erase-
verify sequence as before. The maximum number of repetitions of the erase/erase-verify
sequence is 100.
7.4.3 Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, including the NMI interrupt, are disabled while flash memory is being programmed
or erased, or while the boot program is executing, for the following three reasons:
1. Interrupt during programming/erasing may cause a violation of the programming or erasing
algorithm, with the result that normal operation cannot be assured.
2. If interrupt exception handling starts before the vector address is written or during
programming/erasing, a correct vector cannot be fetched and the CPU malfunctions.
3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be
carried out.
Rev. 1.00, 07/04, page 137 of 570
Erase start
Set EBR1
Enable WDT
Wait 1 µs
Wait 100 µs
SWE bit ← 1
n ← 1
ESU bit ← 1
E bit ← 1
Wait 10 ms
E bit ← 0
Wait 10 µs
ESU bit ← 10
10 µs
Disable WDT
Read verify data
Increment address Verify data + all 1s ?
Last address of block ?
All erase block erased ?
Set block start address as verify address
H'FF dummy write to verify address
Wait 20 µs
Wait 2 µs
EV bit ← 1
Wait 100 µs
End of erasing
Note: * The RTS instruction must not be used during a period between dummy writing of H'FF to a verify address and verify data reading.
SWE bit ← 0
Wait 4 µs
EV bit ← 0
n ≤100 ?
Wait 100 µs
Erase failure
SWE bit ← 0
Wait 4µs
EV bit ← 0
n ← n + 1
Ye s
No
Ye s
Ye s
Ye s
No
No
No
*
Figure 7.4 Erase/Erase-Verify Flowchart
Rev. 1.00, 07/04, page 138 of 570
7.5 Program/Erase Protection
There are three kinds of flash memory program/erase protection; hardware protection, software
protection, and error protection.
7.5.1 Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted because of a transition to reset, subactive mode, subsleep mode, or standby
mode. Flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2),
and erase block register 1 (EBR1) are initialized. In a reset via the RES pin, the reset state is not
entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of
a reset during operation, hold the RES pin low for the RES pulse width specified in the AC
Characteristics section.
7.5.2 Software Protection
Software protection can be implemented against programming/erasing of all flash memory blocks
by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P or E bit
in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase
block register 1 (EBR1), erase protection can be set for individual blocks. When EBR1 is set to
H'00, erase protection is set for all blocks.
7.5.3 Error Protection
In error protection, an error is detected when CPU runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is forcibly aborted. Aborting the program/erase
operation prevents damage to the flash memory due to overprogramming or overerasing.
When the following errors are detected during programming/erasing of flash memory, the FLER
bit in FLMCR2 is set to 1, and the error protection state is entered.
• When the flash memory of the relevant address area is read during programming/erasing
(including vector read and instruction fetch)
• Immediately after exception handling excluding a reset during programming/erasing
• When a SLEEP instruction is executed during programming/erasing
The FLMCR1, FLMCR2, and EBR1 settings are retained, however program mode or erase mode
is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-
entered by re-setting the P or E bit. However, PV and EV bit settings are retained, and a transition
can be made to verify mode. Error protection can be cleared only by a reset.
Rev. 1.00, 07/04, page 139 of 570
7.6 Programmer Mode
In programmer mode, a PROM programmer can be used to perform programming/erasing via a
socket adapter, just as a discrete flash memory. Use a PROM programmer that supports the MCU
device type with the on-chip 64-kbyte flash memory (FZTAT64V5).
7.7 Power-Down States for Flash Memory
In user mode, the flash memory will operate in either of the following states:
• Normal operating mode
The flash memory can be read and written to at high speed.
• Power-down operating mode
The power supply circuit of flash memory can be partly halted. As a result, flash memory can
be read with low power consumption.
• Standby mode
All flash memory circuits are halted.
Table 7.7 shows the correspondence between the operating modes of this LSI and the flash
memory. In subactive mode, the flash memory can be set to operate in power-down mode with the
PDWND bit in FLPWCR. When the flash memory returns to its normal operating state from
power-down mode or standby mode, a period to stabilize operation of the power supply circuits
that were stopped is needed. When the flash memory returns to its normal operating state, bits
STS2 to STS0 in SYSCR1 must be set to provide a wait time of at least 20 µs, even when the
external clock is being used.
Table 7.7 Flash Memory Operating States
Flash Memory Operating State
LSI Operating State PDWND = 0 (Initial Value) PDWND = 1
Active mode Normal operating mode Normal operating mode
Subactive mode Power-down mode Normal operating mode
Sleep mode Normal operating mode Normal operating mode
Subsleep mode Standby mode Standby mode
Standby mode Standby mode Standby mode
Rev. 1.00, 07/04, page 140 of 570
7.8 Notes on Setting Module Standby Mode
When the flash memory is set to enter module standby mode, the system clock supply is stopped
to the module, the function is stopped, and the state is the same as that in standby mode. Also
program operation is stopped in the flash memory. Therefore operation program should be
transferred to the RAM and the program should run in the RAM. Then the flash memory should
be set to enter module standby mode.
Even if an interrupt source occurs while the interrupt is enabled in module standby mode, the
interrupt request is not accepted but the program may run away.
Before the flash memory is set to enter module standby mode, the corresponding bit in the
interrupt enable register should be cleared to 0 and the I bit in CCR should be set to 1. Then after
the flash memory enters module standby mode, NMI and address break interrupt requests should
not be generated. Figure 7.5 shows a module standby mode setting.
Transfer execution program
to RAM (user area)
Clear corresponding bit in
interrupt enable register to 0
Set I bit in CCR to 1
Jump to address of
execution program in RAM
Clear FROMCKSTP
bit in CRSTPR1 to 0
Figure 7.5 Module Standby Mode Setting
RAM0500A_000120030300 Rev. 1.00, 07/04, page 141 of 570
Section 8 RAM
This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit
data bus, enabling two-state access by the CPU to both byte data and word data.
Product Classification RAM Size RAM Address
Flash memory version H8/38086RF 3 kbytes H'F380 to H'FF7F
Masked ROM version H8/38086R 2 kbytes H'F780 to H'FF7F
H8/38085R 2 kbytes H'F780 to H'FF7F
H8/38084R 1 kbyte H'FB80 to H'FF7F
H8/38083R 1 kbyte H'FB80 to H'FF7F
Rev. 1.00, 07/04, page 142 of 570
Rev. 1.00, 07/04, page 143 of 570
Section 9 I/O Ports
The H8/38086R Group has 55 general I/O ports and six general input-only ports. Port 9 is a large
current port, which can drive 15 mA (@VOL = 1.0 V) when a low level signal is output. Any of
these ports can become an input port immediately after a reset. They can also be used as I/O pins
of the on-chip peripheral modules or external interrupt input pins, and these functions can be
switched depending on the register settings. The registers for selecting these functions can be
divided into two types: those included in I/O ports and those included in each on-chip peripheral
module. General I/O ports are comprised of the port control register for controlling inputs/outputs
and the port data register for storing output data and can select inputs/outputs in bit units.
For details on the execution of bit manipulation instructions to the port data register (PDR), see
section 2.8.3, Bit-Manipulation Instruction.
For details on block diagrams for each port, see Appendix B.1, I/O Port Block Diagrams.
9.1 Port 1
Port 1 is an I/O port also functioning as an SCI4 I/O pin, TPU I/O pin, and asynchronous event
counter input pin. Figure 9.1 shows its pin configuration.
P13/TIOCB1/TCLKB
P12/TIOCA1/TCLKA
P11/AEVL
P10/AEVH
P16/SCK4
Port 1
P15/TIOCB2
P14/TIOCA2/TCLKC
Figure 9.1 Port 1 Pin Configuration
Port 1 has the following registers.
• Port data register 1 (PDR1)
• Port control register 1 (PCR1)
• Port pull-up control register 1 (PUCR1)
• Port mode register 1 (PMR1)
Rev. 1.00, 07/04, page 144 of 570
9.1.1 Port Data Register 1 ( PDR1)
PDR1 is a register that stores data of port 1.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
P16
P15
P14
P13
P12
P11
P10
1
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If port 1 is read while PCR1 bits are set to 1, the values
stored in PDR1 are read, regardless of the actual pin
states. If port 1 is read while PCR1 bits are cleared to 0,
the pin states are read.
Bit 7 is reserved. This bit is always read as 1 and cannot
be modified.
9.1.2 Port Control Register 1 (PCR1)
PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
PCR16
PCR15
PCR14
PCR13
PCR12
PCR11
PCR10
1
0
0
0
0
0
0
0
W
W
W
W
W
W
W
Setting a PCR1 bit to 1 makes the corresponding pin
(P16 to P10) an output pin, while clearing the bit to 0
makes the pin an input pin. The settings in PCR1 and in
PDR1 are valid when the corresponding pin is
designated as a general I/O pin.
PCR1 is a write-only register. These bits are always
read as 1.
Bit 7 is reserved. This bit cannot be modified.
Rev. 1.00, 07/04, page 145 of 570
9.1.3 Port Pull-Up Control Register 1 (PUCR1)
PUCR1 controls the pull-up MOS of the port 1 pins in bit units.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
PUCR16
PUCR15
PUCR14
PUCR13
PUCR12
PUCR11
PUCR10
1
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
When a PCR1 bit is cleared to 0, setting the
corresponding PUCR1 bit to 1 turns on the pull-up MOS
for the corresponding pin, while clearing the bit to 0
turns off the pull-up MOS.
Bit 7 is reserved. This bit is always read as 1 and
cannot be modified.
9.1.4 Port Mode Register 1 (PMR1)
PMR1 controls the selection of functions for port 1 pins.
Bit Bit Name
Initial
Value R/W Description
7 to 2 All 1 Reserved
These bits are always read as 1 and cannot be modified.
1 AEVL 0 R/W P11/AEVL Pin Function Switch
Selects whether pin P11/AEVL is used as P11 or as
AEVL.
0: P11 I/O pin
1: AEVL input pin
0 AEVH 0 R/W P10/AEVH Pin Function Switch
Selects whether pin P10/AEVH is used as P10 or as
AEVH.
0: P10 I/O pin
1: AEVH input pin
Rev. 1.00, 07/04, page 146 of 570
9.1.5 Pin Functions
The relationship between the register settings and the port functions is shown below.
P16/SCK4 pin
The pin function is switched as shown below according to the combination of the CKS3 to CKS0
bits in SCSR4 and PCR16 bit in PCR1.
CKS3*1 1*1 0*1
CKS2 to CKS0*1 Other than B'111*1 B'111*1 x*1
PCR16 0 1 x x
Pin Function P16 input pin P16 output pin SCK4 input pin*2 SCK4 output pin*2
[Legend] x: Don't care.
Notes: 1. Supported only by the F-ZTATTM version.
2. Only port function is available for the masked ROM version.
P15/TIOCB2 pin
The pin function is switched as shown below according to the combination of the TPU channel 2
setting by the MD1 and MD0 bits in TMDR_2, IOB3 to IOB0 bits in TIOR_2, and CCLR1 and
CCLR0 bits in TCR_2, and the PCR15 bit in PCR1.
TPU Channel 2
Setting
Next table (1) Next table (2)
PCR15 0 1
P15 input pin P15 output pin Pin Function TIOCB2 output pin
TIOCB2 input pin*
Note: * When the MD1 and MD0 bits are set to B'00 and the IOB3 bit to 1, the pin function
becomes the TIOCB2 input pin.
TPU Channel 2
Setting
(2) (1) (2) (2) (1) (2)
MD1, MD0 B'00 B'10 B'11
IOB3 to IOB0 B'0000
B'0100
B'1xxx
B'0001 to
B'0011
B'0101 to
B'0111
B'xx00 Other than B'xx00
CCLR1, CCLR0 B'10 B'10
Output Function Output
compare
output
PWM
mode 2
output
[Legend] x: Don't care.
Rev. 1.00, 07/04, page 147 of 570
P14/TIOCA2/TCLKC pin
The pin function is switched as shown below according to the combination of the TPU channel 2
setting by the MD1 and MD0 bits in TMDR_2, IOA3 to IOA0 bits in TIOR_2, and CCLR1 and
CCLR0 bits in TCR_2, the TPSC2 to TPSC0 bits in TCR_2, and the PCR14 bit in PCR1.
TPU Channel 2
Setting
Next table (1) Next table (2)
PCR14 0 1
P14 input pin P14 output pin TIOCA2 output pin
TIOCA2 input pin*1
Pin Function
TCLKC input pin*2
Notes: 1. When the MD1 and MD0 bits are set to B'00 and the IOA3 bit to 1, the pin function
becomes the TIOCA2 input pin.
2. When the TPSC2 to TPSC0 bits in TCR_2 are set to B'110, the pin function becomes
the TCLKC input pin.
TPU Channel 2
Setting
(2) (1) (2) (1) (1) (2)
MD1, MD0 B'00 B'1x B'11
IOA3 to IOA0 B'0000
B'0100
B'1xxx
B'0001 to
B'0011
B'0101 to
B'0111
B'xx00 Other than
B'xx00
Other than B'xx00
CCLR1, CCLR0 Other than
B'10
B'10
Output Function Output
compare
output
PWM mode
1* output
PWM mode
2 output
[Legend] x: Don't care.
Note: * The output of the TIOCB2 pin is disabled.
Rev. 1.00, 07/04, page 148 of 570
P13/TIOCB1/TCLKB pin
The pin function is switched as shown below according to the combination of the TPU channel 1
setting by the MD1 and MD0 bits in TMDR_1, IOB3 to IOB0 bits in TIOR_1, and CCLR1 and
CCLR0 bits in TCR_1, the TPSC2 to TPSC0 bits in TCR_1 and TCR_2, and the PCR13 bit in
PCR1.
TPU Channel 1
Setting
Next table (1) Next table (2)
PCR13 0 1
P13 input pin P13 output pin TIOCB1 output pin
TIOCB1 input pin*1
Pin Function
TCLKB input pin*2
Notes: 1. When the MD1 and MD0 bits are set to B'00 and the IOB3 bit to 1, the pin function
becomes the TIOCB1 input pin.
2. When the TPSC2 to TPSC0 bits in TCR_1 or TCR_2 are set to B'101, the pin function
becomes the TCLKB input pin.
TPU Channel 1
Setting
(2) (1) (2) (2) (1) (2)
MD1, MD0 B'00 B'10 B'11
IOB3 to IOB0 B'0000
B'0100
B'1xxx
B'0001 to
B'0011
B'0101 to
B'0111
B'xx00 Other than B'xx00
CCLR1, CCLR0 Other than
B'10
B'10
Output Function Output
compare
output
PWM mode
2 output
[Legend] x: Don't care.
Rev. 1.00, 07/04, page 149 of 570
P12/TIOCA1/TCLKA pin
The pin function is switched as shown below according to the combination of the TPU channel 1
setting by the MD1 and MD0 bits in TMDR_1, IOA3 to IOA0 bits in TIOR_1, and CCLR1 and
CCLR0 bits in TCR_1, the TPSC2 to TPSC0 bits in TCR_1 and TCR_2, and the PCR12 bit in
PCR1.
TPU Channel 1
Setting
Next table (1) Next table (2)
PCR12 0 1
P12 input pin P12 output pin TIOCA1 output pin
TIOCA1 input pin*1
Pin Function
TCLKA input pin*2
Notes: 1. When the MD1 and MD0 bits are set to B'00 and the IOA3 bit to 1, the pin function
becomes the TIOCA1 input pin.
2. When the TPSC2 to TPSC0 bits in TCR_1 or TCR_2 are set to B'100, the pin function
becomes the TCLKA input pin.
TPU Channel 1
Setting
(2) (1) (2) (1) (1) (2)
MD1, MD0 B'00 B'1x B'10 B'11
IOA3 to IOA0 B'0000
B'0100
B'1xxx
B'0001 to
B'0011
B'0101 to
B'0111
B'xx00 Other than
B'xx00
Other than B'xx00
CCLR1, CCLR0 Other than
B'10
B'10
Output Function Output
compare
output
PWM
mode 1*
output
PWM mode
2 output
[Legend] x: Don't care.
Note: * The output of the TIOCB1 pin is disabled.
P11/AEVL pin
The pin function is switched as shown below according to the combination of the AEVL bit in
PMR1 and PCR11 bit in PCR.
AEVL 0 1
PCR11 0 1 x
Pin Function P11 input pin P11 output pin AEVL input pin
[Legend] x: Don't care.
Rev. 1.00, 07/04, page 150 of 570
P10/AEVH pin
The pin function is switched as shown below according to the combination of the AEVH bit in
PMR1 and PCR10 bit in PCR.
AEVH 0 1
PCR10 0 1 x
Pin Function P10 input pin P10 output pin AEVH input pin
[Legend] x: Don't care.
9.1.6 Input Pull-Up MOS
Port 1 has an on-chip input pull-up MOS function that can be controlled by software. When a
PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the input pull-up MOS
for that pin. The input pull-up MOS function is in the off state after a reset.
(n = 6 to 0)
PCR1n 0 1
PUCR1n 0 1 x
Input Pull-Up MOS Off On Off
[Legend] x: Don't care.
Rev. 1.00, 07/04, page 151 of 570
9.2 Port 3
Port 3 is an I/O port also functioning as an SCI4 I/O pin, SCI3_2 I/O pin, IIC2 I/O pin, and RTC
output pin. Figure 9.2 shows its pin configuration.
P32/TXD32/SCL
P31/RXD32/SDA
P30/SCK32/TMOW
P37/SO4
Port 3
P36/SI4
Figure 9.2 Port 3 Pin Configuration
Port 3 has the following registers.
• Port data register 3 (PDR3)
• Port control register 3 (PCR3)
• Port pull-up control register 3 (PUCR3)
• Port mode register 3 (PMR3)
9.2.1 Port Data Register 3 ( PDR3)
PDR3 is a register that stores data of port 3.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
P37
P36
P32
P31
P30
0
0
1
1
1
0
0
0
R/W
R/W
R/W
R/W
R/W
If port 3 is read while PCR3 bits are set to 1, the values
stored in PDR3 are read, regardless of the actual pin
states. If port 3 is read while PCR3 bits are cleared to 0,
the pin states are read.
Bits 5 to 3 are reserved. These bits are always read as 1
and cannot be modified.
Rev. 1.00, 07/04, page 152 of 570
9.2.2 Port Control Register 3 (PCR3)
PCR3 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 3.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
PCR37
PCR36
PCR32
PCR31
PCR30
0
0
1
1
1
0
0
0
W
W
W
W
W
Setting a PCR3 bit to 1 makes the corresponding pin
(P37, P36, P32 to P30) an output pin, while clearing the
bit to 0 makes the pin an input pin. The settings in PCR3
and in PDR3 are valid when the corresponding pin is
designated as a general I/O pin.
PCR3 is a write-only register. These bits are always
read as 1.
Bits 5 to 3 are reserved. These bits cannot be modified.
9.2.3 Port Pull-Up Control Register 3 (PUCR3)
PUCR3 controls the pull-up MOS of the port 3 pins in bit units.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
PUCR37
PUCR36
PUCR30
0
0
1
1
1
1
1
0
R/W
R/W
R/W
When a PCR3 bit is cleared to 0, setting the
corresponding PUCR3 bit to 1 turns on the pull-up MOS
for the corresponding pin, while clearing the bit to 0
turns off the pull-up MOS.
Bits 5 to 1 are reserved. These bits are always read as 1
and cannot be modified.
Rev. 1.00, 07/04, page 153 of 570
9.2.4 Port Mode Register 3 (PMR3)
PMR3 controls the selection of functions for port 3 pins.
Bit Bit Name
Initial
Value R/W Description
7 to 1 All 1 Reserved
These bits are always read as 1 and cannot be modified.
0 TMOW 0 R/W P30/SCK32/TMOW Pin Function Switch
Selects whether pin P30/SCK32/TMOW is used as
P30/SCK32 or as TMOW.
0: P30/SCK32 I/O pin
1: TMOW output pin
9.2.5 Pin Functions
The relationship between the register settings and the port functions is shown below.
P37/SO4 pin
The pin function is switched as shown below according to the combination of the TE bit in SCR4
and PCR37 bit in PCR3.
TE*1 0*1 1*1
PCR37 0 1 x
Pin Function P37 input pin P37 output pin SO4 output pin*2
[Legend] x: Don't care.
Notes: 1. Supported only by the F-ZTATTM version.
2. Only port function is available for the masked ROM version.
P36/SI4 pin
The pin function is switched as shown below according to the combination of the RE bit in SCR4
and PCR36 bit in PCR3.
RE*1 0*1 1*1
PCR36 0 1 x
Pin Function P36 input pin P36 output pin SI4 input pin*2
[Legend] x: Don't care.
Notes: 1. Supported only by the F-ZTATTM version.
2. Only port function is available for the masked ROM version.
Rev. 1.00, 07/04, page 154 of 570
P32/TXD32/SCL pin
The pin function is switched as shown below according to the combination of the PCR32 bit in
PCR3, ICE bit in ICRR1, TE32 bit in SCR32, and SPC32 bit in SPCR.
ICE 0 1
SPC32 0 1 0
TE32 0 1 0
PCR32 0 1 x x
Pin Function P32 input pin P32 output pin TXD32 output pin SCL output pin
[Legend] x: Don't care.
P31/RXD32/SDA pin
The pin function is switched as shown below according to the combination of the PCR31 bit in
PCR3, ICE bit in ICCR1, and RE32 bit in SCR32.
ICE 0 1
RE32 0 1 0
PCR31 0 1 x x
Pin Function P31 input pin P31 output pin RXD32 input pin SDA I/O pin
[Legend] x: Don't care.
P30/SCK32/TMOW pin
The pin function is switched as shown below according to the combination of the TMOW bit in
PMR3, PCR30 bit in PCR3, CKE321 and CKE320 bits in SCR32, and COM32 bit in SMR32.
TMOW 0 1
CKE321 0 1 x
CKE320 0 1 x x
COM32 0 1 x x x
PCR30 0 1 x x x
Pin Function P30 input
pin
P30 output
pin
SCK32 output pin SCK32 input pin TMOW output
pin
[Legend] x: Don't care.
Rev. 1.00, 07/04, page 155 of 570
9.2.6 Input Pull-Up MOS
Port 3 has an on-chip input pull-up MOS function that can be controlled by software. When a
PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the input pull-up MOS
for that pin. The input pull-up MOS function is in the off state after a reset.
(n = 7, 6, 0)
PCR3n 0 1
PUCR3n 0 1 x
Input Pull-Up MOS Off On Off
[Legend] x: Don't care.
9.3 Port 4
Port 4 is an I/O port also functioning as an SCI3_1 data I/O pin and timer F I/O pin. Figure 9.3
shows its pin configuration.
P42/TXD31/IrTXD/TMOFH
Port 4
P41/RXD31/IrRXD/TMOFL
P40/SCK31/TMIF
Figure 9.3 Port 4 Pin Configuration
Port 4 has the following registers.
• Port data register 4 (PDR4)
• Port control register 4 (PCR4)
• Port mode register 4 (PMR4)
Rev. 1.00, 07/04, page 156 of 570
9.3.1 Port Data Register 4 ( PDR4)
PDR4 is a register that stores data of port 4.
Bit Bit Name
Initial
Value R/W Description
7 to 3 All 1 Reserved
These bits are always read as 1 and cannot be modified.
2
1
0
P42
P41
P40
0
0
0
R/W
R/W
R/W
If port 4 is read while PCR4 bits are set to 1, the values
stored in PDR4 are read, regardless of the actual pin
states. If port 4 is read while PCR4 bits are cleared to 0,
the pin states are read.
9.3.2 Port Control Register 4 (PCR4)
PCR4 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 4.
Bit Bit Name
Initial
Value R/W Description
7 to 3 All 1 Reserved
These bits are always read as 1 and cannot be modified.
2
1
0
PCR42
PCR41
PCR40
0
0
0
W
W
W
Setting a PCR4 bit to 1 makes the corresponding pin an
output pin, while clearing the bit to 0 makes the pin an
input pin. The settings in PCR4 and in PDR4 are valid
when the corresponding pin is designated as a general
I/O pin.
PCR4 is a write-only register. These bits are always
read as 1.
Rev. 1.00, 07/04, page 157 of 570
9.3.3 Port Mode Register 4 (PMR4)
PMR4 controls the selection of functions for port 4 pins.
Bit Bit Name
Initial
Value R/W Description
7 to 3 All 1 Reserved
These bits are always read as 1 and cannot be modified.
2 TMOFH 0 R/W P42/TXD31/IrTXD/TMOFH Pin Function Switch
Selects whether pin P42/TXD31/IrTXD/TMOFH is used
as P42 or TXD31/IrTXD, or as TMOFH.
0: P42 I/O pin or TXD31/IrTXD output pin
1: TMOFH output pin
1 TMOFL 0 R/W P41/RXD31/IrRXD/TMOFL Pin Function Switch
Selects whether pin P41/RXD31/IrRXD/TMOFL is used
as P41 or RXD31/IrRXD, or as TMOFL.
0: P41 I/O pin or RXD31/IrRXD input pin
1: TMOFL output pin
0 TMIF 0 R/W P40/SCK31/TMIF Pin Function Switch
Selects whether pin P40/SCK31/TMIF is used as
P40/SCK31 or as TMIF.
0: P40/SCK31 I/O pin
1: TMIF output pin
9.3.4 Pin Functions
The relationship between the register settings and the port functions is shown below.
P42/TXD31/IrTXD/TMOFH pin
The pin function is switched as shown below according to the combination of the TMOFH bit in
PMR4, PCR42 bit in PCR4, IrE bit in IrCR, TE bit in SCR3, and SPC31 bit in SPCR.
TMOFH 0 1
SPC31 0 1 0
TE 0 1 0
IrE x 0 1 x
PCR42 0 1 x x x
Pin Function P42 input pin P42 output pin TXD31 output
pin
IrTXD output
pin
TMOFH
output pin
[Legend] x: Don't care.
Rev. 1.00, 07/04, page 158 of 570
P41/RXD31/IrRXD/TMOFL pin
The pin function is switched as shown below according to the combination of the TMOFL bit in
PMR4, PCR41 bit in PCR4, IrE bit in IrCR, and RE bit in SCR3.
TMOFL 0 1
RE 0 1 x
IrE x 0 1 x
PCR41 0 1 x x x
Pin Function P41 input pin P41 output
pin
RXD31 input
pin
IrRXD input
pin
TMOFL output
pin
[Legend] x: Don't care.
P40/SCK31/TMIF pin
The pin function is switched as shown below according to the combination of the TMIF bit in
PMR4, PCR40 bit in PCR4, CKE1 and CKE0 bits in SCR3, and COM bit in SMR3.
TMIF 0 1
CKE1 0 1 0
CKE0 0 1 0 x
COM 0 1 x x x
PCR40 0 1 x x x
Pin Function P40 input pin P40 output
pin
SCK31 output
pin
SCK31 input
pin
TMIF input pin
[Legend] x: Don't care.
Rev. 1.00, 07/04, page 159 of 570
9.4 Port 5
Port 5 is an I/O port also functioning as a wakeup interrupt input pin and LCD segment output pin.
Figure 9.4 shows its pin configuration.
P55/WKP5/SEG6
P56/WKP6/SEG7
P57/WKP7/SEG8
Port 5
P50/WKP0/SEG1
P54/WKP4/SEG5
P53/WKP3/SEG4
P52/WKP2/SEG3
P51/WKP1/SEG2
Figure 9.4 Port 5 Pin Configuration
Port 5 has the following registers.
• Port data register 5 (PDR5)
• Port control register 5 (PCR5)
• Port pull-up control register 5 (PUCR5)
• Port mode register 5 (PMR5)
9.4.1 Port Data Register 5 ( PDR5)
PDR5 is a register that stores data of port 5.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
P57
P56
P55
P54
P53
P52
P51
P50
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If port 5 is read while PCR5 bits are set to 1, the values
stored in PDR5 are read, regardless of the actual pin
states. If port 5 is read while PCR5 bits are cleared to 0,
the pin states are read.
Rev. 1.00, 07/04, page 160 of 570
9.4.2 Port Control Register 5 (PCR5)
PCR5 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 5.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
PCR57
PCR56
PCR55
PCR54
PCR53
PCR52
PCR51
PCR50
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Setting a PCR5 bit to 1 makes the corresponding pin an
output pin, while clearing the bit to 0 makes the pin an
input pin. The settings in PCR5 and in PDR5 are valid
when the corresponding pin is designated as a general
I/O pin.
PCR5 is a write-only register. These bits are always
read as 1.
9.4.3 Port Pull-Up Control Register 5 (PUCR5)
PUCR5 controls the pull-up MOS of the port 5 pins in bit units.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
PUCR57
PUCR56
PUCR55
PUCR54
PUCR53
PUCR52
PUCR51
PUCR50
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
When a PCR5 bit is cleared to 0, setting the
corresponding PUCR5 bit to 1 turns on the pull-up MOS
for the corresponding pin, while clearing the bit to 0
turns off the pull-up MOS.
Rev. 1.00, 07/04, page 161 of 570
9.4.4 Port Mode Register 5 (PMR5)
PMR5 controls the selection of functions for port 5 pins.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
WKP7
WKP6
WKP5
WKP4
WKP3
WKP2
WKP1
WKP0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P5n/WKPn/SEGn+1 Pin Function Switch
When pin P5n/WKPn/SEGn+1 is not used as SEGn+1,
these bits select whether the pin is used as P5n or
WKPn.
0: P5n I/O pin
1: WKPn input pin
(n = 7 to 0)
Note: For use as SEGn+1, see section 20.3.1, LCD Port Control Register (LPCR).
9.4.5 Pin Functions
The relationship between the register settings and the port functions is shown below.
P57/WKP7/SE G 8 t o P 54/WKP4/SEG5 pins
The pin function is switched as shown below according to the combination of the WKPn bit in
PMR5, PCR5n bit in PCR5, and SGS3 to SGS0 bits in LPCR.
(n = 7 to 4)
SGS3 to SGS0
Other than B'0010, B'0011, B'0100,
B'0101, B'0110, B'0111, B'1000, B'1001
B'0010, B'0011, B'0100, B'0101,
B'0110, B'0111, B'1000, B'1001
WKPn 0 1 x
PCR5n 0 1 x x
Pin Function P5n input
pin
P5n output
pin
WKPn input
pin
SEGn+1 output pin
[Legend] x: Don't care.
Rev. 1.00, 07/04, page 162 of 570
P53/WKP3/SE G 4 t o P 50/WKP0/SEG1 pins
The pin function is switched as shown below according to the combination of the WKPm bit in
PMR5, PCR5m bit in PCR5, and SGS3 to SGS0 bits in LPCR.
(m = 3 to 0)
SGS3 to SGS0 Other than B'0001, B'0010, B'0011,
B'0100, B'0101, B'0110, B'0111, B'1000
B'0001, B'0010, B'0011, B'0100,
B'0101, B'0110, B'0111, B'1000
WKPm 0 1 x
PCR5m 0 1 x x
Pin Function P5m input
pin
P5m output
pin
WKPm input
pin
SEGm+1 output pin
[Legend] x: Don't care.
9.4.6 Input Pull-Up MOS
Port 5 has an on-chip input pull-up MOS function that can be controlled by software. When the
PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the input pull-up MOS
for that pin. The input pull-up MOS function is in the off state after a reset.
(n = 7 to 0)
PCR5n 0 1
PUCR5n 0 1 x
Input Pull-Up MOS Off On Off
[Legend] x: Don't care.
Rev. 1.00, 07/04, page 163 of 570
9.5 Port 6
Port 6 is an I/O port also functioning as an LCD segment output pin. Figure 9.5 shows its pin
configuration.
P63/SEG12
P62/SEG11
P65/SEG14
P67/SEG16
Port 6
P66/SEG15
P64/SEG13
P61/SEG10
P60/SEG9
Figure 9.5 Port 6 Pin Configuration
Port 6 has the following registers.
• Port data register 6 (PDR6)
• Port control register 6 (PCR6)
• Port pull-up control register 6 (PUCR6)
9.5.1 Port Data Register 6 ( PDR6)
PDR6 is a register that stores data of port 6.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
P67
P66
P65
P64
P63
P62
P61
P60
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If port 6 is read while PCR6 bits are set to 1, the values
stored in PDR6 are read, regardless of the actual pin
states. If port 6 is read while PCR6 bits are cleared to 0,
the pin states are read.
Rev. 1.00, 07/04, page 164 of 570
9.5.2 Port Control Register 6 (PCR6)
PCR6 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 6.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
PCR67
PCR66
PCR65
PCR64
PCR63
PCR62
PCR61
PCR60
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Setting a PCR6 bit to 1 makes the corresponding pin an
output pin, while clearing the bit to 0 makes the pin an
input pin. The settings in PCR6 and in PDR6 are valid
when the corresponding pin is designated as a general
I/O pin.
PCR6 is a write-only register. These bits are always
read as 1.
9.5.3 Port Pull-Up Control Register 6 (PUCR6)
PUCR6 controls the pull-up MOS of the port 6 pins in bit units.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
PUCR67
PUCR66
PUCR65
PUCR64
PUCR63
PUCR62
PUCR61
PUCR60
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
When a PCR6 bit is cleared to 0, setting the
corresponding PUCR6 bit to 1 turns on the pull-up MOS
for the corresponding pin, while clearing the bit to 0
turns off the pull-up MOS.
Rev. 1.00, 07/04, page 165 of 570
9.5.4 Pin Functions
The relationship between the register settings and the port functions is shown below.
P67/SEG16 to P64/SEG13 pins
The pin function is switched as shown below according to the combination of the PCR6n bit in
PCR6 and SGS3 to SGS0 bits in LPCR.
(n = 7 to 4)
SGS3 to SGS0
Other than B'0100, B'0101, B'0110,
B'0111, B'1000, B'1001, B'1010, B'1011
B'0100, B'0101, B'0110, B'0111,
B'1000, B'1001, B'1010, B'1011
PCR6n 0 1 x
Pin Function P6n input pin P6n output pin SEGn+9 output pin
[Legend] x: Don't care.
P63/SEG12 to P60/SEG9 pins
The pin function is switched as shown below according to the combination of the PCR6m bit in
PCR6 and SGS3 to SGS0 bits in LPCR.
(m = 3 to 0)
SGS3 to SGS0
Other than B'0011, B'0100, B'0101,
B'0110, B'0111, B'1000, B'1001, B'1010
B'0011, B'0100, B'0101, B'0110,
B'0111, B'1000, B'1001, B'1010
PCR6m 0 1 x
Pin Function P6m input pin P6m output pin SEGm+9 output pin
[Legend] x: Don't care.
9.5.5 Input Pull-Up MOS
Port 6 has an on-chip input pull-up MOS function that can be controlled by software. When the
PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the input pull-up MOS
for that pin. The input pull-up MOS function is in the off state after a reset.
(n = 7 to 0)
PCR6n 0 1
PUCR6n 0 1 x
Input Pull-Up MOS Off On Off
[Legend] x: Don't care.
Rev. 1.00, 07/04, page 166 of 570
9.6 Port 7
Port 7 is an I/O port also functioning as an LCD segment output pin. Figure 9.6 shows its pin
configuration.
P75/SEG22
P76/SEG23
P77/SEG24
Port 7
P70/SEG17
P74/SEG21
P73/SEG20
P72/SEG19
P71/SEG18
Figure 9.6 Port 7 Pin Configuration
Port 7 has the following registers.
• Port data register 7 (PDR7)
• Port control register 7 (PCR7)
9.6.1 Port Data Register 7 ( PDR7)
PDR7 is a register that stores data of port 7.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
P77
P76
P75
P74
P73
P72
P71
P70
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If port 7 is read while PCR7 bits are set to 1, the values
stored in PDR7 are read, regardless of the actual pin
states. If port 7 is read while PCR7 bits are cleared to 0,
the pin states are read.
Rev. 1.00, 07/04, page 167 of 570
9.6.2 Port Control Register 7 (PCR7)
PCR7 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 7.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
PCR77
PCR76
PCR75
PCR74
PCR73
PCR72
PCR71
PCR70
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Setting a PCR7 bit to 1 makes the corresponding pin an
output pin, while clearing the bit to 0 makes the pin an
input pin. The settings in PCR7 and in PDR7 are valid
when the corresponding pin is designated as a general
I/O pin.
PCR7 is a write-only register. These bits are always
read as 1.
9.6.3 Pin Functions
The relationship between the register settings and the port functions is shown below.
P77/SEG24 to P74/SEG21 pins
The pin function is switched as shown below according to the combination of the PCR7n bit in
PCR7 and SGS3 to SGS0 bits in LPCR.
(n = 7 to 4)
SGS3 to SGS0
Other than B'0110, B'0111, B'1000,
B'1001, B'1010, B'1011, B'1100, B'1101
B'0110, B'0111, B'1000, B'1001,
B'1010, B'1011, B'1100, B'1101
PCR7n 0 1 x
Pin Function P7n input pin P7n output pin SEGn+17 output pin
[Legend] x: Don't care.
P73/SEG20 to P70/SEG17 pins
The pin function is switched as shown below according to the combination of the PCR7m bit in
PCR7 and SGS3 to SGS0 bits in LPCR.
(m = 3 to 0)
SGS3 to SGS0
Other than B'0101, B'0110, B'0111,
B'1000, B'1001, B'1010, B'1011, B'1100
B'0101, B'0110, B'0111, B'1000,
B'1001, B'1010, B'1011, B'1100
PCR7m 0 1 x
Pin Function P7m input pin P7m output pin SEGm+17 output pin
[Legend] x: Don't care.
Rev. 1.00, 07/04, page 168 of 570
9.7 Port 8
Port 8 is an I/O port also functioning as an LCD segment output pin. Figure 9.7 shows its pin
configuration.
P87/SEG32
Port 8
P86/SEG31
P85/SEG30
P84/SEG29
P83/SEG28
P82/SEG27
P81/SEG26
P80/SEG25
Figure 9.7 Port 8 Pin Configuration
Port 8 has the following registers.
• Port data register 8 (PDR8)
• Port control register 8 (PCR8)
9.7.1 Port Data Register 8 ( PDR8)
PDR8 is a register that stores data of port 8.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
P87
P86
P85
P84
P83
P82
P81
P80
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If port 8 is read while PCR8 bits are set to 1, the values
stored in PDR8 are read, regardless of the actual pin
states. If port 8 is read while PCR8 bits are cleared to 0,
the pin states are read.
Rev. 1.00, 07/04, page 169 of 570
9.7.2 Port Control Register 8 (PCR8)
PCR8 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 8.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
PCR87
PCR86
PCR85
PCR84
PCR83
PCR82
PCR81
PCR80
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Setting a PCR8 bit to 1 makes the corresponding pin
(P87 to P80) an output pin, while clearing the bit to 0
makes the pin an input pin. The settings in PCR8 and in
PDR8 are valid when the corresponding pin is
designated as a general I/O pin.
PCR8 is a write-only register. These bits are always
read as 1.
9.7.3 Pin Functions
The relationship between the register settings and the port functions is shown below.
P87/SEG32 to P84/SEG29 pins
The pin function is switched as shown below according to the combination of the PCR8n bit in
PCR8 and SGS3 to SGS0 bits in LPCR.
(n = 7 to 4)
SGS3 to SGS0
Other than B'1000, B'1001, B'1010,
B'1011, B'1100, B'1101, B'1110, B'1111
B'1000, B'1001, B'1010, B'1011,
B'1100, B'1101, B'1110, B'1111
PCR8n 0 1 x
Pin Function P8n input pin P8n output pin SEGn+25 output pin
[Legend] x: Don't care.
P83/SEG28 to P80/SEG25 pins
The pin function is switched as shown below according to the combination of the PCR8m bit in
PCR8 and SGS3 to SGS0 bits in LPCR.
(m = 3 to 0)
SGS3 to SGS0
Other than B'0111, B'1000, B'1001,
B'1010, B'1011, B'1100, B'1101, B'1110
B'0111, B'1000, B'1001, B'1010,
B'1011, B'1100, B'1101, B'1110
PCR8m 0 1 x
Pin Function P8m input pin P8m output pin SEGm+25 output pin
[Legend] x: Don't care.
Rev. 1.00, 07/04, page 170 of 570
9.8 Port 9
Port 9 is an I/O port also functioning as an external interrupt input pin and PWM output pin.
Figure 9.8 shows its pin configuration.
P93
Port 9
P92/IRQ4
P91/PWM2
P90/PWM1
Figure 9.8 Port 9 Pin Configuration
Port 9 has the following registers.
• Port data register 9 (PDR9)
• Port control register 9 (PCR9)
• Port mode register 9 (PMR9)
9.8.1 Port Data Register 9 ( PDR9)
PDR9 is a register that stores data of port 9.
Bit Bit Name
Initial
Value R/W Description
7 to 4 All 1
Reserved
These bits are always read as 1 and cannot be modified.
3
2
1
0
P93
P92
P91
P90
1
1
1
1
R/W
R/W
R/W
R/W
If port 9 is read while PCR9 bits are set to 1, the values
stored in PDR9 are read, regardless of the actual pin
states. If port 9 is read while PCR9 bits are cleared to 0,
the pin states are read.
Rev. 1.00, 07/04, page 171 of 570
9.8.2 Port Control Register 9 (PCR9)
PCR9 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 9.
Bit Bit Name
Initial
Value R/W Description
7 to 4 All 1 Reserved
These bits are always read as 1 and cannot be modified.
3
2
1
0
PCR93
PCR92
PCR91
PCR90
0
0
0
0
W
W
W
W
Setting a PCR9 bit to 1 makes the corresponding pin an
output pin, while clearing the bit to 0 makes the pin an
input pin. The settings in PCR9 and in PDR9 are valid
when the corresponding pin is designated as a general
I/O pin.
PCR9 is a write-only register. These bits are always
read as 1.
9.8.3 Port Mode Register 9 (PMR9)
PMR9 controls the selection of functions for port 9 pins.
Bit Bit Name
Initial
Value R/W Description
7 to 4 All 1 Reserved
These bits are always read as 1 and cannot be modified.
3 0 R/W Reserved
Although this bit is readable/writable, 1 should not be
written to this bit.
2 IRQ4 0 R/W P92/IRQ4 Pin Function Switch
Selects whether pin P92/IRQ4 is used as P92 or as
IRQ4.
0: P92 I/O pin
1: IRQ4 input pin
1
0
PWM2
PWM1
0
0
R/W
R/W
P9n/PWMn+1 Pin Function Switch
Select whether pin P9n/PWMn+1 is used as P9n or as
PWMn+1. (n = 1, 0)
0: P9n I/O pin
1: PWMn+1 output pin
Rev. 1.00, 07/04, page 172 of 570
9.8.4 Pin Functions
The relationship between the register settings and the port functions is shown below.
P93 pin
The pin function is switched as shown below according to the PCR93 bit in PCR9.
PCR93 0 1
Pin Function P93 input pin P93 output pin
P92/IRQ4 pin
The pin function is switched as shown below according to the combination of the IRQ4 bit in
PMR9 and PCR92 bit in PCR9.
IRQ4 0 1
PCR92 0 1 x
Pin Function P92 input pin P92 output pin IRQ4 input pin
[Legend] x: Don't care.
P91/PWM2, P90/PWM1 pins
The pin function is switched as shown below according to the combination of the PWMn+1 bit in
PMR9 and PCR9n bit in PCR9.
(n = 1, 0)
PWMn+1 0 1
PCR9n 0 1 x
Pin Function P9n input pin P9n output pin PWMn+1 output pin
[Legend] x: Don't care.
Rev. 1.00, 07/04, page 173 of 570
9.9 Port A
Port A is an I/O port also functioning as an LCD common output pin. Figure 9.9 shows its pin
configuration.
PA3/COM4
Port A
PA2/COM3
PA1/COM2
PA0/COM1
Figure 9.9 Port A Pin Configuration
Port A has the following registers.
• Port data register A (PDRA)
• Port control register A (PCRA)
9.9.1 Port Data Register A ( PDRA)
PDRA is a register that stores data of port A.
Bit Bit Name
Initial
Value R/W Description
7 to 4 All 1 Reserved
These bits are always read as 1 and cannot be modified.
3
2
1
0
PA3
PA2
PA1
PA0
0
0
0
0
R/W
R/W
R/W
R/W
If port A is read while PCRA bits are set to 1, the values
stored in PDRA are read, regardless of the actual pin
states. If port A is read while PCRA bits are cleared to 0,
the pin states are read.
Rev. 1.00, 07/04, page 174 of 570
9.9.2 Port Control Regi ster A (PCRA)
PCRA selects inputs/outputs in bit units for pins to be used as general I/O ports of port A.
Bit Bit Name
Initial
Value R/W Description
7 to 4 All 1 Reserved
These bits are always read as 1 and cannot be modified.
3
2
1
0
PCRA3
PCRA2
PCRA1
PCRA0
0
0
0
0
W
W
W
W
Setting a PCRA bit to 1 makes the corresponding pin an
output pin, while clearing the bit to 0 makes the pin an
input pin. The settings in PCRA and in PDRA are valid
when the corresponding pin is designated as a general
I/O pin.
PCRA is a write-only register. These bits are always
read as 1.
9.9.3 Pin Functions
The relationship between the register settings and the port functions is shown below.
PA3/COM4 pin
The pin function is switched as shown below according to the combination of the PCRA3 bit in
PCRA and SGS3 to SGS0 bits.
SGS3 to SGS0 B'0000 Other than B'0000
PCRA3 0 1 x
Pin Function PA3 input pin PA3 output pin COM4 output pin
[Legend] x: Don't care.
PA2/COM3 pin
The pin function is switched as shown below according to the combination of the PCRA2 bit in
PCRA and SGS3 to SGS0 bits.
SGS3 to SGS0 B'0000 Other than B'0000
PCRA2 0 1 x
Pin Function PA2 input pin PA2 output pin COM3 output pin
[Legend] x: Don't care.
Rev. 1.00, 07/04, page 175 of 570
PA1/COM2 pin
The pin function is switched as shown below according to the combination of the PCRA1 bit in
PCRA and SGS3 to SGS0 bits.
SGS3 to SGS0 B'0000 Other than B'0000
PCRA1 0 1 x
Pin Function PA1 input pin PA1 output pin COM2 output pin
[Legend] x: Don't care.
PA0/COM1 pin
The pin function is switched as shown below according to the combination of the PCRA0 bit in
PCRA and SGS3 to SGS0 bits.
SGS3 to SGS0 B'0000 Other than B'0000
PCRA0 0 1 x
Pin Function PA0 input pin PA0 output pin COM1 output pin
[Legend] x: Don't care.
Rev. 1.00, 07/04, page 176 of 570
9.10 Port B
Port B is an I/O port also functioning as an interrupt input pin, analog input pin, output pin for
internal reference voltage of the ∆Σ A/D converter and external reference voltage of the ∆Σ A/D
converter. Figure 9.10 shows its pin configuration.
ACOM
PB7/Ain1
Port B
PB6/Ain2
PB5/Vref/REF
PB0/AN0/IRQ
0
PB2/AN2/IRQ
3
PB1/AN1/IRQ
1
Figure 9.10 Port B Pin Configuration
Port B has the following registers.
• Port data register B (PDRB)
• Port mode register B (PMRB)
9.10.1 Port Data Register B (PDRB)
PDRB is a register that stores data of port B.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
PB7
PB6
PB5
PB2
PB1
PB0
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
R
R
R
R
R
R
Reading PDRB always gives the pin states. However, if
a port B pin is selected as an analog input channel by
the CH3 to CH0 bits in AMR of the A/D converter or the
AIN1 and AIN0 bits in ADSSR of the ∆Σ A/D converter,
that pin is read as 0 regardless of the input voltage. If bit
5 is selected as an external reference voltage (Vref) by
the VREF1 and VREF0 bits in ADCR of the ∆Σ A/D
converter, the pin is read as 0 regardless of the input
voltage.
Rev. 1.00, 07/04, page 177 of 570
9.10.2 Port Mode Register B (PMRB)
PMRB controls the selection of the port B pin functions.
Bit Bit Name
Initial
Value R/W Description
7 to 5 All 1 Reserved
These bits are always read as 1 and cannot be modified.
4 ADTSTCHG 0 R/W TEST/ADTRG Pin Function Switch
Selects whether pin TEST/ADTRG is used as TEST or
as ADTRG.
0: TEST pin
1: ADTRG input pin
For details on the setting of the ADTRG input pin, refer
to section 18.4.2, External Trigger Input Timing.
3 1 Reserved
This bit is always read as 1 and cannot be modified.
2 IRQ3 0 R/W PB2/AN2/IRQ3 Pin Function Switch
Selects whether pin PB2/AN2/IRQ3 is used as PB2/AN2
or as IRQ3.
0: PB2/AN2 input pin
1: IRQ3 input pin
1 IRQ1 0 R/W PB1/AN1/IRQ1 Pin Function Switch
Selects whether pin PB1/AN1/IRQ1 is used as PB1/AN1
or as IRQ1.
0: PB1/AN1 input pin
1: IRQ1 input pin
0 IRQ0 0 R/W PB0/AN0/IRQ0 Pin Function Switch
Selects whether pin PB0/AN0/IRQ0 is used as PB0/AN0
or as IRQ0.
0: PB0/AN0 input pin
1: IRQ0 input pin
Rev. 1.00, 07/04, page 178 of 570
9.10.3 Pin Functions
The relationship between the register settings and the port functions is shown below.
PB7/Ain1 pin
The pin function is switched as shown below according to the AIN1 and AIN2 bits in ADSSR.
AIN1 and AIN2 Other than B'01 B'01
Pin Function PB7 input pin Ain1 input pin
PB6/Ain2 pin
The pin function is switched as shown below according to the AIN1 and AIN2 bits in ADSSR.
AIN1 and AIN2 Other than B'10 B'10
Pin Function PB6 input pin Ain2 input pin
PB5/Vref/REF pin
The pin function is switched as shown below according to the VREF1 and VREF2 bits in ADCR.
VREF1 and VREF2 Other than B'00 B'01 B'10, B'11
Pin Function PB5 input pin Vref input pin REF output pin
Note: When these bits are set to B'10 or B'11, the PB5/Vref/REF pin functions as a REF output
pin. Thus the power should not be input to the pin. If the power is input, it is short-circuited
internally with the REF output and will cause a failure.
Rev. 1.00, 07/04, page 179 of 570
PB2/AN2/IRQ3 pin
The pin function is switched as shown below according to the combination of the CH3 to CH0 bits
in AMR and IRQ3 bit in PMRB.
IRQ3 0 1
CH3 to CH0 Other than B'0110 B'0110 Other than B'0110
Pin Function PB2 input pin AN2 input pin IRQ3 input pin
PB1/AN1/IRQ1 pin
The pin function is switched as shown below according to the combination of the CH3 to CH0 bits
in AMR and IRQ1 bit in PMRB.
IRQ1 0 1
CH3 to CH0 Other than B'0101 B'0101 Other than B'0101
Pin Function PB1 input pin AN1 input pin IRQ1 input pin
PB0/AN0/IRQ0 pin
The pin function is switched as shown below according to the combination of the CH3 to CH0 bits
in AMR and IRQ0 bit in PMRB.
IRQ0 0 1
CH3 to CH0 Other than B'0100 B'0100 Other than B'0100
Pin Function PB0 input pin AN0 input pin IRQ0 input pin
Rev. 1.00, 07/04, page 180 of 570
9.11 Input/Output Data Inversion
9.11.1 Serial Port Control Register (SPCR)
SPCR switches input/output data inversion of the RXD (IrRXD) and TXD (IrTXD) pins.
Figure 9.11 shows a input/output data inversion function.
SCINV0
SCINV2
P31/RXD32
P41/RXD31/IrRXD
P32/TXD32
P42/TXD31/IrTXD
RXD32
RXD31/IrRXD
TXD32
TXD31/IrTXD
SCINV1
SCINV3
Figure 9.11 Input/Output Data Inversion Function
Bit Bit Name
Initial
Value R/W Description
7, 6 All 1 Reserved
These bits are always read as 1 and cannot be modified.
5 SPC32 0 R/W P32/TXD32/SCL Pin Function Switch
Selects whether pin P32/TXD32/SCL is used as
P32/SCL or as TXD32.
0: P32/SCL I/O pin
1: TXD32 output pin*
Note: * Set the TE32 bit in SCR32 after setting this bit to
1.
4 SPC31 0 R/W P42/TXD31/IrTXD/TMOFH Pin Function Switch
Selects whether pin P42/TXD31/IrTXD/TMOFH is used
as P42/TMOFH or as TXD31/IrTXD.
0: P42 I/O pin or TMOFH output pin
1: TXD31/IrTXD output pin*
Note: * Set the TE bit in SCR3 after setting this bit to 1.
3 SCINV3 0 R/W TXD32 Pin Output Data Inversion Switch
Specifies whether output data of the TXD32 pin is to be
inverted or not.
0: TXD32 output data is not inverted
1: TXD32 output data is inverted
Rev. 1.00, 07/04, page 181 of 570
Bit Bit Name
Initial
Value R/W Description
2 SCINV2 0 R/W RXD32 Pin Input Data Inversion Switch
Specifies whether input data of the RXD32 pin is to be
inverted or not.
0: RXD32 input data is not inverted
1: RXD32 input data is inverted
1 SCINV1 0 R/W TXD31/IrTXD Pin Output Data Inversion Switch
Specifies whether output data of the TXD31/IrTXD pin is
to be inverted or not.
0: TXD31/IrTXD output data is not inverted
1: TXD31/IrTXD output data is inverted
0 SCINV0 0 R/W RXD31/IrRXD Pin Input Data Inversion Switch
Specifies whether input data of the RXD31/IrRXD pin is
to be inverted or not.
0: RXD31/IrRXD input data is not inverted
1: RXD31/IrRXD input data is inverted
Note: When the serial port control register is modified, the data being input or output up to that
point is inverted immediately after the modification, and an invalid data change is input or
output. When modifying the serial port control register, modification must be made in a state
in which data changes are invalidated.
9.12 Usage Notes
9.12.1 How to Handle Unused Pin
If an I/O pin not used by the user system is floating, pull it up or down.
• If an unused pin is an input pin, it is recommended to handle it in one of the following ways:
Pull it up to Vcc with an on-chip pull-up MOS.
Pull it up to Vcc with an external resistor of approximately 100 kΩ.
Pull it down to Vss with an external resistor of approximately 100 kΩ.
For a pin also used by the A/D converter, pull it up to AVcc. With an external resistor of
approximately 100 kΩ.
• If an unused pin is an output pin, it is recommended to handle it in one of the following ways:
Set the output of the unused pin to high and pull it up to Vcc with an on-chip pull-up MOS.
Set the output of the unused pin to high and pull it up to Vcc with an external resistor of
approximately 100 kΩ.
Set the output of the unused pin to low and pull it down to GND with an external resistor of
approximately 100 kΩ.
Rev. 1.00, 07/04, page 182 of 570
RTC3000A_000120030300 Rev. 1.00, 07/04, page 183 of 570
Section 10 Realtime Clock (RTC)
The realtime clock (RTC) is a timer used to count time ranging from a second to a week.
Interrupts can be generated ranging from 0.25 seconds to a week. Figure 10.1 shows the block
diagram of the RTC.
10.1 Features
• Counts seconds, minutes, hours, and day-of-week
• Start/stop function
• Reset function
• Readable/writable counter of seconds, minutes, hours, and day-of-week with BCD codes
• Periodic (0.25 seconds, 0.5 seconds, one second, minute, hour, day, and week) interrupts
• 8-bit free running counter
• Selection of clock source
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (For details, refer to section 6.4, Module Standby Function.)
PSS
32-kHz
oscillator
circuit
RTCCSR
RSECDR
RMINDR
RWKDR
Clock count
control circuit
Interrupt
control circuit Interrupt
RTCCR1
RHRDR
RTCCR2
RTCFLG
Internal data bus
1/4
TMOW
[Legend]
RTCCSR:
RSECDR:
RMINDR:
RHRDR:
Clock source select register
Second date register/
free running counter data register
Minute date register
Hour date register
RWKDR:
RTCCR1:
RTCCR2:
RTCFLG:
PSS:
Day-of-week date register
RTC control register 1
RTC control register 2
RTC interrupt flag register
Prescaler S
Figure 10.1 Block Diagram of RTC
Rev. 1.00, 07/04, page 184 of 570
10.2 Input/Output Pin
Table 10.1 shows the RTC input/output pin.
Table 10.1 Pin Configuration
Name Abbreviation I/O Function
Clock output TMOW Output RTC divided clock output
10.3 Register Descriptions
The RTC has the following registers.
• Second data register/free running counter data register (RSECDR)
• Minute data register (RMINDR)
• Hour data register (RHRDR)
• Day-of-week data register (RWKDR)
• RTC control register 1 (RTCCR1)
• RTC control register 2 (RTCCR2)
• Clock source select register (RTCCSR)
• RTC Interrupt flag register (RTCFLG)
Rev. 1.00, 07/04, page 185 of 570
10.3.1 Second Data Register/Free Running Counter Data Register (RSECDR)
RSECDR counts the BCD-coded second value. The setting range is decimal 00 to 59. It is an 8-bit
read register used as a counter, when it operates as a free running counter. For more information
on reading seconds, minutes, hours, and day-of-week, see section 10.4.3, Data Reading Procedure.
Bit Bit Name
Initial
Value R/W Description
7 BSY — R RTC Busy
This bit is set to 1 when the RTC is updating (operating)
the values of second, minute, hour, and day-of-week data
registers. When this bit is 0, the values of second, minute,
hour, and day-of-week data registers must be adopted.
6
5
4
SC12
SC11
SC10
—
—
—
R/W
R/W
R/W
Counting Ten's Position of Seconds
Counts on 0 to 5 for 60-second counting.
3
2
1
0
SC03
SC02
SC01
SC00
—
—
—
—
R/W
R/W
R/W
R/W
Counting One's Position of Seconds
Counts on 0 to 9 once per second. When a carry is
generated, 1 is added to the ten's position.
10.3.2 Minute Data Register (RM IN DR )
RMINDR counts the BCD-coded minute value on the carry generated once per minute by the
RSECDR counting. The setting range is decimal 00 to 59.
Bit Bit Name
Initial
Value R/W Description
7 BSY — R RTC Busy
This bit is set to 1 when the RTC is updating (operating)
the values of second, minute, hour, and day-of-week data
registers. When this bit is 0, the values of second, minute,
hour, and day-of-week data registers must be adopted.
6
5
4
MN12
MN11
MN10
—
—
—
R/W
R/W
R/W
Counting Ten's Position of Minutes
Counts on 0 to 5 for 60-minute counting.
3
2
1
0
MN03
MN02
MN01
MN00
—
—
—
—
R/W
R/W
R/W
R/W
Counting One's Position of Minutes
Counts on 0 to 9 once per minute. When a carry is
generated, 1 is added to the ten's position.
Rev. 1.00, 07/04, page 186 of 570
10.3.3 Hour Data Register (RHRDR)
RHRDR counts the BCD-coded hour value on the carry generated once per hour by RMINDR.
The setting range is either decimal 00 to 11 or 00 to 23 by the selection of the 12/24 bit in
RTCCR1.
Bit Bit Name
Initial
Value R/W Description
7 BSY — R RTC Busy
This bit is set to 1 when the RTC is updating (operating)
the values of second, minute, hour, and day-of-week data
registers. When this bit is 0, the values of second, minute,
hour, and day-of-week data registers must be adopted.
6 — 0 — Reserved
This bit is always read as 0.
5
4
HR11
HR10
—
—
R/W
R/W
Counting Ten's Position of Hours
Counts on 0 to 2 for ten's position of hours.
3
2
1
0
HR03
HR02
HR01
HR00
—
—
—
—
R/W
R/W
R/W
R/W
Counting One's Position of Hours
Counts on 0 to 9 once per hour. When a carry is
generated, 1 is added to the ten's position.
Rev. 1.00, 07/04, page 187 of 570
10.3.4 Day-of-Week Data Regi s ter (R WKDR)
RWKDR counts the BCD-coded day-of-week value on the carry generated once per day by
RHRDR. The setting range is decimal 0 to 6 using bits WK2 to WK0.
Bit Bit Name
Initial
Value R/W Description
7 BSY — R RTC Busy
This bit is set to 1 when the RTC is updating (operating)
the values of second, minute, hour, and day-of-week data
registers. When this bit is 0, the values of second, minute,
hour, and day-of-week data registers must be adopted.
6 to 3 — All 0 — Reserved
These bits are always read as 0.
2
1
0
WK2
WK1
WK0
—
—
—
R/W
R/W
R/W
Day-of-Week Counting
Day-of-week is indicated with a binary code
000: Sunday
001: Monday
010: Tuesday
011: Wednesday
100: Thursday
101: Friday
110: Saturday
111: Setting prohibited
Rev. 1.00, 07/04, page 188 of 570
10.3.5 RTC Control Register 1 (RTCCR1)
RTCCR1 controls start/stop and reset of the clock timer. For the definition of time expression, see
figure 10.2.
Bit Bit Name
Initial
Value R/W Description
7 RUN — R/W RTC Operation Start
0: Stops RTC operation
1: Starts RTC operation
6 12/24 — R/W Operating Mode
0: RTC operates in 12-hour mode. RHRDR counts on 0
to 11.
1: RTC operates in 24-hour mode. RHRDR counts on 0
to 23.
5 PM — R/W A.m./P.m.
0: Indicates a.m. when RTC is in the 12-hour mode.
1: Indicates p.m. when RTC is in the 12-hour mode.
4 RST 0 R/W Reset
0: Normal operation
1: Resets registers and control circuits except RTCCSR
and this bit. Clear this bit to 0 after having been set to 1.
3 to 0 — All 0 — Reserved
These bits are always read as 0.
24-hour count 01234567891011121314151617
12-hour count 0
PM
24-hour count
12-hour count
PM
0 (Morning) 1 (Afternoon)
Noon
1234567891011012345
18 19 20 21 22 23 0
6
1 (Afternoon) 0
7 8 9 10 11 0
Figure 10.2 Definition of Time Expression
Rev. 1.00, 07/04, page 189 of 570
10.3.6 RTC Control Register 2 (RTCCR2)
RTCCR2 controls RTC periodic interrupts of week, day, hour, minute, one second, 0.5 seconds,
and 0.25 seconds. Enabling interrupts of week, day, hour, minute, one second, 0.5 seconds, and
0.25 seconds sets the corresponding flag to 1 in the RTC interrupt flag register (RTCFLG) when
an interrupt occurs. It also controls an overflow interrupt of a free running counter when RTC
operates as a free running counter.
Bit Bit Name
Initial
Value R/W Description
7 FOIE — R/W Free Running Counter Overflow Interrupt Enable
0: Disables an overflow interrupt
1: Enables an overflow interrupt
6 WKIE — R/W Week Periodic Interrupt Enable
0: Disables a week periodic interrupt
1: Enables a week periodic interrupt
5 DYIE — R/W Day Periodic Interrupt Enable
0: Disables a day periodic interrupt
1: Enables a day periodic interrupt
4 HRIE — R/W Hour Periodic Interrupt Enable
0: Disables an hour periodic interrupt
1: Enables an hour periodic interrupt
3 MNIE — R/W Minute Periodic Interrupt Enable
0: Disables a minute periodic interrupt
1: Enables a minute periodic interrupt
2 1SEIE — R/W One-Second Periodic Interrupt Enable
0: Disables a one-second periodic interrupt
1: Enables a one-second periodic interrupt
1 05SEIE — R/W 0.5-Second Periodic Interrupt Enable
0: Disables a 0.5-second periodic interrupt
1: Enables a 0.5-second periodic interrupt
0 025SEIE — R/W 0.25-Second Periodic Interrupt Enable
0: Disables a 0.25-second periodic interrupt
1: Enables a 0.25-second periodic interrupt
Rev. 1.00, 07/04, page 190 of 570
10.3.7 Clock Source Select Register (RTCCSR)
RTCCSR selects clock source. A free running counter controls start/stop of counter operation by
the RUN bit in RTCCR1. When a clock other than 32.768 kHz is selected, the RTC is disabled
and operates as an 8-bit free running counter. When the RTC operates as an 8-bit free running
counter, RSECDR enables counter values to be read. An interrupt can be generated by setting 1 to
the FOIE bit in RTCCR2 and enabling an overflow interrupt of the free running counter. A clock
in which the system clock is divided by 32, 16, 8, or 4 is output in active or sleep mode.
Bit Bit Name
Initial
Value R/W Description
7 — 0 — Reserved
This bit is always read as 0.
6
5
4
RCS6
RCS5
SUB32K
0
0
0
R/W
R/W
R/W
Clock Output Selection
Select a clock output from the TMOW pin when setting
the TMOW bit in PMR3 to 1.
000: φ/4
010: φ/8
100: φ/16
110: φ/32
xx1: φw
3
2
1
0
RCS3
RCS2
RCS1
RCS0
1
0
0
0
R/W
R/W
R/W
R/W
Clock Source Selection
0000: φ/8⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0001: φ/32⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0010: φ/128⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0011: φ/256⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0100: φ/512⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0101: φ/2048⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0110: φ/4096⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0111: φ/8192⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
1xxx: 32.768 kHz⋅⋅⋅⋅⋅RTC operation
[Legend] x: Don't care.
Rev. 1.00, 07/04, page 191 of 570
10.3.8 RTC Interrupt Flag Register (RTCFLG)
RTCFLG sets the corresponding flag when an interrupt occurs. Each flag is not cleared
automatically even if the interrupt is accepted. To clear the flag, 0 should be written to the flag.
Bit Bit Name
Initial
Value R/W Description
7 FOIFG 0 R/W* [Setting condition]
When a free running counter overflows
[Clearing condition]
0 is written to FOIFG when FOIFG = 1
6 WKIFG 0 R/W* [Setting condition]
When a week periodic interrupt occurs
[Clearing condition]
0 is written to WKIFG when WKIFG = 1
5 DYIFG 0 R/W* [Setting condition]
When a day periodic interrupt occurs
[Clearing condition]
0 is written to DYIFG when DYIFG = 1
4 HRIFG 0 R/W* [Setting condition]
When an hour periodic interrupt occurs
[Clearing condition]
0 is written to HRIFG when HRIFG = 1
3 MNIFG 0 R/W* [Setting condition]
When a minute periodic interrupt occurs
[Clearing condition]
0 is written to MNIFG when MNIFG = 1
2 SEIFG 0 R/W* [Setting condition]
When a one-second periodic interrupt occurs
[Clearing condition]
0 is written to SEIFG when SEIFG = 1
1 05SEIFG 0 R/W* [Setting condition]
When a 0.5-second periodic interrupt occurs
[Clearing condition]
0 is written to 05SEIFG when 05SEIFG = 1
0 025SEIFG 0 R/W* [Setting condition]
When a 0.25-second periodic interrupt occurs
[Clearing condition]
0 is written to 025SEIFG when 025SEIFG = 1
Note: * Only 0 can be written to clear the flag.
Rev. 1.00, 07/04, page 192 of 570
10.4 Operation
10.4.1 Initial Settings of Registers after Power-On
The RTC registers that store second, minute, hour, and day-of week data are not reset by a RES
input. Therefore, all registers must be set to their initial values after power-on.
10.4.2 Initial Setting Procedure
Figure 10.3 shows the procedure for the initial setting of the RTC. To set the RTC again, also
follow this procedure.
When the second, minute, hour, or day-of-week data is set, check the BSY bit. When the BSY bit
is cleared to 0, clear the RUN bit in RTCCR1 to 0 to stop the RTC operation.
RTC operation is stopped.
RTC registers and clock count
controller are reset.
Clock output and clock source are
selected and second, minute, hour,
day-of-week, operating mode, and
a.m/p.m are set.
RTC operation is started.
RUN in RTCCR1 = 0
RST in RTCCR1 = 1
RST in RTCCR1 = 0
Set RTCCSR, RSECDR,
RMINDR, RHRDR,
RWKDR, 12/24 in
RTCCR1, and PM
RUN in RTCCR1 = 1
BSY = 0
Figure 10.3 Initial Setting Procedure
Rev. 1.00, 07/04, page 193 of 570
10.4.3 Data Reading Procedure
When the seconds, minutes, hours, or day-of-week datum is updated while time data is being read,
the data obtained may not be correct, and so the time data must be read again. Figure 10.4 shows
an example in which correct data is not obtained. In this example, since only RSECDR is read
after data update, about 1-minute inconsistency occurs.
To avoid reading in this timing, the following processing must be performed.
1. Check the setting of the BSY bit, and when the BSY bit changes from 1 to 0, read from the
second, minute, hour, and day-of-week registers. When about 62.5 ms is passed after the BSY
bit is set to 1, the registers are updated, and the BSY bit is cleared to 0.
2. Making use of interrupts, read from the second, minute, hour, and day-of week registers after
the corresponding flag of RTCFLG is set to 1 and the BSY bit is confirmed to be 0.
3. Read from the second, minute, hour, and day-of week registers twice in a row, and if there is
no change in the read data, the read data is used.
Before update RWKDR = H'03, RHDDR = H'13, RMINDR = H'46, RSECDR = H'59
BSY bit = 0
(1) Day-of-week data register read H'03
(2) Hour data register read H'13
(3) Minute data register read H'46
BSY bit -> 1 (under data update)
After update RWKDR = H'03, RHDDR = H'13, RMINDR = H'47, RSECDR = H'00
BSY bit -> 0
(4) Second data register read H'00
Processing flow
Figure 10.4 Example: Re a di ng of Inaccurate Time Data
Rev. 1.00, 07/04, page 194 of 570
10.5 Interrupt Sources
There are eight kinds of RTC interrupts: a free-running counter overflow, week interrupt, day
interrupt, hour interrupt, minute interrupt, one-second interrupt, 0.5-second interrupt, and 0.25-
second interrupt.
When using an interrupt, initiate the RTC last after other registers are set.
When an interrupt request of the RTC occurs, the corresponding flag in RTCFLG is set to 1. When
clearing the flag, write 0.
Table 10.2 shows a interrupt sources.
Table 10.2 Interrupt Sources
Interrupt Name Interrupt Source Interrupt Enable Bit
Overflow interrupt Occurs when the free running counter is
overflown.
FOIE
Week periodic interrupt Occurs every week when the day-of-week date
register value becomes 0.
WKIE
Day periodic interrupt Occurs every day when the day-of-week date
register is counted.
DYIE
Hour periodic interrupt Occurs every hour when the hour date register
is counted.
HRIE
Minute periodic interrupt Occurs every minute when the minute date
register is counted.
MNIE
One-second periodic
interrupt
Occurs every second when the one-second
date register is counted.
1SEIE
0.5-second periodic
interrupt
Occurs every 0.5 seconds. 05SEIE
0.25-second periodic
interrupt
Occurs every 0.25 seconds. 025SEIE
10.6 Usage Note
10.6.1 Note on Clock Count
The subclock must be connected to the 32.768-kHz resonator. When the 38.4-kHz resonator etc. is
connected, the correct time count is not possible.
Rev. 1.00, 07/04, page 195 of 570
Section 11 Timer F
The timer F is a 16-bit timer having an output compare function. The timer F also provides for
external event counting, and counter resetting, interrupt request generation, toggle output, etc.,
using compare match signals. Thus, it can be applied to various systems. The timer F can also be
used as two independent 8-bit timers (timer FH and timer FL). Figure 11.1 shows a block diagram
of the timer F.
11.1 Features
• Choice of five counter input clocks
Internal clocks (φ/32, φ/16, φ/4, and φW/4) or external clocks can be selected.
• Toggle output function
Toggle output is performed to the TMOFH or TMOFL pin using a compare match signal.
The initial value of toggle output can be set.
• Counter resetting by a compare match signal
• Two interrupt sources: One compare match, one overflow
• Choice of 16-bit or 8-bit mode by settings of bits CKSH2 to CKSH0 in TCRF
• Can operate in watch mode, subactive mode, and subsleep mode
When φW/4 is selected as an internal clock, the timer F can operate in watch mode, subactive
mode, and subsleep mode.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (For details, refer to section 6.4, Module Standby Function.)
Rev. 1.00, 07/04, page 196 of 570
PSS
Toggle
circuit
Toggle
circuit
φ
φ
W
/4
TMIF
TMOFL
TMOFH
TCRF
TCFL
OCRFL
TCFH
OCRFH
TCSRF
Comparator
Comparator Match
Internal data bus
IRRTFH
IRRTFL
[Legend]
TCRF:
TCSRF:
TCFH:
TCFL:
OCRFH:
OCRFL:
IRRTFH:
IRRTFL:
PSS:
Timer control register F
Timer control status register F
8-bit timer counter FH
8-bit timer counter FL
Output compare register FH
Output compare register FL
Timer FH interrupt request flag
Timer FL interrupt request flag
Prescaler S
Figure 11.1 Block Diagram of Timer F
Rev. 1.00, 07/04, page 197 of 570
11.2 Input/Output Pins
Table 11.1 shows the input/output pins of the timer F.
Table 11.1 Pin Configuration
Name Abbreviation I/O Function
Timer F event input TMIF Input Event input pin to TCFL
Timer FH output TMOFH Output Timer FH toggle output pin
Timer FL output TMOFL Output Timer FL toggle output pin
11.3 Register Descriptions
The timer F has the following registers.
• Timer counters FH and FL (TCFH, TCFL)
• Output compare registers FH and FL (OCRFH, OCRFL)
• Timer control register F (TCRF)
• Timer control/status register F (TCSRF)
11.3.1 Timer Counters FH and FL (TCFH, TCFL)
TCF is a 16-bit read/write up-counter configured by cascaded connection of 8-bit timer counters
TCFH and TCFL. In addition to the use of TCF as a 16-bit counter with TCFH as the upper 8 bits
and TCFL as the lower 8 bits, TCFH and TCFL can also be used as independent 8-bit counters.
TCFH and TCFL are initialized to H'00 upon a reset.
(1) 16-Bit Mode (TCF)
When CKSH2 is cleared to 0 in TCRF, TCF operates as a 16-bit counter. The TCF input clock is
selected by bits CKSL2 to CKSL0 in TCRF.
TCF can be cleared in the event of a compare match by means of CCLRH in TCSRF.
When TCF overflows from H'FFFF to H'0000, OVFH is set to 1 in TCSRF. If OVIEH in TCSRF
is 1 at this time, IRRTFH is set to 1 in IRR2, and if IENTFH in IENR2 is 1, an interrupt request is
sent to the CPU.
Rev. 1.00, 07/04, page 198 of 570
(2) 8-Bit Mode (TCFH/TCFL)
When CKSH2 is set to 1 in TCRF, TCFH and TCFL operate as two independent 8-bit counters.
The TCFH (TCFL) input clock is selected by bits CKSH2 to CKSH0 (CKSL2 to CKSL0) in
TCRF.
TCFH (TCFL) can be cleared in the event of a compare match by means of CCLRH (CCLRL) in
TCSRF.
When TCFH (TCFL) overflows from H'FF to H'00, OVFH (OVFL) is set to 1 in TCSRF. If
OVIEH (OVIEL) in TCSRF is 1 at this time, IRRTFH (IRRTFL) is set to 1 in IRR2, and if
IENTFH (IENTFL) in IENR2 is 1, an interrupt request is sent to the CPU.
11.3.2 Output Compare Registers FH and FL (OCRFH, OCRFL)
OCRF is a 16-bit read/write register composed of the two registers OCRFH and OCRFL. In
addition to the use of OCRF as a 16-bit register with OCRFH as the upper 8 bits and OCRFL as
the lower 8 bits, OCRFH and OCRFL can also be used as independent 8-bit registers.
(1) 16-Bit Mode (OCRF)
When CKSH2 is cleared to 0 in TCRF, OCRF operates as a 16-bit register. OCRF contents are
constantly compared with TCF, and when both values match, CMFH is set to 1 in TCSRF. At the
same time, IRRTFH is set to 1 in IRR2. If IENTFH in IENR2 is 1 at this time, an interrupt request
is sent to the CPU.
Toggle output can be provided from the TMOFH pin by means of compare matches, and the
output level can be set by means of the TOLH bit in TCRF.
(2) 8-Bit Mode (OCRFH/OCR FL)
When CKSH2 is set to 1 in TCRF, OCRFH and OCRFL operate as two independent 8-bit
registers. OCRFH contents are compared with TCFH, and OCRFL contents are with TCFL. When
the OCRFH (OCRFL) and TCFH (TCFL) values match, CMFH (CMFL) is set to 1 in TCSRF. At
the same time, IRRTFH (IRRTFL) is set to 1 in IRR2. If IENTFH (IENTFL) in IENR2 is 1 at this
time, an interrupt request is sent to the CPU.
Toggle output can be provided from the TMOFH pin (TMOFL pin) by means of compare
matches, and the output level can be set by means of the TOLH (TOLL) bit in TCRF.
Rev. 1.00, 07/04, page 199 of 570
11.3.3 Timer Control Register F (TCR)
TCRF switches between 16-bit mode and 8-bit mode, selects the input clock from among four
internal clock sources, and selects the output level of the TMOFH and TMOFL pins.
Bit Bit Name
Initial
Value R/W Description
7 TOLH 0 W Toggle Output Level H
Sets the TMOFH pin output level.
0: Low level
1: High level
6
5
4
CKSH2
CKSH1
CKSH0
0
0
0
W
W
W
Clock Select H
Select the clock input to TCFH from among four
internal clock sources or TCFL overflow.
000: 16-bit mode, counting on TCFL overflow signal
001: 16-bit mode, counting on TCFL overflow signal
010: 16-bit mode, counting on TCFL overflow signal
011: Using prohibited
100: 8-bit mode, counting on φ/32
101: 8-bit mode, counting on φ/16
110: 8-bit mode, counting on φ/4
111: 8-bit mode, counting on φW/4
3 TOLL 0 W Toggle Output Level L
Sets the TMOFL pin output level.
0: Low level
1: High level
2
1
0
CKSL2
CKSL1
CKSL0
0
0
0
W
W
W
Clock Select L
Select the clock input to TCFL from among four internal
clock sources or external event input.
000: Counting on a rising or falling edge of an external
event (TMIF pin)*
001: Counting on a rising or falling edge of an external
event (TMIF pin)*
010: Counting on a rising or falling edge of an external
event (TMIF pin)*
011: Using prohibited
100: Internal clock: counting on φ/32
101: Internal clock: counting on φ/16
110: Internal clock: counting on φ/4
111: Internal clock: counting on φW/4
Note: * The TMIFEG bit in IEGR selects which edge of an external event is used for counting.
Rev. 1.00, 07/04, page 200 of 570
11.3.4 Timer Control/Status Register F (TCSRF)
TCSRF performs counter clear selection, overflow flag setting, and compare match flag setting,
and controls enabling of overflow interrupt requests.
Bit Bit Name
Initial
Value R/W Description
7 OVFH 0 R/W* Timer Overflow Flag H
[Setting condition]
When TCFH overflows from H'FF to H'00
[Clearing condition]
When this bit is written to 0 after reading OVFH = 1
6 CMFH 0 R/W* Compare Match Flag H
This is a status flag indicating that TCFH has matched
OCRFH.
[Setting condition]
When the TCFH value matches the OCRFH value
[Clearing condition]
When this bit is written to 0 after reading CMFH = 1
5 OVIEH 0 R/W Timer Overflow Interrupt Enable H
Selects enabling or disabling of interrupt generation
when TCFH overflows.
0: TCFH overflow interrupt request is disabled
1: TCFH overflow interrupt request is enabled
4 CCLRH 0 R/W Counter Clear H
In 16-bit mode, this bit selects whether TCF is cleared
when TCF and OCRF match. In 8-bit mode, this bit
selects whether TCFH is cleared when TCFH and
OCRFH match.
In 16-bit mode:
0: TCF clearing by compare match is disabled
1: TCF clearing by compare match is enabled
In 8-bit mode:
0: TCFH clearing by compare match is disabled
1: TCFH clearing by compare match is enabled
Rev. 1.00, 07/04, page 201 of 570
Bit Bit Name
Initial
Value R/W Description
3 OVFL 0 R/W* Timer Overflow Flag L
This is a status flag indicating that TCFL has
overflowed.
[Setting condition]
When TCFL overflows from H'FF to H'00
[Clearing condition]
When this bit is written to 0 after reading OVFL = 1
2 CMFL 0 R/W* Compare Match Flag L
This is a status flag indicating that TCFL has matched
OCRFL.
[Setting condition]
When the TCFL value matches the OCRFL value
[Clearing condition]
When this bit is written to 0 after reading CMFL = 1
1 OVIEL 0 R/W Timer Overflow Interrupt Enable L
Selects enabling or disabling of interrupt generation
when TCFL overflows.
0: TCFL overflow interrupt request is disabled
1: TCFL overflow interrupt request is enabled
0 CCLRL 0 R/W Counter Clear L
Selects whether TCFL is cleared when TCFL and
OCRFL match.
0: TCFL clearing by compare match is disabled
1: TCFL clearing by compare match is enabled
Note: * Only 0 can be written to clear the flag.
Rev. 1.00, 07/04, page 202 of 570
11.4 Operation
The timer F is a 16-bit counter that increments on each input clock pulse. The timer F value is
constantly compared with the value set in the output compare register F, and the counter can be
cleared, an interrupt requested, or port output toggled, when the two values match. The timer F
can also be used as two independent 8-bit timers.
11.4.1 Timer F Operation
The timer F has two operating modes, 16-bit timer mode and 8-bit timer mode. The operation in
each of these modes is described below.
(1) Operation in 16-Bit Timer Mode
When the CKSH2 bit is cleared to 0 in TCRF, the timer F operates as a 16-bit timer.
Following a reset, TCF is initialized to H'0000, OCRF to H'FFFF, and TCRF and TCSRF to H'00.
The counter is incremented by an input signal from an external event (TMIF pin). The TMIFEG
bit in IEGR selects which edge of an external event is used for counting.
The timer F operating clock can be selected from internal clocks or external events according to
settings of bits CKSL2 to CKSL0 in TCRF.
OCRF contents are constantly compared with TCF, and when both values match, CMFH is set to
1 in TCSRF. If IENTFH in IENR2 is 1 at this time, an interrupt request is sent to the CPU, and at
the same time, TMOFH pin output is toggled. If CCLRH in TCSRF is 1, TCF is cleared. The
output level of the TMOFH pin can be set by the TOLH bit in TCRF.
When TCF overflows from H'FFFF to H'0000, OVFH is set to 1 in TCSRF. If OVIEH in TCSRF
and IENTFH in IENR2 are both 1, an interrupt request is sent to the CPU.
(2) Operation in 8-Bit Timer Mode
When CKSH2 is set to 1 in TCRF, TCF operates as two independent 8-bit timers, TCFH and
TCFL. The TCFH/TCFL input clock is selected by CKSH2 to CKSH0/CKSL2 to CKSL0 in
TCRF.
When the OCRFH/OCRFL and TCFH/TCFL values match, CMFH/CMFL is set to 1 in TCSRF. If
IENTFH/IENTFL in IENR2 is 1, an interrupt request is sent to the CPU, and at the same time,
TMOFH pin/TMOFL pin output is toggled. If CCLRH/CCLRL in TCSRF is 1, TCFH/TCFL is
cleared. The output level of the TMOFH pin/TMOFL pin can be set by TOLH/TOLL in TCRF.
When TCFH/TCFL overflows from H'FF to H'00, OVFH/OVFL is set to 1 in TCSRF. If
OVIEH/OVIEL in TCSRF and IENTFH/IENTFL in IENR2 are both 1, an interrupt request is sent
to the CPU.
Rev. 1.00, 07/04, page 203 of 570
11.4.2 TCF Increment Timing
(1) Internal Clock Operation
TCF is incremented by internal clock or external event input. Bits CKSH2 to CKSH0 or CKSL2 to
CKSL0 in TCRF select one of internal clock sources (φ/32, φ/16, φ/4, or φW/4) created by dividing
the system clock (φ or φW).
(2) External Event Operation
When the CKSL2 bit in TCRF is cleared to 0, external event input is selected. The counter is
incremented at both rising and falling edges of external events. The TMIFEG bit in IEGR selects
which edge of an external event is used for counting. The external event pulse width requires
clock time longer than 2 system clocks (φ), or 2 subclocks (φSUB), depending on the operating
mode. Note that an external event does not operate correctly with the lower pulse width.
11.4.3 TMOFH/TMOFL Output Timing
In TMOFH/TMOFL output, the value set in TOLH/TOLL in TCRF is output. The output is
toggled by the occurrence of a compare match.
Figure 11.2 shows the output timing.
φ
Count input clock
TCF
OCRF
TMOFH, TMOFL
Compare match signal
NN
NN
N+1 N+1
TMIF
(TMIFEG = 1)
Figure 11.2 TMOFH/TMOFL Output Timing
Rev. 1.00, 07/04, page 204 of 570
11.4.4 TCF Clear Timing
TCF can be cleared by a compare match with OCRF.
11.4.5 Timer Overflow Flag (OVF) Set Timing
OVF is set to 1 when TCF overflows from H'FFFF to H'0000.
11.4.6 Compare Match Flag Set Timing
The compare match flag (CMFH or CMFL) is set to 1 when the TCF and OCRF values match.
The compare match signal is generated in the last state during which the values match (when TCF
is updated from the matching value to a new value). When TCF matches OCRF, the compare
match signal is not generated until the next counter clock.
11.5 Timer F Operating States
The timer F operating states are shown in table 11.2.
Table 11.2 Timer F Operating States
Operating
Mode
Reset
Active
Sleep
Watch Sub-active Sub-sleep
Standby Module
Standby
TCF Reset Functions* Functions* Functions/
Halted*
Functions/
Halted*
Functions/
Halted*
Halted Halted
OCRF Reset Functions Retained Retained Functions Retained Retained Retained
TCRF Reset Functions Retained Retained Functions Retained Retained Retained
TCSRF Reset Functions Retained Retained Functions Retained Retained Retained
Note: * When φW/4 is selected as the TCF internal clock in active mode or sleep mode, since
the system clock and internal clock are mutually asynchronous, synchronization is
maintained by a synchronization circuit. This results in a maximum count cycle error of
1/φ (s). When the counter is operated in subactive mode, watch mode, or subsleep
mode, φW /4 must be selected as the internal clock. The counter will not operate if any
other internal clock is selected.
Rev. 1.00, 07/04, page 205 of 570
11.6 Usage Notes
The following types of contention and operation can occur when the timer F is used.
11.6.1 16-Bit Timer Mode
In toggle output, TMOFH pin output is toggled when all 16 bits match and a compare match
signal is generated. If a TCRF write by a MOV instruction and generation of the compare match
signal occur simultaneously, TOLH data is output to the TMOFH pin as a result of the TCRF
write. TMOFL pin output is unstable in 16-bit mode, and should not be used; the TMOFL pin
should be used as a port pin.
If an OCRFL write and compare match signal generation occur simultaneously, the compare
match signal is invalid. However, if the written data and the counter value match, a compare
match signal will be generated at that point. As the compare match signal is output in
synchronization with the TCFL clock, a compare match will not result in compare match signal
generation if the clock is stopped.
Compare match flag CMFH is set when all 16 bits match and a compare match signal is generated.
Compare match flag CMFL is set if the setting conditions for the lower 8 bits are satisfied.
When TCF overflows, OVFH is set. OVFL is set if the setting conditions are satisfied when the
lower 8 bits overflow. If a TCFL write and overflow signal output occur simultaneously, the
overflow signal is not output.
11.6.2 8-Bit Timer Mode
(1) TCFH, OCRFH
In toggle output, TMOFH pin output is toggled when a compare match occurs. If a TCRF write by
a MOV instruction and generation of the compare match signal occur simultaneously, TOLH data
is output to the TMOFH pin as a result of the TCRF write.
If an OCRFH write and compare match signal generation occur simultaneously, the compare
match signal is invalid. However, if the written data and the counter value match, a compare
match signal will be generated at that point. The compare match signal is output in
synchronization with the TCFH clock.
If a TCFH write and overflow signal output occur simultaneously, the overflow signal is not
output.
Rev. 1.00, 07/04, page 206 of 570
(2) TCFL, OCRFL
In toggle output, TMOFL pin output is toggled when a compare match occurs. If a TCRF write by
a MOV instruction and generation of the compare match signal occur simultaneously, TOLL data
is output to the TMOFL pin as a result of the TCRF write.
If an OCRFL write and compare match signal generation occur simultaneously, the compare
match signal is invalid. However, if the written data and the counter value match, a compare
match signal will be generated at that point. As the compare match signal is output in
synchronization with the TCFL clock, a compare match will not result in compare match signal
generation if the clock is stopped.
If a TCFL write and overflow signal output occur simultaneously, the overflow signal is not
output.
11.6.3 Flag Clearing
When φW/4 is selected as the internal clock, "Interrupt source generation signal" will be operated
with φW and the signal will be outputted with φW width. And, "Overflow signal" and "Compare
match signal" are controlled with 2 cycles of φW signals. Those signals are output with 2-cycle
width of φW (figure 11.3)
In active (high-speed, medium-speed) mode, even if you cleared interrupt request flag during the
term of validity of "Interrupt source generation signal", same interrupt request flag is set. (1 in
figure 11.3) And, the timer overflow flag and compare match flag cannot be cleared during the
term of validity of "Overflow signal" and "Compare match signal".
For interrupt request flag is set right after interrupt request is cleared, interrupt process to one time
timer FH, timer FL interrupt might be repeated. (2 in figure 11.3) Therefore, to definitely clear
interrupt request flag in active (high-speed, medium-speed) mode, clear should be processed after
the time that calculated with below (1) formula. And, to definitely clear timer overflow flag and
compare match flag, clear should be processed after read timer control status register F (TCSRF)
after the time that calculated with below (1) formula.
For ST of (1) formula, please substitute the longest number of execution states in used instruction.
(10 states of RTE instruction when MULXU, DIVXU instruction is not used, 14 states when
MULXU, DIVXU instruction is used)
In subactive mode, there are not limitation for interrupt request flag, timer overflow flag, and
compare match flag clear.
Rev. 1.00, 07/04, page 207 of 570
The term of validity of "Interrupt source generation signal"
= 1 cycle of φW + waiting time for completion of executing instruction
+ interrupt time synchronized with φ
= 1/φW + ST × (1/φ) + (2/φ) (second).....(1)
ST: Executing number of execution states
Method 1 is recommended to operate for time efficiency.
Method 1
1. Prohibit interrupt in interrupt handling routine (set IENFH, IENFL to 0).
2. After program process returned normal handling, clear interrupt request flags (IRRTFH,
IRRTFL) after more than that calculated with (1) formula.
3. After reading the timer control status register F (TCSRF), clear the timer overflow flags
(OVFH, OVFL) and compare match flags (CMFH, CMFL).
4. Enable interrupts (set IENFH, IENFL to 1).
Method 2
1. Set interrupt handling routine time to more than time that calculated with (1) formula.
2. Clear interrupt request flags (IRRTFH, IRRTFL) at the end of interrupt handling routine.
3. After read timer control status register F (TCSRF), clear timer overflow flags (OVFH,
OVFL) and compare match flags (CMFH, CMFL).
All above attentions are also applied in 16-bit mode and 8-bit mode.
φ
W
Program processing
Interrupt source generation
signal (internal signal,
nega-active)
Overflow signal, compare
match signal (internal signal,
nega-active)
Interrupt request flag
(IRRTFH, IRRTFL)
Interrupt Normal
Interrupt request
flag clear
2
Interrupt
Interrupt request
flag clear
1
Figure 11.3 Clear Interrupt Reques t Flag when
Interrupt Source Generation Signal is Valid
Rev. 1.00, 07/04, page 208 of 570
11.6.4 Timer Counter (TCF) Read/Write
When φW/4 is selected as the internal clock in active (high-speed, medium-speed) mode, write on
TCF is impossible. And when reading TCF, as the system clock and internal clock are mutually
asynchronous, TCF synchronizes with synchronization circuit. This results in a maximum TCF
read value error of ±1.
When reading or writing TCF in active (high-speed, medium-speed) mode is needed, please select
the internal clock except for φW/4 before read/write is performed.
In subactive mode, even if φW /4 is selected as the internal clock, TCF can be read from or written
to normally.
TIMTPU3B_000020020700 Rev. 1.00, 07/04, page 209 of 570
Section 12 16-Bit Timer Pulse Unit (TPU)
The H8/38086R Group have an on-chip 16-bit timer pulse unit (TPU) comprised of two 16-bit
timer channels. The function list of the TPU is shown in table 12.1. A block diagram of the TPU is
shown in figure 12.1.
12.1 Features
• Maximum 4-pulse input/output
• Selection of 7 or 8 counter input clocks for each channel
• The following operations can be set for each channel:
Waveform output at compare match
Input capture function
Counter clear operation
Multiple timer counters (TCNT) can be written to simultaneously
Simultaneous clearing by compare match and input capture is possible
Register synchronous input/output is possible by synchronous counter operation
PWM output with any duty level is possible
A maximum 3-phase PWM output is possible in combination with synchronous operation
• Operation with cascaded connection
• Fast access via internal 16-bit bus
• 6-type interrupt sources
• Register data can be transmitted automatically
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (For details, refer to section 6.4, Module Standby Function.)
Rev. 1.00, 07/04, page 210 of 570
Table 12.1 TPU Functions
Item Channel 1 Channel 2
Count clock φ/1
φ/4
φ/16
φ/64
φ/256
TCLKA
TCLKB
φ/1
φ/4
φ/16
φ/64
φ/1024
TCLKA
TCLKB
TCLKC
General registers (TGR) TGRA_1
TGRB_1
TGRA_2
TGRB_2
I/O pins TIOCA1
TIOCB1
TIOCA2
TIOCB2
Counter clear function TGR compare match or input
capture
TGR compare match or input
capture
0 output O O
1 output O O
Compare
match
output
Toggle output O O
Input capture function O O
Synchronous operation O O
PWM mode O O
Interrupt sources 3 sources
• Compare match or input
capture 1A
• Compare match or
input capture 1B
• Overflow
3 sources
• Compare match or
input capture 2A
• Compare match or
input capture 2B
• Overflow
Rev. 1.00, 07/04, page 211 of 570
Channel 2
TMDR
TSR
TCR
TIOR
TIER
Channel 1
TMDR
TSR
TCR
TIOR
TIER
TGRA
TCNT
TGRB
Control logic for channels 1 and 2
TGRA
TCNT
TGRB
Bus
interface
Common
TSYR
Control logic
TSTR
φ/1
φ/4
φ/16
φ/64
φ/256
φ/1024
TCLKA
TCLKB
TCLKC
[Legend]
TSTR:
TSYR:
TCR:
TMDR:
TCNT:
Timer start register
Timer synchro register
Timer control register
Timer mode register
Timer counter
Timer I/O control registers
Timer interrupt enable register
Timer status register
TImer general registers (A, B)
TIOCA1
TIOCB1
TIOCA2
TIOCB2
Interrupt request signals
Channel 1:
Channel 2:
Internal data bus
Module data bus
TGI1A
TGI1B
TCI1V
TGI2A
TGI2B
TCI2V
Input/output pins
Channel 1:
Channel 2:
Clock input
Internal clock:
External clock:
TIOR:
TIER:
TSR:
TGR (A, B):
Figure 12.1 Block Diagram of TPU
12.2 Input/Output Pins
Table 12.2 Pin Configuration
Channel Symbol I/O Function
Common TCLKA Input External clock A input pin
TCLKB Input External clock B input pin
TCLKC Input External clock C input pin
1 TIOCA1 I/O TGRA_1 input capture input/output compare
output/PWM output pin
TIOCB1 I/O TGRB_1 input capture input/output compare
output/PWM output pin
2 TIOCA2 I/O TGRA_2 input capture input/output compare
output/PWM output pin
TIOCB2 I/O TGRB_2 input capture input/output compare
output/PWM output pin
Rev. 1.00, 07/04, page 212 of 570
12.3 Register Descriptions
The TPU has the following registers for each channel.
Channel 1:
• Timer control register_1 (TCR_1)
• Timer mode register_1 (TMDR_1)
• Timer I/O control register_1 (TIOR_1)
• Timer interrupt enable register_1 (TIER_1)
• Timer status register_1 (TSR_1)
• Timer counter_1 (TCNT_1)
• Timer general register A_1 (TGRA_1)
• Timer general register B_1 (TGRB_1)
Channel 2:
• Timer control register_2 (TCR_2)
• Timer mode register_2 (TMDR_2)
• Timer I/O control register_2 (TIOR_2)
• Timer interrupt enable register_2 (TIER_2)
• Timer status register_2 (TSR_2)
• Timer counter_2 (TCNT_2)
• Timer general register A_2 (TGRA_2)
• Timer general register B_2 (TGRB_2)
Common:
• Timer start register (TSTR)
• Timer synchro register (TSYR)
Rev. 1.00, 07/04, page 213 of 570
12.3.1 Timer Control Register (TCR)
TCR controls TCNT operation for each channel. The TPU has a total of two TCR registers, one
for each channel. TCR should be set when TCNT operation is stopped.
Bit Bit Name
Initial
Value R/W Description
7 0 Reserved
This bit is always read as 0 and cannot be modified.
6
5
CCLR1
CCLR0
0
0
R/W
R/W
Counter Clear 1 and 0
These bits select the TCNT counter clearing source.
See table 12.3 for details.
4
3
CKEG1
CKEG0
0
0
R/W
R/W
Clock Edge 1 and 0
These bits select the input clock edge. When the
internal clock is counted using both edges, the input
clock period is halved (e.g. φ/4 both edges = φ/2 rising
edge). Internal clock edge selection is valid when the
input clock is φ/4 or slower. If the input clock is φ/1, this
setting is ignored and count at a rising edge is selected.
00: Count at rising edge
01: Count at falling edge
1X: Count at both edges
[Legend] X: Don't care
2
1
0
TPSC2
TPSC1
TPSC0
0
0
0
R/W
R/W
R/W
Timer Prescaler 2 to 0
These bits select the TCNT counter clock. The clock
source can be selected independently for each
channel. See tables12.4 and 12.5 for details.
Table 12.3 CCLR1 and CCLR 0 (Ch a nnel s 1 and 2)
Channel Bit 6
CCLR1 Bit 5
CCLR0 Description
1, 2 0 0 TCNT clearing disabled
1 TCNT cleared by TGRA compare match/input capture
1 0 TCNT cleared by TGRB compare match/input capture
1 TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous
operation*
Note: * Synchronous operation is selected by setting the SYNC bit in TSYR to 1.
Rev. 1.00, 07/04, page 214 of 570
Table 12.4 TPSC2 to TPSC0 (Channel 1)
Channel Bit 2
TPSC2 Bit 1
TPSC1 Bit 0
TPSC0 Description
1 0 0 0 Internal clock: counts on φ/1
1 Internal clock: counts on φ/4
1 0 Internal clock: counts on φ/16
1 Internal clock: counts on φ/64
1 0 0 External clock: counts on TCLKA pin input
1 External clock: counts on TCLKB pin input
1 0 Internal clock: counts on φ/256
1 Counts on TCNT_2 overflow
Table 12.5 TPSC2 to TPSC0 (Channel 2)
Channel Bit 2
TPSC2 Bit 1
TPSC1 Bit 0
TPSC0 Description
2 0 0 0 Internal clock: counts on φ/1
1 Internal clock: counts on φ/4
1 0 Internal clock: counts on φ/16
1 Internal clock: counts on φ/64
1 0 0 External clock: counts on TCLKA pin input
1 External clock: counts on TCLKB pin input
1 0 External clock: counts on TCLKC pin input
1 Internal clock: counts on φ/1024
Rev. 1.00, 07/04, page 215 of 570
12.3.2 Timer Mode Register (TMDR)
TMDR sets the operating mode for each channel. The TPU has a total of two TMDR registers, one
for each channel. TMDR should be set when TCNT operation is stopped.
Bit Bit Name
Initial
Value R/W Description
7, 6 All 1 Reserved
These bits are always read as 1 and cannot be
modified.
5, 4 All 0 Reserved
These bits are always read as 0 and cannot be
modified.
3, 2 All 0 Reserved
The write value should always be 0.
1
0
MD1
MD0
0
0
R/W
R/W
Modes 1 and 0
These bits set the timer operating mode.
See table 12.6 for details.
Table 12.6 MD3 to MD0
Bit 1
MD1 Bit 0
MD0 Description
0 0 Normal operation
1 Reserved
1 0 PWM mode 1
1 PWM mode 2
Rev. 1.00, 07/04, page 216 of 570
12.3.3 Timer I/O Control Register (TIOR)
TIOR controls TGR. The TPU has a total of two TIOR registers, one for each channel. Care is
required as TIOR is affected by the TMDR setting.
The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is
cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is
cleared to 0 is specified.
• TIOR_1, TIOR_2
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
IOB3
IOB2
IOB1
IOB0
All 0 R/W
R/W
R/W
R/W
I/O Control B3 to B0
Specify the function of TGRB.
For details, refer to tables 12.7 and 12.8.
3
2
1
0
IOA3
IOA2
IOA1
IOA0
All 0 R/W
R/W
R/W
R/W
I/O Control A3 to A0
Specify the function of TGRA.
For details, refer to tables 12.9 and 12.10.
Rev. 1.00, 07/04, page 217 of 570
Table 12.7 TIOR_1 (Channel 1)
Description
Bit 7
IOB3 Bit 6
IOB2 Bit 5
IOB1 Bit 4
IOB0 TGRB_1
Function
TIOCB1 Pin Function
0 0 0 0 Output disabled
1
Output
compare
register Initial output is 0
0 output at compare match
1 0 Initial output is 0
1 output at compare match
1 Initial output is 0
Toggle output at compare match
1 0 0 Output disabled
1 Initial output is 1
0 output at compare match
1 0 Initial output is 1
1 output at compare match
1 Initial output is 1
Toggle output at compare match
1 0 0 0 Capture input source is TIOCB1 pin
Input capture at rising edge
1 Capture input source is TIOCB1 pin
Input capture at falling edge
1 X
Input capture
register
Capture input source is TIOCB1 pin
Input capture at both edges
1 X X Setting prohibited
[Legend]
X: Don't care
Rev. 1.00, 07/04, page 218 of 570
Table 12.8 TIOR_2 (Channel 2)
Description
Bit 7
IOB3 Bit 6
IOB2 Bit 5
IOB1 Bit 4
IOB0 TGRB_2
Function
TIOCB2 Pin Function
0 0 0 0 Output disabled
1
Output
compare
register Initial output is 0
0 output at compare match
1 0 Initial output is 0
1 output at compare match
1 Initial output is 0
Toggle output at compare match
1 0 0 Output disabled
1 Initial output is 1
0 output at compare match
1 0 Initial output is 1
1 output at compare match
1 Initial output is 1
Toggle output at compare match
1 X 0 0 Capture input source is TIOCB2 pin
Input capture at rising edge
1 Capture input source is TIOCB2 pin
Input capture at falling edge
1 X
Input capture
register
Capture input source is TIOCB2 pin
Input capture at both edges
[Legend]
X: Don't care
Rev. 1.00, 07/04, page 219 of 570
Table 12.9 TIOR_1 (Channel 1)
Description
Bit 3
IOA3 Bit 2
IOA2 Bit 1
IOA1 Bit 0
IOA0 TGRA_1
Function
TIOCA1 Pin Function
0 0 0 0 Output disabled
1
Output
compare
register Initial output is 0
0 output at compare match
1 0 Initial output is 0
1 output at compare match
1 Initial output is 0
Toggle output at compare match
1 0 0 Output disabled
1 Initial output is 1
0 output at compare match
1 0 Initial output is 1
1 output at compare match
1 Initial output is 1
Toggle output at compare match
1 0 0 0 Capture input source is TIOCA1 pin
Input capture at rising edge
1 Capture input source is TIOCA1 pin
Input capture at falling edge
1 X
Input
capture
register
Capture input source is TIOCA1 pin
Input capture at both edges
1 X X Setting prohibited
[Legend]
X: Don't care
Rev. 1.00, 07/04, page 220 of 570
Table 12.10 TIOR_2 (Channel 2)
Description
Bit 3
IOA3 Bit 2
IOA2 Bit 1
IOA1 Bit 0
IOA0 TGRA_2
Function
TIOCA2 Pin Function
0 0 0 0 Output disabled
1
Output
compare
register Initial output is 0
0 output at compare match
1 0 Initial output is 0
1 output at compare match
1 Initial output is 0
Toggle output at compare match
1 0 0 Output disabled
1 Initial output is 1
0 output at compare match
1 0 Initial output is 1
1 output at compare match
1 Initial output is 1
Toggle output at compare match
1 X 0 0 Capture input source is TIOCA2 pin
Input capture at rising edge
1 Capture input source is TIOCA2 pin
Input capture at falling edge
1 X
Input capture
register
Capture input source is TIOCA2 pin
Input capture at both edges
[Legend]
X: Don't care
Rev. 1.00, 07/04, page 221 of 570
12.3.4 Timer Interrupt Enable Register (TIER)
TIER controls enabling or disabling of interrupt requests for each channel. The TPU has a total of
two TIER registers, one for each channel.
Bit Bit Name
Initial
Value R/W Description
7 0 R/W Reserved
This bit is readable/writable.
6 1 Reserved
This bit is always read as 1 and cannot be modified.
5 0 Reserved
The write value should always be 0.
4 TCIEV 0 R/W Overflow Interrupt Enable
Enables or disables interrupt requests (TCIV) by the
TCFV flag when the TCFV flag in TSR is set to 1.
0: Interrupt requests (TCIV) by TCFV disabled
1: Interrupt requests (TCIV) by TCFV enabled
3, 2 All 0 Reserved
These bits are always read as 0 and cannot be
modified.
1 TGIEB 0 R/W TGR Interrupt Enable B
Enables or disables interrupt requests (TGIB) by the
TGFB bit when the TGFB bit in TSR is set to 1.
0: Interrupt requests (TGIB) by TGFB bit disabled
1: Interrupt requests (TGIB) by TGFB bit enabled
0 TGIEA 0 R/W TGR Interrupt Enable A
Enables or disables interrupt requests (TGIA) by the
TGFA bit when the TGFA bit in TSR is set to 1.
0: Interrupt requests (TGIA) by TGFA bit disabled
1: Interrupt requests (TGIA) by TGFA bit enabled
Rev. 1.00, 07/04, page 222 of 570
12.3.5 Timer Status Register (TSR )
TSR indicates the status for each channel. The TPU has a total of two TSR registers, one for each
channel.
Bit Bit Name
Initial
Value R/W Description
7, 6 All 1 Reserved
These bits are always read as 1 and cannot be modified.
5 0 Reserved
This bit is always read as 0 and cannot be modified.
4 TCFV 0 R/(W)* Overflow Flag
Status flag that indicates that TCNT overflow has
occurred.
[Setting condition]
When the TCNT value overflows (changes from H'FFFF
to H'0000 )
[Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
3, 2 All 0 Reserved
These bits are always read as 0 and cannot be modified.
1 TGFB 0 R/(W)* Input Capture/Output Compare Flag B
Status flag that indicates the occurrence of TGRB input
capture or compare match.
[Setting conditions]
• When TCNT = TGRB and TGRB is functioning as
output compare register
• When TCNT value is transferred to TGRB by input
capture signal and TGRB is functioning as input
capture register
[Clearing condition]
• When 0 is written to TGFB after reading TGFB = 1
Rev. 1.00, 07/04, page 223 of 570
Bit Bit Name
Initial
value R/W Description
0 TGFA 0 R/(W)* Input Capture/Output Compare Flag A
Status flag that indicates the occurrence of TGRA input
capture or compare match.
[Setting conditions]
• When TCNT = TGRA and TGRA is functioning as
output compare register
• When TCNT value is transferred to TGRA by input
capture signal and TGRA is functioning as input
capture register
[Clearing condition]
• When 0 is written to TGFA after reading TGFA = 1
Note: * Only 0 can be written to clear the flag.
12.3.6 Timer Counter (TCNT)
TCNT is a 16-bit readable/writable counter. The TPU has a total of two TCNT counters, one for
each channel.
TCNT is initialized to H'0000 by a reset or in hardware standby mode.
TCNT cannot be accessed in 8-bit units; it must always be accessed in 16-bit units.
12.3.7 Timer General Register (TGR)
TGR is a 16-bit readable/writable register, functioning as either output compare or input capture
register. The TPU has a total of four TGR registers, two for each channel. TGR is initialized to
H'FFFF by a reset. TGR cannot be accessed in 8-bit units; it must always be accessed in 16-bit
units.
Rev. 1.00, 07/04, page 224 of 570
12.3.8 Timer Start Register (TSTR )
TSTR selects TCNT operation/stoppage for channels 1 and 2. TCNT starts counting for channel in
which the corresponding bit is set to 1. When setting the operating mode in TMDR or setting the
TCNT count clock in TCR, first stop the TCNT operation.
Bit Bit Name
Initial
Value R/W Description
7 to 3 All 0 Reserved
The write value should always be 0.
2
1
CST2
CST1
0
0
R/W
R/W
Counter Start 2 and 1
These bits select operation or stoppage for TCNT.
If 0 is written to the CST bit during operation with the
TIOC pin designated for output, the counter stops but the
output compare output level of the TIOC pin is retained. If
TIOR is written to when the CST bit is cleared to 0, the
pin output level will be changed to the set initial output
value.
0: TCNT_n count operation is stopped
1: TCNT_n performs count operation
(n = 2 or 1)
0 0 Reserved
The write value should always be 0.
Rev. 1.00, 07/04, page 225 of 570
12.3.9 Timer Synchro Register (TSYR)
TSYR selects independent operation or synchronous operation of TCNT for each channel.
Synchronous operation is performed for channel in which the corresponding bit in TSYR is set to
1.
Bit Bit Name
Initial
Value R/W Description
7 to 3 All 0 Reserved
The write value should always be 0.
2
1
SYNC2
SYNC1
0
0
R/W
R/W
Timer Synchro 2 and 1
These bits select whether operation is independent of
or synchronized with other channels.
When synchronous operation is selected, the TCNT
synchronous presetting of multiple channels, and
synchronous clearing by counter clearing on another
channel, are possible.
To set synchronous operation, the SYNC bits must be
set to 1. To set synchronous clearing, in addition to the
SYNC bit, the TCNT clearing source must also be set
by means of bits CCLR1 and CCLR0 in TCR.
0: TCNT_n operates independently (TCNT presetting/
clearing is unrelated to other channels)
1: TCNT_n performs synchronous operation
TCNT synchronous presetting/synchronous
clearing is possible
(n = 2 or 1)
0 0 Reserved
The write value should always be 0.
Rev. 1.00, 07/04, page 226 of 570
12.4 Interface to CPU
12.4.1 16-Bit Registers
TCNT and TGR are 16-bit registers. As the data bus to the CPU is 16 bits wide, these registers
cannot be read or written to in 8-bit units; 16-bit access must always be used.
An example of 16-bit register access operation is shown in figure 12.2.
H
L
CPU
TCNTH TCNTL
Module data bus
Bus interface
Internal data bus
Figure 12.2 16-Bit Register Access Operation [CPU ↔ TCNT (16 Bits)]
12.4.2 8-Bit Registers
Registers other than TCNT and TGR are 8-bit. As the data bus to the CPU is 16 bits wide, these
registers can be read and written to in 16-bit units. They can also be read and written to in 8-bit
units.
Examples of 8-bit register access operation are shown in figure 12.3, 12.4, and 12.5.
Bus interface
H
Internal data bus
L
CPU
Module data bus
TCR
Figure 12.3 8-Bit Register Access Operation [CPU ↔ TCR (Upper 8 Bits)]
Rev. 1.00, 07/04, page 227 of 570
Bus interface
H
Internal data bus
L
CPU
Module data bus
TMDR
Figure 12.4 8-Bit Register Access Operation [CPU ↔ TMDR (Lower 8 Bits)]
Bus interface
H
Internal data bus
L
CPU
Module data bus
TCR TMDR
Figure 12.5 8-Bit Register Access Operation [CPU ↔ TCR and TMDR (16 Bits)]
Rev. 1.00, 07/04, page 228 of 570
12.5 Operation
12.5.1 Basic Functions
Each channel has TCNT and TGR. TCNT performs up-counting, and is also capable of free-
running operation, periodic counting, and external event counting.
TGR can be used as an input capture register or output compare register.
(1) Counter Operation
When one of bits CST1 and CST2 is set to 1 in TSTR, TCNT for the corresponding channel
begins counting. TCNT can operate as a free-running counter, periodic counter, for example.
(a) Example of Count Operation Setting Procedure
Figure 12.6 shows an example of the count operation setting procedure.
Operation selection
Select counter clock
Periodic counter
Select counter clearing source
Select output compare register
Set period
Free-running counter
Start count operation
<Free-running counter><Periodic counter>
Start count operation
Select the counter
clock with bits
TPSC2 to TPSC0 in
TCR. At the same
time, select the
input clock edge
with bits CKEG1
and CKEG0 in TCR.
For periodic counter
operation, select
TGR to be used as
the TCNT clearing
source with bits
CCLR1 and CCLR0 in
TCR.
Designate TGR
selected in [2] as an
output compare
register by means of
TIOR.
Set the periodic
counter cycle in
TGR selected in [2].
Set the CST bit in
TSTR to 1 to start
the counter
operation.
[1]
[1]
[2]
[2]
[3][3]
[4]
[4]
[5]
[5]
Figure 12.6 Example of Counter Oper ation Setting Pr ocedure
Rev. 1.00, 07/04, page 229 of 570
(b) Free-Running Count Operation and Periodic Count Operation
Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters.
When the relevant bit in TSTR is set to 1, the corresponding TCNT starts up-count operation as a
free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is
set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests
an interrupt. After overflow, TCNT starts counting up again from H'0000.
Figure 12.7 illustrates free-running counter operation.
TCNT value
H'FFFF
H'0000
CST bit
TCFV
Time
Figure 12.7 Free-Running Counter Operation
When compare match is selected as the TCNT clearing source, TCNT for the relevant channel
performs periodic count operation. TGR for setting the period is designated as an output compare
register, and counter clearing by compare match is selected by means of bits CCLR0 and CCLR1
in TCR. After the settings have been made, TCNT starts up-count operation as a periodic counter
when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR,
the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000.
If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt.
After a compare match, TCNT starts counting up again from H'0000.
Figure 12.8 illustrates periodic counter operation.
TCNT value
TGR
H'0000
CST bit
TGF
Time
Counter cleared by TGR
compare match
Flag cleared by software
Figure 12.8 Periodic Counter Operation
Rev. 1.00, 07/04, page 230 of 570
(2) Waveform Outpu t by Co mp are Ma t c h
The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare
match.
(a) Example of Setting Procedure for Waveform Output by Compare Match
Figure 12.9 shows an example of the setting procedure for waveform output by compare match.
Input selection
Select waveform output mode
Start count operation
< Waveform output >
Select 0 output or 1 output for initial value, and
0 output, 1 output, or toggle output, by for compare
match output value means of TIOR. The set
initial value is output at the TIOC pin until the
first compare match occurs.
Set the timing for compare match generation in
TGR.
Set the CST bit in TSTR to 1 to start the count
operation.
[1]
[2]
[1]
[2] Set output timing
[3]
[3]
Figure 12.9 Example of Setting Procedure for Waveform Output by Compare Match
(b) Examples of Waveform Output Operation
Figure 12.10 shows an example of 0 output/1 output.
In this example, TCNT has been designated as a free-running counter, and settings have been
made such that 1 is output by compare match A, and 0 is output by compare match B. When the
set level and the pin level match, the pin level does not change.
TCNT value
H'FFFF
H'0000
TIOCA
TIOCB
Time
TGRA
TGRB
No change No change
No change No change
1 output
0 output
Figure 12.10 Example of 0 Output/1 Output Operation
Rev. 1.00, 07/04, page 231 of 570
Figure 12.11 shows an example of toggle output.
In this example, TCNT has been designated as a periodic counter (with counter clearing on
compare match B), and settings have been made such that the output is toggled by both compare
match A and compare match B.
TCNT value
H'FFFF
H'0000
TIOCB
TIOCA
Time
TGRB
TGRA
Toggle output
Toggle output
Counter cleared by TGRB compare match
Figure 12.11 Example of Toggle Output Operation
(3) Input Capture Function
The TCNT value can be transferred to TGR on detection of the TIOC pin input edge.
Rising edge, falling edge, or both edges can be selected as the detected edge.
(a) Example of Input Capture Operation Setting Procedure
Figure 12.12 shows an example of the setting procedure for input capture operation.
Input selection
Select input capture input
Start count
<Input capture operation>
Designate TGR as an input capture register by
means of TIOR, and select the input capture source
and, rising edge, falling edge, or both edges as the
input signal edge.
Set the CST bit in TSTR to 1 to start the count
operation.
[1]
[2]
[1]
[2]
Figure 12.12 Example of Setting Procedure for Input Capture Operation
Rev. 1.00, 07/04, page 232 of 570
(b) Example of Input Capture Operation
Figure 12.13 shows an example of input capture operation.
In this example, both rising and falling edges have been selected as the input capture input edge of
the TIOCA pin, the falling edge has been selected as the input capture input edge of the TIOCB
pin, and counter clearing by TGRB input capture has been designated for TCNT.
TCNT value
H'0180
H'0000
TIOCA
TGRA
H'0010
H'0005
Counter cleared by TIOCB
input (falling edge)
H'0160
H'0005 H'0160 H'0010
TGRB H'0180
TIOCB
Time
Figure 12.13 Example of Input Capture Operation
Rev. 1.00, 07/04, page 233 of 570
12.5.2 Synchronous Operation
In synchronous operation, the values in multiple TCNT counters can be rewritten simultaneously
(synchronous presetting). Also, multiple TCNT counters can be cleared simultaneously by making
the appropriate setting in TCR (synchronous clearing).
Synchronous operation enables TGR to be incremented with respect to a single time base.
Synchronous operation can be set for each channel.
(1) Example of Synchronous Operation Setting Procedure
Figure 12.14 shows an example of the synchronous operation setting procedure.
No
Yes
Synchronous operation
selection
Set synchronous
operation
Synchronous presetting
Set TCNT
<Synchronous presetting> <Counter clearing> <Synchronous clearing>
Synchronous clearing
Clearing
source generation
channel?
Select counter
clearing source
Start count
Set synchronous
counter clearing
Start count
Set 1 to the SYNC bits in TSYR corresponding to the channels to be designated for synchronous
operation.
When the TCNT counter of any of the channels designated for synchronous operation is
written to, the same value is simultaneously written to the other TCNT counters.
Use bits CCLR1 and CCLR0 in TCR to specify TCNT clearing by input capture/output compare,
etc.
Use bits CCLR1 and CCLR0 in TCR to designate synchronous clearing for the counter clearing
source.
Set 1 to the CST bits in TSTR for the relevant channels, to start the count operation.
[1]
[2]
[3]
[4]
[5]
[1]
[3]
[5]
[4]
[5]
[2]
Figure 12.14 Example of Synchronous Operation Setting Procedure
Rev. 1.00, 07/04, page 234 of 570
(2) Example of Synchronous Operation
Figure 12.15 shows an example of synchronous operation.
In this example, synchronous operation and PWM mode 1 have been designated for channels 1
and 2, TGRB_1 compare match has been set as the channel 1 counter clearing source, and
synchronous clearing has been set for the channel 2 counter clearing source.
Two-phase PWM waveforms are output from pins TIOC1A and TIOC2A. At this time,
synchronous presetting, and synchronous clearing by TGRB_1 compare match, are performed for
channel 1 and 2 TCNT counters, and the data set in TGRB_1 is used as the PWM cycle.
For details on PWM modes, see section 12.5.4, PWM Modes.
TCNT_1 and TCNT_2
H'0000
TIOCA1
Time
Synchronous clearing by TGRB_1 compare match
TGRA_2
TGRA_1
TGRB_2
TGRB_1
TIOCA2
Figure 12.15 Example of Synchronous Operation
Rev. 1.00, 07/04, page 235 of 570
12.5.3 Operation with Cascaded Connection
Operation as a 32-bit counter can be performed by cascading two 16-bit counter channels.
This function is enabled when the TPSC2 to TPSC0 bits in TCR are set to count on TCNT2
overflow for the channel 1 counter clock.
Table 12.11 shows the counter combination used in operation with the cascaded connection.
Table 12.11 Counter Combination in Operation with Cascaded Connection
Combination Upper 16 bits Lower 16 bits
Channel 1 and channel 2 TCNT1 TCNT2
(1) Setting Procedure for Operation with Cascaded Connection
Figure 12.16 shows the setting procedure for cascaded connection operation.
Operation with cascaded
connection
[1]
[1] Set bits TPSC2 to TPSC0 in TCR in
channel 1 to B'111 to select to count
on TCNT2 overflow.
[2] Set 1 to the CST bit in TSTR corresponding
the upper and lower channels to start
counting.
[2]
<Operation with cascaded connection>
Set operation with cascaded
connection
Start count
Figure 12.16 Setting Procedure for Operation with Cascaded Operation
Rev. 1.00, 07/04, page 236 of 570
(2) Example of Operation with Cascaded Connection
Figure 12.17 shows an example of operation with cascaded connection, where TCNT1 is set to
count TCNT2 overflow, TCRA_1 and TCRA_2 are set to be input capture registers, and the TIOC
pin rising edge is selected.
If rising edges are input simultaneously to the TIOCA1 and TIOCA2 pins, the upper 16 bits of 32-
bit data are transferred to TGRA_1 and the lower 16 bits are transferred to TGRA_2.
TIOCA1
TIOCA2
TCNT2
TCNT1
TCNT1
clock
TCNT2
clock
H'03A2H'03A1
H'FFFF H'0000 H'0001
TGRA_1 H'03A2
H'0000
TGRA_2
Figure 12.17 Example of Operation with Cascaded Connection
Rev. 1.00, 07/04, page 237 of 570
12.5.4 PWM Modes
In PWM mode, PWM waveforms are output from the output pins. The output level can be selected
as 0, 1, or toggle output in response to a compare match of each TGR.
Designating TGR compare match as the counter clearing source enables the period to be set in that
register. All channels can be designated for PWM mode independently. Synchronous operation is
also possible.
There are two PWM modes, as described below.
(1) PWM Mode 1
PWM output is generated from the TIOCA pin by pairing TGRA with TGRB. The level specified
by bits IOA0 to IOA3 in TIOR is output from the TIOCA pin at compare match A, and the level
specified by bits IOB0 to IOB3 in TIOR is output at compare match B. The initial output value is
the value set in TGRA. If the set values of paired TGRs are identical, the output value does not
change even if a compare match occurs.
In PWM mode 1, PWM output is enabled up to 2 phases.
(2) PWM Mode 2
PWM output is generated using one TGR as the cycle register and the others as duty registers. The
output specified in TIOR is performed by means of compare matches. Upon counter clearing by a
synchronization register compare match, the output value of each pin is the initial value set in
TIOR. If the set values of the cycle and duty registers are identical, the output value does not
change even if a compare match occurs.
In PWM mode 2, PWM output is enabled up to 3 phases.
The correspondence between PWM output pins and registers is shown in table 12.12.
Table 12.12 PWM Output Registers and Output Pins
Output Pins
Channel Registers PWM Mode 1 PWM Mode 2*
1 TGRA_1 TIOCA1 TIOCA1
TGRB_1 TIOCB1
2 TGRA_2 TIOCA2 TIOCA2
TGRB_2 TIOCB2
Note: * In PWM mode 2, PWM output is not possible for TGR in which the period is set.
Rev. 1.00, 07/04, page 238 of 570
(3) Example of PWM Mode Setting Procedure
Figure 12.18 shows an example of the PWM mode setting procedure.
PWM mode
Select counter clock
Select counter clearing source
Select waveform output level
Set TGR
Set PWM mode
Start count
<PWM mode>
Select the counter clock with bits TPSC2 to
TPSC0 in TCR. At the same time, select the
input clock edge with bits CKEG1 and CKEG0
in TCR.
Use bits CCLR1 and CCLR0 in TCR to select the
TGR to be used as the TCNT clearing source.
Use TIOR to designate the TGR as an output
compare register, and select the initial value and
output value.
Set the cycle in the TGR selected in [2], and set
the duty in the other TGR.
Select the PWM mode with bits MD3 to MD0 in
TMDR.
Set the CST bit in TSTR to 1 start the count
operation.
[1]
[2]
[3]
[4]
[5]
[6]
[1]
[2]
[3]
[4]
[5]
[6]
Figure 12.18 Example of PWM Mode Setting Procedure
(4) Examples of PWM Mode Operation
Figure 12.19 shows an example of PWM mode 1 operation. In this example, TGRA compare
match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output
value, and 1 is set as the TGRB output value.
In this case, the value set in TGRA is used as the period, and the values set in TGRB are used as
the duty levels.
TCNT value
TGRA
H'0000
TIOCA
Time
TGRB
Counter cleared by
TGRA compare match
Figure 12.19 Example of PWM Mode Operation (1)
Rev. 1.00, 07/04, page 239 of 570
Figure 12.20 shows an example of PWM mode 2 operation. In this example, synchronous
operation is designated for channels 1 and 2, TGRB_1 compare match is set as the TCNT clearing
source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers
(TGRA_1, TGRB_1, and TGRA_2), outputting a 3-phase PWM waveform.
In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs are
used as the duty levels.
TCNT_1 and TCNT_2
Synchronous clearing by
TGRB_2 compare match
Time
H'0000
TIOCA1
TGRA_1
TGRB_1
TGRA_2
TGRB_2
TIOCB1
TIOCA2
Figure 12.20 Example of PWM Mode Operation (2)
Rev. 1.00, 07/04, page 240 of 570
Figure 12.21 shows examples of PWM waveform output with 0% duty and 100% duty in PWM
mode.
TCNT value
TGRA
H'0000
TIOCA
Time
TGRB
0% duty
TGRB rewritten
TGRB
rewritten
TGRB rewritten
TCNT value
TGRA
H'0000
TIOCA
Time
TGRB
100% duty
TGRB rewritten
TGRB rewritten
TGRB rewritten
Output does not change when cycle register and duty register
compare matches occur simultaneously
TCNT value
TGRA
H'0000
TIOCA
Time
TGRB
100% duty
TGRB rewritten
TGRB rewritten
TGRB rewritten
Output does not change when cycle register and duty
register compare matches occur simultaneously
0% duty
Figure 12.21 Example of PWM Mode Operation (3)
Rev. 1.00, 07/04, page 241 of 570
12.6 Interrupt Sources
There are two kinds of TPU interrupt source; TGR input capture/compare match and TCNT
overflow. Each interrupt source has its own status flag and enable/disable bit, allowing the
generation of interrupt request signals to be enabled or disabled individually.
When an interrupt source is generated, the corresponding status flag in TSR is set to 1. If the
corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The
interrupt request is cleared by clearing the status flag to 0.
Channel priority can be changed by the interrupt controller, however the priority within a channel
is fixed. For details, see section 4, Interrupt Controller.
Table 12.13 lists the TPU interrupt sources.
Table 12.13 TPU Interrupts
Channel Name Interrupt Source Interrupt Flag Priority
1 TGI1A TGRA_1 input capture/compare match TGFA_1 High
TGI1B TGRB_1 input capture/compare match TGFB_1
TCI1V TCNT_1 overflow TCFV_1
2 TGI2A TGRA_2 input capture/compare match TGFA_2
TGI2B TGRB_2 input capture/compare match TGFB_2
TCI2V TCNT_2 overflow TCFV_2 Low
(1) Input Capture/Compare Match Interrupt
An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1
by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt
request is cleared by clearing the TGF flag to 0. The TPU has a total of four input capture/compare
match interrupts, two for each channel.
(2) Overflow Interrupt
An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to
1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing
the TCFV flag to 0. The TPU has a total of two overflow interrupts, one for each channel.
Rev. 1.00, 07/04, page 242 of 570
12.7 Operation Timing
12.7.1 Input/Output Timing
(1) TCNT Count Timing
Figure 12.22 shows TCNT count timing in internal clock operation, and figure 12.23 shows TCNT
count timing in external clock operation.
TCNT
TCNT
input clock
Internal clock
φ
N-1 N N+1 N+2
Falling edge Rising edge
Figure 12.22 Count Timing in Internal Clock Operation
TCNT
TCNT
input clock
External clock
φ
N-1 N N+1 N+2
Falling edge Rising edge Falling edge
Figure 12.23 Count Timing in External Clock Operation
Rev. 1.00, 07/04, page 243 of 570
(2) Output Compare Output Timing
A compare match signal is generated in the last state in which TCNT and TGR match (the point at
which the count value matched by TCNT is updated). When a compare match signal is generated,
the output value set in TIOR is output at the output compare output pin (TIOC pin). After a match
between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is
generated.
Figure 12.24 shows output compare output timing.
TGR
TCNT
TCNT
input clock
N
NN+1
Compare
match signal
TIOC pin
φ
Figure 12.24 Output Compare Output Timing
(3) Input Capture Signal Timing
Figure 12.25 shows input capture signal timing.
TCNT
Input capture
input
NN+1 N+2
N N+2
TGR
Input capture
signal
φ
Figure 12.25 Input Capture Input Signal Timing
Rev. 1.00, 07/04, page 244 of 570
(4) Timing for Counter Clearing by Compare Match/Inpu t Capture
Figure 12.26 shows the timing when counter clearing on compare match is specified, and figure
12.27 shows the timing when counter clearing on input capture is specified.
TCNT
Counter
clear signal
Compare
match signal
TGR N
NH'0000
φ
Figure 12.26 Counter Clear Timing (Compare Match)
TCNT
Counter clear
signal
Input capture
signal
TGR
NH'0000
N
φ
Figure 12.27 Counter Clear Timing (Input Capture)
Rev. 1.00, 07/04, page 245 of 570
12.7.2 Interrupt Signal Timing
(1) TGF Flag Setting Timing in Case of Compare Match
Figure 12.28 shows the timing for setting of the TGF flag in TSR on compare match, and TGI
interrupt request signal timing.
TGR
TCNT
TCNT input
clock
N
NN+1
Compare
match signal
TGF flag
TGI interrupt
φ
Figure 12.28 TGI Interrupt Timing (Compare Match)
(2) TGF Flag Setting Timing in Case of Input Capture
Figure 12.29 shows the timing for setting of the TGF flag in TSR on input capture, and TGI
interrupt request signal timing.
TGR
TCNT
Input capture
signal
N
N
TGF flag
TGI interrupt
φ
Figure 12.29 TGI Interrupt Timing (Input Capture)
Rev. 1.00, 07/04, page 246 of 570
(3) TCFV Flag Setting Timing
Figure 12.30 shows the timing for setting of the TCFV flag in TSR on overflow, and TCIV
interrupt request signal timing.
Overflow
signal
TCNT
(overflow)
TCNT input
clock
H'FFFF H'0000
TCFV flag
TCIV interrupt
φ
Figure 12.30 TCIV Interrupt Setting Timing
(4) Status Flag Clearing Timing
After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. Figure 12.31 shows the
timing for status flag clearing by the CPU.
Status flag
Write signal
Address TSR address
Interrupt
request
signal
TSR write cycle
φ
T
1
T
2
Figure 12.31 Timing for Status Flag Clearing by CPU
Rev. 1.00, 07/04, page 247 of 570
12.8 Usage Notes
12.8.1 Module Standby Function Setting
TPU operation can be disabled or enabled using the clock stop register. The initial setting is for
the TPU to operate. Register access is enabled by clearing the module standby function. For
details, refer to section 6.4, Module Standby Function.
12.8.2 Input Clock Restrictions
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection. The TPU will not operate properly at narrower
pulse widths.
12.8.3 Caution on Period Setting
When counter clearing on compare match is set, TCNT is cleared in the last state in which it
matches the TGR value (the point at which the count value matched by TCNT is updated).
Consequently, the actual counter frequency is given by the following formula:
f =
φ
(N + 1)
Where f: Counter frequency
φ: Operating frequency
N: TGR set value
Rev. 1.00, 07/04, page 248 of 570
12.8.4 Contention between TCNT Write and Clear Operation
If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes
priority and the TCNT write is not performed.
Figure 12.32 shows the timing in this case.
Counter clear
signal
Write signal
Address
φ
TCNT address
TCNT
TCNT write cycle
T1T2
N H'0000
Figure 12.32 Contention between TCNT Write and Clear Operation
12.8.5 Contention between TCNT Write and Increment Operation
If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes priority and
TCNT is not incremented.
Figure 12.33 shows the timing in this case.
TCNT input
clock
Write signal
Address
φ
TCNT address
TCNT
TCNT write cycle
NM
TCNT write data
T
1
T
2
Figure 12.33 Contention between TCNT Write and Increment Operation
Rev. 1.00, 07/04, page 249 of 570
12.8.6 Contention between TGR Write and Co mpare Match
If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes priority and
the compare match signal is inhibited. A compare match does not occur even if the previous value
is written.
Figure 12.34 shows the timing in this case.
Compare
match signal
Write signal
Address
φ
TGR address
TCNT
TGR write cycle
T
1
T
2
NM
TGR write data
TGR
N N+1
Inhibited
Figure 12.34 Contention between TGR Write and Compare Match
Rev. 1.00, 07/04, page 250 of 570
12.8.7 Contention between TGR Read and Input Capture
If an input capture signal is generated in the T1 state of a TGR read cycle, data that is read will be
data after input capture transfer.
Figure 12.35 shows the timing in this case.
Input capture
signal
Read signal
Address
φ
TGR address
TGR
TGR read cycle
T
1
T
2
M
Internal
data bus
X M
Figure 12.35 Contention between TGR Read and Input Capture
12.8.8 Contention between TGR Write and Input Capture
If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture
operation takes priority and the write to TGR is not performed.
Figure 12.36 shows the timing in this case.
Input capture
signal
Write signal
Address
φ
TCNT
TGR write cycle
T1T2
M
TGR
M
TGR address
Figure 12.36 Contention between TGR Write and Input Capture
Rev. 1.00, 07/04, page 251 of 570
12.8.9 Contention between Overflow and Counter Clearing
If overflow and counter clearing occur simultaneously, the TCFV flag in TSR is not set and TCNT
clearing takes priority.
Figure 12.37 shows the operation timing when a TGR compare match is specified as the clearing
source, and when H'FFFF is set in TGR.
Counter
clear signal
TCNT input
clock
φ
TCNT
TGF
TCFV Disabled
H'FFFF H'0000
Figure 12.37 Contention between Overflow and Counter Clearing
12.8.10 Contention between TCNT Write and Overflow
If there is an up-count in the T2 state of a TCNT write cycle and overflow occurs, the TCNT write
takes priority and the TCFV flag in TSR is not set.
Figure 12.38 shows the operation timing when there is contention between TCNT write and
overflow.
Write signal
Address
φ
TCNT address
TCNT
TCNT write cycle
T1T2
H'FFFF M
TCNT write data
TCFV flag
Figure 12.38 Contention between TCNT Write and Overflow
Rev. 1.00, 07/04, page 252 of 570
12.8.11 Multiplexing of I/O Pins
The TIOCA1 I/O pin is multiplexed with the TCLKA input pin, the TIOCB1 I/O pin with the
TCLKB input pin, and the TIOCA2 I/O pin with the TCLKC input pin. When an external clock is
input, compare match output should not be performed from a multiplexed pin.
12.8.12 Interrupts when Module Standby Function is Used
If the module standby function is used when an interrupt has been requested, it will not be possible
to clear the CPU interrupt source. Interrupts should therefore be disabled before using the module
standby function.
Rev. 1.00, 07/04, page 253 of 570
Section 13 Asynchronous Event Counter (AEC)
The asynchronous event counter (AEC) is an event counter that is incremented by external event
clock or internal clock input. Figure 13.1 shows a block diagram of the asynchronous event
counter.
13.1 Features
• Can count asynchronous events
Can count external events input asynchronously without regard to the operation of system
clocks (φ) or subclocks (φSUB).
• Can be used as two-channel independent 8-bit event counter or single-channel independent 16-
bit event counter.
• Event/clock input is enabled when IRQAEC goes high or event counter PWM output
(IECPWM) goes high.
• Both edge sensing can be used for IRQAEC or event counter PWM output (IECPWM)
interrupts. When the asynchronous counter is not used, they can be used as independent
interrupts.
• When an event counter PWM is used, event clock input enabling/disabling can be controlled at
a constant cycle.
• Selection of four clock sources
Three internal clocks (φ/2, φ/4, or φ/8) or external event can be selected.
• Both edge counting is possible for the AEVL and AEVH pins.
• Counter resetting and halting of the count-up function can be controlled by software.
• Automatic interrupt generation on detection of an event counter overflow
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (For details, refer to section 6.4, Module Standby Function.)
• The IRQAEC pin can select the on-chip oscillator and the system clock oscillator during a
reset, though this function does not apply to a reset by the watchdog timer. (Supported only by
the masked ROM version.)
Rev. 1.00, 07/04, page 254 of 570
IECPWM
AEVH
AEVL
IRQAEC
ECCR
PSS
ECCSR
Internal data bus
OVH
OVL
ECPWCR
ECPWDR
AEGSR
ECH
(8 bits) CK
ECL
(8 bits) CK
IRREC
To CPU interrupt
(IRREC2)
Edge sensing
circuit
Edge sensing
circuit
Edge sensing
circuit
PWM waveform generator
φ
φ/2
φ/4, φ/8
φ/2, φ/4,
φ/8, φ/16,
φ/32, φ/64
[Legend]
ECPWCR:
ECPWDR:
AEGSR:
ECCSR:
Event counter PWM compare register
Event counter PWM data register
Input pin edge select register
Event counter control/status register
ECL:
ECCR:
ECH:
Event counter L
Event counter control register
Event counter H
Figure 13.1 Block Diagram of Asynchronous Event Counter
13.2 Input/Output Pins
Table 13.1 shows the pin configuration of the asynchronous event counter.
Table 13.1 Pin Configuration
Name Abbreviation I/O Function
Asynchronous event
input H
AEVH Input Event input pin for input to event counter H
Asynchronous event
input L
AEVL Input Event input pin for input to event counter L
Event input enable
interrupt input
IRQAEC Input Input pin for interrupt enabling event input
Input pin to select the on-chip oscillator and the
system clock oscillator (supported only by the
masked ROM version)
Rev. 1.00, 07/04, page 255 of 570
13.3 Register Descriptions
The asynchronous event counter has the following registers.
• Event counter PWM compare register (ECPWCR)
• Event counter PWM data register (ECPWDR)
• Input pin edge select register (AEGSR)
• Event counter control register (ECCR)
• Event counter control/status register (ECCSR)
• Event counter H (ECH)
• Event counter L (ECL)
13.3.1 Event Counter PWM Compare Register (ECPWCR)
ECPWCR sets the one conversion period of the event counter PWM waveform.
Bit Bit Name
Initial
Value R/W Description
15 ECPWCR15 1 R/W
14 ECPWCR14 1 R/W
13 ECPWCR13 1 R/W
12 ECPWCR12 1 R/W
11 ECPWCR11 1 R/W
10 ECPWCR10 1 R/W
9 ECPWCR9 1 R/W
8 ECPWCR8 1 R/W
7 ECPWCR7 1 R/W
6 ECPWCR6 1 R/W
5 ECPWCR5 1 R/W
4 ECPWCR4 1 R/W
3 ECPWCR3 1 R/W
2 ECPWCR2 1 R/W
1 ECPWCR1 1 R/W
0 ECPWCR0 1 R/W
One Conversion Period of Event Counter PWM
Waveform
When the ECPWME bit in AEGSR is 1, the event
counter PWM is operating and therefore ECPWCR
should not be modified.
When changing the conversion period, the event counter
PWM must be halted by clearing the ECPWME bit in
AEGSR to 0 before modifying ECPWCR.
Rev. 1.00, 07/04, page 256 of 570
13.3.2 Event Counter PWM Data Regi ster (ECPWDR)
ECPWDR controls data of the event counter PWM waveform generator.
Bit Bit Name
Initial
Value R/W Description
15 ECPWDR15 0 W
14 ECPWDR14 0 W
13 ECPWDR13 0 W
12 ECPWDR12 0 W
11 ECPWDR11 0 W
10 ECPWDR10 0 W
9 ECPWDR9 0 W
8 ECPWDR8 0 W
7 ECPWDR7 0 W
6 ECPWDR6 0 W
5 ECPWDR5 0 W
4 ECPWDR4 0 W
3 ECPWDR3 0 W
2 ECPWDR2 0 W
1 ECPWDR1 0 W
0 ECPWDR0 0 W
Data Control of Event Counter PWM Waveform
Generator
When the ECPWME bit in AEGSR is 1, the event
counter PWM is operating and therefore ECPWDR
should not be modified.
When changing the conversion cycle, the event counter
PWM must be halted by clearing the ECPWME bit in
AEGSR to 0 before modifying ECPWDR.
Rev. 1.00, 07/04, page 257 of 570
13.3.3 Input Pin Edge Select Register (AEGSR)
AEGSR selects rising, falling, or both edge sensing for the AEVH, AEVL, and IRQAEC pins.
Bit Bit Name
Initial
Value R/W Description
7
6
AHEGS1
AHEGS0
0
0
R/W
R/W
AEC Edge Select H
Select rising, falling, or both edge sensing for the AEVH
pin.
00: Falling edge on AEVH pin is sensed
01: Rising edge on AEVH pin is sensed
10: Both edges on AEVH pin are sensed
11: Setting prohibited
5
4
ALEGS1
ALEGS0
0
0
R/W
R/W
AEC Edge Select L
Select rising, falling, or both edge sensing for the AEVL
pin.
00: Falling edge on AEVL pin is sensed
01: Rising edge on AEVL pin is sensed
10: Both edges on AEVL pin are sensed
11: Setting prohibited
3
2
AIEGS1
AIEGS0
0
0
R/W
R/W
IRQAEC Edge Select
Select rising, falling, or both edge sensing for the
IRQAEC pin.
00: Falling edge on IRQAEC pin is sensed
01: Rising edge on IRQAEC pin is sensed
10: Both edges on IRQAEC pin are sensed
11: Setting prohibited
1 ECPWME 0 R/W Event Counter PWM Enable
Controls operation of event counter PWM and selection
of IRQAEC.
0: AEC PWM halted, IRQAEC selected
1: AEC PWM enabled, IRQAEC not selected
0 0 R/W Reserved
This bit can be read from or written to. However, this bit
should not be set to 1.
Rev. 1.00, 07/04, page 258 of 570
13.3.4 Event Counter Control Register (ECCR)
ECCR controls the counter input clock and IRQAEC/IECPWM.
Bit Bit Name
Initial
Value R/W Description
7
6
ACKH1
ACKH0
0
0
R/W
R/W
AEC Clock Select H
Select the clock used by ECH.
00: AEVH pin input
01: φ/2
10: φ/4
11: φ/8
5
4
ACKL1
ACKL0
0
0
R/W
R/W
AEC Clock Select L
Select the clock used by ECL.
00: AEVL pin input
01: φ/2
10: φ/4
11: φ/8
3
2
1
PWCK2
PWCK1
PWCK0
0
0
0
R/W
R/W
R/W
Event Counter PWM Clock Select
Select the event counter PWM clock.
000: φ/2
001: φ/4
010: φ/8
011: φ/16
1X0: φ/32
1X1 φ/64
0 0 R/W Reserved
This bit can be read from or written to. However, this bit
should not be set to 1.
[Legend] X: Don't care.
Rev. 1.00, 07/04, page 259 of 570
13.3.5 Event Counter Control/Status Register (ECCSR)
ECCSR controls counter overflow detection, counter resetting, and count-up function.
Bit Bit Name
Initial
Value R/W Description
7 OVH 0 R/W* Counter Overflow H
This is a status flag indicating that ECH has overflowed.
[Setting condition]
When ECH overflows from H'FF to H'00
[Clearing condition]
When this bit is written to 0 after reading OVH = 1
6 OVL 0 R/W* Counter Overflow L
This is a status flag indicating that ECL has overflowed.
[Setting condition]
When ECL overflows from H'FF to H'00 while CH2 is set
to 1
[Clearing condition]
When this bit is written to 0 after reading OVL = 1
5 0 R/W Reserved
Although this bit is readable/writable, it should not be set
to 1.
4 CH2 0 R/W Channel Select
Selects how ECH and ECL event counters are used
0: ECH and ECL are used together as a single-channel
16-bit event counter
1: ECH and ECL are used as two-channel 8-bit event
counter
3 CUEH 0 R/W Count-Up Enable H
Enables event clock input to ECH.
0: ECH event clock input is disabled (ECH value is
retained)
1: ECH event clock input is enabled
Rev. 1.00, 07/04, page 260 of 570
Bit Bit Name
Initial
Value R/W Description
2 CUEL 0 R/W Count-Up Enable L
Enables event clock input to ECL.
0: ECL event clock input is disabled (ECL value is
retained)
1: ECL event clock input is enabled
1 CRCH 0 R/W Counter Reset Control H
Controls resetting of ECH.
0: ECH is reset
1: ECH reset is cleared and count-up function is
enabled
0 CRCL 0 R/W Counter Reset Control L
Controls resetting of ECL.
0: ECL is reset
1: ECL reset is cleared and count-up function is enabled
Note: * Only 0 can be written to clear the flag.
Rev. 1.00, 07/04, page 261 of 570
13.3.6 Event Counter H (ECH)
ECH is an 8-bit read-only up-counter that operates as an independent 8-bit event counter. ECH
also operates as the upper 8-bit up-counter of a 16-bit event counter configured in combination
with ECL.
Bit Bit Name
Initial
Value R/W Description
7 ECH7 0 R
6 ECH6 0 R
5 ECH5 0 R
4 ECH4 0 R
3 ECH3 0 R
2 ECH2 0 R
1 ECH1 0 R
0 ECH0 0 R
Either the external asynchronous event AEVH pin, φ/2,
φ/4, or φ/8, or the overflow signal from lower 8-bit
counter ECL can be selected as the input clock source.
ECH can be cleared to H'00 by software.
13.3.7 Event Counter L (ECL)
ECL is an 8-bit read-only up-counter that operates as an independent 8-bit event counter. ECL
also operates as the upper 8-bit up-counter of a 16-bit event counter configured in combination
with ECH.
Bit Bit Name
Initial
Value R/W Description
7 ECL7 0 R
6 ECL6 0 R
5 ECL5 0 R
4 ECL4 0 R
3 ECL3 0 R
2 ECL2 0 R
1 ECL1 0 R
0 ECL0 0 R
Either the external asynchronous event AEVL pin, φ/2,
φ/4, or φ/8 can be selected as the input clock source.
ECL can be cleared to H'00 by software.
Rev. 1.00, 07/04, page 262 of 570
13.4 Operation
13.4.1 16-Bit Counter Operation
When bit CH2 is cleared to 0 in ECCSR, ECH and ECL operate as a 16-bit event counter.
Any of four input clock sources—φ/2, φ/4, φ/8, or AEVL pin input—can be selected by means of
bits ACKL1 and ACKL0 in ECCR. When AEVL pin input is selected, input sensing is selected
with bits ALEGS1 and ALEGS0.
Note that the input clock is enabled when IRQAEC is high or IECPWM is high. When IRQAEC is
low or IECPWM is low, the input clock is not input to the counter, which therefore does not
operate. Figure 13.2 shows the software procedure when ECH and ECL are used as a 16-bit event
counter.
Clear CH2 to 0
Set ACKL1, ACKL0, ALEGS1, and ALEGS0
Clear CUEH, CUEL, CRCH, and CRCL to 0
Clear OVH and OVL to 0
Set CUEH, CUEL, CRCH, and CRCL to 1
Start
End
Figure 13.2 Software Procedure when Using ECH and ECL as 16-Bit Event Counter
As CH2 is cleared to 0 by a reset, ECH and ECL operate as a 16-bit event counter after a reset,
and as ACKL1 and ACKL0 are cleared to B'00, the operating clock is asynchronous event input
from the AEVL pin (using falling edge sensing).
When the next clock is input after the count value reaches H'FF in both ECH and ECL, ECH and
ECL overflow from H'FFFF to H'0000, the OVH flag is set to 1 in ECCSR, the ECH and ECL
count values each return to H'00, and counting up is restarted. When an overflow occurs, the
IRREC bit is set to 1 in IRR2. If the IENEC bit in IENR2 is 1 at this time, an interrupt request is
sent to the CPU.
Rev. 1.00, 07/04, page 263 of 570
13.4.2 8-Bit Counter Operation
When bit CH2 is set to 1 in ECCSR, ECH and ECL operate as independent 8-bit event counters.
φ/2, φ/4, φ/8, or AEVH pin input can be selected as the input clock source for ECH by means of
bits ACKH1 and ACKH0 in ECCR, and φ/2, φ/4, φ/8, or AEVL pin input can be selected as the
input clock source for ECL by means of bits ACKL1 and ACKL0 in ECCR. Input sensing is
selected with bits AHEGS1 and AHEGS0 when AEVH pin input is selected, and with bits
ALEGS1 and ALEGS0 when AEVL pin input is selected.
Note that the input clock is enabled when IRQAEC is high or IECPWM is high. When IRQAEC is
low or IECPWM is low, the input clock is not input to the counter, which therefore does not
operate. Figure 13.3 shows the software procedure when ECH and ECL are used as 8-bit event
counters.
Set CH2 to 1
Set ACKH1, ACKH0, ACKL1, ACKL0,
AHEGS1, AHEGS0, ALEGS1, and ALEGS0
Clear CUEH, CUEL, CRCH, and CRCL to 0
Clear OVH and OVL to 0
Set CUEH, CUEL, CRCH, and CRCL to 1
Start
End
Figure 13.3 Software Procedure when Using ECH and ECL as 8-Bit Event Counters
When the next clock is input after the ECH count value reaches H'FF, ECH overflows, the OVH
flag is set to 1 in ECCSR, the ECH count value returns to H'00, and counting up is restarted.
Similarly, when the next clock is input after the ECL count value reaches H'FF, ECL overflows,
the OVL flag is set to 1 in ECCSR, the ECL count value returns to H'00, and counting up is
restarted. When an overflow occurs, the IRREC bit is set to 1 in IRR2. If the IENEC bit in IENR2
is 1 at this time, an interrupt request is sent to the CPU.
Rev. 1.00, 07/04, page 264 of 570
13.4.3 IRQAEC Operation
When the ECPWME bit in AEGSR is 0, the ECH and ECL input clocks are enabled when
IRQAEC goes high. When IRQAEC goes low, the input clocks are not input to the counters, and
so ECH and ECL do not count. ECH and ECL count operations can therefore be controlled from
outside by controlling IRQAEC. In this case, ECH and ECL cannot be controlled individually.
IRQAEC can also operate as an interrupt source.
Interrupt enabling is controlled by IENEC2 in IENR1. When an IRQAEC interrupt is generated,
IRR1 interrupt request flag IRREC2 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an
interrupt request is sent to the CPU.
Rising, falling, or both edge sensing can be selected for the IRQAEC input pin with bits AIAGS1
and AIAGS0 in AEGSR.
13.4.4 Event Counter PWM Operation
When the ECPWME bit in AEGSR is 1, the ECH and ECL input clocks are enabled when event
counter PWM output (IECPWM) is high. When IECPWM is low, the input clocks are not input to
the counters, and so ECH and ECL do not count. ECH and ECL count operations can therefore be
controlled cyclically from outside by controlling event counter PWM. In this case, ECH and ECL
cannot be controlled individually.
IECPWM can also operate as an interrupt source.
Interrupt enabling is controlled by IENEC2 in IENR1. When an IECPWM interrupt is generated,
IRR1 interrupt request flag IRREC2 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an
interrupt request is sent to the CPU.
Rising, falling, or both edge detection can be selected for IECPWM interrupt sensing with bits
AIAGS1 and AIAGS0 in AEGSR.
Figure 13.4 and table 13.2 show examples of event counter PWM operation.
t
off
= T × (N
dr
+1)
t
on
t
cm
= T × (N
cm
+1)
t
on
:
t
off
:
t
cm
:
T:
N
dr
:
N
cm
:
Clock input enable time
Clock input disable time
One conversion period
ECPWM input clock cycle
Value of ECPWDR
Fixed low when N
dr
=H'FFFF
Value of ECPWCR
Figure 13.4 Event Counter Operation Waveform
Note: Ndr and Ncm above must be set so that Ndr < Ncm. If the settings do not satisfy this
condition, the output of the event counter PWM is fixed low.
Rev. 1.00, 07/04, page 265 of 570
Table 13.2 Examples of Event Counter PWM Operation
Conditions: fosc = 4 MHz, fφ = 4 MHz, high-speed active mode, ECPWCR value (Ncm) =
H'7A11, ECPWDR value (Ndr) = H'16E3
Clock
Source
Selection
Clock
Source
Cycle (T)*
ECPWCR
Value (Ncm)
ECPWDR
Value (Ndr)
toff = T ×
(Ndr + 1)
tcm = T ×
(Ncm + 1)
ton = tcm –
toff
φ/2 0.5 µs 2.93 ms 15.625 ms 12.695 ms
φ/4 1 µs 5.86 ms 31.25 ms 25.39 ms
φ/8 2 µs 11.72 ms 62.5 ms 50.78 ms
φ/16 4 µs 23.44 ms 125.0 ms 101.56 ms
φ/32 8 µs 46.88 ms 250.0 ms 203.12 ms
φ/64 16 µs
H'7A11
D'31249
H'16E3
D'5859
93.76 ms 500.0 ms 406.24 ms
Note: * toff minimum width
13.4.5 Operation of Clock Input Enabl e / Disable Function
The clock input to the event counter can be controlled by the IRQAEC pin when ECPWME in
AEGSR is 0, and by the event counter PWM output, IECPWM when ECPWME in AEGSR is 1.
As this function forcibly terminates the clock input by each signal, a maximum error of one count
will occur depending on the IRQAEC or IECPWM timing. Figure 13.5 shows an example of the
operation.
Clock stopped
N+2 N+3 N+4 N+5 N+6N N+1
Edge generated by clock return
Input event
IRQAEC or IECPWM
Actually counted clock source
Counter value
Figure 13.5 Example of Clock Control Operation
Rev. 1.00, 07/04, page 266 of 570
13.5 Operating States of Asynchronous Event Counter
The operating states of the asynchronous event counter are shown in table 13.3.
Table 13.3 Operating States of Asynchronous Event Counter
Operating
Mode
Reset
Active
Sleep
Watch Sub-active Sub-sleep
Standby Module
Standby
AEGSR Reset Functions Functions Retained*1 Functions Functions Retained*1 Retained
ECCR Reset Functions Functions Retained*1 Functions Functions Retained*1 Retained
ECCSR Reset Functions Functions Retained*1 Functions Functions Retained*1 Retained
ECH Reset Functions Functions Functions*1*2 Functions*2 Functions*2 Functions*1*2 Halted
ECL Reset Functions Functions Functions*1*2 Functions2 Functions*2 Functions*1*2 Halted
IEQAEC Reset Functions Functions Retained*3 Functions Functions Retained*3 Retained*4
Event counter
PWM
Reset Functions Functions Retained Retained Retained Retained Retained
Notes: 1. When an asynchronous external event is input, the counter increments. However, when
an overflow occurs in standby mode or watch mode, the counter overflow H/L flags are
set by reading ECCSR after clearing standby mode or watch mode.
2. Functions when asynchronous external events are selected; halted and retained
otherwise.
3. Clock control by IRQAEC operates, but interrupts do not.
4. As the clock is stopped in module standby mode, IRQAEC has no effect.
Rev. 1.00, 07/04, page 267 of 570
13.6 Usage Notes
1. When reading the values in ECH and ECL, first clear bits CUEH and CUEL to 0 in ECCSR in
8-bit mode and clear bit CUEL to 0 in 16-bit mode to prevent asynchronous event input to the
counter. The correct value will not be returned if the event counter increments while being
read.
2. Use a clock with a frequency of up to 10 MHz for input to the AEVH and AEVL pins, and
ensure that the high and low widths of the clock are at least 30 ns. The duty cycle is
immaterial.
Table 13.4 shows a maximum clock frequency.
Table 13.4 Maximum Clock Frequency
Mode Maximum Clock Frequency
Input to AEVH/AEVL Pin
Active (high-speed), sleep (high-speed) 10 MHz
Active (medium-speed), sleep (medium-speed) (φ/8)
(φ/16)
(φ/32)
fOSC = 1 MHz to 4 MHz (φ/64)
2 · fOSC
fOSC
1/2 · fOSC
1/4 · fOSC
Watch, subactive, subsleep, standby (φW/2)
(φW/4)
φW = 32.768 kHz or 38.4 kHz (φW/8)
1000 kHz
500 kHz
250 kHz
3. When AEC uses with 16-bit mode, set CUEH in ECCSR to 1 first, set CRCH in ECCSR to 1
second, or set both CUEH and CRCH to 1 at same time before clock input. When AEC is
operating on 16-bit mode, do not change CUEH. Otherwise, ECH will be miscounted up.
4. When ECPWME in AEGSR is 1, the event counter PWM is operating and therefore ECPWCR
and ECPWDR should not be modified.
When changing the data, clear the ECPWME bit in AEGSR to 0 (halt the event counter PWM)
before modifying these registers.
5. The event counter PWM data register and event counter PWM compare register must be set so
that event counter PWM data register < event counter PWM compare register. If the settings
do not satisfy this condition, do not set ECPWME to 1 in AEGSR.
6. As synchronization is established internally when an IRQAEC interrupt is generated, a
maximum error of 1 tcyc will occur between clock halting and interrupt acceptance.
Rev. 1.00, 07/04, page 268 of 570
WDT0110A_000020020200 Rev. 1.00, 07/04, page 269 of 570
Section 14 Watchdog Timer
This LSI incorporates the watchdog timer (WDT). The WDT is an 8-bit timer that can generate an
internal reset signal if a system becomes uncontrolled and prevents the CPU from writing to the
timer counter, thus allowing it to overflow.
When this watchdog timer function is not needed, the WDT can be used as an interval timer. In
interval timer operation, an interval timer interrupt is generated each time the counter overflows.
14.1 Features
The WDT features are described below.
• Selectable from nine counter input clocks
Eight internal clock sources (φ/64, φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096, and φ/8192)
or the on-chip oscillator (ROSC/2048) can be selected as the timer-counter clock.
• Watchdog timer mode
If the counter overflows, this LSI is internally reset.
• Interval timer mode
If the counter overflows, an interval timer interrupt is generated.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (For details, refer to section 6.4, Module Standby Function.)
Figure 14.1 shows a block diagram of the WDT.
φ
CLK
Internal reset signal or
interrupt request signal
PSS TCWD
TMWD
Internal data bus
TCSRWD2
TCSRWD1
[Legend]
TCSRWD1:
TCSRWD2:
TCWD:
TMWD:
PSS:
Timer control/status register WD1
Timer control/status register WD2
Timer counter WD
Timer mode register WD
Prescaler S
on-chip
oscillator
Interrupt/reset control
Figure 14.1 Block Diagram of Watchdog Timer
Rev. 1.00, 07/04, page 270 of 570
14.2 Register Descriptions
The watchdog timer has the following registers.
• Timer control/status register WD1 (TCSRWD1)
• Timer control/status register WD2 (TCSRWD2)
• Timer counter WD (TCWD)
• Timer mode register WD (TMWD)
14.2.1 Timer Control/Status Register WD1 (TCSRWD1)
TCSRWD1 performs the TCSRWD1 and TCWD write control. TCSRWD1 also controls the
watchdog timer operation and indicates the operating state. TCSRWD1 must be rewritten by using
the MOV instruction. The bit manipulation instruction cannot be used to change the setting value.
Bit Bit Name
Initial
Value R/W Description
7 B6WI 1 R/W Bit 6 Write Inhibit
The TCWE bit can be written only when the write value
of the B6WI bit is 0.
This bit is always read as 1.
6 TCWE 0 R/W Timer Counter WD Write Enable
TCWD can be written when the TCWE bit is set to 1.
When writing data to this bit, the write value for bit 7
must be 0.
5 B4WI 1 R/W Bit 4 Write Inhibit
The TCSRWE bit can be written only when the write
value of the B4WI bit is 0. This bit is always read as 1.
4 TCSRWE 0 R/W Timer Control/Status Register WD Write Enable
The WDON and WRST bits can be written when the
TCSRWE bit is set to 1.
When writing data to this bit, the write value for bit 5
must be 0.
3 B2WI 1 R/W Bit 2 Write Inhibit
The WDON bit can be written only when the write value
of the B2WI bit is 0. This bit is always read as 1.
Rev. 1.00, 07/04, page 271 of 570
Bit Bit Name
Initial
Value R/W Description
2 WDON 0 R/W Watchdog Timer On
TCWD starts counting up when the WDON bit is set to
1 and halts when the WDON bit is cleared to 0.
[Setting condition]
When 1 is written to the WDON bit and 0 to the B2WI
bit while the TCSRWE bit is 1
[Clearing conditions]
• Reset by RES pin
• When 0 is written to the WDON bit and 0 to the
B2WI bit while the TCSRWE bit is 1
1 B0WI 1 R/W Bit 0 Write Inhibit
The WRST bit can be written only when the write value
of the B0WI bit is 0. This bit is always read as 1.
0 WRST 0 R/W Watchdog Timer Reset
[Setting condition]
When TCWD overflows and an internal reset signal is
generated
[Clearing conditions]
• Reset by RES pin
• When 0 is written to the WRST bit and 0 to the
B0WI bit while the TCSRWE bit is 1
Rev. 1.00, 07/04, page 272 of 570
14.2.2 Timer Control/Status Register WD2 (TCSRWD2)
TCSRWD2 performs the TCSRWD2 write control, mode switching, and interrupt control.
TCSRWD2 must be rewritten by using the MOV instruction. The bit manipulation instruction
cannot be used to change the setting value.
Bit Bit Name
Initial
Value R/W Description
7 OVF 0 R/(W)*1Overflow Flag
Indicates that TCWD has overflowed (changes from
H'FF to H'00).
[Setting condition]
When TCWD overflows (changes from H'FF to H'00)
When internal reset request generation is selected in
watchdog timer mode, this bit is cleared automatically
by the internal reset after it has been set.
[Clearing condition]
• When TCSRWD2 is read when OVF = 1, then 0 is
written to OVF*4
6 B5WI 1 R/(W)*2Bit 5 Write Inhibit
The WT/IT bit can be written only when the write value
of the B5WI bit is 0. This bit is always read as 1.
5 WT/IT 0 R/(W)*3Timer Mode Select
Selects whether the WDT is used as a watchdog timer
or interval timer.
0: Watchdog timer mode
1: Interval timer mode
4 B3WI 1 R/(W)*2Bit 3 Write Inhibit
The IEOVF bit can be written only when the write value
of the B3WI bit is 0. This bit is always read as 1.
3 IEOVF 0 R/(W)*3Overflow Interrupt Enable
Enables or disables an overflow interrupt request in
interval timer mode.
0: Disables an overflow interrupt
1: Enables an overflow interrupt
2 to 0 All 1 Reserved
These bits are always read as 1.
Notes: 1. Only 0 can be written to clear the flag.
2. Write operation is necessary because this bit controls data writing to other bit. This bit is
always read as 1.
3. Writing is possible only when the write conditions are satisfied.
4. In subactive mode, clear this flag after setting the CKS3 to CKS0 bits in TMWD to
B'0XXX (on-chip oscillator).
Rev. 1.00, 07/04, page 273 of 570
14.2.3 Timer Counter WD (TCWD)
TCWD is an 8-bit readable/writable up-counter. When TCWD overflows from H'FF to H'00, the
internal reset signal is generated in watchdog timer mode, the WRST bit in TCSRWD1 is set to 1,
and the OVF bit in TCSRWD2 is set to 1. TCWD is initialized to H'00.
14.2.4 Timer Mode Register WD (TMWD)
TMWD selects the input clock.
Bit Bit Name
Initial
Value R/W Description
7 to 4 All 1 Reserved
These bits are always read as 1.
3
2
1
0
CKS3
CKS2
CKS1
CKS0
1
1
1
1
R/W
R/W
R/W
R/W
Clock Select 3 to 0
Select the clock to be input to TCWD.
1000: Internal clock: counts on φ/64
1001: Internal clock: counts on φ/128
1010: Internal clock: counts on φ/256
1011: Internal clock: counts on φ/512
1100: Internal clock: counts on φ/1024
1101: Internal clock: counts on φ/2048
1110: Internal clock: counts on φ/4096
1111: Internal clock: counts on φ/8192
0XXX: on-chip oscillator: counts on ROSC/2048
For the on-chip oscillator overflow periods, see section
25, Electrical Characteristics.
In active (medium-speed) mode or sleep (medium-
speed) mode, the setting of B'0XXX and interval timer
mode is disabled.
[Legend] X: Don't care.
Rev. 1.00, 07/04, page 274 of 570
14.3 Operation
14.3.1 Watchdog Timer Mode
The watchdog timer is provided with an 8-bit up-counter. To use it as the watchdog timer, clear
the WT/IT bit in TCSRWD2 to 0. (To write the WT/IT bit, two write accesses are required.) If 1 is
written to the WDON bit and 0 to the B2WI bit simultaneously when the TCSRWE bit in
TCSRWD1 is set to 1, TCWD begins counting up. (To operate the watchdog timer, two write
accesses to TCSRWD1 are required.) When a clock pulse is input after the TCWD count value has
reached H'FF, the watchdog timer overflows and an internal reset signal is generated. The internal
reset signal is output for a period of 512 φosc clock cycles. TCWD is a writable counter, and when a
value is set in TCWD, the count-up starts from that value. An overflow period in the range of 1 to
256 input clock cycles can therefore be set, according to the TCWD set value.
Figure 14.2 shows an example of watchdog timer operation.
Example: With 30-ms overflow period when φ = 4 MHz
4 × 10
6
× 30 × 10
–3
= 14.6
8192
TCWD overflow
H'FF
H'00
Internal reset
signal
H'F1
TCWD
count value
H'F1 written
to TCWD
H'F1 written to TCWD Reset generated
Start
512 φ
osc
clock cycles
Therefore, 256 – 15 = 241 (H'F1) is set in TCW.
Figure 14.2 Example of Watchdog Timer Operation
Rev. 1.00, 07/04, page 275 of 570
14.3.2 Interval Timer Mode
Figure 14.3 shows the operation in interval timer mode. To use the WDT as an interval timer, set
the WT/IT bit in TCSRWD2 to 1.
When the WDT is used as an interval timer, an interval timer interrupt request is generated each
time the TCNT overflows. Therefore, an interval timer interrupt can be generated at intervals.
TCNT
count value
H'00
Time
H'FF
WT/IT = 0
TME = 1
Interval timer
interrupt
request generated
Interval timer
interrupt
request generated
Interval timer
interrupt
request generated
Interval timer
interrupt
request generated
Interval timer
interrupt
request generated
Figure 14.3 Interval Timer Mode Operation
14.3.3 Timing of Overflow Flag (OVF) Setting
Figure 14.4 shows the timing of the OVF flag setting. The OVF flag in TCSRWD2 is set to 1 if
TCNT overflows. At the same time, a reset signal is output in watchdog timer mode and an
interval timer interrupt is generated in interval timer mode.
φ
TCNT H'FF H'00
Overflow signal
OVF
Figure 14.4 Timing of OVF Flag Setting
Rev. 1.00, 07/04, page 276 of 570
14.4 Interrupt
During interval timer mode operation, an overflow generates an interval timer interrupt. The
interval timer interrupt is requested whenever the OVF flag is set to 1 while the IEOVF bit in
TCSRWD2 is set to 1. The OVF flag must be cleared to 0 in the interrupt handling routine.
14.5 Usage Notes
14.5.1 Switching between Watchdog Timer Mode and Interval Timer Mode
If the mode is switched between watchdog timer and interval timer, while the WDT is operating,
errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the
WDON bit to 0) before switching the mode.
14.5.2 Module Standby Mode C on t rol
The WDCKSTP bit in CKSTPR2 is valid when the WDON bit in the timer control/status register
1 (TCSRWD1) is cleared to 0. The WDCKSTP bit can be cleared to 0 while the WDON bit is set
to 1 (while the watchdog timer is operating). However, the watchdog timer does not enter module
standby mode but continues operating. When the WDON bit is cleared to 0 by software after the
watchdog timer stops operating, the WDCKSTP bit is valid at the same time and the watchdog
timer enters module standby mode.
SCI0012A_010020040500 Rev. 1.00, 07/04, page 277 of 570
Section 15 Serial Communication Interface 3 (SCI3, IrDA)
The serial communication interface 3 (SCI3) can handle both asynchronous and clocked
synchronous serial communication. In the asynchronous method, serial data communication can
be carried out using standard asynchronous communication chips such as a Universal
Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface
Adapter (ACIA). A function is also provided for serial communication between processors
(multiprocessor communication function) with two channels (SCI3_1 and SCI3_2). Table 15.1
shows the SCI3 channel configuration.
The SCI3_1 can transmit and receive IrDA communication waveforms based on the Infrared Data
Association (IrDA) standard version 1.0.
15.1 Features
• Choice of asynchronous or clocked synchronous serial communication mode
• Full-duplex communication capability
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously.
Double-buffering is used in both the transmitter and the receiver, enabling continuous
transmission and continuous reception of serial data.
• On-chip baud rate generator allows any bit rate to be selected
• On-chip baud rate generator, internal clock, or external clock can be selected as a transfer
clock source.
• Six interrupt sources
Transmit-end, transmit-data-empty, receive-data-full, overrun error, framing error, and parity
error.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (For details, refer to section 6.4, Module Standby Function.)
Asynchronous mode
• Data length: 7, 8, or 5 bits
• Stop bit length: 1 or 2 bits
• Parity: Even, odd, or none
• Receive error detection: Parity, overrun, and framing errors
• Break detection: Break can be detected by reading the RXD32 pin level directly in the case of
a framing error
Rev. 1.00, 07/04, page 278 of 570
Clocked synchronous mode
• Data length: 8 bits
• Receive error detection: Overrun errors detected
Table 15.1 SCI3 Channel Configuration
Channel Abbreviation Pin*1 Register*2 Register Address
SMR3_1 H'FF98
BRR3_1 H'FF99
SCR3_1 H'FF9A
TDR3_1 H'FF9B
SSR3_1 H'FF9C
RDR3_1 H'FF9D
RSR3_1
Channel 1 SCI3_1 SCK31
RXD31
TXD31
TSR3_1
IrCR H'FFA7
SMR3_2 H'FFA8
BRR3_2 H'FFA9
SCR3_2 H'FFAA
TDR3_2 H'FFAB
SSR3_2 H'FFAC
RDR3_2 H'FFAD
RSR3_2
Channel 2 SCI3_2 SCK32
RXD32
TXD32
TSR3_2
Notes: 1. Pin names SCK3, RXD3, and TXD3 are used in the text for all channels, omitting the
channel designation.
2. In the text, channel description is omitted for registers and bits.
Rev. 1.00, 07/04, page 279 of 570
Figure 15.1 (1) shows a block diagram of the SCI3_1 and figure 15.1 (2) shows that of the
SCI3_2.
Clock
SCK
31
BRR3_1
TSR3_1
SPCR
IrCR
Transmit/receive
control circuit
Internal data bus
[Legend]
RSR3_1:
RDR3_1:
TSR3_1:
TDR3_1:
SMR3_1:
SCR3_1:
SSR3_1:
BRR3_1:
BRC3_1:
SPCR:
IrCR:
Receive shift register 3_1
Receive data register 3_1
Transmit shift register 3_1
Transmit data register 3_1
Serial mode register 3_1
Serial control register 3_1
Serial status register 3_1
Bit rate register 3_1
Bit rate counter 3_1
Serial port control register
IrDA control register
Interrupt request
(TEI31, TXI31, RXI31, ERI31)
Internal clock (φ/64, φ/16, φw/2, φ)
External clock
BRC3_1
Baud rate generator
TXD31
RXD31
SMR3_1
SCR3_1
SSR3_1
TDR3_1
RDR3_1
RSR3_1
Figure 15.1 (1) Block Diagram of SCI 3_ 1
Rev. 1.00, 07/04, page 280 of 570
Clock
SCK32
BRR3_2
TSR3_2
SPCR
Transmit/receive
control circuit
Internal data bus
[Legend]
RSR3_2:
RDR3_2:
TSR3_2:
TDR3_2:
SMR3_2:
SCR3_2:
SSR3_2:
BRR3_2:
BRC3_2:
SPCR:
Receive shift register 3_2
Receive data register 3_2
Transmit shift register 3_2
Transmit data register 3_2
Serial mode register 3_2
Serial control register 3_2
Serial status register 3_2
Bit rate register 3_2
Bit rate counter 3_2
Serial port control register
Interrupt request
(TEI32, TXI32, RXI32, ERI32)
Internal clock (φ/64, φ/16, φw/2, φ)
External clock
BRC3_2
Baud rate generator
TXD32
RXD32
SMR3_2
SCR3_2
SSR3_2
TDR3_2
RDR3_2RSR3_2
Figure 15.1 (2) Block Diagram of SCI 3_ 2
Rev. 1.00, 07/04, page 281 of 570
15.2 Input/Output Pins
Table 15.2 shows the SCI3 pin configuration.
Table 15.2 Pin Configuration
Pin Name Abbreviation I/O Function
SCI3 clock SCK31,
SCK32
I/O SCI3 clock input/output
SCI3 receive data
input
RXD31,
RXD32
Input SCI3 receive data input
SCI3 transmit data
output
TXD31,
TXD32
Output SCI3 transmit data output
15.3 Register Descriptions
The SCI3 has the following registers for each channel.
• Receive shift register 3 (RSR3)*
• Receive data register 3 (RDR3)*
• Transmit shift register 3 (TSR3)*
• Transmit data register 3 (TDR3)*
• Serial mode register 3 (SMR3)*
• Serial control register 3 (SCR3)*
• Serial status register 3 (SSR3)*
• Bit rate register 3 (BRR3)*
• Serial port control register (SPCR)
• IrDA control register (IrCR)
Note: * These register names are abbreviated to RSR, RDR, TSR, TDR, SMR, SCR, SSR, and
BRR in the text.
Rev. 1.00, 07/04, page 282 of 570
15.3.1 Receive Shift Register (RSR)
RSR is a shift register that receives serial data input from the RXD31 or RXD32 pin and converts
it into parallel data. When one byte of data has been received, it is transferred to RDR
automatically. RSR cannot be directly accessed by the CPU.
15.3.2 Receive Data Register (RDR)
RDR is an 8-bit register that stores receive data. When the SCI3 has received one byte of serial
data, it transfers the received serial data from RSR to RDR, where it is stored. After this, RSR is
receive-enabled. As RSR and RDR function as a double buffer in this way, continuous receive
operations are possible. After confirming that the RDRF bit in SSR is set to 1, read RDR only
once. RDR cannot be written to by the CPU. RDR is initialized to H'00.
RDR is initialized to H'00 by a reset or in standby mode, watch mode, or module standby mode.
15.3.3 Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI3 first
transfers transmit data from TDR to TSR automatically, then sends the data that starts from the
LSB to the TXD31 or TXD32 pin. Data transfer from TDR to TSR is not performed if no data has
been written to TDR (if the TDRE bit in SSR is set to 1). TSR cannot be directly accessed by the
CPU.
15.3.4 Transmit Data Register (TDR)
TDR is an 8-bit register that stores data for transmission. When the SCI3 detects that TSR is
empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-
buffered structure of TDR and TSR enables continuous serial transmission. If the next transmit
data has already been written to TDR during transmission of one-frame data, the SCI3 transfers
the written data to TSR to continue transmission. To achieve reliable serial transmission, write
transmit data to TDR only once after confirming that the TDRE bit in SSR is set to 1. TDR is
initialized to H'FF.
TDR is initialized to H'FF by a reset or in standby mode, watch mode, or module standby mode.
Rev. 1.00, 07/04, page 283 of 570
15.3.5 Serial Mode Regis ter (S M R)
SMR sets the SCI3's serial communication format and selects the clock source for the on-chip
baud rate generator.
SMR is initialized to H'00 by a reset or in standby mode, watch mode, or module standby mode.
Bit Bit Name
Initial
Value R/W Description
7 COM 0 R/W Communication Mode
0: Asynchronous mode
1: Clocked synchronous mode
6 CHR 0 R/W Character Length (enabled only in asynchronous
mode)
0: Selects 8 or 5 bits as the data length.
1: Selects 7 or 5 bits as the data length.
When 7-bit data is selected. the MSB (bit 7) in TDR is
not transmitted. To select 5 bits as the data length, set
1 to both the PE and MP bits. The three most
significant bits (bits 7, 6, and 5) in TDR are not
transmitted. In clocked synchronous mode, the data
length is fixed to 8 bits regardless of the CHR bit
setting.
5 PE 0 R/W Parity Enable (enabled only in asynchronous mode)
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity bit is
checked in reception. In clocked synchronous mode,
parity bit addition and checking is not performed
regardless of the PE bit setting.
Rev. 1.00, 07/04, page 284 of 570
Bit Bit Name
Initial
Value R/W Description
4 PM 0 R/W Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
When even parity is selected, a parity bit is added in
transmission so that the total numver of 1 bits in the
transmit data plus the parity bit is an even number, in
reception, a check is carried out to confirm that the
number of 1 bits in the receive data plus the parity bit is
an enen number.
When odd parity is selected, a parity bit is added in
transmission so that the total numver of 1 bits in the
transmit data plus the parity bit is an odd numver, in
reception, a check is carried out to confirm that the
numver of 1bits in the receive data plus the parity bit is
an odd numver.
If parity bit addition and checking is disabled in clocked
synchronous mode and asynchronous mode, the PM
bit setting is invalid.
3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous mode)
Selects the stop bit length in transmission.
0: 1 stop bit
1: 2 stop bits
For reception, only the first stop bit is checked,
regardless of the value in the bit. If the second stop bit
is 0, it is treated as the start bit of the next transmit
character.
2 MP 0 R/W Multiprocessor Mode
When this bit is set to 1, the multiprocessor
communication function is enabled. The PE bit and PM
bit settings are invalid. In clocked synchronous mode,
this bit should be cleared to 0.
Rev. 1.00, 07/04, page 285 of 570
Bit Bit Name
Initial
Value R/W Description
1
0
CKS1
CKS0
0
0
R/W
R/W
Clock Select 0 and 1
These bits select the clock source for the on-chip baud
rate generator.
00: φ clock (n = 0)
01: φw/2 or φ w clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
When the setting value is 0 in active (medium-
speed/high-speed) mode and sleep (medium-
speed/high-speed) mode φw/2 clock is set. In subacive
mode and subsleep mode, φw clock is set. The SCI3 is
enabled only, when φw/2 is selected for the CPU
operating clock.
For the relationship between the bit rate register setting
and the baud rate, see section 15.3.8, Bit Rate
Register (BRR). n is the decimal representation of the
value of n in BRR (see section 15.3.8, Bit Rate
Register (BRR)).
15.3.6 Serial Control Register (SCR)
SCR enables or disables SCI3 transfer operations and interrupt requests, and selects the transfer
clock source. For details on interrupt requests, refer to section 15.8, Interrupt Requests.
SCR is initialized to H'00 by a reset or in standby mode, watch mode, or module standby mode.
Bit Bit Name
Initial
Value R/W Description
7 TIE 0 R/W Transmit Interrupt Enable
When this bit is set to 1, the TXI (TXI32) interrupt
request is enabled. TXI (TXI32) can be released by
clearing the TDRE it or TI bit to 0.
6 RIE 0 R/W Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt requests
are enabled.
RXI (RXI32) and ERI (ERI32) can be released by
clearing the RDRF bit or the FER, PER, or OER error
flag to 0, or by clearing the RIE bit to 0.
Rev. 1.00, 07/04, page 286 of 570
Bit Bit Name
Initial
Value R/W Description
5 TE 0 R/W Transmit Enable
When this bit is set to 1, transmission is enabled. When
this bit is 0, the TDRE bit in SSR is fixed at 1. When
transmit data is written to TDR while this bit is 1, Bit
TDRE in SSR is cleared to 0 and serial data
tansmission is started. Be sure to carry out SMR
settings, and setting of bit SPC31 or SPC32 in SPCR,
to decide the transmission format before setting bit TE
to 1.
4 RE 0 R/W Receive Enable
When this bit is set to 1, reception is enabled. In this
state, serial data reception is started when a start bit is
detected in asynchronous mode or serial clock input is
detected in clocked synchronous mode. Be sure to
carry out the SMR settings to decide the reception
format before setting bit RE to 1.
Note that the RDRF, FER, PER, and OER flags in SSR
are not affected when bit RE is cleared to 0, and retain
their previous state
3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only when the
MP bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and OER status flags in SSR is
prohibited. On receiving data in which the
multiprocessor bit is 1, this bit is automatically cleared
and normal reception is resumed. For details, refer to
section 15.6, Multiprocessor Communication Function.
2 TEIE 0 R/W Transmit End Interrupt Enable
When this bit is set to 1, the TEI interrupt request is
enabled. TEI can be released by clearing bit TDRE to 0
and clearing bit TEND to 0 in SSR, or by clearing bit
TEIE to 0.
Rev. 1.00, 07/04, page 287 of 570
Bit Bit Name
Initial
Value R/W Description
1
0
CKE1
CKE0
0
0
R/W
R/W
Clock Enable 0 and 1
Select the clock source.
Asynchronous mode:
00: Internal baud rate generator (SCK31 or SCK32 pin
functions as an I/O port)
01: Internal baud rate generator (Outputs a clock of the
same frequency as the bit rate from the SCK31 or
SCK32 pin)
10: External clock (Inputs a clock with a frequency 16
times the bit rate from the SCK31 or SCK32 pin)
11: Reserved
Clocked synchronous mode:
00: Internal clock (SCK31 or SCK32 pin functions as
clock output)
01: Reserved
10: External clock (SCK31 or SCK32 pin functions as
clock input)
11: Reserved
Rev. 1.00, 07/04, page 288 of 570
15.3.7 Serial Status Regis ter (SS R )
SSR consists of status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot be written to
flags TDRE, RDRF, OER, PER, and FER; they can only be cleared.
SSR is initialized to H'84 by a reset or in standby mode, watch mode, or module standby mode.
Bit Bit Name
Initial
Value R/W Description
7 TDRE 1 R/(W)*Transmit Data Register Empty
Indicates that transmit data is stored in TDR.
[Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the transmit data is written to TDR
6 RDRF 0 R/(W)*Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
• When serial reception ends normally and receive
data is transferred from RSR to RDR
[Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1
When data is read from RDR
If an error is detected in reception, or if the RE bit in
SCR has been cleared to 0, RDR and bit RDRF are not
affected and retain their previous state.
Note that if data reception is completed while bit RDRF
is still set to 1, an overrun error (OER) will occur and
the receive data will be lost.
Rev. 1.00, 07/04, page 289 of 570
Bit Bit Name
Initial
Value R/W Description
5 OER 0 R/(W)*Overrun Error
[Setting condition]
• When an overrun error occurs in reception
[Clearing condition]
• When 0 is written to OER after reading OER = 1
When bit RE in SCR is cleared to 0, bit OER is not
affected and retains its previous state.
When an overrun error occurs, RDR retains the receive
data it held before the overrun error occurred, and data
received after the error is lost. Reception cannot be
continued with bit OER set to 1, and in clocked
synchronous mode, transmission cannot be continued
either.
4 FER 0 R/(W)*Framing Error
[Setting condition]
• When a framing error occurs in reception
[Clearing condition]
• When 0 is written to FER after reading FER = 1
When bit RE in SCR is cleared to 0, bit FER is not
affected and retains its previous state.
Note that, in 2-stop-bit mode, only the first stop bit is
checked for a value of 1, and the second stop bit is not
checked. When a framing error occurs, the receive
data is transferred to RDR but bit RDRF is not set.
Reception cannot be continued with bit FER set to 1. In
clocked synchronous mode, neither transmission nor
reception is possible when bit FER is set to 1.
Rev. 1.00, 07/04, page 290 of 570
Bit Bit Name
Initial
Value R/W Description
3 PER 0 R/(W)*Parity Error
[Setting condition]
• When a parity error is generated during reception
[Clearing condition]
• When 0 is written to PER after reading PER = 1
When bit RE in SCR is cleared to 0, bit PER is not
affected and retains its previous state.
• Receive data in which a parity error has occurred is
still transferred to RDR, but bit RDRF is not set.
Reception cannot be continued with bit PER set to
1. In clocked synchronous mode, neither
transmission nor reception is possible when bit
PER is set to 1.
2 TEND 1 R Transmit End
[Setting conditions]
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of a
1-byte serial transmit character
[Clearing conditions]
• When 0 is written to TDRE after readingTDRE = 1
• When the transmit data is written to TDR
1 MPBR 0 R Multiprocessor Bit Receive
MPBR stores the multiprocessor bit in the receive
character data. When the RE bit in SCR is cleared to 0,
its previous state is retained.
0 MPBT 0 R/W Multiprocessor Bit Transfer
MPBT stores the multiprocessor bit to be added to the
transmit character data.
Note: * Only 0 can be written to clear the flag.
Rev. 1.00, 07/04, page 291 of 570
15.3.8 Bit Rate Register (BRR)
BRR is an 8-bit readable/writable register that adjusts the bit rate. BRR is initialized to H'FF.
Table 15.3 shows the relationship between the N setting in BRR and the n setting in bits CKS1
and CKS0 in SMR in asynchronous mode. Table 15.5 shows the maximum bit rate for each
frequency in asynchronous mode. The values shown in both tables 15.3 and 15.5 are values in
active (high-speed) mode. Table 15.6 shows the relationship between the N setting in BRR and the
n setting in bits CKS1 and CKS0 in SMR in clocked synchronous mode. The values shown in
table 15.6 are values in active (high-speed) mode. The N setting in BRR and error for other
operating frequencies and bit rates can be obtained by the following formulas:
[Asynchronous Mode]
N = OSC
32 × 22n × B – 1
Error (%) = × 100
B (bit rate obtained from n, N, OSC) – R (bit rate in left-hand column in table 15.3)
R (bit rate in left-hand column in table 15.3)
[Legend] B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
OSCφ: Value of φOSC (Hz)
n: Baud rate generator input clock number (n = 0, 2, or 3)
(The relation between n and the clock is shown in table 15.3)
Rev. 1.00, 07/04, page 292 of 570
Table 15.3 Examples of BRR Settings for Various Bit Rates (Asynchron ous Mode) (1)
32.8kHz 38.4kHz 2MHz 2.097152MHz
Bit
Rate
(bit/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
110 — — — 0 10 –0.83 2 35 –1.36 2 36 0.64
150 0 6 –2.38 0 7 0.00 2 25 0.16 2 26 1.14
200 0 4 2.50 0 5 0.00 2 19 –2.34 3 4 2.40
250 0 3 2.50 — — — 0 249 0.00 3 3 2.40
300 — — — 0 3 0.00 0 207 0.16 0 217 0.21
600 — — — 0 1 0.00 0 103 0.16 2 6 –2.48
1200 — — — 0 0 0.00 0 51 0.16 0 54 –0.70
2400 — — — — — — 0 25 0.16 0 26 1.14
4800 — — — — — — 0 12 0.16 0 13 –2.48
9600 — — — — — — — — — 0 6 –2.48
19200 — — — — — — — — — — — —
31250 — — — — — — 0 1 0.00 — — —
38400 — — — — — — — — — — — —
Table 15.3 Examples of BRR Settings for Various Bit Rates (Asynchron ous Mode) (2)
2.4576MHz 3MHz 3.6864MHz 4MHz
Bit
Rate
(bit/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
110 3 10 –0.83 2 52 0.50 2 64 0.70 2 70 0.03
150 3 7 0.00 2 38 0.16 3 11 0.00 2 51 0.16
200 3 5 0.00 2 28 1.02 3 8 0.00 2 38 0.16
250 2 18 1.05 2 22 1.90 2 28 –0.69 2 30 0.81
300 3 3 0.00 3 4 2.34 3 5 0.00 2 25 0.16
600 3 1 0.00 0 155 0.16 3 2 0.00 0 207 0.16
1200 3 0 0.00 0 77 0.16 2 5 0.00 0 103 0.16
2400 2 1 0.00 0 38 0.16 2 2 0.00 0 51 0.16
4800 2 0 0.00 0 19 –2.34 0 23 0.00 0 25 0.16
9600 0 7 0.00 0 9 –2.34 0 11 0.00 0 12 0.16
19200 0 3 0.00 0 4 –2.34 0 5 0.00 — — —
31250 — — — 0 2 0.00 — — — 0 3 0.00
38400 0 1 0.00 — — — 0 2 0.00 — — —
Rev. 1.00, 07/04, page 293 of 570
Table 15.3 Examples of BRR Settings for Various Bit Rates (Asynchron ous Mode) (3)
4.9152MHz 5MHz 6MHz 6.144MHz
Bit
Rate
(bit/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
110 2 86 0.31 2 28 –0.25 2 106 –0.44 2 108 0.08
150 3 15 0.00 2 64 0.16 2 77 0.16 3 19 0.00
200 3 11 0.00 2 48 –0.35 2 58 –0.69 3 11 0.00
250 2 37 1.05 2 38 0.16 2 46 –0.27 3 11 0.00
300 3 7 0.00 2 32 –1.36 2 38 0.16 3 9 0.00
600 3 3 0.00 0 256 1.33 3 4 –2.34 3 4 0.00
1200 3 1 0.00 0 129 0.16 0 155 0.16 2 9 0.00
2400 3 0 0.00 0 64 0.16 0 77 0.16 2 4 0.00
4800 2 1 0.00 0 32 –1.36 0 38 0.16 0 39 0.00
9600 2 0 0.00 2 0 1.73 0 19 –2.34 0 19 0.00
19200 0 7 0.00 0 7 1.73 0 9 –2.34 0 9 0.00
31250 0 4 –1.70 0 4 0.00 0 5 0.00 0 5 2.4
38400 0 3 0.00 0 3 1.73 0 4 –2.34 0 4 0.00
Table 15.3 Examples of BRR Settings for Various Bit Rates (Asynchron ous Mode) (4)
7.3728MHz 8MHz 9.8304MHz 10MHz
Bit
Rate
(bit/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
110 2 130 –0.07 2 141 0.03 2 174 –0.26 2 177 –0.25
150 3 23 0.00 2 103 0.16 3 31 0.00 2 129 0.16
200 3 17 0.00 2 77 0.16 3 23 0.00 2 97 –0.35
250 2 57 –0.69 2 62 –0.79 2 76 –0.26 2 77 0.16
300 3 11 0.00 2 51 0.16 3 15 0.00 2 64 0.16
600 3 5 0.00 2 25 0.16 3 7 0.00 2 32 –1.36
1200 3 2 0.00 2 12 0.16 3 3 0.00 2 15 1.73
2400 2 5 0.00 0 103 0.16 3 1 0.00 0 129 0.16
4800 2 2 0.00 0 51 0.16 3 0 0.00 0 64 0.16
9600 0 23 0.00 0 25 0.16 2 1 0.00 0 32 –1.36
19200 0 11 0.00 0 12 0.16 2 0 0.00 0 15 1.73
31250 — — — 0 7 0.00 0 9 –1.70 0 9 0.00
38400 0 5 0.00 — — — 0 7 0.00 0 7 1.73
Rev. 1.00, 07/04, page 294 of 570
Table 15.4 Relation between n and Clock
SMR Setting
n
Clock CKS1 CKS0
0 φ 0 0
0 φW/2*1/φW*2 0 1
2 φ/16 1 0
3 φ/64 1 1
Notes: 1. φW/2 clock in active (medium-speed/high-speed) mode and sleep (medium-speed/high-
speed) mode
2. φW clock in subactive mode and subsleep mode
In subactive or subsleep mode, the SCI3 can be operated only when CPU clock is φW/2.
Table 15.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
Setting
OSC (MHz) Maximum Bit Rate (bit/s) n N
0 0
0.0384 1200 0 0
2 62500 0 0
2.097152 65535 0 0
2.4576 76800 0 0
3 93750 0 0
3.6864 115200 0 0
4 125000 0 0
4.9152 153595 0 0
5 156250 0 0
6 187500 0 0
6.144 192000 0 0
7.3728 230400 0 0
8 250000 0 0
9.8304 307200 0 0
10 312500 0 0
Note: * When CKS1 = 0 and CKS0 = 1 in SMR
Rev. 1.00, 07/04, page 295 of 570
Table 15.6 BRR Settings for Various Bit Rates (Clocked Synchron o us Mo de) ( 1)
OSC 32.8 kHz 38.4 kHz 2 MHz
Bit Rate
(bit/s) n N Error (%) n N Error (%) n N Error (%)
200 0 40 0.00 0 47 0.00 2 155 0.16
250 0 32 −0.61 0 37 1.05 2 124 0.00
300 0 26 1.23 0 31 0.00 2 103 0.16
500 0 15 2.50 0 18 1.05 2 62 −0.79
1k 0 7 2.50 2 30 0.81
2.5k 0 199 0.00
5k 0 99 0.00
10k 0 49 0.00
25k 0 19 0.00
50k 0 9 0.00
100k 0 4 0.00
250k 0 1 0.00
500k 0* 0* 0.00*
1M
Note: * Continuous transmission/reception is not possible.
Rev. 1.00, 07/04, page 296 of 570
Table 15.6 BRR Settings for Various Bit Rates (Clocked Synchron o us Mo de) ( 2)
OSC 4 MHz 8 MHz 10 MHz
Bit Rate
(bit/s) n N Error (%) n N Error (%) n N Error (%)
200 3 77 0.16 3 155 0.16 3 194 0.16
250 2 249 0.00 3 124 0.00 3 155 0.16
300 2 207 0.16 3 103 0.16 3 129 0.16
500 2 124 0.00 2 249 0.00 3 77 0.16
1k 2 62 −0.79 2 124 0.00 2 155 0.16
2.5k 2 24 0.00 2 49 0.00 2 62 −0.79
5k 0 199 0.00 2 24 0.00 2 30 0.81
10k 0 99 0.00 0 199 0.00 2 249 0.00
25k 0 39 0.00 0 79 0.00 0 99 0.00
50k 0 19 0.00 0 39 0.00 0 49 0.00
100k 0 9 0.00 0 19 0.00 0 24 0.00
250k 0 3 0.00 0 7 0.00 0 9 0.00
500k 0 1 0.00 0 3 0.00 0 4 0.00
1M 0* 0* 0.00* 0 1 0.00
Note: * Continuous transmission/reception is not possible.
The value set in BRR is given by the following formula:
N = OSC
4 × 2
2n
× B – 1
B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
OSC: Value of φOSC (Hz)
n: Baud rate generator input clock number (n = 0, 2, or 3)
(The relation between n and the clock is shown in table 15.7.)
Rev. 1.00, 07/04, page 297 of 570
Table 15.7 Relation between n and Clock
SMR Setting
n
Clock CKS1 CKS0
0 φ 0 0
0 φW/2*1/φW*2 0 1
2 φ/16 1 0
3 φ/64 1 1
Notes: 1. φW/2 clock in active (medium-speed/high-speed) mode and sleep (medium-speed/high-
speed) mode
2. φW clock in subactive or subsleep mode
In subactive or subsleep mode, the SCI3_1 and SCI3_2 can be operated only when
CPU clock is φW/2.
15.3.9 Serial Port Control Register (SPCR)
SPCR selects the functions of the TXD32 and TXD31 pins.
Bit Bit Name
Initial
Value R/W Description
7
6
1
1
Reserved
These bits are always read as 1 and cannot be
modified.
5 SPC32 0 R/W P32/TXD33 Pin Function Switch
Selects whether pin P32/TXD32 is used as P32 or as
TXD32.
0: P32 I/O pin
1: TXD32 output pin
Set the TE32 bit in SCR32 after setting this bit to 1.
4 SPC31 0 R/W P42/TXD31 Pin Function Switch
Selects whether pin P42/TXD31 is used as P42 or as
TXD31.
0: P42 I/O pin
1: TXD31 output pin
Set the TE bit in SCR after setting this bit to 1.
Rev. 1.00, 07/04, page 298 of 570
Bit Bit Name
Initial
Value R/W Description
3 SCINV3 0 R/W TXD32 Pin Output Data Inversion Switch
Selects whether output data of the TXD32 pin is
inverted or not.
0: Output data of TXD32 pin is not inverted.
1: Output data of TXD32 pin is inverted.
2 SCINV2 0 R/W TXD32 Pin Input Data Inversion Switch
Selects whether input data of the TXD32 pin is inverted
or not.
0: Output data of TXD32 pin is not inverted.
1: Output data of TXD32 pin is inverted.
1 SCINV1 0 R/W TXD31 Pin Output Data Inversion Switch
Selects whether output data of the TXD31 pin is
inverted or not.
0: Output data of TXD31 pin is not inverted.
1: Output data of TXD31 pin is inverted.
0 SCINV0 0 R/W RXD31 Pin Input Data Inversion Switch
Selects whether input data of the RXD31 pin is inverted
or not.
0: Input data of RXD31 pin is not inverted.
1: Input data of RXD31 pin is inverted.
Note: When the serial port control register is modified, the data being input or output up to that
point is inverted immediately after the modification, and an invalid data change is input or
output. When modifying the serial port control register, modification must be made in a state
in which data changes are invalidated.
Rev. 1.00, 07/04, page 299 of 570
15.3.10 IrDA Control Register (IrCR)
IrCR controls the IrDA operation of the SCI3_1.
Bit Bit Name
Initial
Value R/W Description
7 IrE 0 R/W IrDA Enable
Selects whether the SCI3_1 I/O pins function as the
SCI or IrDA.
0: TXD31/IrTXD or RXD31/IrRXD pin functions as
TXD31 or RXD31
1: TXD31/IrTXD or RXD31/IrRXD pin functions as
IrTXD or IrRXD
6
5
4
IrCKS2
IrCKS1
IrCKS0
0
0
0
R/W
R/W
R/W
IrDA Clock Select
If the IrDA function is enabled, these bits set the high-
pulse width when encoding the IrTXD output pulse.
000: Bit rate × 3/16
001: φ/2
010: φ/4
011: φ/8
100: φ/16
101: Setting prohibited
11x: Setting prohibited
3 to 0 0 Reserved
These bits are always read as 0 and cannot be
modified.
[Legend] x: Don't care.
Rev. 1.00, 07/04, page 300 of 570
15.4 Operation in Asynchronous Mode
Figure 15.2 shows the general format for asynchronous serial communication. One frame consists
of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and
finally stop bits (high level). In asynchronous mode, synchronization is performed at the falling
edge of the start bit during reception. The data is sampled on the 8th pulse of a clock with a
frequency 16 times the bit period, so that the transfer data is latched at the center of each bit.
Inside the SCI3, the transmitter and receiver are independent units, enabling full duplex. Both the
transmitter and the receiver also have a double-buffered structure, so data can be read or written
during transmission or reception, enabling continuous data transfer. Table 15.8 shows the 16 data
transfer formats that can be set in asynchronous mode. The format is selected by the settings in
SMR as shown in table 15.9.
LSB
Start
bit
MSB
Mark state
Stop bit
Transmit/receive data
1
Serial
data
Parity
bit
1 bit 1 or
2 bits
5, 7, or 8 bits 1 bit,
or none
One unit of transfer data (character or frame)
Figure 15.2 Data Format in Asynchronous Communication
15.4.1 Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK31 (SCK32) pin can be selected as the SCI3's serial clock source, according to the setting
of the COM bit in SMR and the CKE0 and CKE1 bits in SCR. When an external clock is input at
the SCK31 (SCK32) pin, the clock frequency should be 16 times the bit rate used. For details on
selection of the clock source, see table 15.10. When the SCI3 is operated on an internal clock, the
clock can be output from the SCK31 (SCK32) pin. The frequency of the clock output in this case
is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the
transfer data, as shown in figure 15.3.
0
1 character (frame)
D0 D1 D2 D3 D4 D5 D6 D7 0/1 11
Clock
Serial data
Figure 15.3 Relationship between Output Clock and T ransfer Data Phase
(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits)
Rev. 1.00, 07/04, page 301 of 570
Table 15.8 Data Transfer Formats (Asynchronous Mode)
1
START
START
START
START
START
START
START
START
START
START
START
START
2345
8-bit data
8-bit data
8-bit data
8-bit data
5-bit data
5-bit data
7-bit data
7-bit data
7-bit data
7-bit data
7-bit data
7-bit data
6789
STOP
STOP
10
STOP
STOP
11
STOP
MPB
STOP
MPB
STOP
STOP
STOP
STOP
P
STOP
P
STOP
STOP
MPB
STOP
12
STOP
MPB
STOP
STOP
STOP
SMR
CHR PE MP STOP
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
0
1
0
11
START
START
8-bit data
8-bit data
P
STOP
P
STOP STOP
START
START
5-bit data
5-bit data
STOPP
PSTOP
STOP
Serial Data Transfer Format and Frame Length
[Legend]
START:
STOP:
P:
MPB:
Start bit
Stop bit
Parity bit
Multiprocessor bit
Rev. 1.00, 07/04, page 302 of 570
Table 15.9 SMR Settings and Corresponding Data Transfer Formats
SMR Data Transfer Format
Bit 7
COM Bit 6
CHR Bit 2
MP Bit 5
PE Bit 3
STOP
Mode Data
Length Multiprocessor
Bit Parity
Bit Stop Bit
Length
0 1 bit 0
1
No
2 bits
0 1 bit
0
1
1
8-bit data
Yes
2 bits
0 1 bit 0
1
No
2 bits
0 1 bit
1
0
1
1
7-bit data
No
Yes
2 bits
0 1 bit 0
1
8-bit data Yes
2 bits
0 1 bit
0
1
1
5-bit data No
2 bits
0 1 bit 0
1
7-bit data Yes
No
2 bits
0 1 bit
0
1
1
1
1
Asynchron-
ous mode
5-bit data No Yes
2 bits
1 * 0 * * Clocked
synchrono-us
mode
8-bit data No No No
[Legend] *: Don't care.
Rev. 1.00, 07/04, page 303 of 570
Table 15.10 SMR and SCR Settings and Clock Source Selection
SMR SCR
Bit 7 Bit 1 Bit 0
Transmit/Receive Clock
COM CKE1 CKE0
Mode Clock Source SCK Pin Function
0 I/O port (SCK31 or SCK32 pin
not used)
0
1
Internal
Outputs clock with same
frequency as bit rate
0
1 0
Asynchronous
mode
External Inputs clock with frequency 16
times bit rate
0 0 Internal Outputs serial clock 1
1 0
Clocked
synchronous mode External Inputs serial clock
0 1 1
1 0 1
1 1 1
Reserved (Do not specify these combinations)
Rev. 1.00, 07/04, page 304 of 570
15.4.2 SCI3 Initialization
Follow the flowchart as shown in figure 15.4 to initialize the SCI3. When the TE bit is cleared to
0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of
the RDRF, PER, FER, and OER flags, or the contents of RDR. When the external clock is used in
asynchronous mode, the clock must be supplied even during initialization. When the external
clock is used in clocked synchronous mode, the clock must not be supplied during initialization.
Wait
<Initialization completion>
Start initialization
Set data transfer format in SMR
[1]
Set CKE1 and CKE0 bits in SCR3
No
Yes
Set value in BRR
Clear TE and RE bits in SCR to 0
[2]
[3]
Set TE and RE bits in
SCR to 1, and set RIE, TIE, TEIE,
and MPIE bits.
Set SPC32 (SPC31) bit in SPCR to 1
[4]
1-bit interval elapsed?
[1] Set the clock selection in SCR.
Be sure to clear bits RIE, TIE, TEIE, and
MPIE, and bits TE and RE, to 0.
When the clock output is selected in
asynchronous mode, clock is output
immediately after CKE1 and CKE0
settings are made. When the clock
output is selected at reception in clocked
synchronous mode, clock is output
immediately after CKE1, CKE0, and RE
are set to 1.
[2] Set the data transfer format in SMR.
[3] Write a value corresponding to the bit
rate to BRR. Not necessary if an
external clock is used.
[4] Wait at least one bit interval, then set the
TE bit or RE bit in SCR to 1. Setting bits
TE and RE enables the TXD31 (TXD32)
and RXD31 (RXD32) pins to be used.
Also set the RIE, TIE, TEIE, and MPIE
bits, depending on whether interrupts are
required. In asynchronous mode, the bits
are marked at transmission and idled at
reception to wait for the start bit.
Figure 15.4 Sample SCI3 Initi ali zation Flowchar t
Rev. 1.00, 07/04, page 305 of 570
15.4.3 Data Transmission
Figure 15.5 shows an example of operation for transmission in asynchronous mode. In
transmission, the SCI3 operates as described below.
1. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that
data has been written to TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI3 sets the TDRE flag to 1 and starts
transmission. If the TIE bit in SCR is set to 1 at this time, a TXI31 (TXI32) interrupt request is
generated. Continuous transmission is possible because the TXI31 (TXI32) interrupt routine
writes next transmit data to TDR before transmission of the current transmit data has been
completed.
3. The SCI3 checks the TDRE flag at the timing for sending the stop bit.
4. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then
serial transmission of the next frame is started.
5. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the “mark
state” is entered, in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI
interrupt request is generated.
6. igure 15.6 shows a sample flowchart for transmission in asynchronous mode.
1 frame
Start
bit
Start
bit
Transmit
data
Transmit
data
Parity
bit
Stop
bit
Parity
bit
Stop
bit
Mark
state
1 frame
01D0D1D70/11 110D0D1 D70/1
Serial
data
TDRE
TEND
LSI
operation
TXI31 (TXI32)
interrupt
request
generated
TDRE flag
cleared to 0
User
processing
Data written
to TDR
TXI31 (TXI32) interrupt request
generated
TEI31 (TEI32) interrupt request
generated
Figure 15.5 Example SCI3 Operation in Transmission in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)
Rev. 1.00, 07/04, page 306 of 570
No
<End>
Yes
Start transmission
Read TDRE flag in SSR
Set SPC32 (SPC31) bit in SPCR to 1
[1]
Write transmit data to TDR
Yes
No
No
Yes
Read TEND flag in SSR
[2]
No
Yes
[3]
Clear PDR to 0 and
set PCR to 1
Clear TE bit in SCR to 0
TDRE = 1
All data transmitted?
TEND = 1
Break output?
[1] Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. When data is
written to TDR, the TDRE flag is
automaticaly cleared to 0.
(After the TE bit is set to 1, one
frame of 1 is output, then
transmission is possible.)
[2] To continue serial transmission,
read 1 from the TDRE flag to
confirm that writing is possible,
then write data to TDR. When data
is written to TDR, the TDRE flag is
automaticaly cleared to 0.
[3] To output a break in serial
transmission, after setting PCR to 1
and PDR to 0, clear the TE bit in
SCR to 0.
Figure 15.6 Sample Serial Transmission Flowchart (As ynchronous Mode)
Rev. 1.00, 07/04, page 307 of 570
15.4.4 Serial Data Reception
Figure 15.7 shows an example of operation for reception in asynchronous mode. In serial
reception, the SCI operates as described below.
1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs
internal synchronization, receives data in RSR, and checks the parity bit and stop bit.
• Parity check
The SCI3 checks that the number of 1 bits in the receive data conforms to the parity (odd or
even) set in bit PM in the serial mode register (SMR).
• Stop bit check
The SCI3 checks that the stop bit is 1. If two stop bits are used, only the first is checked.
• Status check
The SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred
from RSR to RDR.
2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an
ERI31 (ERI32) interrupt request is generated. Receive data is not transferred to RDR.
3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to
RDR. If the RIE bit in SCR is set to 1 at this time, an ERI31 (ERI32) interrupt request is
generated.
4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive
data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI31 (ERI32)
interrupt request is generated.
5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI31 (RXI32) interrupt
request is generated. Continuous reception is possible because the RXI31 (RXI32) interrupt
routine reads the receive data transferred to RDR before reception of the next receive data has
been completed.
Rev. 1.00, 07/04, page 308 of 570
1 frame
Start
bit
Start
bit
Receive
data
Receive
data
Parity
bit
Stop
bit
Parity
bit
Stop
bit
Mark state
(idle state)
1 frame
01 D0 D1 D7 0/1 1 0 10 D0 D1 D7 0/1
Serial
data
RDRF
FER
LSI
operation
User
processing
RDRF
cleared to 0
RDR data read Framing error
processing
RXI31 (RXI32)
request
0 stop bit
detected
ERI request in
response to
framing error
Figure 15.7 Example SCI3 Operation in Reception in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)
Table 15.11 shows the states of the SSR status flags and receive data handling when a receive
error is detected. If a receive error is detected, the RDRF flag retains its state before receiving
data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the
OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.8 shows a sample
flowchart for serial data reception.
Table 15.11 SSR Status Flags and Receive Data Handling
SSR Status Flag
RDRF* OER FER PER Receive Data Receive Error Type
1 1 0 0 Lost Overrun error
0 0 1 0 Transferred to RDR Framing error
0 0 0 1 Transferred to RDR Parity error
1 1 1 0 Lost Overrun error + framing error
1 1 0 1 Lost Overrun error + parity error
0 0 1 1 Transferred to RDR Framing error + parity error
1 1 1 1 Lost Overrun error + framing error +
parity error
Note: * The RDRF flag retains the state it had before data reception. However, note that if RDR
is read after an overrun error has occurred in a frame because reading of the receive
data in the previous frame was delayed, the RDRF flag will be cleared to 0.
Rev. 1.00, 07/04, page 309 of 570
Yes
<End>
No
Start reception
[1]
No
Yes
Read RDRF flag in SSR [2]
[3]
Clear RE bit in SCR to 0
Read OER, PER, and
FER flags in SSR
Error processing
(Continued on next page)
[4]
Read receive data in RDR
Yes
No
OER+PER+FER = 1
RDRF = 1
All data received?
[1] Read the OER, PER, and FER flags in
SSR to identify the error. If a receive
error occurs, performs the appropriate
error processing.
[2] Read SSR and check that RDRF = 1,
then read the receive data in RDR.
The RDRF flag is cleared automatically.
[3] To continue serial reception, before the
stop bit for the current frame is
received, read the RDRF flag and read
RDR.
The RDRF flag is cleared automatically.
[4] If a receive error occurs, read the OER,
PER, and FER flags in SSR to identify
the error. After performing the
appropriate error processing, ensure
that the OER, PER, and FER flags are
all cleared to 0. Reception cannot be
resumed if any of these flags are set to
1. In the case of a framing error, a
break can be detected by reading the
value of the input port corresponding to
the RXD31 (RXD32) pin.
(A)
Figure 15.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (1)
Rev. 1.00, 07/04, page 310 of 570
<End>
(A)
Error processing
Parity error processing
Yes
No
Clear OER, PER, and
FER flags in SSR to 0
No
Yes
No
Yes
Framing error processing
No
Yes
Overrun error processing
OER = 1
FER = 1
Break?
PER = 1
[4]
Figure 15.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (2)
Rev. 1.00, 07/04, page 311 of 570
15.5 Operation in Clocked Synchronous Mode
Figure 15.9 shows the general format for clocked synchronous communication. In clocked
synchronous mode, data is transmitted or received synchronous with clock pulses. A single
character in the transmit data consists of the 8-bit data starting from the LSB. In clocked
synchronous serial communication, data on the transmission line is output from one falling edge of
the serial clock to the next. In clocked synchronous mode, the SCI3 receives data in synchronous
with the rising edge of the serial clock. After 8-bit data is output, the transmission line holds the
MSB state. In clocked synchronous mode, no parity or multiprocessor bit is added. Inside the
SCI3, the transmitter and receiver are independent units, enabling full-duplex communication
through the use of a common clock. Both the transmitter and the receiver also have a double-
buffered structure, so data can be read or written during transmission or reception, enabling
continuous data transfer.
Don't
care
Don't
care
One unit of transfer data (character or frame)
8-bit
Bit 0
Serial data
Synchronization
clock
Bit 1 Bit 3 Bit 4 Bit 5
LSB MSB
Bit 2 Bit 6 Bit 7
*
*
Note: * High except in continuous transfer
Figure 15.9 Data Format in Clocked Synchronous Communication
15.5.1 Clock
Either an internal clock generated by the on-chip baud rate generator or an external
synchronization clock input at the SCK31 (SCK32) pin can be selected, according to the setting of
the COM bit in SMR and CKE0 and CKE1 bits in SCR. When the SCI3 is operated on an internal
clock, the serial clock is output from the SCK31 (SCK32) pin. Eight serial clock pulses are output
in the transfer of one character, and when no transfer is performed the clock is fixed high.
15.5.2 SCI3 Initialization
Before transmitting and receiving data, the SCI3 should be initialized as described in a sample
flowchart in figure 15.4.
Rev. 1.00, 07/04, page 312 of 570
15.5.3 Serial Data Transmission
Figure 15.10 shows an example of SCI3 operation for transmission in clocked synchronous mode.
In serial transmission, the SCI3 operates as described below.
1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI recognizes that data has
been written to TDR, and transfers the data from TDR to TSR.
2. The SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at
this time, a TXI31 (TXI32) interrupt request is generated.
3. 8-bit data is sent from the TXD31 (TXD32) pin synchronized with the output clock when
output clock mode has been specified, and synchronized with the input clock when use of an
external clock has been specified. Serial data is transmitted sequentially from the LSB (bit 0),
from the TXD31 (TXD32) pin.
4. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7).
5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission
of the next frame is started.
6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains
the output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI31 (TEI32)
is generated.
7. The SCK31 (SCK32) pin is fixed high.
Figure 15.11 shows a sample flowchart for serial data transmission. Even if the TDRE flag is
cleared to 0, transmission will not start while a receive error flag (OER, FER, or PER) is set to 1.
Make sure that the receive error flags are cleared to 0 before starting transmission.
Serial
clock
Serial
data Bit 1Bit 0 Bit 7 Bit 0
1 frame 1 frame
Bit 1 Bit 6 Bit 7
TDRE
TEND
LSI
operation
User
processing
TXI31 (TXI32) interrupt request
generated
Data written
to TDR
TDRE flag
cleared
to 0
TXI31 (TXI32)
interrupt
request
generated
TEI31 (TEI32) interrupt request
generated
Figure 15.10 Example of SCI3 Operation in Transmission in Clocked Synchronous Mode
Rev. 1.00, 07/04, page 313 of 570
No
<End>
Yes
Start transmission
Read TDRE flag in SSR
Set SPC32 (SPC31) bit in SPCR to 1
[1]
Write transmit data to TDR
No
Yes
No
Yes
Read TEND flag in SSR
[2]
Clear TE bit in SCR to 0
TDRE = 1
All data transmitted?
TEND = 1
[1] Read SSR and check that the TDRE flag is
set to 1, then write transmit data to TDR.
When data is written to TDR, the TDRE flag
is automatically cleared to 0. When clock
output is selected and data is written to
TDR, clocks are output to start the data
transmission.
[2] To continue serial transmission, be sure to
read 1 from the TDRE flag to confirm that
writing is possible, then write data to TDR.
When data is written to TDR, the TDRE flag
is automatically cleared to 0.
Figure 15.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode)
Rev. 1.00, 07/04, page 314 of 570
15.5.4 Serial Data Reception (Clocked Synchronous Mode)
Figure 15.12 shows an example of SCI3 operation for reception in clocked synchronous mode. In
serial reception, the SCI3 operates as described below.
1. The SCI3 performs internal initialization synchronous with a synchronous clock input or
output, starts receiving data.
2. The SCI3 stores the received data in RSR.
3. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
in SSR is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this
time, an ERI31 (ERI32) interrupt request is generated, receive data is not transferred to RDR,
and the RDRF flag remains to be set to 1.
4. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI31 (RXI32) interrupt
request is generated.
Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
Serial
data
RDRF
OER
LSI
operation
RXI31 (RXI32)interrupt
request generated
RXI31 (RXI32)
interrupt
request
generated
ERI interrupt request
generated by
overrun error
Overrun error
processing
RDRF flag
cleared
to 0
RDR data read RDR data has
not been read
(RDRF = 1)
User
processing
Serial
clock
1 frame 1 frame
Figure 15.12 Example of SCI3 Reception Operation in Clocked Synchronous Mode
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.13 shows a sample flowchart
for serial data reception.
Rev. 1.00, 07/04, page 315 of 570
Yes
<End>
No
Start reception
[1]
[4]
No
Yes
Read RDRF flag in SSR [2]
[3]
Clear RE bit in SCR to 0
Overrun error processing
(Continued below)
Read receive data in RDR
Yes
No
OER = 1?
RDRF = 1?
Data reception continued?
Read OER flag in SSR
<End>
Start overrun error processing
Overrun error processing
Clear OER flag in SSR to 0
[4]
[1] Read the OER flag in SSR to determine if
there is an error. If an overrun error has
occurred, execute overrun error processing.
[2] Read SSR and check that the RDRF flag is
set to 1, then read the receive data in RDR.
When data is read from RDR, the RDRF
flag is automatically cleared to 0.
[3] To continue serial reception, before the
MSB (bit 7) of the current frame is received,
reading the RDRF flag and reading RDR
should be finished. When data is read from
RDR, the RDRF flag is automatically
cleared to 0.
[4] If an overrun error occurs, read the OER
flag in SSR, and after performing the
appropriate error processing, clear the OER
flag to 0. Reception cannot be resumed if
the OER flag is set to 1.
Figure 15.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode)
Rev. 1.00, 07/04, page 316 of 570
15.5.5 Simultaneous Serial Data Transmission and Reception
Figure 15.14 shows a sample flowchart for simultaneous serial transmit and receive operations.
The following procedure should be used for simultaneous serial data transmit and receive
operations. To switch from transmit mode to simultaneous transmit and receive mode, after
checking that the SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear
TE to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive
mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished
reception, clear RE to 0. Then after checking that the RDRF and receive error flags (OER, FER,
and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single instruction.
Yes
<End>
No
Start transmission/reception
[3]
Overrun error processing
[4]
Read receive data in RDR
Yes
No
OER = 1
Data transmission/reception
continued?
[1]
Read TDRE flag in SSR
Set SPC32 (SPC31) bit in SPCR to 1
No
Yes
TDRE = 1
Write transmit data to TDR
No
Yes
RDRF = 1
Read OER flag in SSR
[2]
Read RDRF flag in SSR
Clear TE and RE bits in SCR to 0
[1] Read SSR and check that the TDRE
flag is set to 1, then write transmit
data to TDR.
When data is written to TDR, the
TDRE flag is automatically cleared to
0.
[2] Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR.
When data is read from RDR, the
RDRF flag is automatically cleared to
0.
[3] To continue serial transmission/
reception, before the MSB (bit 7) of
the current frame is received, finish
reading the RDRF flag, reading RDR.
Also, before the MSB (bit 7) of the
current frame is transmitted, read 1
from the TDRE flag to confirm that
writing is possible. Then write data to
TDR.
When data is written to TDR, the
TDRE flag is automatically cleared to
0. When data is read from RDR, the
RDRF flag is automatically cleared to
0.
[4] If an overrun error occurs, read the
OER flag in SSR, and after
performing the appropriate error
processing, clear the OER flag to 0.
Transmission/reception cannot be
resumed if the OER flag is set to 1.
For overrun error processing, see
figure 15.13.
Figure 15.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
(Clocked Synchronous Mode)
Rev. 1.00, 07/04, page 317 of 570
15.6 Multiprocessor Communication Function
Use of the multiprocessor communication function enables data transfer between a number of
processors sharing communication lines by asynchronous serial communication using the
multiprocessor format, in which a multiprocessor bit is added to the transfer data. When
multiprocessor communication is performed, each receiving station is addressed by a unique ID
code. The serial communication cycle consists of two component cycles; an ID transmission cycle
that specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to
differentiate between the ID transmission cycle and the data transmission cycle. If the
multiprocessor bit is 1, the cycle is an ID transmission cycle; if the multiprocessor bit is 0, the
cycle is a data transmission cycle. Figure 15.15 shows an example of inter-processor
communication using the multiprocessor format. The transmitting station first sends the ID code
of the receiving station with which it wants to perform serial communication as data with a 1
multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added.
When data with a 1 multiprocessor bit is received, the receiving station compares that data with its
own ID. The station whose ID matches then receives the data sent next. Stations whose IDs do not
match continue to skip data until data with a 1 multiprocessor bit is again received.
The SCI3 uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1,
transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags,
RDRF, FER, and OER to 1, are inhibited until data with a 1 multiprocessor bit is received. On
reception of a receive character with a 1 multiprocessor bit, the MPBR bit in SSR is set to 1 and
the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is
set to 1 at this time, an RXI31 (RXI32) interrupt is generated.
When the multiprocessor format is selected, the parity bit setting is rendered invalid. All other bit
settings are the same as those in normal asynchronous mode. The clock used for multiprocessor
communication is the same as that in normal asynchronous mode.
Transmitting
station
Receiving
station A
Receiving
station B
Receiving
station C
Receiving
station D
(ID = 01) (ID = 02) (ID = 03) (ID = 04)
Serial transmission line
Serial
data
ID transmission cycle =
receiving station
specification
Data transmission cycle =
Data transmission to
receiving station specified by ID
(MPB = 1) (MPB = 0)
H'01 H'AA
[Legend]
MPB: Multiprocessor bit
Figure 15.15 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A)
Rev. 1.00, 07/04, page 318 of 570
15.6.1 Multiprocessor Serial Data Transmission
Figure 15.16 shows a sample flowchart for multiprocessor serial data transmission. For an ID
transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission
cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI3 operations are the same
as those in asynchronous mode.
No
<End>
Yes
Start transmission
Read TDRE flag in SSR
Set SPC32 (SPC31) bit in SPCR to 1
[1]
Set MPBT bit in SSR
Yes
No
No
Yes
Read TEND flag in SSR
[2]
No
Yes
[3]
Clear PDR to 0 and set PCR to 1
Clear TE bit in SCR to 0
TDRE = 1
Data transmission continued?
TEND = 1?
Break output?
Write transmit data to TDR
[1] Read SSR and check that the TDRE
flag is set to 1, set the MPBT bit in
SSR to 0 or 1, then write transmit
data to TDR. When data is written to
TDR, the TDRE flag is automatically
cleared to 0.
[2] To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR. When data is
written to TDR, the TDRE flag is
automatically cleared to 0.
[3] To output a break in serial
transmission, set the port PCR to 1,
clear PDR to 0, then clear the TE bit
in SCR to 0.
Figure 15.16 Sample Multiprocessor Serial Transmission Flowchart
Rev. 1.00, 07/04, page 319 of 570
15.6.2 Multiprocessor Serial Data Reception
Figure 15.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in
SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving data
with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI31 (RXI32) interrupt
request is generated at this time. All other SCI3 operations are the same as in asynchronous mode.
Figure 15.18 shows an example of SCI3 operation for multiprocessor format reception.
Yes
<End>
No
Start reception
No
Yes
[4]
Clear RE bit in SCR to 0
Receive error processing
(Continued on
next page)
[5]
Yes
No
FER+OER = 1
RDRF = 1
Data reception continued?
Set MPIE bit in SCR to 1 [1]
[2]
Read OER and FER flags in SSR
Read RDRF flag in SSR [3]
Read receive data in RDR
No
Yes
[A]
This station’s ID?
Read OER and FER flags in SSR
Yes
No
Read RDRF flag in SSR
No
Yes
FER+OER = 1
Read receive data in RDR
RDRF = 1
[1] Set the MPIE bit in SCR to 1.
[2] Read OER and FER in SSR to check for
errors. Receive error processing is performed
in cases where a receive error occurs.
[3] Read SSR and check that the RDRF flag is
set to 1, then read the receive data in RDR
and compare it with this station’s ID.
If the data is not this station’s ID, set the MPIE
bit to 1 again.
When data is read from RDR, the RDRF flag
is automatically cleared to 0.
[4] Read SSR and check that the RDRF flag is
set to 1, then read the data in RDR.
[5] If a receive error occurs, read the OER and
FER flags in SSR to identify the error. After
performing the appropriate error processing,
ensure that the OER and FER flags are all
cleared to 0.
Reception cannot be resumed if either of
these flags is set to 1.
In the case of a framing error, a break can be
detected by reading the RXD31 (RXD32) pin
value.
Figure 15.17 Sample Multiprocessor Serial Reception Flowchart (1)
Rev. 1.00, 07/04, page 320 of 570
<End>
Start receive error processing
Yes
No
Clear OER and
FER flags in SSR to 0
No
Yes
No
Yes
Framing error processing
Overrun error processing
OER = 1?
FER = 1?
Break?
[5]
[A]
Figure 15.17 Sample Multiprocessor Serial Reception Flowchart (2)
Rev. 1.00, 07/04, page 321 of 570
RXI31 (RXI32)
interrupt
request
MPIE cleared
to 0
RXI31 (RXI32)
interrupt request
is not generated, and
RDR retains its state
RXI31 (RXI32)
interrupt
request
MPIE cleared
to 0
RXI31 (RXI32)
interrupt
request
1 frame
Start
bit
Start
bit
Receive
data (ID1)
Receive data
(Data1)
MPB MPB
Stop
bit
Stop
bit
Mark state
(idle state)
1 frame
01D0D1D711 110D0D1 D7
ID1
0
Serial
data
MPIE
RDRF
RDR
value
RDR
value
LSI
operation
User
processing
RDRF flag
cleared
to 0
RDR data read When data is not
this station's ID,
MPIE is set to 1
again
1 frame
Start
bit
Start
bit
Receive
data (ID2)
Receive data
(Data2)
MPB MPB
Stop
bit
Stop
bit
Mark state
(idle state)
1 frame
01D0D1D711 110
(a) When data does not match this receiver's ID
(b) When data matches this receiver's ID
D0 D1 D7
ID2 Data2ID1
0
Serial
data
MPIE
RDRF
LSI
operation
User
processing
RDRF flag
cleared
to 0
RDRF flag
cleared
to 0
RDR data read When data is
this station's
ID, reception
is continued
RDR data read
MPIE set to 1
again
Figure 15.18 Example of SCI3 Operation in Reception Using Multiprocessor Format
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
Rev. 1.00, 07/04, page 322 of 570
15.7 IrDA Operation
IrDA operation can be used with the SCI3_1. Figure 15.19 shows an IrDA block diagram.
If the IrDA function is enabled using the IrE bit in IrCR, the TXD31 and RXD31 pins in the
SCI3_1 are allowed to encode and decode the waveform based on the IrDA standard version 1.0
(function as the IrTXD and IrRXD pins). Connecting these pins to the infrared data
transceiver/receiver achieves infrared data communication based on the system defined by the
IrDA standard version 1.0.
In the system defined by the IrDA standard version 1.0, communication is started at a transfer rate
of 9600 bps, which can be modified as required. The IrDA interface provided by this LSI does not
incorporate the capability of automatic modification of the transfer rate; the transfer rate must be
modified through programming.
IrDA SCI3_1
IrCR
TXD31/IrTXD
RXD31/IrRXD
TXD
RXD
Pulse encoderPhase inversion
Phase inversion Pulse decoder
Figure 15.19 IrDA Block Diagram
15.7.1 Transmission
During transmission, the output signals from the SCI (UART frames) are converted to IR frames
using the IrDA interface (see figure 15.20).
For serial data of level 0, a high-level pulse having a width of 3/16 of the bit rate (1-bit interval) is
output (initial setting). The high-level pulse can be selected using the IrCKS2 to IrCKS0 bits in
IrCR.
The high-level pulse width is defined to be 1.41 µs at minimum and (3/16 + 2.5%) × bit rate or
(3/16 × bit rate) +1.08 µs at maximum. For example, when the frequency of system clock φ is 10
MHz, a high-level pulse width of at least 2.82 µs to 3.2 µs can be specified.
For serial data of level 1, no pulses are output.
Rev. 1.00, 07/04, page 323 of 570
UART frame
Data
IR frame
Data
0000 011 11 1
0000 011 11 1
Transmission Reception
Bit
cycle
Pulse width is 1.6 µs to
3/16 bit cycle
Start
bit
Stop
bit
Stop
bit
Start
bit
Figure 15.20 IrDA Transmission and Reception
15.7.2 Reception
During reception, IR frames are converted to UART frames using the IrDA interface before
inputting to the SCI3_1.
Data of level 0 is output each time a high-level pulse is detected and data of level 1 is output when
no pulse is detected in a bit cycle. If a pulse has a high-level width of less than 2.82 µs, the
minimum width allowed, the pulse is recognized as level 0.
Rev. 1.00, 07/04, page 324 of 570
15.7.3 High-Level Pulse Width Selection
Table 15.12 shows possible settings for bits IrCKS2 to IrCKS0 (minimum pulse width), and this
LSI's operating frequencies and bit rates, for making the pulse width shorter than 3/16 times the bit
rate in transmission.
Table 15.12 IrCKS2 to IrCKS0 Bit Settings
Operating Bit Rate (bps) (Upper Row) / Bit Interval × 3/16 (µs) (Lower Row)
Frequency 2400 9600 19200 38400
φ (MHz) 78.13 19.53 9.77 4.88
2 010 010 010 010
2.097152 010 010 010 010
2.4576 010 010 010 010
3 011 011 011 011
3.6864 011 011 011 011
4.9152 011 011 011 011
5 011 011 011 011
6 100 100 100 100
6.144 100 100 100 100
7.3728 100 100 100 100
8 100 100 100 100
9.8304 100 100 100 100
10 100 100 100 100
Rev. 1.00, 07/04, page 325 of 570
15.8 Interrupt Requests
The SCI3 creates the following six interrupt requests: transmit end, transmit data empty, receive
data full, and receive errors (overrun error, framing error, and parity error). Table 15.13 shows the
interrupt sources.
Table 15.13 SCI3 Interrupt Reques ts
Interrupt Requests Abbreviation Interrupt Sources
Receive Data Full RXI Setting RDRF in SSR
Transmit Data Empty TXI Setting TDRE in SSR
Transmission End TEI Setting TEND in SSR
Receive Error ERI Setting OER, FER, and PER in SSR
Each interrupt request can be enabled or disabled by means of bits TIE and RIE in SCR.
When the TDRE bit in SSR is set to 1, a TXI31 (TXI32) interrupt is requested. When the TEND
bit in SSR is set to 1, a TEI31 (TEI32) interrupt is requested. These two interrupts are generated
during transmission.
The initial value of the TDRE flag in SSR is 1. Thus, when the TIE bit in SCR is set to 1 before
transferring the transmit data to TDR, a TXI31 (TXI32) interrupt request is generated even if the
transmit data is not ready. The initial value of the TEND flag in SSR is 1. Thus, when the TEIE bit
in SCR is set to 1 before transferring the transmit data to TDR, a TEI31 (TEI32) interrupt request
is generated even if the transmit data has not been sent. It is possible to make use of the most of
these interrupt requests efficiently by transferring the transmit data to TDR in the interrupt routine.
To prevent the generation of these interrupt requests (TXI31 and TEI31), set the enable bits (TIE
and TEIE) that correspond to these interrupt requests to 1, after transferring the transmit data to
TDR.
When the RDRF bit in SSR is set to 1, an RXI31 (RXI32) interrupt is requested, and if any of bits
OER, PER, and FER is set to 1, an ERI31 (ERI32) interrupt is requested. These two interrupt
requests are generated during reception.
The SCI3 can carry out continuous reception using an RXI31 (RXI32) and continuous
transmission using a TXI31 (TXI32).
These interrupts are shown in table 15.14.
Rev. 1.00, 07/04, page 326 of 570
Table 15.14 Transmit/Receive Interrupts
Interrupt Flags Interrupt Request Conditions Notes
RXI31
(RXI32)
RDRF
RIE
When serial reception is
performed normally and receive
data is transferred from RSR to
RDR, bit RDRF is set to 1, and if
bit RIE is set to 1 at this time, an
RXI31 (RXI32) is enabled and an
interrupt is requested. (See figure
15.21 (a).)
The RXI31 (RXI32) interrupt
routine reads the receive data
transferred to RDR and clears bit
RDRF to 0. Continuous reception
can be performed by repeating
the above operations until
reception of the next RSR data is
completed.
TXI31
(TXI32)
TDRE
TIE
When TSR is found to be empty
(on completion of the previous
transmission) and the transmit
data placed in TDR is transferred
to TSR, bit TDRE is set to 1. If bit
TIE is set to 1 at this time, a
TXI31 (TXI32) is enabled and an
interrupt is requested. (See figure
15.21 (b).)
The TXI31 (TXI32) interrupt
routine writes the next transmit
data to TDR and clears bit TDRE
to 0. Continuous transmission can
be performed by repeating the
above operations until the data
transferred to TSR has been
transmitted.
TEI31
(TEI32)
TEND
TEIE
When the last bit of the character
in TSR is transmitted, if bit TDRE
is set to 1, bit TEND is set to 1. If
bit TEIE is set to 1 at this time, a
TEI31 (TEI32) is enabled and an
interrupt is requested. (See figure
15.21 (c).)
A TEI31 (TEI32) indicates that the
next transmit data has not been
written to TDR when the last bit of
the transmit character in TSR is
transmitted.
Rev. 1.00, 07/04, page 327 of 570
RDR
→
RSR (reception in progress)
RDRF = 0
RXD31 (RXD32) pin
RDR
RSR↑ (reception completed, transfer)
RDRF 1
(RXI request when RIE = 1)
RXD31 (RXD32) pin
Figure 15.21 (a) RDRF Setting and RXI Interrupt
TDR (next transmit data)
TSR (transmission in progress)
TDRE = 0
TXD31 (TXD32) pin
TDR
TSR (transmission completed, transfer)
TDRE 1
(TXI request when TIE = 1)
TXD31 (TXD32) pin
→
↓
Figure 15.21 (b) TDRE Setting and TXI Interrupt
TDR
TSR (transmission in progress)
TEND = 0
TXD31 (TXD32) pin
TDR
TSR (transmission completed)
TEND 1
(TEI request when TEIE = 1)
TXD31 (TXD32) pin
→
Figure 15.21 (c) TEND Setting and TEI Interrupt
Rev. 1.00, 07/04, page 328 of 570
15.9 Usage Notes
15.9.1 Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RXD31
(RXD32) pin value directly. In a break, the input from the RXD31 (RXD32) pin becomes all 0,
setting the FER flag, and possibly the PER flag. Note that as the SCI3 continues the receive
operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again.
15.9.2 Mark State and Break Sending
When TE is 0, the TXD31 (TXD32) pin is used as an I/O port whose direction (input or output)
and level are determined by PCR and PDR. This can be used to set the TXD31 (TXD32) pin to
mark state (high level) or send a break during serial data transmission. To maintain the
communication line at mark state until TE is set to 1, set both PCR and PDR to 1. As TE is cleared
to 0 at this point, the TXD31 (TXD32) pin becomes an I/O port, and 1 is output from the TXD31
(TXD32) pin. To send a break during serial transmission, first set PCR to 1 and PDR to 0, and
then clear TE to 0. When TE is cleared to 0, the transmitter is initialized regardless of the current
transmission state, the TXD31 (TXD32) pin becomes an I/O port, and 0 is output from the TXD31
(TXD32) pin.
15.9.3 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Transmission cannot be started when a receive error flag (OER, PER, or FER) is set to 1, even if
the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting
transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared
to 0.
Rev. 1.00, 07/04, page 329 of 570
15.9.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 16 times the
transfer rate. In reception, the SCI3 samples the falling edge of the start bit using the basic clock,
and performs internal synchronization. Receive data is latched internally at the rising edge of the
8th pulse of the basic clock as shown in figure 15.22.
Thus, the reception margin in asynchronous mode is given by formula (1) below.
M = (0.5 – ) – – (L – 0.5) F × 100(%)
1
2N
D – 0.5
N
... Formula (1)
Where N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in
formula (1), the reception margin can be given by the formula.
M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed for in
system design.
Internal basic
clock
16 clocks
8 clocks
Receive data
(RXD31/RXD32)
Synchronization
sampling timing
Start bit D0 D1
Data sampling
timing
15 0 7 15 00 7
Figure 15.22 Receive Data Sampling Timing in Asynchronous Mode
Rev. 1.00, 07/04, page 330 of 570
15.9.5 Note on Switc hi ng SC K3 1 ( S CK 3 2) Pin Function
If pin SCK31 (SCK32) is used as a clock output pin by the SCI3 in clocked synchronous mode
and is then switched to a general input/output pin (a pin with a different function), the pin outputs
a low level signal for half a system clock (φ) cycle immediately after it is switched.
This can be prevented by either of the following methods according to the situation.
(1) When SCK31 (SCK32) Function is Switched from Clock Output to Non Clock-Output
When stopping data transfer, issue one instruction to clear bits TE and RE to 0 and to set bits
CKE1 and CKE0 in SCR to 1 and 0, respectively.
In this case, bit COM in SMR should be left 1. The above prevents the SCK31 (SCK32) pin from
being used as a general input/output pin. To avoid an intermediate level of voltage from being
applied to the SCK31 (SCK32) pin, the line connected to the SCK31 (SCK32) pin should be
pulled up to the VCC level via a resistor, or supplied with output from an external device.
(2) When SCK31 (SCK32) Function is Switched from Clock Output to General
Input/Output
When stopping data transfer,
1. Issue one instruction to clear bits TE and RE to 0 and to set bits CKE1 and CKE0 in SCR to 1
and 0, respectively.
2. Clear bit COM in SMR to 0
3. Clear bits CKE1 and CKE0 in SCR to 0. Note that special care is also needed here to avoid an
intermediate level of voltage from being applied to the SCK31 (SCK32) pin.
15.9.6 Relation between Writing to TDR and Bit TDRE
Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial
transmission has not been prepared in TDR. When data is written to TDR, bit TDRE is cleared to
0 automatically. When the SCI3 transfers data from TDR to TSR, bit TDRE is set to 1.
Data can be written to TDR irrespective of the state of bit TDRE, but if new data is written to
TDR while bit TDRE is cleared to 0, the data previously stored in TDR will be lost if it has not yet
been transferred to TSR. Accordingly, to ensure that serial transmission is performed dependably,
you should first check that bit TDRE is set to 1, then write the transmit data to TDR only once (not
two or more times).
Rev. 1.00, 07/04, page 331 of 570
15.9.7 Relation between RDR Reading and bit RDRF
In a receive operation, the SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0
when reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1, this
indicates that an overrun error has occurred.
When the contents of RDR are read, bit RDRF is cleared to 0 automatically. Therefore, if RDR is
read more than once, the second and subsequent read operations will be performed while bit
RDRF is cleared to 0. Note that, when an RDR read is performed while bit RDRF is cleared to 0,
if the read operation coincides with completion of reception of a frame, the next frame of data may
be read. This is shown in figure 15.23.
Frame 1 Frame 2 Frame 3
Data 1Communication line
RDRF
RDR
Data 2 Data 3
Data 1 Data 2
RDR read RDR read
(A)
Data 1 is read at point (A)
Data 2 is read at point (B)
(B)
Figure 15.23 Relation between RDR Read Timing and Data
In this case, only a single RDR read operation (not two or more) should be performed after first
checking that bit RDRF is set to 1. If two or more reads are performed, the data read the first time
should be transferred to RAM, etc., and the RAM contents used. Also, ensure that there is
sufficient margin in an RDR read operation before reception of the next frame is completed. To be
precise in terms of timing, the RDR read should be completed before bit 7 is transferred in clocked
synchronous mode, or before the STOP bit is transferred in asynchronous mode.
15.9.8 Transmit and Receive Operations when Making State Transition
Make sure that transmit and receive operations have completely finished before carrying out state
transition processing.
15.9.9 Setting in Subactive or Subsleep Mode
In subactive or subsleep mode, the SCI3 can operate only when the CPU clock is φW/2. The SA1
bit in SYSCR2 should be set to 1.
Rev. 1.00, 07/04, page 332 of 570
Rev. 1.00, 07/04, page 333 of 570
Section 16 Serial Communication Interface 4 (SCI4)
The serial communication interface 4 (SCI4) can handle clocked synchronous serial
communication with the 8-bit buffer. The SCI4 is supported only by the F-ZTAT version. When
the on-chip emulator debugger etc. is used, the SCK4, SI4, and SO4 pins in SCI4 are used by the
system. Therefore the SCI4 is not available for the user.
16.1 Features
• Eight internal clocks (φ/1024, φ/256, φ/64, φ/32, φ/16, φ/8, φ/4, φ/2) or external clock can be
selected as a clock source.
• Receive error detection: Overrun errors detected
• Four interrupt sources
Transmit-end, transmit-data-empty, receive-data-full, and overrun error
• Full-duplex communication capability
Buffering is used in both the transmitter and the receiver, enabling continuous transmission
and continuous reception of serial data.
• When the on-chip emulator debugger etc. is not used, the SCI4 is available for the user.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (For details, refer to section 6.4, Module Standby Function.)
Rev. 1.00, 07/04, page 334 of 570
Figure 16.1 shows a block diagram of the SCI4.
PSS
SCSR4
SCR4
TDR4
SR4
TEI
TXI
RXI
ERI
RDR4
SCK4
Transmit/receive
control circuit
[Legend]
SCSR4:
SCR4:
TDR4:
SR4:
RDR4:
Serial control status register 4
Serial control register 4
Transmit data register 4
Shift register 4
Receive data register 4
φ
SO4
SI4
Internal data bus
Figure 16.1 Block Diagram of SCI4
16.2 Input/Output Pins
Table 16.1 shows the SCI4 pin configuration.
Table 16.1 Pin Configuration
Pin Name Abbreviation I/O Function
SCI4 clock SCK4 I/O SCI4 clock input/output
SCI4 data input SI4 Input SCI4 receive data input
SCI4 data output SO4 Output SCI4 transmit data output
Rev. 1.00, 07/04, page 335 of 570
16.3 Register Descriptions
The SCI4 has the following registers.
• Serial control register 4 (SCR4)
• Serial control/status register 4 (SCSR4)
• Transmit data register 4 (TDR4)
• Receive data register 4 (RDR4)
• Shift Register 4 (SR4)
16.3.1 Serial Control Register 4 (SCR4)
SCR4 enables or disables interrupt requests and controls SCI4 transfer operations.
Bit Bit Name
Initial
Value R/W Description
7 TIE 0 R/W Transmit Interrupt Enable
Enables or disables a transmit data empty interrupt
(TXI) request when serial transmit data is transferred
from TDR4 to SR4 and the TDRE flag in SCSR4 is set
to 1. TXI can be cleared by clearing the TDRE flag in
SCSR4 to 0 after the flag is read as 1 or clearing this
bit to 0.
0: Transmit data empty interrupt (TXI) request disabled
1: Transmit data empty interrupt (TXI) request enabled
6 RIE 0 R/W Receive Interrupt Enable
Enables or disables a receive data full interrupt (RXI)
request and receive error interrupt (ERI) request when
serial receive data is transferred from SR4 to RDR4
and the RDRF flag in SCSR4 is set to 1. RXI and ERI
can be cleared by clearing the RDRF or ORER flag in
SCSR4 to 0 after the flag is read as 1 or clearing this
bit to 0.
0: Receive data full interrupt (RXI) request and receive
error interrupt (ERI) request disabled
1: Receive data full interrupt (RXI) request and receive
error interrupt (ERI) request enabled
Rev. 1.00, 07/04, page 336 of 570
Bit Bit Name
Initial
Value R/W Description
5 TEIE 0 R/W Transmit End Interrupt Enable
Enables or disables a transmit end interrupt (TEI)
request when there is no valid transmit data in TDR4
during transmission of MSB data. TEI can be cleared
by clearing the TEND flag in SCSR4 to 0 after the flag
is read as 1 or clearing this bit to 0.
0: Transmit end interrupt (TEI) request disabled
1: Transmit end interrupt (TEI) request enabled
4 SOL 0 R/W Extended Data
Sets the output level of the SO4 pin. When this bit is
read, the output level of the SO4 pin is read. The
output of the SO4 pin retains the value of the last bit of
transmit data after transmission is completed.
However, if this bit is changed before or after
transmission, the output level of the SO4 pin can be
changed. When the output level of the SO4 pin is
changed, the SOLP bit should be cleared to 0 and the
MOV instruction should be used. Note that this bit
should not be changed during transmission because
incorrect operation may occur.
[When reading]
0: The output level of the SO4 pin is low.
1: The output level of the SO4 pin is high.
[When writing]
0: The output level of the SO4 pin is changed to low.
1: The output level of the SO4 pin is changed to high.
3 SOLP 1 R/W SOL Write Protect
Controls change of the output level of the SO4 pin due
to the change of the SOL bit. When the output level of
the SO4 pin is changed, the setting of SOL = 1 and
SOLP = 0 or SOL = 0 and SOLP = 0 is made by the
MOV instruction. This bit is always read as 1.
0: When writing, the output level is changed according
to the value of the SOL pin.
1: When reading, this bit is always read as 1 and
cannot be modified.
Rev. 1.00, 07/04, page 337 of 570
Bit Bit Name
Initial
Value R/W Description
2 SRES 0 R/W Forcible Reset
When the internal sequencer is forcibly initialized, 1
should be written to this bit. When 1 is written to this
flag, the internal sequencer is forcibly reset and then
this flag is automatically cleared to 0. Note that the
values of the internal registers are retained. (The
TDRE flag in SCSR4 is set to 1 and the RDRF, ORER,
and TEND flags are cleared to 0. The TE and RE bits
in SCR4 are cleared to 0.)
0: Normal operation
1: Internal sequencer is forcibly reset
1 TE 0 R/W Transmit Enable
Enables or disables start of the SCI4 serial
transmission. When this bit is cleared to 0, the TERE
flag in SCSR4 is fixed to 1. When transmit data is
written to TDR4 while this bit is set to 1, the TDRE flag
in SCSR4 is automatically cleared to 0 and serial data
transmission is started.
0: Transmission disabled (SO4 pin functions as I/O
port)
1: Transmission enabled (SO4 pin functions as
transmit data pin)
0 RE 0 R/W Receive Enable
Enables or disables start of the SCI4 serial reception.
Note that the RDRF and ORER flags in SCSR4 are not
affected even if this bit is cleared to 0, and retain their
previous state. Serial data reception is started when
the synchronous clock input is detected while this bit is
set to 1 (when an external clock is selected). When an
internal clock is selected, the synchronous clock is
output and serial data reception is started.
0: Reception disabled (SI4 pin functions as I/O port)
1: Reception enabled (SI4 pin functions as receive data
pin)
Rev. 1.00, 07/04, page 338 of 570
16.3.2 Serial Control/Status Register 4 (SCSR4)
SCSR4 indicates the operating state and error state, selects the clock source, and controls the
prescaler division ratio.
SCSR4 can be read from or written to by the CPU at any time. 1 cannot be written to flags TDRE,
RDRF, ORER, and TEND. To clear these flags to 0, 1 should be read from them in advance.
Bit Bit Name
Initial
Value R/W Description
7 TDRE 1 R/(W)* Transmit Data Empty
Indicates that data is transferred from TDR4 to SR4
and the next serial transmit data can be written to
TDR4.
[Setting conditions]
• When the TE bit in SCR4 is 0
• When data is transferred from TDR4 to SR4 and
data can be written to TDR4
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When data is written to TDR4
6 RDRF 0 R/(W)*Receive Data Full
Indicates that the receive data is stored in RDR4.
[Setting condition]
• When serial reception ends normally and receive
data is transferred from SR4 to RDR4
[Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1
• When data is read from RDR4
Rev. 1.00, 07/04, page 339 of 570
Bit Bit Name
Initial
Value R/W Description
5 ORER 0 R/(W)*Overrun Error
Indicates that an overrun error occurs during reception
and then abnormal termination occurs. In transfer
mode, the output level of the SO4 pin is fixed to low
while this flag is set to 1. When the RE bit in SCR4 is
cleared to 0, the ORER flag is not affected and retains
its previous state. When RDR4 retains the receive data
it held before the overrun error occurred, and data
received after the error is lost. Reception cannot be
continued with the ORER flag set to 1, and
transmission cannot be continued either.
[Setting condition]
• When the next serial reception is completed while
RDRF = 1
[Clearing condition]
• When 0 is written to ORER after reading ORER = 1
4 TEND 0 R/(W)*Transmit End
Indicates that the TDRE flag has been set to 1 at
transmission of the last bit of transmit data.
[Setting condition]
• When TDRE = 1 at transmission of the last bit of
transmit data
[Clearing conditions]
• When 0 is written to TEND after reading TEND = 1
• When data is written to TDR4 with an instruction
3
2
1
0
CKS3
CKS2
CKS1
CKS0
1
0
0
0
R/W
R/W
R/W
R/W
Clock Source Select and Pin Function
Select the clock source to be supplied and set the
input/output for the SCK4 pin. The prescaler division
ratio and transfer clock cycle when an internal clock is
selected are shown in table 16.2. When an external
clock is selected, the external clock cycle should be at
least 4/φ.
Note: * Only 0 can be written to clear the flag.
Rev. 1.00, 07/04, page 340 of 570
Table 16.2 shows a prescaler division ratio and transfer clock cycle.
Table 16.2 Prescaler Division Ratio and Transf er Clock Cycle (Internal Clock)
Bit 3 Bit 2 Bit 1 Bit 0 Transfer Clock Cycle Function
CKS3
CKS2
CKS1
CKS0
Prescaler
Division
Ratio φ =
5 MHz φ =
2.5 MHz Clock
Resource Pin
Function
0 0 0 0 φ/1024 204.8 µs 409.6 µs Internal
clock
SCK4
output pin
0 0 0 1 φ/256 51.2 µs 102.4 µs Internal
clock
SCK4
output pin
0 0 1 0 φ/64 12.8 µs 25.6 µs Internal
clock
SCK4
output pin
0 0 1 1 φ/32 6.4 µs 12.8 µs Internal
clock
SCK4
output pin
0 1 0 0 φ/16 3.2 µs 6.4 µs Internal
clock
SCK4
output pin
0 1 0 1 φ/8 1.6 µs 3.2 µs Internal
clock
SCK4
output pin
0 1 1 0 φ/4 0.8 µs 1.6 µs Internal
clock
SCK4
output pin
0 1 1 1 φ/2 0.8 µs Internal
clock
SCK4
output pin
1 0 0 0 I/O port (initial value)
1 0 0 1 I/O port
1 0 1 0 I/O port
1 0 1 1 I/O port
1 1 0 0 I/O port
1 1 0 1 I/O port
1 1 1 0 I/O port
1 1 1 1 External
clock
SCK4 input
pin
Rev. 1.00, 07/04, page 341 of 570
16.3.3 Transmit Data Regi s ter 4 ( T DR 4)
TDR4 is an 8-bit register that stores data for serial transmission. When the SCI4 detects that SR4
is empty, it transfers the transmit data written in TDR4 to SR4 and starts serial transmission. If the
next transmit data is written to TDR4 while serial data in SR4 is being transmitted, continuous
serial transmission is possible. TDR4 can be read from or written to by the CPU at any time.
TDR4 is initialized to H'FF.
16.3.4 Receive Data Register 4 (RDR4)
RDR4 is an 8-bit register that stores receive data. When the SCI4 has received one byte of serial
data, it transfers the received serial data from SR4 to RDR4, where it is stored. Then receive
operation is completed. After this, SR4 is receive-enabled. RDR4 cannot be written to by the CPU.
RDR4 is initialized to H'00.
16.3.5 Shift Register 4 (SR4)
SR4 is a register that receives or transmits serial data. SR4 cannot be directly read from or written
to by the CPU.
Rev. 1.00, 07/04, page 342 of 570
16.4 Operation
The SCI4 is a serial communication interface that transmits and receives data in synchronization
with a clock pulse and is suitable for high-speed serial communication. The data transfer format is
fixed to 8-bit data. The internal clock or external clock can be selected as a clock source. An
overrun error during reception can be detected. The transmit and receive units are configured with
double buffering mechanism. Since the mechanism enables to write data during transmission and
to read data during reception, data is consecutively transmitted and received.
16.4.1 Clock
The eight internal clocks or an external clock can be selected as a transfer clock. When the
external clock is selected, the SCK4 pin is a clock input pin. When the internal clock is selected,
the SCK4 pin is a synchronous clock output pin. The synchronous clock is output eight pulses for
1-character transmission or reception. While neither transmission nor reception is being
performed, the signal is fixed high.
When the internal clock or external clock is not selected according to the combination of the
CKS3 to CKS0 bits in SCSR4, the SCK4 pin functions as an I/O port.
16.4.2 Data Transfer Format
Figure 16.2 shows the SCI4 transfer format.
SCK4
SO4/SI4 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Figure 16.2 Data Transfer Format
In clocked synchronous communication, data on the communication line is output from the falling
edge to the next falling edge of the synchronous clock. The data is guaranteed to be settled at the
rising edge of the synchronous clock. One character starts with the LSB and ends with the MSB.
After transmitting the MSB, the communication line retains the MSB level.
The SCI4 latches data at the rising edge of the synchronous clock on reception. The data transfer
format is fixed to 8-bit data. While transmission is stopped, the output level on the SO4 pin can be
changed by the SOL setting in SCR4.
Rev. 1.00, 07/04, page 343 of 570
16.4.3 Data Transmission/Reception
Before data transmission and reception, clear the TE and RE bits in SCR4 to 0 and then initialize
as the following procedure of figure 16.3.
Note: Before changing operating modes or communication format, the TE and RE bits must be
cleared to 0. Clearing the TE bit to 0 sets the TDRE flag to 1. Note that clearing the RE bit
to 0 does not affect the RDRF or ORER flag and the contents of RDR4.
When the external clock is used, the clock must not be supplied during operation including
initialization.
<Transmission/reception started>
Start of Initialization
Clear TE and RE bits in SCR4 to 0
Clear CKS3 to CKS0 bits in
SCSR4 to 0
Set TE and RE bits in SCR4 to 1.
Set RIE, TIE, and TEIE bits.
Figure 16.3 Flowchart E x ample of SCI4 Initialization
Rev. 1.00, 07/04, page 344 of 570
16.4.4 Data Transmission
Figure 16.4 shows an example flowchart of data transmission. Data transmission should be
performed as the following procedure after the SCI4 initialization.
Read TDRE in SCSR4
TDRE = 1?
Write transmit data in TDR4
TDRE bit cleared to 0 automatically
Data transferred from TDR4 to SR4
Start transmission by setting
TDRE bit to 1
Transmission will
continue?
Read TEND in SCSR4
TEND = 1?
TEI occurs (TEIE = 1)
Clear TE bit in SCR4 to 0
<Transmission completed> Note: Hatching area indicates SCI internal operation.
Yes
No
Yes
No
Yes
No
[1] Pin SO4 functions as output pin for transmit
data
[2] After reading SCSR4 and confirming TDRE
= 1, write transmit data in TDR4. Writing data
in TDR4 clears the TDRE bit to 0 automati-
cally. At this time, the clock is output to start
data transmission.
[3] To consecutively transmit data, read TDRE
= 1 to confirm that TDR4 is ready. After that,
write data in TDR4. Writing data in TDR4
clears the TDRE bit to 0 automatically.
[1]
[2]
[3]
Initialization
Start transmission (TE = 1)
Figure 16.4 Flowchar t Ex ampl e of Da ta Trans m i ssi on
Rev. 1.00, 07/04, page 345 of 570
During transmission, the SCI4 operates as shown below.
1. The SCI4 sets the TE bit to 1 and clears the TDRE flag to 0 when transmit data is written to in
TDR4 to transmit data from TDR4 to SR4. After that, the SCI4 sets the TDRE flag to 1 to start
transmission. At this time, when the TIE bit in SCR4 is set to 1, a TXI is generated.
2. In clock output mode, the SCI4 outputs eight pulses of the synchronous clock. When the
external clock is selected, the SCI4 outputs data in synchronization with the input clock.
3. Serial data is output from the LSB (bit 0) to MSB (bit 7) on pin SO4. The SCI4 checks the
TDRE flag at the timing of outputting the MSB (bit 7).
4. When TDRE = 0, data in TDR4 is transmitted to SR4 and then the data of the next frame starts
to be transmitted. When TDRE = 1, the SCI4 sets the TEND bit to 1 and holds the output level
after transmitting the MSB (bit 7). At this time, when the TEIE bit in SCR4 is set to 1, a TEI is
generated.
5. After the transmission, the output level on pin SCK4 is fixed high.
Note: Transmission cannot be performed when the error flag (ORER) which indicates the data
reception status is set to 1. Before transmission, confirm that the ORER flag is cleared to
0.
Figure 16.5 shows the example of transmission operation.
Synchronous clock
Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
TDRE
TEND
LSI operation
User operation
TXI
generated
TDRE
cleared
TEI
generated
TXI
generated
1 frame
Data written
to TDR4
1 frame
Figure 16.5 Transmit Operati on Exam p l e
Rev. 1.00, 07/04, page 346 of 570
16.4.5 Data Reception
Figure 16.6 shows an example flowchart of data reception. Data reception should be performed as
the following procedure after the SCI4 initialization.
Read ORER in SCSR4
ORER = 1?
Read received data in RDR4
RDRF = 1?
Read RDRF in SCSR4
Data transfer will
continue?
Clear RE bit in SCR4 to 0
Note: Hatching area indicates SCI internal operation.
No
Yes
No
Yes
Yes
No
[1] Pin SI4 functions as input pin for receive
data
[2][3] When a reception error occurs, read the ORER
flag in SCSR4 and then clears the ORER flag
to 0 after executing the error processing. When
the ORER flag is set to 1, both transmission
and reception cannot be restarted.
[4] After reading SCSR4 and confirming RDRF = 1,
read the receive data in RDR4. The RDRF flag
is automatically cleared to 0. Changes in the
RDRF flag from 0 to 1 can be notified by an RXI
interrupt.
[5] To consecutively receive data, reading the RDRF
flag and RDR4 must be completed before
receiving the MSB (bit 7) of the current frame.
[1]
[2]
[5]
Initialization
Start reception (RE = 1)
RDRF cleared to 0 automatically
<Reception completed>
Clear ORER flag in SCSR4 to 0
Error processing
Overrun error processing
<Completed>
Error
processing
(Shown below)
[4]
[3]
[3]
Figure 16.6 Flowchart Example of Data Reception
Rev. 1.00, 07/04, page 347 of 570
During reception, the SCI4 operates as shown below.
1. The SCI4 initialization is performed in synchronization with the synchronous clock input or
output and starts reception.
2. The SCI4 stores received data from the LSB to MSB of SR4.
3. After reception, the SCI4 checks that RDRF = 0 and whether receive data is ready for being
transferred from SR4 to RDR4.
4. When confirms that an overrun error has not occurred, the RDRF bit is set to 1 and the
received data is stored in RDR4. At this time, when the RIE bit in SCR4 is set to 1, an RXI is
generated. When an overrun error is detected by checking, the ORER flag is set to 1. The
RDRF bit retains the previously set value. If the RIE bit in SCR4 is set to 1, an ERI is
generated.
5. An overrun error is detected when the next data reception is completed with the RDRF bit in
SCSR4 set to 1. The received data is not transferred from SR4 to RDR4.
Note: Reception cannot be performed when the error flag is set to 1. Before reception, confirm
that the ORER and RDRF flags are cleared to 0.
Figure 16.7 shows an operation example of reception.
LSI operation
User operation
RXI
generated
RDRF
cleared
ERI generated
by overrun error
RXI
generated
Data read
from RDR4
RDR4 has not
been read from
(RDRF = 1)
Overrun error
processing
Synchronous clock
Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
RDRF
ORER
1 frame 1 frame
Figure 16.7 Receive Operation Example
Rev. 1.00, 07/04, page 348 of 570
16.4.6 Simultaneous Data Transmission and Reception
Figure 16.8 shows an example flowchart of simultaneous data transmission and reception.
Simultaneous data transmission and reception should be performed as the following procedure
after the SCI4 initialization.
Read TDRE in SCSR4
TDRE = 1?
Write transmit data in TDR4
TDRE bit cleared to 0 automatically
Data transferred from TDR4 to SR4
Start transmission/reception
by setting TDRE bit to 1
ORER = 1?
Read RDRF in SCSR4
RDRF = 1?
Clear TE and RE bits in SCR4 to 0
<Transmission and reception completed>
Note: Hatching area indicates SCI internal operation.
Yes
No
Yes
No
Yes
No
[1] Pin SO4 functions as output pin for transmit
data and pin SI4 functions as input pin for
receive data. Simultaneous transmission and
reception is enabled.
[2] After reading SCSR4 and confirming TDRE
= 1, write transmit data in TDR4. Writing data
in TDR4 clears the TDRE bit to 0 automati-
cally. At this time, the clock is output to start
data transfer.
[3] When a reception error occurs, read the ORER
flag in SCSR4 and then clear the ORER flag
to 0 after executing the error processing. When
the ORER flag is set to 1, both transmission
and reception cannot be restarted.
[4] After reading SCSR4 and confirming RDRF = 1,
read receive data in RDR4 and clear the RDRF
flag to 0. An RXI interrupt can also be used to
confirm that the RDRF flag value has been changed
from 0 to 1.
[5] To consecutively transmit and receive data, the
following operation must be completed: reading
the RDRF flag and reading RDR4 before receiving
the MSB (bit 7) of the current frame: confirming
that TDR4 is ready for writing by reading TDRE
= 1 before transmitting the MSB (bit 7) and writing
data to TDR4 to clear the TDRE flag to 0.
[1]
[2]
Initialization
Start transmission (TE = 1, RE = 1)
Read received data in RDR4
Data transfer will
continue?
Yes
No
RDRF cleared to 0 automatically
Error
processing [3]
Read ORER in SCSR4
[4]
[5]
Figure 16.8 Flowchart Example of Simultaneous Transmission and Reception
Rev. 1.00, 07/04, page 349 of 570
Notes: 1. When switching from transmission to simultaneous data transmission and reception,
confirm that the SCI4 completes transmission and both the TDRE and TEND bits are
set to 1. After that, clear the TE bit to 0 and then set both the TE and RE bits to 1.
2. When switching from reception to simultaneous data transmission and reception,
confirm that the SCI4 completes reception and both the RDRF and ORER flags are
cleared to 0 after clearing the RE bit to 0. After that, set both the TE and RE bits to 1.
16.5 Interrupt Sources
The SCI4 has four interrupt sources: transmit end, transmit data empty, receive data full, and
receive error (overrun error).
Table 16.3 lists the descriptions of the interrupt sources.
Table 16.3 SCI4 Interrupt Sources
Abbreviation Condition Interrupt Source
RXI RIE = 1 Receive data full (RDRF)
TXI TIE = 1 Transmit data empty (TDRE)
TEI TEIE = 1 Transmit end (TEND)
ERI RIE = 1 Receive error (ORER)
The interrupt requests can be enabled/disabled by the TIE and RIE bits in SCR4.
When the TDRE flag in SCSR4 is set to 1, a TXI is generated. When the TEND bit in SCSR4 is
set to 1, a TEI is generated. These two interrupt requests are generated during transmission.
The TDRE flag in SCSR4 is initialized to 1. Therefore, if a TXI request is enabled by setting the
TIE bit in SCR4 to 1 before transmit data is transferred to TDR4, a TXI is generated even when
transmit data is not ready.
If transmit data is transferred to TDR4 in the interrupt handling routine, these interrupt requests
can be effectively used.
To avoid the occurrence of the interrupt requests (TXI and TEI), clear the corresponding interrupt
enable bits (TIE and TEIE) to 0 after transmit data is transferred to TDR4.
When the RDRF bit in SCSR4 is set to 1, an RXI is generated. When the ORER flag is set to 1, an
ERI is generated. These two interrupt requests are generated during reception.
Rev. 1.00, 07/04, page 350 of 570
16.6 Usage Notes
When using the SCI4, keep in mind the following.
16.6.1 Relationship between Writing to TDR4 and TDRE
The TDRE flag in SCSR4 is a status flag that indicates that data to be transmitted has not been
stored in TDR4. When writing data to TDR4, the TDRE flag is automatically cleared to 0. The
TDRE flag is set to 1 when the SCI4 transfers data from TDR4 to SR4.
Data is written to TDR4 regardless of the TDRE flag value. However, if data is written to TDR4
with TDRE = 0, the previous data is lost unless the previous data has been transferred to SR4.
Accordingly, to ensure transmission, writing transmit data to TDR4 must be performed once after
confirming that the TDRE flag has been set to 1. (Do not write more than once.)
16.6.2 Receive Error Flag and Transmission
While the receive error flag (ORER) is set to 1, transmission cannot be started even if the TDRE
flag is cleared to 0. To start transmission, the ORER flag must be cleared to 0.
Note that the ORER flag cannot be cleared to 0 even if the RE bit is cleared to 0.
16.6.3 Relationship between Reading RDR 4 and RDR F
The SCI4 always checks the RDRF flag status during reception. When the RDRF flag is cleared to
0 at the end of a frame, the reception is completed without error. When the RDRF flag is set to 1,
it indicates that an overrun has occurred.
Since reading RDR4 clears the RDRF flag to 0 automatically, if RDR4 is read twice or more, the
data is read with the RDRF flag cleared to 0. In this case, when the timing of the read operation
matches that of the data reception of the next frame, the read data may be the next frame data.
Figure 16.9 shows this operation.
Rev. 1.00, 07/04, page 351 of 570
Number of transfer
RDRF
Data 1 Data 2 Data 3
Frame 1 Frame 2 Frame 3
(A)
RDR4
(B)
RDR4 read
At the timing of (A), data 1 is read.
At the timing of (B), data 2 is read.
Data 1 Data 2
RDR4 read
Figure 16.9 Relationshi p bet ween Reading RDR4 and RDR F
In this case, RDR4 must be read only once after confirming RDRF = 1. If reading RDR4 twice or
more, store the read data in the RAM, and use the stored data. In addition, there should be a
margin from the timing of reading RDR4 to completion of the next frame reception. (Reading
RDR4 should be completed before the bit 7 transfer.)
16.6.4 SCK4 Output Waveform when Internal Clock of φ/2 is Selected
When the internal clock of φ/2 is selected by the CKS3 to CKS0 bits in SCSR4 and continuous
transmission or reception is performed, one pulse of high period is lengthened after eight pulses of
the clock has been output as shown in figure 16.10.
SO4/SI4 Bit0 Bit1 Bit2 Bit0 Bit1 Bit2Bit3 Bit4 Bit5 Bit6 Bit7
SCK4
Figure 16.10 Transfer Format when Internal Clock of φ/2 is Selected
Rev. 1.00, 07/04, page 352 of 570
Rev. 1.00, 07/04, page 353 of 570
Section 17 14-Bit PWM
This LSI has an on-chip 14-bit pulse width modulator (PWM) with two channels. Connecting the
PWM to the low-pass filter enables the PWM to be used as a D/A converter. The standard PWM
or pulse-division type PWM can be selected by software. Figure 17.1 shows a block diagram of
the 14-bit PWM.
17.1 Features
• Choice of four conversion periods
A conversion period of 131,072/φ with a minimum modulation width of 8/φ, a conversion
period of 65,536/φ with a minimum modulation width of 4/φ, a conversion period of 32,768/φ
with a minimum modulation width of 2/φ, or a conversion period of 16,384/φ with a minimum
modulation width of 1/φ, can be selected.
• Pulse division method for less ripple
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (For details, refer to section 6.4, Module Standby Function.)
• The standard PWM or pulse-division type PWM can be selected by software.
φ/2
φ/4
φ/8
φ/16
PWM
PWM waveform
generator
Pulse-division type waveform
[Legend]
PWDR:
PWCR:
PWM data register
PWM control register
Standard waveform
Internal data bus
PWDR
Asynchronous event counter
PWCR
PWM waveform
generator
Figure 17.1 Block Diagram of 14-Bit PWM
Rev. 1.00, 07/04, page 354 of 570
17.2 Input/Output Pins
Table 17.1 shows the 14-bit PWM pin configuration.
Table 17.1 Pin Configuration
Name Abbreviation I/O Function
PWM1 output pin PWM1 Output Standard PWM/pulse-division type
PWM waveform output (PWM1)
PWM2 output pin PWM2 Output Standard PWM/pulse-division type
PWM waveform output (PWM2)
17.3 Register Descriptions
The 14-bit PWM has the following registers.
• PWM1 control register (PWCR1)
• PWM1 data register (PWDR1)
• PWM2 control register (PWCR2)
• PWM2 data register (PWDR2)
Rev. 1.00, 07/04, page 355 of 570
17.3.1 PWM Control Register (PWCR)
PWCR selects the input clocks and selects whether the standard PWM or pulse-division type
PWM is used.
Bit Bit Name
Initial
Value R/W Description
7 to 3 All 1 Reserved
These bits are always read as 1 and cannot be
modified.
2 PWCRm2 0 W PWM Output Waveform Select
Selects whether the standard PWM waveform or pulse-
division type PWM waveform is output.
0: Pulse-division type PWM waveform is output
1: Standard PWM waveform is output
1
0
PWCRm1
PWCRm0
0
0
W
W
Clock Select 1 and 0
Select the clock supplied to the 14-bit PWM. These bits
are write-only bits and always read as 1.
00: The input clock is φ/2 (tφ* = 2/φ)
A conversion period is 16,384/φ, with a
minimum modulation width of 1/φ
01: The input clock is φ/4 (tφ* = 4/φ)
A conversion period is 32,768/φ, with a
minimum modulation width of 2/φ
10: The input clock is φ/8 (tφ* = 8/φ)
A conversion period is 65,536/φ, with a
minimum modulation width of 4/φ
11: The input clock is φ/16 (tφ* = 16/φ)
A conversion period is 131,072/φ, with a
minimum modulation width of 8/φ
Note: * tφ: Period of PWM clock input
m = 2 or 1
17.3.2 PWM Data Register (PWDR)
PWDR is a 14-bit write-only register. PWDR indicates high level width in one PWM waveform
cycle when the pulse-division type PWM is selected.
When 14-bit data is written to PWDR, the contents are latched in the PWM waveform generator
and the PWM waveform generation data is updated.
PWDR is initialized to H'C000.
Rev. 1.00, 07/04, page 356 of 570
17.4 Operation
17.4.1 Setting for Pulse-Division Type PWM Operation
When using the pulse-division type PWM, set the registers in this sequence:
1. Set the PWM1 or PWM2 bit in PMR9 (according to the PWM channel used) to 1 to set the
P90/PWM1 or P91/PWM2 pin to function as a PWM pin.
2. Set PWCR to select a conversion period of 131,072/φ (PWCR1 = 1, PWCR0 = 1), 65,536/φ
(PWCR1 = 1, PWCR0 = 0), 32,768/φ (PWCR1 = 1, PWCR0 = 1), or 16,384/φ (PWCR1 = 0,
PWCR0 = 0).
3. Set the output waveform data in PWDR. When the data is written to PWDR, the contents are
latched in the PWM waveform generator, and the PWM waveform generation data is updated
in synchronization with internal signals.
One conversion period consists of 64 pulses, as shown in figure 17.2. The total high-level width
during this period (TH) corresponds to the data in PWDR. This relation can be expressed as
follows:
TH = (data value in PWDR + 64) × tφ/2
where tφ is the period of PWM clock input: 2/φ (PWCR = H'0), 4/φ (PWCR = H'1), 8/φ (PWCR =
H'2), or 16/φ (PWCR = H'3).
Example: To set one conversion period to 32,768 µs, set as follows.
When PWCRm1 and PWCRm0 are cleared to 0, one conversion period is 16,384/φ. Therefore
φ becomes 0.5 MHz. At this time, tfn is 512 µs and 1/φ (accuracy) is 2.0 µs.
When PWCRm1 is cleared to 0 and PWCRm0 is set to 1, one conversion period is 32,768/φ.
Therefore φ becomes 1 MHz. At this time, tfn is 512 µs and 2/φ (accuracy) is 2.0 µs.
When PWCRm1 is set to 1 and PWCRm0 is cleared to 0, one conversion period is 65,536/φ.
Therefore φ becomes 2 MHz. At this time, tfn is 512 µs and 4/φ (accuracy) is 2.0 µs.
Therefore, to set one conversion period to 32,768 µs, the system clock (φ) should be 0.5 MHz, 1
MHz, or 2 MHz.
Note: m = 2 or 1
Rev. 1.00, 07/04, page 357 of 570
tf1
tH1
TH =
tH1 + tH2 + tH3 + . . . tH64
tf1 + tf2 + tf3 . . . = tH64
tf2 tf63
One conversion period
tf64
tH2 tH3 tH63 tH64
Figure 17.2 Waveform Output by PWM
17.4.2 Setting for Standard PWM O peration
When using the standard PWM, set the registers in this sequence:
1. Set the PWM1 or PWM2 bit in PMR9 (according to the PWM channel used) to 1 to set the
P90/PWM1 or P91/PWM2 pin to function as a PWM pin.
2. Set PWCRm2 to 1 to select the standard PWM waveform. (m = 2 or 1)
3. Set the event counter PWM in the asynchronous event counter. For the setting method, see
description of the event counter PWM operation in the asynchronous event counter.
4. The PWM pin outputs the PWM waveform set by the event counter.
Note: When the standard waveform is used, 16-bit counter operation, 8-bit counter operation,
and IRQAEC operation for the asynchronous event counter are not available because the
PWM for the asynchronous event counter is used.
When the IECPWM signal of the asynchronous event counter goes high, ECH and ECL
increment. However, when the signal goes low, these counters stop. (For details, refer to
section 13.4, Operation.)
17.4.3 PWM Operating States
The PWM operating states are shown in table 17.2.
Table 17.2 PWM Operating States
Operating
Mode
Reset
Active
Sleep
Watch
Subactive
Subsleep
Standby Module
Standby
PWCRm Reset Functions Functions Retained Retained Retained Retained Retained
PWDRm Reset Functions Functions Retained Retained Retained Retained Retained
(m = 2 or 1)
Rev. 1.00, 07/04, page 358 of 570
ADCMS3AA_000020020900 Rev. 1.00, 07/04, page 359 of 570
Section 18 A/D Converter
This LSI includes a successive approximation type 10-bit A/D converter that allows up to three
analog input channels to be selected. The block diagram of the A/D converter is shown in figure
18.1.
18.1 Features
• 10-bit resolution
• Input channels: Three channels
• High-speed conversion: 12.4 µs per channel (at 5-MHz operation)
• Sample and hold function
• Conversion start method
A/D conversion can be started by software and external trigger.
• Interrupt source
An A/D conversion end interrupt request can be generated.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (For details, refer to section 6.4, Module Standby Function.)
Rev. 1.00, 07/04, page 360 of 570
Multiplexer
Internal data bus
Reference
voltage
+
-
Comparator
AV
CC
AV
SS
Control logic
ADSR
AMR
ADRR
IRRAD
AN0
AN1
AN2
ADTRG
AVCC
[Legend]
AMR:
ADSR:
ADRR:
IRRAD:
A/D mode register
A/D start register
A/D result register
A/D conversion end interrupt request flag
AVSS
Figure 18.1 Block Diagram of A/D Converter
Rev. 1.00, 07/04, page 361 of 570
18.2 Input/Output Pins
Table 18.1 shows the input pins used by the A/D converter.
Table 18.1 Pin Configuration
Pin Name Abbreviation I/O Function
Analog power supply pin AVcc Input Power supply and reference voltage of
analog part
Analog ground pin AVss Input Ground and reference voltage of analog
part
Analog input pin 0 AN0 Input
Analog input pin 1 AN1 Input
Analog input pin 2 AN2 Input
Analog input pins
External trigger input pin ADTRG Input External trigger input that controls the
A/D conversion start.
18.3 Register Descriptions
The A/D converter has the following registers.
• A/D result register (ADRR)
• A/D mode register (AMR)
• A/D start register (ADSR)
18.3.1 A/D Result Register (ADRR)
ADRR is a 16-bit read-only register that stores the results of A/D conversion. The upper 10 bits of
the data are stored in ADRR. ADRR can be read by the CPU at any time, but the ADRR value
during A/D conversion is undefined. After A/D conversion is completed, the conversion result is
stored as 10-bit data, and this data is retained until the next conversion operation starts. The initial
value of ADRR is undefined.
Rev. 1.00, 07/04, page 362 of 570
18.3.2 A/D Mode Register (AM R)
AMR sets the A/D conversion time, and selects the external trigger and analog input pins.
Bit Bit Name
Initial
Value R/W Description
7 CKS 0 R/W Clock Select
Sets the A/D conversion time.
0: Conversion time = 62 states
1: Conversion time = 31 states
6 TRGE 0 R/W External Trigger Select
Enables or disables the A/D conversion start by the
external trigger input.
0: Disables the A/D conversion start by the external
trigger input.
1: Starts A/D conversion at the rising or falling edge of
the ADTRG pin
The edge of the ADTRG pin is selected by the
ADTRGNEG bit in IEGR.
5
4
1
1
Reserved
These bits are always read as 1 and cannot be
modified.
3
2
1
0
CH3
CH2
CH1
CH0
0
0
0
0
R/W
R/W
R/W
R/W
Channel Select 3 to 0
Select the analog input channel.
00xx: No channel selected
0100: AN0
0101: AN1
0110: AN2
0111: Using prohibited
1xxx: Using prohibited
The channel selection should be made while the ADSF
bit is cleared to 0.
[Legend] x: Don't care.
Rev. 1.00, 07/04, page 363 of 570
18.3.3 A/D Start Register (ADSR)
ADSR starts and stops the A/D conversion.
Bit Bit Name
Initial
Value R/W Description
7 ADSF 0 R/W When this bit is set to 1, A/D conversion is started.
When conversion is completed, the converted data is
set in ADRR and at the same time this bit is cleared to
0. If this bit is written to 0, A/D conversion can be
forcibly terminated.
6 to 0 All 1 Reserved
These bits are always read as 1 and cannot be
modified.
18.4 Operation
The A/D converter operates by successive approximation with 10-bit resolution. When changing
the conversion time or analog input channel, in order to prevent incorrect operation, first clear the
bit ADSF to 0 in ADSR.
18.4.1 A/D Conversion
1. A/D conversion is started from the selected channel when the ADSF bit in ADSR is set to 1,
according to software.
2. When A/D conversion is completed, the result is transferred to the A/D result register.
3. On completion of conversion, the IRRAD flag in IRR2 is set to 1. If the IENAD bit in IENR2
is set to 1 at this time, an A/D conversion end interrupt request is generated.
4. The ADSF bit remains set to 1 during A/D conversion. When A/D conversion ends, the
ADSF bit is automatically cleared to 0 and the A/D converter enters the wait state.
Rev. 1.00, 07/04, page 364 of 570
18.4.2 External Trigger Input Timing
The A/D converter can also start A/D conversion by input of an external trigger signal. External
trigger input is enabled at the ADTRG pin when the ADTSTCHG bit in PMRB is set to 1* and
TRGE bit in AMR is set to 1. Then when the input signal edge designated in the ADTRGNEG bit
in IEGR is detected at the ADTRG pin, the ADSF bit in ADSR will be set to 1, starting A/D
conversion.
Figure 18.2 shows the timing.
Note: * The ADTRG input pin is shared with the TEST pin. Therefore when the pin is used as
the ADTRG pin, reset should be cleared while the 0-fixed or 1-fixed signal is input to
the TEST pin. Then the ADTSTCHG bit should be set to 1 after the TEST signal is
fixed.
φ
ADTRG
(when
ADTRGNEG = 0)
ADSF A/D conversion
Figure 18.2 External Trigger Input Timing
18.4.3 Operating States of A/D Converter
Table 18.2 shows the operating states of the A/D converter.
Table 18.2 Operating States of A/D Converter
Operating
Mode
Reset
Active
Sleep
Watch Sub-
active Sub-
sleep
Standby Module
Standby
AMR Reset Functions Functions Retained Retained Retained Retained Retained
ADSR Reset Functions Functions Retained Retained Retained Retained Retained
ADRR Retained* Functions Functions Retained Retained Retained Retained Retained
Note: * Undefined at a power-on reset.
Rev. 1.00, 07/04, page 365 of 570
18.5 Example of Use
An example of how the A/D converter can be used is given below, using channel 1 (pin AN1) as
the analog input channel. Figure 18.3 shows the operation timing.
1. Bits CH3 to CH0 in the A/D mode register (AMR) are set to 0101, making pin AN1 the
analog input channel. A/D interrupts are enabled by setting bit IENAD to 1, and A/D
conversion is started by setting bit ADSF to 1.
2. When A/D conversion is completed, bit IRRAD is set to 1, and the A/D conversion result is
stored in ADRR. At the same time bit ADSF is cleared to 0, and the A/D converter goes to the
idle state.
3. Bit IENAD = 1, so an A/D conversion end interrupt is requested.
4. The A/D interrupt handling routine starts.
5. The A/D conversion result is read and processed.
6. The A/D interrupt handling routine ends.
If bit ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place.
Figures 18.4 and 18.5 show flowcharts of procedures for using the A/D converter.
Rev. 1.00, 07/04, page 366 of 570
Interrupt (IRRAD)
IENAD
ADSF
ADRR
Channel 1 (AN1)
operating state
Note: * indicates instruction execution by software.
Set*
Set*
A/D conversion starts
Idle Idle Idle
A/D conversion (1) A/D conversion (2)
Set*
A/D conversion result (1)
Read conversion result
A/D conversion result (2)
↓
↓
Read conversion result
↓
Figure 18.3 Example of A/D Co nver si on Operation
Rev. 1.00, 07/04, page 367 of 570
Start
Set A/D conversion speed and input channel
Disable A/D conversion end interrupt
Start A/D conversion
Perform A/D conversion?
End
Read ADSR
ADSF = 0?
Read ADRR data
Yes
Yes
No
No
Figure 18.4 Flowchart of Proced ure for Using A/D Converter (Polling by Software)
Set A/D conversion speed and input channel
Start
Enable A/D conversion end interrupt
Start A/D conversion
Clear IRRAD bit in IRR2 to 0
Read ADRR data
A/D conversion end
interrupt generated?
Perform A/D conversion?
End
No
No
Yes
Yes
Figure 18.5 Flowchart of Proced ure for Using A/D Converter (Interrupts Used)
Rev. 1.00, 07/04, page 368 of 570
18.6 A/D Conversion Accuracy Definitions
This LSI's A/D conversion accuracy definitions are given below.
• Resolution
The number of A/D converter digital output codes
• Quantization error
The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 18.6).
• Offset error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from the minimum voltage value 0000000000 to 0000000001
(see figure 18.7).
• Full-scale error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from 1111111110 to 1111111111 (see figure 18.7).
• Nonlinearity error
The error with respect to the ideal A/D conversion characteristics between zero voltage and
full-scale voltage. Does not include offset error, full-scale error, or quantization error.
• Absolute accuracy
The deviation between the digital value and the analog input value. Includes offset error, full-
scale error, quantization error, and nonlinearity error.
111
110
101
100
011
010
001
000
1
8
2
8
6
8
7
8
FS
Quantization error
Digital output
Ideal A/D conversion
characteristic
Analog
input voltage
3
8
4
8
5
8
Figure 18.6 A/D Conversion Accuracy Definitions (1)
Rev. 1.00, 07/04, page 369 of 570
FS
Digital output
Ideal A/D conversion
characterist
Nonlinearity
error
Analog
input voltage
Offset error
Actual A/D conversion
characteristic
Full-scale error
Figure 18.7 A/D Conversion Accuracy Definitions (2)
18.7 Usage Notes
18.7.1 Permissible Signal Source Impedance
This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal
for which the signal source impedance is 10 kΩ or less. This specification is provided to enable
the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling
time; if the sensor output impedance exceeds 10 kΩ, charging may be insufficient and it may not
be possible to guarantee A/D conversion accuracy. However, with a large capacitance provided
externally, the input load will essentially comprise only the internal input resistance of 10 kΩ, and
the signal source impedance is ignored. However, as a low-pass filter effect is obtained in this
case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5
mV/µs or greater) (see figure 18.8). When converting a high-speed analog signal, a low-
impedance buffer should be inserted.
Rev. 1.00, 07/04, page 370 of 570
18.7.2 Influences on Absolute Accuracy
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely
affect absolute accuracy. Be sure to make the connection to an electrically stable GND.
Care is also required to ensure that filter circuits do not interfere with digital signals or act as
antennas on the mounting board.
48 pF
10 kΩ
C
in
=
15 pF
Sensor output
impedance
up to 10 kΩ
This LSI
Low-pass
filter C
up to 0.1 µF
Sensor input
A/D converter
equivalent circuit
Figure 18.8 Example of Analog Input Circuit
18.7.3 Usage Notes
1. ADRR should be read only when the ADSF bit in ADSR is cleared to 0.
2. Changing the digital input signal at an adjacent pin during A/D conversion may adversely
affect conversion accuracy.
3. When A/D conversion is started after clearing module standby mode, wait for 10φ clock
cycles before starting A/D conversion.
4. In active mode and sleep mode, the analog power supply current flows in the ladder resistance
even when the A/D converter is on standby. Therefore, if the A/D converter is not used, it is
recommended that AVcc be connected to the system power supply and the ADCKSTP bit be
cleared to 0 in CKSTPR1.
ADCMS3AA_000020040600 Rev. 1.00, 07/04, page 371 of 570
Section 19 ∆Σ A/D Converter
This LSI includes a ∆Σ modulation (Σ∆ modulation or SDM) type 14-bit ∆Σ A/D converter that
allows up to two analog input channels to be selected. Note that the ∆Σ A/D converter is not
available for the audio equipment. The block diagram of the ∆Σ A/D converter is shown in figure
19.1.
19.1 Features
• 14-bit resolution
• Two input channels
• Conversion method: Secondary ∆Σ and 320-times oversampling type
• Conversion time: 200 µs per channel (at 1.6 MHz operation)
• Interrupt source
An A/D conversion end interrupt request can be generated.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (For details, refer to section 6.4, Module Standby Function.)
Rev. 1.00, 07/04, page 372 of 570
PGA
ADCR
Internal data bus
PSS
Multiplexer
IRRSDADCN
fovs = φ
fovs = φ/2, φ/4, φ/8, φ/16, φ/32
Secondary ∆Σ
A/D converter
LCD drive power supply circuit
Reference voltage
generator
[Legend]
ADCR:
ADSSR:
IRRSDADCN:
ADDR:
BGRMR:
A/D control register
A/D start/status register
A/D conversion end interrupt request flag
A/D data register
BGA control register
Band-gap
reference circuit
Clock interrupt
control circuit
Dout (16 bits;
14 bits are valid)
Programmable gain amplifier
System clock (φ)
ADSSR
LCD
ADDR (16 bits)
Ain1
Ain2
Vref/REF
ACOM
Buffer
BGRMR
Figure 19.1 Block Diagram of ∆Σ A/D Converter
Rev. 1.00, 07/04, page 373 of 570
19.2 Input/Output Pins
Table 19.1 shows the pins used by the ∆Σ A/D converter.
Table 19.1 Pin Configuration
Pin Name Abbreviation I/O Function
Reference voltage pin Vref Input External reference voltage input
Internal reference
voltage output pin
REF Output Internal reference voltage output
Analog voltage
stabilization pin
ACOM Output Stabilization capacitance connection
(for 0.1µF capacitor connection)
Analog input pin 1 Ain1 Input
Analog input pin 2 Ain2 Input
Analog input pins
Analog power supply
pin for the ∆Σ A/D
converter
DVcc Input Power supply pin
19.3 Register Descriptions
The ∆Σ A/D converter has the following registers.
• A/D data register (ADDR)
• BGR control register (BGRMR)
• A/D control register (ADCR)
• A/D start/status register (ADSSR)
19.3.1 A/D Data Regi ster (A DDR)
ADDR is a 16-bit read-only register that stores the results of A/D conversion. ADDR can be read
by the CPU at any time, but the ADDR value during A/D conversion is undefined. After A/D
conversion is completed, 14-bit data of the conversion result is stored in upper 14 bits in ADDR,
and this data is retained until the next conversion operation starts. The initial value of ADDR is
undefined.
Rev. 1.00, 07/04, page 374 of 570
19.3.2 BGR Control Register (BGRMR)
BGRMR controls operation of the band-gap reference circuit (BGR) and adjusts the internal
reference voltage output from the REF pin (BGR output voltage).
Bit Bit Name Initial Value R/W Description
7 BGRSTPN* 0 R/W Band-Gap Reference Circuit Control
Sets operation or stop of the band-gap reference circuit.
0: Band-gap reference circuit stops
1: Band-gap reference circuit operates
6 to
3
All 1 Reserved
These bits are always read as 1 and cannot be modified.
2
1
0
BTRM2
BTRM1
BTRM0
0
0
0
R/W
R/W
R/W
BGR Output Voltage Trimming
Adjust approximately 1.2-V BGR output voltage.
000: ±0 V
001: +0.14 V
010: +0.09 V
011: +0.04 V
100: −0.04 V
101: −0.09 V
110: −0.14 V
111: −0.18 V
Note: * When the BGRSTPN bit is 0 (when the band-gap reference circuit is halted), the 3-V
constant-voltage power supply circuit of the LCD is halted.
The time from the point at which the BGRSTPN bit is set to 1 until the BGR output
voltage is stabilized to approximately 1.2 V is approximately 10 µs.
Rev. 1.00, 07/04, page 375 of 570
19.3.3 A/D Control Register (ADCR)
ADCR sets the conversion mode, PGA multiplication ratio, and reference voltage, and selects the
analog input channel and oversampling frequency.
Bit Bit Name Initial Value R/W Description
7 MOD 0 R/W Conversion Mode Select
Sets the conversion mode. When the MOD bit is set to 1,
A/D conversion is executed regardless of the ADS bit in
ADSSR.
0: Wait mode
1: Continuous mode
6
5
4
OVS2
OVS1
OVS0
0
0
0
R/W
R/W
R/W
Oversampling Frequency Select
Select the oversampling frequency.
000: φ
001: φ/2
010: φ/4
011: φ/8
100: φ/16
101: φ/32
11x: Setting prohibited
Rev. 1.00, 07/04, page 376 of 570
Bit Bit Name Initial Value R/W Description
3
2
VREF1
VREF0
0
0
R/W
R/W
PB5/Vref/REF Pin Function Switch and Reference Voltage
Select
These bits specify whether the PB5/Vref/REF pin functions
as a PB5 pin, Vref pin, or REF pin. In addition, these bits
select the external reference voltage (Vref) or internal
reference voltage (REF) as the reference voltage of the ∆Σ
A/D converter. When the REF is to be selected, set these
bits after the BGRSTPN bit in BGRMR has been set to 1 to
operate the BGR.
00: Functions as a PB5 input pin
01: Functions as a Vref input pin, and the external
reference voltage (Vref) is input to the reference
generator
10: Functions as a REF output pin
11: Functions as a REF output pin, and the internal
reference voltage (REF) is input to the reference
generator
When these bits are set to B'11, the REF voltage is input to
the reference voltage generator in the ∆Σ A/D converter at
the same timing as the internal reference voltage (REF) is
output from the REF pin. To operate the ∆Σ A/D converter
with the internal reference voltage (REF), set these bits to
B'11.
1
0
PGA1
PGA0
0
0
R/W
R/W
PGA Gain Select
Set the analog input voltage multiplication ratio ranging
from 1/3 times to 4 times.
00: 1 time
01: 2 times
10: 4 times
11: 1/3 times
[Legend] x: Don’t care.
Rev. 1.00, 07/04, page 377 of 570
19.3.4 A/D Start/Stat us Regi ster (ADSSR)
ADSSR consists of the A/D conversion status flag, analog input channel select bit, and bypass
select bit.
Bit Bit Name Initial Value R/W Description
7 ADS 0 R/W A/D Start
When this bit is set to 1 in wait mode (the MOD bit in
ADCR is cleared to 0), A/D conversion is started.
6 ADST 0 R A/D Status Flag
When this bit is read in wait mode (the MOD bit in ADCR is
cleared to 0), A/D conversion status can be identified.
0: In the idle state
1: During A/D conversion
5
4
AIN1
AIN0
0
0
R/W
R/W
Analog Input Channel Select
Select the analog input channel.
00: Not selected
01: Ain1
10: Ain2
11: Not selected
3 BYPGA 0 R/W PGA Bypass Select
Selects whether the analog input is to the PGA or
secondary ∆Σ A/D converter.
0: To the PGA
1: To the secondary ∆Σ A/D converter
2 to
0
All 0 Reserved
These bits cannot be modified.
Note: When the BYPGA bit is set to 1 and the PGA factor is 1, the factor of analog input voltage is
also 1. However, analog input voltage is limited to range from 0 to Vref [V] when the
BYPGA bit is set to 1 and from 0 to 0.9 Vref [V] when the PGA factor is 1. Therefore when
the factor of analog input voltage is 1, the setting when the BYPGA bit is set to 1 should be
used.
Rev. 1.00, 07/04, page 378 of 570
19.4 Operation
The ∆Σ A/D converter uses the ∆Σ modulator and converts the analog input voltage range
specified by the Vref pin to digital data with 14-bit resolution. The ∆Σ A/D converter is
configured of two blocks: the analog block whose main part is a ∆Σ modulator and digital block
consisted of the digital filter control circuit.
In the analog block, voltage of the analog input pins (Vin1 and Vin2) is sampled by the frequency
320 times the conversion frequency (oversampling frequency) and then converted to the 1-bit
digital row with the secondary ∆Σ modulator. The conversion result is output as 14-bit data with
unsigned binary coded to ADDR via the decimation filter in the digital block. The ADD13 bit in
ADDR is MSB and the ADD0 bit is LSB.
19.4.1 Wait Mode
In wait mode, A/D conversion is executed once for the specified one analog input channel as
follows.
1. A/D conversion is started from the selected channel when the ADS bit in ADSSR is set to 1,
according to software.
2. When A/D conversion is completed, the result is transferred to the A/D data register.
3. On completion of conversion, the IRRSAD flag in IRR2 is set to 1. If the IENSAD bit in
IENR2 is set to 1 at this time, an A/D conversion end interrupt request is generated.
4. The ADST bit remains set to 1 during A/D conversion. When A/D conversion ends, the ADS
bit is automatically cleared to 0 and the ∆Σ A/D converter enters the wait state.
19.4.2 Continuous Mode
In continuous mode, A/D conversion is executed continuously for the specified single analog input
channel as follows.
1. A/D conversion is started from the selected channel when the MOD bit in ADCR is set to 1,
according to software.
2. When A/D conversion is completed, the result is transferred to the A/D data register.
3. On completion of conversion, the IRRSAD flag in IRR2 is set to 1. If the IENSAD bit in
IENR2 is set to 1 at this time, an A/D conversion end interrupt request is generated.
4. Then steps 2 and 3 are repeated. To stop continuous mode, a reset should be executed, a
transition should be made to watch, subactive, subsleep, or standby mode, or the MOD bit in
ADCR should be cleared to 0.
Rev. 1.00, 07/04, page 379 of 570
19.4.3 Operating States of ∆Σ A/D Converter
Table 19.2 shows the operating states of the ∆Σ A/D converter.
Table 19.2 Operating States of ∆Σ A/D Converter
Operatin
g Mode
Reset
Active
Sleep
Watch Sub-
active Sub-
sleep
Standby Module
Standby
ADCR Reset Functions Retained Retained Retained Retained Retained Retained
ADSSR Reset Functions Functions Retained Retained Retained Retained Retained
ADDR Retained* Functions Functions Retained Retained Retained Retained Retained
BGRMR Reset Functions Retained Retained Functions Retained Retained Retained
Note: * Undefined at a power-on reset.
19.5 Example of Use
19.5.1 Wait Mode
An example of how the ∆Σ A/D converter can be used is given below, using channel 1 (pin Ain1)
as the analog input channel. Figure 19.2 shows the operation timing.
1. The AIN1 and AIN0 bits in ADSSR are set to B'01, making pin Ain1 the analog input
channel. A/D conversion is started (the ADS bit is set to 1) by setting the IENSAD bit to 1.
2. When A/D conversion is completed, the IRRSAD bit is set to 1, and the A/D conversion
result is stored in ADDR. At the same time the ADST bit is cleared to 0, and the ∆Σ A/D
converter enters the idle state.
3. The IENSAD bit is set to 1, so an A/D conversion end interrupt is requested.
4. The A/D interrupt handling routine starts.
5. The A/D conversion result is read and processed.
6. The A/D interrupt handling routine ends.
If the ADS bit is cleared to 0 and then set to 1, A/D conversion starts and steps 2 to 6 take place.
Figures 19.3 and 19.4 show flowcharts of procedures for using the ∆Σ A/D converter.
Rev. 1.00, 07/04, page 380 of 570
19.5.2 Continuous Mode
An example of how the ∆Σ A/D converter can be used is given below, using channel 1 (pin Ain1)
as the analog input channel. Figure 19.5 shows the operation timing.
1. The AIN1 and AIN0 bits in ADSSR are set to B'01, making pin Ain1 the analog input
channel. The IENSAD bit is set to 1.
2. A/D conversion is started (the MOD bit in ADCR is set to 1).
3. When A/D conversion is completed, the IRRSAD bit is set to 1, and the A/D conversion
result is stored in ADDR.
4. The IENSAD bit is set to 1, so an A/D conversion end interrupt is requested.
5. The A/D interrupt handling routine starts.
6. The A/D conversion result is read and processed.
7. The A/D interrupt handling routine ends.
Then steps 3 to 7 are repeated. To stop continuous mode, a reset should be executed, a transition
should be made to watch, subactive, subsleep, or standby mode, or the MOD bit in ADCR should
be cleared to 0.
Rev. 1.00, 07/04, page 381 of 570
Interrupt (IRRSDADCN)
IENSAD
ADS
ADST
ADDR
Channel 1 (Ain1)
operating state
Note: * indicates instruction execution by software.
Set*
Set*
A/D conversion starts
Idle Idle Idle
A/D conversion (1) A/D conversion (2)
Set*Clear*
Read conversion result
A/D conversion result (1) A/D conversion result (2)
↓
↓Read conversion result
↓
Figure 19.2 Example of ∆Σ A/D Conversion Operation (Wait Mode)
Rev. 1.00, 07/04, page 382 of 570
Start
Set A/D conversion speed and input channel
Disable A/D conversion end interrupt
Start A/D conversion
Perform A/D conversion?
End
Read ADSSR
ADDR = 0?
Read ADRR data
Yes
Yes
No
No
Figure 19.3 Flowchart of Proced ure for Usin g ∆Σ A/D Converter (Polling by Software)
Set A/D conversion speed and input channel
Start
Enable A/D conversion end interrupt
Start A/D conversion
Clear IRRSAD bit in IRR2 to 0
Read ADDR data
A/D conversion end
interrupt generated?
Perform A/D conversion?
End
No
No
Yes
Yes
Figure 19.4 Flowchart of Proced ure for Usin g ∆Σ A/D Converter (Interrupts Used)
Rev. 1.00, 07/04, page 383 of 570
IENSAD
MOD
ADDR
Interrupt (IRRSDADCN)
Channel 1 (Ain1)
operating state
Note: * indicates instruction execution by software.
Set*
Set*
A/D conversion
starts
Idle A/D conversion (3)A/D conversion (1) A/D conversion (2)
Read conversion result
A/D conversion result (1) A/D conversion result (2)
↓
↓Read conversion result
Figure 19.5 Example of ∆Σ A/D Conversion Operation (Continuous Mode)
Rev. 1.00, 07/04, page 384 of 570
19.6 Usage Notes
19.6.1 Reference Voltage
In normal operation, pulse current of several µA flows to the Vref pin which is the reference
power supply pin. Connect the reference voltage which can apply stable voltage to the Vref pin.
19.6.2 Analog Voltage Stabilization Pin (ACOM Pin)
The ACOM pin is used to connect a capacitor (0.1 µF) to GND because of the internal amplifier
phase compensation of the ∆Σ A/D Converter. Do not connect the ACOM pin to the devices other
than capacitors or circuits.
19.6.3 After Clearing Module Standby Mode
When A/D conversion is started after clearing module standby mode, wait for 10φ clock cycles
before starting A/D conversion.
19.6.4 Influences on Accuracy
1. Changing the digital input signal at an adjacent pin during A/D conversion may adversely
affect conversion accuracy.
2. Noise in GND may adversely affect accuracy. Be sure to make the connection to an
electrically stable GND. Care is also required to ensure that filter circuits do not interfere with
digital signals or act as antennas on the mounting board.
LCDSG02A_000120040500 Rev. 1.00, 07/04, page 385 of 570
Section 20 LCD Controller/Driver
This LSI has an on-chip segment-type LCD control circuit, LCD driver, and power supply circuit,
enabling it to directly drive an LCD panel.
20.1 Features
• Display capacity
Duty Cycle Internal Driver
Static 32 SEG
1/2 32 SEG
1/3 32 SEG
1/4 32 SEG
• LCD RAM capacity
8 bits × 16 bytes (128 bits)
• Word access to LCD RAM
• The segment output pins can be used as ports.
SEG32 to SEG1 pins can be used as ports in groups of four.
• Common output pins not used because of the duty cycle can be used for common double-
buffering (parallel connection).
With 1/2 duty, parallel connection of COM1 to COM2, and of COM3 to COM4, can be used
In static mode, parallel connection of COM1 to COM2, COM3, and COM4 can be used
• Choice of 11 frame frequencies
• A or B waveform selectable by software
• On-chip power supply split-resistor
• Display possible in operating modes other than standby mode
• On-chip 3-V constant-voltage power supply circuit
This power circuit can constantly supply 3 V to LCD drive power supply without using Vcc
voltage.
• Output of the 3-V constant-voltage power supply circuit adjustable
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (For details, refer to section 6.4, Module Standby Function.)
Rev. 1.00, 07/04, page 386 of 570
Figure 20.1 shows a block diagram of the LCD controller/driver.
φ/2 to φ/256
φw
SEGn (n = 1 to 32)
LPCR
LCR
LCR2
Display timing generator
LCD RAM
16 bytes
Internal data bus
32-bit
shift
register
LCD drive
power supply
(On-chip 3-V
constant-voltage
power supply circuit)
Segment
driver
Common
data latch
Common
driver
V1
C1
C2
V2
V3
Vss
COM1
COM4
SEG32
SEG31
SEG30
SEG29
SEG28
SEG1
[Legend]
LPCR:
LCR:
LCR2:
LTRMR:
BGRMR:
Vcc
LTRMR
BGRMR
LCD port control register
LCD control register
LCD control register 2
LCD trimming register
BGR control register
Figure 20.1 Block Diagram of LCD Controller/Driver
Rev. 1.00, 07/04, page 387 of 570
20.2 Input/Output Pins
Table 20.1 shows the LCD controller/driver pin configuration.
Table 20.1 Pin Configuration
Name Symbol I/O Function
Segment output
pins
SEG32 to SEG1 Output LCD segment drive pins
All pins are multiplexed as port pins (setting
programmable)
Common output
pins
COM4 to COM1 Output LCD common drive pins
Pins can be used in parallel with static or
1/2 duty
LCD power supply
pins
V1, V2, V3 — Used when a bypass capacitor is connected
externally, and when an external power supply
circuit is used
LCD step-up
capacitance pins
C1, C2 — Capacitance pins for stepping up the LCD drive
power supply
Rev. 1.00, 07/04, page 388 of 570
20.3 Register Descriptions
The LCD controller/driver has the following registers.
• LCD port control register (LPCR)
• LCD control register (LCR)
• LCD control register 2 (LCR2)
• LCD trimming register (LTRMR)
• BGR control register (BGRMR)
• LCDRAM
20.3.1 LCD Port Contro l Register (LPCR)
LPCR selects the duty cycle, LCD driver, and pin functions.
Bit Bit Name
Initial
Value R/W Description
7
6
5
DTS1
DTS0
CMX
0
0
0
R/W
R/W
R/W
Duty Cycle Select 1 and 0
Common Function Select
The combination of DTS1 and DTS0 selects static, 1/2,
1/3, or 1/4 duty. CMX specifies whether or not the
same waveform is to be output from multiple pins to
increase the common drive power when not all
common pins are used because of the duty setting.
For details, see table 20.2.
4 — — W Reserved
Only 0 can be written to this bit.
3
2
1
0
SGS3
SGS2
SGS1
SGS0
0
0
0
0
R/W
R/W
R/W
R/W
Segment Driver Select 3 to 0
Select the segment drivers to be used.
For details, see table 20.3.
Rev. 1.00, 07/04, page 389 of 570
Table 20.2 Duty Cycle and Common Function Selection
Bit 7:
DTS1 Bit 6:
DTS0 Bit 5:
CMX
Duty Cycle
Common Drivers
Notes
0 0 0 Static COM1 Do not use COM4, COM3, and
COM2
1 COM4 to COM1 COM4, COM3, and COM2
output the same waveform as
COM1
1 0 1/2 duty COM2 to COM1 Do not use COM4 and COM3
1 COM4 to COM1 COM4 outputs the same
waveform as COM3, and COM2
outputs the same waveform as
COM1
1 0 0 1/3 duty COM3 to COM1 Do not use COM4
1 COM4 to COM1 Do not use COM4
1 X 1/4 duty COM4 to COM1 —
[Legend]
X: Don't care
Table 20.3 Segment Driver Selection
Function of Pins SEG32 to SEG1
Bit 3:
SGS3 Bit 2:
SGS2 Bi t 1:
SGS1 Bi t 0:
SGS0 SEG32 to
SEG29 SEG28 to
SEG25 SEG24 to
SEG21 SEG20 to
SEG17 SEG16 to
SEG13 SEG12 to
SEG9 SEG8 to
SEG5 SEG4 to
SEG1
0 0 0 0 Port Port Port Port Port Port Port Port
1 Port Port Port Port Port Port Port SEG
1 0 Port Port Port Port Port Port SEG SEG
1 Port Port Port Port Port SEG SEG SEG
1 0 0 Port Port Port Port SEG SEG SEG SEG
1 Port Port Port SEG SEG SEG SEG SEG
1 0 Port Port SEG SEG SEG SEG SEG SEG
1 Port SEG SEG SEG SEG SEG SEG SEG
1 0 0 0 SEG SEG SEG SEG SEG SEG SEG SEG
1 SEG SEG SEG SEG SEG SEG SEG Port
1 0 SEG SEG SEG SEG SEG SEG Port Port
1 SEG SEG SEG SEG SEG Port Port Port
1 0 0 SEG SEG SEG SEG Port Port Port Port
1 SEG SEG SEG Port Port Port Port Port
1 0 SEG SEG Port Port Port Port Port Port
1 SEG Port Port Port Port Port Port Port
Rev. 1.00, 07/04, page 390 of 570
20.3.2 LCD Control Register (LCR)
LCR controls LCD drive power supply and display data, and selects the frame frequency.
Bit Bit Name
Initial
Value R/W Description
7 — 1 — Reserved
This bit is always read as 1 and cannot be modified.
6 PSW 0 R/W LCD Drive Power Supply Control
Can be used to turn off the LCD drive power supply
when LCD display is not required in power-down mode,
or when an external power supply is used. When the
ACT bit is cleared to 0 or in standby mode, the LCD
drive power supply is turned off regardless of the
setting of this bit.
0: LCD drive power supply is turned off
1: LCD drive power supply is turned on
5 ACT 0 R/W Display Function Activate
Specifies whether or not the LCD controller/driver is
used. Clearing this bit to 0 halts operation of the LCD
controller/driver. The LCD drive power supply is also
turned off, regardless of the setting of the PSW bit.
However, register contents are retained.
0: LCD controller/driver halts
1: LCD controller/driver operates
4 DISP 0 R/W Display Data Control
Specifies whether the LCD RAM contents are
displayed or blank data is displayed regardless of the
LCD RAM contents.
0: Blank data is displayed
1: LCD RAM data is displayed
3
2
1
0
CKS3
CKS2
CKS1
CKS0
0
0
0
0
R/W
R/W
R/W
R/W
Frame Frequency Select 3 to 0
Select the operating clock and the frame frequency.
However, in subactive mode, watch mode, and
subsleep mode, the system clock (φ) is halted.
Therefore display operations are not performed if one
of the clocks from φ/2 to φ/256 is selected. If LCD
display is required in these modes, φW, φW/2, or φW/4
must be selected as the operating clock.
For details, see table 20.4.
Rev. 1.00, 07/04, page 391 of 570
Table 20.4 Frame Frequency Selection
Bit 3: Bit 2: Bit 1: Bit 0: Frame Frequency*1
CKS3 CKS2 CKS1 CKS0 Operating Clock φ = 2 MHz φ = 250 kHz*3
0 X 0 0 φW 128 Hz*2 128 Hz*2
1 φW/2 64 Hz*2 64 Hz*2
1 X φW/4 32 Hz*2 32 Hz*2
1 0 0 0 φ/2 — 244 Hz
1 φ/4 977 Hz 122 Hz
1 0 φ/8 488 Hz 61 Hz
1 φ/16 244 Hz 30.5 Hz
1 0 0 φ/32 122 Hz —
1 φ/64 61 Hz —
1 0 φ/128 30.5 Hz —
1 φ/256 — —
[Legend]
X: Don't care
Notes: 1. When 1/3 duty is selected, the frame frequency is 4/3 times the value shown.
2. This is the frame frequency when φW = 32.768 kHz.
3. This is the frame frequency in active (medium-speed, φOSC/8) mode when φ = 2 MHz.
Rev. 1.00, 07/04, page 392 of 570
20.3.3 LCD Control Register 2 (LCR2)
LCR2 controls switching between the A waveform and B waveform, selection of the step-up clock
for the 3-V constant-voltage circuit, connection with the LCD power-supply split resistor, and
turning on or off 3-V constant-voltage power supply.
Bit Bit Name
Initial
Value R/W Description
7 LCDAB 0 R/W A Waveform/B Waveform Switching Control
Specifies whether the A waveform or B waveform is
used as the LCD drive waveform.
0: Drive using A waveform
1: Drive using B waveform
6 HCKS 0 R/W Step-Up Clock Selection for 3-V Constant-Voltage
Power Supply Circuit
Selects a step-up clock for use in the 3-V constant-
voltage power supply circuit. The step-up clock is
obtained by dividing the clock selected by the CKS3 to
CKS0 bits in LCR into 4 or 8.
0: Divided into 4
1: Divided into 8
5 CHG 0 R/W Connection Control of LCD Power-Supply Split
Resistor
Selects whether an LCD power-supply split resistor is
disconnected or connected from or to LCD drive power
supply.
0: Disconnected
1: Connected
4 SUPS 0 R/W 3-V Constant-Voltage Power Supply Control
Can be used to turn off the 3-V constant-voltage power
supply when LCD display is not required in power-
down mode, or when an external power supply is used.
When the BGRSTPN bit in BGRMR is cleared to 0 or in
standby mode, the 3-V constant-voltage power supply
is turned off regardless of the setting of this bit.
0: 3-V constant-voltage power supply is turned off
1: 3-V constant-voltage power supply is turned on
3 to 0 — — W Reserved
Only 0 can be written to these bits.
Rev. 1.00, 07/04, page 393 of 570
20.3.4 LCD Trimming Register (LTRMR)
LTRMR adjusts 3-V constant-voltage used for LCD drive power supply and trims the output
voltage adjustment of 3-V constant-voltage power supply circuit.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
TRM3
TRM2
TRM1
TRM0
0
0
0
0
R/W
R/W
R/W
R/W
Output Voltage Adjustment of 3-V Constant-Voltage
Power Supply Circuit
By adjusting reference voltage that generates 3-V
constant voltage, LCD drive power supply can be set to
3 V. Following values* indicate the voltage of the V1
pin.
0000: 3.00 V 1000: 3.48 V
0001: 2.94 V 1001: 3.42 V
0010: 2.88 V 1010: 3.36 V
0011: 2.85 V 1011: 3.30 V
0100: 2.79 V 1100: 3.24 V
0101: 2.76 V 1101: 3.18 V
0110: 2.70 V 1110: 3.12 V
0111: 2.67 V 1111: 3.06 V
3 — 1 — Reserved
This bit is always read as 1 and cannot be modified.
2
1
0
CTRM2
CTRM1
CTRM0
0
0
0
R/W
R/W
R/W
Variable Voltage Adjustment of 3-V Constant-Voltage
Power Supply
3-V power supply used for LCD drive power supply is
adjustable within the range of 3 V ±10%. If an LCD
panel does not function normally due to a temperature
in which LCD is used, set these bits to adjust it.
000: 3.00 V
001: 3.09 V
010: 3.18 V
011: 3.27 V
100: 2.64 V
101: 2.73 V
110: 2.82 V
111: 2.91 V
Note: * These are approximate values and are not guaranteed. Therefore these values should
be used as reference values.
Rev. 1.00, 07/04, page 394 of 570
20.3.5 BGR Control Register (BGRMR)
BGRMR controls whether the band-gap reference circuit (BGR) which generates the reference
voltage of the 3-V constant-voltage power supply and ∆Σ A/D converter operates or halts, and
adjusts the reference voltage.
Bit Bit Name
Initial
Value R/W Description
7 BGRSTPN 0 R/W Band-Gap Reference Circuit Control
Controls whether the band-gap reference circuit
operates or halts.
0: Band-gap reference circuit halts
1: Band-gap reference circuit operates
6 to 3 All 1 Reserved
These bits are always read as 1 and cannot be
modified.
2
1
0
BTRM2
BTRM1
BTRM0
0
0
0
R/W
R/W
R/W
BGR Output Voltage Trimming
BGR Output Voltage Trimming
Adjust approximately 1.2-V BGR output voltage.
000: ±0 V
001: +0.14 V
010: +0.09 V
011: +0.04 V
100: −0.04 V
101: −0.09 V
110: −0.14 V
111: −0.18 V
Rev. 1.00, 07/04, page 395 of 570
20.4 Operation
20.4.1 Settings up to LCD Display
To perform LCD display, the hardware and software related items described below must first be
determined.
(1) Hardware Settings
(a) Using 1/2 duty
When 1/2 duty is used, interconnect pins V2 and V3 as shown in figure 20.2.
V1
V2
V3
V
CC
V
SS
Figure 20.2 Handling of LCD Drive Power Supply when Using 1/2 Du ty
(b) Large-Panel Display
As the impedance of the on-chip power supply split-resistor is large, it may not be suitable for
driving a large panel. If the display lacks sharpness when using a large panel, refer to section
20.4.5, Boosting LCD Drive Power Supply. When static or 1/2 duty is selected, the common
output drive capability can be increased. Set CMX to 1 when selecting the duty cycle. In this
mode, with a static duty cycle pins COM4 to COM1 output the same waveform, and with 1/2 duty
the COM1 waveform is output from pins COM2 and COM1, and the COM2 waveform is output
from pins COM4 and COM3.
(c) LCD Drive Power Supply Setting
With this LSI, there are two ways of providing LCD power: by using the on-chip power supply
circuit, or by using an external power supply circuit.
When an external power supply circuit is used for the LCD drive power supply, connect the
external power supply to the V1 pin.
Rev. 1.00, 07/04, page 396 of 570
(2) Software Settings
(a) Duty Selection
Any of four duty cycles—static, 1/2 duty, 1/3 duty, or 1/4 duty—can be selected with bits DTS1
and DTS0.
(b) Segment Driver Selection
The segment drivers to be used can be selected with bits SGS3 to SGS0.
(c) Frame Frequency Selection
The frame frequency can be selected by setting bits CKS3 to CKS0. The frame frequency should
be selected in accordance with the LCD panel specification. For the clock selection method in
watch mode, subactive mode, and subsleep mode, see section 20.4.4, Operation in Power-Down
Modes.
(d) A or B Waveform Selection
Either the A or B waveform can be selected as the LCD waveform to be used by means of
LCDAB.
(e) LCD Drive Power Supply Selection
When an external power supply circuit is used, turn the LCD drive power supply off with the PSW
bit.
Rev. 1.00, 07/04, page 397 of 570
20.4.2 Relationship between LCD RAM and Dis pl ay
The relationship between the LCD RAM and the display segments differs according to the duty
cycle. LCD RAM maps for the different duty cycles are shown in figures 20.3 to 20.6.
After setting the registers required for display, data is written to the part corresponding to the duty
using the same kind of instruction as for ordinary RAM, and display is started automatically when
turned on. Word- or byte-access instructions can be used for RAM setting.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
H'F37F
H'F370
SEG31 SEG31 SEG31 SEG31SEG32 SEG32 SEG32 SEG32
SEG2 SEG2 SEG2 SEG2 SEG1 SEG1 SEG1 SEG1
COM4 COM3 COM2 COM1 COM4 COM3 COM2 COM1
Figure 20.3 LCD RAM Map (1/4 Duty)
H'F37F
H'F370
SEG31 SEG31 SEG31SEG32 SEG32 SEG32
SEG2 SEG2 SEG2 SEG1 SEG1 SEG1
COM3
Space not used for display
COM2 COM1 COM3 COM2 COM1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Figure 20.4 LCD RAM Map (1/3 Duty)
Rev. 1.00, 07/04, page 398 of 570
H'F37F
H'F370
H'F377 SEG29 SEG29SEG30 SEG30SEG31 SEG31SEG32 SEG32
SEG4 SEG4 SEG3 SEG3 SEG2 SEG2 SEG1 SEG1
Display space
Space not used
for display
COM2 COM1 COM2 COM1 COM2 COM1 COM2 COM1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Figure 20.5 LCD RAM Map (1/2 Duty)
H'F37F
H'F370
H'F373 SEG25SEG26SEG27SEG28SEG29SEG30SEG31SEG32
Display space
Space not used
for display
SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1
COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Figure 20.6 LCD RAM Map (Static Mode)
Rev. 1.00, 07/04, page 399 of 570
Figure 20.7 shows a output waveforms for each duty cycle (A waveform).
M
Data
(a) Waveform with 1/4 duty
(c) Waveform with 1/2 duty
(d) Waveform with static output
M: LCD alternation signal
(b) Waveform with 1/3 duty
COM1
COM2
COM3
COM4
SEGn
M
Data
COM1
COM2
SEGn
M
Data
COM1
SEGn
M
Data
1 frame 1 frame
1 frame 1 frame
COM1
V1
V2
V3
V
SS
V1
V2
V3
V
SS
V1
V2
V3
V
SS
V1
V2
V3
V
SS
V1
V2
V3
V
SS
V1
V2,V3
V
SS
V1
V
SS
V1
V
SS
V1
V2,V3
V
SS
V1
V2,V3
V
SS
V1
V2
V3
V
SS
V1
V2
V3
V
SS
V1
V1
V2
V3
V
SS
V2
V3
V
SS
COM2
COM3
SEGn
Figure 20.7 Output Waveforms f or Each Duty Cycle (A Waveform)
Rev. 1.00, 07/04, page 400 of 570
Figure 20.8 shows a output waveforms for each duty cycle (B waveform).
M: LCD alternation signal
M
Data
(a) Waveform with 1/4 duty
(c) Waveform with 1/2 duty
(d) Waveform with static output
(b) Waveform with 1/3 duty
COM1
COM2
COM3
COM4
SEGn
M
Data
COM1
COM2
SEGn
M
Data
COM1
SEGn
M
Data
1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame
1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame
COM1
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2,V3
VSS
V1
VSS
V1
VSS
V1
V2,V3
VSS
V1
V2,V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V1
V2
V3
VSS
V2
V3
VSS
COM2
COM3
SEGn
Figure 20.8 Output Waveforms f or Each Duty Cycle (B Waveform)
Rev. 1.00, 07/04, page 401 of 570
Table 20.5 shows a output levels.
Table 20.5 Output Levels
Data 0 0 1 1
M 0 1 0 1
Static Common output V1 VSS V1 VSS
Segment output V1 VSS VSS V1
1/2 duty Common output V2, V3 V2, V3 V1 VSS
Segment output V1 VSS VSS V1
1/3 duty Common output V3 V2 V1 VSS
Segment output V2 V3 VSS V1
1/4 duty Common output V3 V2 V1 VSS
Segment output V2 V3 VSS V1
M: LCD alternation signal
20.4.3 3-V Constant-Voltage Power Supply Circuit
This LSI incorporates a 3-V constant-voltage power supply circuit consisting of a band gap
reference circuit (BGR), a triple step-up circuit, etc. This allows the 3 V constant voltage to drive
LCD driver independently of Vcc.
Before activating a step-up circuit, LCD controller/driver operates and set the duty cycle, pin
function of the LCD driver or I/O, display data, frame frequencies, etc. Insert a capacitance of 0.1
µF between the C1 pin and C2 pin, and connect a capacitance of 0.1 µF to each of V1, V2, and V3
pins. (See figure 20.9.)
After this setting, setting the BGRSTPN bit in the BGR control register (BGRMR) to 1 activates
the band gap reference circuit, generating 1 V constant voltage (VLCD3) at the V3 pin. Furthermore,
selecting the step-up circuit clock of the LCD control register 2 (LCR2) and setting the SUPS bit
to 1 activates the triple step-up circuit, generating 2 V constant voltage, twice VLCD3, at the V2 pin,
and generating 3 V constant voltage, triple VLCD3, at the V1 pin.
Notes: 1. Power supply might be insufficient when a large panel is driven. In this case, use Vcc
for power supply, or use an external power supply circuit.
2. Do not use a polarized capacitance such as an electrolytic capacitor for connection
between the C1 pin and C2 pin.
3. A 3-V constant-voltage power supply circuit is turned on by SUSP bit regardless of the
setting of the PSW bit.
Rev. 1.00, 07/04, page 402 of 570
C1
C2
V2
V1
C
C
C: 0.1 µF
CC
V3
Figure 20.9 Capacitance Connection when Using 3-V Consta nt -V oltage
Power Supply Circuit
20.4.4 Operation in Power-Down Modes
In this LSI, the LCD controller/driver can be operated even in the power-down modes. The
operating state of the LCD controller/driver in the power-down modes is summarized in table
20.6.
In subactive mode, watch mode, and subsleep mode, the system clock oscillator stops, and
therefore, unless φW, φW/2, or φW/4 has been selected by bits CKS3 to CKS0, the clock will not be
supplied and display will halt. The subclock can be turned on or off by setting the 32KSTOP bit in
the SUB32K control register (SUB32CR). When it is turned off, display will halt. Since there is a
possibility that a direct current will be applied to the LCD panel in this case, it is essential to
ensure that the subclock is turned on and φW, φW/2, or φW/4 is selected.
In active (medium-speed) mode, the system clock is switched, and therefore bits CKS3 to CKS0
must be modified to ensure that the frame frequency does not change.
Rev. 1.00, 07/04, page 403 of 570
Table 20.6 Power-Down Modes and Display Operation
Mode
Reset
Active
Sleep
Watch
Subactive
Subsleep
Standby
Module
Standby
Clock φ Runs Runs Runs Stops Stops Stops Stops Stops*4
φw Runs Runs Runs Runs*5 Runs*5 Runs*5 Stops*1 Stops*4
Display ACT = 0 Stops Stops Stops Stops Stops Stops Stops*2 Stops
operation ACT = 1 Stops Functions Functions Functions*3*5Functions*3*5Functions*3*5Stops*2 Stops
Notes: 1. The subclock oscillator does not stop, but clock supply is halted.
2. The LCD drive power supply is turned off regardless of the setting of the PSW bit.
3. Display operation is performed only if φW, φW/2, or φW/4 is selected as the operating
clock.
4. The clock supplied to the LCD stops.
5. When the 32KSTOP bit in SUB32CR is set to 1, the subclock φW halts and display
operation halts.
20.4.5 Boosting LCD Drive Power Supply
When a large panel is driven, the on-chip power supply capacity may be insufficient. In this case,
the power supply impedance must be reduced. This can be done by connecting bypass capacitors
of around 0.1 to 0.3 µF to pins V1 to V3, as shown in figure 20.10, or by adding a split resistor
externally.
This LSI
VCC
VSS
V1
V2
V3
R
R
R
R
R =
C = 0.1 to 0.3 µF
several kΩ to
several MΩ
Figure 20.10 Connection of External Split Resistor
Rev. 1.00, 07/04, page 404 of 570
IFIIC10A_000020020200 Rev. 1.00, 07/04, page 405 of 570
Section 21 I2C Bus Interface 2 (IIC2)
The I2C bus interface 2 conforms to and provides a subset of the Philips I2C bus (inter-IC bus)
interface functions. The register configuration that controls the I2C bus differs partly from the
Philips configuration, however. Figure 21.1 shows a block diagram of the I2C bus interface 2.
Figure 21.2 shows an example of I/O pin connections to external circuits.
21.1 Features
• Selection of I2C format or clocked synchronous serial format
• Continuous transmission/reception
Since the shift register, transmit data register, and receive data register are independent from
each other, the continuous transmission/reception can be performed.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (For details, refer to section 6.4, Module Standby Function.)
I2C bus format
• Start and stop conditions generated automatically in master mode
• Selection of acknowledge output levels when receiving
• Automatic loading of acknowledge bit when transmitting
• Bit synchronization/wait function
In master mode, the state of SCL is monitored per bit, and the timing is synchronized
automatically.
If transmission/reception is not yet possible, set the SCL to low until preparations are
completed.
• Six interrupt sources
Transmit data empty (including slave-address match), transmit end, receive data full (including
slave-address match), arbitration lost, NACK detection, and stop condition detection
• Direct bus drive
Two pins, SCL and SDA pins, function as CMOS outputs in normal operation (when the
port/serial function is selected) and NMOS outputs when the bus drive function is selected.
Clocked synchronous format
• Four interrupt sources
Transmit-data-empty, transmit-end, receive-data-full, and overrun error
Rev. 1.00, 07/04, page 406 of 570
SCL
ICCR1
Transfer clock
generation
circuit
Address
comparator
Interrupt
generator Interrupt request
Bus state
decision circuit
Arbitration
decision circuit
Noise canceler
Noise canceler
Output
control
Output
control
Transmission/
reception
control circuit
ICCR2
ICMR
ICSR
ICIER
ICDRR
ICDRS
ICDRT
I
2
C bus control register 1
I
2
C bus control register 2
I
2
C bus mode register
I
2
C bus status register
I
2
C bus interrupt enable register
I
2
C bus transmit data register
I
2
C bus receive data register
I
2
C bus shift register
Slave address register
[Legend]
ICCR1:
ICCR2:
ICMR:
ICSR:
ICIER:
ICDRT:
ICDRR:
ICDRS:
SAR:
SAR
SDA
Internal data bus
Figure 21.1 Block Diagram of I2C Bus Interface 2
Rev. 1.00, 07/04, page 407 of 570
Vcc Vcc
SCL in
SCL out
SCL
SDA in
SDA out
SDA
SCL
(Master)
(Slave 1) (Slave 2)
SDA
SCL in
SCL out
SCL
SDA in
SDA out
SDA
SCL in
SCL out
SCL
SDA in
SDA out
SDA
Figure 21.2 External Circuit Connections of I/O Pins
21.2 Input/Output Pins
Table 21.1 summarizes the input/output pins used by the I2C bus interface 2.
Table 21.1 Pin Configuration
Name Abbreviation I/O Function
Serial clock pin SCL I/O IIC serial clock input/output
Serial data pin SDA I/O IIC serial data input/output
21.3 Register Descriptions
The I2C bus interface 2 has the following registers.
• I2C bus control register 1 (ICCR1)
• I2C bus control register 2 (ICCR2)
• I2C bus mode register (ICMR)
• I2C bus interrupt enable register (ICIER)
• I2C bus status register (ICSR)
• Slave address register (SAR)
• I2C bus transmit data register (ICDRT)
• I2C bus receive data register (ICDRR)
• I2C bus shift register (ICDRS)
Rev. 1.00, 07/04, page 408 of 570
21.3.1 I2C Bus Control Register 1 (ICCR1)
ICCR1 enables or disables the I2C bus interface 2, controls transmission or reception, and selects
master or slave mode, transmission or reception, and transfer clock frequency in master mode.
Bit Bit Name
Initial
Value R/W Description
7 ICE 0 R/W I2C Bus Interface 2 Enable
0: This module is halted. (SCL and SDA pins are set to
the port/serial function.)
1: This bit is enabled for transfer operations. (SCL and
SDA pins are bus drive state.)
6 RCVD 0 R/W Reception Disable
This bit enables or disables the next operation when
TRS is 0 and ICDRR is read.
0: Enables next reception
1: Disables next reception
5
4
MST
TRS
0
0
R/W
R/W
Master/Slave Select
Transmit/Receive Select
In master mode with the I2C bus format, when
arbitration is lost, MST and TRS are both reset by
hardware, causing a transition to slave receive mode.
Modification of the TRS bit should be made between
transfer frames.
After data receive has been started in slave receive
mode, when the first seven bits of the receive data
agree with the slave address that is set to SAR and the
eighth bit is 1, TRS is automatically set to 1. If an
overrun error occurs in master mode with the clock
synchronous serial format, MST is cleared to 0 and
slave receive mode is entered.
Operating modes are described below according to
MST and TRS combination. When clocked
synchronous serial format is selected and MST is 1,
clock is output.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
3
2
1
0
CKS3
CKS2
CKS1
CKS0
0
0
0
0
R/W
R/W
R/W
R/W
Transfer Clock Select 3 to 0
These bits are valid only in master mode and should be
set according to the necessary transfer rate. For details
on transfer rate, see table 21.2.
Rev. 1.00, 07/04, page 409 of 570
Table 21.2 Transfer Rate
Bit 3 Bit 2 Bit 1 Bit 0 Transfer Rate
CKS3 CKS2 CKS1 CKS0 Clock φ = 2 MHz φ = 5 MHz φ = 10 MHz
0 φ/28 71.4 kHz 179 kHz 357 kHz 0
1 φ/40 50.0 kHz 125 kHz 250 kHz
0 φ/48 41.7 kHz 104 kHz 208 kHz
0
1
1 φ/64 31.3 kHz 78.1 kHz 156 kHz
0 φ/80 25.0 kHz 62.5 kHz 125 kHz 0
1 φ/100 20.0 kHz 50.0 kHz 100 kHz
0 φ/112 17.9 kHz 44.6 kHz 89.3 kHz
0
1
1
1 φ/128 15.6 kHz 39.1 kHz 78.1 kHz
0 φ/56 35.7 kHz 89.3 kHz 179 kHz 0
1 φ/80 25.0 kHz 62.5 kHz 125 kHz
0 φ/96 20.8 kHz 52.1 kHz 104 kHz
0
1
1 φ/128 15.6 kHz 39.1 kHz 78.1 kHz
0 φ/160 12.5 kHz 31.3 kHz 62.5 kHz 0
1 φ/200 10.0 kHz 25.0 kHz 50.0 kHz
0 φ/224 8.9 kHz 22.3 kHz 44.6 kHz
1
1
1
1 φ/256 7.8 kHz 19.5 kHz 39.1 kHz
Rev. 1.00, 07/04, page 410 of 570
21.3.2 I2C Bus Control Register 2 (ICCR2)
ICCR1 issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls
reset in the control part of the I2C bus interface 2.
Bit Bit Name
Initial
Value R/W Description
7 BBSY 0 R/W Bus Busy
This bit enables to confirm whether the I2C bus is
occupied or released and to issue start/stop conditions
in master mode. With the clocked synchronous serial
format, this bit has no meaning. With the I2C bus format,
this bit is set to 1 when the SDA level changes from
high to low under the condition of SCL = high, assuming
that the start condition has been issued. This bit is
cleared to 0 when the SDA level changes from low to
high under the condition of SCL = high, assuming that
the stop condition has been issued. Write 1 to BBSY
and 0 to SCP to issue a start condition. Follow this
procedure when also re-transmitting a start condition.
Write 0 in BBSY and 0 in SCP to issue a stop condition.
To issue start/stop conditions, use the MOV instruction.
6 SCP 1 R/W Start/Stop Issue Condition Disable
The SCP bit controls the issue of start/stop conditions in
master mode.
To issue a start condition, write 1 in BBSY and 0 in
SCP. A retransmit start condition is issued in the same
way. To issue a stop condition, write 0 in BBSY and 0 in
SCP. This bit is always read as 1. If 1 is written, the
data is not stored.
5 SDAO 1 R/W SDA Output Value Control
This bit is used with SDAOP when modifying output
level of SDA. This bit should not be manipulated during
transfer.
0: When reading, SDA pin outputs low.
When writing, SDA pin is changed to output low.
1: When reading, SDA pin outputs high.
When writing, SDA pin is changed to output Hi-Z
(outputs high by external pull-up resistance).
Rev. 1.00, 07/04, page 411 of 570
Bit Bit Name
Initial
Value R/W Description
4 SDAOP 1 R/W SDAO Write Protect
This bit controls change of output level of the SDA pin
by modifying the SDAO bit. To change the output level,
clear SDAO and SDAOP to 0 or set SDAO to 1 and
clear SDAOP to 0 by the MOV instruction. This bit is
always read as 1.
3 SCLO 1 R This bit monitors SCL output level. When SCLO is 1,
SCL pin outputs high. When SCLO is 0, SCL pin
outputs low.
2 1 Reserved
This bit is always read as 1, and cannot be modified.
1 IICRST 0 R/W IIC Control Part Reset
This bit resets the control part except for I2C registers. If
this bit is set to 1 when hang-up occurs because of
communication failure during I2C operation, I2C control
part can be reset without setting ports and initializing
registers.
0 1 Reserved
This bit is always read as 1, and cannot be modified.
21.3.3 I2C Bus Mode Register (ICMR)
ICMR selects whether the MSB or LSB is transferred first, performs master mode wait control,
and selects the transfer bit count.
Bit Bit Name
Initial
Value R/W Description
7 MLS 0 R/W MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
Set this bit to 0 when the I2C bus format is used.
6 WAIT 0 R/W Wait Insertion Bit
In master mode with the I2C bus format, this bit selects
whether to insert a wait after data transfer except the
acknowledge bit. When WAIT is set to 1, after the fall of
the clock for the final data bit, low period is extended for
two transfer clocks. If WAIT is cleared to 0, data and
acknowledge bits are transferred consecutively with no
wait inserted.
The setting of this bit is invalid in slave mode with the
I2C bus format or with the clocked synchronous serial
format.
Rev. 1.00, 07/04, page 412 of 570
Bit Bit Name
Initial
Value R/W Description
5, 4 All 1 Reserved
These bits are always read as 1, and cannot be
modified.
3 BCWP 1 R/W BC Write Protect
This bit controls the BC2 to BC0 modifications. When
modifying BC2 to BC0, this bit should be cleared to 0
and use the MOV instruction. In clock synchronous
serial mode, BC should not be modified.
0: When writing, values of BC2 to BC0 are set.
1: When reading, 1 is always read.
When writing, settings of BC2 to BC0 are invalid.
2
1
0
BC2
BC1
BC0
0
0
0
R/W
R/W
R/W
Bit Counter 2 to 0
These bits specify the number of bits to be transferred
next. When read, the remaining number of transfer bits
is indicated. With the I2C bus format, the data is
transferred with one addition acknowledge bit. Bit BC2
to BC0 settings should be made during an interval
between transfer frames. If bits BC2 to BC0 are set to a
value other than 000, the setting should be made while
the SCL pin is low. The value returns to 000 at the end
of a data transfer, including the acknowledge bit. With
the clock synchronous serial format, these bits should
not be modified.
I2C Bus Format Clock Synchronous Serial Format
000: 9 bits 000: 8 bits
001: 2 bits 001: 1 bits
010: 3 bits 010: 2 bits
011: 4 bits 011: 3 bits
100: 5 bits 100: 4 bits
101: 6 bits 101: 5 bits
110: 7 bits 110: 6 bits
111: 8 bits 111: 7 bits
Rev. 1.00, 07/04, page 413 of 570
21.3.4 I2C Bus Interrupt Enable Register (ICIER)
ICIER enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be
transferred, and confirms acknowledge bits to be received.
Bit Bit Name
Initial
Value R/W Description
7 TIE 0 R/W Transmit Interrupt Enable
When the TDRE bit in ICSR is set to 1, this bit enables
or disables the transmit data empty interrupt (TXI).
0: Transmit data empty interrupt request (TXI) is
disabled.
1: Transmit data empty interrupt request (TXI) is
enabled.
6 TEIE 0 R/W Transmit End Interrupt Enable
This bit enables or disables the transmit end interrupt
(TEI) at the rising of the ninth clock while the TDRE bit
in ICSR is 1. TEI can be canceled by clearing the TEND
bit or the TEIE bit to 0.
0: Transmit end interrupt request (TEI) is disabled.
1: Transmit end interrupt request (TEI) is enabled.
5 RIE 0 R/W Receive Interrupt Enable
This bit enables or disables the receive data full
interrupt request (RXI) and the overrun error interrupt
request (ERI) with the clocked synchronous format,
when a receive data is transferred from ICDRS to
ICDRR and the RDRF bit in ICSR is set to 1. RXI can
be canceled by clearing the RDRF or RIE bit to 0.
0: Receive data full interrupt request (RXI) and overrun
error interrupt request (ERI) with the clocked
synchronous format are disabled.
1: Receive data full interrupt request (RXI) and overrun
error interrupt request (ERI) with the clocked
synchronous format are enabled.
4 NAKIE 0 R/W NACK Receive Interrupt Enable
This bit enables or disables the NACK receive interrupt
request (NAKI) and the overrun error (setting of the
OVE bit in ICSR) interrupt request (ERI) with the
clocked synchronous format, when the NACKF and AL
bits in ICSR are set to 1. NAKI can be canceled by
clearing the NACKF, OVE, or NAKIE bit to 0.
0: NACK receive interrupt request (NAKI) is disabled.
1: NACK receive interrupt request (NAKI) is enabled.
Rev. 1.00, 07/04, page 414 of 570
Bit Bit Name
Initial
Value R/W Description
3 STIE 0 R/W Stop Condition Detection Interrupt Enable
0: Stop condition detection interrupt request (STPI) is
disabled.
1: Stop condition detection interrupt request (STPI) is
enabled.
2 ACKE 0 R/W Acknowledge Bit Judgement Select
0: The value of the receive acknowledge bit is ignored,
and continuous transfer is performed.
1: If the receive acknowledge bit is 1, continuous
transfer is halted.
1 ACKBR 0 R Receive Acknowledge
In transmit mode, this bit stores the acknowledge data
that are returned by the receive device. This bit cannot
be modified.
0: Receive acknowledge = 0
1: Receive acknowledge = 1
0 ACKBT 0 R/W Transmit Acknowledge
In receive mode, this bit specifies the bit to be sent at
the acknowledge timing.
0: 0 is sent at the acknowledge timing.
1: 1 is sent at the acknowledge timing.
Rev. 1.00, 07/04, page 415 of 570
21.3.5 I2C Bus Status Register (ICSR)
ICSR performs confirmation of interrupt request flags and status.
Bit Bit Name
Initial
Value R/W Description
7 TDRE 0 R/W Transmit Data Register Empty
[Setting condition]
• When data is transferred from ICDRT to ICDRS and
ICDRT becomes empty
• When TRS is set
• When a start condition (including re-transfer) has
been issued
• When transmit mode is entered from receive mode
in slave mode
[Clearing conditions]
• When 0 is written in TDRE after reading TDRE = 1
• When data is written to ICDRT with an instruction
6 TEND 0 R/W Transmit End
[Setting conditions]
• When the ninth clock of SCL rises with the I2C bus
format while the TDRE flag is 1
• When the final bit of transmit frame is sent with the
clock synchronous serial format
[Clearing conditions]
• When 0 is written in TEND after reading TEND = 1
• When data is written to ICDRT with an instruction
5 RDRF 0 R/W Receive Data Register Full
[Setting condition]
• When a receive data is transferred from ICDRS to
ICDRR
[Clearing conditions]
• When 0 is written in RDRF after reading RDRF = 1
• When ICDRR is read with an instruction
Rev. 1.00, 07/04, page 416 of 570
Bit Bit Name
Initial
Value R/W Description
4 NACKF 0 R/W No Acknowledge Detection Flag
[Setting condition]
• When no acknowledge is detected from the receive
device in transmission while the ACKE bit in ICIER
is 1
[Clearing condition]
• When 0 is written in NACKF after reading NACKF =
1
3 STOP 0 R/W Stop Condition Detection Flag
[Setting condition]
• When a stop condition is detected after frame
transfer
[Clearing condition]
• When 0 is written in STOP after reading STOP = 1
2 AL/OVE 0 R/W Arbitration Lost Flag/Overrun Error Flag
This flag indicates that arbitration was lost in master
mode with the I2C bus format and that the final bit has
been received while RDRF = 1 with the clocked
synchronous format.
When two or more master devices attempt to seize the
bus at nearly the same time, if the I2C bus interface
detects data differing from the data it sent, it sets AL to
1 to indicate that the bus has been taken by another
master.
[Setting conditions]
• If the internal SDA and SDA pin disagree at the rise
of SCL in master transmit mode
• When the SDA pin outputs high in master mode
while a start condition is detected
• When the final bit is received with the clocked
synchronous format while RDRF = 1
[Clearing condition]
• When 0 is written in AL/OVE after reading
AL/OVE=1
Rev. 1.00, 07/04, page 417 of 570
Bit Bit Name
Initial
Value R/W Description
1 AAS 0 R/W Slave Address Recognition Flag
In slave receive mode, this flag is set to 1 if the first
frame following a start condition matches bits SVA6 to
SVA0 in SAR.
[Setting conditions]
• When the slave address is detected in slave receive
mode
• When the general call address is detected in slave
receive mode.
[Clearing condition]
• When 0 is written in AAS after reading AAS=1
0 ADZ 0 R/W General Call Address Recognition Flag
This bit is valid in I2C bus format slave receive mode.
[Setting condition]
• When the general call address is detected in slave
receive mode
[Clearing conditions]
• When 0 is written in ADZ after reading ADZ=1
21.3.6 Slave Address Register (SAR)
SAR selects the communication format and sets the slave address. When the chip is in slave mode
with the I2C bus format, if the upper 7 bits of SAR match the upper 7 bits of the first frame
received after a start condition, the chip operates as the slave device.
Bit Bit Name
Initial
Value R/W Description
7 to 1 SVA6 to
SVA0
All 0 R/W Slave Address 6 to 0
These bits set a unique address in bits SVA6 to SVA0,
differing form the addresses of other slave devices
connected to the I2C bus.
0 FS 0 R/W Format Select
0: I2C bus format is selected.
1: Clocked synchronous serial format is selected.
Rev. 1.00, 07/04, page 418 of 570
21.3.7 I2C Bus Transmit Data Register (ICDRT)
ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the
space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to
ICDRS and starts transferring data. If the next transfer data is written to ICDRT during
transferring data of ICDRS, continuous transfer is possible. If the MLS bit of ICMR is set to 1
and when the data is written to ICDRT, the MSB/LSB inverted data is read. The initial value of
ICDRT is H'FF. The initial value of ICDRT is H'FF.
21.3.8 I2C Bus Receive Data Register (ICDRR)
ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR
transfers the receive data from ICDRS to ICDRR and the next data can be received. ICDRR is a
receive-only register, therefore the CPU cannot write to this register. The initial value of ICDRR
is H'FF.
21.3.9 I2C Bus Shift Register (ICDRS)
ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from
ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from
ICDRS to ICDRR after data of one byte is received. This register cannot be read directly from the
CPU.
Rev. 1.00, 07/04, page 419 of 570
21.4 Operation
The I2C bus interface can communicate either in I2C bus mode or clocked synchronous serial mode
by setting FS in SAR.
21.4.1 I2C Bus Format
Figure 21.3 shows the I2C bus formats. Figure 21.4 shows the I2C bus timing. The first frame
following a start condition always consists of 8 bits.
S SLA R/WA DATA A A/AP
1111n7
1m
(a) I2C bus format (FS = 0)
(b) I2C bus format (Start condition retransmission, FS = 0)
n: Transfer bit count
(n = 1 to 8)
m: Transfer frame count
(m ≥ 1)
S SLA R/WA DATA
111n17
1m1
S SLA R/WA DATA A/AP
111n27
1m2
111
A/A
n1 and n2: Transfer bit count (n1 and n2 = 1 to 8)
m1 and m2: Transfer frame count (m1 and m2 ≥ 1)
11
Figure 21.3 I2C Bus Formats
SDA
SCL
S
1 to 7
SLA
8
R/W
9
A
1 to 7
DATA
8 9 1 to 7 8 9
A DATA P
A
Figure 21.4 I2C Bus Timing
[Legend]
S: Start condition. The master device drives SDA from high to low while SCL is high.
SLA: Slave address
R/W: Indicates the direction of data transfer: from the slave device to the master device when
R/W is 1, or from the master device to the slave device when R/W is 0.
A: Acknowledge. The receive device drives SDA to low.
DATA: Transfer data
P: Stop condition. The master device drives SDA from low to high while SCL is high.
Rev. 1.00, 07/04, page 420 of 570
21.4.2 Master Transmit Operation
In master transmit mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. For master transmit mode operation timing, refer to
figures 21.5 and 21.6. The transmission procedure and operations in master transmit mode are
described below.
1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
bits in ICCR1 to 1. (Initial setting)
2. Read the BBSY flag in ICCR2 to confirm that the bus is free. Set the MST and TRS bits in
ICCR1 to select master transmit mode. Then, write 1 to BBSY and 0 to SCP using MOV
instruction. (Start condition issued) This generates the start condition.
3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte data
show the slave address and R/W) to ICDRT. At this time, TDRE is automatically cleared to 0,
and data is transferred from ICDRT to ICDRS. TDRE is set again.
4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1
at the rise of the 9th transmit clock pulse. Read the ACKBR bit in ICIER, and confirm that the
slave device has been selected. Then, write second byte data to ICDRT. When ACKBR is 1,
the slave device has not been acknowledged, so issue the stop condition. To issue the stop
condition, write 0 to BBSY and SCP using MOV instruction. SCL is fixed low until the
transmit data is prepared or the stop condition is issued.
5. The transmit data after the second byte is written to ICDRT every time TDRE is set.
6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last
byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR = 1) from the
receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or
NACKF.
7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode.
Rev. 1.00, 07/04, page 421 of 570
TDRE
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
TEND
[5] Write data to ICDRT (third byte)
ICDRT
ICDRS
[2] Instruction of start
condition issuance [3] Write data to ICDRT (first byte)
[4] Write data to ICDRT (second byte)
User
processing
1
Bit 7
Slave address
Address + R/WData 1
Data 1
Data 2
Address + R/W
Bit 6 Bit 7 Bit 6Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2123456789
A
R/W
Figure 21.5 Master Transmit Mode Operation Timing (1)
TDRE
[6] Issue stop condition. Clear TEND.
[7] Set slave receive mode
TEND
ICDRT
ICDRS
19 23456789
AA/A
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
Bit 7 Bit 6
Data n
Data n
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
[5] Write data to ICDRT
User
processing
Figure 21.6 Master Transmit Mode Operation Timing (2)
Rev. 1.00, 07/04, page 422 of 570
21.4.3 Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data from the slave
device, and returns an acknowledge signal. For master receive mode operation timing, refer to
figures 21.7 and 21.8. The reception procedure and operations in master receive mode are shown
below.
1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master
transmit mode to master receive mode. Then, clear the TDRE bit to 0 and set the ACKBT bit
in ICIER.
2. When ICDRR is read (dummy data read), reception is started, and the receive clock is output,
and data received, in synchronization with the internal clock. The master device outputs the
level specified by ACKBT in ICIER to SDA, at the 9th receive clock pulse.
3. After the reception of first frame data is completed, the RDRF bit in ICST is set to 1 at the rise
of 9th receive clock pulse. At this time, the receive data is read by reading ICDRR, and RDRF
is cleared to 0.
4. The continuous reception is performed by reading ICDRR every time RDRF is set. If 8th
receive clock pulse falls after reading ICDRR by the other processing while RDRF is 1, SCL is
fixed low until ICDRR is read.
5. If next frame is the last receive data, set the RCVD bit in ICCR1 and set the ACKBT bit in
ICIER. to 1 before reading ICDRR. This enables the issuance of the stop condition after the
next reception.
6. When the RDRF bit is set to 1 at rise of the 9th receive clock pulse, and clearing the STOP bit
in ICSR issue the stage condition.
7. When the STOP bit in ICSR is set to 1, read ICDRR. Then clear the RCVD bit to 0.
8. Clear the MST bit in ICCR1 and then, the operation returns to the slave receive mode.
Rev. 1.00, 07/04, page 423 of 570
TDRE
TEND
ICDRS
ICDRR
[1] Clear TDRE after clearing
TEND and TRS
[2] Read ICDRR (dummy read)
[3] Read ICDRR
1
A
2134567899
A
TRS
RDRF
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output) Bit 7
Master transmit mode Master receive mode
Bit 7Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
User
processing
Data 1
Data 1
Figure 21.7 Master Receive Mode Operation Timing (1)
RDRF
RCVD
ICDRS
ICDRR
Data n-1 Data n
Data n
Data n-1
[5] Read ICDRR after setting RCVD [6] Issue stop
condition
[7] Read ICDRR,
and clear RCVD [8] Set slave
receive mode
19 23456789
AA/A
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
User
processing
Figure 21.8 Master Receive Mode Operation Timing (2)
Rev. 1.00, 07/04, page 424 of 570
21.4.4 Slave Transmit Operation
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs
the receive clock and returns an acknowledge signal. For slave transmit mode operation timing,
refer to figures 21.9 and 21.10.
The transmission procedure and operations in slave transmit mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive
mode, and wait until the slave address matches.
2. When the slave address matches in the first frame following detection of the start condition,
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS and ICSR bits in ICCR1 are
set to 1, and the mode changes to slave transmit mode automatically. The continuous
transmission is performed by writing transmit data to ICDRT every time TDRE is set.
3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1,
with TDRE = 1. When TEND is set, clear TEND.
4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is free.
5. Clear TDRE.
TDRE
TEND
ICDRS
ICDRR
1
A
2134567899
A
TRS
ICDRT
SCL
(Master output)
Slave receive mode Slave transmit mode
SDA
(Master output)
SDA
(Slave output)
SCL
(Slave output)
Bit 7 Bit 7
Data 1
Data 1
Data 2 Data 3
Data 2
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
[2] Write data to ICDRT (data 1) [2] Write data to ICDRT (data 2) [2] Write data to ICDRT (data 3)
User
processing
Figure 21.9 Slave Transmit Mode Operation Timing (1)
Rev. 1.00, 07/04, page 425 of 570
TDRE
Data n
TEND
ICDRS
ICDRR
19 23456789
TRS
ICDRT
A
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
SCL
(Slave output)
Bit 7
Slave transmit mode
Slave receive
mode
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
A
[3] Clear TEND [5] Clear TDRE
[4] Read ICDRR (dummy read)
after clearing TRS
User
processing
Figure 21.10 Slave Transmit Mode Operation Timing (2)
21.4.5 Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. For slave receive mode operation timing, refer to
figures 21.11 and 21.12. The reception procedure and operations in slave receive mode are
described below.
1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive
mode, and wait until the slave address matches.
2. When the slave address matches in the first frame following detection of the start condition,
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the
read data show the slave address and R/W, it is not used.)
3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is
fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be
returned to the master device, is reflected to the next transmit frame.
4. The last byte data is read by reading ICDRR.
Rev. 1.00, 07/04, page 426 of 570
ICDRS
ICDRR
12 1345678 99
AA
RDRF
Data 1 Data 2
Data 1
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
SCL
(Slave output)
Bit 7 Bit 7Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
[2] Read ICDRR (dummy read) [2] Read ICDRR
User
processing
Figure 21.11 Slave Receive Mode Operation Timing (1)
ICDRS
ICDRR
12345678 99
AA
RDRF
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
SCL
(Slave output)
User
processing
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Data 1
[3] Set ACKBT [3] Read ICDRR [4] Read ICDRR
Data 2
Data 1
Figure 21.12 Slave Receive Mode Operation Timing (2)
Rev. 1.00, 07/04, page 427 of 570
21.4.6 Clocked Synchronous Serial Format
This module can be operated with the clocked synchronous serial format, by setting the FS bit in
SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When
MST is 0, the external clock input is selected.
Data Transfer Format
Figure 21.13 shows the clocked synchronous serial transfer format.
The transfer data is output from the rise to the fall of the SCL clock, and the data at the rising edge
of the SCL clock is guaranteed. The MLS bit in ICMR sets the order of data transfer, in either the
MSB first or LSB first. The output level of SDA can be changed during the transfer wait, by the
SDAO bit in ICCR2.
SDA Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
SCL
Figure 21.13 Clocked Synchronous Serial Transfer Format
Transmit Operation
In transmit mode, transmit data is output from SDA, in synchronization with the fall of the transfer
clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For
transmit mode operation timing, refer to figure 21.14. The transmission procedure and operations
in transmit mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial
setting)
2. Set the TRS bit in ICCR1 to select the transmit mode. Then, TDRE in ICSR is set.
3. Confirm that TDRE has been set. Then, write the transmit data to ICDRT. The data is
transferred from ICDRT to ICDRS, and TDRE is set automatically. The continuous
transmission is performed by writing data to ICDRT every time TDRE is set. When changing
from transmit mode to receive mode, clear TRS while TDRE is 1.
Rev. 1.00, 07/04, page 428 of 570
12 781 78 1
SCL
TRS
Bit 0
Data 1
Data 1
Data 2 Data 3
Data 2 Data 3
Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 Bit 0
Bit 1
SDA
(Output)
TDRE
ICDRT
ICDRS
User
processing
[3] Write data
to ICDRT
[3] Write data
to ICDRT
[3] Write data
to ICDRT
[3] Write data
to ICDRT
[2] Set TRS
Figure 21.14 Transmit Mode Operation Timing
Receive Operation
In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when
MST in ICCR1 is 1, and is input when MST is 0. For receive mode operation timing, refer to
figure 21.15. The reception procedure and operations in receive mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial
setting)
2. When the transfer clock is output, set MST to 1 to start outputting the receive clock.
3. When the receive operation is completed, data is transferred from ICDRS to ICDRR and
RDRF in ICSR is set. When MST = 1, the next byte can be received, so the clock is
continually output. The continuous reception is performed by reading ICDRR every time
RDRF is set. When the 8th clock is risen while RDRF is 1, the overrun is detected and
AL/OVE in ICSR is set. At this time, the previous reception data is retained in ICDRR.
4. To stop receiving when MST = 1, set RCVD in ICCR1 to 1, then read ICDRR. Then, SCL is
fixed high after receiving the next byte data.
Rev. 1.00, 07/04, page 429 of 570
12 781 7812
SCL
MST
TRS
RDRF
ICDRS
ICDRR
SDA
(Input) Bit 0 Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 Bit 0
Bit 1
User
processing
Data 1
Data 1
Data 2
Data 2
Data 3
[2] Set MST
(when outputting the clock) [3] Read ICDRR [3] Read ICDRR
Figure 21.15 Receive Mode Operation Timing
21.4.7 Noise Canceler
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 21.16 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
C
QD
Match detector
Internal
SCL or SDA
signal
SCL or SDA
input signal
Sampling
clock
Sampling clock
System clock
period
Latch Latch
C
Q
D
Figure 21.16 Block Diagram of Noise Conceler
Rev. 1.00, 07/04, page 430 of 570
21.4.8 Example of Use
Flowcharts in respective modes that use the I2C bus interface are shown in figures 21.17 to 21.20.
BBSY=0 ?
No
TEND=1 ?
No
Yes
Start
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[13]
[14]
[15]
Initialize
Set MST and TRS
in ICCR1 to 1.
Write 1 to BBSY
and 0 to SCP.
Write transmit data
in ICDRT
Write 0 to BBSY
and SCP
Set MST to 1 and TRS
to 0 in ICCR1
Read BBSY in ICCR2
Read TEND in ICSR
Read ACKBR in ICIER
Mater receive mode
Yes
ACKBR=0 ?
Write transmit data in ICDRT
Read TDRE in ICSR
Read TEND in ICSR
Clear TEND in ICSR
Read STOP in ICSR
Clear TDRE in ICSR
End
Write transmit data in ICDRT
Transmit
mode?
No
Yes
TDRE=1 ?
Last byte?
STOP=1 ?
No
No
No
No
No
Yes
Yes
TEND=1 ?
Yes
Yes
Yes
[1] Test the status of the SCL and SDA lines.
[2] Set master transmit mode.
[3] Issue the start candition.
[4] Set the first byte (slave address + R/W) of transmit data.
[5] Wait for 1 byte to be transmitted.
[6] Test the acknowledge transferred from the specified slave device.
[7] Set the second and subsequent bytes (except for the final byte) of transmit data.
[8] Wait for ICDRT empty.
[9] Set the last byte of transmit data.
[10] Wait for last byte to be transmitted.
[11] Clear the TEND flag.
[12] Clear the STOP flag.
[13] Issue the stop condition.
[14] Wait for the creation of stop condition.
[15] Set slave receive mode. Clear TDRE.
[12]
Clear STOP in ICSR
Figure 21.17 Sample Flowchart for Master Transmit Mode
Rev. 1.00, 07/04, page 431 of 570
No
Yes
RDRF=1 ?
No
Yes
RDRF=1 ?
Last receive
- 1?
Mater receive mode
Clear TEND in ICSR
Clear TRS in ICCR1 to 0
Clear TDRE in ICSR
Clear ACKBT in ICIER to 0
Dummy-read ICDRR
Read RDRF in ICSR
Read ICDRR
Set ACKBT in ICIER to 1
Set RCVD in ICCR1 to 1
Read ICDRR
Read RDRF in ICSR
Write 0 to BBSY
and SCP
Read STOP in ICSR
Read ICDRR
Clear RCVD in ICCR1 to 0
Clear MST in ICCR1 to 0
Note: * Do not activate an interrupt during the execution of steps [1] to [3].
End
No
Yes
STOP=1 ?
No
Yes
[1] Clear TEND, select master receive mode, and then clear TDRE.*
[2] Set acknowledge to the transmit device.*
[3] Dummy-read ICDDR.*
[4] Wait for 1 byte to be received
[5] Check whether it is the (last receive - 1).
[6] Read the receive data.
[7] Set acknowledge of the final byte. Disable continuous reception (RCVD = 1).
[8] Read the (final byte - 1) of receive data.
[9] Wait for the last byte to be receive.
[10] Clear the STOP flag.
[11] Issue the stop condition.
[12] Wait for the creation of stop condition.
[13] Read the last byte of receive data.
[14] Clear RCVD.
[15] Set slave receive mode.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[11]
[12]
[13]
Clear STOP in ICSR.
[10]
[14]
[15]
Figure 21.18 Sample Flowchart for Master Receive Mode
Rev. 1.00, 07/04, page 432 of 570
TDRE=1 ?
Yes
Yes
No
Slave transmit mode
Clear AAS in ICSR
Write transmit data
in ICDRT
Read TDRE in ICSR
Last
byte?
Write transmit data
in ICDRT
Read TEND in ICSR
Clear TEND in ICSR
Clear TRS in ICCR1 to 0
Dummy read ICDRR
Clear TDRE in ICSR
End
[1] Clear the AAS flag.
[2] Set transmit data for ICDRT (except for the last data).
[3] Wait for ICDRT empty.
[4] Set the last byte of transmit data.
[5] Wait for the last byte to be transmitted.
[6] Clear the TEND flag .
[7] Set slave receive mode.
[8] Dummy-read ICDRR to release the SCL line.
[9] Clear the TDRE flag.
No
No
Yes
TEND=1 ?
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
Figure 21.19 Sample Flowchart for Slave Transmit Mode
Rev. 1.00, 07/04, page 433 of 570
No
Yes
RDRF=1 ?
No
Yes
RDRF=1 ?
Last receive
- 1?
Slave receive mode
Clear AAS in ICSR
Clear ACKBT in ICIER to 0
Dummy-read ICDRR
Read RDRF in ICSR
Read ICDRR
Set ACKBT in ICIER to 1
Read ICDRR
Read RDRF in ICSR
Read ICDRR
End
No
Yes
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[1] Clear the AAS flag.
[2] Set acknowledge to the transmit device.
[3] Dummy-read ICDRR.
[4] Wait for 1 byte to be received.
[5] Check whether it is the (last receive - 1).
[6] Read the receive data.
[7] Set acknowledge of the last byte.
[8] Read the (last byte - 1) of receive data.
[9] Wait the last byte to be received.
[10] Read for the last byte of receive data.
Figure 21.20 Sample Flowchart for Slave Receive Mode
Rev. 1.00, 07/04, page 434 of 570
21.5 Interrupt Request
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,
NACK receive, STOP recognition, and arbitration lost/overrun. Table 21.3 shows the contents of
each interrupt request.
Table 21.3 Interrupt Requests
Interrupt Request
Abbreviation
Interrupt Condition
I2C Mode
Clocked
Synchronous
Mode
Transmit Data Empty TXI (TDRE=1) • (TIE=1) ! !
Transmit End TEI (TEND=1)
• (TEIE=1) ! !
Receive Data Full RXI (RDRF=1)
• (RIE=1) ! !
STOP Recognition STPI (STOP=1)
• (STIE=1) ! ×
NACK Receive ! ×
Arbitration
Lost/Overrun
NAKI {(NACKF=1)+(AL=1)}
•
(NAKIE=1) ! !
When interrupt conditions described in table 21.3 are 1 and the I bit in CCR is 0, the CPU
executes interrupt exception processing. Interrupt sources should be cleared in the exception
processing. TDRE and TEND are automatically cleared to 0 by writing the transmit data to
ICDRT. RDRF are automatically cleared to 0 by reading ICDRR. TDRE is set to 1 again at the
same time when transmit data is written to ICDRT. When TDRE is cleared to 0, then an excessive
data of one byte may be transmitted.
Rev. 1.00, 07/04, page 435 of 570
21.6 Bit Synchronous Circuit
In master mode,this module has a possibility that high level period may be short in the two states
described below.
• When SCL is driven to low by the slave device
• When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pull-
up resistance)
Therefore, it monitors SCL and communicates by bit with synchronization.
Figure 21.21 shows the timing of the bit synchronous circuit and table 21.4 shows the time when
SCL output changes from low to Hi-Z then SCL is monitored.
SCL V
IH
SCL monitor
timing reference
clock
Internal SCL
Figure 21.21 Timing of Bit Synchronous Circuit
Table 21.4 Time for Monitoring SCL
CKS3 CKS2 Time for Monitoring SCL
0 7.5 tcyc 0
1 19.5 tcyc
0 17.5 tcyc 1
1 41.5 tcyc
Rev. 1.00, 07/04, page 436 of 570
PSCKT11A_000120040500 Rev. 1.00, 07/04, page 437 of 570
Section 22 Power-On Reset Circuit
This LSI has an on-chip power-on reset circuit. A block diagram of the power-on reset circuit is
shown in figure 22.1.
22.1 Feature
• Power-on reset circuit
An internal reset signal is generated at turning the power on by externally connecting a
capacitor.
Voltage
detector
(Recommended) R
(100 kΩ)
Vcc
System
clock Divider 3-bit
counter Internal reset signal
RES
CRES
Figure 22.1 Power-On Reset Circuit
Rev. 1.00, 07/04, page 438 of 570
22.2 Operation
22.2.1 Power-On Reset Circuit
The operation timing of the power-on reset circuit is shown in figure 22.2. As the power supply
voltage rises, the capacitor, which is externally connected to the RES pin, is gradually charged
through the on-chip pull-up resistor (100 kΩ). The low level of the RES pin is sent to the chip and
the whole chip is reset. When the level of the RES pin reaches to the predetermined level, a
voltage detection circuit detects it. Then a 3-bit counter starts counting up. When the 3-bit counter
counts φ for 8 times, an overflow signal is generated and an internal reset signal is cleared.
The noise cancellation circuit of approximately 100 ns is incorporated to prevent the incorrect
operation of the chip by noise on the RES pin.
The capacitance (CRES) which is connected to the RES pin can be computed using the following
formula; where the power supply rise time (t_vtr) = 5 ms, the RES rise time (t_vtr x 2) = 10 ms,
and the on-chip resistor = 10 kΩ. For details, refer to section 25, Electrical Characteristics.
10ms
C = = 0.1µF
100kΩ
Note that the power supply voltage (Vcc) must fall below Vpor = 100 mV and rise after charge on
the RES pin is removed. To remove charge on the RES pin, it is recommended that the diode
should be placed near Vcc. If the power supply voltage (Vcc) rises from the point above Vpor, a
power-on reset may not occur.
Vcc
t_vtr
t_vtr × 2
V_rst
t_cr t_out (eight states)
RES
Internal reset
signal
Figure 22.2 Power-On Reset Circuit Operation Timing
ABK0002A_000020030700 Rev. 1.00, 07/04, page 439 of 570
Section 23 Address Break
The address break simplifies on-board program debugging. It requests an address break interrupt
when the set break condition is satisfied. The interrupt request is not affected by the I bit in CCR.
Break conditions that can be set include instruction execution at a specific address and a
combination of access and data at a specific address. With the address break function, the
execution start point of a program containing a bug is detected and execution is branched to the
correcting program. Use of module standby mode enables this module to be placed in standby
mode independently when not used. (For details, refer to section 6.4, Module Standby Function.)
Figure 23.1 shows a block diagram of the address break.
BAR2H BAR2L
BDR2H BDR2L
ABRKCR2
ABRKSR2
Internal address bus
Comparator
Interrupt
generation
control circuit
Internal data bus
Comparator
Interrupt
[Legend]
BAR2H, BAR2L: Break address register 2
BDR2H, BDR2L: Break data register 2
ABRKCR2: Address break control register 2
ABRKSR2: Address break status register 2
Figure 23.1 Block Diagram of Address Break
23.1 Register Descriptions
The address break has the following registers.
• Address break control register 2 (ABRKCR2)
• Address break status register 2 (ABRKSR2)
• Break address register 2 (BAR2H, BAR2L)
• Break data register 2 (BDR2H, BDR2L)
Rev. 1.00, 07/04, page 440 of 570
23.1.1 Address Break Control Register 2 (ABRKCR2)
ABRKCR2 sets address break conditions.
Bit Bit Name
Initial
Value R/W Description
7 RTINTE2 1 R/W RTE Interrupt Enable
When this bit is 0, the interrupt immediately after
executing RTE is masked and then one instruction must
be executed. When this bit is 1, the interrupt is not
masked.
6
5
CSEL21
CSEL20
0
0
R/W
R/W
Condition Select 1 and 0
These bits set address break conditions.
00: Instruction execution cycle (no data comparison)
01: CPU data read cycle
10: CPU data write cycle
11: CPU data read/write cycle
4
3
2
ACMP22
ACMP21
ACMP20
0
0
0
R/W
R/W
R/W
Address Compare Condition Select 2 to 0
These bits set the comparison condition between the
address set in BAR2 and the internal address bus.
000: Compares 16-bit addresses
001: Compares upper 12-bit addresses
010: Compares upper 8-bit addresses
011: Compares upper 4-bit addresses
1xx: Setting prohibited
1
0
DCMP21
DCMP20
0
0
R/W
R/W
Data Compare Condition Select 1 and 0
These bits set the comparison condition between the
data set in BDR2 and the internal data bus.
00: No data comparison
01: Compares lower 8-bit data between BDR2L and
data bus
10: Compares upper 8-bit data between BDR2H and
data bus
11: Compares 16-bit data between BDR2 and data bus
[Legend] x: Don't care.
Rev. 1.00, 07/04, page 441 of 570
When an address break is set in the data read cycle or data write cycle, the data bus used will
depend on the combination of the byte/word access and address. Table 23.1 shows the access and
data bus used. When an I/O register space with an 8-bit data bus width is accessed in word size, a
byte access is generated twice. For details on data widths of each register, see section 24.1,
Register Addresses (Address Order).
Table 23.1 Access and Data Bus Used
Word Access Byte Access
Even Address Odd Address Even Address Odd Address
ROM space Upper 8 bits Lower 8 bits Upper 8 bits Upper 8 bits
RAM space Upper 8 bits Lower 8 bits Upper 8 bits Upper 8 bits
I/O register with
8-bit data bus width
Upper 8 bits Upper 8 bits Upper 8 bits Upper 8 bits
I/O register with
16-bit data bus width*1
Upper 8 bits Lower 8 bits — —
I/O register with
16-bit data bus width*2
Upper 8 bits Lower 8 bits Upper 8 bits Upper 8 bits
Notes: 1. Registers whose addresses do not range from H'FF96 and H'FF97, and H'FFB8 to
H'FFBB with 16-bit data bus width.
2. Registers whose addresses range from H'FF96 and H'FF97, and H'FFB8 to H'FFBB.
23.1.2 Address Break Status Register 2 (ABRKSR2)
ABRKSR2 consists of the address break interrupt flag and the address break interrupt enable bit.
Bit Bit Name
Initial
Value R/W Description
7 ABIF2 0 R/W Address Break Interrupt Flag
[Setting condition]
When the condition set in ABRKCR2 is satisfied
[Clearing condition]
When 0 is written after ABIF=1 is read
6 ABIE2 0 R/W Address Break Interrupt Enable
When this bit is 1, an address break interrupt request is
enabled.
5 to 0 — All 1 — Reserved
These bits are always read as 1.
Rev. 1.00, 07/04, page 442 of 570
23.1.3 Break Address Registers 2 (BAR2H, BAR2L)
BAR2H and BAR2L are 16-bit read/write registers that set the address for generating an address
break interrupt. When setting the address break condition to the instruction execution cycle, set the
first byte address of the instruction. The initial value of this register is H'FFFF.
23.1.4 Break Data Registers 2 (BDR2H, BDR2L)
BDR2H and BDR2L are 16-bit read/write registers that set the data for generating an address
break interrupt. BDR2H is compared with the upper 8-bit data bus. BDR2L is compared with the
lower 8-bit data bus. When memory or registers are accessed by byte, the upper 8-bit data bus is
used for even and odd addresses in the data transmission. Therefore, comparison data must be set
in BDR2H for byte access. For word access, the data bus used depends on the address. See section
23.1.1, Address Break Control Register 2 (ABRKCR2), for details. The initial value of this
register is undefined.
23.2 Operation
When the ABIF2 and ABIE2 bits in ABRKSR2 are set to 1, the address break function generates
an interrupt request to the CPU. The ABIF2 bit in ABRKSR2 is set to 1 by the combination of the
address set in BAR2, the data set in BDR2, and the conditions set in ABRKCR2. When the
interrupt request is accepted, interrupt exception handling starts after the instruction being
executed ends. The address break interrupt is not masked by the I bit in CCR of the CPU.
Rev. 1.00, 07/04, page 443 of 570
Figures 23.2 show the operation examples of the address break interrupt setting.
NOP
instruc-
tion
prefetch
Register setting
• ABRKCR2 = H'80
• BAR2 = H'025A
Program
0258
025A
025C
0260
0262
:
*
NOP
NOP
MOV.W @H'025A,R0
NOP
NOP
:
0258
Address
bus
φ
Interrupt
request
025A 025C 025E SP-2 SP-4
NOP
instruc-
tion
prefetch
MOV
instruc-
tion 1
prefetch
MOV
instruc-
tion 2
prefetch
Internal
processing Stack save
Interrupt acceptance
Underline indicates the address
to be stacked.
When the address break is specified in instruction execution cycle
Figure 23.2 Address Break Interrupt Operation Example (1)
MOV
instruc-
tion 1
prefetch
Register setting
• ABRKCR2 = H'A0
• BAR2 = H'025A
Program
0258
025A
025C
0260
0262
:
*
NOP
NOP
MOV.W @H'025A,R0
NOP
NOP
:
025C
Address
bus
φ
Interrupt
request
025E 0260 025A 0262 0264 SP-2
MOV
instruc-
tion 2
prefetch
NOP
instruc-
tion
prefetch
MOV
instruc-
tion
execution
Next
instru-
ction
prefetch
Internal
processing
Stack
save
NOP
instruc-
tion
prefetch
Interrupt acceptance
Underline indicates the address
to be stacked.
When the address break is specified in the data read cycle
Figure 23.2 Address Break Interrupt Operation Example (2)
Rev. 1.00, 07/04, page 444 of 570
23.3 Operating States of Address Break
The operating states of the address break are shown in table 23.2.
Table 23.2 Operating States of Address Break
Operating
Mode
Reset
Active
Sleep
Watch Sub-
active Sub-sleep
Standby Module
Standby
ABRKCR2 Reset Functions Retained Retained Functions Retained Retained Retained
ABRKSR2 Reset Functions Retained Retained Functions Retained Retained Retained
BAR2H Reset Functions Retained Retained Functions Retained Retained Retained
BAR2L Reset Functions Retained Retained Functions Retained Retained Retained
BDR2H Retained* Functions Retained Retained Functions Retained Retained Retained
BDR2L Retained* Functions Retained Retained Functions Retained Retained Retained
Note: * Undefined at a power-on reset
Rev. 1.00, 07/04, page 445 of 570
Section 24 List of Registers
The register list gives information on the on-chip I/O register addresses, how the register bits are
configured, and the register states in each operating mode. The information is given as shown
below.
1. Register addresses (address order)
• Registers are listed from the lower allocation addresses.
• Registers are classified by functional modules.
• The data bus width is indicated.
• The number of access states is indicated.
2. Register bits
• Bit configurations of the registers are described in the same order as the register addresses.
• Reserved bits are indicated by in the bit name column.
• When registers consist of 16 bits, bits are described from the MSB side.
3. Register states in each operating mode
• Register states are described in the same order as the register addresses.
• The register states described here are for the basic operating modes. If there is a specific reset
for an on-chip peripheral module, refer to the section on that on-chip peripheral module.
Rev. 1.00, 07/04, page 446 of 570
24.1 Register Addresses (Address Order)
The data bus width indicates the number of bits by which the register is accessed.
The number of access states indicates the number of states based on the specified reference clock.
Register Name
Abbre-
viation
Bit No.
Address
Module
Name
Data
Bus
Width
Access
State
Serial control register 4 SCR4 8 H'F00C SCI4 8 2
Serial control/status register 4 SCSR4 8 H'F00D SCI4 8 2
Transmit data register 4 TDR4 8 H'F00E SCI4 8 2
Receive data register 4 RDR4 8 H'F00F SCI4 8 2
Flash memory control register 1 FLMCR1 8 H'F020 ROM 8 2
Flash memory control register 2 FLMCR2 8 H'F021 ROM 8 2
Flash memory power control register FLPWCR 8 H'F022 ROM 8 2
Erase block register1 EBR1 8 H'F023 ROM 8 2
Flash memory enable register FENR 8 H'F02B ROM 8 2
Timer start register TSTR 8 H'F030 TPU 8 2
Timer synchro register TSYR 8 H'F031 TPU 8 2
Timer control register_1 TCR_1 8 H'F040 TPU_1 8 2
Timer mode register_1 TMDR_1 8 H'F041 TPU_1 8 2
Timer I/O control register_1 TIOR_1 8 H'F042 TPU_1 8 2
Timer interrupt enable register_1 TIER_1 8 H'F044 TPU_1 8 2
Timer status register_1 TSR_1 8 H'F045 TPU_1 8 2
Timer counter_1 TCNT_1 16 H'F046 TPU_1 16 2
Timer general register A_1 TGRA_1 16 H'F048 TPU_1 16 2
Timer general register B_1 TGRB_1 16 H'F04A TPU_1 16 2
Timer control register_2 TCR_2 8 H'F050 TPU_2 8 2
Timer mode register_2 TMDR_2 8 H'F051 TPU_2 8 2
Timer I/O control register_2 TIOR_2 8 H'F052 TPU_2 8 2
Timer interrupt enable register_2 TIER_2 8 H'F054 TPU_2 8 2
Timer status register_2 TSR_2 8 H'F055 TPU_2 8 2
Timer counter_2 TCNT_2 16 H'F056 TPU_2 16 2
Timer general register A_2 TGRA_2 16 H'F058 TPU_2 16 2
Timer general register B_2 TGRB_2 16 H'F05A TPU_2 16 2
Rev. 1.00, 07/04, page 447 of 570
Register Name
Abbre-
viation
Bit No.
Address
Module
Name
Data
Bus
Width
Access
State
A/D control register ADCR 8 H'F060 ∆Σ A/D
converter
8 2
A/D start/status register ADSSR 8 H'F061 ∆Σ A/D
converter
8 2
A/D data register ADDR 16 H'F062 ∆Σ A/D
converter
16 2
RTC interrupt flag register RTCFLG 8 H'F067 RTC 8 2
Second data register/free running
counter data register
RSECDR 8 H'F068 RTC 8 2
Minute data register RMINDR 8 H'F069 RTC 8 2
Hour data register RHRDR 8 H'F06A RTC 8 2
Day-of-week data register RWKDR 8 H'F06B RTC 8 2
RTC control register 1 RTCCR1 8 H'F06C RTC 8 2
RTC control register 2 RTCCR2 8 H'F06D RTC 8 2
SUB32k control register SUB32CR 8 H'F06E Clock pulse
generator
8 2
Clock source select register RTCCSR 8 H'F06F RTC 8 2
I2C bus control register 1 ICCR1 8 H'F078 IIC2 8 2
I2C bus control register 2 ICCR2 8 H'F079 IIC2 8 2
I2C bus mode register ICMR 8 H'F07A IIC2 8 2
I2C bus interrupt enable register ICIER 8 H'F07B IIC2 8 2
I2C bus status register ICSR 8 H'F07C IIC2 8 2
Slave address register SAR 8 H'F07D IIC2 8 2
I2C bus transmit data register ICDRT 8 H'F07E IIC2 8 2
I2C bus receive data register ICDRR 8 H'F07F IIC2 8 2
Interrupt priority register A IPRA 8 H'F080 Interrupts 8 2
Interrupt priority register B IPRB 8 H'F081 Interrupts 8 2
Interrupt priority register C IPRC 8 H'F082 Interrupts 8 2
Interrupt priority register D IPRD 8 H'F083 Interrupts 8 2
Interrupt priority register E IPRE 8 H'F084 Interrupts 8 2
Address break control register 2 ABRKCR2 8 H'F096 Address break 8 2
Address break status register 2 ABRKSR2 8 H'F097 Address break 8 2
Break address register 2H BAR2H 8 H'F098 Address break 8 2
Break address register 2L BAR2L 8 H'F099 Address break 8 2
Rev. 1.00, 07/04, page 448 of 570
Register Name
Abbre-
viation
Bit No.
Address
Module
Name
Data
Bus
Width
Access
State
Break data register 2H BDR2H 8 H'F09A Address break 8 2
Break data register 2L BDR2L 8 H'F09B Address break 8 2
Event counter PWM compare
register
ECPWCR 16 H'FF8C AEC*1 16 2
Event counter PWM data register ECPWDR 16 H'FF8E AEC*1 16 2
Wakeup edge select register WEGR 8 H'FF90 Interrupts 8 2
Serial port control register SPCR 8 H'FF91 SCI3 8 2
Input pin edge select register AEGSR 8 H'FF92 AEC*1 8 2
Event counter control register ECCR 8 H'FF94 AEC*1 8 2
Event counter control/status register ECCSR 8 H'FF95 AEC*1 8 2
Event counter H ECH 8 H'FF96 AEC*1 8 2
Event counter L ECL 8 H'FF97 AEC*1 8 2
Serial mode register 3_1 SMR3_1 8 H'FF98 SCI3_1 8 3
Bit rate register 3_1 BRR3_1 8 H'FF99 SCI3_1 8 3
Serial control register 3_1 SCR3_1 8 H'FF9A SCI3_1 8 3
Transmit data register 3_1 TDR3_1 8 H'FF9B SCI3_1 8 3
Serial status register 3_1 SSR3_1 8 H'FF9C SCI3_1 8 3
Receive data register 3_1 RDR3_1 8 H'FF9D SCI3_1 8 3
LCD port control register LPCR 8 H'FFA0 LCD*3 8 2
LCD control register LCR 8 H'FFA1 LCD*3 8 2
LCD control register 2 LCR2 8 H'FFA2 LCD*3 8 2
LCD trimming register LTRMR 8 H'FFA3 LCD*3 8 2
BGR control register BGRMR 8 H'FFA4 LCD*3 8 2
IrDA control register IrCR 8 H'FFA7 IrDA 8 3
Serial mode register 3_2 SMR3_2 8 H'FFA8 SCI3_2 8 3
Bit rate register 3_2 BRR3_2 8 H'FFA9 SCI3_2 8 3
Serial control register 3_2 SCR3_2 8 H'FFAA SCI3_2 8 3
Transmit data register 3_2 TDR3_2 8 H'FFAB SCI3_2 8 3
Serial status register 3_2 SSR3_2 8 H'FFAC SCI3_2 8 3
Receive data register 3_2 RDR3_2 8 H'FFAD SCI3_2 8 3
Timer mode register WD TMWD 8 H'FFB0 WDT*2 8 2
Timer control/status register WD1 TCSRWD1 8 H'FFB1 WDT*2 8 2
Timer control/status register WD2 TCSRWD2 8 H'FFB2 WDT*2 8 2
Rev. 1.00, 07/04, page 449 of 570
Register Name
Abbre-
viation
Bit No.
Address
Module
Name
Data
Bus
Width
Access
State
Timer counter WD TCWD 8 H'FFB3 WDT*2 8 2
Timer control register F TCRF 8 H'FFB6 Timer F 8 2
Timer control/status register F TCSRF 8 H'FFB7 Timer F 8 2
8-bit timer counter FH TCFHH 8 H'FFB8 Timer F 8 2
8-bit timer counter FL TCFL 8 H'FFB9 Timer F 8 2
Output compare register FH OCRFH 8 H'FFBA Timer F 8 2
Output compare register FL OCRFL 8 H'FFBB Timer F 8 2
A/D result register ADRR 16 H'FFBC A/D converter 16 2
A/D mode register AMR 8 H'FFBE A/D converter 8 2
A/D start register ADSR 8 H'FFBF A/D converter 8 2
Port mode register 1 PMR1 8 H'FFC0 I/O ports 8 2
Oscillator Control Register OSCCR 8 H'FFC1 Clock pulse
generator
8 2
Port mode register 3 PMR3 8 H'FFC2 I/O ports 8 2
Port mode register 4 PMR4 8 H'FFC3 I/O ports 8 2
Port mode register 5 PMR5 8 H'FFC4 I/O ports 8 2
Port mode register 9 PMR9 8 H'FFC8 I/O ports 8 2
Port mode register B PMRB 8 H'FFCA I/O ports 8 2
PWM2 control register PWCR22 8 H'FFCD 14-bit PWM 8 2
PWM2 data register PWDR2 16 H'FFCE 14-bit PWM 16 2
PWM1 control register PWCR1 8 H'FFD0 14-bit PWM 8 2
PWM1 data register PWDR1 16 H'FFD2 14-bit PWM 16 2
Port data register 1 PDR1 8 H'FFD4 I/O ports 8 2
Port data register 3 PDR3 8 H'FFD6 I/O ports 8 2
Port data register 4 PDR4 8 H'FFD7 I/O ports 8 2
Port data register 5 PDR5 8 H'FFD8 I/O ports 8 2
Port data register 6 PDR6 8 H'FFD9 I/O ports 8 2
Port data register 7 PDR7 8 H'FFDA I/O ports 8 2
Port data register 8 PDR8 8 H'FFDB I/O ports 8 2
Port data register 9 PDR9 8 H'FFDC I/O ports 8 2
Port data register A PDRA 8 H'FFDD I/O ports 8 2
Port data register B PDRB 8 H'FFDE I/O ports 8 2
Port pull-up control register 1 PUCR1 8 H'FFE0 I/O ports 8 2
Rev. 1.00, 07/04, page 450 of 570
Register Name
Abbre-
viation
Bit No.
Address
Module
Name
Data
Bus
Width
Access
State
Port pull-up control register 3 PUCR3 8 H'FFE1 I/O ports 8 2
Port pull-up control register 5 PUCR5 8 H'FFE2 I/O ports 8 2
Port pull-up control register 6 PUCR6 8 H'FFE3 I/O ports 8 2
Port control register 1 PCR1 8 H'FFE4 I/O ports 8 2
Port control register 3 PCR3 8 H'FFE6 I/O ports 8 2
Port control register 4 PCR4 8 H'FFE7 I/O ports 8 2
Port control register 5 PCR5 8 H'FFE8 I/O ports 8 2
Port control register 6 PCR6 8 H'FFE9 I/O ports 8 2
Port control register 7 PCR7 8 H'FFEA I/O ports 8 2
Port control register 8 PCR8 8 H'FFEB I/O ports 8 2
Port control register 9 PCR9 8 H'FFEC I/O ports 8 2
Port control register A PCRA 8 H'FFED I/O ports 8 2
System control register 1 SYSCR1 8 H'FFF0 System 8 2
System control register 2 SYSCR2 8 H'FFF1 System 8 2
IRQ edge select register IEGR 8 H'FFF2 Interrupts 8 2
Interrupt enable register 1 IENR1 8 H'FFF3 Interrupts 8 2
Interrupt enable register 2 IENR2 8 H'FFF4 Interrupts 8 2
Interrupt mask register INTM 8 H'FFF5 Interrupts 8 2
Interrupt request register 1 IRR1 8 H'FFF6 Interrupts 8 2
Interrupt request register 2 IRR2 8 H'FFF7 Interrupts 8 2
Wakeup interrupt request register IWPR 8 H'FFF9 Interrupts 8 2
Clock stop register 1 CKSTPR1 8 H'FFFA System 8 2
Clock stop register 2 CKSTPR2 8 H'FFFB System 8 2
Notes: 1. AEC: Asynchronous event counter
2. WDT: Watchdog timer
3. LCD: LCD controller/driver
Rev. 1.00, 07/04, page 451 of 570
24.2 Register Bits
Register bit names of the on-chip peripheral modules are described below.
Register
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 Module
Name
SCR4 TIE RIE TEIE SOL SOLP SRES TE RE
SCSR4 TDRE RDRF ORER TEND CKS3 CKS2 CKS1 CKS0
TDR4 TDR47 TDR46 TDR45 TDR44 TDR43 TDR42 TDR41 TDR40
RDR4 RDR47 RDR46 RDR45 RDR44 RDR43 RDR42 RDR41 RDR40
SCI4
FLMCR1 SWE ESU PSU EV PV E P
FLMCR2 FLER
FLPWCR PDWND
EBR1 EB6 EB5 EB4 EB3 EB2 EB1 EB0
FENR FLSHE
ROM
TSTR CST2 CST1
TSYR SYNC2 SYNC1
TPU
TCR_1 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
TMDR_1 MD1 MD0
TIOR_1 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0
TIER_1 TCIEV TGIEB TGIEA
TSR_1_ TCFV TGFB TGFA
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TCNT_1
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TGRA_1
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TGRB_1
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TPU_1
TCR_2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
TMDR_2 MD1 MD0
TIOR_2 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0
TIER_2 TCIEV TGIEB TGIEA
TSR_2 TCFV TGFB TGFA
TPU_2
Rev. 1.00, 07/04, page 452 of 570
Register
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 Module
Name
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
TCNT_2
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TGRA_2
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TGRB_2
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TPU_2
ADCR MOD OVS2 OVS1 OVS0 VREF1 VREF0 PGA1 PGA0
ADSSR ADS ADST AIN1 AIN0 BYPGA
ADD13 ADD12 ADD11 ADD10 ADD9 ADD8 ADD7 ADD6 ADDR
ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
∆Σ A/D
converter
RTCFLG FOIFG WKIFG DYIFG HRIFG MNIFG SEIFG 05SEIFG 025SEIFG
RSECDR BSY SC12 SC11 SC10 SC03 SC02 SC01 SC00
RMINDR BSY MN12 MN11 MN10 MN03 MN02 MN01 MN00
RHRDR BSY HR11 HR10 HR03 HR02 HR01 HR00
RWKDR BSY WK2 WK1 WK0
RTCCR1 RUN 12/24 PM RST
RTCCR2 FOIE WKIE DYIE HRIE MNIE 1SEIE 05SEIE 025SEIE
RTC
SUB32CR 32KSTOP Clock pulse
generator
RTCCSR RCS6 RCS5 SUB32K RCS3 RCS2 RCS1 RCS0 RTC
ICCR1 ICE RCVD MST TRS CKS3 CKS2 CKS1 CKS0
ICCR2 BBSY SCP SDAO SDAOP SCLO IICRST
ICMR MLS WAIT BCWP BC2 BC1 BC0
ICIER TIE TEIE RIE NAKIE STIE ACKE ACKBR ACKBT
ICSR TDRE TEND RDRF NACKF STOP AL/OVE AAS ADZ
SAR SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS
ICDRT ICDRT7 ICDRT6 ICDRT5 ICDRT4 ICDRT3 ICDRT2 ICDRT1 ICDRT0
ICDRR ICDRR7 ICDRR6 ICDRR5 ICDRR4 ICDRR3 ICDRR2 ICDRR1 ICDRR0
IIC2
A IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0
IPRB IPRB7 IPRB6 IPRB5 IPRB4 IPRB3 IPRB2 IPRB1 IPRB0
IPRC IPRC7 IPRC6 IPRC5 IPRC4 IPRC3 IPRC2 IPRC1 IPRC0
IPRD IPRD7 IPRD6 IPRD5 IPRD4 IPRD3 IPRD2 IPRD1 IPRD0
IPRE IPRE7 IPRE6 IPRE5 IPRE4
Interrupts
Rev. 1.00, 07/04, page 453 of 570
Register
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 Module
Name
ABRKCR2 RTINTE2 CSEL21 CSEL20 ACMP22 ACMP21 ACMP20 DCMP21 DCMP20
ABRKSR2 ABIF2 ABIE2
BAR2H BARH27 BARH26 BARH25 BARH24 BARH23 BARH22 BARH21 BARH20
BAR2L BARL27 BARL26 BARL25 BARL24 BARL23 BARL22 BARL21 BARL20
BDR2H BDRH27 BDRH26 BDRH25 BDRH24 BDRH23 BDRH22 BDRH21 BDRH20
BDR2L BDRL27 BDRL26 BDRL25 BDRL24 BDRL23 BDRL22 BDRL21 BDRL20
Address
break
ECPWCR ECPWCR15 ECPWCR14 ECPWCR13 ECPWCR12 ECPWCR11 ECPWCR10 ECPWCR9 ECPWCR8
ECPWCR7 ECPWCR6 ECPWCR5 ECPWCR4 ECPWCR3 ECPWCR2 ECPWCR1 ECPWCR0
ECPWDR ECPWDR15 ECPWDR14 ECPWDR13 ECPWDR12 ECPWDR11 ECPWDR10 ECPWDR9 ECPWDR8
ECPWDR7 ECPWDR6 ECPWDR5 ECPWDR4 ECPWDR3 ECPWDR2 ECPWDR1 ECPWDR0
AEC*1
WEGR WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0 Interrupts
SPCR SPC32 SPC31 SCINV3 SCINV2 SCINV1 SCINV0 SCI3
AEGSR AHEGS1 AHEGS0 ALEGS1 ALEGS0 AIEGS1 AIEGS0 ECPWME
ECCR ACKH1 ACKH0 ACKL1 ACKL0 PWCK2 PWCK1 PWCK0
ECCSR OVH OVL CH2 CUEH CUEL CRCH CRCL
ECH ECH7 ECH6 ECH5 ECH4 ECH3 ECH2 ECH1 ECH0
ECL ECL7 ECL6 ECL5 ECL4 ECL3 ECL2 ECL1 ECL0
AEC*1
SMR3_1 COM CHR PE PM STOP MP CKS1 CKS0
BRR3_1 BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0
SCR3_1 TIE RIE TE RE MPIE TEIE CKE1 CKE0
TDR3_1 TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0
SSR3_1 TDRE RDRF OER FER PER TEND MPBR MPBT
RDR3_1 RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0
SCI3_1
LPCR DTS1 DTS0 CMX SGS3 SGS2 SGS1 SGS0
LCR PSW ACT DISP CKS3 CKS2 CKS1 CKS0
LCR2 LCDAB HCKS CHG SUPS
LTRMR TRM3 TRM2 TRM1 TRM0 CTRM2 CTRM1 CTRM0
BGRMR BGRSTPN BTRM2 BTRM1 BTRM0
LCD*3
IrCR IrE IrCKS2 IrCKS1 IrCKS0 IrDA
Rev. 1.00, 07/04, page 454 of 570
Register
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 Module
Name
SMR3_2 COM32 CHR32 PE32 PM32 STOP32 MP32 CKS321 CKS320
BRR3_2 BRR327 BRR326 BRR325 BRR324 BRR323 BRR322 BRR321 BRR320
SCR3_2 TIE32 RIE32 TE32 RE32 MPIE32 TEIE32 CKE321 CKE320
TDR3_2 TDR327 TDR326 TDR325 TDR324 TDR323 TDR322 TDR321 TDR320
SSR3_2 TDRE32 RDRF32 OER32 FER32 PER32 TEND32 MPBR32 MPBT32
RDR3_2 RDR327 RDR326 RDR325 RDR324 RDR323 RDR322 RDR321 RDR320
SCI3_2
TMWD CKS3 CKS2 CKS1 CKS0
TCSRWD1 B6WI TCWE B4WI TCSRWE B2WI WDON BOWI WRST
TCSRWD2 OVF B5WI WT/IT B3WI IEOVF
TCWD TCW7 TCW6 TCW5 TCW4 TCW3 TCW2 TCW1 TCW0
WDT*2
TCRF TOLH CKSH2 CKSH1 CKSH0 TOLL CKSL2 CKSL1 CKSL0
TCSRF OVFH CMFH OVIEH CCLRH OVFL CMFL OVIEL CCLRL
TCFH TCFH7 TCFH6 TCFH5 TCFH4 TCFH3 TCFH2 TCFH1 TCFH0
TCFL TCFL7 TCFL6 TCFL5 TCFL4 TCFL3 TCFL2 TCFL1 TCFL0
OCRFH OCRFH7 OCRFH6 OCRFH5 OCRFH4 OCRFH3 OCRFH2 OCRFH1 OCRFH0
OCRFL OCRFL7 OCRFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0
Timer F
ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADRR
ADR1 ADR0
AMR CKS TRGE CH3 CH2 CH1 CH0
ADSR ADSF
A/D
converter
PMR1 AEVL AEVH I/O ports
OSCCR IRQAECF OSCF — Clock pulse
generator
PMR3 TMOW
PMR4 TMOFH TMOFL TMIF
PMR5 WKP7 WKP6 WKP5 WKP4 WKP3 WKP2 WKP1 WKP0
PMR9 IRQ4 PWM2 PWM1
PMRB ADTSTCHG IRQ3 IRQ1 IRQ0
I/O ports
PWCR22 PWCR22 PWCR21 PWCR20
PWDR213 PWDR212 PWDR211 PWDR210 PWDR29 PWDR28 PWDR2
PWDR27 PWDR26 PWDR25 PWDR24 PWDR23 PWDR22 PWDR21 PWDR20
PWCR1 PWCR12 PWCR11 PWCR10
PWDR113 PWDR112 PWDR111 PWDR110 PWDR19 PWDR18 PWDR1
PWDR17 PWDR16 PWDR15 PWDR14 PWDR13 PWDR12 PWDR11 PWDR10
14-bit
PWM
Rev. 1.00, 07/04, page 455 of 570
Register
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 Module
Name
PDR1 P16 P15 P14 P13 P12 P11 P10
PDR3 P37 P36 P32 P31 P30
PDR4 P42 P41 P40
PDR5 P57 P56 P55 P54 P53 P52 P51 P50
PDR6 P67 P66 P65 P64 P63 P62 P61 P60
PDR7 P77 P76 P75 P74 P73 P72 P71 P70
PDR8 P87 P86 P85 P84 P83 P82 P81 P80
PDR9 P93 P92 P91 P90
PDRA PA3 PA2 PA1 PA0
PDRB PB7 PB6 PB5 PB2 PB1 PB0
PUCR1 PUCR16 PUCR15 PUCR14 PUCR13 PUCR12 PUCR11 PUCR10
PUCR3 PUCR37 PUCR36 PUCR30
PUCR5 PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50
PUCR6 PUCR67 PUCR66 PUCR65 PUCR64 PUCR63 PUCR62 PUCR61 PUCR60
PCR1 PCR16 PCR15 PCR14 PCR13 PCR12 PCR11 PCR10
PCR3 PCR37 PCR36 PCR32 PCR31 PCR30
PCR4 PCR42 PCR41 PCR40
PCR5 PCR57 PCR56 PCR55 PCR54 PCR53 PCR52 PCR51 PCR50
PCR6 PCR67 PCR66 PCR65 PCR64 PCR63 PCR62 PCR61 PCR60
PCR7 PCR77 PCR76 PCR75 PCR74 PCR73 PCR72 PCR71 PCR70
PCR8 PCR87 PCR86 PCR85 PCR84 PCR83 PCR82 PCR81 PCR80
PCR9 PCR93 PCR92 PCR91 PCR90
PCRA PCRA3 PCRA2 PCRA1 PCRA0
I/O ports
SYSCR1 SSBY STS2 STS1 STS0 LSON TMA3 MA1 MA0
SYSCR2 NESEL DTON MSON SA1 SA0
System
IEGR NMIEG TMIFG ADTRGNEG IEG4 IEG3 IEG1 IEG0 Interrupts
IENR1 IENRTC IENWP IEN4 IEN3 IENEC2 IEN1 IEN0
IENR2 IENDT IENAD IENSAD IENTFH IENTFL IENEC
INTM INTM1 INTM0
IRR1 IRR4 IRR3 IRREC2 IRRI1 IRRI0
IRR2 IRRDT IRRAD IRRSAD IRRTFH IRRTFL IRREC
IWPR IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0
Rev. 1.00, 07/04, page 456 of 570
Register
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 Module
Name
CKSTPR1 S4CKSTP
*4
S31CKSTP S32CKSTPADCKSTP — TFCKSTP FROMCKSTP*4 RTCCKSTP
CKSTPR2 ADBCKST
P
TPUCKSTP IICCKSTP PW2CKSTP AECCKSTP WDCKSTP PW1CKSTP LDCKSTP
System
Notes: 1. AEC: Asynchronous event counter
2. WDT: Watchdog timer
3. LCD: LCD controller/driver
4. This bit is available only for the flash memory version. In the masked ROM version, this
bit is reserved.
Rev. 1.00, 07/04, page 457 of 570
24.3 Register States in Each Operating Mode
Register
Abbreviation
Reset
Active
Sleep
Watch
Subactive
Subsleep
Standby
Module
SCR4
SCSR4
TDR4
RDR4
SCR4
FLMCR1 Initialized Initialized
FLMCR2 Initialized
FLPWCR Initialized
EBR1 Initialized Initialized
FENR Initialized
ROM
TSTR Initialized Initialized
TSYR Initialized Initialized
TPU
TCR_1 Initialized Initialized
TMDR_1 Initialized Initialized
TIOR_1 Initialized Initialized
TIER_1 Initialized Initialized
TSR_1_ Initialized Initialized
TCNT_1 Initialized Initialized
TGRA_1 Initialized Initialized
TGRB_1 Initialized Initialized
TPU_1
TCR_2 Initialized Initialized
TMDR_2 Initialized Initialized
TIOR_2 Initialized Initialized
TIER_2 Initialized Initialized
TSR_2 Initialized Initialized
TCNT_2 Initialized Initialized
TGRA_2 Initialized Initialized
TGRB_2 Initialized Initialized
TPU_2
ADCR Initialized
ADSSR Initialized
∆Σ A/D
converter
ADDR
Rev. 1.00, 07/04, page 458 of 570
Register
Abbreviation
Reset
Active
Sleep
Watch
Subactive
Subsleep
Standby
Module
RTCFLG Initialized
RSECDR Initialized
RMINDR Initialized
RHRDR Initialized
RWKDR
RTCCR1
RTCCR2
RTC
SUB32CR Initialized Clock pulse
generator
RTCCSR Initialized RTC
ICCR1 Initialized
ICCR2 Initialized
ICMR Initialized
ICIER Initialized
ICSR Initialized
SAR Initialized
ICDRT Initialized
ICDRR Initialized
IIC2
IPRA Initialized
IPRB Initialized
IPRC Initialized
IPRD Initialized
IPRE Initialized
Interrupts
ABRKCR2 Initialized
ABRKSR2 Initialized
BAR2H Initialized
BAR2L Initialized
BDR2H
BDR2L
Address break
ECPWCR Initialized
ECPWDR Initialized
AEC*1
WEGR Initialized Interrupts
SPCR Initialized SCI3
Rev. 1.00, 07/04, page 459 of 570
Register
Abbreviation
Reset
Active
Sleep
Watch
Subactive
Subsleep
Standby
Module
AEGSR Initialized
ECCR Initialized
ECCSR Initialized
ECH Initialized
ECL Initialized
AEC*1
SMR3_1 Initialized Initialized Initialized
BRR3_1 Initialized Initialized Initialized
SCR3_1 Initialized Initialized Initialized
TDR3_1 Initialized Initialized Initialized
SSR3_1 Initialized Initialized Initialized
RDR3_1 Initialized Initialized Initialized
SCI3_1
LPCR Initialized
LCR Initialized
LCR2 Initialized
LTRMR Initialized
BGRMR Initialized
LCD*3
IrCR Initialized Initialized Initialized IrDA
SMR3_2 Initialized Initialized Initialized
BRR3_2 Initialized Initialized Initialized
SCR3_2 Initialized Initialized Initialized
TDR3_2 Initialized Initialized Initialized
SSR3_2 Initialized Initialized Initialized
RDR3_2 Initialized Initialized Initialized
SCI3_2
TMWD Initialized
TCSRWD1 Initialized
TCSRWD2 Initialized
TCWD Initialized
WDT*2
TCRF Initialized
TCSRF Initialized
TCFHH Initialized
TCFL Initialized
OCRFH Initialized
OCRFL Initialized
Timer F
Rev. 1.00, 07/04, page 460 of 570
Register
Abbreviation
Reset
Active
Sleep
Watch
Subactive
Subsleep
Standby
Module
ADRR
AMR Initialized
ADSR Initialized
A/D converter
PMR1 Initialized
PMR3 Initialized
PMR4 Initialized
PMR5 Initialized
PMR9 Initialized
PMRB Initialized
I/O ports
PWCR2 Initialized
PWDR2 Initialized
PWCR1 Initialized
PWDR1 Initialized
14-bit PWM
PDR1 Initialized I/O ports
OSCCR Initialized Clock pulse
generator
PDR3 Initialized
PDR4 Initialized
PDR5 Initialized
PDR6 Initialized
PDR7 Initialized
PDR8 Initialized
PDR9 Initialized
PDRA Initialized
PDRB Initialized
PUCR1 Initialized
PUCR3 Initialized
PUCR5 Initialized
PUCR6 Initialized
PCR1 Initialized
PCR3 Initialized
PCR4 Initialized
PCR5 Initialized
I/O ports
Rev. 1.00, 07/04, page 461 of 570
Register
Abbreviation
Reset
Active
Sleep
Watch
Subactive
Subsleep
Standby
Module
PCR6 Initialized
PCR7 Initialized
PCR8 Initialized
PCR9 Initialized
PCRA Initialized
I/O ports
SYSCR1 Initialized
SYSCR2 Initialized
System
IEGR Initialized
IENR1 Initialized
IENR2 Initialized
INTM Initialized
IRR1 Initialized
IRR2 Initialized
IWPR Initialized
Interrupts
CKSTPR1 Initialized
CKSTPR2 Initialized
System
Notes: is not initialized.
1. AEC: Asynchronous event counter
2. WDT: Watchdog timer
3. LCD: LCD controller/driver
Rev. 1.00, 07/04, page 462 of 570
Rev. 1.00, 07/04, page 463 of 570
Section 25 Electrical Characteristics
25.1 Absolute Maximum Ratings for F-ZTAT Version
Table 25.1 lists the absolute maximum ratings.
Table 25.1 Absolute Maximum Ratings
Item Symbol Value Unit Note
Power supply voltage VCC –0.3 to +4.3 V *1
Analog power supply voltage AVCC –0.3 to +4.3 V
Input voltage Other than port B Vin –0.3 to VCC +0.3 V
Port B AVin –0.3 to AVCC +0.3 V
Operating temperature Topr –20 to +75
(regular specifications)
°C
–40 to +85
(wide-range specifications)*2
+75
(products shipped as chips)*3
Storage temperature Tstg –55 to +125 °C
Notes: 1. Permanent damage may occur to the chip if absolute maximum ratings are exceeded.
Normal operation should be under the conditions specified in Electrical Characteristics.
Exceeding these values can result in incorrect operation and reduced reliability.
2. The operating temperature range for flash memory programming/erasing is Ta = −20 to
+75°C.
3. Power may be applied when the temperature is between –20 and +75°C.
Rev. 1.00, 07/04, page 464 of 570
25.2 Electrical Characteristics for F-ZTAT Version
25.2.1 Power Supply Voltage and Operating Range
The power supply voltage and operating range are indicated by the shaded region in the figures.
(1) Power Supply Voltage and Oscillation Frequency Range
· All operating mode
· Refer to no. 2 in the note.
38.4
1.8 3.6
2.7
VCC (V)
fW (kHz)
32.768
2.0
4.2
10.0
2.71.8 3.6
VCC (V)
fosc (MHz)
· Active (high-speed) mode
· Sleep (high-speed) mode
· Refer to no.1 in the note.
· Active (high-speed) mode
· Sleep (high-speed) mode
· Refer to no.1 in the note.
[10-MHz version]
2.0
4.2
10.0
2.71.8 3.6
VCC (V)
fosc (MHz)
[4-MHz version]
Notes: 1. The fosc values are those when a resonator
is used; when an external clock is used, the
minimum value of fosc is 1 MHz.
2. When a resonator is used, hold VCC at
2.2 V to 3.6 V from power-on until the
oscillation settling time has elapsed.
Rev. 1.00, 07/04, page 465 of 570
(2) Power Supply Voltage and Operating Frequenc y Range
· Subactive mode
· Subsleep mode (except CPU)
· Watch mode (except CPU)
16.384
8.192
4.096
1.8 2.7 3.6
V
CC
(V)
φ
SUB
(kHz)
19.2
9.6
4.8
(1.0)
10
2.0
4.2
2.71.8 3.6
V
CC
(V)
φ (MHz)
· Active (high-speed) mode
· Sleep (high-speed) mode (except CPU)
· Refer to no.1 in the note.
[10-MHz version]
[4-MHz version]
(15.625)
1250
31.25
525
2.71.8 3.6
V
CC
(V)
φ (MHz)
· Active (medium-speed) mode
· Sleep (medium-speed) mode
(except A/D converter)
· Refer to no.2 in the note.
(1.0)
10
2.0
4.2
2.71.8 3.6
V
CC
(V)
φ (MHz)
· Active (high-speed) mode
· Sleep (high-speed) mode (except CPU)
· Refer to no.1 in the note.
(15.625)
1250
31.25
525
2.71.8 3.6
V
CC
(V)
φ (MHz)
· Active (medium-speed) mode
· Sleep (medium-speed) mode
(except A/D converter)
· Refer to no.2 in the note.
Notes: 1.
2.
The value in parentheses is the minimum operating
frequency when an external clock is input. When
using a resonator, the minimum operating frequency
(φ ) is 1 MHz
The value in parentheses is the minimum operating
frequency when an external clock is input. When
using a resonator, the minimum operating frequency
(φ ) is 31.25 kHz.
Rev. 1.00, 07/04, page 466 of 570
(3) Analog Power Supply Voltage and A/D Converter Operating Frequency Range
· Active (high-speed) mode
· Sleep (high-speed) mode
· Refer to no.1 in the note.
· Active (high-speed) mode
· Sleep (high-speed) mode
· Refer to no.1 in the note.
[10-MHz version]
[4-MHz version]
Notes: 1. The minimum operating frequency (φ) is 2 MHz when using a resonator;
and 1 MHz when using an external clock.
2. The minimum operating frequency (φ) is 31.25 kHz when using a resonator;
and 15.625 kHz when using an external clock.
· Active (medium-speed) mode
· Sleep (medium-speed) mode
· Refer to no.2 in the note.
· Active (medium-speed) mode
· Sleep (medium-speed) mode
· Refer to no.2 in the note.
10.0
2.0
4.2
2.71.8 3.6
(1.0)
(1.0)
10.0
2.0
4.2
2.71.8 3.6
AV
CC
(V) AV
CC
(V)
AV
CC
(V) AV
CC
(V)
(15.625)
(15.625)
1250
31.25
2.7 3.6
31.25
525
2.7 3.6
φ (MHz)
φ (MHz)
φ (MHz)
φ (MHz)
Rev. 1.00, 07/04, page 467 of 570
25.2.2 DC Characteristics
Table 25.2 lists the DC characteristics.
Table 25.2 DC Characteri stic s
VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified.
Values
Item Symbol Applicable Pins Test Condition Min. Typ. Max. Unit Notes
Input high
voltage
VIH RES, NMI, WKP0
to WKP7, IRQ0,
IRQ1, IRQ3, IRQ4,
AEVL, AEVH,
TMIC, TMIF, TMIG,
ADTRG, SCK32,
SCK31, SCK4
0.9VCC — VCC + 0.3 V
RXD32, RXD31 0.8VCC — VCC + 0.3
OSC1 0.9VCC — VCC + 0.3
X1 VCC = 2.7 to 3.6 V 0.9VCC — VCC + 0.3
P10 to P16,
P30 to P32,
P36, P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
P90 to P93,
PA0 to PA3,
TCLKA, TCLKB,
TCLKC, TIOCA1,
TIOCA2, TIOCB1,
TIOCB2, SCL, SDA
0.8VCC — VCC + 0.3
PB0 to PB2,
PB5 to PB7
0.8VCC — AVCC + 0.3
IRQAEC 0.9VCC — VCC + 0.3
Rev. 1.00, 07/04, page 468 of 570
Applicable Values
Item Symbol Pins Test Condition Min. Typ. Max. Unit Notes
Input low
voltage
VIL RES, NMI, WKP0
to WKP7, IRQ0,
IRQ1, IRQ3, IRQ4,
IRQAEC, AEVL,
AEVH, TMIF,
ADTRG, SCK32,
SCK31, SCK4
–0.3 — 0.1VCC V
RXD32, RXD31 –0.3 — 0.2VCC
OSC1 –0.3 — 0.1VCC
X1 VCC = 2.7 to 3.6 V –0.3 — 0.1VCC
P10 to P16,
P30 to P32,
P36, P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
P90 to P93,
PA0 to PA3,
TCLKA, TCLKB,
TCLKC, TIOCA1,
TIOCB1, TIOCA2,
TIOCB2, SCL,
SDA,
PB0 to PB2,
PB5 to PB7
–0.3 — 0.2VCC
–IOH = 1.0 mA
VCC = 2.7 to 3.6 V
VCC – 1.0 — — V Output high
voltage
VOH P13, P14,
P16, P17,
P30 to P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PA0 to PA3
–IOH = 0.1 mA
VCC = 1.8 to 3.6 V
VCC – 0.3 — —
P90 to P93 IOH = 1.0 mA
VCC = 2.7 to 3.6 V
VCC – 1.0 — —
I
OH = 0.1 mA
VCC = 1.8 to 3.6 V
VCC – 0.3 — —
Rev. 1.00, 07/04, page 469 of 570
Applicable Values
Item Symbol Pins Test Condition Min. Typ. Max. Unit Notes
Output low
voltage
VOL P10 to P16,
P30 to P32,
P36, P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PA0 to PA3
IOL = 0.4 mA — — 0.5 V
P90 to P93 IOL = 15 mA,
VCC = 2.7 to 3.6 V
— — 1.0
I
OL = 10 mA,
VCC = 2.2 to 3.6 V
— — 0.5
I
OL = 8 mA — — 0.5
SCL, SDA VCC = 1.8 to 3.6 V
IOL = 3.0 mA
— — 0.4
Input/output
leakage
current
| IIL | NMI, OSC1, X1,
P10 to P16,
P30 to P32,
P36, P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
IRQAEC,
PA0 to PA3,
P90 to P93
VIN = 0.5 V to
VCC – 0.5 V
— — 1.0 µA
PB0 to PB2,
PB5 to PB7
VIN = 0.5 V to
AVCC – 0.5 V
— — 1.0
Pull-up MOS
current
–Ip P10 to P16,
P30 to P32,
P36, P37,
P50 to P57,
P60 to P67
VCC = 3 V,
VIN = 0 V
30 — 180 µA
Rev. 1.00, 07/04, page 470 of 570
Applicable Values
Item Symbol Pins Test Condition Min. Typ. Max. Unit Notes
Input
capacitance*3
CIN All input pins
except power
supply pin
f = 1 MHz,
VIN =0 V,
Ta = 25°C
— — 15.0 pF
Active mode
current
consumption
IOPE1 V
CC Active (high-speed)
mode,
VCC = 1.8 V,
fOSC = 2 MHz
— 1.1 — mA *1*2*4
Max.
guideline =
1.1 × typ.
Active (high-speed)
mode,
VCC = 3 V,
fOSC = 4 MHz
— 3.0 — *1*2
Max.
guideline =
1.1 × typ.
Active (high-speed)
mode,
VCC = 3 V,
fOSC = 10 MHz
— 6.6 10 *1*2
I
OPE2 V
CC Active (medium-
speed) mode,
VCC = 1.8 V,
fOSC = 2 MHz,
φosc/64
— 0.4 — mA *1*2*4
Max.
guideline =
1.1 × typ.
Active (medium-
speed) mode,
VCC = 3 V,
fOSC = 4 MHz,
φosc/64
— 0.7 — *1*2
Max.
guideline =
1.1 × typ.
Active (medium-
speed) mode,
VCC = 3 V,
fOSC = 10 MHz,
φosc/64
— 1.1 1.8 *1*2
ISLEEP V
CC V
CC= 1.8 V,
fOSC= 2 MHz
— 0.7 — mA *1*2*4
Max.
guideline =
1.1 × typ.
Sleep mode
current
consumption
V
CC= 3 V,
fOSC= 4 MHz
— 1.7 — *1*2
Max.
guideline =
1.1 × typ.
V
CC= 3 V,
fOSC= 10 MHz
— 3.5 5.0 *1*2
Rev. 1.00, 07/04, page 471 of 570
Applicable Values
Item Symbol Pins Test Condition Min. Typ. Max. Unit Notes
Subactive
mode current
consumption
ISUB V
CC V
CC = 2.7 V,
LCD on, 32-kHz
crystal resonator
(φSUB = φw/8)
— 10 — µA *1*2
Reference
value
V
CC = 2.7 V,
LCD on, 32-kHz
crystal resonator
(φSUB = φw/2)
— 25 50 *1*2
Subsleep
mode current
consumption
ISUBSP V
CC V
CC = 2.7 V,
LCD on, 32-kHz
crystal resonator
(φSUB = φw/2)
— 4.8 16.0 µA *1*2
Watch mode
current
consumption
IWATCH V
CC V
CC = 1.8 V,
Ta = 25°C,
32-kHz crystal
resonator,
LCD not used
— 0.4 — µA *1*2*4
Reference
value
V
CC = 2.7 V,
32-kHz crystal
resonator,
LCD not used
— 2.0 6.0 *1*2
VCC = 1.8 V,
Ta = 25°C,
32-kHz crystal
resonator
not used
TBD *1*2*4
Reference
value
Standby mode
current
consumption
ISTBY V
CC
VCC = 3.0 V,
Ta = 25°C,
32-kHz crystal
resonator not used
— 0.3 —
µA
*1*2
Reference
value
32-kHz crystal
resonator not used
— 1.0 5.0 *1*2
32KSTOP = 1 — TBD — *1*2
Reference
value
RAM data
retaining
voltage
VRAM V
CC 1.5 — — V
IOL Output pins
except port 9
— — 0.5 mA Allowable
output low
current
(per pin) P90 to P93 — — 15.0
Rev. 1.00, 07/04, page 472 of 570
Values
Item Symbol Applicable Pins Test Condition Min. Typ. Max. Unit Notes
∑ IOL Output pins
except port 9
— — 20.0 mA Allowable
output low
current (total) Port 9 — — 60.0
VCC = 2.7 V to 3.6 V — — 2.0 Allowable
output high
current
(per pin)
–IOH All output pins
VCC = 1.8 V to 3.6 V — — 0.2
mA
Allowable
output high
current (total)
∑ – IOH All output pins — — 10.0 mA
Notes: 1. Pin states during current measurement.
Mode
RES
Pin
Internal State Other
Pins LCD Power
Supply
Oscillator Pins
Active (high-speed)
mode (IOPE1)
VCC V
CC Halted
Active (medium-speed)
mode (IOPE2)
Only CPU operates
On-chip WDT oscillator is off
Sleep mode VCC Only on-chip timers operate
On-chip WDT oscillator is off
VCC Halted
System clock oscillator:
crystal resonator
Subclock oscillator:
Pin X1 = GND
Subactive mode VCC Only CPU operates
On-chip WDT oscillator is off
VCC Halted
Subsleep mode VCC Only on-chip timers operate,
CPU stops
On-chip WDT oscillator is off
VCC Halted
Watch mode VCC Only time base operates, CPU
stops
On-chip WDT oscillator is off
VCC Halted
System clock oscillator:
crystal resonator
Subclock oscillator:
crystal resonator
Standby mode VCC CPU and timers both stop
On-chip WDT oscillator is off
VCC Halted System clock oscillator:
crystal resonator
Subclock oscillator:
Pin X1 = GND
2. Excludes current in pull-up MOS transistors and output buffers.
3. Except for the package for the TLP-85V.
4. Supported only by the 4MHz version.
Rev. 1.00, 07/04, page 473 of 570
25.2.3 AC Characteristics
Table 25.3 lists the control signal timing, table 25.4 lists the serial interface timing, and table 25.5
lists the I2C bus interface timing.
Table 25.3 Control Signal Timing
VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified.
Applicable Values Reference
Item Symbol Pins Test Condition Min. Typ. Max. Unit Figure
System clock
oscillation frequency
fOSC OSC1, OSC2 VCC = 2.7 to 3.6 V 2.0 — 10.0 MHz
V
CC = 1.8 to 3.6 V 2.0 — 4.2
OSC clock (φOSC) cycle
time
tOSC OSC1, OSC2 VCC = 2.7 to 3.6 V 100 — 500
(1000)
ns Figure 25.2
*2
V
CC = 1.8 to 3.6 V 250 — 500
(1000)
tcyc 1 — 64 tOSC System clock (φ) cycle
time — — 64 µs
Subclock oscillation
frequency
fW X1, X2 — 32.768
or 38.4
— kHz
Watch clock (φW) cycle
time
tW X1, X2 — 30.5 or
26.0
— µs Figure 25.2
Subclock (φSUB) cycle
time
tsubcyc 2 — 8 tW *1
Instruction cycle time 2 — — tcyc
tsubcyc
Oscillation stabilization
time
trc OSC1, OSC2 Crystal resonator
(VCC = 2.7 to 3.6 V)
— 0.8 2.0 ms Figure 25.10
Crystal resonator
(VCC = 2.2 to 3.6 V)
— 1.2 3
Ceramic resonator
(VCC = 2.2 to 3.6 V)
— 20 45 µs Figure 25.10
Ceramic resonator
(other than above)
— 80 —
Other than above — — 50 ms
Rev. 1.00, 07/04, page 474 of 570
Applicable Values Reference
Item Symbol Pins Test Condition Min. Typ. Max. Unit Figure
trc X1, X2 VCC = 2.2 to 3.6 V — — 2.0 s Figure 5.7 Oscillation stabilization
time Other than above — 4 —
External clock high
width
tCPH OSC1 VCC = 2.2 to 3.6 V 40 — — ns Figure 25.2
V
CC = 1.8 to 3.6 V 100 — —
X1 — 15.26
or
13.02
— µs
External clock low
width
tCPL OSC1 40 — — ns Figure 25.2
X1 — 15.26
or
13.02
— µs
tCPr OSC1 — — 10 ns Figure 25.2 External clock F time
X1 — — 55.0 ns
tCPf OSC1 — — 10 ns Figure 25.2 External clock fall time
X1 — — 55.0 ns
RES pin low width tREL RES 10 — — tcyc Figure
25.3*3
Input pin high width tIH IRQ0, IRQ1,
NMI,
IRQ3, IRQ4,
IRQAEC,
WKP0 to WKP7,
TMIF, ADTRG
2 — — tcyc
tsubcyc
Figure 25.4
AEVL, AEVH 0.5 — — tosc
t
TCKWH TCLKA, TCLKB,
TCLKC,
TIOCA1,
TIOCB1,
TIOCA2,
TIOCB2
Single edge
specified
1.5 — — tcyc Figure 25.7
Both edges
specified
2.5 — —
Rev. 1.00, 07/04, page 475 of 570
Applicable Values Reference
Item Symbol Pins Test Condition Min. Typ. Max. Unit Figure
Input pin low width tIL IRQ0, IRQ1,
NMI,
IRQ3, IRQ4,
IRQAEC,
WKP0 to WKP7,
TMIF, ADTRG
2 — — tcyc
tsubcyc
Figure 25.4
AEVL, AEVH 0.5 — — tosc
t
TCKWL TCLKA, TCLKB,
TCLKC,
TIOCA1,
TIOCB1,
TIOCA2,
TIOCB2
Single edge
specified
1.5 — — tcyc Figure 25.7
Both edges
specified
2.5 — —
Notes: 1. Selected with the SA1 and SA0 bits in the system control register 2 (SYSCR2).
2. The value in parentheses is tOSC (max.) when an external clock is used.
3. For details on the power-on reset characteristics, refer to table 25.9 and figure 25.1.
Table 25.4 Serial Interface Timing
VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified.
Values Reference
Item Symbol Test Condition Min. Typ. Max. Unit Figure
Asynchronous tscyc 4 — — tcyc or Figure 25.5 Input clock
cycle Clocked
synchronous
6 — —
t
subcyc
Input clock pulse width tSCKW 0.4 — 0.6 tscyc Figure 25.5
Transmit data delay time
(clocked synchronous)
tTXD — — 1 tcyc or
tsubcyc
Figure 25.6
Receive data setup time
(clocked synchronous)
tRXS 400.0 — — ns Figure 25.6
Receive data hold time
(clocked synchronous)
tRXH 400.0 — — ns Figure 25.6
Rev. 1.00, 07/04, page 476 of 570
Table 25.5 I2C Bus Interface Timing
VCC = 1.8 V to 3.6 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise specified.
Test Values Reference
Item Symbol Condition Min. Typ. Max. Unit Figure
SCL input cycle time tSCL 12tcyc + 600 — — ns Figure 25.8
SCL input high width tSCLH 3tcyc + 300 — — ns
SCL input low width tSCLL 5tcyc + 300 — — ns
SCL and SDA input fall time tSf — — 300 ns
SCL and SDA input spike
pulse removal time
tSP — — 1tcyc ns
SDA input bus-free
time
tBUF 5tcyc — — ns
Start condition input hold
time
tSTAH 3tcyc — — ns
Retransmission start
condition input setup time
tSTAS 3tcyc — — ns
Setup time for stop condition
input
tSTOS 3tcyc — — ns
Data-input setup time tSDAS 1tcyc + 20 — — ns
Data-input hold time tSDAH 0 — — ns
Capacitive load of
SCL and SDA
Cb 0 — 400 pF
SCL and SDA output fall
time
tSf — — 300 ns
Rev. 1.00, 07/04, page 477 of 570
25.2.4 A/D Converter Characteristics
Table 25.6 lists the A/D converter characteristics.
Table 25.6 A/D Converter Characteristics
VCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified.
Applicable Values
Item Symbol Pins Test Condition Min. Typ. Max. Unit Notes
Analog power
supply voltage
AVCC AVCC 1.8 — 3.6 V
*1
Analog input
voltage
AVIN AN0 to AN2 –0.3 — AVCC +
0.3
V
AIOPE AVCC AVCC = 3.0 V — — 1.0 mA Analog power
supply current AISTOP1 AVCC — 600 — µA
*2
Reference
value
AISTOP2 AVCC — — 5 µA
*3
Analog input
capacitance
CAIN AN0 to AN2 — — 15.0 pF
Allowable signal
source
impedance
RAIN — — 10.0 kΩ
Resolution (data
length)
— — 10 Bits
Nonlinearity error AVCC = 2.7 V to 3.6 V
VCC = 2.7 V to 3.6 V
— — ±3.5 LSB
AVCC = 2.0 V to 3.6 V
VCC = 2.0 V to 3.6 V
— — ±5.5
Other than above — — ±7.5
Quantization
error
— — ±0.5 LSB
Absolute
accuracy
AVCC = 2.7 V to 3.6 V
VCC = 2.7 V to 3.6 V
— — ±4.0 LSB
AVCC = 2.0 V to 3.6 V
VCC = 2.0 V to 3.6 V
— — ±6.0
Other than above — — ±8.0
Conversion time AVCC = 2.7 V to 3.6 V
VCC = 2.7 V to 3.6 V
12.4 — 124 µs
Other than above 31 — 124
Notes: 1. Set AVCC = VCC when the A/D converter is not used.
2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle.
3. AISTOP2 is the current at a reset and in standby, watch, subactive, and subsleep modes
while the A/D converter is idle.
Rev. 1.00, 07/04, page 478 of 570
25.2.5 ∆Σ A/D Converter Characteristics
Table 25.7 lists the ∆Σ A/D converter characteristics.
Table 25.7 ∆Σ A/D Converter Characteristics
Applicable Values
Item Symbol Pins Test Condition Min. Typ. Max. Unit Notes
Analog power
supply voltage
DVcc DVcc 2.2/
2.7
3.6 V *1*4
DIOPE DVcc DVcc = 3.0 V,
fOVS = 1.6 MHz
TBD mA Reference
value
Analog power
supply current
DISTOP1 DVcc DVcc = 3.0 V,
fOVS = 1.6 MHz
TBD µA *2
Reference
value
DISTOP2 DVcc DVcc = 3.0 V,
fOVS = 1.6 MHz
TBD µA *3
Reference
value
Resolution 14 — — Bits
DVcc = 2.2 to 3.6 V,
Vcc = 2.2 to 3.6 V
0.25 1.6 TBD MHz
Oversampling
frequency
fOVS
DVcc = 2.7 to 3.6 V,
Vcc = 2.7 to 3.6 V
0.25 1.6 TBD MHz
DVcc = 2.2 to 3.6 V,
Vcc = 2.2 to 3.6 V
0.78 5.0 TBD kHz
Sampling
frequency
fS
DVcc = 2.7 to 3.6 V,
Vcc = 2.7 to 3.6 V
0.78 5.0 TBD kHz
DVcc = 2.2 to 3.6 V,
Vcc = 2.2 to 3.6 V
TBD 200 1280 µs
Conversion speed
DVcc = 2.7 to 3.6 V,
Vcc = 2.7 to 3.6 V
TBD 200 1280 µs
Integral lineality
error
PGA bypass
(DVcc = 3.0 V,
Vref = 2.7 V, conversion
speed = 160 µs)
— TBD — LSB
Rev. 1.00, 07/04, page 479 of 570
Values
Item Symbol
Applicable
Pins Test Condition Min. Typ. Max. Unit Notes
Differential
lineality error
PGA bypass
(DVcc = 3.0 V,
Vref = 2.7 V, conversion
speed = 160 µs)
— TBD — LSB
Offset error PGA bypass
(DVcc = 3.0 V,
Vref = 2.7 V, conversion
speed = 160 µs)
— TBD — mV
Full scale error PGA bypass
(DVcc = 3.0 V,
Vref = 2.7 V, conversion
speed = 160 µs)
— TBD — LSB
— 1/3 — V/V
— 1 — V/V
— 2 — V/V
PGA gain
— 4 — V/V
PGA = 1/3,
DVcc = 3.0 V
— TBD — mV
PGA = 1,
DVcc = 3.0 V
— TBD — mV
PGA = 2,
DVcc = 3.0 V
— TBD — mV
PGA gain error Tad
PGA = 4,
DVcc = 3.0 V
— TBD — mV
Internal reference
voltage
REF — TBD — V *5
External
reference voltage
V
ref 0.1
DVcc
— 0.9 DVcc V
Rev. 1.00, 07/04, page 480 of 570
Values
Item Symbol
Applicable
Pins Test Condition Min. Typ. Max. Unit Notes
Analog data input
voltage
Ain Ain1, Ain2 PGA = 1/3 0.3 — 2.7 Vref
(2.7 Vref <
DVcc)
V
PGA = 1, bypass 0.1 — Vref V
PGA = 2 0.1 — 0.5 Vref V
PGA = 4 0.1 — 0.25 Vref V
Operating
temperature
Ta 0 — 50 °C
Notes: 1. Set DVcc = Vcc when the ∆Σ A/D converter is not used.
2. DISTOP1 is the current in active and sleep modes while the ∆Σ A/D converter is idle.
3. DISTOP2 is the current at a reset and in standby, watch, subactive, and subsleep modes
while the ∆Σ A/D converter is idle.
4. Minimum values are 2.2 V and 2.7 V for the 4 MHz version and 10 MHz version,
respectively. DVcc should be connected to Vcc when the ∆Σ A/D converter is not used.
5. BGR stabilization time = 10 µs (Ta = 25°C, Vcc = 3.0 V)
Rev. 1.00, 07/04, page 481 of 570
25.2.6 LCD Characteristics
Table 25.8 shows the LCD characteristics.
Table 25.8 LCD Characteristics
VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified.
Values
Item Symbol
Applicable
Pins Test Condition Min. Typ. Max. Unit Notes
Segment driver drop
voltage
VDS SEG1 to
SEG32
ID = 2 µA
V1 = 2.7 V to 3.6 V
— — 0.6 V *1
Common driver drop
voltage
VDC COM1 to
COM4
ID = 2 µA
V1 = 2.7 V to 3.6 V
— — 0.3 V *1
LCD power supply
split-resistance
RLCD Between V1 and VSS 1.5 3.0 7.0 MΩ
LCD display voltage VLCD V1 2.2 — 3.6 V *2
V3 power supply
voltage
VLCD3 V3 Between V3 and VSS 0.9 1.0 1.1 V *3*4
V2 power supply
voltage
VLCD2 V2 Between V2 and VSS — 2.0
(VLCD3 × 2)
— V *3*4
V1 power supply
voltage
VLCD1 V1 Between V1 and VSS — 3.0
(VLCD3 × 3)
— V *3*4
3-V constant voltage
LCD power supply
circuit current
consumption
ILCD Vcc Vcc = 3.0 V
Booster clock:
125 kHz
— 20 — µA Reference
value*4*5
Notes: 1. The voltage drop from power supply pins V1, V2, V3, and VSS to each segment pin or
common pin.
2. When the LCD display voltage is supplied from an external power source, ensure that
the following relationship is maintained: V1 ≥ V2 ≥ V3 ≥ VSS.
3. The value when the LCD power supply split-resistor is separated and 3-V constant
voltage power supply circuit is driven.
4. For details on the register (BGRMR) setting range when the voltage of the V3 pin is set
to 1.0 V, refer to section 20.3.5, BGR Control Register (BGRMR).
5. Includes the current consumption of the band-gap reference circuit (operation).
Rev. 1.00, 07/04, page 482 of 570
25.2.7 Power-On Reset Circuit Characteristics
Table 25.9 lists the power-on reset circuit characteristics.
Table 25.9 Power-On Reset Circuit Characteristics
VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V,
Ta = −20 to +75°C (regular specifications), Ta = −40 to +85°C (wide-ra nge specifications),
unless otherwise specified.
Values
Item Symbol Test Condition Min. Typ. Max. Unit Notes
Reset voltage V_rst 0.7Vcc 0.8Vcc 0.9Vcc V
Power supply rise time t_vtr The Vcc rise time should be at least twice as
fast as the RES rise time.
Reset count time t_out 0.8 — 4.0 µs
Count start time t_cr Adjustable by the value of the external capacitor
of the RES pin.
On-chip pull-up
resistance
Rp Vcc = 3.0 V 60 100 — kΩ
25.2.8 Watchdog Timer Characteristics
Table 25.10 Watchdog Timer Characteristics
VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V,
Ta = −20 to +75°C (regular specifications), Ta = −40 to +85°C (wide-ra nge specifications),
unless otherwise specified.
Applicable Values
Item Symbol Pins Test Condition Min. Typ. Max. Unit Notes
On-chip oscillator
overflow time
tovf 0.2 0.4 — s
Rev. 1.00, 07/04, page 483 of 570
25.2.9 Flash Memory Charac teri st ic s Preliminary
Table 25.11 lists the flash memory characteristics.
Table 25.11 Flash Memory Characterist i cs
AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, VCC = 1.8 V to 3.6 V (operating voltage range in
reading), VCC = 3.0 V to 3.6 V (operating vol ta ge ran ge i n progr amming/erasing),
Ta = –20 to +75°C (operating temperature range in programming/erasing)
Test Values
Item Symbol Condition Min. Typ. Max. Unit
Programming time (per 128 bytes)*1*2*4 t
P — 7 200 ms
Erase time (per block)*1*3*6 t
E — 100 1200 ms
Maximum number of reprogrammings NWEC 1000*8*11 10000*9 — Times
100*8*12 10000*9 —
Data retention time tDRP 10*10 — — Years
Programming Wait time after SWE bit setting*1 x 1 — — µs
Wait time after PSU bit setting*1 y 50 — — µs
Wait time after P bit setting*1*4 z1 1 ≤ n ≤ 6 28 30 32 µs
z2 7 ≤ n ≤ 1000 198 200 202 µs
z3
Additional-
programming
8 10 12 µs
Wait time after P bit clear*1 α 5 — — µs
Wait time after PSU bit clear*1 β 5 — — µs
Wait time after PV bit setting*1 γ 4 — — µs
Wait time after dummy write*1 ε 2 — — µs
Wait time after PV bit clear*1 η 2 — — µs
Wait time after SWE bit clear*1 θ 100 — — µs
Maximum programming count*1*4*5 N — — 1000 Times
Rev. 1.00, 07/04, page 484 of 570
Test Values
Item Symbol Condition Min. Typ. Max. Unit
Erase Wait time after SWE bit setting*1 x 1 — — µs
Wait time after ESU bit setting*1 y 100 — — µs
Wait time after E bit setting*1*6 z 10 — 100 ms
Wait time after E bit clear*1 α 10 — — µs
Wait time after ESU bit clear*1 β 10 — — µs
Wait time after EV bit setting*1 γ 20 — — µs
Wait time after dummy write*1 ε 2 — — µs
Wait time after EV bit clear*1 η 4 — — µs
Wait time after SWE bit clear*1 θ 100 — — µs
Maximum erase count*1*6*7 N — — 120 Times
Notes: 1. Make the time settings in accordance with the program/erase algorithms.
2. The programming time for 128 bytes. (Indicates the total time for which the P bit in the
flash memory control register 1 (FLMCR1) is set. The program-verify time is not
included.)
3. The time required to erase one block. (Indicates the total time for which the E bit in the
flash memory control register 1 (FLMCR1) is set. The erase-verify time is not
included.)
4. Programming time maximum value (tP (max.)) = wait time after P bit setting (z) ×
maximum number of programmings (N)
5. Set the maximum number of programmings (N) according to the actual set values of
z1, z2, and z3, so that it does not exceed the programming time maximum value (tP
(max.)). The wait time after P bit setting (z1, z2) should be changed as follows
according to the value of the number of programmings (n).
Number of programmings (n)
1 ≤ n ≤ 6 z1 = 30 µs
7 ≤ n ≤ 1000 z2 = 200 µs
6. Erase time maximum value (tE (max.)) = wait time after E bit setting (z) × maximum
number of erases (N)
7. Set the maximum number of erases (N) according to the actual set value of (z), so that
it does not exceed the erase time maximum value (tE (max.)).
8. The minimum number of times in which all characteristics are guaranteed following
reprogramming. (The guarantee covers the range from 1 to the minimum value.)
9. Reference value at 25°C. (Guideline showing number of reprogrammings over which
functioning will be retained under normal circumstances.)
10. Data retention characteristics within the range indicated in the specifications, including
the minimum value for reprogrammings.
11. Applies to an operating voltage range when reading data of 2.7 to 3.6 V.
12. Applies to an operating voltage range when reading data of 1.8 to 3.6 V.
Rev. 1.00, 07/04, page 485 of 570
25.3 Absolute Maximum Ratings for Masked ROM Version
Table 25.12 lists the absolute maximum ratings.
Table 25.12 Absolute Maximum Ratings
Item Symbol Value Unit Note
Power supply voltage VCC –0.3 to +4.3 V
*1
Analog power supply voltage AVCC –0.3 to +4.3 V
Input voltage Other than port B Vin –0.3 to VCC +0.3 V
Port B AVin –0.3 to AVCC +0.3 V
Operating temperature Topr –20 to +75
(regular specifications)
°C
–40 to +85
(wide-range specifications)
+75 (products shipped as
chips)*2
Storage temperature Tstg –55 to +125 °C
Notes: 1. Permanent damage may occur to the chip if absolute maximum ratings are exceeded.
Normal operation should be under the conditions specified in Electrical Characteristics.
Exceeding these values can result in incorrect operation and reduced reliability.
2. Power may be applied when the temperature is between –20 and +75°C.
Rev. 1.00, 07/04, page 486 of 570
25.4 Electrical Characteristics for Masked ROM Version
25.4.1 Power Supply Voltage and Operating Range
The power supply voltage and operating range are indicated by the shaded region in the figures.
(1) Power Supply Voltage and Oscillation Frequency Range
· All operating mode
· Refer to no.2 in the note.
38.4
1.8 3.6
2.7
V
CC
(V)
fW (kHz)
32.768
2.0
4.2
10.0
2.71.8 3.6
V
CC
(V)
fosc (MHz)
· Active (high-speed) mode
· Sleep (high-speed) mode
· Refer to no.1 in the note. Notes: 1. The fosc values are those when a resonator
is used; when an external clock is used, the
minimum value of fosc is 1 MHz.
2. When a resonator is used, hold VCC at
2.2 V to 3.6 V from power-on until the
oscillation settling time has elapsed.
Rev. 1.00, 07/04, page 487 of 570
(2) Power Supply Voltage and Operating Frequenc y Range
· Subactive mode
· Subsleep mode (except CPU)
· Watch mode (except CPU)
16.384
8.192
4.096
1.8 2.7 3.6
VCC (V)
φ SUB (kHz)
19.2
9.6
4.8
(1.0)
10
2.0
4.2
2.71.8 3.6
VCC (V)
φ (MHz)
· Active (high-speed) mode
· Sleep (high-speed) mode (except CPU)
· Refer to no.1 in the note.
(15.625)
1250
31.25
525
2.71.8 3.6
VCC (V)
φ (MHz)
· Active (medium-speed) mode
· Sleep (medium-speed) mode
(except A/D converter)
· Refer to no.2 in the note.
Notes: 1.
2.
The value in parentheses is the minimum operating
frequency when an external clock is input. When
using a resonator, the minimum operating frequency
(φ ) is 1 MHz
The value in parentheses is the minimum operating
frequency when an external clock is input. When
using a resonator, the minimum operating frequency
(φ ) is 31.25 kHz.
(3) Analog Power Supply Voltage and A/D Converter Operating Frequency Range
· Active (high-speed) mode
· Sleep (high-speed) mode
· Refer to no.1 in the note.
Notes: 1. The minimum operating frequency (φ) is 2 MHz when using a resonator;
and 1 MHz when using an external clock.
2. The minimum operating frequency (φ) is 31.25 kHz when using a resonator;
and 15.625 kHz when using an external clock.
· Active (medium-speed) mode
· Sleep (medium-speed) mode
· Refer to no.2 in the note.
(1.0)
10.0
2.0
4.2
2.71.8 3.6
AVCC(V) AVCC(V)
(15.625)
1250
31.25
2.7 3.6
φ (MHz)
φ (MHz)
525
Rev. 1.00, 07/04, page 488 of 570
25.4.2 DC Characteristics
Table 25.13 lists the DC characteristics.
Table 25.13 DC Characteri sti c s
VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified.
Values
Item Symbol Appl icable Pins Test Condition Min. Typ. Max. Unit Notes
Input high
voltage
VIH RES, NMI, WKP0 to
WKP7, IRQ0, IRQ1,
IRQ3, IRQ4, AEVL,
AEVH, TMIF,
ADTRG, SCK32,
SCK31, SCK4
0.9VCC — VCC + 0.3 V
RXD32, RXD31 0.8VCC — VCC + 0.3
OSC1 0.9VCC — VCC + 0.3
X1 VCC = 2.7 to 3.6 V 0.9VCC — VCC + 0.3
P10 to P16,
P30 to P32,
P36, P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
P90 to P93,
PA0 to PA3,
TCLKA, TCLKB,
TCLKC, TIOCA1,
TIOCA2, TIOCB1,
TIOCB2, SCL, SDA
0.8VCC — VCC + 0.3
PB0 to PB2,
PB5 to PB7
0.8VCC — AVCC + 0.3
IRQAEC 0.9VCC — VCC + 0.3
Rev. 1.00, 07/04, page 489 of 570
Values
Item Symbol Appl icable Pins Test Condition Min. Typ. Max. Unit Notes
Input low
voltage
VIL RES, NMI, WKP0 to
WKP7, IRQ0, IRQ1,
IRQ3, IRQ4,
IRQAEC, AEVL,
AEVH, TMIF,
ADTRG, SCK32,
SCK31, SCK4
–0.3 — 0.1VCC V
RXD32, RXD31 –0.3 — 0.2VCC
OSC1 –0.3 — 0.1VCC
X1 VCC = 2.7 to 3.6 V –0.3 — 0.1VCC
P10 to P16,
P30 to P32,
P36, P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
P90 to P93,
PA0 to PA3,
TCLKA, TCLKB,
TCLKC, TIOCA1,
TIOCB1, TIOCA2,
TIOCB2, SCL,
SDA,
PB0 to PB2
PB5 to PB7
–0.3 — 0.2VCC
–IOH = 1.0 mA
VCC = 2.7 to 3.6 V
VCC – 1.0 — — V Output high
voltage
VOH P10 to P16,
P30 to P32,
P36, P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PA0 to PA3
–IOH = 0.1 mA
VCC = 1.8 to 3.6 V
VCC – 0.3 — —
P90 to P93 –IOH = 1.0 mA
VCC = 2.7 to 3.6 V
VCC – 1.0 — —
–IOH = 0.1 mA
VCC = 1.8 to 3.6 V
VCC – 0.3 — —
Rev. 1.00, 07/04, page 490 of 570
Values
Item Symbol Applicable Pins Test Condition Min. Typ. Max. Unit Notes
Output low
voltage
VOL P10 to P16,
P30 to P32,
P36, P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PA0 to PA3
IOL = 0.4 mA — — 0.5 V
P90 to P93 IOL = 15 mA
VCC = 2.7 to 3.6 V
— — 1.0
I
OL = 10 mA
VCC = 2.2 to 3.6 V
— — 0.5
I
OL = 8.0 mA
VCC = 1.8 to 3.6 V
— — 0.5
SCL, SDA VCC = 1.8 to 3.6 V
IOL = 3.0 mA
— — 0.4 V
Input/output
leakage
current
| IIL | NMI, OSC1, X1,
P10 to P16,
P30 to P32,
P36, P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
IRQAEC,
PA0 to PA3,
P90 to P93
VIN = 0.5 V to
VCC – 0.5 V
— — 1.0 µA
PB0 to PB2
PB5 to PB7
VIN = 0.5 V to
AVCC – 0.5 V
— — 1.0
Pull-up MOS
current
–Ip P10 to P16,
P30 to P32,
P36, P37,
P50 to P57,
P60 to P67
VCC = 3 V,
VIN = 0 V
30 — 180 µA
Input
capacitance*3
CIN All input pins except
power supply pin
f = 1 MHz,
VIN =0 V,
Ta = 25°C
— — 15.0 pF
Rev. 1.00, 07/04, page 491 of 570
Values
Item Symbol Applicable Pins Test Condition Mi n. Typ. Max. Unit Notes
Active mode
current
consumption
IOPE1 V
CC Active (high-speed) mode,
VCC = 1.8 V,
fOSC = 2 MHz
— TBD — mA *1*2
Max.
guideline =
1.1 × typ.
Active (high-speed) mode,
VCC = 3 V,
fOSC = 4 MHz
— TBD — *1*2
Max.
guideline =
1.1 × typ.
Active (high-speed) mode,
VCC = 3 V,
fOSC = 10 MHz
— TBD TBD *1*2
I
OPE2 V
CC Active (medium-speed)
mode,
VCC = 1.8 V,
fOSC = 2 MHz,
φosc/64
— TBD — mA *1*2
Max.
guideline =
1.1 × typ.
Active (medium-speed)
mode,
VCC = 3 V,
fOSC = 4 MHz,
φosc/64
— TBD — *1*2
Max.
guideline =
1.1 × typ.
Active (medium-speed)
mode,
VCC = 3 V,
fOSC = 10 MHz,
φosc/64
— TBD TBD *1*2
ISLEEP V
CC V
CC= 1.8 V,
fOSC= 2 MHz
— TBD — mA *1*2
Max.
guideline =
1.1 × typ.
Sleep mode
current
consumption
V
CC= 3 V,
fOSC= 4 MHz
— TBD — *1*2
Max.
guideline =
1.1 × typ.
V
CC= 3 V,
fOSC= 10 MHz
— TBD TBD *1*2
Rev. 1.00, 07/04, page 492 of 570
Values
Item Symbol Applicable Pins Test Condition Mi n. Typ. Max. Unit Notes
Subactive
mode current
consumption
ISUB V
CC V
CC = 1.8 V,
LCD on, 32-kHz crystal
resonator (φSUB = φw/2)
— TBD — µA *1*2
Reference
value
V
CC = 2.7 V,
LCD on, 32-kHz crystal
resonator (φSUB = φw/8)
— TBD — *1*2
Reference
value
V
CC = 2.7 V,
LCD on, 32-kHz crystal
resonator (φSUB = φw/2)
— TBD TBD *1*2
Subsleep
mode current
consumption
ISUBSP V
CC V
CC = 2.7 V,
LCD on, 32-kHz crystal
resonator (φSUB = φw/2)
— TBD TBD µA *1*2
Watch mode
current
consumption
IWATCH V
CC V
CC = 1.8 V,
Ta = 25°C,
32-kHz crystal resonator,
LCD not used
— TBD — µA *1*2
Reference
value
V
CC = 2.7 V,
32-kHz crystal resonator,
LCD not used
— TBD TBD *1*2
Standby mode
current
consumption
ISTBY V
CC V
CC = 1.8 V,
Ta = 25°C,
32-kHz crystal resonator
not used
— TBD — µA *1*2
Reference
value
V
CC = 3.0 V,
Ta = 25°C,
32-kHz crystal resonator
not used
— TBD — *1*2
Reference
value
32-kHz crystal resonator
not used
— TBD TBD *1*2
32KSTOP = 1 — TBD — *1*2
Reference
value
Rev. 1.00, 07/04, page 493 of 570
Applicable Values
Item Symbol Pins Test Condition Min. Typ. Max. Unit Notes
RAM data retaining
voltage
VRAM V
CC 1.5 — — V
IOL Output pins
except port 9
— — 0.5 mA Allowable output low
current
(per pin) P90 to P93 — — 15.0
∑ IOL Output pins
except port 9
— — 20.0 mA Allowable output low
current (total)
Port 9 — — 60.0
VCC = 2.7 to 3.6 V — — 2.0 Allowable output high
current
(per pin)
–IOH All output
pins
VCC = 1.8 to 3.6 V — — 0.2
mA
Allowable output high
current (total)
∑ – IOH All output
pins
— — 10.0 mA
Notes: 1. Pin states during current measurement.
Mode
RES
Pin
Internal State Other
Pins LCD Power
Supply
Oscillator Pins
Active (high-speed)
mode (IOPE1)
VCC V
CC Halted
Active (medium-speed)
mode (IOPE2)
Only CPU operates
On-chip WDT oscillator is off
Sleep mode VCC Only on-chip timers operate
On-chip WDT oscillator is off
VCC Halted
System clock oscillator:
crystal resonator
Subclock oscillator:
Pin X1 = GND
Subactive mode VCC Only CPU operates
On-chip WDT oscillator is off
VCC Halted
Subsleep mode VCC Only on-chip timers operate,
CPU stops
On-chip WDT oscillator is off
VCC Halted
Watch mode VCC Only time base operates, CPU
stops
On-chip WDT oscillator is off
VCC Halted
System clock oscillator:
crystal resonator
Subclock oscillator:
crystal resonator
Standby mode VCC CPU and timers both stop
On-chip WDT oscillator is off
VCC Halted System clock oscillator:
crystal resonator
Subclock oscillator:
Pin X1 = GND
2. Excludes current in pull-up MOS transistors and output buffers.
3. Except for the package for the TLP-85V.
Rev. 1.00, 07/04, page 494 of 570
25.4.3 AC Characteristics
Table 25.14 lists the control signal timing, table 25.15 lists the serial interface timing, and table
25.16 lists the I2C bus interface timing.
Table 25.14 Control Signal Timing
VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified.
Applicable Values Reference
Item Symbol Pins Test Condition Min. Typ. Max. Unit Figure
System clock
oscillation frequency
fOSC OSC1, OSC2 VCC = 2.7 to 3.6 V 2.0 — 10.0 MHz
V
CC = 1.8 to 3.6 V 2.0 — 4.2
On-chip oscillator
is used
VCC = 1.8 to 2.7 V
2.0 — 4.2 *4
On-chip oscillator
is used
VCC = 2.7 to 3.6 V
2.0 — 10
OSC clock (φOSC) cycle
time
tOSC OSC1, OSC2 VCC = 2.7 to 3.6 V 100 — 500
(1000)
ns Figure 25.2
*2
V
CC = 1.8 to 3.6 V 250 — 500
(1000)
On-chip oscillator
is used
VCC = 1.8 to 2.7 V
238 — 500 *4
On-chip oscillator
is used
VCC = 2.7 to 3.6 V
100 — 500
tcyc 1 — 64 tOSC System clock (φ)
cycle time — — 64 µs
Subclock oscillation
frequency
fW X1, X2 — 32.768
or 38.4
— kHz Figure 5.7
Watch clock (φW) cycle
time
tW X1, X2 — 30.5 or
26.0
— µs Figure 25.2
Subclock (φSUB) cycle
time
tsubcyc 2 — 8 tW *1
Instruction cycle time 2 — — tcyc
tsubcyc
Rev. 1.00, 07/04, page 495 of 570
Applicable Values Reference
Item Symbol Pins Test Condition Min. Typ. Max. Unit Figure
Oscillation stabilization
time
trc OSC1, OSC2 Ceramic resonator
VCC = 2.2 to 3.6 V
— 20 45 µs Figure 25.10
Ceramic resonator
Other than above
— 80 —
Crystal resonator
VCC = 2.7 to 3.6 V
— 0.8 2 ms
Crystal resonator
VCC = 2.2 to 3.6 V
— 1.2 3
Other than above — — 50
On-chip oscillator
is used
70 — 100 µs *4
X1, X2 VCC = 2.2 to 3.6 V — — 2 s Figure 5.7
Other than above — 4 —
tCPH OSC1 VCC = 2.7 to 3.6 V 40 — — ns Figure 25.2
V
CC = 1.8 to 3.6 V 100 — —
External clock high
width
X1 — 15.26
or
13.02
— µs
tCPL OSC1 VCC = 2.7 to 3.6 V 40 — — ns Figure 25.2
V
CC = 1.8 to 3.6 V 100 — —
External clock low
width
X1 — 15.26
or
13.02
— µs
tCPr OSC1 VCC = 2.7 to 3.6 V — — 10 ns Figure 25.2
V
CC = 1.8 to 3.6 V — — 25
External clock rise
time
X1 — — 55.0 ns
tCPf OSC1 VCC = 2.7 to 3.6 V — — 10 ns Figure 25.2
V
CC = 1.8 to 3.6 V — — 25
External clock fall time
X1 — — 55.0 ns
RES pin low width tREL RES 10 — — tcyc Figure 25.3*3
Rev. 1.00, 07/04, page 496 of 570
Applicable Values Reference
Item Symbol Pins Test Condition Min. Typ. Figure Unit Figure
Input pin high width tIH IRQ0, IRQ1,
NMI, IRQ3,
IRQ4, IRQAEC,
WKP0 to WKP7,
TMIF, ADTRG
2 — — tcyc
tsubcyc
Figure 25.4
AEVL, AEVH 0.5 — — tosc
t
TCKWH TCLKA, TCLKB,
TCLKC,
TIOCA1,
TIOCB1,
TIOCA2,
TIOCB2
Single edge
specified
1.5 — — tcyc Figure 25.7
Both edges
specified
2.5 — —
Input pin low width tIL IRQ0, IRQ1,
NMI, IRQ3,
IRQ4,
IRQAEC,
WKP0 to WKP7,
TMIF, ADTRG
2 — — tcyc
tsubcyc
Figure 25.4
AEVL, AEVH 0.5 — — tosc
t
TCKWL TCLKA, TCLKB,
TCLKC,
TIOCA1,
TIOCB1,
TIOCA2,
TIOCB2
Single edge
specified
1.5 — — tcyc Figure 25.7
Both edges
specified
2.5 — —
Notes: 1. Selected with the SA1 and SA0 bits in the system control register 2 (SYSCR2).
2. The value in parentheses is tOSC (max.) when an external clock is used.
3. For details on the power-on reset characteristics, refer to table 25.20 and figure 25.1.
4. The characteristic ranges from minimum to maximum values according to variations in
such as the temperature, power supply voltage, and production lot. When designing the
system, consider the specifications fully. For the actual data of this product, see our
website.
Rev. 1.00, 07/04, page 497 of 570
Table 25.15 Serial Interface Timing
VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified.
Values Reference
Item Symbol Test Condition Min. Typ. Max. Unit Figure
Asynchronous tscyc 4 — — Figure 25.5 Input clock
cycle Clocked
synchronous
6 — —
tcyc or tsubcyc
Input clock pulse width tSCKW 0.4 — 0.6 tscyc Figure 25.5
Transmit data delay time
(clocked synchronous)
tTXD — 1 tcyc or tsubcyc Figure 25.6
Receive data setup time
(clocked synchronous)
tRXS 400.0 — — ns Figure 25.6
Receive data hold time
(clocked synchronous)
tRXH 400.0 — — ns Figure 25.6
Rev. 1.00, 07/04, page 498 of 570
Table 25.16 I2C Bus Interface Timing
VCC = 1.8 V to 3.6 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise specified.
Test Values Reference
Item Symbol Condition Min. Typ. Max. Unit Figure
SCL input cycle time tSCL 12tcyc + 600 — — ns Figure 25.8
SCL input high width tSCLH 3tcyc + 300 — — ns
SCL input low width tSCLL 5tcyc + 300 — — ns
SCL and SDA input fall time tSf — — 300 ns
SCL and SDA input spike
pulse removal time
tSP — — 1tcyc ns
SDA input bus-free
time
tBUF 5tcyc — — ns
Start condition input hold
time
tSTAH 3tcyc — — ns
Retransmission start
condition input setup time
tSTAS 3tcyc — — ns
Setup time for stop condition
input
tSTOS 3tcyc — — ns
Data-input setup time tSDAS 1tcyc + 20 — — ns
Data-input hold time tSDAH 0 — — ns
Capacitive load of
SCL and SDA
Cb 0 — 400 pF
SCL and SDA output fall
time
tSf — — 300 ns
Rev. 1.00, 07/04, page 499 of 570
25.4.4 A/D Converter Characteristics
Table 25.17 lists the A/D converter characteristics.
Table 25.17 A/D Converter Characteristics
VCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified.
Applicable Values
Item Symbol Pins Test Condition Min. Typ. Max. Unit Notes
Analog power supply
voltage
AVCC AVCC 1.8 — 3.6 V *1
Analog input voltage AVIN AN0 to AN7 –0.3 — AVCC +
0.3
V
AIOPE AVCC AVCC = 3.0 V — — 1.0 mA Analog power supply
current AISTOP1 AVCC — 600 — µA
*2
Reference
value
AISTOP2 AVCC — — 5 µA
*3
Analog input
capacitance
CAIN AN0 to AN7 — — 15.0 pF
Allowable signal
source impedance
RAIN — — 10.0 kΩ
Resolution (data
length)
— — 10 Bits
Nonlinearity error AVCC = 2.7 V to 3.6 V
VCC = 2.7 V to 3.6 V
— — ±3.5 LSB
AVCC = 2.0 V to 3.6 V
VCC = 2.0 V to 3.6 V
— — ±5.5
Other than above — — ±7.5
*4
Quantization error — — ±0.5 LSB
Absolute accuracy AVCC = 2.7 V to 3.6 V
VCC = 2.7 V to 3.6 V
— — ±4.0 LSB
AVCC = 2.0 V to 3.6 V
VCC = 2.0 V to 3.6 V
— — ±6.0
Other than above — — ±8.0
*4
Conversion time AVCC = 2.7 V to 3.6 V
VCC = 2.7 V to 3.6 V
12.4 — 124 µs
Other than above 31 — 124
Notes: 1. Set AVCC = VCC when the A/D converter is not used.
2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle.
3. AISTOP2 is the current at a reset and in standby, watch, subactive, and subsleep modes
while the A/D converter is idle.
4. Conversion time = 62 µs
Rev. 1.00, 07/04, page 500 of 570
25.4.5 ∆Σ A/D Converter Characteristics
Table 25.18 lists the ∆Σ A/D converter characteristics.
Table 25.18 ∆Σ A/D Converter Characteristics
Applicable Values
Item Symbol Pins Test Condition Min. Typ. Max. Unit Notes
Analog power supply
voltage
DVcc DVcc 2.2 3.6 V *1
DIOPE DVcc DVcc = 3.0 V,
fOVS = 1.6 MHz
TBD mA Reference
value
Analog power supply
current
DISTOP1 DVcc DVcc = 3.0 V,
fOVS = 1.6 MHz
TBD µA *2
Reference
value
DISTOP2 DVcc DVcc = 3.0 V,
fOVS = 1.6 MHz
TBD µA *3
Reference
value
Resolution 14 — — Bits
DVcc = 2.2 to 3.6 V,
Vcc = 2.2 to 3.6 V
0.25 1.6 TBD MHz
Oversampling frequency fOVS
DVcc = 2.7 to 3.6 V,
Vcc = 2.7 to 3.6 V
0.25 1.6 TBD MHz
DVcc = 2.2 to 3.6 V,
Vcc = 2.2 to 3.6 V
0.78 5.0 TBD kHz
Sampling frequency fS
DVcc = 2.7 to 3.6 V,
Vcc = 2.7 to 3.6 V
0.78 5.0 TBD kHz
DVcc = 2.2 to 3.6 V,
Vcc = 2.2 to 3.6 V
TBD 200 1280 µs
Conversion speed
DVcc = 2.7 to 3.6 V,
Vcc = 2.7 to 3.6 V
TBD 200 1280 µs
Integral lineality error PGA bypass
(DVcc = 3.0 V,
Vref = 2.7 V,
conversion speed =
160 µs)
— TBD — LSB
Rev. 1.00, 07/04, page 501 of 570
Values
Item Symbol
Applicable
Pins Test Condition Min. Typ. Max. Unit Notes
Differential lineality
error
PGA bypass
(DVcc = 3.0 V,
Vref = 2.7 V, conversion
speed = 160 µs)
— TBD — LSB
Offset error PGA bypass
(DVcc = 3.0 V,
Vref = 2.7 V, conversion
speed = 160 µs)
— TBD — mV
Full scale error PGA bypass
(DVcc = 3.0 V,
Vref = 2.7 V, conversion
speed = 160 µs)
— TBD — LSB
— 1/3 — V/V
— 1 — V/V
— 2 — V/V
PGA gain
— 4 — V/V
PGA = 1/3,
DVcc = 3.0 V
— TBD — mV
PGA = 1,
DVcc = 3.0 V
— TBD — mV
PGA = 2,
DVcc = 3.0 V
— TBD — mV
PGA gain error Tad
PGA = 4,
DVcc = 3.0 V
— TBD — mV
Internal reference
voltage
REF — TBD — V *4
External reference
voltage
V
ref 0.1 DVcc — 0.9 DVcc V
Rev. 1.00, 07/04, page 502 of 570
Values
Item Symbol
Applicable
Pins Test Condition Min. Typ. Max. Unit Notes
Analog data input
voltage
Ain Ain1, Ain2 PGA = 1/3 0.3 — 2.7 Vref
(2.7 Vref
< DVcc)
V
PGA = 1, bypass 0.1 — Vref V
PGA = 2 0.1 — 0.5 Vref V
PGA = 4 0.1 — 0.25 Vref V
Operating temperature Ta 0 — 50 °C
Notes: 1. Set DVcc = Vcc when the ∆Σ A/D converter is not used.
2. DISTOP1 is the current in active and sleep modes while the ∆Σ A/D converter is idle.
3. DISTOP2 is the current at a reset and in standby, watch, subactive, and subsleep modes
while the ∆Σ A/D converter is idle.
4. BGR stabilization time = 10 µs (Ta = 25°C, Vcc = 3.0 V)
Rev. 1.00, 07/04, page 503 of 570
25.4.6 LCD Characteristics
Table 25.19 shows the LCD characteristics.
Table 25.19 LCD Characteristics
VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified.
Values
Item Symbol
Applicable
Pins Test Condition Min. Typ. Max. Unit Notes
Segment driver drop
voltage
VDS SEG1 to
SEG32
ID = 2 µA
V1 = 2.7 V to 3.6 V
— — 0.6 V *1
Common driver drop
voltage
VDC COM1 to
COM4
ID = 2 µA
V1 = 2.7 V to 3.6 V
— — 0.3 V *1
LCD power supply split-
resistance
RLCD Between V1 and VSS 1.5 3.0 7.0 MΩ
LCD display voltage VLCD V1 2.2 — 3.6 V *2
V3 power supply
voltage
VLCD3 V3 Between V3 and VSS 0.9 1.0 1.1 V *3*4
V2 power supply
voltage
VLCD2 V2 Between V2 and VSS — 2.0
(VLCD3 ×
2)
— V *3*4
V1 power supply
voltage
VLCD1 V1 Between V1 and VSS — 3.0
(VLCD3 ×
3)
— V *3*4
3-V constant voltage
LCD power supply
circuit current
consumption
ILCD Vcc VCC = 3.0 V
Booster clock:
125 kHz
— 20 — µA Reference
value*4*5
Notes: 1. The voltage drop from power supply pins V1, V2, V3, and VSS to each segment pin or
common pin.
2. When the LCD display voltage is supplied from an external power source, ensure that
the following relationship is maintained: V1 ≥ V2 ≥ V3 ≥ VSS.
3. The value when the LCD power supply split-resistor is separated and 3-V constant
voltage power supply circuit is driven.
4. For details on the register (BGRMR) setting range when the voltage of the V3 pin is set
to 1.0 V, refer to section 20.3.5, BGR Control Register (BGRMR).
5. Includes the current consumption of the band-gap reference circuit (operation).
Rev. 1.00, 07/04, page 504 of 570
25.4.7 Power-On Reset Circuit Characteristics
Table 25.20 lists the power-on reset circuit characteristics.
Table 25.20 Power-On Reset Circuit Characteristics
VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V,
Ta = −20 to +75°C (regular specifications), Ta = −40 to +85°C (wide-ra nge specifications),
unless otherwise specified.
Values
Item Symbol Test Condition Min. Typ. Max. Unit Notes
Reset voltage V_rst 0.7Vcc 0.8Vcc 0.9Vcc V
Power supply rise time t_vtr The Vcc rise time should be at least twice as
fast as the RES rise time.
Reset count time t_out 0.8 — 4.0 µs
Count start time t_cr Adjustable by the value of the external
capacitor of the RES pin.
On-chip pull-up resistance Rp Vcc = 3.0 V 60 100 — kΩ
Vcc
t_vtr
t_vtr × 2
V_rst
t_cr t_out (eight states)
RES
Internal reset
signal
Figure 25.1 Power-On Reset Circuit Reset Timing
Rev. 1.00, 07/04, page 505 of 570
25.4.8 Watchdog Timer Characteristics
Table 25.21 Watchdog Timer Characteristics
VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V,
Ta = −20 to +75°C (regular specifications), Ta = −40 to +85°C (wide-ra nge specifications),
unless otherwise specified.
Applicable Values
Item Symbol Pins Test Condition Min. Typ. Max. Unit Notes
On-chip oscillator
overflow time
tovf 0.2 0.4 — s
Rev. 1.00, 07/04, page 506 of 570
25.5 Operation Timing
Figures 25.2 to 25.7 show operation timings.
tOSC, tw
VIH
VIL
tCPH tCPL
tCPr
OSC1
x1
tCPf
Figure 25.2 Clock Input Timing
RES
VIL
tREL
Figure 25.3 RES Low Width Timing
VIH
VIL
tIL
NMI, IRQ0, IRQ1, IRQ3,
IRQ4,TMIF, ADTRG,
WKP0 to WKP7,
IRQAEC, AEVL, AEVH
tIH
Figure 25.4 Input Timing
Rev. 1.00, 07/04, page 507 of 570
t
scyc
t
SCKW
SCK31
SCK32
Figure 25.5 SCK3 Input Clock Timing
tscyc
tTXD
tRXS tRXH
VOH*
VIH or VOH*
VIL or VOL*
VOL*
OH
OL
SCK31
SCK32
TXD31
TXD32
(transmit data)
RXD31
RXD32
(receive data)
Note: * Output timing reference levels
Output high
Output low
Load conditions are shown in figure 25.9.
V = 1/2 Vcc + 0.2 V
V = 0.8 V
Figure 25.6 SCI3 Input/Output Timing in Clocked Synchronous Mode
TCLKA to TCLKC
t
TCKWL
t
TCKWH
Figure 25.7 Clock Input Timing for TCLKA to TCLKC Pins
Rev. 1.00, 07/04, page 508 of 570
SCL
VIH
VIL
tSTAH
tBUF
P*S*
tSf tSr
tSCL tSDAH
tSCLH
tSCLL
SDA
Sr*
tSTAS
tSP tSTOS
tSDAS
P*
Note: * S, P, and Sr represent the following:
S: Start condition
P: Stop condition
Sr: Retransmission start condition
Figure 25.8 I2C Bus Interface Input/Output Timing
25.6 Output Load Circuit
VCC
2.4 kΩ
12 kΩ30 pF
LSI output pin
Figure 25.9 Output Load Condition
Rev. 1.00, 07/04, page 509 of 570
25.7 Resonator Equivalent Circuit
OSC1
L
S
C
S
C
O
R
S
OSC2
Crystal Resonator Parameters
(Manufacture's Publicly Relesed Values)
Frequency
(MHz)
R
S
(max.)
C
O
(max.)
Frequency
(MHz)
R
S
(max.)
C
O
(max.)
Frequency
(MHz)
R
S
(max.)
C
O
(max.)
Manufacturer
Ceramic Resonator Parameters (1)
(Manufacturer's Publicly Released Values)
Manufacturer
Murata Manufacturing Co., Ltd.
Murata Manufacturing
Co., Ltd.
Manufacturer
4.194
100 Ω
16 pF
10
30 Ω
16 pF
2
18.3 Ω
36.94 pF
Caramic Resonator Parameters (2)
(Manufacturer's Publicly Released Values)
10
4.6 Ω
32.31 pF
4.194
68 Ω
36.72 pF
NIHON DEMPA
KOGYO CO., LTD.
Figure 25.10 Resonator Equivalent Circuit
25.8 Usage Note
The F-ZTAT and masked ROM versions satisfy the electrical characteristics shown in this
manual, but actual electrical characteristic values, operating margins, noise margins, and other
properties may vary due to differences in manufacturing process, on-chip ROM, layout patterns,
and so on.
When system evaluation testing is carried out using the F-ZTAT version, the same evaluation
testing should also be conducted for the masked ROM version when changing over to that version.
Rev. 1.00, 07/04, page 510 of 570
Rev. 1.00, 07/04, page 511 of 570
Appendix
A. Instruction Set
A.1 Instruction List
Condition Code
Symbol Description
Rd General destination register
Rs General source register
Rn General register
ERd General destination register (address register or 32-bit register)
ERs General source register (address register or 32-bit register)
ERn General register (32-bit register)
(EAd) Destination operand
(EAs) Source operand
PC Program counter
SP Stack pointer
CCR Condition-code register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (overflow) flag in CCR
C C (carry) flag in CCR
disp Displacement
→ Transfer from the operand on the left to the operand on the right, or transition from
the state on the left to the state on the right
+ Addition of the operands on both sides
– Subtraction of the operand on the right from the operand on the left
× Multiplication of the operands on both sides
÷ Division of the operand on the left by the operand on the right
∧ Logical AND of the operands on both sides
∨ Logical OR of the operands on both sides
⊕ Logical exclusive OR of the operands on both sides
¬ NOT (logical complement)
( ), < > Contents of operand
Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers
(R0 to R7 and E0 to E7).
Rev. 1.00, 07/04, page 512 of 570
Condition Code Notation (cont)
Symbol Description
↔
Changed according to execution result
* Undetermined (no guaranteed value)
0 Cleared to 0
1 Set to 1
— Not affected by execution of the instruction
∆ Varies depending on conditions, described in notes
Rev. 1.00, 07/04, page 513 of 570
Table A.1 Instruction Set
1. Data Transfer Instructions
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States
*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
MOV.B #xx:8, Rd
MOV.B Rs, Rd
MOV.B @ERs, Rd
MOV.B @(d:16, ERs), Rd
MOV.B @(d:24, ERs), Rd
MOV.B @ERs+, Rd
MOV.B @aa:8, Rd
MOV.B @aa:16, Rd
MOV.B @aa:24, Rd
MOV.B Rs, @ERd
MOV.B Rs, @(d:16, ERd)
MOV.B Rs, @(d:24, ERd)
MOV.B Rs, @–ERd
MOV.B Rs, @aa:8
MOV.B Rs, @aa:16
MOV.B Rs, @aa:24
MOV.W #xx:16, Rd
MOV.W Rs, Rd
MOV.W @ERs, Rd
MOV.W @(d:16, ERs), Rd
MOV.W @(d:24, ERs), Rd
MOV.W @ERs+, Rd
MOV.W @aa:16, Rd
MOV.W @aa:24, Rd
MOV.W Rs, @ERd
MOV.W Rs, @(d:16, ERd)
MOV.W Rs, @(d:24, ERd)
Operation
#xx:8 → Rd8
Rs8 → Rd8
@ERs → Rd8
@(d:16, ERs) → Rd8
@(d:24, ERs) → Rd8
@ERs → Rd8
ERs32+1 → ERs32
@aa:8 → Rd8
@aa:16 → Rd8
@aa:24 → Rd8
Rs8 → @ERd
Rs8 → @(d:16, ERd)
Rs8 → @(d:24, ERd)
ERd32–1 → ERd32
Rs8 → @ERd
Rs8 → @aa:8
Rs8 → @aa:16
Rs8 → @aa:24
#xx:16 → Rd16
Rs16 → Rd16
@ERs → Rd16
@(d:16, ERs) → Rd16
@(d:24, ERs) → Rd16
@ERs → Rd16
ERs32+2 → @ERd32
@aa:16 → Rd16
@aa:24 → Rd16
Rs16 → @ERd
Rs16 → @(d:16, ERd)
Rs16 → @(d:24, ERd)
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
W
W
W
W
W
W
W
W
W
W
W
2
4
2
2
2
2
2
2
4
8
4
8
4
8
4
8
2
2
2
2
4
6
2
4
6
4
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
2
4
6
10
6
4
6
8
4
6
10
6
4
6
8
4
2
4
6
10
6
6
8
4
6
10
Normal
Advanced
↔
↔
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MOV
Rev. 1.00, 07/04, page 514 of 570
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
MOV.W Rs, @–ERd
MOV.W Rs, @aa:16
MOV.W Rs, @aa:24
MOV.L #xx:32, ERd
MOV.L ERs, ERd
MOV.L @ERs, ERd
MOV.L @(d:16, ERs), ERd
MOV.L @(d:24, ERs), ERd
MOV.L @ERs+, ERd
MOV.L @aa:16, ERd
MOV.L @aa:24, ERd
MOV.L ERs, @ERd
MOV.L ERs, @(d:16, ERd)
MOV.L ERs, @(d:24, ERd)
MOV.L ERs, @–ERd
MOV.L ERs, @aa:16
MOV.L ERs, @aa:24
POP.W Rn
POP.L ERn
PUSH.W Rn
PUSH.L ERn
MOVFPE @aa:16, Rd
MOVTPE Rs, @aa:16
Operation
ERd32–2 → ERd32
Rs16 → @ERd
Rs16 → @aa:16
Rs16 → @aa:24
#xx:32 → ERd32
ERs32 → ERd32
@ERs → ERd32
@(d:16, ERs) → ERd32
@(d:24, ERs) → ERd32
@ERs → ERd32
ERs32+4 → ERs32
@aa:16 → ERd32
@aa:24 → ERd32
ERs32 → @ERd
ERs32 → @(d:16, ERd)
ERs32 → @(d:24, ERd)
ERd32–4 → ERd32
ERs32 → @ERd
ERs32 → @aa:16
ERs32 → @aa:24
@SP → Rn16
SP+2 → SP
@SP → ERn32
SP+4 → SP
SP–2 → SP
Rn16 → @SP
SP–4 → SP
ERn32 → @SP
Cannot be used in
this LSI
Cannot be used in
this LSI
W
W
W
L
L
L
L
L
L
L
L
L
L
L
L
L
L
W
L
W
L
B
B
6
2
4
4
6
10
6
10
2
4
4
4
6
6
8
6
8
4
4
2
4
2
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
6
8
6
2
8
10
14
10
10
12
8
10
14
10
10
12
6
10
6
10
Normal
Advanced
↔
↔
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Cannot be used in
this LSI
Cannot be used in
this LSI
MOV
POP
PUSH
MOVFPE
MOVTPE
Rev. 1.00, 07/04, page 515 of 570
2. Arithmetic Instructions
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
ADD.B #xx:8, Rd
ADD.B Rs, Rd
ADD.W #xx:16, Rd
ADD.W Rs, Rd
ADD.L #xx:32, ERd
ADD.L ERs, ERd
ADDX.B #xx:8, Rd
ADDX.B Rs, Rd
ADDS.L #1, ERd
ADDS.L #2, ERd
ADDS.L #4, ERd
INC.B Rd
INC.W #1, Rd
INC.W #2, Rd
INC.L #1, ERd
INC.L #2, ERd
DAA Rd
SUB.B Rs, Rd
SUB.W #xx:16, Rd
SUB.W Rs, Rd
SUB.L #xx:32, ERd
SUB.L ERs, ERd
SUBX.B #xx:8, Rd
SUBX.B Rs, Rd
SUBS.L #1, ERd
SUBS.L #2, ERd
SUBS.L #4, ERd
DEC.B Rd
DEC.W #1, Rd
DEC.W #2, Rd
Operation
Rd8+#xx:8 → Rd8
Rd8+Rs8 → Rd8
Rd16+#xx:16 → Rd16
Rd16+Rs16 → Rd16
ERd32+#xx:32 →
ERd32
ERd32+ERs32 →
ERd32
Rd8+#xx:8 +C → Rd8
Rd8+Rs8 +C → Rd8
ERd32+1 → ERd32
ERd32+2 → ERd32
ERd32+4 → ERd32
Rd8+1 → Rd8
Rd16+1 → Rd16
Rd16+2 → Rd16
ERd32+1 → ERd32
ERd32+2 → ERd32
Rd8 decimal adjust
→ Rd8
Rd8–Rs8 → Rd8
Rd16–#xx:16 → Rd16
Rd16–Rs16 → Rd16
ERd32–#xx:32 → ERd32
ERd32–ERs32 → ERd32
Rd8–#xx:8–C → Rd8
Rd8–Rs8–C → Rd8
ERd32–1 → ERd32
ERd32–2 → ERd32
ERd32–4 → ERd32
Rd8–1 → Rd8
Rd16–1 → Rd16
Rd16–2 → Rd16
B
B
W
W
L
L
B
B
L
L
L
B
W
W
L
L
B
B
W
W
L
L
B
B
L
L
L
B
W
W
2
4
6
2
4
6
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1)
(1)
(2)
(2)
—
—
—
—
—
—
—
—
*
(1)
(1)
(2)
(2)
—
—
—
—
—
—
2
2
4
2
6
2
2
2
2
2
2
2
2
2
2
2
2
2
4
2
6
2
2
2
2
2
2
2
2
2
Normal
Advanced
↔
↔
↔
↔↔↔↔↔↔
↔↔↔↔↔↔↔
—
—
—
—
—
—
↔↔↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔
(3)
(3)
—
—
—
(3)
(3)
—
—
—
↔↔↔
↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔
—
—
—
*
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
↔
↔
↔
↔
↔
↔
↔
↔
↔↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔↔↔↔↔
↔
↔
↔
↔
↔↔↔
↔↔↔
↔↔↔
ADD
ADDX
ADDS
INC
DAA
SUB
SUBX
SUBS
DEC
Rev. 1.00, 07/04, page 516 of 570
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States
*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
DEC.L #1, ERd
DEC.L #2, ERd
DAS.Rd
MULXU. B Rs, Rd
MULXU. W Rs, ERd
MULXS. B Rs, Rd
MULXS. W Rs, ERd
DIVXU. B Rs, Rd
DIVXU. W Rs, ERd
DIVXS. B Rs, Rd
DIVXS. W Rs, ERd
CMP.B #xx:8, Rd
CMP.B Rs, Rd
CMP.W #xx:16, Rd
CMP.W Rs, Rd
CMP.L #xx:32, ERd
CMP.L ERs, ERd
Operation
ERd32–1 → ERd32
ERd32–2 → ERd32
Rd8 decimal adjust
→ Rd8
Rd8 × Rs8 → Rd16
(unsigned multiplication)
Rd16 × Rs16 → ERd32
(unsigned multiplication)
Rd8 × Rs8 → Rd16
(signed multiplication)
Rd16 × Rs16 → ERd32
(signed multiplication)
Rd16 ÷ Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
(unsigned division)
ERd32 ÷ Rs16 → ERd32
(Ed: remainder,
Rd: quotient)
(unsigned division)
Rd16 ÷ Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
(signed division)
ERd32 ÷ Rs16 → ERd32
(Ed: remainder,
Rd: quotient)
(signed division)
Rd8–#xx:8
Rd8–Rs8
Rd16–#xx:16
Rd16–Rs16
ERd32–#xx:32
ERd32–ERs32
L
L
B
B
W
B
W
B
W
B
W
B
B
W
W
L
L
2
4
6
2
2
2
2
2
4
4
2
2
4
4
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
2
2
14
22
16
24
14
22
16
24
2
2
4
2
4
2
Normal
Advanced
↔
↔
↔
—
—
*
—
—
—
—
—
—
—
—
(1)
(1)
(2)
(2)
↔
↔
↔
↔
↔
*
—
—
—
—
—
—
—
—
—
—
(7)
(7)
(7)
(7)
—
—
(6)
(6)
(8)
(8)
↔
↔
↔
↔
—
—
—
—
—
—
—
—
—
—
—
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
DEC
DAS
MULXU
MULXS
DIVXU
DIVXS
CMP
Rev. 1.00, 07/04, page 517 of 570
Mnemonic Operation
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States
*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
NEG.B Rd
NEG.W Rd
NEG.L ERd
EXTU.W Rd
EXTU.L ERd
EXTS.W Rd
EXTS.L ERd
0–Rd8 → Rd8
0–Rd16 → Rd16
0–ERd32 → ERd32
0 → (<bits 15 to 8>
of Rd16)
0 → (<bits 31 to 16>
of ERd32)
(<bit 7> of Rd16) →
(<bits 15 to 8> of Rd16)
(<bit 15> of ERd32) →
(<bits 31 to 16> of
ERd32)
B
W
L
W
L
W
L
2
2
2
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
2
2
2
2
2
2
2
Normal
Advanced
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
0
0
0
0
0
0
—
—
—
—
↔↔↔↔
↔↔
NEG
EXTU
EXTS
Rev. 1.00, 07/04, page 518 of 570
3. Logic Instructions
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States
*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
AND.B #xx:8, Rd
AND.B Rs, Rd
AND.W #xx:16, Rd
AND.W Rs, Rd
AND.L #xx:32, ERd
AND.L ERs, ERd
OR.B #xx:8, Rd
OR.B Rs, Rd
OR.W #xx:16, Rd
OR.W Rs, Rd
OR.L #xx:32, ERd
OR.L ERs, ERd
XOR.B #xx:8, Rd
XOR.B Rs, Rd
XOR.W #xx:16, Rd
XOR.W Rs, Rd
XOR.L #xx:32, ERd
XOR.L ERs, ERd
NOT.B Rd
NOT.W Rd
NOT.L ERd
Operation
Rd8∧#xx:8 → Rd8
Rd8∧Rs8 → Rd8
Rd16∧#xx:16 → Rd16
Rd16∧Rs16 → Rd16
ERd32∧#xx:32 → ERd32
ERd32∧ERs32 → ERd32
Rd8⁄#xx:8 → Rd8
Rd8⁄Rs8 → Rd8
Rd16⁄#xx:16 → Rd16
Rd16⁄Rs16 → Rd16
ERd32⁄#xx:32 → ERd32
ERd32⁄ERs32 → ERd32
Rd8⊕#xx:8 → Rd8
Rd8⊕Rs8 → Rd8
Rd16⊕#xx:16 → Rd16
Rd16⊕Rs16 → Rd16
ERd32⊕#xx:32 → ERd32
ERd32⊕ERs32 → ERd32
¬ Rd8 → Rd8
¬ Rd16 → Rd16
¬ Rd32 → Rd32
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
B
W
L
2
4
6
2
4
6
2
4
6
2
2
4
2
2
4
2
2
4
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
2
4
2
6
4
2
2
4
2
6
4
2
2
4
2
6
4
2
2
2
Normal
Advanced
↔
↔
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AND
OR
XOR
NOT
Rev. 1.00, 07/04, page 519 of 570
4. Shift Instructions
Mnemonic
Operand Size
No. of
States*1
Condition Code
IHNZVC
SHAL.B Rd
SHAL.W Rd
SHAL.L ERd
SHAR.B Rd
SHAR.W Rd
SHAR.L ERd
SHLL.B Rd
SHLL.W Rd
SHLL.L ERd
SHLR.B Rd
SHLR.W Rd
SHLR.L ERd
ROTXL.B Rd
ROTXL.W Rd
ROTXL.L ERd
ROTXR.B Rd
ROTXR.W Rd
ROTXR.L ERd
ROTL.B Rd
ROTL.W Rd
ROTL.L ERd
ROTR.B Rd
ROTR.W Rd
ROTR.L ERd
B
W
L
B
W
L
B
W
L
B
W
L
B
W
L
B
W
L
B
W
L
B
W
L
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Normal
Advanced
↔
↔
↔
↔
Addressing Mode and
Instruction Length (bytes)
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Operation
MSB LSB
0
C
MSB LSB
0
C
C
MSB LSB
0C
MSB LSB
C
MSB LSB
C
MSB LSB
C
MSB LSB
C
MSB LSB
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SHAL
SHAR
SHLL
SHLR
ROTXL
ROTXR
ROTL
ROTR
Rev. 1.00, 07/04, page 520 of 570
5. Bit-Manipulation Instructions
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States
*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
BSET #xx:3, Rd
BSET #xx:3, @ERd
BSET #xx:3, @aa:8
BSET Rn, Rd
BSET Rn, @ERd
BSET Rn, @aa:8
BCLR #xx:3, Rd
BCLR #xx:3, @ERd
BCLR #xx:3, @aa:8
BCLR Rn, Rd
BCLR Rn, @ERd
BCLR Rn, @aa:8
BNOT #xx:3, Rd
BNOT #xx:3, @ERd
BNOT #xx:3, @aa:8
BNOT Rn, Rd
BNOT Rn, @ERd
BNOT Rn, @aa:8
BTST #xx:3, Rd
BTST #xx:3, @ERd
BTST #xx:3, @aa:8
BTST Rn, Rd
BTST Rn, @ERd
BTST Rn, @aa:8
BLD #xx:3, Rd
Operation
(#xx:3 of Rd8) ← 1
(#xx:3 of @ERd) ← 1
(#xx:3 of @aa:8) ← 1
(Rn8 of Rd8) ← 1
(Rn8 of @ERd) ← 1
(Rn8 of @aa:8) ← 1
(#xx:3 of Rd8) ← 0
(#xx:3 of @ERd) ← 0
(#xx:3 of @aa:8) ← 0
(Rn8 of Rd8) ← 0
(Rn8 of @ERd) ← 0
(Rn8 of @aa:8) ← 0
(#xx:3 of Rd8) ←
¬ (#xx:3 of Rd8)
(#xx:3 of @ERd) ←
¬ (#xx:3 of @ERd)
(#xx:3 of @aa:8) ←
¬ (#xx:3 of @aa:8)
(Rn8 of Rd8) ←
¬ (Rn8 of Rd8)
(Rn8 of @ERd) ←
¬ (Rn8 of @ERd)
(Rn8 of @aa:8) ←
¬ (Rn8 of @aa:8)
¬ (#xx:3 of Rd8) → Z
¬ (#xx:3 of @ERd) → Z
¬ (#xx:3 of @aa:8) → Z
¬ (Rn8 of @Rd8) → Z
¬ (Rn8 of @ERd) → Z
¬ (Rn8 of @aa:8) → Z
(#xx:3 of Rd8) → C
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
2
2
2
2
2
2
2
2
2
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
8
8
2
8
8
2
8
8
2
8
8
2
8
8
2
8
8
2
6
6
2
6
6
2
Normal
Advanced
↔↔↔↔↔↔
↔
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BSET
BCLR
BNOT
BTST
BLD
Rev. 1.00, 07/04, page 521 of 570
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States
*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
BLD #xx:3, @ERd
BLD #xx:3, @aa:8
BILD #xx:3, Rd
BILD #xx:3, @ERd
BILD #xx:3, @aa:8
BST #xx:3, Rd
BST #xx:3, @ERd
BST #xx:3, @aa:8
BIST #xx:3, Rd
BIST #xx:3, @ERd
BIST #xx:3, @aa:8
BAND #xx:3, Rd
BAND #xx:3, @ERd
BAND #xx:3, @aa:8
BIAND #xx:3, Rd
BIAND #xx:3, @ERd
BIAND #xx:3, @aa:8
BOR #xx:3, Rd
BOR #xx:3, @ERd
BOR #xx:3, @aa:8
BIOR #xx:3, Rd
BIOR #xx:3, @ERd
BIOR #xx:3, @aa:8
BXOR #xx:3, Rd
BXOR #xx:3, @ERd
BXOR #xx:3, @aa:8
BIXOR #xx:3, Rd
BIXOR #xx:3, @ERd
BIXOR #xx:3, @aa:8
Operation
(#xx:3 of @ERd) → C
(#xx:3 of @aa:8) → C
¬ (#xx:3 of Rd8) → C
¬ (#xx:3 of @ERd) → C
¬ (#xx:3 of @aa:8) → C
C → (#xx:3 of Rd8)
C → (#xx:3 of @ERd24)
C → (#xx:3 of @aa:8)
¬ C → (#xx:3 of Rd8)
¬ C → (#xx:3 of @ERd24)
¬ C → (#xx:3 of @aa:8)
C∧(#xx:3 of Rd8) → C
C∧(#xx:3 of @ERd24) → C
C∧(#xx:3 of @aa:8) → C
C∧ ¬ (#xx:3 of Rd8) → C
C∧ ¬ (#xx:3 of @ERd24) → C
C∧ ¬ (#xx:3 of @aa:8) → C
C∨(#xx:3 of Rd8) → C
C∨(#xx:3 of @ERd24) → C
C∨(#xx:3 of @aa:8) → C
C∨ ¬ (#xx:3 of Rd8) → C
C∨ ¬ (#xx:3 of @ERd24) → C
C∨ ¬ (#xx:3 of @aa:8) → C
C⊕(#xx:3 of Rd8) → C
C⊕(#xx:3 of @ERd24) → C
C⊕(#xx:3 of @aa:8) → C
C⊕ ¬ (#xx:3 of Rd8) → C
C⊕ ¬ (#xx:3 of @ERd24) → C
C⊕ ¬ (#xx:3 of @aa:8) → C
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
2
2
2
2
2
2
2
2
2
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6
6
2
6
6
2
8
8
2
8
8
2
6
6
2
6
6
2
6
6
2
6
6
2
6
6
2
6
6
Normal
Advanced
↔↔↔↔↔
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔
BLD
BILD
BIST
BST
BAND
BIAND
BOR
BIOR
BXOR
BIXOR
Rev. 1.00, 07/04, page 522 of 570
6. Branching Instructions
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Mnemonic
Operand Size
No. of
States
*1
Condition Code
IHNZVC
BRA d:8 (BT d:8)
BRA d:16 (BT d:16)
BRN d:8 (BF d:8)
BRN d:16 (BF d:16)
BHI d:8
BHI d:16
BLS d:8
BLS d:16
BCC d:8 (BHS d:8)
BCC d:16 (BHS d:16)
BCS d:8 (BLO d:8)
BCS d:16 (BLO d:16)
BNE d:8
BNE d:16
BEQ d:8
BEQ d:16
BVC d:8
BVC d:16
BVS d:8
BVS d:16
BPL d:8
BPL d:16
BMI d:8
BMI d:16
BGE d:8
BGE d:16
BLT d:8
BLT d:16
BGT d:8
BGT d:16
BLE d:8
BLE d:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
Normal
Advanced
Addressing Mode and
Instruction Length (bytes)
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
Operation
Always
Never
C∨ Z = 0
C∨ Z = 1
C = 0
C = 1
Z = 0
Z = 1
V = 0
V = 1
N = 0
N = 1
N⊕V = 0
N⊕V = 1
Z∨ (N⊕V) = 0
Z∨ (N⊕V) = 1
If condition
is true then
PC ← PC+d
else next;
Branch
Condition
Bcc
Rev. 1.00, 07/04, page 523 of 570
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States
*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
JMP @ERn
JMP @aa:24
JMP @@aa:8
BSR d:8
BSR d:16
JSR @ERn
JSR @aa:24
JSR @@aa:8
RTS
Operation
PC ← ERn
PC ← aa:24
PC ← @aa:8
PC → @–SP
PC ← PC+d:8
PC → @–SP
PC ← PC+d:16
PC → @–SP
PC ← ERn
PC → @–SP
PC ← aa:24
PC → @–SP
PC ← @aa:8
PC ← @SP+
—
—
—
—
—
—
—
—
—
2
2
4
4
2
4
2
2
2
—
—
—
—
—
—
—
—
—
4
6
Normal
Advanced
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8
6
8
6
8
8
8
10
8
10
8
10
12
10
JMP
BSR
JSR
RTS
Rev. 1.00, 07/04, page 524 of 570
7. System Control Instructions
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States
*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
RTE
SLEEP
LDC #xx:8, CCR
LDC Rs, CCR
LDC @ERs, CCR
LDC @(d:16, ERs), CCR
LDC @(d:24, ERs), CCR
LDC @ERs+, CCR
LDC @aa:16, CCR
LDC @aa:24, CCR
STC CCR, Rd
STC CCR, @ERd
STC CCR, @(d:16, ERd)
STC CCR, @(d:24, ERd)
STC CCR, @–ERd
STC CCR, @aa:16
STC CCR, @aa:24
ANDC #xx:8, CCR
ORC #xx:8, CCR
XORC #xx:8, CCR
NOP
Operation
CCR ← @SP+
PC ← @SP+
Transition to power-
down state
#xx:8 → CCR
Rs8 → CCR
@ERs → CCR
@(d:16, ERs) → CCR
@(d:24, ERs) → CCR
@ERs → CCR
ERs32+2 → ERs32
@aa:16 → CCR
@aa:24 → CCR
CCR → Rd8
CCR → @ERd
CCR → @(d:16, ERd)
CCR → @(d:24, ERd)
ERd32–2 → ERd32
CCR → @ERd
CCR → @aa:16
CCR → @aa:24
CCR∧#xx:8 → CCR
CCR∨#xx:8 → CCR
CCR⊕#xx:8 → CCR
PC ← PC+2
—
—
B
B
W
W
W
W
W
W
B
W
W
W
W
W
W
B
B
B
—
2
2
2
2
2
2
4
4
6
10
6
10
4
4
6
8
6
8
2
10
2
2
2
6
8
12
8
8
10
2
6
8
12
8
8
10
2
2
2
2
Normal
Advanced
↔
↔
↔
↔
↔
↔
↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔↔↔
RTE
SLEEP
LDC
STC
ANDC
ORC
XORC
NOP
Rev. 1.00, 07/04, page 525 of 570
8. Block Transfer Instructions
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
EEPMOV. B
EEPMOV. W
Operation
if R4L ≠ 0 then
repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4L–1 → R4L
until R4L=0
else next
if R4 ≠ 0 then
repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4–1 → R4
until R4=0
else next
—
—
4
4
—
—
8+
4n*2
Normal
Advanced
—
—
—
—
—
—
—
—
—
—8+
4n*2
EEPMOV
Notes: 1. The number of states in cases where the instruction code and its operands are located
in on-chip memory is shown here. For other cases, see Appendix A.3, Number of
Execution States.
2. n is the value set in register R4L or R4.
(1) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0.
(2) Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0.
(3) Retains its previous value when the result is zero; otherwise cleared to 0.
(4) Set to 1 when the adjustment produces a carry; otherwise retains its previous value.
(5) The number of states required for execution of an instruction that transfers data in
synchronization with the E clock is variable.
(6) Set to 1 when the divisor is negative; otherwise cleared to 0.
(7) Set to 1 when the divisor is zero; otherwise cleared to 0.
(8) Set to 1 when the quotient is negative; otherwise cleared to 0.
Rev. 1.00, 07/04, page 526 of 570
A.2 Operation Code Map
Table A.2 Operation Code Map (1)
AH
AL 0123456789ABCDEF
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
NOP
BRA
MULXU
BSET
BRN
DIVXU
BNOT
STC
BHI
MULXU
BCLR
LDC
BLS
DIVXU
BTST
ORC
OR.B
BCC
RTS
OR
XORC
XOR.B
BCS
BSR
XOR
BOR
BIOR
BXOR
BIXOR
BAND
BIAND
ANDC
AND.B
BNE
RTE
AND
LDC
BEQ
TRAPA
BLD
BILD
BST
BIST
BVC
MOV
BPL
JMP
BMI
EEPMOV
ADDX
SUBX
BGT
JSR
BLE
MOV
ADD
ADDX
CMP
SUBX
OR
XOR
AND
MOV
Instruction when most significant bit of BH is 0.
Instruction when most significant bit of BH is 1.
Instruction code:
Table A-2
(2)
Table A-2
(2)
Table A-2
(2)
Table A-2
(2)
Table A-2
(2)
BVS BLTBGE
BSR
Table A-2
(2)
Table A-2
(2)
Table A-2
(2)
Table A-2
(2)
Table A-2
(2)
Table A-2
(2)
Table A-2
(2)
Table A-2
(2)
Table A-2
(2)
Table A-2
(2)
Table A-2
(3)
1st byte 2nd byte
AH BHAL BL
ADD
SUB
MOV
CMP
MOV.B
Rev. 1.00, 07/04, page 527 of 570
Table A.2 Operation Code Map (2)
AH AL
BH 0123456789ABCDEF
01
0A
0B
0F
10
11
12
13
17
1A
1B
1F
58
79
7A
MOV
INC
ADDS
DAA
DEC
SUBS
DAS
BRA
MOV
MOV
BHI
CMP
CMP
LDC/STC
BCC
OR
OR
BPL BGT
Instruction code:
BVS
SLEEP
BVC BGE
Table A-2
(3)
Table A-2
(3)
Table A-2
(3)
ADD
MOV
SUB
CMP
BNE
AND
AND
INC
EXTU
DEC
BEQ
INC
EXTU
DEC
BCS
XOR
XOR
SHLL
SHLR
ROTXL
ROTXR
NOT
BLS
SUB
SUB
BRN
ADD
ADD
INC
EXTS
DEC
BLT
INC
EXTS
DEC
BLE
SHAL
SHAR
ROTL
ROTR
NEG
BMI
1st byte 2nd byte
AH BHAL BL
SUB
ADDS
SHLL
SHLR
ROTXL
ROTXR
NOT
SHAL
SHAR
ROTL
ROTR
NEG
Rev. 1.00, 07/04, page 528 of 570
Table A.2 Operation Code Map (3)
AH
ALBH
BLCH
CL
0123456789ABCDEF
01406
01C05
01D05
01F06
7Cr06
7Cr07
7Dr06
7Dr07
7Eaa6
7Eaa7
7Faa6
7Faa7
MULXS
BSET
BSET
BSET
BSET
DIVXS
BNOT
BNOT
BNOT
BNOT
MULXS
BCLR
BCLR
BCLR
BCLR
DIVXS
BTST
BTST
BTST
BTST
OR XOR
BOR
BIOR
BXOR
BIXOR
BAND
BIAND
AND
BLD
BILD
BST
BIST
Instruction when most significant bit of DH is 0.
Instruction when most significant bit of DH is 1.
Instruction code:
*
*
*
*
*
*
*
*
1
1
1
1
2
2
2
2
BOR
BIOR
BXOR
BIXOR
BAND
BIAND
BLD
BILD
BST
BIST
Notes: 1.
2.
r is the register designation field.
aa is the absolute address field.
1st byte 2nd byte
AH BHAL BL
3rd byte
CH DHCL DL
4th byte
LDC
STC
LDC LDC LDC
STC STC STC
Rev. 1.00, 07/04, page 529 of 570
A.3 Number of Execution States
The status of execution for each instruction of the H8/300H CPU and the method of calculating
the number of states required for instruction execution are shown below. Table A.4 shows the
number of cycles of each type occurring in each instruction, such as instruction fetch and data
read/write. Table A.3 shows the number of states required for each cycle. The total number of
states required for execution of an instruction can be calculated by the following expression:
Execution states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN
Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed.
BSET #0, @FF00
From table A.4:
I = L = 2, J = K = M = N= 0
From table A.3:
SI = 2, SL = 2
Number of states required for execution = 2 × 2 + 2 × 2 = 8
When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and
on-chip RAM is used for stack area.
JSR @@ 30
From table A.4:
I = 2, J = K = 1, L = M = N = 0
From table A.3:
SI = SJ = SK = 2
Number of states required for execution = 2 × 2 + 1 × 2+ 1 × 2 = 8
Rev. 1.00, 07/04, page 530 of 570
Table A.3 Number of Cycles in Each Instruction
Execution Status Access Location
(Instruction Cycle) On-Chip Memory On-Chip Peripheral Module
Instruction fetch SI 2 —
Branch address read SJ
Stack operation SK
Byte data access SL 2 or 3*
Word data access SM —
Internal operation SN 1
Note: * Depends on which on-chip peripheral module is accessed. See section 24.1, Register
Addresses (Address Order).
Rev. 1.00, 07/04, page 531 of 570
Table A.4 Number of Cycles in Each Instruction
Instruction
Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
ADD ADD.B #xx:8, Rd
ADD.B Rs, Rd
ADD.W #xx:16, Rd
ADD.W Rs, Rd
ADD.L #xx:32, ERd
ADD.L ERs, ERd
1
1
2
1
3
1
ADDS ADDS #1/2/4, ERd 1
ADDX ADDX #xx:8, Rd
ADDX Rs, Rd
1
1
AND AND.B #xx:8, Rd
AND.B Rs, Rd
AND.W #xx:16, Rd
AND.W Rs, Rd
AND.L #xx:32, ERd
AND.L ERs, ERd
1
1
2
1
3
2
ANDC ANDC #xx:8, CCR 1
BAND BAND #xx:3, Rd
BAND #xx:3, @ERd
BAND #xx:3, @aa:8
1
2
2
1
1
Bcc BRA d:8 (BT d:8)
BRN d:8 (BF d:8)
BHI d:8
BLS d:8
BCC d:8 (BHS d:8)
BCS d:8 (BLO d:8)
BNE d:8
BEQ d:8
BVC d:8
BVS d:8
BPL d:8
BMI d:8
BGE d:8
2
2
2
2
2
2
2
2
2
2
2
2
2
Rev. 1.00, 07/04, page 532 of 570
Instruction
Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
Bcc
BLT d:8
BGT d:8
BLE d:8
BRA d:16(BT d:16)
BRN d:16(BF d:16)
BHI d:16
BLS d:16
BCC d:16(BHS d:16)
BCS d:16(BLO d:16)
BNE d:16
BEQ d:16
BVC d:16
BVS d:16
BPL d:16
BMI d:16
BGE d:16
BLT d:16
BGT d:16
BLE d:16
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
BCLR BCLR #xx:3, Rd
BCLR #xx:3, @ERd
BCLR #xx:3, @aa:8
BCLR Rn, Rd
BCLR Rn, @ERd
BCLR Rn, @aa:8
1
2
2
1
2
2
2
2
2
2
BIAND BIAND #xx:3, Rd
BIAND #xx:3, @ERd
BIAND #xx:3, @aa:8
1
2
2
1
1
BILD BILD #xx:3, Rd
BILD #xx:3, @ERd
BILD #xx:3, @aa:8
1
2
2
1
1
Rev. 1.00, 07/04, page 533 of 570
Instruction
Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
BIOR BIOR #xx:3, Rd
BIOR #xx:3, @ERd
BIOR #xx:3, @aa:8
1
2
2
1
1
BIST BIST #xx:3, Rd
BIST #xx:3, @ERd
BIST #xx:3, @aa:8
1
2
2
2
2
BIXOR BIXOR #xx:3, Rd
BIXOR #xx:3, @ERd
BIXOR #xx:3, @aa:8
1
2
2
1
1
BLD BLD #xx:3, Rd
BLD #xx:3, @ERd
BLD #xx:3, @aa:8
1
2
2
1
1
BNOT BNOT #xx:3, Rd
BNOT #xx:3, @ERd
BNOT #xx:3, @aa:8
BNOT Rn, Rd
BNOT Rn, @ERd
BNOT Rn, @aa:8
1
2
2
1
2
2
2
2
2
2
BOR BOR #xx:3, Rd
BOR #xx:3, @ERd
BOR #xx:3, @aa:8
1
2
2
1
1
BSET BSET #xx:3, Rd
BSET #xx:3, @ERd
BSET #xx:3, @aa:8
BSET Rn, Rd
BSET Rn, @ERd
BSET Rn, @aa:8
1
2
2
1
2
2
2
2
2
2
BSR BSR d:8
BSR d:16
2
2
1
1
2
BST BST #xx:3, Rd
BST #xx:3, @ERd
BST #xx:3, @aa:8
1
2
2
2
2
Rev. 1.00, 07/04, page 534 of 570
Instruction
Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
BTST BTST #xx:3, Rd
BTST #xx:3, @ERd
BTST #xx:3, @aa:8
BTST Rn, Rd
BTST Rn, @ERd
BTST Rn, @aa:8
1
2
2
1
2
2
1
1
1
1
BXOR BXOR #xx:3, Rd
BXOR #xx:3, @ERd
BXOR #xx:3, @aa:8
1
2
2
1
1
CMP CMP.B #xx:8, Rd
CMP.B Rs, Rd
CMP.W #xx:16, Rd
CMP.W Rs, Rd
CMP.L #xx:32, ERd
CMP.L ERs, ERd
1
1
2
1
3
1
DAA DAA Rd 1
DAS DAS Rd 1
DEC DEC.B Rd
DEC.W #1/2, Rd
DEC.L #1/2, ERd
1
1
1
DUVXS DIVXS.B Rs, Rd
DIVXS.W Rs, ERd
2
2
12
20
DIVXU DIVXU.B Rs, Rd
DIVXU.W Rs, ERd
1
1
12
20
EEPMOV EEPMOV.B
EEPMOV.W
2
2
2n+2*1
2n+2*1
EXTS EXTS.W Rd
EXTS.L ERd
1
1
EXTU EXTU.W Rd
EXTU.L ERd
1
1
Rev. 1.00, 07/04, page 535 of 570
Instruction
Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
INC INC.B Rd
INC.W #1/2, Rd
INC.L #1/2, ERd
1
1
1
JMP JMP @ERn
JMP @aa:24
JMP @@aa:8
2
2
2
1
2
2
JSR JSR @ERn
JSR @aa:24
JSR @@aa:8
2
2
2
1
1
1
1
2
LDC LDC #xx:8, CCR
LDC Rs, CCR
LDC@ERs, CCR
LDC@(d:16, ERs), CCR
LDC@(d:24,ERs), CCR
LDC@ERs+, CCR
LDC@aa:16, CCR
LDC@aa:24, CCR
1
1
2
3
5
2
3
4
1
1
1
1
1
1
2
MOV MOV.B #xx:8, Rd
MOV.B Rs, Rd
MOV.B @ERs, Rd
MOV.B @(d:16, ERs), Rd
MOV.B @(d:24, ERs), Rd
MOV.B @ERs+, Rd
MOV.B @aa:8, Rd
MOV.B @aa:16, Rd
MOV.B @aa:24, Rd
MOV.B Rs, @Erd
MOV.B Rs, @(d:16, ERd)
MOV.B Rs, @(d:24, ERd)
MOV.B Rs, @-ERd
MOV.B Rs, @aa:8
1
1
1
2
4
1
1
2
3
1
2
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
Rev. 1.00, 07/04, page 536 of 570
Instruction
Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
MOV MOV.B Rs, @aa:16
MOV.B Rs, @aa:24
MOV.W #xx:16, Rd
MOV.W Rs, Rd
MOV.W @ERs, Rd
MOV.W @(d:16,ERs), Rd
MOV.W @(d:24,ERs), Rd
MOV.W @ERs+, Rd
MOV.W @aa:16, Rd
MOV.W @aa:24, Rd
MOV.W Rs, @ERd
MOV.W Rs, @(d:16,ERd)
MOV.W Rs, @(d:24,ERd)
2
3
2
1
1
2
4
1
2
3
1
2
4
1
1
1
1
1
1
1
1
1
1
1
2
MOV
MOV.W Rs, @-ERd
MOV.W Rs, @aa:16
MOV.W Rs, @aa:24
MOV.L #xx:32, ERd
MOV.L ERs, ERd
MOV.L @ERs, ERd
MOV.L @(d:16,ERs), ERd
MOV.L @(d:24,ERs), ERd
MOV.L @ERs+, ERd
MOV.L @aa:16, ERd
MOV.L @aa:24, ERd
MOV.L ERs,@ERd
MOV.L ERs, @(d:16,ERd)
MOV.L ERs, @(d:24,ERd)
MOV.L ERs, @-ERd
MOV.L ERs, @aa:16
MOV.L ERs, @aa:24
1
2
3
3
1
2
3
5
2
3
4
2
3
5
2
3
4
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
MOVFPE MOVFPE @aa:16, Rd*2 2 1
MOVTPE MOVTPE Rs,@aa:16*2 2 1
Rev. 1.00, 07/04, page 537 of 570
Instruction
Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
MULXS MULXS.B Rs, Rd
MULXS.W Rs, ERd
2
2
12
20
MULXU MULXU.B Rs, Rd
MULXU.W Rs, ERd
1
1
12
20
NEG NEG.B Rd
NEG.W Rd
NEG.L ERd
1
1
1
NOP NOP 1
NOT NOT.B Rd
NOT.W Rd
NOT.L ERd
1
1
1
OR OR.B #xx:8, Rd
OR.B Rs, Rd
OR.W #xx:16, Rd
OR.W Rs, Rd
OR.L #xx:32, ERd
OR.L ERs, ERd
1
1
2
1
3
2
ORC ORC #xx:8, CCR 1
POP POP.W Rn
POP.L ERn
1
2
1
2
2
2
PUSH PUSH.W Rn
PUSH.L ERn
1
2
1
2
2
2
ROTL ROTL.B Rd
ROTL.W Rd
ROTL.L ERd
1
1
1
ROTR ROTR.B Rd
ROTR.W Rd
ROTR.L ERd
1
1
1
ROTXL ROTXL.B Rd
ROTXL.W Rd
ROTXL.L ERd
1
1
1
Rev. 1.00, 07/04, page 538 of 570
Instruction
Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
ROTXR ROTXR.B Rd
ROTXR.W Rd
ROTXR.L ERd
1
1
1
RTE RTE 2 2 2
RTS RTS 2 1 2
SHAL SHAL.B Rd
SHAL.W Rd
SHAL.L ERd
1
1
1
SHAR SHAR.B Rd
SHAR.W Rd
SHAR.L ERd
1
1
1
SHLL SHLL.B Rd
SHLL.W Rd
SHLL.L ERd
1
1
1
SHLR SHLR.B Rd
SHLR.W Rd
SHLR.L ERd
1
1
1
SLEEP SLEEP 1
STC STC CCR, Rd
STC CCR, @ERd
STC CCR, @(d:16,ERd)
STC CCR, @(d:24,ERd)
STC CCR,@-ERd
STC CCR, @aa:16
STC CCR, @aa:24
1
2
3
5
2
3
4
1
1
1
1
1
1
2
SUB SUB.B Rs, Rd
SUB.W #xx:16, Rd
SUB.W Rs, Rd
SUB.L #xx:32, ERd
SUB.L ERs, ERd
1
2
1
3
1
SUBS SUBS #1/2/4, ERd 1
Rev. 1.00, 07/04, page 539 of 570
Instruction
Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
SUBX SUBX #xx:8, Rd
SUBX. Rs, Rd
1
1
XOR XOR.B #xx:8, Rd
XOR.B Rs, Rd
XOR.W #xx:16, Rd
XOR.W Rs, Rd
XOR.L #xx:32, ERd
XOR.L ERs, ERd
1
1
2
1
3
2
XORC XORC #xx:8, CCR 1
Notes: 1. n: Specified value in R4L. The source and destination operands are accessed n+1
times respectively.
2. It can not be used in this LSI.
Rev. 1.00, 07/04, page 540 of 570
A.4 Combinations of Instructions and Addressing Modes
Table A.5 Combinations of Instructions and Addressing Modes
Addressing Mode
MOV
POP, PUSH
MOVFPE,
MOVTPE
ADD, CMP
SUB
ADDX, SUBX
ADDS, SUBS
INC, DEC
DAA, DAS
MULXU,
MULXS,
DIVXU,
DIVXS
NEG
EXTU, EXTS
AND, OR, XOR
NOT
BCC, BSR
JMP, JSR
RTS
RTE
SLEEP
LDC
STC
ANDC, ORC,
XORC
NOP
Data
transfer
instructions
Arithmetic
operations
Logical
operations
Shift operations
Bit manipulations
Branching
instructions
System
control
instructions
Block data transfer instructions
BWL
—
—
BWL
WL
B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B
—
B
—
—
#xx
Rn
@ERn
@(d:16.ERn)
@(d:24.ERn)
@ERn+/@ERn
@aa:8
@aa:16
@aa:24
@(d:8.PC)
@(d:16.PC)
@@aa:8
—
BWL
—
—
BWL
BWL
B
L
BWL
B
BW
BWL
WL
BWL
BWL
BWL
B
—
—
—
—
—
B
B
—
—
—
BWL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B
—
—
—
—
W
W
—
—
—
BWL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
W
—
—
—
BWL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
W
—
—
—
BWL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
W
—
—
—
B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B
—
—
—
—
—
—
—
—
—
—
BWL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
W
—
—
—
BWL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
W
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
WL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BW
Functions Instructions
Rev. 1.00, 07/04, page 541 of 570
B. I/O Ports
B.1 I/O Port Block Diagrams
P16
V
CC
V
CC
PUCR16
PDR16
Internal data bus
PCR16
SBY (Low at a reset or in standby mode)
V
SS
SCKO4
SCKI4
SCKIE
SCKOE
SCI4 module
PDR1:
PCR1:
PUCR1:
Port data register 1
Port control register 1
Port pull-up control register 1
Figure B.1 (a) Port 1 Block Diagram (P16) (F-ZTAT Version)
P16
V
CC
V
CC
PUCR16
PDR16
PCR16
SBY
V
SS
PDR1:
PCR1:
PUCR1:
Port data register 1
Port control register 1
Port pull-up control register 1
Internal data bus
Figure B.1 (b) Port 1 Block Diagram (P16) (Masked ROM Version)
Rev. 1.00, 07/04, page 542 of 570
P1n
VCC
VCC
PUCR1n
TPU module
Internal data bus
TO1AE (P12)
TO1BE (P13)
TO2AE (P14)
TO2BE (P15)
TO1A (P12)
TO1B (P13)
TO2A (P14)
TO2B (P15)
TI1A (P12)
TI1B (P13)
TI2A (P14)
TI2B (P15)
TCLKA (P12)
TCLKB (P13)
TCLKC (P14)
PDR1n
PCR1n
SBY
VSS
PDR1:
PCR1:
PUCR1:
n = 5 to 2
Port data register 1
Port control register 1
Port pull-up control register 1
Figure B.1 (c) Port 1 Block Diagram (P15 to P12)
P1n
VCC
VCC
PUCR1n
Internal data bus
PMR1n
PDR1n
AEC module
AEVH(P10)
AEVL(P11)
PCR1n
SBY
VSS
PDR1:
PCR1:
PMR1:
PUCR1:
n = 1, 0
Port data register 1
Port control register 1
Port mode register 1
Port pull-up control register 1
Figure B.1 (d) Port 1 Block Diagram (P11, P10)
Rev. 1.00, 07/04, page 543 of 570
P37
VCC
VCC
PUCR37
PDR37
Internal data bus
PCR37
SCI4 module
SBY
VSS
SO4
TE4
PDR3:
PCR3:
PUCR3:
Port data register 3
Port control register 3
Port pull-up control register 3
Figure B.2 (a) Port 3 Block Diagram (P37) (F-ZTAT Version)
P37
V
CC
V
CC
PUCR37
PDR37
PCR37
SBY
V
SS
PDR3:
PCR3:
PUCR3:
Port data register 3
Port control register 3
Port pull-up control register 3
Internal data bus
Figure B.2 (b) Port 3 Block Diagram (P37) (Masked ROM Version)
Rev. 1.00, 07/04, page 544 of 570
P36
V
CC
V
CC
PUCR36
Internal data bus
PDR36
PCR36
SBY
V
SS
PDR3:
PCR3:
PUCR3:
Port data register 3
Port control register 3
Port pull-up control register 3
SCI4 module
SI
RE
Figure B.2 (c) Port 3 Block Diagram (P36) (F-ZTAT Version)
P36
V
CC
V
CC
PUCR36
PDR36
PCR36
SBY
V
SS
PDR3:
PCR3:
PUCR3:
Port data register 3
Port control register 3
Port pull-up control register 3
Internal data bus
Figure B.2 (d) Port 3 Block Diagram (P36) (Masked ROM Version)
Rev. 1.00, 07/04, page 545 of 570
P32 PDR32
SPC32
SCINV3
PCR32
SBY
V
SS
PDR3:
PCR:
Port data register 3
Port control register 3
V
SS
V
CC
SCI3_2 module
TXD32
Internal data bus
I
2
C bus 2 module
ICE
SCLO
SCLI
Figure B.2 (e) Port 3 Block Diagram (P32)
P31
V
CC
PDR31
Internal data bus
PCR31
SCINV2
SBY
V
SS
V
SS
PDR3:
PCR3:
Port data register 3
Port control register 3
RE32
RXD32
SCI3_2 module
ICE
SDAO
SDAI
I2C bus 2 module
Figure B.2 (f) Port 3 Block Diagram (P31)
Rev. 1.00, 07/04, page 546 of 570
P30
V
CC
V
CC
PUCR30
PMR30
PDR30
PCR30
SCI3_2 module
SBY
V
SS
SCKIE32
SCKOE32
SCKO32
SCKI32
PDR3:
PCR3:
PMR3:
PUCR3:
Port data register 3
Port control register 3
Port mode register 3
Port pull-up control register 3
RTC module
TMOW
Internal data bus
Figure B.2 (g) Port 3 Block Diagram (P30)
Rev. 1.00, 07/04, page 547 of 570
P42 PDR42
PCR42
PMR42
SBY
V
SS
PDR4:
PCR4:
PMR4:
Port data register 4
Port contol register 4
Port mode register 4
V
CC
SCINV1
TXD31/IrTXD
SCI3_1 module
TMOFH
Timer F module
Internal data bus
SPC31
Figure B.3 (a) Port 4 Block Diagram (P42)
Rev. 1.00, 07/04, page 548 of 570
P41
V
CC
SCI3_1 module
PDR41
PMR41
PCR41
Internal data bus
SBY
V
SS
PDR4:
PCR4:
PMR4:
Port data register 4
Port control register 4
Port mode register 4
RE31
RXD31/IrRXD
TMOFL
Timer F module
SCINV0
Figure B.3 (b) Port 4 Block Diagram (P41)
Rev. 1.00, 07/04, page 549 of 570
P40
V
CC
SCI3_1 module
PDR40
Internal data bus
PCR40
PMR40
SBY
V
SS
PDR4:
PCR4:
PMR4:
Port data register 4
Port control register 4
Port mode register 4
SCKIE31
SCKOE31
SCKO31
SCKI31
TMIF
Timer F module
Figure B.3 (c) Port 4 Block Diagram (P40)
Rev. 1.00, 07/04, page 550 of 570
P5n
VCC
VCC
PUCR5n
PMR5n
PDR5n
PCR5n
Internal data bus
SBY
VSS
WKP
n
PDR5:
PCR5:
PMR5:
PUCR5:
n = 7 to 0
Port data register 5
Port control register 5
Port mode register 5
Port pull-up control register 5
Figure B.4 Port 5 Block Diagram
P6n
V
CC
V
CC
PUCR6n
PDR6n
PCR6n
Internal data bus
SBY
V
SS
PDR6:
PCR6:
PUCR6:
n = 7 to 0
Port data register 6
Port control register 6
Port pull-up control register 6
Figure B.5 Port 6 Block Diagram
Rev. 1.00, 07/04, page 551 of 570
P7n
V
CC
PDR7n
PCR7n
Internal data bus
SBY
V
SS
PDR7:
PCR7:
n = 7 to 0
Port data register 7
Port control register 7
Figure B.6 Port 7 Block Diagram
P8n
V
CC
PDR8n
Internal data bus
PCR8n
SBY
V
SS
PDR8:
PCR8:
n = 7 to 0
Port data register 8
Port control register 8
Figure B.7 Port 8 Block Diagram
Rev. 1.00, 07/04, page 552 of 570
P93
V
CC
PDR93
PCR93
Internal data bus
SBY
V
SS
PDR9:
PCR9:
Port data register 9
Port control register 9
Figure B.8 (a) Port 9 Block Diagram (P93)
P92
V
CC
PMR92
PDR92
IRQ
4
PCR92
Internal data bus
SBY
V
SS
PDR9:
PCR9:
PMR9:
Port data register 9
Port control register 9
Port mode register 9
Figure B.8 (b) Port 9 Block Diagram (P92)
Rev. 1.00, 07/04, page 553 of 570
P9n
V
CC
PMR9n
Internal data bus
PDR9n
PCR9n
SBY
V
SS
PDR9:
PCR9:
PMR9:
Port data register 9
Port control register 9
Port mode register 9
n = 1, 0
PWMn+1
PWM module
Figure B.8 (c) Port 9 Block Diagram (P91, P90)
PAn
V
CC
PDRAn
PCRAn
Internal data bus
SBY
V
SS
PDRA:
PCRA:
n = 3 to 0
Port data register A
Port control register A
Figure B.9 Port A Block Diagram
Rev. 1.00, 07/04, page 554 of 570
PBn
DEC
∆Σ A/D module
Internal data bus
ADSSR5, ADSSR4
Ain1, Ain2
n = 7, 6
Figure B.10 (a) Port B Block Diagram (PB7, PB6)
PB5
DEC
Internal data bus
∆Σ A/D module
ADCR3, ADCR2
Vref
Figure B.10 (b) Port B Block Diagram (PB5)
Rev. 1.00, 07/04, page 555 of 570
PBn
DEC AMR3 to AMR0
V
IN
n = 2 to 0 m = 3, 1, 0
PMRBn
Internal data bus
A/D module
Figure B.10 (c) Port B Block Diagram (PB2 to PB0)
Rev. 1.00, 07/04, page 556 of 570
B.2 Port States in Each Operating St ate
Port
Reset
Sleep
(High-Speed/
Medium-Speed)
Subsleep
Standby
Subactive
Active
(High-Speed/
Medium-Speed)
Watch
P16 to P10 High
impedance
Retained Retained High
impedance*
Functioning Functioning Retained
P37, P36,
P32 to P30
High
impedance
Retained Retained High
impedance*
Functioning Functioning Retained
P42 to P40 High
impedance
Retained Retained High
impedance*
Functioning Functioning Retained
P57 to P50 High
impedance
Retained Retained High
impedance*
Functioning Functioning Retained
P67 to P60 High
impedance
Retained Retained High
impedance*
Functioning Functioning Retained
P77 to P70 High
impedance
Retained Retained High
impedance*
Functioning Functioning Retained
P87 to P80 High
impedance
Retained Retained High
impedance*
Functioning Functioning Retained
P93 to P90 High
impedance
Retained Retained High
impedance*
Functioning Functioning Retained
PA3 to PA0 High
impedance
Retained Retained High
impedance*
Functioning Functioning Retained
PB7 to PB5,
PB2 to PB0
High
impedance
High impedance High
impedance
High
impedance*
High
impedance
High impedance High
impedance
Notes: * Registers are retained and output level is high impedance.
Rev. 1.00, 07/04, page 557 of 570
C. Product Code Lineup
Product Classification Product Code Model Marking
Package
(Package Code)
HD64F38086RH4 F38086RH4
HD64F38086RH10 F38086RH10
80 pin QFP (FP-80A)
HD64F38086RW4 F38086RW4
HD64F38086RW10 F38086RW10
80 pin TQFP (TFP-80C)
HD64F38086RLP4V F38086RLP4V
HD64F38086RLP10V F38086RLP10V
80 pin P-TFLGA
(TLP-85V)
HCD64F38086RC4 — Chip
Regular specifications
HCD64F38086RC10 — Chip
HD64F38086RH4W F38086RH4
HD64F38086RH10W F38086RH10
80 pin QFP (FP-80A)
HD64F38086RW4W F38086RW4
HD64F38086RW10W F38086RW10
80 pin TQFP (TFP-80C)
HD64F38086RLP4WV F38086RLP4WV
Flash memory
version
Wide-range
specifications
HD64F38086RLP10WV F38086RLP10WV
80 pin P-TFLGA
(TLP-85V)
HD64338086RH 38086R(***)H 80 pin QFP (FP-80A)
HD64338086RW 38086R(***)W 80 pin TQFP (TFP-80C)
HD64338086RLPV 38086R(***)LPV 80 pin P-TFLGA
(TLP-85V)
Regular specifications
HCD64338086R — Chip
HD64338086RHW 38086R(***)H 80 pin QFP (FP-80A)
HD64338086RWW 38086R(***)W 80 pin TQFP (TFP-80C)
H8/38086R
Group
H8/38086R
Masked ROM
version
Wide-range
specifications
HD64338086RLPWV 38086R(***)LPWV 80 pin P-TFLGA
(TLP-85V)
Rev. 1.00, 07/04, page 558 of 570
Product Classification Product Code Model Marking
Package
(Package Code)
HD64338085RH 38085R(***)H 80 pin QFP (FP-80A)
HD64338085RW 38085R(***)W 80 pin TQFP (TFP-80C)
HD64338085RLPV 38085R(***)LPV 80 pin P-TFLGA
(TLP-85V)
Regular specifications
HCD64338085R — Chip
HD64338085RHW 38085R(***)H 80 pin QFP (FP-80A)
HD64338085RWW 38085R(***)W 80 pin TQFP (TFP-80C)
H8/38086R
Group
H8/38085R Masked ROM
version
Wide-range
specifications
HD64338085RLPWV 38085R(***)LPWV 80 pin P-TFLGA
(TLP-85V)
H8/38084R Regular specifications HD64338084RH 38084R(***)H 80 pin QFP (FP-80A)
Masked ROM
version HD64338084RW 38084R(***)W 80 pin TQFP (TFP-80C)
HD64338084RLPV 38084R(***)LPV 80 pin P-TFLGA
(TLP-85V)
HCD64338084R — Chip
Wide-range
specifications
HD64338084RHW 38084R(***)H 80 pin QFP (FP-80A)
HD64338084RWW 38084R(***)W 80 pin TQFP (TFP-80C)
HD64338084RLPWV 38084R(***)LPWV 80 pin P-TFLGA
(TLP-85V)
H8/38083R Regular specifications HD64338083RH 38083R(***)H 80 pin QFP (FP-80A)
Masked ROM
version HD64338083RW 38083R(***)W 80 pin TQFP (TFP-80C)
HD64338083RLPV 38083R(***)LPV 80 pin P-TFLGA
(TLP-85V)
HCD64338083R — Chip
Wide-range
specifications
HD64338083RHW 38083R(***)H 80 pin QFP (FP-80A)
HD64338083RWW 38083R(***)W 80 pin TQFP (TFP-80C)
HD64338083RLPWV 38083R(***)LPWV 80 pin P-TFLGA
(TLP-85V)
[Legend]
(***): ROM code
Rev. 1.00, 07/04, page 559 of 570
D. Package Dimensions
The package dimensions that are shown in the Renesas Semiconductor Packages Data Book have
priority.
Package Code
JEDEC
JEITA
Mass
(reference value)
FP-80A
—
Conforms
1.2 g
*Dimension including the plating thickness
Base material dimension
60
0˚ – 8˚
0.10
0.12 M
17.2 ± 0.3
41
61
80
120
40
21
17.2 ± 0.3
*0.32 ± 0.08
0.65
3.05 Max
1.6
0.8 ± 0.3
14
2.70
*0.17 ± 0.05
0.10+0.15
–0.10
0.83
0.30 ± 0.06
0.15 ± 0.04
Unit: mm
Figure D.1 Package Dimensions (FP-80A)
Rev. 1.00, 07/04, page 560 of 570
Package Code
JEDEC
JEITA
Mass
(reference value)
TFP-80C
—
Conforms
0.4 g
*Dimension including the plating thickness
Base material dimension
0.10
M
0.10 0.5 ± 0.1
0˚ – 8˚
1.20 Max
14.0 ± 0.2
0.5
12
14.0 ± 0.2
60 41
120
80
61
21
40
*0.17 ± 0.05
1.0
*0.22 ± 0.05
0.10 ± 0.10 1.00
1.25
0.20 ± 0.04
0.15 ± 0.04
Unit: mm
Figure D.2 Package Dimensions (TFP-80C)
Rev. 1.00, 07/04, page 561 of 570
7.0
7.0
0.15
4 ×
0.20 C A
0.20 CB
A
B
0.575
0.575
1.20 Max
0.2 C
0.10
(Flatness of ground plane)
C
C
φ0.08 C
MA B
85 × φ0.35 ± 0.05
13759264810
A
C
E
G
J
B
D
F
H
0.65
0.65
K
Unit: mm
Figure D.3 Package Dimensions (TLP-85V)
Rev. 1.00, 07/04, page 562 of 570
E. Chip Form Specifications
X direction: TBD
Y direction: TBD
X direction: TBD
Y direction: TBD
Maximum dimensions
in chip's plane
0.28 ± 0.02
Max 0.03
Unit: mm
Figure E.1 Cross-Sectional View of Chip
(HCD64338086R, HCD64338085R, HCD64338084R, and HCD64338083R)
X direction: 4.73 ± 0.05
Y direction: 4.73 ± 0.05
X direction: 4.73 ± 0.25
Y direction: 4.73 ± 0.25
Maximum dimensions
in chip's plane
0.28 ± 0.02
Max 0.03
Unit: mm
Figure E.2 Cross-Sectiona l View of Chip (HCD64F38086R)
Rev. 1.00, 07/04, page 563 of 570
F. Bonding Pad Form
Bonding area
Metallic film is visible from here
5 mm72 mm
5 mm 72 mm
Figure F.1 Bonding Pad Form
(HCD64F38086R, HCD64338086R, HCD6433808 5R, HCD64338084R, and HCD64338083R)
Rev. 1.00, 07/04, page 564 of 570
G. Chip Tray Specifications
0.38 ± 0.05
5.50 ± 0.16.25 ± 0.14.0 ± 0.1
5.50 ± 0.1 6.25 ± 0.1
XX'
3.69
3.60
Unit: mm
Cross-sectional view: X to X'
Chip tray code
Nissen Chemitec Corporation
Product code: CT193
Characteristic engraving: CT2038038-038N
51
51
3.80 ± 0.05
3.83 ± 0.05
1.8 ± 0.1
Figure G.1 Chip Tray Specifications
(HCD64338086R, HCD64338085R, HCD64338084R, and HCD64338083R)
Rev. 1.00, 07/04, page 565 of 570
Cross-sectional view: X to X' Unit: mm
0.6 ± 0.1
6.3 ± 0.16.6 ± 0.14.0 ± 0.1
6.3 ± 0.1 6.6 ± 0.1
XX'
4.73
4.73
51
51
5.3 ± 0.05
1.8 ± 0.1 5.3 ± 0.05
Chip orientation
Chip Product
name
Chip tray code
Manufactured by DAINIPPON INK AND CHEMICALS,
INCORPORATED
Product code: CT030
Characteristic engraving: 2CT053053-060
Figure G.2 Chip Tray Specifications (HCD64F38086R)
Rev. 1.00, 07/04, page 566 of 570
Rev. 1.00, 07/04, page 567 of 570
Index
∆Σ A/D converter ................................... 371
14-bit PWM ............................................ 353
16-bit timer pulse unit............................. 209
Counter operation ............................... 228
Free-running count operation.............. 229
Input capture function......................... 231
Input capture signal timing ................. 243
Output compare output timing............ 243
Periodic count operation..................... 229
Synchronous operation ....................... 233
TCNT count timing............................. 242
Toggle output...................................... 230
Waveform output by compare match.. 230
A/D converter ......................................... 359
Address break ......................................... 439
Addressing modes..................................... 39
Absolute address................................... 40
Immediate ............................................. 41
Memory indirect ................................... 41
Program-counter relative ...................... 41
Register direct....................................... 39
Register indirect.................................... 39
Register indirect with displacement...... 40
Register indirect with post-increment... 40
Register indirect with pre-decrement.... 40
Asynchronous Event Counter (AEC)...... 253
Clock pulse generators.............................. 87
Subclock generator ............................... 93
System clock generator......................... 90
Condition field.......................................... 38
Condition-code register (CCR)................. 23
CPU .......................................................... 19
Effective address....................................... 42
Effective address extension ...................... 38
Exception handling................................... 53
Flash memory ......................................... 123
Boot mode........................................... 130
Boot program ...................................... 129
Erase/erase-verify ............................... 136
Erasing units ....................................... 124
Error protection................................... 138
Hardware protection............................ 138
Power-down states .............................. 139
Program/program-verify ..................... 133
Programmer mode............................... 139
Programming units.............................. 124
Programming/erasing in user program
mode....................................................132
Software protection............................. 138
General registers ....................................... 22
I/O ports .................................................. 143
I2C bus format......................................... 419
I2C bus interface 2 (IIC2)........................ 405
Acknowledge ......................................419
Bit synchronous circuit ....................... 435
Clocked synchronous serial format..... 427
Noise canceler..................................... 429
Slave address....................................... 419
Start condition..................................... 419
Stop condition ..................................... 419
Transfer rate........................................ 409
Instruction set............................................ 28
Arithmetic operations instructions ........ 30
Bit manipulation instructions................33
Block data transfer instructions............. 37
Branch instructions ............................... 35
Data transfer instructions ...................... 29
Logic operations instructions................32
Shift instructions ................................... 32
System control instructions................... 36
Interrupt mask bit (I)................................. 23
IrDA........................................................ 322
Rev. 1.00, 07/04, page 568 of 570
Large current ports...................................... 2
LCD controller/driver............................. 385
LCD display........................................ 395
LCD RAM.......................................... 397
Memory map ............................................ 20
On-board programming modes............... 129
Operation field.......................................... 38
Package....................................................... 2
Pin assignment............................................ 4
Power-down modes ................................ 103
Module standby function .................... 119
Sleep mode ......................................... 113
Standby mode ..................................... 113
Subactive mode .................................. 115
Subsleep mode.................................... 114
Power-on reset
Power-on reset circuit......................... 438
Program counter (PC)............................... 23
Realtime clock (RTC)............................. 183
Data reading procedure....................... 193
Initial setting procedure...................... 192
Register field ............................................ 38
Registers
ABRKCR2...................440, 447, 453, 458
ABRKSR2 ...................441, 447, 453, 458
ADCR..........................375, 447, 452, 457
ADDR..........................373, 447, 452, 457
ADRR..........................361, 449, 454, 460
ADSR ..........................363, 449, 454, 460
ADSSR ........................377, 447, 452, 457
AEGSR........................257, 448, 453, 459
AMR............................362, 449, 454, 460
BAR2H........................442, 447, 453, 458
BAR2L ........................442, 447, 453, 458
BDR2H........................442, 448, 453, 458
BDR2L ........................442, 448, 453, 458
BGRMR.......................394, 448, 453, 459
BRR .............................291, 448, 454, 459
CKSTPR1 ................... 107, 450, 456, 461
CKSTPR2 ................... 107, 450, 456, 461
EBR1........................... 127, 446, 451, 457
ECCR.......................... 258, 448, 453, 459
ECCSR........................ 259, 448, 453, 459
ECH ............................ 261, 448, 453, 459
ECL............................. 261, 448, 453, 459
ECPWCR.................... 255, 448, 453, 458
ECPWDR.................... 256, 448, 453, 458
FENR .......................... 128, 446, 451, 457
FLMCR1..................... 125, 446, 451, 457
FLMCR2..................... 126, 446, 451, 457
FLPWCR .................... 128, 446, 451, 457
ICCR1 ......................... 408, 447, 452, 458
ICCR2 ......................... 410, 447, 452, 458
ICDRR ........................ 418, 447, 452, 458
ICDRS................................................. 418
ICDRT ........................ 418, 447, 452, 458
ICIER.......................... 413, 447, 452, 458
ICMR .......................... 411, 447, 452, 458
ICSR ........................... 415, 447, 452, 458
IEGR............................. 67, 450, 455, 461
IENR1........................... 69, 450, 455, 461
INTM ............................ 76, 450, 455, 461
IPR ................................ 75, 447, 452, 458
IrCR ............................ 299, 448, 453, 459
IRR................................ 71, 450, 455, 461
IWPR ............................ 73, 450, 455, 461
LCR............................. 390, 448, 453, 459
LCR2........................... 392, 448, 453, 459
LPCR .......................... 388, 448, 453, 459
LTRMR....................... 393, 448, 453, 459
OCR ............................ 198, 449, 454, 459
OSCCR ......................... 89, 449, 454, 460
PCR1........................... 144, 450, 455, 460
PCR3........................... 152, 450, 455, 460
PCR4........................... 156, 450, 455, 460
PCR5........................... 160, 450, 455, 460
PCR6........................... 164, 450, 455, 461
PCR7........................... 167, 450, 455, 461
PCR8........................... 169, 450, 455, 461
PCR9........................... 171, 450, 455, 461
PCRA.......................... 174, 450, 455, 461
Rev. 1.00, 07/04, page 569 of 570
PDR1 .......................... 144, 449, 455, 460
PDR3 .......................... 151, 449, 455, 460
PDR4 .......................... 156, 449, 455, 460
PDR5 .......................... 159, 449, 455, 460
PDR6 .......................... 163, 449, 455, 460
PDR7 .......................... 166, 449, 455, 460
PDR8 .......................... 168, 449, 455, 460
PDR9 .......................... 170, 449, 455, 460
PDRA ......................... 173, 449, 455, 460
PDRB.......................... 176, 449, 455, 460
PMR1.......................... 145, 449, 454, 460
PMR3.......................... 153, 449, 454, 460
PMR4.......................... 157, 449, 454, 460
PMR5.......................... 161, 449, 454, 460
PMR9.......................... 171, 449, 454, 460
PMRB ......................... 177, 449, 454, 460
PUCR1........................ 145, 449, 455, 460
PUCR3........................ 152, 450, 455, 460
PUCR5........................ 160, 450, 455, 460
PUCR6........................ 164, 450, 455, 460
PWCR......................... 355, 449, 454, 460
PWDR......................... 355, 449, 454, 460
RDR............................ 282, 448, 454, 459
RHRDR ...................... 186, 447, 452, 458
RMINDR .................... 185, 447, 452, 458
RSECDR..................... 185, 447, 452, 458
RSR..................................................... 282
RTCCR1 ..................... 188, 447, 452, 458
RTCCR2 ..................... 189, 447, 452, 458
RTCCSR..................... 190, 447, 452, 458
RTCFLG..................... 191, 447, 452, 458
RWKDR ..................... 187, 447, 452, 458
SAR ............................ 417, 447, 452, 458
SCR..................................................... 448
SCR3........................... 285, 448, 454, 459
SCR4........................... 335, 446, 451, 457
SCSR4 ........................ 338, 446, 451, 457
SMR............................ 283, 448, 454, 459
SPCR .......................... 297, 448, 453, 458
SSR............................. 288, 448, 454, 459
SUB32CR ..................... 88, 447, 452, 458
SYSCR1 ..................... 104, 450, 455, 461
SYSCR2 ..................... 106, 450, 455, 461
TCF ............................. 197, 449, 454, 459
TCNT.......................... 223, 446, 451, 457
TCR............................. 213, 446, 451, 457
TCRF .......................... 199, 449, 454, 459
TCSR .......................... 200, 449, 454, 459
TCSRWD.................... 270, 448, 454, 459
TCWD......................... 273, 449, 454, 459
TDR ............................ 282, 448, 454, 459
TGR ............................ 223, 446, 451, 457
TIER............................ 221, 446, 451, 457
TIOR ........................... 216, 446, 451, 457
TMDR......................... 215, 446, 451, 457
TMWD........................ 273, 448, 454, 459
TSR ............................. 222, 446, 451, 457
TSTR........................... 224, 446, 451, 457
TSYR .......................... 225, 446, 451, 457
WEGR........................... 68, 448, 453, 458
Serial communication interface 3 (SCI3)
Asynchronous mode............................ 300
Bit rate................................................. 291
Break................................................... 328
Clocked synchronous mode ................ 311
Framing error ...................................... 307
Mark state ...........................................328
Multiprocessor communication function
............................................................ 317
Overrun error ...................................... 307
Parity error .......................................... 307
Serial Communication Interface 3 (SCI3,
IrDA)....................................................... 277
Serial Communication Interface 4 (SCI4)
................................................................ 333
Stack pointer (SP) ..................................... 22
Timer F ................................................... 195
16-bit timer mode................................ 202
8-bit timer mode.................................. 202
Vector address........................................... 54
Watchdog timer....................................... 269
Rev. 1.00, 07/04, page 570 of 570
Renesas 16-Bit Single-Chip Microcomputer
Hardware Manual
H8/38086R Group
Publication Date: Rev.1.00, Jul 09, 2004
Published by: Sales Strategic Planning Div.
Renesas Technology Corp.
Edited by: Technical Documentation & Information Department
Renesas Kodaira Semiconductor Co., Ltd.
2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon 1.0
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
http://www.renesas.com
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Hardware Manual
