100324QIX - National Semiconductor

100324

Low Power Hex TTL-to-ECL Translator

General Description

The 100324 is a hex translator, designed to convert TTL

logic levels to 100K ECL logic levels. The inputs are compat-

ible with standard or Schottky TTL. A common Enable (E),

when LOW, holds all inverting outputs HIGH and holds all

true outputs LOW. The differential outputs allow each circuit

to be used as an inverting/non-inverting translator, or as a

differential line driver. The output levels are voltage compen-

sated over the full −4.2V to −5.7V range.

When the circuit is used in the differential mode, the 100324,

due to its high common mode rejection, overcomes voltage

gradients between the TTL and ECL ground systems. The

and V

TTL

power may be applied in either order.

The 100324 is pin and function compatible with the 100124

with similar AC performance, but features power dissipation

roughly half of the 100124 to ease system cooling require-

ments.

Features

nPin/function compatible with 100124

nMeets 100124 AC specifications

n50%power reduction of the 100124

nDifferential outputs

n2000V ESD protection

n−4.2V to −5.7V operating range

nStandard Microcircuit Drawing

(SMD) 5962-9153001

Logic Diagram Pin Names Description

–D

Data Inputs

E Enable Input

–Q

Data Outputs

–Q

Complementary

Data Outputs

DS100313-4

August 1998

100324 Low Power Hex TTL-to-ECL Translator

Connection Diagrams

24-Pin DIP

DS100313-1

24-Pin Quad Cerpak

DS100313-2

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Above which the useful life may be impaired.

Storage Temperature (T

STG

) −65˚C to +150˚C

Maximum Junction Temperature (T

)

Ceramic +175˚C

Pin Potential to Ground Pin −7.0V to +0.5V

TTL

Pin Potential to Ground Pin −0.5V to +6.0V

Input Voltage (DC) −0.5V to +6.0V

Output Current (DC Output HIGH) −50 mA

ESD (Note 2) ≥2000V

Recommended Operating

Conditions

Case Temperature (T

)

Military −55˚C to +125˚C

Supply Voltage (V

) −5.7V to −4.2V

Note 1: Absolute maximum ratings are those values beyond which the de-

vice may be damaged or have its useful life impaired. Functional operation

under these conditions is not implied.

Note 2: ESD testing conforms to MIL-STD-883, Method 3015.

Military Version

DC Electrical Characteristics

=−4.2V to −5.7V, V

CCA

=GND, T

=−55˚C to +125˚C, V

TTL

=+4.5V to +5.5V

Symbol Parameter Min Max Units TCConditions Notes

VOH Output HIGH Voltage −1025 −870 mV 0˚C to +125˚C VIN =VIH (Max)

or VIL (Min) Loading with

50Ωto −2.0V (Notes 3, 4, 5)

−1085 −870 mV −55˚C

VOL Output LOW Voltage −1830 −1620 mV 0˚C to +125˚C

−1830 −1555 mV −55˚C

VOHC Output HIGH Voltage −1035 mV 0˚C to +125˚C VIN =VIH (Max)

or VIL (Min) Loading with

50Ωto −2.0V (Notes 3, 4, 5)

−1085 mV −55˚C

VOLC Output LOW Voltage −1610 mV 0˚C to +125˚C

−1555 mV −55˚C

VIH Input HIGH Voltage 2.0 5.0 V −55˚C to +125˚C Over VTTL,V

EE,T

CRange (Notes 3, 4, 5, 6)

VIL Input LOW Voltage 0.0 0.8 V −55˚C to +125˚C Over VTTL,V

EE,T

CRange (Notes 3, 4, 5, 6)

IIH Input HIGH Current 20 µA −55˚C to +125˚C VIN =+2.7V (Notes 3, 4, 5)

Breakdown Test 100 µA −55˚C to +125˚C VIN =+7.0V

IIL Input LOW Current

Data −0.9 mA −55˚C to +125˚C VIN =+0.4V (Notes 3, 4, 5)

Enable −5.4

VFCD Input Clamp Diode Voltage −1.2 V −55˚C to +125˚C IIN =−18 mA (Notes 3, 4, 5)

IEE VEE Power Supply Current −70 −22 mA −55˚C to +125˚C All Inputs VIN =+4.0V (Notes 3, 4, 5)

ITTL VTTL Power Supply Current 38 mA −55˚C to +125˚C All Inputs VIN =GND (Notes 3, 4, 5)

Note 3: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately

without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case

condition at cold temperatures.

Note 4: Screen tested 100%on each device at −55˚C, +25˚C, and +125˚C, Subgroups 1, 2, 3, 7, and 8.

Note 5: Sample tested (Method 5005, Table I) on each manufactured lot at −55˚C, +25˚C, and +125˚C, Subgroups A1, 2, 3, 7, and 8.

Note 6: Guaranteed by applying specified input condition and testing VOH/VOL.

AC Electrical Characteristics

=−4.2V to −5.7V, V

CCA

=GND, V

TTL

=+4.5V to +5.5V

Symbol Parameter TC=−55˚C TC=+25˚C TC=+125˚C Units Conditions Notes

Min Max Min Max Min Max

tPLH Propagation Delay 0.50 3.00 0.50 2.90 0.30 3.30 ns (Notes 7, 8, 9)

tPHL Data and Enable to Output

Figures 1, 2

tTLH Transition Time 0.35 1.80 0.45 1.80 0.45 1.80 ns (Note 10)

tTHL 20%to 80%,80

%to 20%

Note 7: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately

after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures.

Note 8: Screen tested 100%on each device at +25˚C temperature only, Subgroup A9.

Note 9: Sample tested (Method 5005, Table I) on each manufactured lot at +25˚C, Subgroup A9, and at +125˚C and −55˚C temperatures, SubgroupsA10 and A11.

Note 10: Not tested at +25˚C, +125˚C, and −55˚C temperature (design characterization data).

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Switching Waveform

Test Circuit

DS100313-6

FIGURE 1. Propagation Delay and Transition Times

DS100313-5

Note:

VCC,V

CCA =0V, VEE =−4.5V, VTTL =+5.0V, VIH =+3.0V

L1, L2 and L3 =equal length 50Ωimpedance lines

RT=50Ωterminator internal to scope

Decoupling 0.1 µF from GND to VCC,V

EE and VTTL

All unused outputs are loaded with 50Ωto −2V or with equivalent ECL terminator network

CL=Fixture and stray capacitance ≤3pF

FIGURE 2. AC Test Circuit

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Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Ceramic Dual-In-Line Package (0.400" Wide) (D)

NS Package Number J24E

24 Lead Quad Cerpak (F)

NS Package Number W24B

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VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-

CONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or sys-

tems which, (a) are intended for surgical implant into

the body, or (b) support or sustain life, and whose fail-

ure to perform when properly used in accordance

with instructions for use provided in the labeling, can

be reasonably expected to result in a significant injury

to the user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

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100324 Low Power Hex TTL-to-ECL Translator

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.