DATASHEET
FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER ICS343
IDT™ / ICS™
FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER 1
ICS343 REV K 092109
Description
The ICS343 is a low cost, triple-output, field programmable
clock synthesizer. The ICS343 can generate three output
frequencies from 250 kHz to 200 MHz, using up to three
independently configurable PLLs. The outputs may employ
Spread Spectrum techniques to reduce system
electro-magnetic interference (EMI).
Using ICS’ VersaClock™ software to configure the PLL and
output, the ICS343 contains a One-Time Programmable
(OTP) ROM to allow field programmability. Using
Phase-Locked Loop (PLL) techniques, the device runs from
a standard fundamental mode, inexpensive crystal, or
clock. It can replace multiple crystals and oscillators, saving
board space and cost.
The device also has a power down feature that tri-states the
clock outputs and turns off the PLLs when the PDTS pin is
taken low.
The ICS343 is also available in factory-programmed
custom versions for high-volume applications.
Features
•8-pin SOIC package
•Highly accurate frequency generation
•M/N Multiplier PLL: M = 1...2048, N = 1...1024
•Output clock frequencies up to 200 MHz
•Spread spectrum capability for lower system EMI
•Center or Down Spread up to 4% total
•Selectable 32 kHz or 120 kHz modulation
•Input crystal frequency from 5 to 27 MHz
•Input clock frequency from 2 to 50 MHz
•Operating voltage of 3.3 V, using advanced, low power
CMOS process
•For one output clock, use the ICS341. For two output
clocks, see the ICS342. For more than three outputs, see
the ICS345 or ICS348.
•Available in Pb (lead) free packaging
NOTE: EOL for non-green parts to occur on 5/13/10
per PDN U-09-01
Block Diagram
Crystal
Oscillator
PDTS (both outputs and PLL)
OTP ROM
with PLL
Divider
Values
VDD
GND
CLK1
CLK3
CLK2
PLL Clock Synthesis,
Spred Spectrum and
Control Circuitry
X2
Crystal or
clock input
External capacitors are
required with a crystal input.
X1/ICLK
ICS343
FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER
IDT™ / ICS™
FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER 2
ICS343 REV K 092109
Pin Assignment
8-pin (150 mil) SOIC
Output Clock Selection Table
Pin Descriptions
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a commonly
used trace impedance), place a 33Ω resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20Ω.
Decoupling Capacitor
As with any high-performance mixed-signal IC, the ICS343
must be isolated from system power supply noise to perform
optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and the PCB ground plane.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance of
the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) been the crystal and device. Crystal
capacitors must be connected from each of the pins X1 and
X2 to ground.
The value (in pF) of these crystal caps should equal (CL -6
pF)*2. In this equation, CL= crystal load capacitance in pF.
Example: For a crystal with a 16 pF load capacitance, each
crystal capacitor would be 20 pF [(16-6) x 2] = 20.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
X1/ICLK
VDD
GND
PDTS
CLK1
CLK2
CLK3
X21
2
3
4
8
7
6
5
CLK2 CLK2 CLK3
Output
Frequency
User
Configurable
User
Configurable
User
Configurable
Spread
Amount
User
Configurable
User
Configurable
User
Configurable
Pin
Number
Pin
Name
Pin
Type Pin Description
1 X1/ICLK XI Connect this pin to a crystal or external clock input.
2 VDD Power Connect to +3.3 V.
3 GND Power Connect to ground.
4 CLK1 Output Clock output. Weak internal pull-down when tri-state.
5 CLK3 Output Clock output. Weak internal pull-down when tri-state.
6 CLK2 Output Clock output. Weak internal pull-down when tri-state.
7PDTS
Input Powers down entire chip. Tri-states CLK outputs when low. Internal pull-up.
8 X2 XO Connect this pin to a crystal, or float for clock input.
ICS343
FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER
IDT™ / ICS™
FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER 3
ICS343 REV K 092109
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) The external crystal should be mounted just next to the
device with short traces. The X1 and X2 traces should not
be routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
3) To minimize EMI, the 33Ω series termination resistor (if
needed) should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
ICS343. This includes signal traces just underneath the
device, or on layers adjacent to the ground plane layer used
by the device.
ICS343 Configuration Capabilities
The architecture of the ICS343 allows the user to easily
configure the device to a wide range of output frequencies,
for a given input reference frequency.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be set
within the range of M = 1 to 2048 and N = 1 to 1024.
The ICS343 also provides separate output divide values,
from 2 through 20, to allow the two output clock banks to
support widely differing frequency values from the same
PLL.
Each output frequency can be represented as:
ICS VersaClock Software
ICS applies years of PLL optimization experience into a
user-friendly software that accepts the user’s target
reference clock and output frequencies and generates the
lowest jitter, lowest power configuration, with only a press of
a button. The user does not need to have prior PLL
experience or determine the optimal VCO frequency to
support multiple output frequencies.
VersaClock software quickly evaluates accessible VCO
frequencies with available output divide values and provides
an easy to understand, bar code rating for the target output
frequencies. The user may evaluate output accuracy,
performance trade-off scenarios in seconds.
Spread Spectrum Modulation
The ICS343 utilizes frequency modulation (FM) to distribute
energy over a range of frequencies. By modulating the
output clock frequencies, the device effectively lowers
energy across a broader range of frequencies; thus,
lowering a system’s electro-magnetic interference (EMI).
The modulation rate is the time from transitioning from a
minimum frequency to a maximum frequency and then back
to the minimum.
Spread Spectrum Modulation can be applied as either
“center spread” or “down spread”. During center spread
modulation, the deviation from the target frequency is equal
in the positive and negative directions. The effective
average frequency is equal to the target frequency. In
applications where the clock is driving a component with a
maximum frequency rating, down spread should be applied.
In this case, the maximum frequency, including modulation,
is the target frequency. The effective average frequency is
less than the target frequency.
The ICS343 operates in both center spread and down
spread modes. For center spread, the frequency can be
modulated between +/- 0.125% to +/-2.0%. For down
spread, the frequency can be modulated between -0.25% to
-4.0%.
Both output frequency banks will utilize identical spread
spectrum percentage deviations and modulation rates, if a
common VCO frequency can be identified.
Spread Spectrum Modulation Rate
The spread spectrum modulation frequency applied to the
output clock frequency may occur at a variety of rates. For
applications requiring the driving of “down-circuit” PLLs,
Zero Delay Buffers, or those adhering to PCI standards, the
spread spectrum modulation rate should be set to 30-33
kHz. For other applications, a 120 kHz modulation option is
available.
O
utputFreq REFFreq
OutputDivide
-------------------------------------- M
N
-----
⋅=
ICS343
FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER
IDT™ / ICS™
FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER 4
ICS343 REV K 092109
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS343. These ratings, which
are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Recommended Operation Conditions
Parameter Condition Min. Typ. Max. Units
Supply Voltage, VDD Referenced to GND 7 V
Inputs Referenced to GND -0.5 VDD+ 0.5 V
Clock Outputs Referenced to GND -0.5 VDD+ 0.5 V
Storage Temperature -65 150 °C
Soldering Temperature Max 10 seconds 260 °C
Junction Temperature 125 °C
Parameter Min. Typ. Max. Units
Ambient Operating Temperature (ICS343M) 0 +70 °C
Ambient Operating Temperature (ICS343MI) -40 +85 °C
Power Supply Voltage (measured in respect to GND) +3.15 +3.3 +3.45 V
Power Supply Ramp Time 4 ms
ICS343
FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER
IDT™ / ICS™
FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER 5
ICS343 REV K 092109
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85°C
Note 1: Example with 25 MHz crystal input with three outputs of 33.3 MHz, no load, and VDD = 3.3 V.
Parameter Symbol Conditions Min. Typ. Max. Units
Operating Voltage VDD 3.15 3.3 3.45 V
Operating Supply Current
Input High Voltage
IDD
Configuration
Dependent - See
VersaClockTM
Estimates
mA
Three 33.3333 MHz
outputs, PDTS = 1, No
load
Note 1
14 mA
PDTS = 0 20 µA
Input High Voltage, PDTS VIH VDD-0.5 V
Input Low Voltage, PDTS VIL 0.4 V
Input High Voltage VIH ICLK VDD/2+1 V
Input Low Voltage VIL ICLK VDD/2-1 V
Output High Voltage
(CMOS High)
VOH IOH = -4 mA VDD-0.4 V
Output High Voltage VOH IOH = -12 mA 2.4 V
Output Low Voltage VOL IOL = 12 mA 0.4 V
Short Circuit Current IOS ±70 mA
Nominal Output
Impedance
ZO20 Ω
Internal Pull-up Resistor RPUP PDTS pin 250 kΩ
Internal Pull-down Resistor RPD CLK output 525 kΩ
Input Capacitance CIN Inputs 4 pF
ICS343
FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER
IDT™ / ICS™
FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER 6
ICS343 REV K 092109
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85° C
Note 1: Measured with 15 pF load.
Note 2: Duty Cycle is configuration dependent. Most configurations are minimum 45% and maximum 55%.
Note 3: ICS test mode output occurs for first 170 clock cycles on CLK3 for each PLL powered up.
Thermal Characteristics
Parameter Symbol Conditions Min. Typ. Max. Units
Input Frequency FIN Fundamental Crystal 5 27 MHz
Input Clock 2 50 MHz
Output Frequency 0.25 200 MHz
Output Rise Time tOR 20% to 80%, Note 1 1 ns
Output Fall Time tOF 80% to 20%, Note 1 1 ns
Duty Cycle Note 2 40 49-51 60 %
Output Frequency Synthesis
Error
Configuration Dependent TBD ppm
Power-up time PLL lock time from
power-up, Note 3
410ms
PDTS goes high until
stable CLK output, Spread
Spectrum Off, Note 3
0.2 2 ms
PDTS goes high until
stable CLK output, Spread
Spectrum On, Note 3
47ms
One Sigma Clock Period Jitter Configuration Dependent 50 ps
Maximum Absolute Jitter tja Deviation from Mean.
Configuration Dependent
+200 ps
Parameter Symbol Conditions Min. Typ. Max. Units
Thermal Resistance Junction to
Ambient
θJA Still air 150 °C/W
θJA 1 m/s air flow 140 °C/W
θJA 3 m/s air flow 120 °C/W
Thermal Resistance Junction to Case θJC 40 °C/W
ICS343
FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER
IDT™ / ICS™
FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER 7
ICS343 REV K 092109
Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
INDEX
AREA
1 2
8
D
E
SEATING
PLANE
A1
A
e
- C -
B
.10 (.004) C
C
L
H
h x 45
Millimeters Inches
Symbol Min Max Min Max
A 1.35 1.75 .0532 .0688
A1 0.10 0.25 .0040 .0098
B 0.330.51.013.020
C 0.19 0.25 .0075 .0098
D 4.80 5.00 .1890 .1968
E 3.80 4.00 .1497 .1574
e 1.27 BASIC 0.050 BASIC
H 5.80 6.20 .2284 .2440
h 0.250.50.010.020
L 0.401.27.016.050
α0°8°0°8°
ICS343
FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER
IDT™ / ICS™
FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER 8
ICS343 REV K 092109
Ordering Information
*NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01
Parts that are ordered with a “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The 343M-XX, 343M-XXLF, 343MI-XX, and 343MI-XXLF are factory programmed versions of the 343MP, 343MPLF, 343MIP, and
343MIPLF. A unique “-XX” suffix is assigned by the factory for each custom configuration, and a separate data sheet is kept on
file. For more information on custom part numbers programmed at the factory, please contact your local IDT sales and marketing
representative.
While the information presented herein has been checked for both accuracy and reliability, IDT assumes no responsibility for either its use
or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses
are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended
temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing
by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product
for use in life support devices or critical medical instruments.
Part / Order Number Marking Shipping Packaging Package Temperature
343MP* 343MP Tubes 8-pin SOIC 0 to +70° C
343MIP* 343MIP Tubes 8-pin SOIC -40 to +85° C
343MPLF 343MPLF Tubes 8-pin SOIC 0 to +70° C
343MIPLF 343MIPLF Tubes 8-pin SOIC -40 to +85° C
343M-XX* 343M-XX Tubes 8-pin SOIC 0 to +70° C
343MI-XX* 343MI-XX Tubes 8-pin SOIC -40 to +85° C
343M-XXLF 343MXXLF Tubes 8-pin SOIC 0 to +70° C
343MI-XXLF 343MIXXL Tubes 8-pin SOIC -40 to +85° C
343M-XXT* 343M-XX Tape and Reel 8-pin SOIC 0 to +70° C
343MI-XXT* 343MI-XX Tape and Reel 8-pin SOIC -40 to +85° C
343M-XXLFT 343MXXLF Tape and Reel 8-pin SOIC 0 to +70° C
343MI-XXLFT 343MIXXL Tape and Reel 8-pin SOIC -40 to +85° C
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
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Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
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IDT Europe, Limited
Prime House
Barnett Wood Lane
Leatherhead, Surrey
United Kingdom KT22 7DE
+44 1372 363 339
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
<product line email>
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Innovate with IDT and accelerate your future networks. Contact:
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ICS343
FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER
