DATASHEET FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER ICS343 Description Features The ICS343 is a low cost, triple-output, field programmable clock synthesizer. The ICS343 can generate three output frequencies from 250 kHz to 200 MHz, using up to three independently configurable PLLs. The outputs may employ Spread Spectrum techniques to reduce system electro-magnetic interference (EMI). * 8-pin SOIC package * Highly accurate frequency generation * M/N Multiplier PLL: M = 1...2048, N = 1...1024 * Output clock frequencies up to 200 MHz * Spread spectrum capability for lower system EMI * Center or Down Spread up to 4% total * Selectable 32 kHz or 120 kHz modulation * Input crystal frequency from 5 to 27 MHz * Input clock frequency from 2 to 50 MHz * Operating voltage of 3.3 V, using advanced, low power Using ICS' VersaClockTM software to configure the PLL and output, the ICS343 contains a One-Time Programmable (OTP) ROM to allow field programmability. Using Phase-Locked Loop (PLL) techniques, the device runs from a standard fundamental mode, inexpensive crystal, or clock. It can replace multiple crystals and oscillators, saving board space and cost. The device also has a power down feature that tri-states the clock outputs and turns off the PLLs when the PDTS pin is taken low. CMOS process * For one output clock, use the ICS341. For two output * clocks, see the ICS342. For more than three outputs, see the ICS345 or ICS348. Available in Pb (lead) free packaging NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 The ICS343 is also available in factory-programmed custom versions for high-volume applications. Block Diagram VDD OTP ROM with PLL Divider Values Crystal or clock input CLK1 PLL Clock Synthesis, Spred Spectrum and Control Circuitry CLK2 X1/ICLK Crystal Oscillator CLK3 X2 External capacitors are required with a crystal input. GND PDTS (both outputs and PLL) IDTTM / ICSTM FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER 1 ICS343 REV K 092109 ICS343 FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER Pin Assignment EPROM CLOCK SYNTHESIZER Output Clock Selection Table X1/ I CLK 1 8 X2 VDD 2 7 PDTS GND 3 6 CLK2 CLK1 4 5 CLK3 CLK2 CLK2 CLK3 Output User User User Frequency Configurable Configurable Configurable Spread User User User Amount Configurable Configurable Configurable 8-pin (150 mil) SOIC Pin Descriptions Pin Number Pin Name Pin Type 1 X1/ICLK XI 2 VDD Power Pin Description Connect this pin to a crystal or external clock input. Connect to +3.3 V. 3 GND Power Connect to ground. 4 CLK1 Output Clock output. Weak internal pull-down when tri-state. 5 CLK3 Output Clock output. Weak internal pull-down when tri-state. 6 CLK2 Output Clock output. Weak internal pull-down when tri-state. 7 PDTS Input 8 X2 XO Powers down entire chip. Tri-states CLK outputs when low. Internal pull-up. Connect this pin to a crystal, or float for clock input. External Components Series Termination Resistor Clock output traces over one inch should use series termination. To series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20. Decoupling Capacitor As with any high-performance mixed-signal IC, the ICS343 must be isolated from system power supply noise to perform optimally. A decoupling capacitor of 0.01F must be connected between VDD and the PCB ground plane. capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) been the crystal and device. Crystal capacitors must be connected from each of the pins X1 and X2 to ground. The value (in pF) of these crystal caps should equal (CL -6 pF)*2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with a 16 pF load capacitance, each crystal capacitor would be 20 pF [(16-6) x 2] = 20. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. Crystal Load Capacitors The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load 1) The 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin should IDTTM / ICSTM FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER 2 ICS343 REV K 092109 ICS343 FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) To minimize EMI, the 33 series termination resistor (if needed) should be placed close to the clock output. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the ICS343. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. ICS343 Configuration Capabilities The architecture of the ICS343 allows the user to easily configure the device to a wide range of output frequencies, for a given input reference frequency. The frequency multiplier PLL provides a high degree of precision. The M/N values (the multiplier/divide values available to generate the target VCO frequency) can be set within the range of M = 1 to 2048 and N = 1 to 1024. The ICS343 also provides separate output divide values, from 2 through 20, to allow the two output clock banks to support widely differing frequency values from the same PLL. Each output frequency can be represented as: OutputFreq = REFFreq -------------------------------------OutputDivide M ----N ICS VersaClock Software ICS applies years of PLL optimization experience into a user-friendly software that accepts the user's target reference clock and output frequencies and generates the lowest jitter, lowest power configuration, with only a press of a button. The user does not need to have prior PLL experience or determine the optimal VCO frequency to support multiple output frequencies. EPROM CLOCK SYNTHESIZER VersaClock software quickly evaluates accessible VCO frequencies with available output divide values and provides an easy to understand, bar code rating for the target output frequencies. The user may evaluate output accuracy, performance trade-off scenarios in seconds. Spread Spectrum Modulation The ICS343 utilizes frequency modulation (FM) to distribute energy over a range of frequencies. By modulating the output clock frequencies, the device effectively lowers energy across a broader range of frequencies; thus, lowering a system's electro-magnetic interference (EMI). The modulation rate is the time from transitioning from a minimum frequency to a maximum frequency and then back to the minimum. Spread Spectrum Modulation can be applied as either "center spread" or "down spread". During center spread modulation, the deviation from the target frequency is equal in the positive and negative directions. The effective average frequency is equal to the target frequency. In applications where the clock is driving a component with a maximum frequency rating, down spread should be applied. In this case, the maximum frequency, including modulation, is the target frequency. The effective average frequency is less than the target frequency. The ICS343 operates in both center spread and down spread modes. For center spread, the frequency can be modulated between +/- 0.125% to +/-2.0%. For down spread, the frequency can be modulated between -0.25% to -4.0%. Both output frequency banks will utilize identical spread spectrum percentage deviations and modulation rates, if a common VCO frequency can be identified. Spread Spectrum Modulation Rate The spread spectrum modulation frequency applied to the output clock frequency may occur at a variety of rates. For applications requiring the driving of "down-circuit" PLLs, Zero Delay Buffers, or those adhering to PCI standards, the spread spectrum modulation rate should be set to 30-33 kHz. For other applications, a 120 kHz modulation option is available. IDTTM / ICSTM FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER 3 ICS343 REV K 092109 ICS343 FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS343. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Parameter Condition Min. Supply Voltage, VDD Referenced to GND Inputs Referenced to GND Clock Outputs Referenced to GND Storage Temperature Soldering Temperature Typ. Max. Units 7 V -0.5 VDD+ 0.5 V -0.5 VDD+ 0.5 V -65 150 C 260 C 125 C Max 10 seconds Junction Temperature Recommended Operation Conditions Parameter Min. Typ. Max. Units Ambient Operating Temperature (ICS343M) 0 +70 C Ambient Operating Temperature (ICS343MI) -40 +85 C +3.45 V 4 ms Power Supply Voltage (measured in respect to GND) +3.15 Power Supply Ramp Time IDTTM / ICSTM FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER 4 +3.3 ICS343 REV K 092109 ICS343 FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER DC Electrical Characteristics Unless stated otherwise, VDD = 3.3V 5%, Ambient Temperature -40 to +85 C Parameter Operating Voltage Symbol Conditions VDD Min. Typ. Max. Units 3.15 3.3 3.45 V mA Configuration Dependent - See VersaClockTM Estimates Three 33.3333 MHz outputs, PDTS = 1, No load Note 1 14 mA 20 A V Operating Supply Current Input High Voltage IDD Input High Voltage, PDTS VIH Input Low Voltage, PDTS VIL Input High Voltage VIH ICLK Input Low Voltage VIL ICLK Output High Voltage (CMOS High) VOH IOH = -4 mA VDD-0.4 V Output High Voltage VOH IOH = -12 mA 2.4 V Output Low Voltage VOL IOL = 12 mA Short Circuit Current IOS 70 mA Nominal Output Impedance ZO 20 PDTS = 0 VDD-0.5 0.4 VDD/2+1 V V VDD/2-1 0.4 V V Internal Pull-up Resistor RPUP PDTS pin 250 k Internal Pull-down Resistor RPD CLK output 525 k Input Capacitance CIN Inputs 4 pF Note 1: Example with 25 MHz crystal input with three outputs of 33.3 MHz, no load, and VDD = 3.3 V. IDTTM / ICSTM FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER 5 ICS343 REV K 092109 ICS343 FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER AC Electrical Characteristics Unless stated otherwise, VDD = 3.3V 5%, Ambient Temperature -40 to +85 C Parameter Symbol Input Frequency FIN Conditions Min. Typ. Max. Units Fundamental Crystal 5 27 MHz Input Clock 2 50 MHz 0.25 200 MHz Output Frequency Output Rise Time tOR 20% to 80%, Note 1 1 ns Output Fall Time tOF 80% to 20%, Note 1 1 ns Duty Cycle Note 2 Output Frequency Synthesis Error Configuration Dependent Power-up time PLL lock time from power-up, Note 3 One Sigma Clock Period Jitter Maximum Absolute Jitter tja 40 49-51 60 TBD % ppm 4 10 ms PDTS goes high until stable CLK output, Spread Spectrum Off, Note 3 0.2 2 ms PDTS goes high until stable CLK output, Spread Spectrum On, Note 3 4 7 ms Configuration Dependent 50 ps Deviation from Mean. Configuration Dependent +200 ps Note 1: Measured with 15 pF load. Note 2: Duty Cycle is configuration dependent. Most configurations are minimum 45% and maximum 55%. Note 3: ICS test mode output occurs for first 170 clock cycles on CLK3 for each PLL powered up. Thermal Characteristics Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient JA Still air 150 C/W JA 1 m/s air flow 140 C/W JA 3 m/s air flow 120 C/W Thermal Resistance Junction to Case JC 40 C/W IDTTM / ICSTM FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER 6 ICS343 REV K 092109 ICS343 FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 8 Symbol E Min A A1 B C D E e H h L H INDEX AREA 1 2 D A Inches Max Min 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0 8 Max .0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .1890 .1968 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0 8 h x 45 A1 C -Ce B SEATING PLANE L .10 (.004) C IDTTM / ICSTM FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER 7 ICS343 REV K 092109 ICS343 FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature 343MP* 343MIP* 343MPLF 343MIPLF 343M-XX* 343MI-XX* 343M-XXLF 343MI-XXLF 343M-XXT* 343MI-XXT* 343M-XXLFT 343MI-XXLFT 343MP 343MIP 343MPLF 343MIPLF 343M-XX 343MI-XX 343MXXLF 343MIXXL 343M-XX 343MI-XX 343MXXLF 343MIXXL Tubes Tubes Tubes Tubes Tubes Tubes Tubes Tubes Tape and Reel Tape and Reel Tape and Reel Tape and Reel 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 0 to +70 C -40 to +85 C 0 to +70 C -40 to +85 C 0 to +70 C -40 to +85 C 0 to +70 C -40 to +85 C 0 to +70 C -40 to +85 C 0 to +70 C -40 to +85 C *NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. The 343M-XX, 343M-XXLF, 343MI-XX, and 343MI-XXLF are factory programmed versions of the 343MP, 343MPLF, 343MIP, and 343MIPLF. A unique "-XX" suffix is assigned by the factory for each custom configuration, and a separate data sheet is kept on file. For more information on custom part numbers programmed at the factory, please contact your local IDT sales and marketing representative. While the information presented herein has been checked for both accuracy and reliability, IDT assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDTTM / ICSTM FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER 8 ICS343 REV K 092109 ICS343 FIELD PROGRAMMABLE TRIPLE OUTPUT SS VERSACLOCK SYNTHESIZER EPROM CLOCK SYNTHESIZER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 <product line email> <product line phone> Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 (c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA