KM48V8000C,KM48V8100C CMOS DRAM
This is a family of 8,388,608 x 8 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells
within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -5 or -6), power consumption(Normal or Low power) are
optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Fur-
thermore, Self-refresh operation is available in L-version. This 8Mx8 Fast Page Mode DRAM family is fabricated using Samsung′s
advanced CMOS process to realize high band-width, low power consumption and high reliability.
• Part Identification
- KM48V8000C/C-L(3.3V, 8K Ref.)
- KM48V8100C/C-L(3.3V, 4K Ref.)
• Fast Page Mode operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• +3.3V±0.3V power supply
Control
Clocks
RAS
CAS
W
Vcc
Vss
A0~A12
(A0~A11)*1
A0~A9
(A0~A10)*1
Memory Array
8,388,608 x 8
Cells
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
8M x 8bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Note) *1 : 4K Refresh
• Refresh Cycles
Part
NO. Refresh
cycle Refresh time
Normal L-ver
KM48V8000C* 8K 64ms 128ms
KM48V8100C 4K
• Performance Range
Speed tRAC tCAC tRC tPC
-45 45ns 12ns 80ns 31ns
-5 50ns 13ns 90ns 35ns
-6 60ns 15ns 110ns 40ns
• Active Power Dissipation
Speed 8K 4K
-45 324 432
-5 288 396
-6 252 360
Unit : mW
Sense Amps & I/O
DQ0
to
DQ7
Data out
Buffer
Data in
Buffer
* Access mode & RAS only refresh mode
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)
CAS-before-RAS & Hidden refresh mode
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
Row Decoder
Column Decoder
VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
Row Address Buffer
Col. Address Buffer OE
KM48V8000C,KM48V8100C CMOS DRAM
VCC
DQ0
DQ1
DQ2
DQ3
N.C
VCC
W
RAS
A0
A1
A2
A3
A4
A5
VCC
VSS
DQ7
DQ6
DQ5
DQ4
VSS
CAS
OE
A12(N.C)*
A11
A10
A9
A8
A7
A6
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PIN CONFIGURATION (Top Views)
* (N.C) : N.C for 4K Refresh product
Pin Name Pin Function
A0 - A12 Address Inputs(8K Product)
A0 - A11 Address Inputs(4K Product)
DQ0 - 7 Data In/Out
VSS Ground
RAS Row Address Strobe
CAS Column Address Strobe
WRead/Write Input
OE Data Output Enable
VCC Power(+3.3V)
N.C No Connection
(S : 400mil TSOP(II))
VCC
DQ0
DQ1
DQ2
DQ3
N.C
VCC
W
RAS
A0
A1
A2
A3
A4
A5
VCC
VSS
DQ7
DQ6
DQ5
DQ4
VSS
CAS
OE
A12(N.C)*
A11
A10
A9
A8
A7
A6
VSS
(K : 400mil SOJ)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
•KM48V80(1)00CK •KM48V80(1)00CS
KM48V8000C,KM48V8100C CMOS DRAM
ABSOLUTE MAXIMUM RATINGS
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Parameter Symbol Rating Units
Voltage on any pin relative to VSS VIN,VOUT -0.5 to +4.6 V
Voltage on VCC supply relative to VSS VCC -0.5 to +4.6 V
Storage Temperature Tstg -55 to +150 °C
Power Dissipation PD1W
Short Circuit Output Current IOS 50 mA
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)
*1 :VCC+1.3V at pulse width≤15ns which is measured at VCC
*2 : -1.3 at pulse width≤15ns which is measured at VSS
Parameter Symbol Min Typ Max Units
Supply Voltage VCC 3.0 3.3 3.6 V
Ground VSS 0 0 0 V
Input High Voltage VIH 2.0 -VCC+0.3*1 V
Input Low Voltage VIL -0.3*2 -0.8 V
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Parameter Symbol Min Max Units
Input Leakage Current (Any input 0≤VIN≤VCC+0.3V,
all other pins not under test=0 Volt) II(L) -5 5uA
Output Leakage Current
(Data out is disabled, 0V≤VOUT≤VCC)IO(L) -5 5uA
Output High Voltage Level(IOH=-2mA) VOH 2.4 -V
Output Low Voltage Level(IOL=2mA) VOL -0.4 V
KM48V8000C,KM48V8100C CMOS DRAM
*Note : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one fast page mode cycle time, tPC.
DC AND OPERATING CHARACTERISTICS (Continued)
ICC1* : Operating Current (RAS and CAS, Address cycling @tRC=min.)
ICC2 : Standby Current (RAS=CAS=W=VIH)
ICC3* : RAS-only Refresh Current (CAS=VIH, RAS, Address cycling @tRC=min.)
ICC4* : Fast Page Mode Current (RAS=VIL, CAS, Address cycling @tPC=min.)
ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V)
ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min)
ICC7 : Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=CAS-before-RAS cycling or 0.2V,
W, OE=VIH, Address=Don′t care, DQ=Open, TRC=31.25us
ICCS : Self Refresh Current
RAS=CAS=0.2V, W=OE=A0 ~ A12(A11)=VCC-0.2V or 0.2V, DQ0 ~ DQ7=VCC-0.2V, 0.2V or Open
Symbol Power Speed Max Units
KM48V8000C KM48V8100C
ICC1 Don′t care -45
-5
-6
90
80
70
120
110
100
mA
mA
mA
ICC2 Normal
L Don′t care 1
11
1mA
mA
ICC3 Don′t care -45
-5
-6
90
80
70
120
110
100
mA
mA
mA
ICC4 Don′t care -45
-5
-6
70
60
50
70
60
50
mA
mA
mA
ICC5 Normal
LDon′t care 500
200 500
200 uA
uA
ICC6 Don′t care -45
-5
-6
120
110
100
120
110
100
mA
mA
mA
ICC7 LDon′t care 350 350 uA
ICCS LDon′t care 350 350 uA
KM48V8000C,KM48V8100C CMOS DRAM
CAPACITANCE (TA=25°C, VCC=3.3V, f=1MHz)
Parameter Symbol Min Max Units
Input capacitance [A0 ~ A12] CIN1 -5pF
Input capacitance [RAS, CAS, W, OE]CIN2 -7pF
Output capacitance [DQ0 - DQ7] CDQ -7pF
Test condition : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V
Parameter Symbol -45 -5 -6 Units Note
Min Max Min Max Min Max
Random read or write cycle time tRC 80 90 110 ns
Read-modify-write cycle time tRWC 115 133 153 ns
Access time from RAS tRAC 45 50 60 ns 3,4,10
Access time from CAS tCAC 12 13 15 ns 3,4,5
Access time from column address tAA 23 25 30 ns 3,10
CAS to output in Low-Z tCLZ 000ns 3
Output buffer turn-off delay tOFF 013 013 013 ns 6
Transition time (rise and fall) tT150 150 150 ns 2
RAS precharge time tRP 25 30 40 ns
RAS pulse width tRAS 45 10K 50 10K 60 10K ns
RAS hold time tRSH 12 13 15 ns
CAS hold time tCSH 45 50 60 ns
CAS pulse width tCAS 12 10K 13 10K 15 10K ns
RAS to CAS delay time tRCD 18 33 20 37 20 45 ns 4
RAS to column address delay time tRAD 13 22 15 25 15 30 ns 10
CAS to RAS precharge time tCRP 555ns
Row address set-up time tASR 000ns
Row address hold time tRAH 810 10 ns
Column address set-up time tASC 000ns
Column address hold time tCAH 810 10 ns
Column address to RAS lead time tRAL 23 25 30 ns
Read command set-up time tRCS 000ns
Read command hold time referenced to CAS tRCH 000ns 8
Read command hold time referenced to RAS tRRH 000ns 8
Write command hold time tWCH 810 10 ns
Write command pulse width tWP 810 10 ns
Write command to RAS lead time tRWL 13 15 15 ns
Write command to CAS lead time tCWL 12 13 15 ns
Data set-up time tDS 000ns 9
Data hold time tDH 10 10 10 ns 9
AC CHARACTERISTICS (0°C≤TA≤70°C, See note 2)
KM48V8000C,KM48V8100C CMOS DRAM
AC CHARACTERISTICS (Continued)
Parameter Symbol -45 -5 -6 Units Note
Min Max Min Max Min Max
Refresh period (Normal) tREF 64 64 64 ms
Refresh period (L-ver) tREF 128 128 128 ms
Write command set-up time tWCS 000ns 7
CAS to W delay time tCWD 32 36 38 ns 7
RAS to W delay time tRWD 67 73 83 ns 7
Column address to W delay time tAWD 43 48 53 ns 7
CAS precharge W delay time tCPWD 48 53 60 ns
CAS set-up time (CAS -before-RAS refresh) tCSR 555ns
CAS hold time (CAS -before-RAS refresh) tCHR 10 10 10 ns
RAS to CAS precharge time tRPC 555ns
Access time from CAS precharge tCPA 26 30 35 ns 3
Fast Page mode cycle time tPC 31 35 40 ns
Fast Page mode read-modify-write cycle time tPRWC 70 76 85 ns
CAS precharge time (Fast page cycle) tCP 910 10 ns
RAS pulse width (Fast page cycle) tRASP 45 200K 50 200K 60 200K ns
RAS hold time from CAS precharge tRHCP 28 30 35 ns
OE access time tOEA 12 13 15 ns 3
OE to data delay tOED 12 13 13 ns
Output buffer turn off delay time from OE tOEZ 013 0 13 0 13 ns 6
OE command hold time tOEH 12 13 15 ns
Write command set-up time (Test mode in) tWTS 10 10 10 ns 11
Write command hold time (Test mode in) tWTH 15 15 15 ns 11
W to RAS precharge time (C-B-R refresh) tWRP 10 10 10 ns
W to RAS hold time (C-B-R refresh) tWRH 10 10 10 ns
RAS pulse width (C-B-R self refresh) tRASS 100 100 100 us 13,14,15
RAS precharge time (C-B-R self refresh) tRPS 80 90 110 ns 13,14,15
CAS hold time (C-B-R self refresh) tCHS -50 -50 -50 ns 13,14,15
KM48V8000C,KM48V8100C CMOS DRAM
TEST MODE CYCLE
Parameter Symbol -45 -5 -6 Units Note
Min Max Min Max Min Max
Random read or write cycle time tRC 85 95 115 ns
Read-modify-write cycle time tRWC 120 138 160 ns
Access time from RAS tRAC 50 55 65 ns 3,4,10,12
Access time from CAS tCAC 17 18 20 ns 3,4,5,12
Access time from column address tAA 28 30 35 ns 3,10,12
RAS pulse width tRAS 50 10K 55 10K 65 10K ns
CAS pulse width tCAS 17 10K 18 10K 20 10K ns
RAS hold time tRSH 17 18 20 ns
CAS hold time tCSH 50 55 65 ns
Column Address to RAS lead time tRAL 28 30 35 ns
CAS to W delay time tCWD 37 41 43 ns 7
RAS to W delay time tRWD 72 78 88 ns 7
Column Address to W delay time tAWD 48 53 58 ns 7
Fast Page mode cycle time tPC 36 40 45 ns
Fast Page mode read-modify-write cycle time tPRWC 75 81 90 ns
RAS pulse width (Fast page cycle) tRASP 50 200K 55 200K 65 200K ns
Access time from CAS precharge tCPA 31 35 40 ns 3
OE access time tOEA 17 18 20 ns 3
OE to data delay tOED 17 18 18 ns
OE command hold time tOEH 17 18 20 ns
( Note 11 )
KM48V8000C,KM48V8100C CMOS DRAM
NOTES
An initial pause of 200us is required after power-up followed by any 8 ROR or CBR cycles before proper device operation is
achieved.
VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
Measured with a load equivalent to 1 TTL load and 100pF.
Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
Assumes that tRCD≥tRCD(max).
tOFF(min)and tOEZ(max) define the time at which the output achieves the open circuit condition and are not referenced Voh
or Vol.
tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electric charac-
teristics only. If tWCS≥tWCS(min), the cycles is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If tCWD≥tCWD(min), tRWD≥tRWD(min) and tAWD≥tAWD(min), then the cycle is a read-modify-write cycle
and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the
condition of the data out is indeterminate.
Either tRCH or tRRH must be satisfied for a read cycle.
This parameters are referenced to the CAS falling edge in early write cycles and to the W falling edge in read-modify-write
cycles.
Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only.
If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
These specifications are applied in the test mode.
In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
If tRASS≥100us, then RAS precharge time must use tRPS instead of tRP.
For RAS-only-Refresh and Burst CAS-before-RAS refresh mode, 4096 cycles(4K/8K) of burst refresh must be executed
within 64ms before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before
and after self refresh in order to meet refresh specification.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
1.
2.
3.
4.
15.
KM48V8000C,KM48V8100C CMOS DRAM
tCRP
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
OE VIH -
VIL -
VOH -
VOL -
DQ0 ~ DQ3(7)
READ CYCLE
COLUMN
ADDRESS
ROW
ADDRESS
tRAS tRC
tCRP
tRP
tCSH
tRSHtRCD tCAS
tRAL
tRAD
tASR tRAH tASC tCAH
tAA
tOEA
tCAC
tCLZ
tRAC
OPEN DATA-OUT
tOEZ
tRRH tRCH
Don′t care
Undefined
tRCS
tOFF
KM48V8000C,KM48V8100C CMOS DRAM
tWCS
WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
OE VIH -
VIL -
VIH -
VIL -
DQ0 ~ DQ3(7)
COLUMN
ADDRESS
ROW
ADDRESS
tRAS tRC
tCRP
tRP
tCSH
tRSHtRCD tCAS
tRAL
tRAD
tASR tRAH tASC tCAH
tCRP
tWP
tDS tDH
tWCH
tCWL
tRWL
Don′t care
DATA-IN
Undefined
KM48V8000C,KM48V8100C CMOS DRAM
tOED
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
OE VIH -
VIL -
VIH -
VIL -
DQ0 ~ DQ3(7)
COLUMN
ADDRESS
ROW
ADDRESS
tRAS tRC
tCRP
tRP
tCSH
tRSHtRCD tCAS
tRAL
tRAD
tASR tRAH tASC tCAH
tCRP
DATA-IN
tWP
Don′t care
WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tCWL
tRWL
tDS tDH
tOEH
Undefined
KM48V8000C,KM48V8100C CMOS DRAM
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
OE VIH -
VIL -
VI/OH -
VI/OL -
DQ0 ~ DQ3(7)
ROW
ADDR
tRAS tRWC tRP
tRSHtRCD tCAS
tCSH
tRAD
tASR tRAH tASC tCAH
tCRP
VALID
tWP
Don′t care
READ - MODIFY - WRTIE CYCLE
tRWL
tCWL
tOEZ
tOEA
tOED
tAWD
tCWD
tRWD
DATA-OUT
Undefined
VALID
DATA-IN
tRAC
tAA tCAC
tCLZ
tDS tDH
COLUMN
ADDRESS
KM48V8000C,KM48V8100C CMOS DRAM
tRCH
tOEZ
tCLZ
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
OE VIH -
VIL -
VOH -
VOL -
DQ0 ~ DQ3(7)
COLUMN
ADDRESS
ROW
ADDR
tRHCP
tRASP
tCAS
tASC
tRAD
tASR tRAH
tASC
tCAH
tCRP
VALID
Don′t care
FAST PAGE READ CYCLE
tOEZ
tRRH
DATA-OUT
Undefined
VALID
DATA-OUT
COLUMN
ADDRESS COLUMN
ADDRESS
tRSH
tCAS
tRCD
tPC
¡ó
tCSH tCAH tASC tCAH
¡ó
¡ó
¡ó
tRCH
¡ó
tRCS tRCStRCS
tOEA
tCAC tOEA
tCAC tOEA
tCAC
VALID
DATA-OUT
tCLZ
tOFF
tAA tOFF
tAA
tCLZ tOFF
tOEZ
tRAC
tAA
¡ó
¡ó
tCP
tCAS
tRP
tCP
tRAL
KM48V8000C,KM48V8100C CMOS DRAM
tASC
tCAH
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
OE VIH -
VIL -
VIH -
VIL -
DQ0 ~ DQ3(7)
COLUMN
ADDRESS
ROW
ADDR
tRHCP
tRASP
tCAS
tRAD
tASR tRAH
tASC
tCRP
VALID
Don′t care
FAST PAGE WRITE CYCLE ( EARLY WRITE )
DATA-IN
Undefined
VALID
DATA-IN
tDS
NOTE : DOUT = OPEN
COLUMN
ADDRESS COLUMN
ADDRESS
tRSH
tCAS
tRCD
tPC
¡ó
tCSH tCAH tCAH
¡ó
¡ó
¡ó
tWCS tWCH
tWCS
VALID
DATA-IN
¡ó
¡ó
tWP
tCWL
tWP
tWCH
tWP
tWCS tWCH
tCWL
tRWL
tCWL
tDH tDS tDH tDS tDH
¡ó
¡ó
¡ó
tRP
tCP
tCP
tCAS
tPC
tRAL
tASC
KM48V8000C,KM48V8100C CMOS DRAM
tCAC
tASC
tASC
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
OE VIH -
VIL -
VI/OH -
VI/OL -
DQ0 ~ DQ3(7)
ROW
ADDR
tCSH tRASP
tASR
VALID
Don′t care
FAST PAGE READ - MODIFY - WRITE CYCLE
DATA-OUT
Undefined
tRCD tCP
tRAD
tCAH
tWP
tDH
COL.
ADDR COL.
ADDR
tCAS tCAS
tCRP
tCAH tRAL
tPRWC
tRCS tCWL
tCWD
tAWD
tRWD
tWP
tCWD
tAWD
tCWL
tAA
tRAC
tOEA
tCLZ
tCAC
tOEZ
tCPWD
tOED
VALID
DATA-IN VALID
DATA-OUT VALID
DATA-IN
tCLZ
tDS
tOEA
tAA tDH
tDS
tOEZ
tOED
tRWL
tRP
tRSH
tRAH
KM48V8000C,KM48V8100C CMOS DRAM
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL - ROW
ADDR
tRAS tRC tRP
tASR tRAH
tCRP
Don′t care
RAS - ONLY REFRESH CYCLE
Undefined
NOTE : W, OE, DIN = Don′t care
DOUT = OPEN
tRPC tCRP
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE, A = Don′t care
RAS VIH -
VIL -
CAS VIH -
VIL -
tRAS tRC tRP
tWRP
tRPC
tRP
tCP
tCHR
tCSR
WVIH -
VIL -
tWRH
tOFF
tRPC
VOH -
VOL -
DQ0 ~ DQ3(7)
OPEN
KM48V8000C,KM48V8100C CMOS DRAM
tWRH
tOFF
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
OE VIH -
VIL -
VOH -
VOL -
DQ0 ~ DQ3(7)
HIDDEN REFRESH CYCLE ( READ )
COLUMN
ADDRESS
ROW
ADDRESS
tRAS tRC
tCHRtRCD
tRAD
tASR tRAH tASC tCAH
tCRP
tRCS
tAA
tOEA
tCAC
tCLZ
tRAC
OPEN
Don′t care
tRSH
tOEZ
Undefined
tRC
DATA-OUT
tRP tRP
tRAS
tRAL
KM48V8000C,KM48V8100C CMOS DRAM
RAS VIH -
VIL -
CAS VIH -
VIL -
AVIH -
VIL -
WVIH -
VIL -
OE VIH -
VIL -
VIH -
VIL -
DQ0 ~ DQ3(7)
HIDDEN REFRESH CYCLE ( WRITE )
COLUMN
ADDRESS
ROW
ADDRESS
tRAS tRC
tCHR
tRCD
tRAD
tASR tRAH tASC tCAH
tCRP
Don′t care
tRSH
DATA-IN
tWRP
tWRH
Undefined
tRC
NOTE : DOUT = OPEN
tWCH
tWP
tDH
tRPtRP tRAS
tDS
tWCS
tRAL
KM48V8000C,KM48V8100C CMOS DRAM
Don′t care
Undefined
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Don′t care
RAS VIH -
VIL -
CAS VIH -
VIL -
tRASS tRPS
tRPC
tWRP
tCHS
tRP
tCP
tCSR
WVIH -
VIL -
tWRH
tOFF
tRPC
OPEN
VOH -
VOL -
DQ0 ~ DQ3(7)
TEST MODE IN CYCLE
NOTE : OE, A = Don′t care
RAS VIH -
VIL -
CAS VIH -
VIL -
tRAS tRC tRP
tRPC
tWTS
tRPC
tRP
tCP
tCHR
tCSR
WVIH -
VIL -
tWTH
tOFF
OPEN
VOH -
VOL -
DQ0 ~ DQ3(7)
KM48V8000C,KM48V8100C CMOS DRAM
32 SOJ 400mil
0.400 (10.16)
0.435 (11.06)
0.445 (11.30)
0.830 (21.08)
0.820 (20.84)
MAX
0.841 (21.36)
MAX
0.148 (3.76)
0.032 (0.81)
0.026 (0.66)
0.021 (0.53)
0.015 (0.38)
0.027 (0.69)
0.012 (0.30)
0.006 (0.15)
0.360 (9.15)
0.380 (9.65)
MIN
#32
#1
0.0375 (0.95) 0.050 (1.27)
Units : Inches (millimeters)
PACKAGE DIMENSION
32 TSOP(II) 400mil
0.455 (11.56)
0.471 (11.96)
0.829 (21.05)
0.821 (20.85)
MAX
0.841 (21.35)
0.037 (0.95) 0.050 (1.27)
Units : Inches (millimeters)
0.047 (1.20)
MIN
0.002 (0.05)
0.020 (0.50)
0.012 (0.30)
MAX
0.010 (0.25)
0.004 (0.10)
0.400 (10.16)
0~8
0.030 (0.75)
0.018 (0.45)
TYP
0.010 (0.25)
O
