Cinayv Vif SIGNAL PROCESSING EXCELLENCE SP7512 Double Buffered 12-Bit MDAC FEATURES Monolithic Construction SOIC Package For Surface Mount 12 Bit Resolution 0.01% Non-Linearity pP Compatible Latch-up Protected Low Power - 30mW APPLICATIONS B Function Generators M Programmable Amplifiers Bf Digitally Controlled Attenuators 8 Digitally Controlled Power Supplies DESCRIPTION The $P7512 is a precision monolithic 12-bit multiplying DAC with internal two-stage input storage registers for easy interfacing with microprocessor busses. If is packaged in a 28-pin SOIC to give high I/O design flexibility. Double-Buffered The input registers are sectioned into 3 segments of 4 bits each, all individually addressable. The DAC-register, following the input registers, is a parallel 12-bit register for holding the DAC data while the input registers are updated. Only the data held in the DAC register determines the analog output value of the converter. Microprocessor Compatible The $P7512 has been designed for great flexibility in connecting to bus-oriented systems. The 12 data inputs are organized into 3 independent addressable 4-bit input registers such that the $P7512 can be connected to either a 4, 8 or 16-bit data bus. The control logic of the $P7512 in- cludes chip enable and latch enable inputs for flexible memory mapping. All controls are level-triggered to allow static or dynamic operation. Versatile Outputs A total of 5 output lines are provided by the $P7512 to allow unipolar and bipolar output connection with a minimum of external components. The feedback resistor is internal. The resistor ladder network termination is externally available, thus eliminating an external resistor for the 1 LSB offset in bipolar mode. Monolithic Construction The $P7512 is a one-chip CMOS circuit with a resistor ladder network designed for 0.01% linearity without laser trimming. Small chip size and high manufacturing yields result in greatly reduced cost. 7-63CAUTION: ESD (ElectroStatic Discharge) sensitive device. Permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. Personnel should be properly grounded prior to handling this device. The protective foam should be discharged to the destination socket before davices are removed. Specifications Cypical @ 25C, nominal power supply, Vege = + OV, unipolar unless otherwise noteq). PARAMETER MIN TYP MAX UNITS CONDITIONS DIGITAL INPUT Resolution 12 Bits 2-Quad, Unipolar Coding Binary & Comp. Binary The input coding is complemen I | tary binary if |,, is used. 4-Quad, Bipolar Coding Offset Binary Logic Compatibility CMOS, TIL Digital input voltage must not exceed supply voltage or go below -0.5V ; 0 <0.8V; 24V <1" SVL input Current +] WA Data Set-up Time 250 ns |All strobes are level triggered. See Timing Diagram. Strobe Width 250 ns |All strobes are level triggered. See Timing Diagram. Data Hold Time 0 ns |All strobes are level triggered. See Timing Diagram. REFERENCE INPUT Voltage Range 425 Vv Input Impedance 4K 12K Q ANALOG OUTPUT Scale Factor 62.5 187.5 BA/V occ Scale Factor Accuracy +0.4 % | Using the internal feedback resistor and an extemal opamp. Output Leakage 10 nA | At 25C, the output leakage current will create an offset voltage at the external opamps output. tt doubles every 10C temperature increase. Output Capacitance Coy, 1 allinputs high 80 pF Coy, 1 all inputs low 40 pF Cay, 2, all inputs high 40 pF Cy, 2, all inputs low 80 pF STATIC PERFORMANCE Integral Linearity -KN +0.015 % FSR ~JN +0.05 % FSR Differential Linearity -KN +0.024 -JN +0.097 % FSR Monotonicity -KN Guaranteed to 12 bits -JIN Guaranteed to 10 bits Monotonicity Temp. Range | 0 | | +70 C 7-64Specifications (Typical @ 25C, nominal power supply, Vpee = + 10V. unipolar unless otherwise noted). PARAMETER MIN TYP MAX UNITS CONDITIONS DYNAMIC PERFORMANCE Digital Small Signal Settling 1.0 us Full Scale Transition Settling 2.0 uS | to 0.01% (strobed) Reference Feedthrough Error (Vee: = 2ZOVP) @ 1kHz ] mvV @ 10kHz 2 mV Delay to output from Bits input 100 ns | Delay times are twice the from LDAC 200 ns | amount shown at T, = +125 C from CE 120 ns STABILITY Ty, TO Ty) Scale Factor 2 ppm FSR/C | At 25C, the output leakage current will create an offset voltage output. It doubles every 10C temperature increase. Integral Linearity 0.2 | ppm FSR/C Differential Linearity 0.2 | ppm FSR/C Monotonicity Temp. Range 0 +70 C POWER SUPPLY (V,,,) Operating Voltage +15 +5% V | specifications guaranteed Voltage Range +5 +16 Vv Current 2.5 mA Rejection Ratio 0.002 Sol % TEMPERATURE RANGE Operating 0 +70 C Storage -65 +150 C MECHANICAL Case Style 28-pin SOIC 4 i Ordering Information Double Buffered MDAC 10-Bit Monotonicity: SP7S12IN oo. .eccccceeceeeseseeeeentesenseeneenenes 28-pin SOIC 12-Blt Monotonicity: SP75 12KN ..W0... ee eeeeceeeeeeeeeeeeeeeeeeeeeeees 28-pin SOIC 7-65TRANSFER FUNCTION (N=12) TIMING DIAGRAM BINARY INPUT | UNIPOLAR OUTPUT | BIPOLAR OUTPUT west DW -Vaer 1 - 2N) -Vpep (1-2 (N- DY 100...001 Ver (1/2 + 2N) ~-Vper (2 (N- D) ce 100...000 Vey 0 2 LBE O11...111 Veer (1/2 - 2) Veer (2 N-1) 000...000 0 Vere MBE BIPOLAR OFFSET ADJUST (EXTERNAL) -15V +15V tac aa tp a 20k 7 AAW OUTPUT it el tae TIME AXIS NOT TO SCALE. ALL STROBES ARE LEVEL TRIGGERED. f,: Data Setup Time. Time data must be stable before strobe (byte enable 4M LDAC) goes to0, t; (min) = 250 nsec. fo: Strobe Width. to (min) = 250 nsec. (CE, LBE, MBE, HBE, LDAC). ADJUSTMENT ts: Hold Time. Time data must be stable after strobe goes to *0", tz =0 RANGE 0.2% nsec. tg: Delay from LDAC to Output, t, = 200 nsec. NOTE: Minimum commen active time for CE and any byte enable is 250 TOloy nsec. NOTE: External opamps have to be zeroed before the bipolar offset adjust circuit is connected CONTROL LOGIC STROBE LOGIC t r+} TO INPUT REGISTER BIT 1-BIT 4 HEE O+ Strobe Function TO INPUT REGISTER BIT 5-BIT 8 MBE O 0 data latched (held) TO INPUT REGISTER BIT 9-BIT 12 LBE ] data changing (transfer) LoAG Go-To DAC REGISTER NOTE: The transfer from inut register to DAC register can be performed without Enabling Chip. FUNCTIONAL BLOCK DIAGRAM (MSB) (LSB) ait 2 3 4 5 6 7 B 9 10 11 BIT12 VREF 9 o 6 9 9 9 o 9 9 9 9} 10 it te 13 4 15] 16 17| 18 19] 20 4 eo F| INPUT REGISTER INPUT REGISTER -| INPUT REGISTER 25 HBEO CONTROL 24 LOGIC MBE 0 R 5 23 FBy LBEO 6 a1 0 lor LDAC O- DAC REGISTER 12 BIT MDAC , 7 0 loo 1 O FB4 re Rie 3 FB3 28 26 27 8 2 vont Vpp2 GND GND LOTR 7-66PIN ASSIGNMENTS APPLICATIONS INFORMATION PIN] FUNCTION Unipolar Operation 1 | FB, Feedback Bioolar Overall Figure 1 shows the interconnections for APeeN unipolar operation. Connect |,, and FB, as 2 | LDIR, Ladder Termination shown in diagram. Tie |,, (Pin 7), FB, (Pin 3), 3 | FB, Feedback Bipolar Operation and FB, (Pin 1) to Ground (Pin 8). To 4 | Veer. Reference Voltage Input mainvan spscied Hoenn oest d " - amplifiers must be zeroed. This is best done 5 | FB,, Feedback, Unipolar/Bipolar . . oh * S ONE with V,,., set to zero and, with the DAC jo. Current out into virtual ground register loaded with all bits at zero, adjust 7 | log, Current out-complement of Ip; Rog for Vour =0V 8 | Vsg, Ground, Analog and DAC Register 9 | Bit 1, MsB Bipolar Operation 10 | Bite Figure 2 shows the interconnections for 17 I pia bipolar operation. Connect |, |,,, FB. FB,. FB, as shown in diagram. Tie LDTR to I,,. To 12 | bit4 maintain specified linearity, external 13 | Bits amplifiers must be zeroed. This is best done 14 | Bit6 with V,,,, set to zero and, the DAC register 15 | Bit7 loaded with 10...0 (MSB = 1), set R,,., for 16 | Bre Vour = OV. Then set R.., for V,.; = OV. 7 | Bio Grounding 18 | Bit 10 Connect all GND pins to system analog 19 | Bit ground and tie this to digital ground. All >0 | Bi Ie unused input pins must be grounded. 21 | LDAC, Transfers data from input to DAC register 22 | CE, Chip Enable, active low 23 | LBE, Bit 12 to Bit 9 Enable 24 | MBE, Bit 8 to Bit 5 Enable 25 | HBE. Bit 4 to Bit 1 Enable 26 | Vop2. Supply Analog and DAC Register 27 | Vsg1. Ground input latches 28 | Vop1, Supply input latches NOTE: Pins 8 and 27 and pins 26 and 28 must be con- nected externally. oe VREF we +15 VREF wv vey | Ypp2 | Ypp1 | Yooa_| Yoo om iam 1 1 i P7512 pig. | Sp7512 Reuts SP75 i 1 } i o> o| ceo Vss | Vssi ceo] HBE HBE MBE O" MBE O so LBe o! = Lge oO] VOUT! Loac O_ tbac oO - Ay, Ao, LFATIACN Figure 1. Unipolar Operation Figure 2. Bipolar Operation 7-67This page ief inventionclly blank. 7-68