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The AT87F52 provides the following standard features: 8K
bytes of QuickF lash , 256 byt es of RAM, 32 I/O lines , three
16-bit timer/counters, a six-vector two-level interrupt archi-
tecture, a full duplex serial port, on-chip oscillator, and
clock circuitry. In addition, the AT87F52 is designed with
static logic for oper ation down to zero frequency and sup-
ports tw o software selectable power saving mo des. The
Idle Mode stops the CPU while allowing the RAM,
timer/c oun ters, ser ial port, and int er rupt s ystem to conti nue
func tioning. The Pow er Down M ode save s the RAM c on-
tents but freezes the oscillator, disabling all other chip func-
tions until the next hardware reset.
Pin Description
VCC
Supply voltage.
GND
Ground.
Port 0
Port 0 is an 8-bit open drain bidirectional I/O port. As an
output port, each pin can sink eight TTL inputs. When 1s
are written to port 0 pins, the pins can be used as high-
impedance inputs.
Port 0 can also be configu red to be the multiplexed low-
order address/data bus during accesses to external pro-
gram and data memory. In this mode, P0 has internal pul-
lups.
Port 0 a lso rece ives the code bytes du ring Qui ckFl ash pr o-
grammin g a nd outputs th e c od e by te s dur in g p ro gram ve ri -
fication. External pullups are required during program verifi-
cation.
Port 1
Port 1 is a n 8- bit bi dire ction al I/O por t with inter nal pullu ps.
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins , they are p ulled high by
the internal pullups and can be us ed as inputs. As i nputs,
Port 1 pins that are externally being pulled low will source
current (IIL) because of the internal pullups.
In addition, P1.0 and P1.1 can be configured to be the
timer/counter 2 external count input (P1.0/T2) and the
timer/counter 2 trigger input (P1.1/T2EX), respec tively, as
shown in the followi ng table.
Port 1 also receives the low-order address bytes during
QuickFlash programming and verification.
Port 2
Port 2 is an 8-b it bidirectiona l I/O port with in ternal pullup s.
The Port 2 output buffers can sink/source four TTL inputs.
When 1s are writte n to Port 2 pi ns, they are pu lled hi gh by
the internal pul lups and can be us ed as inputs. As i nputs,
Port 2 pins that are externally being pulled low will s ource
current (IIL) because of the internal pullups.
Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external da ta m emo r y th at u se 16-bit a ddres s es ( MOVX @
DPTR). In this application, Port 2 uses strong internal pul-
lups when emitting 1s. During access es to external data
memory that use 8-bit addresses (MOVX @ RI), Port 2
emits the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some
control signals during QuickFlash programming and verifi-
cation.
Port 3
Port 3 is an 8-b it bidirectiona l I/O port with in ternal pullup s.
The Port 3 output buffers can sink/source four TTL inputs.
When 1s are writte n to Port 3 pi ns, they are pu lled hi gh by
the internal pul lups and can be us ed as inputs. As i nputs,
Port 3 pins that are externally being pulled low will s ource
current (IIL) because of the pullups.
Port 3 also serves the funct ions of var ious s peci al featu res
of the AT89C51, as shown in the following table.
Port 3 also receives some control signals for QuickFlash
programming and verification.
RST
Reset input. A high on this pin for two machine cycles while
the oscill ator is runni ng re se ts the dev ic e.
ALE/PROG
Address Latch Enabl e is an output pulse for latching the
low byte of the address during accesses to external mem-
ory . Thi s pin is al so t h e pr og ra m pu l se in p ut ( PR OG) during
QuickFlash programming.
In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency and may be used for external tim-
ing or clocking purposes. Note, however, that one ALE
Port Pin Alternate Functions
P1.0 T2 (external count input to Timer/Counter 2),
clock-out
P1.1 T2EX (Timer/Counter 2 capture/reload trigger
and direction control)
Port Pin Alternate Functions
P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2 INT0 (external interrupt 0)
P3.3 INT1 (external interrupt 1)
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6 WR (external data memory write strobe)
P3.7 RD (external data memory read strobe)