BLOCK DIAGRAM IS SHOWN BELOW IN4 Vee OUT, OUT 4 12 Q 8 7 c aa a aa Neer asa x Y : x | ECL 100K ECL 100K l INPUT Bae: OUTRUT | BUFFER BUFFER | | xy xy | ECL100K ECL 100K | INPUT ee RL ouTPUT | | BUFFER BUFFER | Y 1 4 5 6 IN9 Veo OUT OUT? MECHANICAL DETAIL IS SHOWN BELOW perro INy V_OUT, OUT, B75 @DECLDL-2-__ iN> VOUTZOUT, 1 7 | 8432 30 325 MADE IN SLO USA I ij , | L 160+.030 LN OO ced) Lge lL I TYP, 020 DIA. TYP, 100 TYP, = bay Tee | (** TYP. ! * Supply valtage: + + = OPERATING SPECIFICATIONS Logic 1 Input at 25C: Voltage - Current + Lagic O Input at25 C: Voltage Current Logic 1 Output at 25 C: Logic O Qutput at 25C: + +-- Operating temperature range: Storage temperature: = + 155ma typical - 1.165 min. 350ua max. .5Ua min. = 1.025 min. Hae = 1.620 max. Oto +85C -55 to +125 C * Delays increase ar decrease less than .5% for a respective increase or decrease of 5% in supply voltage. PART NUMBER TABLE # DELAYS AND TOLERANCES (in ns) [ o 8 o o oa Sg ae | FOO o 250 TYP.+| TEST CONDITONS 1. All measurements are made at 25C. | 2. Vee supply voltage is maintained at 4.6V DC. 3. All units are tested using a positive input pulse provided by a standard open emitter ECL 100K gate. The input and output utilizes a 50 ohm pull-down resistor to - 2; the output is alsa loaded with ane ECL 100K gate. m4, module under test; spacing between pulses [falling edge to rising edge) is three times the pulse width used, Input pulse width used ig 5 to 10ns longer than full delay of -4.5V 45% to Vee - 1475 max. PART NO. OUTPUT || PART NO. OUTPUT DECLDL- 2-2 2t.2 DECGLDL- 2-10 10+1 DECLDL-?2- 2.5 2.54.2 DECLDL-2- 10.5 10.521 DECLDOL-2-3 34.3 DECLDBL-2-11 1144 DECLDL=2-3.5 3.54.3 DECLDBL-2-11.5 11.541 DECLDL-2-4 4.4 DECLBL- 2-12 1241 DECLDL=2-4,5 4.52.4 DECLDOL-2- 12.5 12.541 DECLDL- 2-5 61.5 DECLOL-2- 13 1321 DECLDL-2-5.5 5.54.5 DECLDL=2- 13.5 13.521 DECLDL- 2-6 64.6 DECLDL- 2-14 1441 DECLDL-2- 6.5 6.54.6 DECLDL-2- 14.5 14.541 DECLDL-2-7 TtF |] DECLDL- 2-15 1541 DECLDL-2- 7.5 7.54.7 |/DECLDL- 2-16 1641 DECLDL-2-8 6+.8 DECLDL- 2-17 +1 DECLDL-2- 8.5 8.54.8 DECLDL-2- 18 18+1 DECLDL-2-9 O+,9 DECLDL-=2- 19 1921 DECLDL-2-9.5 9,5+,9 DECLBOL- 2-20 20% 1 All modules can be operated with a minimum input pulse width of 100% of full delay and pulse period approaching square wave; since delay accuracies may be somewhat degraded, it is suggested that the module be evaluated under the intended specific oper- ating conditions. Special modules can be readily manufactured to improve accuracies and/or provide customer specified random delay times for specific applications, Catalog No. C/012580