FUNCTIONAL BLOCK DIAGRAM
A1
RS
RZ1
RZ2
RFRT
RI
AD586
GROUND
VIN NOISE REDUCTION
VOUT
TRIM
NOTE: PINS 1, 3, AND 7 ARE INTERNAL TEST POINTS.
MAKE NO CONNECTIONS TO THESE POINTS.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
High Precision
5 V Reference
AD586
FEATURES
Laser Trimmed to High Accuracy:
5.000 V ⴞ2.0 mV (M Grade)
Trimmed Temperature Coefficient:
2 ppm/ⴗC Max, 0ⴗC to 70ⴗC (M Grade)
5 ppm/ⴗC Max, –40ⴗC to +85ⴗC (B and L Grades)
10 ppm/ⴗC Max, –55ⴗC to +125ⴗC (T Grade)
Low Noise, 100 nV/√Hz
Noise Reduction Capability
Output Trim Capability
MIL-STD-883-Compliant Versions Available
Industrial Temperature Range SOICs Available
Output Capable of Sourcing or Sinking 10 mA
PRODUCT DESCRIPTION
The AD586 represents a major advance in the state-of-the-art in
monolithic voltage references. Using a proprietary ion-implanted
buried Zener diode and laser wafer trimming of high stability
thin-film resistors, the AD586 provides outstanding perfor-
mance at low cost.
The AD586 offers much higher performance than most other
5 V references. Because the AD586 uses an industry standard
pinout, many systems can be upgraded instantly with the AD586.
The buried Zener approach to reference design provides lower
noise and drift than bandgap voltage references. The AD586
offers a noise reduction pin which can be used to further reduce
the noise level generated by the buried Zener.
The AD586 is recommended for use as a reference for 8-, 10-,
12-, 14-, or 16-bit D/A converters which require an external
precision reference. The device is also ideal for successive
approximation or integrating A/D converters with up to 14 bits
of accuracy and, in general, can offer better performance than
the standard on-chip references.
The AD586J, K, L, and M are specified for operation from 0°C
to 70°C, the AD586A and B are specified for –40°C to +85°C
operation, and the AD586S and T are specified for –55°C to
+125°C operation. The AD586J, K, L, and M are available in
an 8-lead plastic DIP. The AD586J, K, L, A, and B are avail-
able in an 8-lead plastic surface mount small outline (SO)
package. The AD586J, K, L, S, and T are available in an 8-lead
cerdip package.
PRODUCT HIGHLIGHTS
1. Laser trimming of both initial accuracy and temperature
coefficients results in very low errors over temperature with-
out the use of external components. The AD586M has a
maximum deviation from 5.000 V of ±2.45 mV between
0°C and 70°C, and the AD586T guarantees ±7.5 mV maxi-
mum total error between –55°C and +125°C.
2. For applications requiring higher precision, an optional fine-
trim connection is provided.
3. Any system using an industry standard pinout reference can
be upgraded instantly with the AD586.
4. Output noise of the AD586 is very low, typically 4 µV p-p. A
noise reduction pin is provided for additional noise filtering
using an external capacitor.
5. The AD586 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD586/883B data sheet for detailed
specifications.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2001
AD586–SPECIFICATIONS
(@ T
A
= 25ⴗC, V
IN
= 15 V unless otherwise noted.)
AD586J AD586K/A AD586L/B AD586M AD586S AD586T
Model Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
Output Voltage 4.980 5.020 4.995 5.005 4.9975 5.0025 4.998 5.002 4.990 5.010 4.9975 5.0025 V
Output Voltage Drift
l
0°C to 70°C25 15 5 2 ppm/°C
–55°C to +125°C20 10 ppm/°C
Gain Adjustment +6 +6 +6 +6 +6 +6 %
–2 –2 –2 –2 –2 –2 %
Line Regulation
1
10.8 V < +V
IN
< 36 V
T
MIN
to T
MAX
100 100 100 100 ±µV/V
11.4 V < +V
IN
< 36 V
T
MIN
to T
MAX
150 150 ±µV/V
Load Regulation
l
Sourcing 0 < I
OUT
< 10 mA
25°C100 100 100 100 150 150 µV/mA
T
MIN
to T
MAX
100 100 100 100 150 150 µV/mA
Sinking –10 < I
OUT
< 0 mA
25°C400 400 400 400 400 400 µV/mA
Quiescent Current 2 32323232323mA
Power Consumption 30 30 30 30 30 30 mW
Output Noise
0.1 Hz to 10 Hz 4 4 4 4 4 4 µV p-p
Spectral Density, 100 Hz 100 100 100 100 100 100 nV/√Hz
Long-Term Stability 15 15 15 15 15 15 ppm/1000 Hr
Short-Circuit Current-to-Ground 45 60 45 60 45 60 45 60 45 60 45 60 mA
Temperature Range
Specified Performance
2
0 70 0 70 0 70 0 70 –55 +125 –55 +125 °C
–40 +85 –40 +85 °C
Operating Performance
3
–40 +85 –40 +85 –40 +85 –40 +85 –55 +125 –55 +125 °C
NOTES
1
Maximum output voltage drift is guaranteed for all packages and grades. Cerdip packaged parts are also 100°C production tested.
2
Lower row shows specified performance for A and B grades.
3
The operating temperature range is defined as the temperatures extremes at which the device will still function. Parts may deviate from their specified performance outside their
specified temperature range.
Specifications subject to change without notice.
Specifications in boldface are rested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifica-
tions are guaranteed, although only those shown in boldface are tested on all production units unless otherwise specified.
ABSOLUTE MAXIMUM RATINGS*
V
IN
to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 V
Power Dissipation
(25°C) . . . . . . . . . . . . . . . . . . . . . 500 mW
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temp (Soldering, 10 sec) . . . . . . . . . . . . . . . . . . . 300°C
Package Thermal Resistance
θ
JC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22°C/W
θ
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110°C/W
Output Protection: Output safe for indefinite short to ground
or V
IN
.
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CONNECTION DIAGRAM
(Top View)
*TP DENOTES FACTORY TEST POINT.
NO CONNECTIONS, EXCEPT DUMMY PCB PAD,
SHOULD BE MADE TO THESE POINTS.
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
TP*
V
IN
TP*
NOISE
REDUCTION
TP*
V
OUT
TRIM
GND
AD586
–2– REV. D
AD586
REV. D –3–
The following specifications are tested at the dice level for AD586JCHIPS. These die are probed at 25ⴗC
only. (TA = 25ⴗC, VIN = 15 V unless otherwise noted.)
DlE SPECIFlCATIONS
AD586JCHIPS
Parameter Min Typ Max Unit
Output Voltage 4.980 5.020 V
Gain Adjustment +6 %
–2 %
Line Regulation
10.8 V < + V
IN
< 36 V 100 ±µV/V
Load Regulation
Sourcing 0 < I
OUT
< 10 mA 100 µV/mA
Sinking –10 < I
OUT
< 0 mA 400 µV/mA
Quiescent Current 3 mA
Short-Circuit Current-to-Ground 60 mA
NOTES
1
Both V
OUT
pads should be connected to the output.
Die Thickness: The standard thickness of Analog Devices Bipolar dice is 24 mils ± 2 mils.
Die Dimensions: The dimensions given have a tolerance of ±2 mils.
Backing: The standard backside surface is silicon (not plated). Analog Devices does not
recommend gold-backed dice for most applications.
Edges: A diamond saw is used to separate wafers into dice thus providing perpendicular
edges halfway through the die.
In contrast to scribed dice, this technique provides a more uniform die shape and size. The
perpendicular edges facilitate handling (such as tweezer pick-up) while the uniform shape
and size simplifies substrate design and die attach.
Top Surface: The standard top surface of the die is covered by a layer of glassivation. All
areas are covered except bonding pads and scribe lines.
Surface Metalization: The metalization to Analog Devices bipolar dice is aluminum.
Minimum thickness is 10,000Å.
Bonding Pads: All bonding pads have a minimum size of 4 mils by 4 mils. The passivation
windows have 3.5 mils by 3.5 mils minimum.
ORDERING GUIDE
Initial Temperature Temperature Package Package
Model*Error Coefficient Range Description Option
AD586JN 20 mV 25 ppm/°C0°C to 70°C Plastic DIP N-8
AD586JQ 20 mV 25 ppm/°C0°C to 70°C Cerdip Q-8
AD586JR 20 mV 25 ppm/°C0°C to 70°C SOIC SO-8
AD586KN 5 mV 15 ppm/°C0°C to 70°C Plastic DIP N-8
AD586KQ 5 mV 15 ppm/°C0°C to 70°C Cerdip Q-8
AD586KR 5 mV 15 ppm/°C0°C to 70°C SOIC SO-8
AD586LN 2.5 mV 5 ppm/°C0°C to 70°C Plastic DIP N-8
AD586LR 2.5 mV 5 ppm/°C0°C to 70°C SOIC SO-8
AD586MN 2 mV 2 ppm/°C0°C to 70°C Plastic DIP N-8
AD586AR 5 mV 15 ppm/°C–40°C to +85°C SOIC SO-8
AD586BR 2.5 mV 5 ppm/°C–40°C to +85°C SOIC SO-8
AD586LQ 2.5 mV 5 ppm/°C0°C to 70°C Cerdip Q-8
AD586SQ 10 mV 20 ppm/°C –55°C to +125°C Cerdip Q-8
AD586TQ 2.5 mV 10 ppm/°C –55°C to +125°C Cerdip Q-8
AD586JCHIPS 20 mV 25 ppm/°C0°C to 70°C
*For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military Products Databook or
current AD586/883B data sheet.
DIE LAYOUT
Die Size: 0.096
ⴛ
0.061 Inches
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD586 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
AD586
REV. D
–4–
THEORY OF OPERATION
The AD586 consists of a proprietary buried Zener diode refer-
ence, an amplifier to buffer the output and several high stability
thin-film resistors as shown in the block diagram in Figure 1.
This design results in a high precision monolithic 5 V output
reference with initial offset of 2.0 mV or less. The temperature
compensation circuitry provides the device with a temperature
coefficient of under 2 ppm/°C.
Using the bias compensation resistor between the Zener output
and the noninverting input to the amplifier, a capacitor can be
added at the NOISE REDUCTION pin (Pin 8) to form a low-
pass filter and reduce the noise contribution of the Zener to
the circuit.
A1
RS
RZ1
RZ2
RFRT
RI
AD586
GROUND
VIN NOISE REDUCTION
VOUT
TRIM
NOTE: PINS 1, 3, AND 7 ARE INTERNAL TEST POINTS.
MAKE NO CONNECTIONS TO THESE POINTS.
Figure 1. Functional Block Diagram
APPLYING THE AD586
The AD586 is simple to use in virtually all precision refer-
ence applications. When power is applied to Pin 2 and Pin 4
is grounded, Pin 6 provides a 5 V output. No external compo-
nents are required; the degree of desired absolute accuracy is
achieved simply by selecting the required device grade. The
AD586 requires less than 3 mA quiescent current from an
operating supply of 12 V or 15 V.
An external fine trim may be desired to set the output level to
exactly 5.000 V (calibrated to a main system reference). System
calibration may also require a reference voltage that is slightly
different from 5.000 V, for example, 5.12 V for binary applica-
tions. In either case, the optional trim circuit shown in Figure 2
can offset the output by as much as 300 mV, if desired, with
minimal effect on other device characteristics.
AD586
GND
V
IN
NOISE
REDUCTION
VO
TRIM
OPTIONAL
NOISE
REDUCTION
CAPACITOR
VIN
OUTPUT
CN
1␮F
10k⍀
Figure 2. Optional Fine Trim Configuration
NOISE PERFORMANCE AND REDUCTION
The noise generated by the AD586 is typically less than 4 µV p-p
over the 0.1 Hz to 10 Hz band. Noise in a 1 MHz bandwidth is
approximately 200 µV p-p. The dominant source of this noise is
the buried Zener which contributes approximately 100 nV/√Hz. In
comparison, the op amp’s contribution is negligible. Figure 3
shows the 0.1 Hz to 10 Hz noise of a typical AD586. The noise
measurement is made with a bandpass filter made of a 1-pole
high-pass filter with a corner frequency at 0.1 Hz and a 2-pole
low-pass filter with a corner frequency at 12.6 Hz to create a
filter with a 9.922 Hz bandwidth.
If further noise reduction is desired, an external capacitor may
be added between the NOISE REDUCTION pin and ground as
shown in Figure 2. This capacitor, combined with the 4 kΩ R
S
and the Zener resistances form a low-pass filter on the output of
the Zener cell. A 1 µF capacitor will have a 3 dB point at 12 Hz,
and it will reduce the high frequency (to 1 MHz) noise to about
160 µV p-p. Figure 4 shows the 1 MHz noise of a typical AD586
both with and without a 1 µF capacitor.
Figure 3. 0.1 Hz to 10 Hz Noise
Figure 4. Effect of 1
µ
F Noise Reduction Capacitor on
Broadband Noise
AD586
REV. D –5–
TURN-ON TIME
Upon application of power (cold start), the time required for the
output voltage to reach its final value within a specified error
band is defined as the turn-on settling time. Two components
normally associated with this are: the time for the active circuits
to settle, and the time for the thermal gradients on the chip to
stabilize. Figure 5 shows the turn-on characteristics of the
AD586. It shows the settling to be about 60 µs to 0.01%. Note
the absence of any thermal tails when the horizontal scale is
expanded to l ms/cm in Figure 5b.
Output turn-on time is modified when an external noise reduc-
tion capacitor is used. When present, this capacitor acts as an
additional load to the internal Zener diode’s current source,
resulting in a somewhat longer turn-on time. In the case of a
1 µF capacitor, the initial turn-on time is approximately 400 ms
to 0.01% (see Figure 5c).
a. Electrical Turn-On
b. Extended Time Scale
c. Turn-On with 1
␮
F C
N
Figure 5. Turn-On Characteristics
DYNAMIC PERFORMANCE
The output buffer amplifier is designed to provide the AD586
with static and dynamic load regulation superior to less com-
plete references.
Many A/D and D/A converters present transient current loads
to the reference, and poor reference response can degrade the
converter’s performance.
Figure 6 displays the characteristics of the AD586 output ampli-
fier driving a 0 mA to 10 mA load.
AD586
V
L
5V
0V
V
OUT
500⍀
3.5V
Figure 6a. Transient Load Test Circuit
Figure 6b. Large-Scale Transient Response
Figure 6c. Fine-Scale Setting for Transient Load
AD586
REV. D
–6–
Centigrade; i.e., ppm/°C. However, because of nonlinearities in
temperature characteristics which originated in standard Zener
references (such as “S” type characteristics), most manufactur-
ers have begun to use a maximum limit error band approach to
specify devices. This technique involves the measurement of the
output at three or more different temperatures to specify an
output voltage error band.
Figure 9 shows the typical output voltage drift for the AD586L
and illustrates the test methodology. The box in Figure 9 is
bounded on the sides by the operating temperature extremes,
and on the top and the bottom by the maximum and minimum
output voltages measured over the operating temperature range.
The slope of the diagonal drawn from the lower left to the upper
right corner of the box determines the performance grade of
the device.
–200 20406080
5.003
5.000
TEMPERATURE – ⴗC
V
MIN
V
MAX
SLOPE
T
MAX
T
MIN
SLOPE = T.C. =
=
=
V
MAX
– V
MIN
(T
MAX
– T
MIN
) ⴛ 5 ⴛ 10
–6
5.0027 – 5.0012
(70ⴗC – 0) ⴛ 5 ⴛ 10
–6
4.3ppm/ⴗC
Figure 9. Typical AD586L Temperature Drift
Each AD586J, K and L grade unit is tested at 0°C, 25°C, and
70°C. Each AD586SQ and TQ grade unit is tested at –55°C,
+25°C, and +125°C. This approach ensures that the variations
of output voltage that occur as the temperature changes within
the specified range will be contained within a box whose diago-
nal has a slope equal to the maximum specified drift. The
position of the box on the vertical scale will change from device
to device as initial error and the shape of the curve vary. The
maximum height of the box for the appropriate temperature
range and device grade is shown in Table I. Duplication of these
results requires a combination of high accuracy and stable tem-
perature control in a test system. Evaluation of the AD586 will
produce a curve similar to that in Figure 9, but output readings
may vary depending on the test methods and equipment utilized.
Table I. Maximum Output Change in mV
Device Maximum Output Change (mV)
Grade 0ⴗC to 70ⴗC –40ⴗC to +85ⴗC –55ⴗC to +125ⴗC
AD586J 8.75
AD586K 5.25
AD586L 1.75
AD586M 0.70
AD586A 9.37
AD586B 3.12
AD586S 18.00
AD586T 9.00
In some applications, a varying load may be both resistive and
capacitive in nature, or the load may be connected to the
AD586 by a long capacitive cable.
Figure 7 displays the output amplifier characteristics driving a
1000 pF, 0 to 10 mA load.
AD586 V
L
5V
0V
VOUT
500⍀
3.5V CL
1000pF
Figure 7a. Capacitive Load Transient Response Test Circuit
Figure 7b. Output Response with Capacitive Load
LOAD REGULATION
The AD586 has excellent load regulation characteristics. Figure
8 shows that varying the load several mA changes the output by
a few µV. The AD586 has somewhat better load regulation
performance sourcing current than sinking current.
–6–4–2
246810
LOAD (mA)
0
–500
–1000
500
1000
⌬V
OUT (␮V)
Figure 8. Typical Load Regulation Characteristics
TEMPERATURE PERFORMANCE
The AD586 is designed for precision reference applications
where temperature performance is critical. Extensive tempera-
ture testing ensures that the device’s high level of performance is
maintained over the operating temperature range.
Some confusion exists in the area of defining and specifying
reference voltage error over temperature. Historically, references
have been characterized using a maximum deviation per degree
AD586
REV. D –7–
NEGATIVE REFERENCE VOLTAGE FROM AN AD586
The AD586 can be used to provide a precision –5.000 V output
as shown in Figure 10. The V
IN
pin is tied to at least a 6 V sup-
ply, the output pin is grounded, and the AD586 ground pin is
connected through a resistor, R
S
, to a –15 V supply. The –5 V
output is now taken from the ground pin (Pin 4) instead of V
OUT.
It is essential to arrange the output load and the supply resistor
R
S
so that the net current through the AD586 is between 2.5 mA
and 10.0 mA. The temperature characteristics and long-term
stability of the device will be essentially the same as that of a
unit used in the standard 5 V output configuration.
AD586
GND
+6V ––
>
+30V
V
OUT
V
IN
2.5mA < –I
L
< 10mA
10V
R
S
–5V
I
L
R
S
–15V
Figure 10. AD586 as a Negative 5 V Reference
USING THE AD586 WITH CONVERTERS
The AD586 is an ideal reference for a wide variety of 8-, 12-,
14-, and 16-bit A/D and D/A converters. Several representative
examples follow.
5 V REFERENCE WITH MULTIPLYING CMOS D/A OR
A/D CONVERTERS
The AD586 is ideal for applications with 10- and 12-bit multi-
plying CMOS D/A converters. In the standard hookup, as
shown in Figure 11, the AD586 is paired with the AD7545
12-bit multiplying DAC and the AD711 high-speed BiFET Op
Amp. The amplifier DAC configuration produces a unipolar
0 V to –5 V output range. Bipolar output applications and
other operating details can be found on the individual prod-
uct data sheets.
AD586
GND
V
OUT
V
IN
AD711K
0.1␮F
–15V
0 TO
–
5V
0.1␮F
+15V
OUT1
AGND
DGND
DB11–DB0
C1
33pF
R2
68⍀
R
FB
15V
V
DD
AD7545K
V
REF
10k⍀
V
OUT
TRIM
15V
Figure 11. Low-Power 12-Bit CMOS DAC Application
The AD586 can also be used as a precision reference for mul-
tiple DACs. Figure 12 shows the AD586, the AD7628 dual
DAC and the AD712 dual op amp hooked up for single supply
operation to produce 0 V to –5 V outputs. Because both DACs
are on the same die and share a common reference and output
op amps, the DAC outputs will exhibit similar gain TCs.
VOUT B =
0 TO –5V
AD586
GND
VIN
AD712
15V
OUT A
DGND
VOUT
15V
AGND
DAC A
DB0
DB7
DATA
INPUTS
OUT B
DAC B
RFB B
RFB A
VREFA
VOUT A =
0 TO –5V
AD7628
VREFB
Figure 12. AD586 as a 5 V Reference for a CMOS Dual
DAC
STACKED PRECISION REFERENCES FOR MULTIPLE
VOLTAGES
Often, a design requires several reference voltages. Three
AD586s can be stacked, as shown in Figure 13, to produce
5.000 V, 10.000 V, and 15.000 V outputs. This scheme can be
extended to any number of AD586s as long as the maximum
load current is not exceeded. This design provides the addi-
tional advantage of improved line regulation on the 5.0 V
output. Changes in V
IN
of 18 V to 50 V produces an output
change that is below the noise level of the references.
22V TO 46V
AD586
GND
V
OUT
V
IN
TRIM 10k⍀
AD586
GND
V
OUT
V
IN
TRIM
AD586
GND
V
OUT
V
IN
TRIM
10k⍀
10k⍀
15.000V
10.000V
5.000V
Figure 13. Multiple AD586s Stacked for Precision 5 V,
10 V, and 15 V Outputs
AD586
REV. D
–8–
PRECISION CURRENT SOURCE
The design of the AD586 allows it to be easily configured as a
current source. By choosing the control resistor R
C
in Figure 14,
you can vary the load current from the quiescent current (2 mA
typically) to approximately 10 mA. The compliance voltage of
this circuit varies from about 5 V to 21 V depending upon the
value of V
IN
.
AD586
GND
V
OUT
V
IN
5V
R
C
I
L
= + I
BIAS
+V
IN
R
C
(500⍀ MIN)
Figure 14. Precision Current Source
PRECISION HIGH CURRENT SUPPLY
For higher currents, the AD586 can easily be connected to a
power PNP or power Darlington PNP device. The circuit in
Figure 15 can deliver up to 4 amps to the load. The 0.1 µF
capacitor is required only if the load has a significant capacitive
component. If the load is purely resistive, improved high-
frequency supply rejection results can be obtained by removing
the capacitor.
AD586
GND
V
OUT
VIN 5V
RC
IL = + IBIAS
RC
0.1␮F
15V
220⍀
2N6285
Figure 15a. Precision High-Current Current Source
AD586
GND
V
OUT
V
IN
0.1␮F
15V
220⍀
2N6285
V
OUT
5V @ 4 AMPS
Figure 15b. Precision High-Current Voltage Source
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm.)
Mini-DIP (N-8) Package
SEATING
PLANE
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.022 (0.558)
0.014 (0.356)
0.160 (4.06)
0.115 (2.93)
0.070 (1.77)
0.045 (1.15)
0.150
(3.81)
MIN
8
14
5
PIN 1
0.280 (7.11)
0.240 (6.10)
0.100 (2.54)
BSC
0.430 (10.92)
0.348 (8.84)
0.195
(4.95)
MAX
0.015 (0.381)
0.008 (0.204)
0.325 (8.25)
0.300 (7.62)
Cerdip (Q-8) Package
14
85
0.310 (7.87)
0.220 (5.59)
PIN 1
0.005 (0.13)
MIN
0.055 (1.35)
MAX
0.1 (2.54) BSC
15°
0°
0.32 (8.13)
0.29 (7.37)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.20 (5.08)
MAX
0.405 (10.29) MAX
0.15
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.35)
0.07 (1.78)
0.03 (0.76)
0.060 (1.52)
0.015 (0.38)
Small Outline (SO-8) Package
0.015 (0.38)
0.007 (0.18)
0.045 (1.15)
0.020 (0.50)
0.205 (5.20)
0.181 (4.60)
85
41
0.198 (5.00)
0.188 (4.75)
0.244 (6.20)
0.228 (5.80)
PIN 1
0.158 (4.00)
0.150 (3.80)
0.0500 (1.27)
TYP
0.069 (1.75)
0.053 (1.35)
SEATING
PLANE
0.010 (0.25)
0.004 (0.10)
0.018 (0.46)
0.014 (0.36)
AD586 Revision History
Location Page
Data Sheet changed from REV. C to REV. D.
Changed Figure 10 to Table I (Maximum Output Change in mV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PRINTED IN U.S.A. C00529b–0–4/01(D)