Semiconductor Components Industries, LLC, 2004
July, 2004 − Rev. 12 1Publication Order Number:
LP2950/D
LP2950, LP2951, NCV2951
100 mA, Low Power Low
Dropout Voltage Regulator
The LP2950 and LP2951 are micropower voltage regulators that are
specifically designed to maintain proper regulation with an extremely
low input−to−output voltage differential. These devices feature a very
low quiescent bias current of 75 A and are capable of supplying
output currents in excess of 100 mA. Internal current and thermal
limiting protection is provided.
The LP2951 has three additional features. The first is the Error
Output that can be used to signal external circuitry of an out of
regulation condition, or as a microprocessor power−on reset. The
second feature allows the output voltage to be preset to 5.0 V, 3.3 V or
3.0 V output (depending on the version) or programmed from 1.25 V
to 29 V. It consists of a pinned out resistor divider along with direct
access to the Error Amplifier feedback input. The third feature is a
Shutdown input that allows a logic level signal to turn−off or turn−on
the regulator output.
Due to the low input−to−output voltage differential and bias current
specifications, these devices are ideally suited for battery powered
computer , c onsumer, a nd industrial e quipment where a n extension o f
useful battery life is desirable. The LP2950 is available in the three
pin case 29 and DPAK packages, and the LP2951 is available in the
eight p in dual−in−line, SOIC−8 and Micro8 s urface mount p ackages.
The ‘A’ suffix devices feature an initial output voltage tolerance
±0.5%.
Features
•Pb−Free Packages are Available
•Low Quiescent Bias Current of 75 A
•Low Input−to−Output Voltage Differential of 50 mV at 100 A and
380 mV at 100 mA
•5.0 V, 3.3 V or 3.0 V ±0.5% Allows Use as a Regulator or Reference
•Extremely Tight Line and Load Regulation
•Requires Only a 1.0 F Output Capacitor for Stability
•Internal Current and Thermal Limiting
•NCV Prefix for Automotive and Other Applications Requiring Site
and Control Changes
LP2951 Additional Features
•Error Output Signals an Out of Regulation Condition
•Output Programmable from 1.25 V to 29 V
•Logic Level Shutdown Input
(See Following Page for Device Information.)
TO−92
Z SUFFIX
CASE 29
See detailed ordering and shipping information in the package
dimensions section on pages 14 and 15 of this data sheet.
See general marking information in the device marking
section on page 16 of this data sheet.
ORDERING & MARKING INFORMATION
PIN CONNECTIONS
23
1
Pin: 1. Output
2. Ground
3. Input
DPAK
DT SUFFIX
CASE 369C
Heatsink surface (shown as terminal 4 in
case outline drawing) is connected to Pin 2.
123
(Top View)
Pin: 1. Input
2. Ground
3. Output
81
81
81
PIN CONNECTIONS
18
7
6
5
2
3
4
(Top View)
Output
Sense
Shutdown
Input
Feedback
Error Output
VO Tap
GND
SOIC−8
D SUFFIX
CASE 751
PDIP−8
N SUFFIX
CASE 626
Micro8
DM SUFFIX
CASE 846A
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4
LP2950, LP2951, NCV2951
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DEVICE INFORMATION
Output Voltage
Operating Ambient
Package 3.0 V 3.3 V 5.0 V Adjustable
Operating
Ambient
Temperature Range
TO−92
Suffix Z LP2950CZ−3.0
LP2950ACZ−3.0 LP2950CZ−3.3
LP2950ACZ−3.3 LP2950CZ−5.0
LP2950ACZ−5.0 Not
Available TA = −40° to +125°C
DPAK
Suffix DT LP2950CDT−3.0
LP2950ACDT−3.0 LP2950CDT−3.3
LP2950ACDT−3.3 LP2950CDT−5.0
LP2950ACDT−5.0 Not
Available TA = −40° to +125°C
SOIC−8 − NCV2951ACD−3.3R2 NCV2951ACDR2 NCV2951CDR2 TA = −40° to +125°C
SOIC−8
Suffix D LP2951CD−3.0
LP2951ACD−3.0 LP2951CD−3.3
LP2951ACD−3.3 LP2951CD
LP2951ACD LP2951CD
LP2951ACD TA = −40° to +125°C
Micro8
Suffix DM LP2951CDM−3.0
LP2951ACDM−3.0 LP2951CDM−3.3
LP2951ACDM−3.3 LP2951CDM
LP2951ACDM LP2951CDM
LP2951ACDM TA = −40° to +125°C
DIP−8
Suffix N LP2951CN−3.0
LP2951ACN−3.0 LP2951CN−3.3
LP2951ACN−3.3 LP2951CN
LP2951ACN LP2951CN
LP2951ACN TA = −40° to +125°C
LP2950Cx−xx / LP2951Cxx−xx 1% Output Voltage Precision at TA = 25°C
LP2950ACx−xx / LP2951ACxx−xx 0.5% Output Voltage Precision at TA = 25°C
From
CMOS/TTL
3
Figure 1. Representative Block Diagrams
This device contains 34 active transistors.
LP2950CZ−5.0
Battery or
Unregulated DC
GND 2
Output 5.0 V/100 mA
1
Input
3
1.23 V
Reference
Error Amplifier
182 k
60 k
1.0 F
GND 4
182 k
60 k
1.23 V
Reference
1.0 F
LP2951CD or CN
Error
Amplifier
Battery or
Unregulated DC
Shutdown
Error
Output
5
VO Tap
Feedback
6
7
Input 8 Output 1Sense 2 5.0 V/100 mA
330 k
To CMOS/TTL
75 mV/
60 mV
Error Detection
Comparator
50 k
60 k
LP2950, LP2951, NCV2951
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MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Rating Symbol Value Unit
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Input Voltage
ÁÁÁÁ
ÁÁÁÁ
VCC
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
30
ÁÁÁ
ÁÁÁ
Vdc
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Power Dissipation and Thermal Characteristics
ÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁ
Maximum Power Dissipation PDInternally Limited W
Case 751(SOIC−8) D Suffix
Thermal Resistance, Junction−to−Ambient RJA 180 °C/W
Thermal Resistance, Junction−to−Case RJC 45 °C/W
Case 369A (DPAK) DT Suffix (Note 1)
Thermal Resistance, Junction−to−Ambient RJA 92 °C/W
Thermal Resistance, Junction−to−Case RJC 6.0 °C/W
Case 29 (TO−226AA/TO−92) Z Suffix
Thermal Resistance, Junction−to−Ambient RJA 160 °C/W
Thermal Resistance, Junction−to−Case RJC 83 °C/W
Case 626 N Suffix
Thermal Resistance, Junction−to−Ambient RJA 105 °C/W
Case 846A (Micro8) DM Suffix
Thermal Resistance, Junction−to−Ambient RJA 240 °C/W
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Feedback Input Voltage
ÁÁÁÁ
ÁÁÁÁ
Vfb
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
−1.5 to +30
ÁÁÁ
ÁÁÁ
Vdc
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Shutdown Input Voltage
ÁÁÁÁ
ÁÁÁÁ
Vsd
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
−0.3 to +30
ÁÁÁ
ÁÁÁ
Vdc
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Error Comparator Output Voltage
ÁÁÁÁ
ÁÁÁÁ
Verr
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
−0.3 to +30
ÁÁÁ
ÁÁÁ
Vdc
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Operating Ambient Temperature Range
ÁÁÁÁ
ÁÁÁÁ
TA
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
−40 to +125
ÁÁÁ
ÁÁÁ
°C
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Maximum Die Junction Temperature Range
ÁÁÁÁ
ÁÁÁÁ
TJ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
+150
ÁÁÁ
ÁÁÁ
°C
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Storage Temperature Range
ÁÁÁÁ
ÁÁÁÁ
Tstg
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
−65 to +150
ÁÁÁ
ÁÁÁ
°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
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ELECTRICAL CHARACTERISTICS (Vin = VO + 1.0 V, IO = 100 A, CO = 1. 0 F, TA = 25°C [Note 3],
unless otherwise noted.) Characteristic Symbol Min Typ Max Unit
Output Voltage, 5.0 V Versions VOV
Vin = 6.0 V, IO = 100 A, TA = 25°C
LP2950C−5.0/LP2951C/NCV2951C* 4.950 5.000 5.050
LP2950AC−5.0/LP2951AC/NCV2951AC* 4.975 5.000 5.025
TA = −40 to +125°C
LP2950C−5.0/LP2951C/NCV2951C* 4.900 − 5.100
LP2950AC−5.0/LP2951AC/NCV2951AC* 4.940 − 5.060
Vin = 6.0 to 30 V, IO = 100 A to 100 mA, TA = −40 to +125°C
LP2950C−5.0/LP2951C/NCV2951C* 4.880 − 5.120
LP2950AC−5.0/LP2951AC/NCV2951AC* 4.925 − 5.075
Output Voltage, 3.3 V Versions VOV
Vin = 4.3 V, IO = 100 A, TA = 25°C
LP2950C−3.3/LP2951C−3.3 3.267 3.300 3.333
LP2950AC−3.3/LP2951AC−3.3/NCV2951AC−3.3* 3.284 3.300 3.317
TA = −40 to +125°C
LP2950C−3.3/LP2951C−3.3 3.234 − 3.366
LP2950AC−3.3/LP2951AC−3.3/NCV2951AC−3.3* 3.260 − 3.340
Vin = 4.3 to 30 V, IO = 100 A to 100 mA, TA = −40 to +125°C
LP2950C−3.3/LP2951C−3.3 3.221 − 3.379
LP2950AC−3.3/LP2951AC−3.3/NCV2951AC−3.3* 3.254 − 3.346
Output Voltage, 3.0 V Versions VOV
Vin = 4.0 V, IO = 100 A, TA = 25°C
LP2950C−3.0/LP2951C−3.0 2.970 3.000 3.030
LP2950AC−3.0/LP2951AC−3.0 2.985 3.000 3.015
TA = −40 to +125°C
LP2950C−3.0/LP2951C−3.0 2.940 − 3.060
LP2950AC−3.0/LP2951AC−3.0 2.964 − 3.036
Vin = 4.0 to 30 V, IO = 100 A to 100 mA, TA = −40 to +125°C
LP2950C−3.0/LP2951C−3.0 2.928 − 3.072
LP2950AC−3.0/LP2951AC−3.0 2.958 − 3.042
1. The Junction−to−Ambient Thermal Resistance is determined by PCB copper area per Figure 27.
2. ESD data available upon request.
3. Low duty pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
4. VO(nom) is the part number voltage option.
5. Noise tests on the LP2951 are made with a 0.01 F capacitor connected across Pins 7 and 1.
*NCV prefix is for automotive and other applications requiring site and change control.
LP2950, LP2951, NCV2951
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5
ELECTRICAL CHARACTERISTICS (continued) (Vin = VO + 1.0 V, IO = 10 0 A, CO = 1.0 F, TA = 25°C [Note 8] ,
unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Line Regulation (Vin = VO(nom) +1.0 V to 30 V) (Note 9) Regline %
LP2950C−XX/LP2951C/LP2951C−XX/NCV2951C* − 0.08 0.20
LP2950AC−XX/LP2951AC/LP2951AC−XX/NCV2951AC* − 0.04 0.10
Load Regulation (IO = 100 A to 100 mA) Regload %
LP2950C−XX/LP2951C/LP2951C−XX/NCV2951C* − 0.13 0.20
LP2950AC−XX/LP2951AC/LP2951AC−XX/NCV2951AC* − 0.05 0.10
Dropout Voltage VI − VOmV
IO = 100 A − 30 80
IO = 100 mA − 350 450
Supply Bias Current ICC
IO = 100 A − 93 120 A
IO = 100 mA − 4.0 12 mA
Dropout Supply Bias Current (Vin = VO(nom) − 0.5 V,
IO = 100 A) (Note 9) ICCdropout −110 170 A
Current Limit (VO Shorted to Ground) ILimit − 220 300 mA
Thermal Regulation Regthermal − 0.05 0.20 %/W
Output Noise Voltage (10 Hz to 100 kHz) (Note 10) VnVrms
CL = 1.0 F − 126 −
CL = 100 F − 56 −
LP2951A/LP2951AC Only
Reference Voltage (TA = 25°C) Vref V
LP2951C/LP2951C−XX/NCV2951C* 1.210 1.235 1.260
LP2951AC/LP2951AC−XX/NCV2951AC* 1.220 1.235 1.250
Reference Voltage (TA = −40 to +125°C) Vref V
LP2951C/LP2951C−XX/NCV2951C* 1.200 − 1.270
LP2951AC/LP2951AC−XX/NCV2951AC* 1.200 − 1.260
Reference Voltage (TA = −40 to +125°C) Vref V
IO = 100 A to 100 mA, Vin = 23 to 30 V
LP2951C/LP2951C−XX/NCV2951C* 1.185 − 1.285
LP2951AC/LP2951AC−XX/NCV2951AC* 1.190 − 1.270
Feedback Pin Bias Current IFB − 15 40 nA
Error Comparator
Output Leakage Current (VOH = 30 V) Ilkg − 0.01 1.0 A
Output Low Voltage (Vin = 4.5 V, IOL = 400 A) VOL − 150 250 mV
Upper Threshold Voltage (Vin = 6.0 V) Vthu 40 45 − mV
Lower Threshold Voltage (Vin = 6.0 V) Vthl − 60 95 mV
Hysteresis (Vin = 6.0 V) Vhy − 15 − mV
Shutdown Input
Input Logic Voltage Vshtdn V
Logic “0” (Regulator “On”) 0 − 0.7
Logic “1” (Regulator “Off”) 2.0 − 30
Shutdown Pin Input Current Ishtdn A
Vshtdn = 2.4 V − 35 50
Vshtdn = 30 V − 450 600
Regulator Output Current in Shutdown Mode Ioff − 3.0 10 A
(Vin = 30 V, Vshtdn = 2.0 V, VO = 0, Pin 6 Connected to Pin 7)
6. The Junction−to−Ambient Thermal Resistance is determined by PCB copper area per Figure 27.
7. ESD data available upon request.
8. Low duty pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
9. VO(nom) is the part number voltage option.
10.Noise tests on the LP2951 are made with a 0.01 F capacitor connected across Pins 7 and 1.
*NCV prefix is for automotive and other applications requiring site and change control.
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DEFINITIONS
Dropout Voltage − The input/output voltage differential
at which the regulator output no longer maintains regulation
against further reductions in input voltage. Measured when
the output drops 100 mV below its nominal value (which is
measured at 1.0 V differential), dropout voltage is affected
by junction temperature, load current and minimum input
supply requirements.
Line Regulation − The change in output voltage for a
change in input voltage. The measurement is made under
conditions of low dissipation or by using pulse techniques
such that average chip temperature is not significantly
affected.
Load Regulation − The change in output voltage for a
change in load current at constant chip temperature.
Maximum Power Dissipation − The maximum total
device dissipation for which the regulator will operate
within specifications.
Bias Current − Current which is used to operate the
regulator chip and is not delivered to the load.
Output Noise Voltage − The RMS ac voltage at the
output, with constant load and no input ripple, measured
over a specified frequency range.
Leakage Current − Current drawn through a bipolar
transistor collector−base junction, under a specified
collector voltage, when the transistor is “off”.
Upper Threshold Voltage − Voltage applied to the
comparator input terminal, below the reference voltage
which is applied to the other comparator input terminal,
which causes the comparator output to change state from a
logic “0” to “1”.
Lower Threshold Voltage − Voltage applied to the
comparator input terminal, below the reference voltage
which is applied to the other comparator input terminal,
which causes the comparator output to change state from a
logic “1” to “0”.
Hysteresis − The difference between Lower Threshold
voltage and Upper Threshold voltage.
Figure 2. Quiescent Current
, OUTPUT VOLTAGE (V)
Vout
, OUTPUT VOLTAGE (V)
Vout
−50
5.00
0
6.0
0
250
0.1
10
TA, AMBIENT TEMPERATURE (°C)
Vin, INPUT VOLTAGE (V)
BIAS CURRENT ( A)µ
Vin, INPUT VOLTAGE (V)
LP2950/LP2951 BIAS CURRENT (mA)
IL, LOAD CURRENT (mA)
Figure 3. Dropout Characteristics
Figure 4. Input Current Figure 5. Output Voltage versus Temperature
1.0 10 100 1.0 2.0 3.0 4.0 5.0 6.0
5.0 10 15 20 25 0 50 100 150
1.0
0.1
0.01
5.0
4.0
3.0
2.0
1.0
0
4.99
4.98
4.97
4.96
4.95
200
150
100
50
0
RL = 50 k
RL = 50
0.1 mA Load Current
No Load
LP2951C
TA = 25°C
LP2951C
200
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RL
DROPOUT VOLTAGE (mV) = 50
T, TEMPERATURE (°C)
0
200
0
8.0
−50
550
−100
7.0
4.70
5.0
0.1
400
LOAD CURRENT (mA)
t, TIME (ms)
, INPUT VOLTAGE (V)
t, TIME (s)
SHUTDOWN AND OUTPUT VOLTAGE (V)
t, TIME (s)
, OUTPUT VOLTAGE (V)
Vin, INPUT VOLTAGE (V)
DROPOUT VOLTAGE (mV)
Figure 6. Dropout Voltage versus Output Current
IO, OUTPUT CURRENT (mA)
Figure 7. Dropout Voltage versus Temperature
Figure 8. Error Comparator Output Figure 9. Line Transient Response
Figure 10. LP2951 Enable Transient Figure 11. Load Transient Response
1.0 10 100 0 50 100 150
4.74 4.78 4.82 4.86 100 200 3004.90 400 500 600 700 800
0 100 200 300 400 42.50.5 1.5 2 3 3.51
300
200
0
500
450
400
300
7.5
7.0
6.5
6.0
5.5
4.0
3.0
1.0
0
5.0
3.0
1.0
−1.0
150
100
0
−50
50
RL = 50
Vin Decreasing
Vin Increasing
Vin
Vout
RL = 50 k
TA = 25°C
CL = 1.0 F
IL = 1.0 mA
VO = 5.0 V
Vout
ILoad
TA = 25°C
IL = 10 mA
Vin = 8.0 V
Vout = 5.0 V
CL = 10 F
Shutdown Input
350
RL
DROPOUT VOLTAGE (mV) = 50 k
55
50
45
40
30
35
350
250
150
100
2.0
OUTPUT VOLTAGE CHANGE (mV)
4.0
2.0
0
−2.0
−6.0
−4.0
OUTPUT VOLTAGE CHANGE
(
mV
)
0
−200
200
400
−400
6.0
4.0
2.0
0
50
Vin
Vout
CL = 1.0 F
TA = 25°C
LP2951C
RL = 330 k
TA = 25°C
CL = 1.0 F
Vout = 5.0 V
IL = 400 A to 75 mA
TA = 25°C
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8
0
100
100
4.0
−40
1.8
1.0
80
V
out, OUTPUT CURRENT (mA)
Vin, INPUT VOLTAGE (V)
VOLTAGE NOISE ( V/ Hz)√
f, FREQUENCY (Hz)
SHUTDOWN THRESHOLD VOLTAGE (V)
t, TEMPERATURE (°C)
RIPPLE REJECTION (dB)
Figure 12. Ripple Rejection
f, FREQUENCY (Hz)
Figure 13. Output Noise
Figure 14. Shutdown Threshold Voltage
versus Temperature Figure 15. Maximum Rated
Output Current
TA = 25°C
CL = 1.0 F
Vin = 6.0 V
Vout = 5.0 V
CL = 1.0 F
µ
CL = 100 F
IL= 0.1 mA
IL= 100 mA
TA = 25°C
VO = 5.0 V
LP2951C
Output Off"
Output On"
TA = 25°C
LP2951CN
60
40
20
0
3.0
2.0
1.0
0
80
60
40
20
0
1.4
1.0
0.8
1.2
1.6
10 100 1.0 k 10 k 100 k 1.0 k 10 k 100 k
−20 40 80 120 160 5.0 15 25 35 4010 20 3060 100 140200
TA = 75°C
4.0
2.0
0
−2.0
−4.0
−6.0
OUTPUT VOLTAGE CHANGE
(
mV
)
LP2950, LP2951, NCV2951
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APPLICATIONS INFORMATION
Introduction
The LP2950/LP2951 regulators are designed with
internal current limiting and thermal shutdown making them
user−friendly. Typical application circuits for the LP2950
and LP2951 are shown in Figures 18 through 26.
These regulators are not internally compensated and thus
require a 1.0 F (or greater) capacitance between the
LP2950/LP2951 output terminal and ground for stability.
Most types of aluminum, tantalum or multilayer ceramic
will perform adequately. Solid tantalums or appropriate
multilayer ceramic capacitors are recommended for
operation below 25°C.
At lower values of output current, less output capacitance
is required for output stability. The capacitor can be reduced
to 0.33 F for currents less than 10 mA, or 0.1 F for currents
below 1.0 mA. Using the 8 pin versions at voltages less than
5.0 V operates the error amplifier at lower values of gain, so
that more output capacitance is needed for stability. For the
worst case operating condition of a 100 mA load at 1.23 V
output (output Pin 1 connected to the feedback Pin 7) a
minimum capacitance of 3.3 F is recommended.
The LP2950 will remain stable and in regulation when
operated with no output load. When setting the output
voltage of the LP2951 with external resistors, the resistance
values should be chosen to draw a minimum of 1.0 A.
A bypass capacitor is recommended across the
LP2950/LP2951 input to ground if more than 4 inches of
wire connects the input to either a battery or power supply
filter capacitor.
Input capacitance at the LP2951 Feedback Pin 7 can
create a pole, causing instability if high value external
resistors are used to set the output voltage. Adding a 100 pF
capacitor between the Output Pin 1 and the Feedback Pin 7
and increasing the output filter capacitor to at least 3.3 F
will stabilize the feedback loop.
Error Detection Comparator
The comparator switches to a positive logic low whenever
the LP2951 output voltage falls more than approximately
5.0% out of regulation. This value is the comparator’s
designed−in o ffset voltage of 60 mV divided by the 1.235 V
internal reference. As shown in the representative block
diagram. This trip level remains 5.0% below normal
regardless of the value of regulated output voltage. For
example, the error flag trip level is 4.75 V for a normal 5.0 V
regulated output, or 9.50 V for a 10 V output voltage.
Figure 2 is a timing diagram which shows the ERROR
signal and the regulated output voltage as the input voltage
to the LP2951 is ramped up and down. The ERROR signal
becomes valid (low) at about 1.3 V input. It goes high when
the input reaches about 5.0 V (Vout exceeds about 4.75 V).
Since the LP2951’s dropout voltage is dependent upon the
load current (refer to the curve in the Typical Performance
Characteristics), the input voltage trip point will vary with
load current. The output voltage trip point does not vary
with load.
The error comparator output is an open collector which
requires an external pullup resistor. This resistor may be
returned to the output or some other voltage within the
system. The resistance value should be chosen to be
consistent with the 400 A sink capability of the error
comparator. A value between 100 k and 1.0 M is
suggested. No pullup resistance is required if this output is
unused.
When operated in the shutdown mode, the error
comparator output will go high if it has been pulled up to an
external supply. To avoid this invalid response, the error
comparator output should be pulled up to Vout (see
Figure 16).
Figure 16. ERROR Output Timing
5.0 V
4.75 V 4.70 V
4.75 V + Vdropout 4.70 V + Vdropout
1.3 V 1.3 V
Not
Valid Pullup
to Vout
Pullup
to Ext
Output
Voltage
ERROR
Input
Voltage
Not
Valid
Programming the Output Voltage (LP2951)
The LP2951CX may be pin−strapped for the nominal
fixed output voltage using its internal voltage divider by
tying Pin 1 (output) to Pin 2 (sense) and Pin 7 (feedback) to
Pin 6 (5.0 V tap). Alternatively, it may be programmed for
any output voltage between its 1.235 reference voltage and
its 30 V maximum rating. An external pair of resistors is
required, as shown in Figure 17.
LP2950, LP2951, NCV2951
http://onsemi.com
10
Figure 17. Adjustable Regulator
Error
Output
Shutdown
Input
Vin
Vout
1.23 to 30
V
3.3 F
0.01 F
NC
NC
R2
R1
100 k
5
3
Error
SD
GND FB
47
6
VO T
SNS 2
Vout
Vin
8
1
The complete equation for the output voltage is:
Vout Vref (1R1R2)IFB R1
where Vref is the nominal 1.235 V reference voltage and IFB
is the feedback pin bias current, nominally − 20 nA. The
minimum recommended load current of 1.0 A forces an
upper limit of 1.2 M on the value of R2, if the regulator
must work with no load. IFB will produce a 2% typical error
in Vout which may be eliminated at room temperature by
adjusting R1. For better accuracy, choosing R2 = 100 k
reduces this error to 0.17% while increasing the resistor
program current to 12 A. Since the LP2951 typically draws
75 A at no load with Pin 2 open circuited, the extra 12 A
of current drawn is often a worthwhile tradeoff for
eliminating the need to set output voltage in test.
Output Noise
In many applications it is desirable to reduce the noise
present at the output. Reducing the regulator bandwidth by
increasing the size of the output capacitor is the only method
for reducing noise on the 3 lead LP2950. However,
increasing the capacitor from 1.0 F to 220 F only
decreases the noise from 430 V to 160 V rms for a 100 kHz
bandwidth at the 5.0 V output.
Noise can be reduced fourfold by a bypass capacitor
across R1, since it reduces the high frequency gain from 4
to unity. Pick
CBypass 1
2R1 x 200 Hz
or about 0.01 F. When doing this, the output capacitor must
be increased to 3.3 F to maintain stability. These changes
reduce the output noise from 430 V to 126 Vrms for a
100 kHz bandwidth at 5.0 V output. With bypass
capacitor added, noise no longer scales with output voltage
so that improvements are more dramatic at higher output
voltages.
Figure 18. 1.0 A Regulator with 1.2 V Dropout
0.01 F
10 k MTB23P06E
1.0 F
Unregulated
Input
Error
Output
Shutdown
Input
Vout
5.0 V ±1.0%
0 to 1.0 A
220 F
2.0 k
5
3
Error
SD
GND FB
47
6
VO T
SNS 2
Vout
Vin
8
1
0.002 F
1.0 M
LP2951CN
LP2950, LP2951, NCV2951
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11
TYPICAL APPLICATIONS
Figure 19. Lithium Ion Battery Cell Charger
1N4001
GND
4.2 V ±0.025 V
NC
NC
50 k
5
3
Error
SD
GND FB
47
6
VO T
SNS 2
Vout
Vin
8
1
0.1 F
NC
LP2951CN
2.2 F
330 pF
806 k
1.0%
2.0 M
1.0%
Lithium Ion
Rechargeable
Cell
Unregulated Input
6.0 to 10 Vdc
Figure 20. Low Drift Current Sink
Error
Output
Shutdown
Input
+V = 2.0 to 30 V
1.0 F
R
5
3
Error
SD
GND FB
47
6
VO T
SNS 2
Vout
Vin
8
1
0.1 F
Load IL = 1.23/R
IL
Figure 21. Latch Off When Error Flag Occurs
Reset
+Vin
Vout
1.0 F
NC
NC
R2
R1
470 k
5
3
Error
SD
GND FB
47
6
VO T
SNS 2
Vout
Vin
8
1
LP2951CN
470 k
Error flag occurs when Vin is too
low to maintain Vout, or if Vout is re-
duced by excessive load current.
Normally
Closed
2N3906
Figure 22. 5.0 V Regulator with 2.5 V Sleep Function
*Sleep
Input
+Vin
Vout
3.3 F
NC
NC
100 k
100 k
470 k
5
3
Error
SD
GND FB
47
6
VO T
SNS 2
Vout
Vin
8
1
LP2951CN 200 k
100 pF
2N3906
47 k
CMOS
Gate
Error
Output
Shutdown
Input
LP2951CN
LP2950, LP2951, NCV2951
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12
330 k
Figure 23. Regulator with Early Warning and Auxiliary Output
+Vin
Memory
V+
1.0 F20
5
3
Error
SD
GND FB
47
6
VO T
SNS 2
Vout
Vin
8
1
LP2951CN
#1
1.0 F
5
3
Error
SD
GND FB
47
6
VO T
SNS 2
Vout
Vin
8
1
LP2951CN
#2
NC
Reset
VDD
P
Early Warning All diodes are 1N4148.
Early Warning flag on low input voltage.
Main output latches off at lower input voltages.
Battery backup on auxiliary output.
Operation: Regulator #1’s Vout is programmed one
diode drop above 5.0 V. Its error flag becomes active
when Vin < 5.7 V. When Vin drops below 5.3 V, the
error flag of regulator #2 becomes active and via Q1
latches the main output “off”. When Vin again exceeds
5.7 V, regulator #1 is back in regulation and the early
warning signal rises, unlatching regulator #2 via D3.
D4
2.7 M
Q1
2N3906
D2
D1
D3
27 k
3.6 V
NiCad
Main
Output
Figure 24. 2.0 A Low Dropout Regulator
+Vin
Vout @ 2.0 A
100 F
NC
NC
R2
R1
470
5
3
Error
SD
GND FB
47
6
VO T
SNS 2
Vout
Vin
8
1
LP2951CN
MJE2955
4.7 M
Error
Flag
Vout = 1.25V (1.0 + R1/R2)
For 5.0 V output, use internal resistors. Wire Pin 6 to 7,
and wire Pin 2 to +Vout Bus.
20 k
47
4.7 F
Tant
0.05
680
0.033 F
2N3906
10 k
Current Limit
Section
220
1000 F
.33 F
.01 F
2N3906
LP2950, LP2951, NCV2951
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13
Figure 25. Open Circuit Detector for 4.0 to 20 mA Current Loop
5
3
Error
SD
Gnd FB
47
6
VO T
SNS 2
Vout
Vin
8
1
LP2951CN
NC
Output*
0.1 F
NC
NC
NC
1N457
1N457 360
1N457
1N4001
24
+ 5.0 V
4.7 k
15
20 mA
4
* High for
IL < 3.5 mA
Figure 26. Low Battery Disconnect
2N3906
5
3
Error
SD
Gnd FB
47
6
VO T
SNS 2
Vout
Vin
8
1
LP2951CN
NC
1.0 F
NC
2
3
1
20
Main V+
Memory V+
6.0 V Lead−Acid
Battery
NiCad Backup
Battery
100 k
31.6 k
MC34164P−5
NC
R , THERMAL RESISTANCE
JAθ
JUNCTION-TO-AIR ( C/W)°
40
50
60
70
80
90
100
0
0.4
0.8
1.2
1.6
2.0
2.4
010203025155.0
L, LENGTH OF COPPER (mm)
PD(max) for TA = 50°C
Minimum
Size Pad
PD
L
L
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
, MAXIMUM POWER DISSIPATION (W)
Free Air
Mounted
Vertically
RJA
2.0 oz. Copper
Figure 27. DPAK Thermal Resistance and Maximum
Power Dissipation versus PCB Copper Length
LP2950, LP2951, NCV2951
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14
ORDERING INFORMATION (LP2950)
Part Number Output Voltage
(Volts) Tolerance (%) Package Shipping†
LP2950CZ−3.0 3.0 1.0 TO−92 2000 Units / Bag
LP2950CZ−3.0RA 3.0 1.0 TO−92 2000 Units / Tape & Reel
LP2950ACZ−3.0 3.0 0.5 TO−92 2000 Units / Bag
LP2950ACZ−3.0RA 3.0 0.5 TO−92 2000 Units / Tape & Reel
LP2950CZ−3.3 3.3 1.0 TO−92 2000 Units / Bag
LP2950CZ−3.3RA 3.3 1.0 TO−92 2000 Units / Tape & Reel
LP2950ACZ−3.3 3.3 0.5 TO−92 2000 Units / Bag
LP2950ACZ−3.3RA 3.3 0.5 TO−92 2000 Units / Tape & Reel
LP2950CZ−5.0 5.0 1.0 TO−92 2000 Units / Bag
LP2950CZ−5.0G 5.0 1.0 TO−92
(Pb−Free) 2000 Units / Bag
LP2950CZ−5.0RA 5.0 1.0 TO−92 2000 Units / Tape & Reel
LP2950CZ−5.0RP 5.0 1.0 TO−92 2000 Units / Ammo Pack
LP2950ACZ−5.0 5.0 0.5 TO−92 2000 Units / Bag
LP2950ACZ−5.0RA 5.0 0.5 TO−92 2000 Units / Tape & Reel
LP2950CDT−3.0 3.0 1.0 DPAK 75 Units / Rail
LP2950CDT−3.0RK 3.0 1.0 DPAK 2500 Units / Tape & Reel
LP2950ACDT−3.0 3.0 0.5 DPAK 75 Units / Rail
LP2950ACDT−3.0G 3.0 0.5 DPAK
(Pb−Free) 75 Units / Rail
LP2950ACDT−3.0RK 3.0 0.5 DPAK 2500 Units / Tape & Reel
LP2950CDT−3.3 3.3 1.0 DPAK 75 Units / Rail
LP2950CDT−3.3RK 3.3 1.0 DPAK 2500 Units / Tape & Reel
LP2950ACDT−3.3 3.3 0.5 DPAK 75 Units / Rail
LP2950ACDT−3.3RG 3.3 0.5 DPAK
(Pb−Free) 75 Units / Rail
LP2950ACDT−3.3RK 3.3 0.5 DPAK 2500 Units / Tape & Reel
LP2950CDT−5.0 5.0 1.0 DPAK 75 Units / Rail
LP2950CDT−5.0RK 5.0 1.0 DPAK 2500 Units / Tape & Reel
LP2950ACDT−5.0 5.0 0.5 DPAK 75 Units / Rail
LP2950ACDT−5.0RK 5.0 0.5 DPAK 2500 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
LP2950, LP2951, NCV2951
http://onsemi.com
15
ORDERING INFORMATION (LP2951)
Part Number Output Voltage
(Volts) Tolerance (%) Package Shipping†
LP2951CD−3.0 3.0 1.0 SOIC−8 98 Units / Rail
LP2951CD−3.0R2 3.0 1.0 SOIC−8 2500 Units / Tape & Reel
LP2951CD−3.0R2G 3.0 1.0 SOIC−8
(Pb−Free) 2500 Units / Tape & Reel
LP2951ACD−3.0 3.0 0.5 SOIC−8 98 Units / Rail
LP2951ACD−3.0G 3.0 0.5 SOIC−8
(Pb−Free) 98 Units / Rail
LP2951ACD−3.0R2 3.0 0.5 SOIC−8 2500 Units / Tape & Reel
LP2951CD−3.3 3.3 1.0 SOIC−8 98 Units / Rail
LP2951CD−3.3R2 3.3 1.0 SOIC−8 2500 Units / Tape & Reel
LP2951CD−3.3R2G 3.3 1.0 SOIC−8
(Pb−Free) 2500 Units / Tape & Reel
LP2951ACD−3.3 3.3 0.5 SOIC−8 98 Units / Rail
LP2951ACD−3.3R2 3.3 0.5 SOIC−8 2500 Units / Tape & Reel
LP2951CD 5.0 or Adj. 1.0 SOIC−8 98 Units / Rail
LP2951CDR2 5.0 or Adj. 1.0 SOIC−8 2500 Units / Tape & Reel
LP2951CDR2G 5.0 or Adj. 1.0 SOIC−8
(Pb−Free) 2500 Units / Tape & Reel
LP2951ACD 5.0 or Adj. 0.5 SOIC−8 98 Units / Rail
LP2951ACDR2 5.0 or Adj. 0.5 SOIC−8 2500 Units / Tape & Reel
LP2951ACDR2G 5.0 or Adj. 0.5 SOIC−8
(Pb−Free) 2500 Units / Tape & Reel
LP2951CDM−3.0R2 3.0 1.0 Micro8 4000 Units / Tape & Reel
LP2951ACDM−3.0R2 3.0 0.5 Micro8 4000 Units / Tape & Reel
LP2951CDM−3.3R2 3.3 1.0 Micro8 4000 Units / Tape & Reel
LP2951ACDM−3.3RG 3.3 0.5 Micro8
(Pb−Free) 4000 Units / Tape & Reel
LP2951ACDM−3.3R2 3.3 0.5 Micro8 4000 Units / Tape & Reel
LP2951CDMR2 5.0 or Adj. 1.0 Micro8 4000 Units / Tape & Reel
LP2951ACDMR2 5.0 or Adj. 0.5 Micro8 4000 Units / Tape & Reel
LP2951CN−3.0 3.0 1.0 DIP−8 50 Units / Rail
LP2951ACN−3.0 3.0 0.5 DIP−8 50 Units / Rail
LP2951CN−3.3 3.3 1.0 DIP−8 50 Units / Rail
LP2951ACN−3.3 3.3 0.5 DIP−8 50 Units / Rail
LP2951CN 5.0 or Adj. 1.0 DIP−8 50 Units / Rail
LP2951ACN 5.0 or Adj. 0.5 DIP−8 50 Units / Rail
NCV2951ACD−3.3R2* 3.3 0.5 SOIC−8 2500 Units / Tape & Reel
NCV2951ACDR2* 5.0 or Adj. 0.5 SOIC−8 2500 Units / Tape & Reel
NCV2951CDR2* 5.0 or Adj. 1.0 SOIC−8 2500 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV prefix is for automotive and other applications requiring site and control changes.
LP2950, LP2951, NCV2951
http://onsemi.com
16
xx = 3.0, 3.3, or 5.0
y = 3 or 5
yy = 30, 33, or 50
z = A or C
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
MARKING DIAGRAMS
2950
CZ−xx
ALYWW
TO−92
Z SUFFIX
CASE 029
*
*This marking diagram also applies to NCV2951.
*
50−y
ALYWW
2950A
CZ−xx
ALYWW 50A−y
ALYWW
50−yy
ALYWW
DPAK
DT SUFFIX
CASE 369C
50Ayy
ALYWW
SOIC−8
D SUFFIX
CASE 751
Micro8
DM SUFFIX
CASE 846A
PAxx
AYW
51z
ALYW
1
8
51z−3
ALYW
1
8
51z−33
ALYW
1
8
P−xx
AYW
51CN
AWL
YYWW
51ACN
AWL
YYWW
51CN−3.0
AWL
YYWW
51ACN−xx
AWL
YYWW 1
8
1
8
PDIP−8
N SUFFIX
CASE 846A
1
8
1
8
1
8
1
8
LP2950, LP2951, NCV2951
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17
PACKAGE DIMENSIONS
TO−226AA/TO−92
Z SUFFIX
PLASTIC PACKAGE
CASE 29−11
ISSUE AL
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. CONTOUR OF PACKAGE BEYOND DIMENSION R
IS UNCONTROLLED.
4. LEAD DIMENSION IS UNCONTROLLED IN P AND
BEYOND DIMENSION K MINIMUM.
R
A
P
J
L
B
K
G
H
SECTION X−X
C
V
D
N
N
XX
SEATING
PLANE DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.175 0.205 4.45 5.20
B0.170 0.210 4.32 5.33
C0.125 0.165 3.18 4.19
D0.016 0.021 0.407 0.533
G0.045 0.055 1.15 1.39
H0.095 0.105 2.42 2.66
J0.015 0.020 0.39 0.50
K0.500 −−− 12.70 −−−
L0.250 −−− 6.35 −−−
N0.080 0.105 2.04 2.66
P−−− 0.100 −−− 2.54
R0.115 −−− 2.93 −−−
V0.135 −−− 3.43 −−−
1
LP2950, LP2951, NCV2951
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18
PACKAGE DIMENSIONS
DPAK
DT SUFFIX
PLASTIC PACKAGE
CASE 369C−0
ISSUE O
5.80
0.228
2.58
0.101
1.6
0.063
6.20
0.244 3.0
0.118
6.172
0.243
mm
inches
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details please download the ON Semiconductor Soldering and
Mozunting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
D
A
K
B
R
V
S
FL
G
2 PL
M
0.13 (0.005) T
E
C
U
J
H
−T− SEATING
PLANE
Z
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.235 0.245 5.97 6.22
B0.250 0.265 6.35 6.73
C0.086 0.094 2.19 2.38
D0.027 0.035 0.69 0.88
E0.018 0.023 0.46 0.58
F0.037 0.045 0.94 1.14
G0.180 BSC 4.58 BSC
H0.034 0.040 0.87 1.01
J0.018 0.023 0.46 0.58
K0.102 0.114 2.60 2.89
L0.090 BSC 2.29 BSC
R0.180 0.215 4.57 5.45
S0.025 0.040 0.63 1.01
U0.020 −−− 0.51 −−−
V0.035 0.050 0.89 1.27
Z0.155 −−− 3.93 −−−
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
123
4
LP2950, LP2951, NCV2951
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19
PACKAGE DIMENSIONS
SOIC−8
D SUFFIX
PLASTIC PACKAGE
CASE 751−07
ISSUE AB
SEATING
PLANE
1
4
58
N
J
X 45
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDAARD IS 751−07
A
BS
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) Z SXS
M
1.52
0.060
7.0
0.275
0.6
0.024 1.270
0.050
4.0
0.155
mm
inches
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
LP2950, LP2951, NCV2951
http://onsemi.com
20
PACKAGE DIMENSIONS
PDIP−8
N SUFFIX
PLASTIC PACKAGE
CASE 626−05
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14
58
F
NOTE 2 −A−
−B−
−T−
SEATING
PLANE
H
J
GDK
N
C
L
M
M
A
M
0.13 (0.005) B M
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.40 10.16 0.370 0.400
B6.10 6.60 0.240 0.260
C3.94 4.45 0.155 0.175
D0.38 0.51 0.015 0.020
F1.02 1.78 0.040 0.070
G2.54 BSC 0.100 BSC
H0.76 1.27 0.030 0.050
J0.20 0.30 0.008 0.012
K2.92 3.43 0.115 0.135
L7.62 BSC 0.300 BSC
M−−− 10 −−− 10
N0.76 1.01 0.030 0.040
LP2950, LP2951, NCV2951
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21
PACKAGE DIMENSIONS
Micro8
DM SUFFIX
PLASTIC PACKAGE
CASE 846A−02
ISSUE F
S
B
M
0.08 (0.003) A S
TDIM MIN MAX MIN MAX
INCHESMILLIMETERS
A2.90 3.10 0.114 0.122
B2.90 3.10 0.114 0.122
C−−− 1.10 −−− 0.043
D0.25 0.40 0.010 0.016
G0.65 BSC 0.026 BSC
H0.05 0.15 0.002 0.006
J0.13 0.23 0.005 0.009
K4.75 5.05 0.187 0.199
L0.40 0.70 0.016 0.028
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. 846A−01 OBSOLETE, NEW STANDARD 846A−02.
−B−
−A−
D
K
G
PIN 1 ID
8 PL
0.038 (0.0015)
−T− SEATING
PLANE
C
HJL
8X 8X
6X mm
inches
SCALE 8:1
1.04
0.041 0.38
0.015
5.28
0.208
4.24
0.167
3.20
0.126
0.65
0.0256
*For additional information on our Pb−Free strategy and soldering
details please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
LP2950, LP2951, NCV2951
http://onsemi.com
22
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