DS-25SF321B–179B–6/2019
Features
Serial Peripheral Interface (SPI) Compatible
Support Protocol: Single, Dual, Quad I/O operation
108 MHz Maximum Operating Frequency
Single 2.7V - 3.6V Single Supply Voltage
Execute-In-Place (XIP) support
Continuous Read mode (with 8/16/32/64 bytes wrap)
Serial Flash Discoverable Parameters (SFDP, JDES216B) support
OTP Memory
- Three Protected Programmable Security Register Pages (Page size: 256 bytes)
- 64-bit factory programmable UID register
Hardware Write Protection (WP pin)
Software Write protection (Programmable non-volatile control registers)
Program and Erase Suspend and Resume
Byte programming size: up to 256 bytes
Erase Size and Duration
- Uniform 4-Kbyte Block Erase (50 ms typical)
- Uniform 32-Kbyte Block Erase (150 ms typical)
- Uniform 64-Kbyte Block Erase (300 ms typical)
- Full Chip Erase (15 seconds typical)
Low Power Dissipation
- Standby Current (25 µA maximum)
- Deep Power Down Current (5 µA maximum)
Endurance: 100,000 Program and Erase Cycles
Data Retention: 20 Years
Industrial Temperature Range (-40
o
C to 85
o
C)
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
- 8-lead N-SOIC (0.150” Narrow and 0.208” Wide)
- 8-pad Ultra-Thin DFN (5 x 6 x 0.6 mm)
- Other Package Options (contact Adesto)
AT25SF321B
32-Mbit SPI Serial Flash
with Dual-I/O and Quad-IO Support
PRELIMINARY DATASHEET
2AT25SF321B
DS-25SF321B–179B–6/2019
Description
The Adesto
®
AT25SF321B is a serial interface Flash memory device designed for use in a wide variety of high-volume
consumer based applications in which program code is shadowed from Flash memory into embedded or external RAM
for execution. The flexible erase architecture of the AT25SF321B is ideal for data storage as well, eliminating the need
for additional data storage devices.
The erase block sizes of the AT25SF321B have been optimized to meet the needs of today's code and data storage
applications. By optimizing the size of the erase blocks, the memory space can be used much more efficiently. Because
certain code modules and data storage segments must reside by themselves in their own erase regions, the wasted and
unused memory space that occurs with large block erase Flash memory devices can be greatly reduced. This increased
memory space efficiency allows additional code routines and data storage segments to be added while still maintaining
the same overall device density.
The device also contains three pages of Security Register that can be used for purposes such as unique device
serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc. These Security Register
pages can be individually locked.
3AT25SF321B
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1. Pin Descriptions and Package Pinouts
Table 1-1. Pin Descriptions
Symbol Name and Function
Asserted
State Type
CS
CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is
deasserted, the device will be deselected and normally be placed in standby mode.
A high-to-low transition on the CS pin is required to start an operation, and a low-
to-high transition is required to end an operation. When ending an internally self-
timed operation such as a program or erase cycle, the device will not enter the
standby mode until the completion of the operation.
Low Input
SCK
SERIAL CLOCK: This pin is used to provide a clock to the device. Command,
address, and input data present on the SI pin is always latched in on the rising
edge of SCK, while output data on the SO pin is always clocked out on the falling
edge of SCK.
- Input
SI (I/O
0
)
SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used
for all data input including command and address sequences. Data on the SI pin is
always latched in on the rising edge of SCK.
With the Dual-Output and Quad-Output Read commands, the SI Pin becomes an
output pin (I/O
0
) in conjunction with other pins to allow two or four bits of data on
(I/O
3-0
) to be clocked in on every falling edge of SCK
Data present on the SI pin will be ignored whenever the device is deselected (CS
is deasserted).
- Input/Output
SO (I/O
1
)
SERIAL OUTPUT: Data on the SO pin is always clocked out on the falling edge of
SCK.
With the Dual-Output Read commands, the SO Pin remains an output pin (I/O
0
) in
conjunction with other pins to allow two bits of data on (I/O
1-0
) to be clocked in on
every falling edge of SCK
The SO pin will be in a high-impedance state whenever the device is deselected
(CS is deasserted).
- Input/Output
WP
(I/O
2
)
WRITE PROTECT: The WP pin controls the hardware locking feature of the
device.
With the Quad-Input Byte/Page Program command, the WP pin becomes an input
pin (I/O
2
) and, along with other pins, allows four bits (on I/O
3-0
) of data to be
clocked in on every rising edge of SCK. With the Quad-Output Read commands,
the WP Pin becomes an output pin (I/O
2
) in conjunction with other pins to allow
four bits of data on (I/O3
3-0
) to be clocked in on every falling edge of SCK.
The WP pin is internally pulled-high and may be left floating if hardware controlled
protection will not be used. However, it is recommended that the WP pin also be
externally connected to V
CC
whenever possible.
- Input/Output
4AT25SF321B
DS-25SF321B–179B–6/2019
HOLD
(I/O
3
)
HOLD: The HOLD pin is used to temporarily pause serial communication without
deselecting or resetting the device. While the HOLD pin is asserted, transitions on
the SCK pin and data on the SI pin will be ignored, and the SO pin will be in a high-
impedance state.
The CS pin must be asserted, and the SCK pin must be in the low state in order for
a Hold condition to start. A Hold condition pauses serial communication only and
does not have an effect on internally self-timed operations such as a program or
erase cycle. Please refer to “Hold Function” on page 38 for additional details on the
Hold operation.
With the Quad-Input Byte/Page Program command, the HOLD pin becomes an
input pin (I/O
3
) and, along with other pins, allows four bits (on I/O
3-0
) of data to be
clocked in on every rising edge of SCK. With the Quad-Output Read commands,
the HOLD Pin becomes an output pin (I/O
3
) in conjunction with other pins to allow
four bits of data on (I/O3
3-0
) to be clocked in on every falling edge of SCK.
The HOLD pin is internally pulled-high and may be left floating if the Hold function
will not be used. However, it is recommended that the HOLD pin also be externally
connected to V
CC
whenever possible.
- Input/Output
V
CC
DEVICE POWER SUPPLY: The V
CC
pin is used to supply the source voltage to the
device. - Power
GND GROUND: The ground reference for the power supply. GND should be connected
to the system ground. - Power
Table 1-1. Pin Descriptions (Continued)
Symbol Name and Function
Asserted
State Type
Figure 1-1. 8-SOIC (0.150” and 0.208”) — Top View Figure 1-2. 8-UDFN — Top View
1
2
3
4
8
7
6
5
CS
SO
WP
GND
VCC
HOLD
SCK
SI
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
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2. Block Diagram
Figure 2-1. Block Diagram
Flash
Memory
Array
Y-Gating
CS
SCK
Note: I/O3-0 pin naming convention is used for Dual-I/O and Quad-I/O commands.
SO (I/O1)
SI (I/O0)
Y-Decoder
Address Latch
X-Decoder
I/O Buffers
and Latches
Control and
Protection Logic
SRAM
Data Buffer
WP (I/O2)
Interface
Control
And
Logic
HOLD (I/O3)
6AT25SF321B
DS-25SF321B–179B–6/2019
3. Memory Array
To provide the greatest flexibility, the memory array of the AT25SF321B can be erased in four levels of granularity
including a full chip erase. The size of the erase blocks is optimized for both code and data storage applications, allowing
both code and data segments to reside in their own erase regions. The Memory Architecture Diagram illustrates the
breakdown of each erase level.
Figure 3-1. Memory Architecture Diagram
64KB 32KB 4KB 1-256 Byte
4KB
3FFFFFh – 3FF000h 256 Bytes 3FFFFFh – 3FFF00h
4KB
3FEFFFh – 3FE000h 256 Bytes 3FFEFFh – 3FFE00h
4KB
3FDFFFh – 3FD000h 256 Bytes 3FFDFFh – 3FFD00h
4KB
3FCFFFh – 3FC000h 256 Bytes 3FFCFFh – 3FFC00h
4KB
3FBFFFh – 3FB000h 256 Bytes 3FFBFFh – 3FFB00h
4KB
3FAFFFh – 3FA000h 256 Bytes 3FFAFFh – 3FFA00h
4KB 3F9FFFh – 3F9000h 256 Bytes 3FF9FFh – 3FF900h
4KB 3F8FFFh – 3F8000h 256 Bytes 3FF8FFh – 3FF800h
4KB 3F7FFFh – 3F7000h 256 Bytes 3FF7FFh – 3FF700h
4KB 3F6FFFh – 3F6000h 256 Bytes 3FF6FFh – 3FF600h
4KB 3F5FFFh – 3F5000h 256 Bytes 3FF5FFh – 3FF500h
4KB 3F4FFFh – 3F4000h 256 Bytes 3FF4FFh – 3FF400h
4KB 3F3FFFh – 3F3000h 256 Bytes 3FF3FFh – 3FF300h
4KB 3F2FFFh – 3F2000h 256 Bytes 3FF2FFh – 3FF200h
4KB 3F1FFFh – 3F1000h 256 Bytes 3FF1FFh – 3FF100h
4KB 3F0FFFh – 3F0000h 256 Bytes 3FF0FFh – 3FF000h
4KB
3EFFFFh – 3EF000h 256 Bytes 3FEFFFh – 3FEF00h
4KB
3EEFFFh – 3EE000h 256 Bytes 3FEEFFh – 3FEE00h
4KB
3EDFFFh – 3ED000h 256 Bytes 3FEDFFh – 3FED00h
4KB
3ECFFFh – 3EC000h 256 Bytes 3FECFFh – 3FEC00h
4KB
3EBFFFh – 3EB000h 256 Bytes 3FEBFFh – 3FEB00h
4KB
3EAFFFh – 3EA000h 256 Bytes 3FEAFFh – 3FEA00h
4KB
3E9FFFh – 3E9000h 256 Bytes 3FE9FFh – 3FE900h
4KB
3E8FFFh – 3E8000h 256 Bytes 3FE8FFh – 3FE800h
4KB 3E7FFFh – 3E7000h
4KB 3E6FFFh – 3E6000h
4KB 3E5FFFh – 3E5000h
4KB 3E4FFFh – 3E4000h 256 Bytes 0017FFh – 001700h
4KB 3E3FFFh – 3E3000h 256 Bytes 0016FFh – 001600h
4KB 3E2FFFh – 3E2000h 256 Bytes 0015FFh – 001500h
4KB 3E1FFFh – 3E1000h 256 Bytes 0014FFh – 001400h
4KB 3E0FFFh – 3E0000h 256 Bytes 0013FFh – 001300h
4KB 00FFFFh–00F000h 256 Bytes 0011FFh – 001100h
4KB 00EFFFh–00E000h 256 Bytes 0010FFh – 001000h
4KB 00DFFFh–00D000h 256 Bytes 000FFFh – 000F00h
4KB 00CFFFh–00C000h 256 Bytes 000CFFh – 000C00h
4KB 00BFFFh–00B000h 256 Bytes 000BFFh – 000B00h
4KB 00AFFFh–00A000h 256 Bytes 000AFFh – 000A00h
4KB 009FFFh–009000h 256 Bytes 0009FFh – 000900h
4KB 008FFFh–008000h 256 Bytes 0008FFh – 000800h
4KB 007FFFh–007000h 256 Bytes 0007FFh – 000700h
4KB 006FFFh–006000h 256 Bytes 0006FFh – 000600h
4KB 005FFFh–005000h 256 Bytes 0005FFh – 000500h
4KB 004FFFh–004000h 256 Bytes 0004FFh – 000400h
4KB 003FFFh–003000h 256 Bytes 0003FFh – 000300h
4KB 002FFFh–002000h 256 Bytes 0002FFh – 000200h
4KB 001FFFh–001000h 256 Bytes 0001FFh – 000100h
4KB 000FFFh–000000h 256 Bytes 0000FFh – 000000h
• • •
64KB
Sector 0
Block Erase Detail Page Program Detail
Page AddressBlock Address
32KB
32KB
Range
• • •
Range
32KB
32KB
• • •
64KB
Sector 63
32KB
32KB
64KB
Sector 62
• • •
• • •
256 Bytes 0013FFh – 001300h
256 Bytes 0013FFh – 001300h
256 Bytes 0012FFh – 001200h
7AT25SF321B
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4. Device Operation
The AT25SF321B is controlled by a set of instructions that are sent from a host controller, SPI Master. The SPI Master
communicates with the AT25SF321B via the SPI bus which is comprised of four pins: Chip Select (CS), Serial Clock
(SCK), Serial Input (SI), and Serial Output (SO).
The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3). The AT25SF321B supports the two most
common modes, SPI Modes 0 and 3. For both SPI modes 0 and 3, data is always latched in on the rising edge of SCK
and always output on the falling edge of SCK.
Figure 4-1. SPI Mode 0 and 3
4.1 Dual Output Read
The AT25SF321B features a Dual-Output Read mode that allow two bits of data to be clocked out of the device every
clock cycle to improve throughput. To accomplish this, both the SI and SO pins are utilized as outputs for the transfer of
data bytes. With the Dual-Output Read Array command, the SI pin becomes an output along with the SO pin.
4.2 Quad Output Read
The AT25SF321B features a Quad-Output Read mode that allow four bits of data to be clocked out of the device every
clock cycle to improve throughput. To accomplish this, the SI, SO,
WP
,
HOLD
pins are utilized as outputs for the transfer
of data bytes. With the Quad-Output Read Array command, the SI,
WP
,
HOLD
pins become outputs along with the SO
pin.
SCK
CS
SI
SO
MSB LSB
MSB LSB
8AT25SF321B
DS-25SF321B–179B–6/2019
5. Commands and Addressing
A valid instruction or operation must always be started by first asserting the CS pin. After the CS pin has been asserted,
the host controller must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode, instruction dependent
information such as address and data bytes would then be clocked out by the host controller. All opcode, address, and
data bytes are transferred with the most-significant bit (MSB) first. An operation is ended by deasserting the CS pin.
Opcodes not supported by the AT25SF321B will be ignored by the device and no operation will be started. The device
will continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and
then reasserted). In addition, if the CS pin is deasserted before complete opcode and address information is sent to the
device, then no operation will be performed and the device will simply return to the idle state and wait for the next
operation.
Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23-A0.
Since the upper address limit of the AT25SF321B memory array is 3FFFFFh, address bits A23-A22 are always ignored
by the device.
Table 5-1. AT25SF321B Command Table
Command Name
Command
Opcode
Bus Transfer
Type
(OP-AD-DA)
(1)
Mode Bit
Present
Mode Bit
Clocks
Wait Cycle
Dummy Clocks
Number of
Data Bytes
System Commands
Enable Reset 66h 1-0-0 N 0 0 0
Reset Device 99h 1-0-0 N 0 0 0
Deep Power-down B9h 1-0-0 N 0 0 0
Release Power-down ABh 1-0-0 N 0 0 0
Read Commands
Normal Read Data 03h 1-1-1 N 0 0 1+
Fast Read 0Bh 1-1-1 N 0 8 1+
Dual Output Fast read 3Bh 1-1-2 N 0 8 1+
Dual I/O Fast read BBh 1-2-2 Y 4 0 1+
Dual I/O Fast read (Continuous Mode) BBh 0-2-2 Y 4 0 1+
Quad Output Fast read 6Bh 1-1-4 N 0 8 1+
Quad I/O Fast read EBh 1-4-4 Y 2 4 1+
Quad I/O Fast read (Continuous Mode) EBh 0-4-4 Y 2 4 1+
Word Read Quad I/O E7h 1-4-4 Y 2 2 1+
Word Read Quad I/O (Continuous
Mode) E7h 0-4-4 Y 2 2 1+
Set Burst With Wrap 77h 1-0-4 N 0 6 1, D[6:4]
Write Commands
Write Enable 06h 1-0-0 N 0 0 0
Volatile SR Write Enable 50h 1-0-0 N 0 0 0
Write Disable 04h 1-0-0 N 0 0 0
9AT25SF321B
DS-25SF321B–179B–6/2019
Program Commands
Page Program 02h 1-1-1 N 0 0 1+
Quad Page Program 32h 1-1-4 N 0 0 1+
Erase Commands
Sector Erase (4KB) 20h 1-1-0 N 0 0 0
Block Erase (32KB) 52h 1-1-0 N 0 0 0
Block Erase (64KB) D8h 1-1-0 N 0 0 0
Chip Erase C7h/60h 1-0-0 N 0 0 0
Suspend/Resume Commands
Program/Erase Suspend 75h 1-0-0 N 0 0 0
Program/Erase Resume 7Ah 1-0-0 N 0 0 0
Status Register Commands
Read Status Register 1 05h 1-0-1 N 0 0 1
Read Status Register 2 35h 1-0-1 N 0 0 1
Read Status Register 3 15h 1-0-1 N 0 0 1
Write Status Register 1 01h 1-0-1 N 0 0 1
Write Status Register 2 31h 1-0-1 N 0 0 1
Write Status Register 3 11h 1-0-1 N 0 0 1
Device Information Commands
Manufacturer/Device ID 90h 1-1-1 N 0 0 2
Mfgr./Device ID Dual I/O 92h 1-2-2 N 0 4 2
Mfgr./Device ID Quad I/O 94h 1-4-4 N 0 4 2
Read JEDEC ID 9Fh 1-0-1 N 0 0 3
Read Serial Flash Discoverable
Parameter 5Ah 1-1-1 N 0 8 1+
OTP Commands
Erase Security Registers 44h 1-1-0 N 0 0 0
Program Security Registers 42h 1-1-1 N 0 0 1+
Read Security Registers 48h 1-1-1 N 0 8 1+
Read Unique ID Number 4Bh 1-0-1 N 0 32 1+
Table 5-1. AT25SF321B Command Table (Continued)
Command Name
Command
Opcode
Bus Transfer
Type
(OP-AD-DA)
(1)
Mode Bit
Present
Mode Bit
Clocks
Wait Cycle
Dummy Clocks
Number of
Data Bytes
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6. Read Commands
6.1 Read Array (0Bh and 03h)
The Read Array command can be used to sequentially read a continuous stream of data from the device by simply
providing the clock pin once the initial starting address is specified. The device incorporates an internal address counter
that automatically increments every clock cycle.
To perform the Read Array operation, the CS pin must first be asserted and the appropriate opcode (0Bh or 03h) must be
clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the
starting address location of the first byte to read within the memory array. Following the three address bytes, an
additional dummy byte needs to be clocked into the device if the 0Bh opcode is used for the Read Array operation.
After the three address bytes (and the dummy byte if using opcode 0Bh) have been clocked in, additional clock cycles
will result in data being output on the SO pin. The data is always output with the MSB of a byte first. When the last byte
(3FFFFFh) of the memory array has been read, the device will continue reading back at the beginning of the array
(000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the array.
Deasserting the CS pin will terminate the read operation and put the SO pin into high-impedance state. The CS pin can
be deasserted at any time and does not require a full byte of data be read.
Figure 6-1. Read Array - 03h Opcode
1. OP = Opcode (command number), AD = Address. DA = Data. A value of 0 indicates that the corresponding transfer does not occur in that command. A
value of 1 indicates that the transfer does occur. For example, 1-0-0 indicates a command transfer occurs, but no address or data transfers occur.
Op: Opcode or Commands (8-bits): 0 => No Opcode[continuous Read], 1 => 8 clocks for Opcode, 2 => 4 clocks for Opcode, 4 => 2 clocks for opcode
AD: Address (24-bits) Only: 0 => No address, Opcode only operation, 1 => 24 clocks for Address, 2 => 12 clocks for address, 4 => 6 clocks for address
AD: Address (24-bits) + Mode (8-bits): 2 => 12 clocks for address, 4 clocks for mode [BBh only], 4 => 6 clocks for address, 2 clocks for mode [EBh & E7h]
DA: Data(8-bits): 1 => 8 clocks for Byte, 2 => 4 clocks for Byte, 4 => 2 clocks for Byte
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11AT25SF321B
DS-25SF321B–179B–6/2019
Figure 6-2. Read Array - 0Bh Opcode
6.2 Dual-Output Read Array (3Bh)
The Dual-Output Read Array command is similar to the standard Read Array command and can be used to sequentially
read a continuous stream of data from the device by simply providing the clock pin once the initial starting address has
been specified. Unlike the standard Read Array command, however, the Dual-Output Read Array command allows two
bits of data to be clocked out of the device on every clock cycle, rather than just one.
To perform the Dual-Output Read Array operation, the CS pin must first be asserted and then the opcode 3Bh must be
clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the
location of the first byte to read within the memory array. Following the three address bytes, a single dummy byte must
also be clocked into the device.
After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data being
output on both the SO and SI pins. The data is always output with the MSB of a byte first and the MSB is always output
on the SO pin. During the first clock cycle, bit seven of the first data byte is output on the SO pin, while bit six of the same
data byte is output on the SI pin. During the next clock cycle, bits five and four of the first data byte are output on the SO
and SI pins, respectively. The sequence continues with each byte of data being output after every four clock cycles.
When the last byte (3FFFFFh) of the memory array has been read, the device will continue reading from the beginning of
the array (000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the
array.Deasserting the CS pin will terminate the read operation and put the SO and SI pins into a high-impedance state.
The CS pin can be deasserted at any time and does not require that a full byte of data be read.
Figure 6-3. Dual-Output Read Array
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SCK
CS
6,6,2
SO
MSB
MSB
2
3
1
0
0
0
1
1
1
0
1
1
6
7
5
4
10
11
9
8
12
39
42
43
41
40
37
38
33
36
35
34
31
32
29
30
44
47
48
46
45
23&2'(
A
A
A
A
A
A
A
A
A
MSB
X
X
X
X
X
X
X
X
MSB
MSB
MSB
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
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D
A
T
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D
A
T
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12AT25SF321B
DS-25SF321B–179B–6/2019
6.3 Dual-I/O Read Array (BBh)
The Dual-I/O Read Array command is similar to the Dual-Output Read Array command and can be used to sequentially
read a continuous stream of data from the device by simply providing the clock pin once the initial starting address with
two bits of address on each clock and two bits of data on every clock cycle.
To perform the Dual-I/O Read Array operation, the CS pin must first be asserted and then the opcode BBh must be
clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the
location of the first byte to read within the memory array. Following the three address bytes, a single mode byte must also
be clocked into the device.
After the three address bytes and the mode byte have been clocked in, additional clock cycles will result in data being
output on both the SO and SI pins. The data is always output with the MSB of a byte first and the MSB is always output
on the SO pin. During the first clock cycle, bit seven of the first data byte is output on the SO pin, while bit six of the same
data byte is output on the SI pin. During the next clock cycle, bits five and four of the first data byte are output on the SO
and SI pins, respectively. The sequence continues with each byte of data being output after every four clock cycles.
When the last byte (3FFFFFh) of the memory array has been read, the device will continue reading from the beginning of
the array (000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the
array.Deasserting the CS pin will terminate the read operation and put the SO and SI pins into a high-impedance state.
The CS pin can be deasserted at any time and does not require that a full byte of data be read.
Figure 6-4. Dual I/O Read Array (Initial command or previous M5, M4 ≠ 1,0)
6.3.1 Dual-I/O Read Array (BBh) with Continuous Read Mode
The Fast Read Dual I/O command can further reduce instruction overhead through setting the Continuous Read Mode
bits (M7-0) after the input Address bits (A23-0), as shown in Figure 6-5. The upper nibble of the (M7-4) controls the
length of the next Fast Read Dual I/O command through the inclusion or exclusion of the first byte instruction code. The
lower nibble bits of the (M3-0) are don't care ("x"). However, the IO pins should be high-impedance prior to the falling
edge of the first data out clock. If the "Continuous Read Mode" bits M5-4 = (1,0), then the next Fast Read Dual I/O
command (after CS is raised and then lowered) does not require the BBH instruction code, as shown in Figure 15. This
reduces the command sequence by eight clocks and allows the Read address to be immediately entered after CS is
asserted low. If the "Continuous Read Mode" bits M5-4 do not equal to (1,0), the next command (after CS is raised and
then lowered) requires the first byte instruction code, thus returning to normal operation. A Continuous Read Mode Reset
command can also be used to reset (M7-0) before issuing normal commands.
I/O0
(SI)
SCK
I/O1
(SO)
CS
MSB
MSB
2 310
1 0 1 1 1 0 1 1
6 754 10 1198 12 2321 2219 20
Opcode
A22 A20 A18 A16 A0M6M4A14 A
Address Bits
A23-A16
M3
M2
M1
M0
Address Bits
A15-A8 A7-A0 M7-M0
MSB
A23 A21 A19 A17 A1M7M5A15 A
2725 2624
D6D4
D3
D2
D1
D0
Byte 1
D7D5
D6
D7
Byte 2
13AT25SF321B
DS-25SF321B–179B–6/2019
Figure 6-5. Dual-I/O Read Array (Previous command set M5, M4 = 1,0)
6.4 Quad-Output Read Array (6Bh)
The Quad-Output Read Array command is similar to the Dual-Output Read Array command. The Quad-Output Read
Array command allows four bits of data to be clocked out of the device on every clock cycle, rather than just one or two.
The Quad Enable bit (QE) of the Status Register must be set to enable for the Quad-Output Read Array instruction.
To perform the Quad-Output Read Array operation, the CS pin must first be asserted and then the opcode 6Bh must be
clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the
location of the first byte to read within the memory array. Following the three address bytes, a single dummy byte must
also be clocked into the device.
After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data being
output on the I/O
3-0
pins. The data is always output with the MSB of a byte first and the MSB is always output on the I/O
3
pin. During the first clock cycle, bit 7 of the first data byte will be output on the I/O
3
pin while bits 6, 5, and 4 of the same
data byte will be output on the I/O
2
, I/O
1
, and I/O
0
pins, respectively. During the next clock cycle, bits 3, 2, 1, and 0 of the
first data byte will be output on the I/O
3
, I/O
2
, I/O
1
and I/O
0
pins, respectively.
The sequence continues with each byte of data being output after every two clock cycles. When the last byte (3FFFFFh)
of the memory array has been read, the device will continue reading from the beginning of the array (000000h). No
delays will be incurred when wrapping around from the end of the array to the beginning of the array.Deasserting the CS
I/O0
(SI)
SCK
I/O1
(SO)
CS
MSB
2 310 6 754 10 1198 12 1715 1613 14
A22 A20 A18 A16 A0M6M4A14 A
Address Bits
A23-A16
M3
M2
M1
M0
Address Bits
A15-A8 A7-A0
M7-M0
MSB
A23 A21 A19 A17 A1M7M5
A15 A
2119 2018
D6D4
D3
D2
D1
D0
Byte 1
D7D5
D6
D7
Byte 2
I/O0
(SI)
SCK
I/O1
(SO)
CS
2 310 6 754 10 1198
A20 A16 A12 A8
A23-A16 A15-A8
A21 A17 A13 A9
D4
D1
D0
D5
D4
Byte 1
D5
D0
D1
Byte 2
I/O2
(WP)
A22 A18 A14 A10 D2D6
D6D2
I/O3
(HOLD)
A23 A19 A15 A11 D3D7
D7D3
14 151312
A4A0M4M0
A7-A0 M7-M0
A6A2M6M2
A7A3M7M3
A5A1M5M1
Dummy
14AT25SF321B
DS-25SF321B–179B–6/2019
pin will terminate the read operation and put the WP, HOLD, SO, SI pins into a high-impedance state. The CS pin can be
deasserted at any time and does not require that a full byte of data be read.
Figure 6-6. Quad-Output Read Array
6.5 Quad-I/O Read Array(EBh)
The Quad-I/O Read Array command is similar to the Quad-Output Read Array command. The Quad-I/O Read Array
command allows four bits of address to be clocked into the device on every clock cycle, rather than just one.
To perform the Quad-I/O Read Array operation, the CS pin must first be asserted and then the opcode EBh must be
clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the
location of the first byte to read within the memory array. Following the three address bytes, a single mode byte must also
be clocked into the device.
After the three address bytes, the mode byte and two dummy bytes have been clocked in, additional clock cycles will
result in data being output on the I/O
3-0
pins. The data is always output with the MSB of a byte first and the MSB is always
output on the I/O
3
pin. During the first clock cycle, bit 7 of the first data byte will be output on the I/O
3
pin while bits 6, 5,
and 4 of the same data byte will be output on the I/O
2
, I/O
1
and I/O
0
pins, respectively. During the next clock cycle, bits 3,
2, 1, and 0 of the first data byte will be output on the I/O
3
, I/O
2
, I/O
1
and I/O
0
pins, respectively. The sequence continues
with each byte of data being output after every two clock cycles.
When the last byte (3FFFFFh) of the memory array has been read, the device will continue reading from the beginning of
the array (000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the
array.Deasserting the CS pin will terminate the read operation and put the I/O
3
, I/O
2
, I/O
1
and I/O
0
pins into a high-
impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.The
Quad Enable bit (QE) of the Status Register must be set to enable for the Quad-I/O Read Array instruction.
I/O0
(SI)
SCK 06%06%2 310
0 1 1 0 1 0 1 1
6 754 10 1198 12 39 42 43414037 3833 36353431 3229 30 44 47 484645
Opcode
AAAA AAAAA 06%X X X X X X X X
Address Bits A23-A0 Don't Care
Byte 1
OUT
Byte 2
OUT
Byte 3
OUT
Byte 4
OUT
Byte 5
OUT
I/O1
(SO)
High-impedance D5 D1 D5 D1 D5 D1 D5 D1 D5 D1
I/O2
(WP)
High-impedance D6 D2 D6 D2 D6 D2 D6 D2 D6 D2
I/O3
(HOLD) MSB MSB MSB MSB MSB
High-impedance D7 D3 D7 D3 D7 D3 D7 D3 D7 D3
D4 D0 D4 D0 D4 D0 D4 D0 D4 D0
CS
15AT25SF321B
DS-25SF321B–179B–6/2019
Figure 6-7. Quad-I/O Read Array (Initial command or previous M5, M4 ≠ 1,0)
6.5.1 Quad-I/O Read Array (EBh) with Continuous Read Mode
The Fast Read Quad I/O command can further reduce instruction overhead through setting the Continuous Read Mode
bits (M7-0) after the input Address bits (A23-0), as shown in Figure 6-7. The upper nibble (M7-4) of the Continuous Read
Mode bits controls the length of the next Fast Read Quad I/O command through the inclusion or exclusion of the first byte
instruction code. The lower nibble bits (M3-0) of the Continuous Read Mode bits are don't care. However, the IO pins
should be high-impedance prior to the falling edge of the first data out clock. If the Continuous Read Mode bits M5-4 =
(1,0), then the next Quad-I/O Read Array command (after CS is raised and then lowered) does not require the EBh
instruction code, as shown in Figure 6-8. This reduces the command sequence by eight clocks and allows the Read
address to be immediately entered after CS is asserted low. If the Continuous Read Mode bits M5-4 do not equal to (1,0),
the next command (after CS is raised and then lowered) requires the first byte instruction code, thus returning to normal
operation. A Continuous Read Mode Reset command can also be used to reset (M7-0) before issuing normal
commands.
Figure 6-8. Quad I/O Read Array with Continuous Read Mode (Previous Command Set M5-4 =1,0)
I/O0
(SI)
SCK
I/O1
(SO)
CS
MSB
2 310
1 1 1 0 1 0 1 1
6 754 10 1198 1917 1816
Opcode
A20 A16 A12 A8
A23-A16 A15-A8
A21 A17 A13 A9
2321 2220
D4
D1
D0
D5
D4
Byte 1
D5
D0
D1
Byte 2
I/O2
(WP)
A22 A18 A14 A10 D2D6
D6D2
I/O3
(HOLD)
A23 A19 A15 A11 D3D7
D7D3
14 151312
A4A0M4M0
A7-A0 M7-M0
A6A2M6M2
A7A3M7M3
A5A1M5M1
Dummy
I/O0
(SI)
SCK
I/O1
(SO)
CS
2 310 6 754 10 1198
A20 A16 A12 A8
A23-A16 A15-A8
A21 A17 A13 A9
D4
D1
D0
D5
D4
Byte 1
D5
D0
D1
Byte 2
I/O2
(WP)
A22 A18 A14 A10 D2D6
D6D2
I/O3
(HOLD)
A23 A19 A15 A11 D3D7
D7D3
14 151312
A4A0M4M0
A7-A0 M7-M0
A6A2M6M2
A7A3M7M3
A5A1M5M1
Dummy
16AT25SF321B
DS-25SF321B–179B–6/2019
6.6 Read Serial Flash Discoverable Parameter (5Ah)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the
functional and feature capabilities of serial Flash devices in a standard set of internal parameter tables. These
parameter tables can be interrogated by host system software to enable adjustments needed to accommodate
divergent features from multiple vendors. SFDP is a JEDEC Standard, JESD216B. For more detailed SFDP values
please contact Adesto.
Figure 6-9. Read Serial Flash Discoverable Parameter Command Sequence Diagram
D D D D D D D D
X X X X X X X XA A A A A A A A
MSB
MSB LSB
MSB
0 1 0 1 1 0 1 0
Output Data Byte 1
8 Dummy Cycles
Address Bits A23-A0
Opcode
DS
2 310 6 754 10 1198 29 3012 33 343231 37 383635 41 424039 45 464443
SI
SCK
SO
CS
17AT25SF321B
DS-25SF321B–179B–6/2019
7. Program and Erase Commands
7.1 Byte/Page Program (02h)
The Byte/Page Program command allows anywhere from a single byte of data to 256 bytes of data to be programmed
into previously erased memory locations. An erased memory location is one that has all eight bits set to the logical “1”
state (a byte value of FFh). Before a Byte/Page Program command can be started, the Write Enable command must
have been previously issued to the device (see “Write Enable (06h)” on page 21) to set the Write Enable Latch (WEL) bit
of the Status Register to a logical “1” state.
To perform a Byte/Page Program command, an opcode of 02h must be clocked into the device followed by the three
address bytes denoting the first byte location of the memory array to begin programming at. After the address bytes have
been clocked in, data can then be clocked into the device and will be stored in an internal buffer.
If the starting memory address denoted by A23-A0 does not fall on an even 256-byte page boundary (A7-A0 are not all
0), then special circumstances regarding which memory locations to be programmed will apply. In this situation, any data
that is sent to the device that goes beyond the end of the page will wrap around back to the beginning of the same page.
For example, if the starting address denoted by A23-A0 is 0000FEh, and three bytes of data are sent to the device, then
the first two bytes of data will be programmed at addresses 0000FEh and 0000FFh while the last byte of data will be
programmed at address 000000h. The remaining bytes in the page (addresses 000001h through 0000FDh) will not be
programmed and will remain in the erased state (FFh). In addition, if more than 256 bytes of data are sent to the device,
then only the last 256 bytes sent will be latched into the internal buffer.
When the CS pin is deasserted, the device will take the data stored in the internal buffer and program it into the
appropriate memory array locations based on the starting address specified by A23-A0 and the number of data bytes
sent to the device. If less than 256 bytes of data were sent to the device, then the remaining bytes within the page will not
be programmed and will remain in the erased state (FFh). The programming of the data bytes is internally self-timed and
should take place in a time of t
PP
or t
BP
if only programming a single byte.
The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin is
deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device
will abort the operation and no data will be programmed into the memory array. In addition, if the memory is in the
protected state, then the Byte/Page Program command will not be executed, and the device will return to the idle state
once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to the logical “0” state if the
program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent, the CS pin being
deasserted on uneven byte boundaries, or because the memory location to be programmed is protected.
While the device is programming, the Status Register can be read and will indicate that the device is busy. For faster
throughput, it is recommended that the Status Register be polled rather than waiting the t
BP
or t
PP
time to determine if the
data bytes have finished programming. At some point before the program cycle completes, the WEL bit in the Status
Register will be reset back to the logical “0” state.
Figure 7-1. Byte Program
6&.&66,6206%06%23&2'(+,*+,03('$1&($$$$$$$$$06%''''''''$''5(66%,76$$'$7$,1
18AT25SF321B
DS-25SF321B–179B–6/2019
Figure 7-2. Page Program
7.2 Block Erase (20h, 52h, or D8h)
A block of 4, 32, or 64 Kbytes can be erased (all bits set to the logical “1” state) in a single operation by using one of three
different opcodes for the Block Erase command. An opcode of 20h is used for a 4-Kbyte erase, an opcode of 52h is used
for a 32-Kbyte erase, or D8h is used for a 64-Kbyte erase. Before a Block Erase command can be started, the Write
Enable command must have been previously issued to the device to set the WEL bit of the Status Register to a logical “1”
state.
To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h, 52h, or D8h) must be
clocked into the device. After the opcode has been clocked in, the three address bytes specifying an address within the
4- or 32- or 64-Kbyte block to be erased must be clocked in. Any additional data clocked into the device will be ignored.
When the CS pin is deasserted, the device will erase the appropriate block. The erasing of the block is internally self-
timed and should take place in a time of t
BLKE
.
Since the Block Erase command erases a region of bytes, the lower order address bits do not need to be decoded by the
device. Therefore, for a 4-Kbyte erase, address bits A11-A0 will be ignored by the device and their values can be either a
logical “1” or “0”. For a 32-Kbyte erase, address bits A14-A0 will be ignored by the device. For a 64-Kbyte erase, address
bits A15-A0 will be ignored by the device. Despite the lower order address bits not being decoded by the device, the
complete three address bytes must still be clocked into the device before the CS pin is deasserted, and the CS pin must
be deasserted on an byte boundary (multiples of eight bits); otherwise, the device will abort the operation and no erase
operation will be performed.
If the memory is in the protected state, then the Block Erase command will not be executed, and the device will return to
the idle state once the CS pin has been deasserted.
The WEL bit in the Status Register will be reset back to the logical “0” state if the erase cycle aborts due to an incomplete
address being sent, the CS pin being deasserted on uneven byte boundaries, or because a memory location within the
region to be erased is protected.
While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device
is busy. For faster throughput, it is recommended that the Status Register be polled to determine if the device has
finished erasing. At some point before the erase cycle completes, the WEL bit in the Status Register will be reset back to
the logical “0” state.
6&.&66,6206%06%23&2'(+,*+,03('$1&($$$$$$06%''''''''$''5(66%,76$$'$7$,1%<7(06%'''''''''$7$,1%<7(Q
19AT25SF321B
DS-25SF321B–179B–6/2019
Figure 7-3. Block Erase
7.3 Chip Erase (60h or C7h)
The entire memory array can be erased in a single operation by using the Chip Erase command. Before a Chip Erase
command can be started, the Write Enable command must have been previously issued to the device to set the WEL bit
of the Status Register to a logical “1” state.
Two opcodes (60h and C7h) can be used for the Chip Erase command. There is no difference in device functionality
when utilizing the two opcodes, so they can be used interchangeably. To perform a Chip Erase, one of the two opcodes
must be clocked into the device. Since the entire memory array is to be erased, no address bytes need to be clocked into
the device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted, the device will erase
the entire memory array. The erasing of the device is internally self-timed and should take place in a time of t
CHPE
.
The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be
deasserted on an byte boundary (multiples of eight bits); otherwise, no erase will be performed. In addition, if the memory
array is in the protected state, then the Chip Erase command will not be executed, and the device will return to the idle
state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to the logical “0” state
if the CS pin is deasserted on uneven byte boundaries or if the memory is in the protected state.
While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device
is busy. For faster throughput, it is recommended that the Status Register be polled to determine if the device has
finished erasing. At some point before the erase cycle completes, the WEL bit in the Status Register will be reset back to
the logical “0” state.
7.4 Program/Erase Suspend (75h)
The Program/Erase Suspend command allows a program or erase operation in progress to be suspended so that other
device operations can be performed. For example, by suspending an erase operation to a particular block, the system
can perform functions such as a program or read to a different block.
Chip Erase cannot be suspended. The Program/Erase Suspend command will be ignored if it is issued during a Chip
Erase.A program operation can be performed while an erase operation is suspended, but the program operation cannot
be suspended while an erase operation is currently suspended.
Other device operations, such as a Read Status Register, can also be performed while a program or erase operation is
suspended. Table 7-4 outlines the operations that are allowed and not allowed during a program or erase suspend.
Since the need to suspend a program or erase operation is immediate, the Write Enable command does not need to be
issued prior to the Program/Erase Suspend command being issued. Therefore, the Program/Erase Suspend command
operates independently of the state of the WEL bit in the Status Register.
To perform a Program/Erase Suspend, the CS pin must first be asserted and the opcode of 75h must be clocked into the
device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored.
When the CS pin is deasserted, the program or erase operation currently in progress will be suspended. The Suspend
(E_SUS or P_SUS) bits in the Write Status Register are set to the logical "1" state to indicate that the program or erase
6&.&66,6206%06%&&&&&&&&23&2'($$$$$$$$$$$$$''5(66%,76$$+,*+,03('$1&(
20AT25SF321B
DS-25SF321B–179B–6/2019
operation has been suspended. In addition, the RDY/BSY bit in the Status Register will indicate that the device is ready
for another operation. The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS
pin must be deasserted on a byte boundary (multiples of eight bits). Otherwise, no suspend operation will be performed.
If a read operation is attempted to a suspended area (page for programming or block for erasing), then the device will
output undefined data. Therefore, when performing a Read Array operation to an unsuspended area and the device's
internal address counter increments and crosses into the suspended area, the device will then start outputting undefined
data until the internal address counter crosses to an unsuspended area.
A program operation is not allowed to a block that has been erase suspended. If a program operation is attempted to an
erase suspended block, then the program operation will abort and the WEL bit in the Status Register will be reset back to
a logical "0" state. Likewise, an erase operation is not allowed to a block that included the page that has been program
suspended. If attempted, the erase operation will abort and the WEL bit in the Status Register will be reset to a logical "0"
state.
If an attempt is made to perform an operation that is not allowed during a program or erase suspend, such as a Write
Status Register operation, then the device will simply ignore the opcode and no operation will be performed. The state of
the WEL bit in the Status Register will not be affected.
7.5 Program/Erase Resume (7Ah)
The Program/Erase Resume command allows a suspended program or erase operation to be resumed and continue
programming a Flash page or erasing a Flash memory block where it left off. The Program/Erase Resume instruction will
be accepted by the device only if the SUS bit in the Write Status Register equals 1 and the RDY/BSY bit equals 0. If the
SUS bit equals 0 or the RDY/BSY bit equals to 1, the Program/Erase Resume command will be ignored by the device. As
with the Program/Erase Suspend command, the Write Enable command does not need to be issued prior to the
Program/Erase Resume command being issued. Therefore, the Program/Erase Resume command operates
independently of the state of the WEL bit in the Status Register.
To perform Program/Erase Resume, the CS pin must first be asserted and opcode 7Ah must be clocked into the device.
No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. When the
CS pin is deasserted, the program or erase operation currently suspended will resume. The E_SUS or P_SUS bit in the
Status Register is reset back to the logical "0" state to indicate the program or erase operation is no longer suspended. In
addition, the RDY/BSY bit in the Status Register will indicate that the device is busy performing a program or erase
operation. The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must
be deasserted on a byte boundary (multiples of eight bits). Otherwise, no resume operation will perform.
During a simultaneous Erase Suspend/Program Suspend condition, issuing the Program/Erase Resume command will
result in the program operation resuming first. After the program operation has been completed, the Program/Erase
Resume command must be issued again in order for the erase operation to be resumed.
While the device is busy resuming a program or erase operation, any attempts at issuing the Program/Erase Suspend
command will be ignored. Therefore, if a resumed program or erase operation needs to be subsequently suspended
again, the system must either wait before issuing the Program/Erase Suspend command, or it must check the status of
the RDY/BSY bit or the E_SUS or P_SUS bit in the Status Register to determine if the previously suspended program or
erase operation has resumed.
21AT25SF321B
DS-25SF321B–179B–6/2019
8. Protection Commands and Features
8.1 Write Enable (06h)
The Write Enable command is used to set the Write Enable Latch (WEL) bit in the Status Register to a logical “1” state.
The WEL bit must be set before a Byte/Page Program, Erase, Program Security Register Pages, Erase Security Register
Pages or Write Status Register command can be executed. This makes the issuance of these commands a two step
process, thereby reducing the chances of a command being accidentally or erroneously executed. If the WEL bit in the
Status Register is not set prior to the issuance of one of these commands, then the command will not be executed.
To issue the Write Enable command, the CS pin must first be asserted and the opcode of 06h must be clocked into the
device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored.
When the CS pin is deasserted, the WEL bit in the Status Register will be set to a logical “1”. The complete opcode must
be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an byte boundary
(multiples of eight bits); otherwise, the device will abort the operation and the WEL bit state will not change.
8.2 Write Disable (04h)
The Write Disable command is us0d to reset the Write Enable Latch (WEL) bit in the Status Register to the logical “0”
state. With the WEL bit reset, all Byte/Page Program, Erase, Program Security Register Page, and Write Status Register
commands will not be executed. Other conditions can also cause the WEL bit to be reset; for more details, refer to the
WEL bit section of the Status Register description.
To issue the Write Disable command, the CS pin must first be asserted and the opcode of 04h must be clocked into the
device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored.
When the CS pin is deasserted, the WEL bit in the Status Register will be reset to a logical “0”. The complete opcode
must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an byte
boundary (multiples of eight bits); otherwise, the device will abort the operation and the WEL bit state will not change.
8.3 Non-Volatile Protection
The device can be software protected against erroneous or malicious program or erase operations by utilizing the Non-
Volatile Protection feature of the device. Non-Volatile Protection can be enabled or disabled by using the Write Status
Register command to change the value of the Protection (CMP, SEC, TB, BP2, BP1, BP0) bits in the Status Register.
The following table outlines the states of the Protection bits and the associated protection area
.
Table 8-1. Memory Array with CMP = 0
Protection Bits Memory Content
SEC TB BP2 BP1 BP0 Address Range Portion
X X 0 0 0 None None
0 0 0 0 1 3F0000h-3FFFFFh Upper 1/64
0 0 0 1 0 3E0000h-3FFFFFh Upper 1/32
0 0 0 1 1 3C0000h-3FFFFFh Upper 1/16
0 0 1 0 0 380000h-3FFFFFh Upper 1/8
0 0 1 0 1 300000h-3FFFFFh Upper 1/4
0 0 1 1 0 200000h-3FFFFFh Upper 1/2
0 1 0 0 1 000000h-00FFFFh Lower 1/64
0 1 0 1 0 000000h-01FFFFh Lower 1/32
22AT25SF321B
DS-25SF321B–179B–6/2019
0 1 0 1 1 000000h-03FFFFh Lower 1/16
0 1 1 0 0 000000h-07FFFFh Lower 1/8
0 1 1 0 1 000000h-0FFFFFh Lower 1/4
0 1 1 1 0 000000h-1FFFFFh Lower 1/2
X X 1 1 1 000000h-3FFFFFh ALL
1 0 0 0 1 3FF000h-3FFFFFh Upper 1/512
1 0 0 1 0 3FE000h-3FFFFFh Upper 1/256
1 0 0 1 1 3FC000h-3FFFFFh Upper 1/128
1 0 1 0 X 3F8000h-3FFFFFh Upper 1/64
1 0 1 1 0 3F8000h-3FFFFFh Upper 1/64
1 1 0 0 1 000000h-000FFFh Lower 1/512
1 1 0 1 0 000000h-001FFFh Lower 1/256
1 1 0 1 1 000000h-003FFFh Lower 1/128
1 1 1 0 X 000000h-007FFFh Lower 1/64
1 1 1 1 0 000000h-007FFFh Lower 1/64
Table 8-2. Memory Array Protection with CMP = 1
Protection Bits Memory Content
SEC TB BP2 BP1 BP0 Address Range Portion
X X 0 0 0 000000h-3FFFFFh All
0 0 0 0 1 000000h-3EFFFFh Lower 63/64
0 0 0 1 0 000000h-3DFFFFh Lower 31/32
0 0 0 1 1 000000h-3BFFFFh Lower 15/16
0 0 1 0 0 000000h-37FFFFh Lower 7/8
0 0 1 0 1 000000h-2FFFFFh Lower 3/4
0 0 1 1 0 000000h-1FFFFFh Lower 1/2
0 1 0 0 1 010000h-3FFFFFh Upper 63/64
0 1 0 1 0 020000h-3FFFFFh Upper 31/32
0 1 0 1 1 040000h-3FFFFFh Upper 15/16
0 1 1 0 0 080000h-3FFFFFh Upper 7/8
0 1 1 0 1 100000h-3FFFFFh Upper 3/4
0 1 1 1 0 200000h-3FFFFFh Upper 1/2
Table 8-1. Memory Array with CMP = 0 (Continued)
Protection Bits Memory Content
SEC TB BP2 BP1 BP0 Address Range Portion
23AT25SF321B
DS-25SF321B–179B–6/2019
As a safeguard against accidental or erroneous protecting or unprotecting of the memory array, the Protection can be
locked from updates by using the WP pin (see “Protected States and the Write Protect Pin” on page 23 for more details).
8.4 Protected States and the Write Protect Pin
The WP pin is not linked to the memory array itself and has no direct effect on the protection status of the memory array.
Instead, the WP pin, is used to control the hardware locking mechanism of the device.
If the WP pin is permanently connected to GND, then the protection bits cannot be changed.
X X 1 1 1 NONE NONE
1 0 0 0 1 000000h-3FEFFFh Lower 1023/1024
1 0 0 1 0 000000h-3FDFFFh Lower 511/512
1 0 0 1 1 000000h-3FBFFFh Lower 255/256
1 0 1 0 X 000000h-3F7FFFh Lower 127/128
1 0 1 1 0 000000h-3F7FFFh Lower 127/128
1 1 0 0 1 001000h-3FFFFFh Upper 1023/1024
1 1 0 1 0 002000h-3FFFFFh Upper 511/512
1 1 0 1 1 004000h-3FFFFFh Upper 255/256
1 1 1 0 X 008000h-3FFFFFh Upper 127/128
1 1 1 1 0 008000h-3FFFFFh Upper 127/128
Table 8-2. Memory Array Protection with CMP = 1 (Continued)
Protection Bits Memory Content
SEC TB BP2 BP1 BP0 Address Range Portion
24AT25SF321B
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9. Security Register Commands
The device contains three extra pages called Security Registers that can be used for purposes such as unique device
serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc. The Security Registers are
independent of the main Flash memory.
Each page of the Security Register can be erased and programmed independently. Each page can also be
independently locked to prevent further changes.
9.1 Erase Security Registers (44h)
Before an erase Security Register Page command can be started, the Write Enable command must have been
previously issued to the device to set the WEL bit of the Status Register to a logical "1" state.
To perform an Erase Security Register Page command, the CS pin must first be asserted and the opcode 44h must be
clocked into the device. After the opcode has been clocked in, the three address bytes specifying the Security Register
Page to be erased must be clocked in. When the CS pin is deasserted, the device will erase the appropriate block. The
erasing of the block is internally self-timed and should take place in a time of t
BE
.
Since the Erase Security Register Page command erases a region of bytes, the lower order address bits do not need to
be decoded by the device. Therefore address bits A7-A0 will be ignored by the device. Despite the lower order address
bits not being decoded by the device, the complete three address bytes must still be clocked into the device before the
CS pin is deasserted, and the CS pin must be deasserted right after the last address bit (A0); otherwise, the device will
abort the operation and no erase operation will be performed.
While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device
is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the t
BE
time to
determine if the device has finished erasing. At some point before the erase cycle completes, the RDY/BSY bit in the
Status Register will be reset back to the logical "0" state.
The WEL bit in the Status Register will be reset back to the logical "0" state if the erase cycle aborts due to an incomplete
address being sent, the CS pin being deasserted on uneven byte boundaries, or because a memory location within the
region to be erased is protected.
The Security Registers Lock Bits (LB3-LB1) in the Status Register can be used to OTP protect the security registers.
Once a Lock Bit is set to 1, the corresponding Security Register will be permanently locked. The Erase Security Register
Page instruction will be ignored for Security Registers which have their Lock Bit set.
Figure 9-1. Erase Security Register Page
Table 9-1. Security Register Addresses for Erase Security Register Page Command
Address A23-A16 A15-A12 A11-A8 A7-A0
Security Register 1 00h 1h 0h Don’t Care
Security Register 2 00h 2h 0h Don’t Care
Security Register 3 00h 3h 0h Don’t Care
6&.&66,
MSB
2
3
1
0
6
7
5
4
OPCODE
$$$$$%,7$''5(66
25AT25SF321B
DS-25SF321B–179B–6/2019
9.2 Program Security Registers (42h)
The Program Security Registers command utilizes the internal 256-byte buffer for processing. Therefore, the contents of
the buffer will be altered from its previous state when this command is issued.
The Security Registers can be programmed in a similar fashion to the Program Array operation up to the maximum clock
frequency specified by f
CLK
. Before a Program Security Registers command can be started, the Write Enable command
must have been previously issued to the device (see “Write Enable (06h)” on page 21) to set the Write Enable Latch
(WEL) bit of the Status Register to a logical “1” state. To program the Security Registers, the CS pin must first be
asserted and the opcode of 42h must be clocked into the device. After the opcode has been clocked in, the three address
bytes must be clocked in to specify the starting address location of the first byte to program within the Security Register.
Figure 9-2. Program Security Registers
9.3 Read Security Registers (48h)
The Security Register can be sequentially read in a similar fashion to the Read Array operation up to the maximum clock
frequency specified by f
CLK
. To read the Security Register, the CS pin must first be asserted and the opcode of 48h must
be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify
the starting address location of the first byte to read within the Security Register. Following the three address bytes, one
dummy byte must be clocked into the device before data can be output.
After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in Security
Register data being output on the SO pin. When the last byte (0003FFh) of the Security Register has been read, the
device will continue reading back at the beginning of the register (000000h). No delays will be incurred when wrapping
around from the end of the register to the beginning of the register.
6&.&66,62
MSB
MSB
2
3
1
0
0
0
1
6
7
5
4
9
8
39
37
38
33
36
35
34
31
32
29
30
OPCODE
HIGH-IMPEDANCE
A
A
A
A
A
A
MSB
D
D
D
D
D
D
D
D
ADDRESS BITS A23-A0
DATA IN BYTE 1
MSB
D
D
D
D
D
D
D
D
DATA IN BYTE n
Table 9-2. Security Register Addresses for Program Security Registers Command
Address A23-A16 A15-A12 A11-A8 A7-A0
Security Register 1 00h 1h 0h Byte Address
Security Register 2 00h 2h 0h Byte Address
Security Register 3 00h 3h 0h Byte Address
26AT25SF321B
DS-25SF321B–179B–6/2019
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS pin can
be deasserted at any time and does not require that a full byte of data be read.
Figure 9-3. Read Security Registers
Table 9-3. Security Register Addresses for Read Security Registers Command
Address A23-A16 A15-A12 A11-A8 A7-A0
Security Register 1 00h 1h 0h Byte Address
Security Register 2 00h 2h 0h Byte Address
Security Register 3 00h 3h 0h Byte Address
6&.&66,62
MSB
MSB
2
3
1
0
0
1
6
7
5
4
10
11
9
8
12
33
36
35
34
31
32
29
30
OPCODE
A
A
A
A
A
A
A
A
A
X
X
X
MSB
MSB
D
D
D
D
D
D
D
D
D
D
ADDRESS BITS A23-A0
MSB
X
X
X
X
X
X
DON'T CARE
DATA BYTE 1
HIGH-IMPEDANCE
27AT25SF321B
DS-25SF321B–179B–6/2019
10. Status Register Commands
10.1 Read Status Register (05h, 35h, and 15h)
The Status Register can be read to determine the device's ready/busy status, as well as the status of many other
functions such as Block Protection. The Status Register can be read at any time, including during an internally self-timed
program or erase operation.
To read Status Register Byte 1, the CS pin must first be asserted and the opcode of 05h must be clocked into the device.
After the opcode has been clocked in, the device will begin outputting Status Register Byte 1 data on the SO pin during
every subsequent clock cycle. After the last bit (0) of Status Register Byte 1 has been clocked out, the sequence will
repeat itself starting again with bit 7 as long as the CS pin remains asserted and the clock pin is being pulsed. The data
in the Status Register is constantly being updated, so each repeating sequence will output new data. Deasserting the CS
pin will terminate the Read Status Register operation and put the SO pin into a high-impedance state. The CS pin can be
deasserted at any time and does not require that a full byte of data be read.
To read Status Register Byte 2, the CS pin must first be asserted and the opcode of 35h must be clocked into the device.
After the opcode has been clocked in, the device will begin outputting Status Register Byte 2 data on the SO pin during
every subsequent clock cycle. After the last bit (0) of Status Register Byte 2 has been clocked out, the sequence will
repeat itself starting again with bit 7 as long as the CS pin remains asserted and the clock pin is being pulsed. The data
in the Status Register is constantly being updated, so each repeating sequence will output new data. Deasserting the CS
pin will terminate the Read Status Register operation and put the SO pin into a high-impedance state. The CS pin can be
deasserted at any time and does not require that a full byte of data be read.
Notes: 1. Only bits 7 through 2 of the Status Register can be modified when using the Write Status Register command.
2.
R/W = Readable and writable
R = Readable only
Table 10-1. Status Register 1 Bit Assignments
Bit
(1)
Mnemonic Name Type
(2)
Description
7 SRP0 Status Register Protection
bit 0
R/W See Table 10-4 on Status Register Protection
6 SEC Block Protection R/W See Table 8-1 and Table 8-2 on Non-Volatile
Protection
5 TB Top or Bottom Protection R/W
4 BP2 Block Protection bit 2 R/W
3 BP1 Block Protection bit 1 R/W
2 BP0 Block Protection bit 0 R/W
1 WEL Write Enable Latch Status R 0 Device is not Write Enabled (default)
1 Device is Write Enabled
0 RDY/BSY Ready/Busy Status R 0 Device is ready
1 Device is busy with an internal operation
28AT25SF321B
DS-25SF321B–179B–6/2019
Figure 10-1. Read Status Register 1
Figure 10-2. Read Status Register 2
Table 10-3 shows the bit assignments for Status Register 3. This register can be read using the Status Register 3 Read
command (15h) and written using the Status Register 3 Write command (11h).
Table 10-2. Status Register 2 Bit Assignments
Bit
(1)
Name Type
(2)
Description
7 E_SUS Erase Suspend Status R
0 Erase operation is not suspended (default)
1 Erase operation is suspended
6 CMP Complement Block
Protection R/W 0 See table on Block Protection
5 LB3 Lock Security Register 3 R/W
0 Security Register page-3 is not locked (default)
1 Security Register page-3 cannot be erased/programmed
4 LB2 Lock Security Register 2 R/W
0 Security Register page-2 is not locked (default)
1 Security Register page-2 cannot be erased/programmed
3 LB1 Lock Security Register 1 R/W
0 Security Register page-1 is not locked (default)
1 Security Register page-1 cannot be erased/programmed
2 P_SUS Program Suspend
Status R
0 Program operation is not suspended (default)
1 Program operation is suspended
1 QE Quad Enable R/W
0 HOLD and WP function normally (default)
1 HOLD and WP are I/O pins
0 SRP1 Status Register Protect
bit 1 R/W See table on Status Register Protection
SCK
CS
SI
SO
MSB
2
3
1
0
0
0
0
0
0
1
0
1
6
7
5
4
10
11
9
8
12
21
22
17
20
19
18
15
16
13
14
23
24
28
29
27
26
25
30
23&2'(
MSB
MSB
D
D
D
D
D
D
D
D
D
D
MSB
D
D
D
D
D
D
D
D
D
D
D
D
D
D
67$7865(*,67(5BYTE 1
HIGH-IMPEDANCE
67$7865(*,67(567$7865(*,67(5BYTE 1 BYTE 1
SCK
CS
SI
SO
MSB
2
3
1
0
0
0
0
1
0
1
6
7
5
4
10
11
9
8
12
21
22
17
20
19
18
15
16
13
14
23
24
28
29
27
26
25
30
23&2'(
MSB
MSB
D
D
D
D
D
D
D
D
D
D
MSB
D
D
D
D
D
D
D
D
D
D
D
D
D
D
67$7865(*,67(5BYTE 2
HIGH-IMPEDANCE
67$7865(*,67(567$7865(*,67(5BYTE 2 BYTE 2
29AT25SF321B
DS-25SF321B–179B–6/2019
10.1.1 SRP1, SRP0 Bits
The SRP1 and SRP0 bits control whether the Status Register can be modified. The state of the
WP
pin along with the
values of the SRP1 and SRP0 determine if the device is software protected, hardware protected, or permanently
protected as shown in Table 10-4.
10.1.2 CMP, SEC, TB, BP2, BP1, BP0 Bits
The CMP, SEC, TB, BP2, BP1, and BP0 bits control which portions of the array are protected from erase and program
operations (see Table 8-1 and Table 8-2).
The CMP bit complements the effect of the other bits.
The SEC bit selects between large and small block size protection.
The TB bit selects between top of the array or bottom of the array protection.
The BP2, BP1, and BP0 bits determine how much of the array is protected.
10.1.3 WEL Bit
The WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit is in the logical “0” state,
the device will not accept any Byte/Page Program, erase, Program Security Register, Erase Security Register, or Write
Table 10-3. Status Register 3 Bit Assignments
Bit Mnemonic Name Type Description
7 Res Reserved R/W 0 Reserved bit.
6:5 DRV[1:0] Drive Strength R/W 11
Drive level. The DRV1 and DRV0 bits are used to determine
the output driver strength during read operations. A setting
of 2’b11 allows the drive strength to be set by hardware
based on the VCC level. Four drive settings are supported.
This field is encoded as follows:
11: Auto (7 pF based on VCC level)
10: 50% (15 pF)
01: 75% (22 pF)
00: 100% (30 pF)
4:0 Res Reserved R/W 0 Reserved bit.
Table 10-4. Status Register Protection Table
SRP1 SRP0 WP Status Register Description
0 0 X Software Protected
The Status Register can be written to after a Write Enable
instruction, WEL = 1.(Factory Default)
0 1 0 Hardware Protected WP
= 0, the Status Register is locked and cannot be written.
0 1 1 Hardware
Unprotected
WP
= 1, the Status Register is unlocked and can be written
to after a Write Enable instruction, WEL = 1.
1 0 X Power Supply Lock-
Down
(1)
Status Register is protected and cannot be written to again
until the next Power-Down, Power-Up cycle.
1. When SRP1, SRP0 = (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to the (0, 0) state.
30AT25SF321B
DS-25SF321B–179B–6/2019
Status Register commands. The WEL bit defaults to the logical “0” state after a device power-up or reset operation. In
addition, the WEL bit will be reset to the logical “0” state automatically under the following conditions:
Write Disable operation completes successfully
Write Status Register operation completes successfully or aborts
Program Security Register operation completes successfully or aborts
Erase Security Register operation completes successfully or aborts
Byte/Page Program operation completes successfully or aborts
Block Erase operation completes successfully or aborts
Chip Erase operation completes successfully or aborts
If the WEL bit is in the logical “1” state, it will not be reset to a logical “0” if an operation aborts due to an incomplete or
unrecognized opcode being clocked into the device before the CS pin is deasserted. In order for the WEL bit to be reset
when an operation aborts prematurely, the entire opcode for a Byte/Page Program, erase, Program Security Register,
Erase Security Register, or Write Status Register command must have been clocked into the device.
10.1.4 RDY/BSY Bit
The RDY/BSY bit is used to determine whether or not an internal operation, such as a program or erase, is in progress.
To poll the RDY/BSY bit to detect the completion of a program or erase cycle, new Status Register data must be
continually clocked out of the device until the state of the RDY/BSY bit changes from a logical “1” to a logical “0”.
10.1.5 LB3, LB2, LB1 Bits
The LB3, LB2, and LB1 bits are used to determine if any of the three Security Register pages are locked.
The LB3 bit is in the logical “1” state if Security Register page-2 is locked and cannot be erased or programmed.
The LB2 bit is in the logical “1” state if Security Register page-1 is locked and cannot be erased or programmed.
The LB1 bit is in the logical “1” state if Security Register page-0 is locked and cannot be erased or programmed.
10.1.6 E_SUS Bit
This bit is set and cleared by hardware and indicates the status of an erase operation. This bit is encoded as follows:
0: Erase operation is not suspended (default)
1: Erase operation is suspended
Hardware clears this bit once the condition that caused the erase suspend operation has been removed. Hardware
typically sets this bit when a Program/Erase Suspend (75h) command is executed, and clears the bit when a
Program/Erase Resume (7Ah) command is executed.
10.1.7 P_SUS Bit
This bit is set and cleared by hardware and indicates the status of an program operation. This bit is encoded as follows:
0: Program operation is not suspended (default)
1: Program operation is suspended
Hardware clears this bit once the condition that caused the program suspend operation has been removed. Hardware
typically sets this bit when a Program/Erase Suspend (75h) command is executed, and clears the bit when a
Program/Erase Resume (7Ah) command is executed.
10.1.8 QE Bit
The QE bit is used to determine if the device is in the Quad Enabled mode. If the QE bit is in the logical “1” state, then the
HOLD and
WP
pins functions as input/output pins similar to the SI and SO. If the QE bit is in the logical “0” state, then the
HOLD pin functions as an input only and the
WP
pin functions as an input only.
31AT25SF321B
DS-25SF321B–179B–6/2019
10.2 Write Status Register (01h)
The Write Status Register command is used to modify the Block Protection, Security Register Lock-down, Quad Enable,
and Status Register Protection. Before the Write Status Register command can be issued, the Write Enable command
must have been previously issued to set the WEL bit in the Status Register to a logical “1”.
The CS pin must be driven high after the eighth bit of the data byte has been latched in. If not, the Write Status Register
instruction is not executed. As soon as the CS pin is driven high, the self-timed Write Status Register cycle is initiated.
While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write
in Progress (WIP) bit. The WIP bit is 1 during the self-timed Write Status Register cycle, and 0 when it is completed.
When the cycle is completed, the Write Enable Latch is reset.
The Write Status Register instruction allows the user to change the values of the Block Protect (SEC, TB, BP2, BP1,
BP0) bits, to define the size of the area that is to be treated as read-only. The Write Status Register instruction also
allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits in accordance with the Write Protect
(WP) pin.
The Status Register Protect (SRP1 and SRP0) bits and Write Protect (/WP) pin allow the device to be put in the
hardware protected mode. The Write Status Register instruction is not executed once the hardware protected mode is
entered.
Figure 10-3. Write Status Register
.
Table 10-5. Write Status Register 1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SRPO SEC TB BP2 BP1 BP0 WEL RDY/BSY
Table 10-6.Write Status Register Byte 2
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
E_SUS CMP LB3 LB2 LB1 P_SUS QE SRP1
Table 10-7.Write Status Register Byte 3
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reserved DRV1 DRV0 Reserved Reserved Reserved Reserved Reserved
32AT25SF321B
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10.3 Write Enable for Volatile Status Register (50h)
The non-volatile Status Register bits can also be written to as volatile bits. During power up reset, the non-volatile Status
Register bits are copied to a volatile version of the Status Register that is used during device operation. This gives more
flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-
volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits.
To write the volatile version of the Status Register bits, the Write Enable for Volatile Status Register (50h) instruction
must be issued prior to each Write Status Registers (01h) instruction. Write Enable for Volatile Status Register instruction
will not set the Write Enable Latch bit. It is only valid for the next following Write Status Registers instruction, to change
the volatile Status Register bit values.
Figure 10-4. Write Enable for Volatile Status Register
11. Other Commands and Functions
The AT25SF321B supports three different commands to access device identification that indicates the manufacturer,
device type, and memory density. The returned data bytes provide information as shown in Table 11-1.
11.1 Read Manufacturer and Device ID (9Fh)
Identification information can be read from the device to enable systems to electronically query and identify the device
while it is in system.
Since not all Flash devices are capable of operating at very high clock frequencies, applications should be designed to
read the identification information from the devices at a reasonably low clock frequency to ensure all devices used in the
application can be identified properly. Once the identification process is complete, the application can increase the clock
frequency to accommodate specific Flash devices that are capable of operating at the higher clock frequencies.
To read the identification information, the CS pin must first be asserted and the opcode of 9Fh must be clocked into the
device. After the opcode has been clocked in, the device will begin outputting the identification data on the SO pin during
6&.&66,62
MSB
2
3
1
0
6
7
5
4
OPCODE
HIGH-IMPEDANCE
Table 11-1.Manufacturer and Device ID Information
Instruction Opcode
Dummy
Bytes
Manufacturer ID
(Byte #1)
Device ID
(Byte #2)
Device ID
(Byte #3)
Read Manufacturer and Device ID
9Fh 0 1Fh 87h 01h
Read ID (Legacy Command)
90h 3 1Fh 15h
Read ID (Dual I/O)
92h 3 1Fh 15h
Read ID (Quad I/O)
94h 3 1Fh 15h
Resume from Deep Power-Down and
Read Device ID
ABh 3 15h
33AT25SF321B
DS-25SF321B–179B–6/2019
the subsequent clock cycles. The first byte output is the Manufacturer ID followed by two bytes of Device ID information.
Deasserting the CS pin terminates the Manufacturer and Device ID read operation and puts the SO pin into a high-
impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.
Figure 11-1. Read Manufacturer and Device ID
Table 11-2. Manufacturer and Device ID Information
Byte Number Data Type Value
1 Manufacturer ID 1Fh
2 Device ID (Part 1) 87h
3 Device ID (Part 2) 01h
Table 11-3. Manufacturer and Device ID Details
Data Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Hex
Value Details
Manufacturer ID
JEDEC Assigned Code
1Fh JEDEC Code: 0001 1111 (1Fh for Adesto)
00011111
Device ID (Part 1)
Family Code Density Code
87h Family Code:100 (AT25SFxxx series)
Density Code: 00111 (32-Mbit)
10000111
Device ID (Part 2)
Sub Code Product Version Code
01h Sub Code: 000 (Standard series)
Product Version: 00001
00000001
SCK
CS
SI
SO
60
9Fh
87
OPCODE
1Fh 87h 01h
MANUFACTURER ID DEVICE ID
BYTE1
DEVICE ID
BYTE2
HIGH-IMPEDANCE
14 1615 22 2423 30 3231
Note: Each transition shown for SI and SO represents one byte (8 bits)
34AT25SF321B
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11.2 Read ID (Legacy Command) (90h)
Identification information can be read from the device to enable systems to electronically query and identify the device
while it is in system. The preferred method for doing so is the JEDEC standard “Read Manufacturer and Device ID (9Fh)”
method described in Section 11.1; however, the legacy Read ID command is supported on the AT25SF321B to enable
backwards compatibility to previous generation devices.
To read the identification information, the CS pin must first be asserted and the opcode of 90h must be clocked into the
device, followed by three dummy bytes. After the opcode has been clocked in followed by three dummy bytes, the device
will begin outputting the identification data on the SO pin during the subsequent clock cycles. The first byte output is the
Manufacturer ID of 1Fh followed by a single byte of data representing a device code of 15h. After the device code is
output, the sequence of bytes repeats.
Deasserting the CS pin will terminate the Read ID operation and put the SO pin into a high-impedance state. The CS pin
can be deasserted at any time and does not require that a full byte of data read.
Figure 11-2. Read ID (Legacy Command)
11.3 Dual I/O Read Manufacture ID/ Device ID (92h)
The Dual I/O Read Manufacturer/Device ID instruction is an alternative to the Release from Power-Down/Device
ID instruction that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by Dual I/O.
The instruction is initiated by driving the CS pin low and shifting the instruction code 92h followed by a 24-bit
address (A23 - A0) of 000000h. If the 24-bit address is initially set to 000001h, the Device ID is read first.
6&.&66,62
MSB
2
3
1
0
1
0
0
6
7
5
4
OPCODE
HIGH-IMPEDANCE
31 323029 38 393735 363433
X X X X X
'800<%<7(6
MSB
D D D D D D D D
'(9,&(,'
35AT25SF321B
DS-25SF321B–179B–6/2019
Figure 11-3. Dual I/O Read Manufacture ID/ Device ID Sequence Diagram
11.4 Quad I/O Read Manufacture ID / Device ID (94h)
The Quad I/O Read Manufacturer/Device ID instruction is an alternative to the Release from Power-Down/Device
ID instruction that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by quad I/O.
The instruction is initiated by driving the CS pin low and shifting the instruction code 94h followed by a 24-bit
address (A23 - A0) of 000000h and four dummy clocks. If the 24-bit address is initially set to 000001h, the Device
ID is read out first.
01234 5 6 7 8910 11 12 13 14 15 16 17 18 19 20 21 22 23
Instruction
92H 6 4 2 0 6420 6 4 2 06420
75317 5 3 1 7 5 3 1 7 5 31
A23-16 A15-8 A7-0 Dummy
23 24 25 26 27 28 29 30 31 40 41 42 43 44 45 46 47
6 4 20642064206420
75317 5 31117 75 5
3 3
/CS
SCLK
SI
(IO0)
SO
(IO1)
/CS
SCLK
SI
(IO0)
SO
(IO1)
MFR ID Device ID
MFR and Device ID
(repeat) MFR ID(repeat)
High_Z
High_Z
High_Z
Device ID(repeat)
32 39
36AT25SF321B
DS-25SF321B–179B–6/2019
Figure 11-4. Quad I/O Read Manufacture ID / Device ID Sequence Diagram
11.5 Deep Power-Down (B9h)
During normal operation, the device will be placed in the standby mode to consume less power as long as the CS pin
remains deasserted and no internal operation is in progress. The Deep Power-Down command offers the ability to place
the device into an even lower power consumption state called the Deep Power-Down mode.
When the device is in the Deep Power-Down mode, all commands including the Read Status Register command will be
ignored with the exception of the Resume from Deep Power-Down command. Since all commands will be ignored, the
mode can be used as an extra protection mechanism against program and erase operations.
Entering the Deep Power-Down mode is accomplished by simply asserting the CS pin, clocking in the opcode of B9h,
and then deasserting the CS pin. Any additional data clocked into the device after the opcode is ignored. When the CS
pin is deasserted, the device enters the Deep Power-Down mode.
The complete opcode must be clocked in before the CS pin is deasserted, and the CS pin must be deasserted on an byte
boundary (multiples of eight bits); otherwise, the device will abort the operation and return to the standby mode once the
CS pin is deasserted. In addition, the device will default to the standby mode after a power-cycle.
The Deep Power-Down command will be ignored if an internally self-timed operation such as a program or erase cycle is
in progress. The Deep Power-Down command must be reissued after the internally self-timed operation has been
completed in order for the device to enter the Deep Power-Down mode.
01234 5 6 7 8910 11 12 13 14 15 16 17 18 19 20 21 22 23
Instruction
94H 4 0 4 0 4040
51515 1 5 1
A23-16 A15-8 A7-0 dummy
23 24 25 26 27 28 29 30 31
/CS
SCLK
SI
(IO0)
SO
(IO1)
/CS
SCLK
SI
(IO0)
SO
(IO1)
High_Z
62626 2 6 2
WP
(IO2)
High_Z
73737 3 7 3
HOLD
(IO3)
High_Z
MFR ID
(repeat)
WP
(IO2)
HOLD
(IO3)
4040
5 1 5 1
6 2 6 2
7 3 7 3
dummy MFR ID Device ID
40 4 0404 0
51515 1 5 1
62626 2 6 2
7 3 737 3 7 3
DID ID
(repeat)
MFR ID
(repeat)
DID ID
(repeat)
37AT25SF321B
DS-25SF321B–179B–6/2019
Figure 11-5. Deep Power-Down
11.6 Resume from Deep Power-Down (ABh)
In order to exit the Deep Power-Down mode and resume normal device operation, the Resume from Deep Power-Down
command must be issued. The Resume from Deep Power-Down command is the only command that the device will
recognize while in the Deep Power-Down mode.
To resume from the Deep Power-Down mode, the CS pin must first be asserted and the opcode of ABh must be clocked
into the device. Any additional data clocked into the device after the opcode will be ignored. When the CS pin is
deasserted, the device will exit the Deep Power-Down mode and return to the standby mode. After the device has
returned to the standby mode, normal command operations such as Read Array can be resumed.
If the complete opcode is not clocked in before the CS pin is deasserted, or if the CS pin is not deasserted on an byte
boundary (multiples of eight bits), then the device aborts the operation and returns to the Deep Power-Down mode.
Figure 11-6. Resume from Deep Power-Down
11.6.1 Resume from Deep Power-Down and Read Device ID (ABh)
The Resume from Deep Power-Down command can also be used to read the Device ID.
When used to release the device from the Power-Down state and obtain the Device ID, the CS pin must first be asserted
and opcode of ABh must be clocked into the device, followed by 3 dummy bytes. The Device ID bits are then shifted out
on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 11-7. This command only outputs a
single byte Device ID. The Device ID value for the AT25SF321B is listed in Table 11-1.
6&.&66,6206%,&&23&2'(+,*+,03('$1&(6WDQGE\0RGH&XUUHQW$FWLYH&XUUHQW'HHS3RZHU'RZQ0RGH&XUUHQWW('3'
6&.&66,62
MSB
,&&
2
3
1
0
1
0
1
0
1
0
1
1
6
7
5
4
OPCODE
HIGH-IMPEDANCE
Deep Power-Down Mode Current
Active Current
Standby Mode Current
tRDPD
38AT25SF321B
DS-25SF321B–179B–6/2019
After the last bit (0) of the Device ID has been clocked out, the sequence repeats itself starting again with bit 7 as long as
the CS pin remains asserted and the SCK pin is being pulsed. After CS is deasserted it must remain high until new
commands can be received.
The same instruction may be used to read device ID when not in power down. In that case, CS does not have to remain
high remain after it is deasserted.
Figure 11-7. Resume from Deep Power-Down and Read Device ID
11.7 Hold Function
The HOLD pin is used to pause the serial communication with the device without having to stop or reset the clock
sequence. The Hold mode, however, does not have an affect on any internally self-timed operations such as a program
or erase cycle. Therefore, if an erase cycle is in progress, asserting the HOLD pin will not pause the operation, and the
erase cycle will continue until it is finished.
If the QE bit value in the Status Register has been set to logical “1”, then the HOLD pin does not function as a control pin.
The HOLD pin will function as an output for Quad-Output Read and input/output for Quad-I/O Read.
The Hold mode can only be entered while the CS pin is asserted. The Hold mode is activated simply by asserting the
HOLD pin during the SCK low pulse. If the HOLD pin is asserted during the SCK high pulse, then the Hold mode won’t be
started until the beginning of the next SCK low pulse. The device will remain in the Hold mode as long as the HOLD pin
and CS pin are asserted.
While in the Hold mode, the SO pin will be in a high-impedance state. In addition, both the SI pin and the SCK pin will be
ignored. The WP pin, however, can still be asserted or deasserted while in the Hold mode.
To end the Hold mode and resume serial communication, the HOLD pin must be deasserted during the SCK low pulse. If
the HOLD pin is deasserted during the SCK high pulse, then the Hold mode won’t end until the beginning of the next SCK
low pulse.
If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been started will be
aborted, and the device will reset the WEL bit in the Status Register back to the logical “0” state.
6&.&66,62
MSB
,&&
2
3
1
0
1
0
1
0
1
0
1
1
6
7
5
4
OPCODE
HIGH-IMPEDANCE
'HHS3RZHU'RZQ0RGH&XUUHQW
Active Current
31 323029 38 393735 363433
X X X X X
'800<%<7(6W5'32
MSB
D D D D D D D D
'(9,&(,'6WDQGE\0RGH&XUUHQW
39AT25SF321B
DS-25SF321B–179B–6/2019
12. Electrical Specifications
12.1 Absolute Maximum Ratings*
Temperature under Bias. . . . . . . . . . . . . -55°C to +125°C
*Notice: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other
conditions beyond those indicated in the operational
sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect device reliability.
Storage Temperature . . . . . . . . . . . . . . . -65°C to +150°C
All Input Voltages (including NC Pins)
with Respect to Ground . . . . . . . . . . . . . . -0.6V to +4.1V
All Output Voltages
with Respect to Ground . . . . . . . . . . -0.6V to V
CC
+ 0.5V
12.2 DC and AC Operating Range
Parameter Condition Value
Operating Temperature (Case) Industrial -40°C to 85°C
V
CC
Power Supply 2.7V to 3.6V
12.3 DC Characteristics
Symbol Parameter Condition
2.7V to 3.6V
UnitsMin Typ Max
I
DPD
Deep Power-Down Current CS, HOLD, WP = V
IH
All inputs at CMOS levels 2 5 µA
I
SB
Standby Current CS, HOLD, WP = V
IH
All inputs at CMOS levels 13 25 µA
I
CC1
Active Current, Read (03h,
0Bh) Operation
f = 20 MHz; I
OUT
= 0mA 3 6 mA
f = 50 MHz; I
OUT
= 0mA 4 7 mA
f = 85 MHz; I
OUT
= 0mA 5 8 mA
I
CC2
Active Current,(3Bh, BBh
Read Operation (Dual)
f = 50 MHz; I
OUT
= 0mA 5 8 mA
f = 85 MHz and 108 MHz;
I
OUT
= 0mA 6 9 mA
I
CC3
Active Current,(6Bh, EBh
Read Operation (Quad)
f = 50 MHz; I
OUT
= 0mA 6 10 mA
f = 85 MHz and 108 MHz;
I
OUT
= 0mA 8 12 mA
I
CC4
Active Current,
Program Operation CS = V
CC
15 mA
40AT25SF321B
DS-25SF321B–179B–6/2019
I
CC5
Active Current,
Erase Operation CS = V
CC
12 mA
I
LI
Input Load Current All inputs at CMOS levels ±2 µA
I
LO
Output Leakage Current All inputs at CMOS levels ±2 µA
V
IL
Input Low Voltage -0.5 V
CC
x 0.2 V
V
IH
Input High Voltage V
CC
x 0.8 V
CC
+ 0.4 V
V
OL
Output Low Voltage I
OL
= 100 µA 0.4 V
V
OH
Output High Voltage I
OH
= -100 µA V
CC
-
0.2V V
12.3 DC Characteristics (Continued)
Symbol Parameter Condition
2.7V to 3.6V
UnitsMin Typ Max
12.4 AC Characteristics - Maximum Clock Frequencies
Symbol Parameter
2.7V to 3.6V
UnitsMin Typ Max
f
CLK
Maximum Clock Frequency for opcodes BBh, E7h, and EBh 108 MHz
f
CLK1
Maximum Clock Frequency for opcodes 0Bh, 3Bh, and 6Bh 85 MHz
f
CLK2
Maximum Clock Frequency for 03h opcode 55 MHz
12.5 AC Characteristics - All Other Parameters
Symbol Parameter
2.7V to 3.6V
Units
Min Typ Max
t
CLKH
Clock High Time 4 ns
t
CLKL
Clock Low Time 4 ns
t
CLKR
Clock Rise Time, Peak-to-Peak (Slew Rate) 0.1 ns/V
t
CLK
Clock Fall Time, Peak-to-Peak (Slew Rate) 0.1 ns/V
t
CSH
Chip Select High Time 20 ns
t
CSLS
Chip Select Low Setup Time (relative to Clock) 5 ns
t
CSLH
Chip Select Low Hold Time (relative to Clock) 5 ns
t
CSHS
Chip Select High Setup Time (relative to Clock) 5 ns
t
CSHH
Chip Select High Hold Time (relative to Clock) 5 ns
41AT25SF321B
DS-25SF321B–179B–6/2019
t
DS
Data In Setup Time 2 ns
t
DH
Data In Hold Time 2 ns
t
DIS
Output Disable Time 6 ns
t
V
Output Valid Time 7 ns
t
OH
Output Hold Time 0 ns
t
HLS
HOLD Low Setup Time (relative to Clock) 5 ns
t
HLH
HOLD Low Hold Time (relative to Clock) 5 ns
t
HHS
HOLD High Setup Time (relative to Clock) 5 ns
t
HHH
HOLD High Hold Time (relative to Clock) 5 ns
t
HLQZ
HOLD Low to Output High-Z 6 ns
t
HHQZ
HOLD High to Output High-Z 6 ns
t
WPS
Write Protect Setup Time 20 ns
t
WPH
Write Protect Hold Time 100 ns
t
EDPD
Chip Select High to Deep Power-Down 20 µs
t
RDPD
Chip Select High to Standby Mode 20 µs
t
RDPO
Resume Deep Power-Down, CS High to ID 20 µs
12.5 AC Characteristics - All Other Parameters (Continued)
Symbol Parameter
2.7V to 3.6V
Units
Min Typ Max
12.6 Program and Erase Characteristics
Symbol
2.7V to 3.6V
Parameter Condition Min Typ Max Units
t
PP
Page Program Time (256 Bytes) 0.6 3.0 ms
t
BP1
First Byte Program Time 30 50 µs
t
BP2
Second Byte Program Time 2.5 12 µs
t
BLKE
Block Erase Time
4 Kbytes 50 300
ms32 Kbytes 150 1600
64 Kbytes 250 2000
t
CHPE
Chip Erase Time 15 30 sec
t
WRSR
Write Status Register Time 5 30 ms
12.7 Power Up Conditions
Symbol Parameter Min Max Units
t
VCSL
Minimum V
CC
to Chip Select Low Time 70 µs
42AT25SF321B
DS-25SF321B–179B–6/2019
12.8 Input Test Waveforms and Measurement Levels
12.9 Output Test Load
AC
DRIVING
LEVELS
AC
MEASUREMENT
LEVEL
0.1VCC
VCC/2
0.9VCC
tR, tF < 2 ns (10% to 90%)
Device
Under
Test
30pF
43AT25SF321B
DS-25SF321B–179B–6/2019
13. AC Waveforms
Figure 13-1. Serial Input Timing
Figure 13-2. Serial Output Timing
Figure 13-3. WP Timing for Write Status Register Command When BPL = 1
&66,6&.6206%+,*+,03('$1&(06%/6%W&6/6W&/.+W&/./W&6+6W&6++W'6W'+W&6/+W&6+
&66,6&.62W9W&/.+W&/./W',6W9W2+
WP
SI
SCK
SO
000
HIGH-IMPEDANCE
MSBX
tWPS tWPH
CS
LSB OF
WRITE STATUS REGISTER
DATA BYTE
MSB OF
WRITE STATUS REGISTER
OPCODE
MSB OF
NEXT OPCODE
44AT25SF321B
DS-25SF321B–179B–6/2019
Figure 13-4. HOLD Timing – Serial Input
Figure 13-5. HOLD Timing – Serial Output
CS
SI
SCK
SO
tHHH tHLS
tHLH tHHS
HOLD
HIGH-IMPEDANCE
CS
SI
SCK
SO
tHHH tHLS
tHLQZ
tHLH tHHS
HOLD
tHHQX
45AT25SF321B
DS-25SF321B–179B–6/2019
14. Ordering Information
Ordering Code
(1)
1.
The shipping carrier option code is not marked on the devices.
Package Operating Voltage
Max. Freq.
(MHz) Operation Range
AT25SF321B-SSHB-B
8S1
2.7V to 3.6V 108 MHz Industrial
(-40°C to +85°C)
AT25SF321B-SSHB-T
AT25SF321B-SHB-B
8S2
AT25SF321B-SHB-T
AT25SF321B-MHB-T 8MA1
Die Wafer Form
(2)
2. Contact Adesto for Die Wafer Form sales information.
DWF
AT 25SF 321 B - S H B - T
Designator
Product Family
Device Density
321 = 32 Mbit
Generation
Shipping Carrier
T = Tape and Reel
Operating Voltage
B = 2.7V - 3.6V
Device Grade
H = Green NiPdAu lead frame
Package Options
S = 8-lead, SOP 0.208” (8S2)
M = 8-pad 5 x 6 UDFN (8MA1)
(-40
o
C to 85
o
C)
B = Bulk (tube)
SS = 8-lead, SOP 0.150” (8S1)
Package Type
8S1 8-lead, 0.150" Narrow, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
8S2 8-lead, 0.208" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
8MA1 8-pad (5 x 6 x 0.6mm body), Thermally Enhanced Plastic Ultra-thin Dual Flat No-lead (UDFN)
DWF Die in Wafer Form
46AT25SF321B
DS-25SF321B–179B–6/2019
15. Packaging Information
15.1 8S1 – 0.150” Narrow JEDEC SOIC
DRAWING NO. REV. TITLE GPC
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A1 0.10 – 0.25
A 1.35 – 1.75
b 0.31 – 0.51
C 0.17 – 0.25
D 4.80 – 5.05
E1 3.81 – 3.99
E 5.79 – 6.20
e 1.27 BSC
L 0.40 – 1.27
Ø 0° – 8°
Ø
E
1
N
TOP VIEW
C
E1
END VIEW
A
b
L
A1
e
D
SIDE VIEW
Package Drawing Contact:
contact@adestotech.com
8S1 G
8/20/14
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
8S1, 8-lead (0.150” Wide Body), Plastic Gull
Wing Small Outline (JEDEC SOIC) SWB
8S1, 8-lead (0.150” Narrow Body), Plastic Gull
Wing Small Outline Package (JEDEC SOIC)
47AT25SF321B
DS-25SF321B–179B–6/2019
15.2 8S2 – 8-lead, 0.208” Wide EIAJ SOIC
TITLE DRAWING NO. GPC REV.
Package Drawing Contact:
contact@adestotech.com
®
8S2STN F
8S2, 8-lead, 0.208” Body, Plastic Small
Outline Package (EIAJ)
4/15/08
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
2. Mismatch of the upper and lower dies and resin burrs aren't included.
3. Determines the true geometric position.
4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.
A 1.70 2.16
A1 0.05 0.25
b 0.35 0.48 4
C 0.15 0.35 4
D 5.13 5.35
E1 5.18 5.40 2
E 7.70 8.26
L 0.51 0.85
θ 0° 8°
e 1.27 BSC 3
θ
1
N
E
TOP VIEW
C
E1
END VIEW
A
b
L
A1
e
D
SIDE VIEW
48AT25SF321B
DS-25SF321B–179B–6/2019
15.3 8MA1 – UDFN
TITLE DRAWING NO.GPC REV.
Package Drawing Contact:
contact@adestotech.com
®
8MA1YFG D
8MA1, 8-pad (5 x 6 x 0.6 mm Body), Thermally
Enhanced Plastic Ultra Thin Dual Flat No Lead
Package (UDFN)
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOT E
A 0.45 0.55 0.60
A1 0.00 0.02 0.05
b 0.35 0.40 0.48
C 0.152 REF
D 4.90 5.00 5.10
D2 3.80 4.00 4.20
E 5.90 6.00 6.10
E2 3.20 3.40 3.60
e 1.27
L 0.50 0.60 0.75
y 0.00 – 0.08
K 0.20 – –
4/15/08
Pin 1 ID
TOP VIEW
E
D
A1
A
SIDE VIEW
y
C
BOTTOM VIEW
E2
D2
L
b
e
1
2
3
4
8
7
6
5
Pin #1 Notch
(0.20 R)
0.45
K
Pin #1
Chamfer
(C 0.35)
Option A
(Option B)
49AT25SF321B
DS-25SF321B–179B–6/2019
16. Revision History
Revision Number Date Tasks
A 5/2019 Initial release of AT25SF321B data sheet.
B 6/2019 Revision B of AT25SF321B data sheet.
Change maximum frequency from 85 MHz to 108 MHz.
Update fclk, fclk1, and fclk2 parameters in Table 12.4.
Update maximum frequency in Ordering Code table.
Corporate Office
California | USA
Adesto Headquarters
3600 Peterson Way
Santa Clara, CA 95054
Phone: (+1) 408.400.0578
Email: contact@adestotech.com
© 2019 Adesto Technologies. All rights reserved. DS-25SF321B–179B–6/2019
Adesto, the Adesto logo, CBRAM and DataFlash are trademarks or registered trademarks of Adesto Technologies Corporation in the United States and other countries. Other company, product, and
service names may be trademarks or service marks of others. Adesto products are covered by one or more patents listed at http://www.adestotech.com/patents.
Disclaimer: Adesto Technologies Corporation (“Adesto”) makes no warranties of any kind, other than those expressly set forth in Adesto’s Terms and Conditions of Sale at
http://www.adestotech.com/terms-conditions. Adesto assumes no responsibility or obligations for any errors which may appear in this document, reserves the right to change devices or specifications
herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Adesto are granted by Adesto
herewith or in connection with the sale of Adesto products, expressly or by implication. Adesto’s products are not authorized for use in medical applications (including, but not limited to, life support systems
and other medical equipment), weapons, military use, avionics, satellites, nuclear applications, or other high risk applications (e.g., applications that, if they fail, can be reasonably expected to result in
personal injury or death) or automotive applications, without the express prior written consent of Adesto.
