Rev.2.00, Oct.24.2003, page 1 of 19
HN 58X2408FPIAG/HN58X2416FP IAG
HN 58X2432FPIAG/HN58X2464FP IAG
Two-wire serial interface
8k EEP ROM (1-kword × 8-bit)/16k EEPR OM (2-kword × 8-bit)
32 k EEP ROM (4-kword × 8-bit)/64k EEPROM (8-kword × 8-bit)
REJ03C 0134-02 00Z
(Previous ADE-203-1262A (Z) Rev. 1.0)
Rev. 2.00
Oct. 24, 2003
Description
HN58X2 4xxFPIAG series are two-wire serial interface EEPRO M (E lectrically Erasable and Programm able
ROM). They realize high speed, low power consumptio n and a high level of reliability by employing
advanced MN OS memory technology a nd C M OS process and low voltag e circuitry tec hnology. They also
have a 32-byte page programm ing function to make t heir w rite operation faster.
Features
• Single s upply: 1.8 V to 5.5 V
• Two-wire seri al interface (I2CTM serial bus*1)
• Clock frequency: 400 kHz
• Power dis si pat ion:
Standby: 3 µA (max)
Active (Read ): 1 mA (m ax)
Active (Write): 3 mA (max)
• Automa tic page write: 32-byte/page
• Wri te cycle tim e: 10 ms (2.7 V to 5.5 V)/15ms (1.8 V to 2.7 V)
• Endurance: 105 Cycles (Page write mode)
• Data retention: 10 Yea rs
• Small size packages: SOP-8pin
• Shipping tape and reel: 2,500 IC/reel
• Temperature range: −40 t o +85°C
• There are also lead free products.
Note: 1. I2C is a trademark of Philips Corporation.
HN58X240 8/HN58X2416/HN58X2432 /HN58X2464FPIAG
Rev.2.00, Oct.24.2003, page 2 of 19
Ordering Inform ation
Type No. Internal organization Operating volta ge Frequenc y Package
HN58X2408FPIAG 8k bit (1024 × 8-bit) 1.8 V to 5.5 V 400 kHz 150 mil 8-pin plastic S OP
HN58X2416FPIAG 16k bit (2048 × 8-bit) (FP-8DB)
HN58X2432FPIAG 32k bit (4096 × 8-bit)
HN58X2464FPIAG 64k bit (8192 × 8-bit)
HN58X2408FPIAGE 8k bit (1024 × 8-bit) 1.8 V to 5.5 V 400 kHz 150 mil 8-pin plastic S OP
HN58X2416FPIAGE 16k bit (2048 × 8-bit) (FP-8DBV)
HN58X2432FPIAGE 32k bit (4096 × 8-bit) Lead free
HN58X2464FPIAGE 64k bit (8192 × 8-bit)
Pin Arrangem ent
1
2
3
4
8
7
6
5
A0
A1
A2
V
SS
V
CC
WP
SCL
SDA
(Top view)
8-pin SOP
Pin Description
Pin name Function
A0 to A2 Device address
SCL Serial clock input
SDA Serial data input/output
WP Write protect
VCC Power supply
VSS Ground
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Rev.2.00, Oct.24.2003, page 3 of 19
Block Diagram
Control
logic
High voltage generator
Address generator
X decoderY decoder
Memory array
Y-select & Sense amp.
Serial-parallel converter
V
CC
V
SS
WP
A0, A1, A2
SCL
SDA
Absolute Maximum Ratings
Parameter Symbol Value Unit
Supply voltage relative to VSS V
CC −0.6 to +7.0 V
Input voltage relative to VSS Vin
−0.5*2 to +7.0*3 V
Operating tem perature range*1 Topr
−40 to +85 °C
Storage temperature range Tstg −65 to +125 °C
Notes: 1. Including electrical characteristics and data retention.
2. Vin (min): −3.0 V for pulse w idth ≤ 50 ns.
3. Should not exceed VCC + 1.0 V.
DC Operating Conditions
Parameter Symbol Min Typ Max Unit
Supply voltage VCC 1.8 5.5 V
V
SS 0 0 0 V
Input high voltage VIH V
CC × 0.7 V
CC + 1.0 V
Input low voltage VIL −0.3*1 V
CC × 0.3 V
Operating tem perature Top r −40 +85
°C
Note: 1. VIL (min): −1.0 V for pulse width ≤ 50 ns.
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Rev.2.00, Oct.24.2003, page 4 of 19
DC Characteristics (Ta = −
−−
−40 to +85°
°°
°C, VCC = 1.8 V to 5.5 V)
Parameter Symbol Min Typ Max Unit Test conditions
Input leakage current ILI 2.0
µA VCC = 5.5 V, Vin = 0 to 5.5 V
Output leakage current ILO 2.0
µA VCC = 5.5 V, Vout = 0 to 5.5 V
Standby VCC current ISB 1.0 3.0
µA Vin = VSS or VCC
Read VCC curren t ICC1 1.0 mA VCC = 5.5 V, Read at 400 kHz
Write VCC current ICC2 3.0 mA VCC = 5.5 V, Write at 400 kHz
Output low voltage VOL2 0.4 V VCC = 4.5 to 5.5 V, IOL = 1.6 mA
VCC = 2.7 to 4.5 V, IOL = 0.8 mA
VCC = 1.8 to 2.7 V, IOL = 0.4 mA
V
OL1 0.2 V VCC = 1.8 to 2.7 V, IOL = 0.2 m A
Capacitance (Ta = +25°
°°
°C, f = 1 MHz)
Parameter
Symbol
Min
Typ
Max
Unit Test
conditions
Input capacitance (A0 to A2, SCL, WP) Cin *1 6.0 pF Vin = 0 V
Output capacitance (S DA) CI/O*1 6.0 pF Vout = 0 V
Note: 1. This parameter is sampled and not 100% tested.
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Rev.2.00, Oct.24.2003, page 5 of 19
AC Characteristics (Ta = −
−−
−40 to +85°
°°
°C, VCC = 1.8 to 5.5 V)
Test C on d ition s
• Input pules levels :
VIL = 0.2 × V CC
VIH = 0.8 × VCC
• Input rise and fall time: ≤ 20 ns
• Input and output timing reference levels : 0.5 × VCC
• Output load: TTL Gate + 100 pF
Parameter Symbol Min Typ Max Unit Notes
Clock frequency fSCL 400 kHz
Clock pulse width low tLOW 1200
ns
Clock pulse width high tHIGH 600 ns
Noise suppression time tI 50 ns 1
Access tim e tAA 100
900 ns
Bus free time for next mode tBUF 1200
ns
Start hold time tHD.STA 600 ns
Start setup time tSU.STA 600 ns
Data in hold time tHD.DAT 0 ns
Data in setup time tSU.DAT 100 ns
Input rise time tR 300 ns 1
Input fall time tF 300 ns 1
Stop setup time tSU.STO 600 ns
Data out hold time tDH 50 ns
Write cycle time VCC = 2.7 V to 5.5 V tWC 10 ms 2
V
CC = 1.8 V to 2.7 V tWC 15 ms 2
Notes: 1. This parameter is sampled and not 100% tested.
2. tWC is the time from a stop condition to the end of internally controlled write cycle.
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Rev.2.00, Oct.24.2003, page 6 of 19
Timing Waveforms
Bus Ti ming
tF
1/fSCL
tHIGH
tSU.STA tHD.STA tHD.DAT tSU.DAT tSU.STO
tBUF
tDH
tAA
tLOW tR
SCL
SDA
(in)
SDA
(out)
Write Cycle Timing
SCL
SDA D0 in
Write data ACK
(Address (n))
t
WC
(Internally controlled)
Stop condition Start condition
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Rev.2.00, Oct.24.2003, page 7 of 19
Pin Function
Serial Clock (S CL)
The SC L pin is used t o control se rial input/output data tim ing. The S C L input is us ed to posit ive edge
clock data into EEPROM device and negative edge clock data out of each device. Maximum clock rate is
400 kHz.
Serial Input/Output Data (SDA)
The SDA pin is bidirectional for serial data transfer. The SDA pin needs to be pulled up by resistor as that
pin is open-drain driven structure. Use proper resistor value for your system by consi dering V OL, IOL and
the SDA pin ca pacitance. Except for a start condition and a stop condit ion whi ch w il l be disc uss e d later,
the SDA transition needs to be completed during the SCL low period.
Data Validity (SDA data change timing wav eform)
SCL
SDA
Data
change Data
change
Note: High-to-low and low-to-high change of SDA should be done during the SCL low period.
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Rev.2.00, Oct.24.2003, page 8 of 19
Device Address (A0, A1, A2)
Eight devices can be wired for one common data bus line as maximum. Device address pins are used to
distinguish each device and device address pins s hould be connected to V CC or VSS. When device addres s
code provided from SDA pin matches correspondi ng hard-w ired device addres s pins A0 to A2, that one
device can be activated. As for 8k to 16k EEPROM, whole or som e device address pi ns don't need to be
fixed since device address code provided from the SDA pin is used as memor y address signal.
Pin Connections for A0 to A2
Pin connection
Memory size M ax con nect
number
A2
A1
A0
Notes
8k bit 2 VCC/VSS*1 ×*2 × Use A0, A1 for memory address a8 and a9
16k bit 1 × × × Use A0, A1, A2 for memory address a8, a9 and
a10
32k bit 8 VCC/VSS V
CC/VSS V
CC/VSS
64k bit 8 VCC/VSS V
CC/VSS V
CC/VSS
Notes: 1. “VCC/VSS” means that device address pin should be connected to VCC or VSS.
2. × = Don’t care (Open is also approval.)
Write Protect (WP)
When the Write Protect pin (WP) is high, the write protection feature is enabled and operates as shown in
the following table. W hen the WP is low , write operation for all memory arrays are allowed . The read
operation is always act ivated irrespective of the W P pi n status . W P s hould be fixed high or low during
operations since WP does not provide a latch function.
Write Protect Area
Write protect area
WP pin
status 8k bit 16k bit 32k bit 64k bit
VIH Upper 1/2 (4k bit) Upper 1/2 (8k bit) Upper 1/4 (8k bit) Upper 1/4 (16k bit)
VIL Normal read/write operation
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Rev.2.00, Oct.24.2003, page 9 of 19
Functional Description
Start Condition
A high-to-low transition of the SDA with the SCL high is needed in order to start read, write operation (See
start condition and stop condition).
Stop Condition
A low-t o-high trans it ion of the SDA with the SCL hi gh is a stop condi tio n. The stand-by operation start s
after a read sequence by a stop condition. In the case of write operation, a st op condition terminates the
write data inputs and place the device in a internally-timed write cycle to the memories. After the
internally-timed write cycle which is specified as tWC, the device ent ers a standby mo de (See write cycle
timing).
Start Condition and Stop Condition
SCL
SDA
(in)
Stop conditionStart condition
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Rev.2.00, Oct.24.2003, page 10 of 19
Acknowledge
All addresses and data words are serially transmitted to and from in 8-bit w ords. The receiver sends a zero
to acknowledge that it has received each word. This happens during ninth clock cycle. The transmitter
keeps bus open to receive acknowledgme nt from the receiver at the ninth clock. In the write operation,
EEPROM sends a zero to acknowledge after receiving every 8-bit words. In the read operation, EEPROM
sends a zero to acknowl edge after receiving the devi ce address word. After send ing read data, the
EEPROM wai ts acknowledgment by keeping bus open. If the EEPRO M receives zero as an acknowledge,
it sends read data of next address. If the EEPROM receives acknow ledg me nt "1" (no acknowle dgm ent)
and a following stop cond ition, it stops the read operation and ente rs a stand-by m ode. If the EEPR O M
receives neither acknowledgment "0" nor a stop condition, the EEPR OM keeps bus open without se nding
read data.
Acknowledge Timing Waveform
SCL
SDA IN
SDA OUT
12 89
Acknowledge
out
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Rev.2.00, Oct.24.2003, page 11 of 19
Device Addressing
The EEPR O M device requires an 8-bit device address word following a start condition to enable the chip
for a read or a write operation. The device address word consists of 4-bit device code, 3-bit device address
code and 1-bit read/write(R/ W) code. The most significant 4-bit of the device address word are used to
distinguish device type and this EEPROM uses “1010” fixed code. The device address word is followed
by the 3-bit device address code in the order of A2, A1, A0. The device address code select s one device
out of all devices which are connected to the bus. This means that the device is selected if the inputted 3-
bit device address code is equal to the corresponding hard-wired A2-A0 pin status. As for the 8kbit and
16kbit EEP R O Ms, whole or some bits of their device address code m ay be use d as the mem ory addres s
bits. For example, A0 and A1 are used as a8 and a9 for the 8kbit. The 16kbit doesn't use the device
address code instead al l 3 bits are used as the mem ory addres s bits a8, a9 and a10. The eighth bit of the
device address word is the read/write(R/W) bit. A write operation is initiated if this bit is low and a read
operation is initiated if this bit is high. Upon a compare of the device address word, the EEP ROM enters
the read or write operation after outputting the zero as an acknowl edge. The EEP ROM turns to a stand-by
state if the device code is not “1010” or device address code doesn’t coincide with st atus of the correspond
hard-wired device address pins A 0 to A2.
Device Address Word
Device address word (8-bit)
Device code (fixed) Device address code*1 R/W code*2
32k, 64k 1 0 1 0 A2 A1 A0 R/W
8k 1 0 1 0 A2 a9 a8 R/W
16k 1 0 1 0 a10 a9 a8 R/W
Notes: 1. A2 to A0 are device address and a10 to a8 are memory address.
2. R/W=“1” is read and R/W = “0” is write.
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Rev.2.00, Oct.24.2003, page 12 of 19
Write Op erations
Byte Write:
A write operation requires an 8-bit device address word with R/W = “0”. Then the EEPROM s ends
acknowledgm en t "0" at the ninth clock cycle. After these, the 8kbit to 16kbit EEPR O Ms receive 8-bit
memory address word, on the other hand the 32kbit and 64kbit EEPROMs receive 2 sequence 8-bit
memory address words. Upon receipt of this memory address, the EEPROM outputs acknowledgment "0"
and receives a following 8-bit write data. After receipt of write data, the EEPR O M outputs
acknowledgmen t "0". If the EEPROM receives a stop condition, the EEPRO M enters an internally-timed
write cycle and terminates receipt of SCL, S D A inputs until completion of the write cycle. The EEPR OM
returns to a standby mode after completion of the write cycle.
Byte Write Operation
8k to 16k
Device
address Memory
address (n) Write data (n)
Device
address 1st Memory
address (n) 2nd Memory
address (n) Write data (n)
Start Stop
32k to 64k
1010
1010
W
W
a7
a6
a5
a4
a3
a2
a1
a0
a12
a11
a10
a9
a8
a7
a6
a5
a4
a3
a2
a1
a0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Stop
Start
ACK ACK ACK
ACK ACK
R/W
ACK
R/W
*
1
*
1
*
1
*
2
Notes: 1. Don‘t care bits for 32k and 64k.
2. Don‘t care bit for 32k.
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Rev.2.00, Oct.24.2003, page 13 of 19
Page Write :
The EEPROM is capable of the page write operation whic h allow s any num ber of bytes up to 32 bytes to
be written in a single write cycle. The page write is the same sequence as the byte w rite except for
inputting the more write data. The page write is initiated by a start condition, device address word,
mem ory addres s(n) and w rite data(D n) w ith every ninth bit acknowledgment. The EEPROM enters the
page write operation if the EEPRO M receives more write data(Dn+1) instead of receiving a stop cond ition.
The a0 to a4 address bits are automatically incremented upon receiving write data(Dn+1). The EEPROM
can continue to receive write data up to 32 bytes. If the a0 to a4 address bits reaches the last address of the
page, the a0 to a4 address bits will roll over to the first address of the same page and previous wri te data
will be overwritten. Upon receiving a stop condition, the EEPROM stops receiving write data and enters
internally-timed write cycle.
Page Write Operation
Device
address Memory
address (n) Write data (n+m)Write data (n)
8k to
16k 1010 W
a7
a6
a5
a4
a3
a2
a1
a0
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Stop
Start ACK ACK
ACK
R/W ACK
Notes: 1. Don‘t care bits for 32k and 64k.
2. Don‘t care bit for 32k.
Device
address 1st Memory
address (n) 2nd Memory
address (n) Write data (n+m)Write data (n)
32k to
64k 1010 W
a12
a11
a10
a9
a8
a7
a6
a5
a4
a3
a2
a1
a0
D7
D6
D5
D4
D3
D2
D1
D0
D5
D4
D3
D2
D1
D0
Stop
Start ACK ACK ACK ACK
ACK
R/W
*
1
*
1
*
1
*
2
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Rev.2.00, Oct.24.2003, page 14 of 19
Acknowledge Polling:
Acknow l edge pol ling feature is use d to show if the EEPROM is in a internally-timed w rite cycle or not.
This feature is initiated by the stop condition after inputting w rite data. This requires the 8-bit device
address wo rd following t he start condition during a internally-tim ed w rite cycle. Ackno wl edge pol ling w ill
operate when the R/W code = “0”. Acknowledgm ent “1” (no acknowledgment) shows the EEP R OM is in
a internally-timed write cycle and acknowledgment “0” shows that the internally-timed write cycle has
completed. See Write Cycle Polling using ACK .
Wr it e C y c le Polling Us in g ACK
Send
write command
Send
stop condition
to initiate write cycle
Send
start condition
Send
device address word
with R/W = 0
Send
memory address Send
start condition
Send
stop condition
Send
stop condition
Proceed random address
read operation
Proceed write operation
Next operation is
addressing the memory
Yes
Yes
No
No
ACK
returned
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Rev.2.00, Oct.24.2003, page 15 of 19
Read Operation
There are three read operations: current address read, random read, and sequential read. Read operations
are initiated the same way as w rite operations with the exception of R/W = “1”.
Current A ddress Read:
The internal address counter maintai ns the last address acces s ed during the las t read or write operation,
with incremented by one. C urrent address read ac cesses the address kept by the internal address counter.
After receiving a start condition and the device address word(R /W is “1”), the EEPR OM outputs the 8-bit
current address data from the mos t signi fica nt bit followi ng ackno wl edgm ent “0”. If the EEPROM
receives acknowledgment “1” (no acknowledgment) and a following stop condition, the EEPROM stops
the read operation and is turned to a standby state. In case the EEPROM has accessed the last address of
the last page at previous read operation, the current address will roll over and returns to zero address. In
case the EEPROM has accessed the last address of the page at previous write operation, the current address
will roll over within page addressing and returns to the first address in the same page. The current address
is valid while power is on. The current address after power on will be indefinite. The random read
operation described below is neces sa ry to define the mem ory address .
Current A ddress Read Operation
8k to 64k
Device
address Read data (n+1)
Start Stop
1010
R
D7
D6
D5
D4
D3
D2
D1
D0
ACK No ACK
R/W
*
1
*
2
*
3
Notes: 1. Don‘t care bit for 16k.
2. Don‘t care bits for 8k and 16k.
3. Don‘t care bits for 4k, 8k and 16k.
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Rev.2.00, Oct.24.2003, page 16 of 19
Random Read:
This is a read operation with defined read address . A random read requi res a dum m y wri te to set read
address. The EEPR OM receives a start condition, device address word(R/W=0) and memory address (8-bit
for 8kbit to 16kbit EEP ROMs, 2 × 8-bit for 32kbit and 64kbit EE P ROMs) se quenti ally. The EEP ROM
outputs acknowledgm ent “0” after receiving memory address then enters a current address read with
receiving a start condition. The EEPR OM outputs the read data of the address w hich was defined in the
dummy write operation. A fter receiving ackno wl edgm en t “1”(no acknow ledgment) and a following stop
condition, the EEPR OM stops the random read operation and returns to a standby st ate.
Ran dom Rea d Operati on
Device
address Device
address
Memory
address (n) Read data (n)
8k to
16k 1010 1010
@@@
@@@
###
WR
a7
a6
a5
a4
a3
a2
a1
a0
D5
D6
D7
D4
D3
D2
D1
D0
Start Start
ACK
ACK
R/W ACK
R/W
Notes: 1. Don‘t care bits for 32k and 64k.
2. Don‘t care bit for 32k.
3. 2nd device address code (#) should be same as 1st (@).
Device
address Device
address
1st Memory
address (n) 2nd Memory
address (n) Read data (n)
32k to
64k 1010 ###
1010 RW
a12
a11
a10
a9
a8
a7
a6
a5
a4
a3
a2
a1
a0
D7
D6
D5
D4
D3
D2
D1
D0
Stop
Start Start
ACK ACK No ACK
Stop
No ACK
ACK
R/W ACK
R/W
*
1
*
1
*
1
*
2
Dummy write
Dummy write Currect address read
Currect address read
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Rev.2.00, Oct.24.2003, page 17 of 19
Sequential Read:
Sequential reads are initiated by either a current address read or a random read. If the EEPROM receives
acknowledgmen t “0” after 8-bit read data, the read address is increme nted and the next 8-bit read data are
coming out. This operation can be continued as long as the EEPR O M receives acknowledgment “0”. The
address will roll over and returns address zero if it reaches the last address of the last page. The sequential
read can be continued after roll over. The sequential read is terminated if the EEPROM receives
acknowledgm en t “1” (no acknowledgment) and a following stop cond iti on.
Sequential Read Operation
Device
address Read data (n+m)Read data (n) Read data (n+1) Read data (n+2)
8k to
64k 1010
R
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Stop
Start ACK ACK No ACK
ACK
R/W ACK
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Rev.2.00, Oct.24.2003, page 18 of 19
Notes
Data Protecti on at VCC On/Off
When VCC is turned on or off, noise on the SC L and S D A inputs generated by external circuits (CPU, etc)
may act as a trigger and turn the EEPR OM to unintentional program mode. To prevent this unintentional
programming, this EEPROM has a power on reset function. Be careful of the notices described below in
order for the power on reset function to operate correctly.
• SC L and SDA should be fixed to VCC or VSS during VCC on/off. Low to high or high to low transi t ion
during VCC on/off may caus e the trigge r for the unintentional programming.
• VCC should be turned off after the EEPROM is placed in a standby s ta te.
• VCC shoul d be turned on from the ground level (VSS) in order for the EEPROM not to enter the
unintentional program m ing mode.
• VCC turn on speed should be lo nger than 10 µs.
Write/Erase Endurance and Data Retention Time
The endurance is 105 cycles in case of page programming and 104 cycles in case of byte programming (1%
cumulative failure rate). The data retention time is more than 10 years when a device is page-program m ed
less than 104 cycles.
Noise Suppression Time
This EE PROM have a nois e sup press i on functi on at SCL and SDA i nputs , that cut nois e of widt h less th an
50 ns. Be careful not to allow noise of width more than 50 ns.
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Rev.2.00, Oct.24.2003, page 19 of 19
Package D imensions
HN 58X2408FPIAG/HN 58X2416FPIAG/HN58X2432F PIAG/HN58X2464F PIAG (FP-8DB)
HN58X2408F PIAGE/H N 58X2416FPIAG E/H N 58X2432FPIAG E/HN58X2464FPIAGE (FP-8DBV)
Package Code
JEDEC
JEITA
Mass
(reference value)
FP-8DB, FP-8DBV
—
—
0.08 g
*Dimension including the plating thickness
Base material dimension
0˚ – 8˚
1.27
85
14
0.10
0.25
M
1.73 Max
3.90
*0.22
4.89
0.14
+ 0.114
– 0.038
0.69 Max 6.02 ± 0.18
+ 0.034
– 0.017
0.60
+ 0.289
– 0.194
1.06
0.40 ± 0.06
0.20 ± 0.03
5.15 Max
*0.42
+0.063
–0.064
Unit: mm
Revision History
HN58X2408 F PIAG/HN 58X2416FPIA G /
HN5 8X 2 432 F P IA G /H N 58X2464FP IA G D ata Sh eet
Contents of Mod ification Rev. Date
Page Description
1.0 Mar. 30, 2001 Initial issue
2.00 Oct. 24, 2003
2
19
Change form a t issued by Renesas Technology C orp.
Deletion of Preliminary
Ordering Information
Addition of HN58X2408FPIAGE, HN58X2416FPIAGE,
HN58X2432FPIAGE, H N58X 2464FPIAGE
Package Dimensions
FP-8DB to FP-8DB, FP-8DBV
©
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