Document # SRAM119 REV I Revised July 2010
P4C1256
HIGH SPEED 32K x 8
STATIC CMOS RAM
FEATURES
High Speed (Equal Access and Cycle Times)
– 12/15/20/25/35 ns (Commercial)
– 15/20/25/35/45 ns (Industrial)
– 20/25/35/45/55/70 ns (Military)
Low Power
Single 5V±10% Power Supply
Easy Memory Expansion Using CE and OE Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast tOE
Automatic Power Down
Packages
– 28-Pin 300 mil DIP, SOJ, TSOP
– 28-Pin 300 mil Ceramic DIP
– 28-Pin 600 mil Plastic and Ceramic DIP
– 28-Pin CERPACK
– 28-Pin Solder Seal Flat Pack
– 28-Pin SOP
– 28-Pin LCC (350 mil x 550 mil)
– 32-Pin LCC (450 mil x 550 mil)
FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS
DIP (P5, P6, C5, C5-1, D5-1, D5-2), SOJ (J5), SOP (S11-1, S11-3)
CERPACK (F4, FS-5) SIMILAR
DESCRIPTION
14-
CEOE)
WE
CEOEWE
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
Page 2Document # SRAM119 REV I
DC ELECTRICAL CHARACTERISTICS
(2)
Sym Parameter Value Unit
CC
TERM
TA °C
T °C
T °C
PT
I
MAXIMUM RATINGS(1) RECOMMENDED OPERATING CONDITIONS
Grade(2) Ambient Temp GND VCC
CAPACITANCES(4)
CCA
Sym Parameter Conditions Typ Unit
C
C
Sym Parameter Test Conditions
P4C1256 P4C1256L
Unit
Min Max Min Max
CC CC
IL (3) (3)
CC CC CC CC
LC (3) (3)
OL
Load) IOL CC
Load) ICC
ILI CC
CC
MIL -5
µA
-5
ILO CC CE ,
CC
MIL -5
µA
-5
I
CECC
MIL — 45 —
— —
I
CECC
LC
MIL — —
— —
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
Page 3Document # SRAM119 REV I
DATA RETENTION CHARACTERISTICS (P4C1256L Military Temperature Only)
DATA RETENTION WAVEFORM
Sym Parameter Test Conditions Min
Typ* VCC= Max VCC=
Unit
2.0V 3.0V 2.0V 3.0V
DR CC
ICCDR CECC
CC
15 µA
CDR
R
† RC
§
* TA
RC
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Sym Parameter Temperature Range -12 -15 -20 -25 -35 -45 -55 -70 Unit
ICC
155 145
165 155
165 155
CCCEIL, OE
Sym Parameter
-12 -15 -20 -25 -35 -45 -55 -70
Unit
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
RC 12 15 25 35 45 55
AA 12 15 25 35 45 55
AC 12 15 25 35 45 55
22233333
22233333
5911 15 25
OE
59 15 25
5911 15 25
PD
12 15 25 35
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
CC(2)
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
Page 4Document # SRAM119 REV I
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(5)
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)
Notes:
IL and IIL
WE
CEOE
CE
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
Page 5Document # SRAM119 REV I
AC CHARACTERISTICS—WRITE CYCLE
CC(2)
Sym Parameter -12 -15 -20 -25 -35 -45 -55 -70 Unit
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
12 15 25 35 45 55
9 15 22 35
9 15 25 35 45
AS
911 15 22 25 35
911 13 15 25
11 15 25
33333333
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(10,11)
CE and WE
OE
CEWE
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
Page 6Document # SRAM119 REV I
AC TEST CONDITIONS TRUTH TABLE
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(10)
Mode CE OE WE I/O Power
X X
D L
L L D
L X L
Figure 1. Output Load Figure 2. Thevenin Equivalent
Note:
-
CC
CC
D
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
Page 7Document # SRAM119 REV I
ORDERING INFORMATION
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
Page 8Document # SRAM119 REV I
LCC PIN CONFIGURATIONS
TSOP (T1)
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
Page 9Document # SRAM119 REV I
SIDE BRAZED CERAMIC DUAL IN-LINE PACKAGE (300 MILS)
C5
Min Max
A -
C
D -
E
L
Q
S1 -
S2 -
C5-1
Min Max
A -
C
D -
E
L
Q
S1 -
S2 -
SIDE BRAZED CERAMIC DUAL IN-LINE PACKAGE (600 MILS)
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
Page 10Document # SRAM119 REV I
CERDIP DUAL IN-LINE PACKAGE
CERDIP DUAL IN-LINE PACKAGE
D5-1
Min Max
A -
C
D -
E
L
Q
S1 -
α 15°
D5-2
Min Max
A -
C
D -
E
L
Q
S1 -
α 15°
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
Page 11Document # SRAM119 REV I
CERPACK CERAMIC FLAT PACKAGE
F4
Min Max
A
c
D -
E
k
L
Q
S -
S1 -
SOLDER SEAL FLAT PACK
FS-5
Min Max
A
c
D
E
E1 -
E2 -
E3 -
L
Q
S1 -
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
Page 12Document # SRAM119 REV I
RECTANGULAR LEADLESS CHIP CARRIER (28 PINS)
L5
Min Max
A
A1
D
D1
D2
D3 -
E
E1
E2
E3 -
L
L1
L2
5
9
SOJ SMALL OUTLINE IC PACKAGE
J5
Min Max
A
A1 -
C
D
E
E1
E2
Q -
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
Page 13Document # SRAM119 REV I
PLASTIC DUAL IN-LINE PACKAGE
P5
Min Max
A -
A1 -
C
D
E1
E
-
L
α 15°
RECTANGULAR LEADLESS CHIP CARRIER (32 PINS)
L6
32
Min Max
A
A1
D
D1
D2
D3 -
E
E1
E2
E3 -
L
L1
L2
9
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
Page 14Document # SRAM119 REV I
T1
Min Max
A
A2
D
E
D
TSOP THIN SMALL OUTLINE PACKACGE (8 x 13.4 mm)
PLASTIC DUAL IN-LINE PACKAGE
P6
Min Max
A
A1
C
D
E1
E
L
α 15°
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
Page 15Document # SRAM119 REV I
SOIC/SOP SMALL OUTLINE IC PACKAGE
S11-3
Min Max
A
A1
C
D
E
L
SOIC/SOP SMALL OUTLINE IC PACKAGE
S11-1
Min Max
A
A1
C
D
E
L
α
P4C1256 - HIGH SPEED 32K X 8 STATIC CMOS RAM
Page 16Document # SRAM119 REV I
REVISIONS
DOCUMENT NUMBER SRAM 119
DOCUMENT TITLE
REV ISSUE DATE ORIGINATOR DESCRIPTION OF CHANGE
OR RKK
A
C
D
E
F
I
