DALLAS SEMICONDUCTOR PRELIMINARY 3.3V DS21354 and 5V DS21554 E1 Single Chip Transceivers (SCT) PRELIMINARY FEATURES * * * * * * * * * * * * * * * * * * * Complete E1 (CEPT) PCM-30/ISDN-PRI transceiver functionality Onboard long and short haul line interface for clock/data recovery and waveshaping 32-bit or 128-bit crystal-less jitter attenuator Frames to FAS, CAS, CCS, and CRC4 formats Integral HDLC controller with 64-byte buffers configurable for Sa Bits, DS0 or sub DS0 operation Dual two-frame elastic store slip buffers that can connect to asynchronous backplanes up to 8.192 MHz Interleaving PCM Bus Operation 8-bit parallel control port that can be used directly on either multiplexed or non- multiplexed buses (Intel or Motorola) Extracts and inserts CAS signaling Detects and generates remote and AIS alarms Programmable output clocks for Fractional E1, H0, and H12 applications Fully independent transmit and receive functionality Full access to Si and Sa bits aligned with CRC-4 multiframe Four separate loopback functions for testing functions Large counters for bipolar and code violations, CRC4 code word errors, FAS word errors, and E bits IEEE 1149.1 JTAG-Boundary Scan Architecture Pin compatible with DS2154/52/352/552 SCTs 3.3V (DS21354) or 5V (DS21554) supply; low power CMOS 100-pin LQFP package (14mm X 14mm) 100 1 ORDERING INFORMATION DS21354L DS21354LN (00 C to 700 C) (-400 C to +850 C) DS21554L DS21554LN (00 C to 700 C) (-400 C to +850 C) DESCRIPTION The DS21354/554 Single-Chip Transceiver (SCT) contains all of the necessary functions for connection to E1 lines. The device is an upward compatible version of the DS2153 and DS2154 SCTs. The onboard clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to an NRZ serial stream. The DS21354/554 automatically adjusts to E1 22AWG (0.6 mm) twisted-pair cables from 0 to over 2km in Page 1 of 109 12799 Preliminary DS21354 & DS21554 length. The device can generate the necessary G.703 waveshapes for both 75 ohm coax and 120 ohm twisted cables. The onboard jitter attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It is also used for extracting and inserting signaling data, Si, and Sa bit information. The onboard HDLC controller can be used for Sa bit links or DS0s. The device contains a set of internal registers which the user can access and control the operation of the unit. Quick access via the parallel control port allows a single controller to handle many E1 lines. The device fully meets all of the latest E1 specifications including ITU-T G.703,G.704, G.706, G.823, G.932, and I.431, ETS 300 011, 300 233, and 300 166, as well as CTR12 and CTR4. Page 2 of 109 12799 Preliminary DS21354 & DS21554 TABLE OF CONTENTS 1. INTRODUCTION ...........................................................................................................................5 1.1 1.2 2. FUNCTIONAL DESCRIPTION ..........................................................................................................6 DOCUMENT REVISION HISTORY.........................................................................................7 PIN DESCRIPTION ........................................................................................................................9 2.1 PIN FUNCTION DESCRIPTION ............................................................................................14 2.1.1 Transmit Side Pins ..........................................................................................................14 2.1.2 Receive Side Pins ............................................................................................................16 2.1.3 Parallel Control Port Pins ...............................................................................................19 2.1.4 JTAG Test Access Port Pins............................................................................................20 2.1.5 Interleave Bus Operation Pins.........................................................................................21 2.1.6 Line Interface Pins..........................................................................................................21 2.1.7 Supply Pins......................................................................................................................22 3. PARALLEL PORT........................................................................................................................23 3.1 4. REGISTER MAP.....................................................................................................................23 CONTROL, ID, AND TEST REGISTERS...................................................................................28 4.1 4.2 4.3 4.4 4.5 5. POWER-UP SEQUENCE ..............................................................................................................28 FRAMER LOOPBACK ..................................................................................................................33 AUTOMATIC ALARM GENERATION .............................................................................................33 REMOTE LOOPBACK ..................................................................................................................35 LOCAL LOOPBACK.....................................................................................................................35 STATUS AND INFORMATION REGISTERS............................................................................38 5.1 6. CRC4 SYNC COUNTER ..............................................................................................................39 ERROR COUNT REGISTERS.....................................................................................................43 6.1 6.2 6.3 6.4 BPV OR CODE VIOLATION COUNTER .........................................................................................43 CRC4 ERROR COUNTER............................................................................................................43 E-BIT COUNTER .......................................................................................................................44 FAS ERROR COUNTER ..............................................................................................................44 7. DS0 MONITORING FUNCTION.................................................................................................46 8. SIGNALING OPERATION ..........................................................................................................48 8.1 PROCESSOR BASED SIGNALING ..................................................................................................48 8.2 HARDWARE BASED SIGNALING ..................................................................................................50 8.2.1 Receive Side ....................................................................................................................50 8.2.2 Transmit Side ..................................................................................................................50 9. PER-CHANNEL CODE GENERATION AND LOOPBACK ....................................................52 9.1 TRANSMIT SIDE CODE GENERATION ..........................................................................................52 9.1.1 Simple Idle Code Insertion and Per-Channel Loopback.................................................52 9.1.2 Per-Channel Code Insertion ...........................................................................................53 9.2 RECEIVE SIDE CODE GENERATION .............................................................................................53 10. CLOCK BLOCKING REGISTERS .........................................................................................55 11. ELASTIC STORES OPERATION ...........................................................................................57 Page 3 of 109 12799 Preliminary 11.1 11.2 12. 12.1 12.2 12.3 13. DS21354 & DS21554 RECEIVE SIDE ...........................................................................................................................57 TRANSMIT SIDE ........................................................................................................................57 ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION..................................58 HARDWARE SCHEME .................................................................................................................58 INTERNAL REGISTER SCHEME BASED ON DOUBLE-FRAME..........................................................58 INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME ....................................................60 HDLC CONTROLLER FOR THE SA BITS OR DS0.............................................................62 13.1 GENERAL OVERVIEW.................................................................................................................62 13.2 HDLC STATUS REGISTERS ........................................................................................................62 13.3 BASIC OPERATION DETAILS .......................................................................................................63 13.3.1 Receive a HDLC Message ...............................................................................................63 13.3.2 Transmit an HDLC Message...........................................................................................63 13.4 HDLC REGISTER DESCRIPTION .................................................................................................64 14. 14.1 14.2 14.3 15. 15.1 15.2 15.3 16. 16.1 16.2 17. 17.1 17.2 LINE INTERFACE FUNCTIONS ............................................................................................70 RECEIVE CLOCK AND DATA RECOVERY .....................................................................................70 TRANSMIT WAVESHAPING AND LINE DRIVING ...........................................................................71 JITTER ATTENUATOR ................................................................................................................72 JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT........................76 DESCRIPTION ............................................................................................................................76 INSTRUCTION REGISTER ............................................................................................................79 TEST REGISTERS .......................................................................................................................81 INTERLEAVED PCM BUS OPERATION ..............................................................................85 CHANNEL INTERLEAVE ..............................................................................................................86 FRAME INTERLEAVE ..................................................................................................................86 FUNCTIONAL TIMING DIAGRAMS.....................................................................................87 RECEIVE ...................................................................................................................................87 TRANSMIT ................................................................................................................................90 18. OPERATING PARAMETERS .................................................................................................96 19. AC TIMING PARAMETERS AND DIAGRAMS....................................................................97 19.1 19.2 19.3 19.4 20. MULTIPLEXED BUS AC CHARACTERISTICS .................................................................................97 NON-MULTIPLEXED BUS AC CHARACTERISTICS ......................................................................100 RECEIVE SIDE AC CHARACTERISTICS ......................................................................................103 TRANSMIT AC CHARACTERISTICS ...........................................................................................106 MECHANICAL DESCRIPTION............................................................................................109 Page 4 of 109 12799 Preliminary DS21354 & DS21554 1. INTRODUCTION The DS21354/554 is a superset version of the popular DS2153 and DS2154 SCTs offering the new features listed below. All of the original features of the DS2153 and DS2154 have been retained and software created for the original devices is transferrable into the DS21354/554. New Features in the DS21354 and DS21554 FEATURE HDLC controller with 64-byte buffers for Sa bits or DS0s or sub DS0s Interleaving PCM bus operation IEEE 1149.1 JTAG-Boundary Scan Architecture 3.3V (DS21354 only) supply Line Interface Support for the G.703 2.048 Synchronization Interface Customer Disconnect Indication (...101010...) Generator Open Drain Line Driver Option SECTION 15 18 17 2 and 3 16 6 16 New Features in the DS2154 (also in the DS21354 and DS21554) FEATURE Option for non-multiplexed bus operation Crystal-less jitter attenuation Additional hardware signaling capability including: Receive signaling reinsertion to a backplane multiframe sync Availability of signaling in a separate PCM data stream Signaling freezing Interrupt generated on change of signaling data Improved receive sensitivity: 0 dB to -43 dB Per-channel code insertion in both transmit and receive paths Expanded access to Sa and Si bits RCL, RLOS, RRA, and RAIS alarms now interrupt on change of state 8.192 MHz clock synthesizer Per-channel loopback Addition of hardware pins to indicate carrier loss and signaling freeze Line interface function can be completely decoupled from the framer/formatter to allow: Interface to optical, HDSL, and other NRZ interfaces "tap" the transmit and receive bipolar data streams for monitoring purposes Be able to corrupt data and insert framing errors, CRC errors, etc. Transmit and receive elastic stores now have independent backplane clocks Ability to monitor one DS0 channel in both the transmit and receive paths Access to the data streams in between the framer/formatter and the elastic stores AIS generation in the line interface that is independent of loopbacks Transmit current limiter to meet the 50 mA short circuit requirement Option to extend carrier loss criteria to a 1 ms period as per ETS 300 233 Automatic RAI generation to ETS 300 011 specifications Page 5 of 109 SECTION 1 and 2 12 7 12 8 11 4 1 8 1 1 1 6 1 1 and 3 12 3 3 12799 Preliminary DS21354 & DS21554 1.1 Functional Description The analog AMI/HDB3 waveform off of the E1 line is transformer coupled into the RRING and RTIP pins of the DS21354/554. The device recovers clock and data from the analog signal and passes it through the jitter attenuation mux to the receive side framer where the digital serial stream is analyzed to locate the framing/multi-frame pattern. The DS21354/554 contains an active filter that reconstructs the analog received signal for the nonlinear losses that occur in transmission. The device has a usable receive sensitivity of 0 dB to -43 dB which allows the device to operate on cables over 2km in length. The receive side framer locates FAS frame and CRC and CAS multiframe boundaries as well as detects incoming alarms including, carrier loss, loss of synchronization, AIS and Remote Alarm. If needed, the receive side elastic store can be enabled in order to absorb the phase and frequency differences between the recovered E1 data stream and an asynchronous backplane clock which is provided at the RSYSCLK input. The clock applied at the RSYSCLK input can be either a 2.048/4.096/8.192 MHz clock or a 1.544 MHz clock. The transmit side framer is totally independent from the receive side in both the clock requirements and characteristics. Data off of a backplane can be passed through a transmit side elastic store if necessary. The transmit formatter will provide the necessary frame/multiframe data overhead for E1 transmission. Reader's Note: This data sheet assumes a particular nomenclature of the E1 operating environment. In each 125 us frame, there are 32 eight-bit timeslots numbered 0 to 31. Timeslot 0 is transmitted first and received first. These 32 timeslots are also referred to as channels with a numbering scheme of 1 to 32. Timeslot 0 is identical to channel 1, timeslot 1 is identical to Channel 2, and so on. Each timeslot (or channel) is made up of eight bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is the LSB and is transmitted last. The term "locked" is used to refer to two clock signals that are phase or frequency locked or derived from a common clock (i.e., a 1.544MHz clock may be locked to a 2.048MHz clock if they share the same 8KHz component). Throughout this data sheet, the following abbreviations will be used: FAS CAS MF Si CRC4 CCS Sa E-bit Frame Alignment Signal Channel Associated Signaling Multiframe International bits Cyclical Redundancy Check Common Channel Signaling Additional bits CRC4 Error Bits Page 6 of 109 12799 Preliminary DS21354 & DS21554 1.2 DOCUMENT REVISION HISTORY Date 1-27-1999 Notes Initial release Page 7 of 109 12799 Local Loopback Page 8 JTAG PORT Receive Line I/F Clock / Data Recovery of 109 TTIP TRING 32.768MHz MCLK RTIP XTALD 16.384 MHz RRING 8XCLK VCO / PLL MUX RPOSI RCLKI RNEGI RNEGO RCLKO RPOSO MUX LIUC Sa Framer Loopback Jitter Attenuator Either transmit or receive path 8 MUX D0 to D7 / AD0 to AD7 7 HDLC/BOC Controller Sa / DS0 LOTC MUX Elastic Store Sync Control Elastic Store Timing Control Interleave Bus Interleave Bus 8.192MHz Clock Synthesizer RSYSCLK Timing Control Hardware Signaling Insertion Signaling Buffer CI Parallel & Test Control Port (routed to all blocks) SYNC CLOCK DATA Transmit Side Formatter DATA CLOCK SYNC Receive Side Framer HDLC/BOC Controller Sa / DS0 TLINK TLCLK TCHBLK TCHCLK TCLK TSER TSIG TSSYNC TSYSCLK TDATA TESO TSYNC RSYNC RMSYNC RFSYNC RDATA RSYSCLK RSER RLINK RLCLK RCHBLK RCHCLK RSIGF RSIG 8MCLK RCL RCLK RLOS/LOTC Preliminary DS21354 & DS21554 DS21354/554 Single-Chip Transceiver Figure 1-1 CO INT* A0 to A6 ALE(AS) / A7 RD*(DS*) WR*(R/W*) BTS CS* Remote Loopback TEST TPOSO TCLKO TNEGO TNEGI TCLKI TPOSI LIUC JTDO JTDI JTCLK JTMS JRST* Transmit Line I/F 12799 Preliminary DS21354 & DS21554 2. PIN DESCRIPTION Pin Description Sorted by Pin Number Table 2-1 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 SYMBOL RCHBLK JTMS 8MCLK JTCLK JTRST* RCL JTDI NC NC JTDO BTS LIUC 8XCLK TEST NC RTIP RRING RVDD RVSS RVSS MCLK XTALD NC RVSS INT* NC NC NC TTIP TVSS TVDD TRING TCHBLK TLCLK TLINK CI TSYNC TPOSI TNEGI TCLKI TCLKO TNEGO TPOSO DVDD DVSS TYPE O I O I I O I - - O I I O I - I I - - - I O - - O - - - O - - O O O I I I/O I I I O O O - - DESCRIPTION Receive Channel Block IEEE 1149.1 Test Mode Select 8.192 MHz Clock IEEE 1149.1 Test Clock Signal IEEE 1149.1 Test Reset Receive Carrier Loss IEEE 1149.1 Test Data Input No Connect (do not connect any signal to this pin) No Connect (do not connect any signal to this pin) IEEE 1149.1 Test Data Output Bus Type Select Line Interface Connect Eight Times Clock Test No Connect (do not connect any signal to this pin) Receive Analog Tip Input Receive Analog Ring Input Receive Analog Positive Supply Receive Analog Signal Ground Receive Analog Signal Ground Master Clock Input Quartz Crystal Driver No Connect Receive Analog Signal Ground Interrupt No Connect (do not connect any signal to this pin) No Connect (do not connect any signal to this pin) No Connect (do not connect any signal to this pin) Transmit Analog Tip Output Transmit Analog Signal Ground Transmit Analog Positive Supply Transmit Analog Ring Output Transmit Channel Block Transmit Link Clock Transmit Link Data Carry In Transmit Sync Transmit Positive Data Input Transmit Negative Data Input Transmit Clock Input Transmit Clock Output Transmit Negative Data Output Transmit Positive Data Output Digital Positive Supply Digital Signal Ground Page 9 of 109 12799 Preliminary 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 TCLK TSER TSIG TESO TDATA TSYSCLK TSSYNC TCHCLK CO MUX D0/AD0 D1/AD1 D2/AD2 D3/AD3 DVSS DVDD D4/AD4 D5/AD5 D6/AD6 D7/AD7 A0 A1 A2 A3 A4 A5 A6 ALE(AS)/A7 RD*(DS*) CS* FMS WR*(R/W*) RLINK RLCLK DVSS DVDD RCLK DVDD DVSS RDATA RPOSI RNEGI RCLKI RCLKO RNEGO RPOSO RCHCLK RSIGF RSIG RSER DS21354 & DS21554 I I I O I I I O O I I/O I/O I/O I/O - - I/O I/O I/O I/O I I I I I I I I I I I I O O - - O - - O I I I O O O O O O O Transmit Clock Transmit Serial Data Transmit Signaling Input Transmit Elastic Store Output Transmit Data Transmit System Clock Transmit System Sync Transmit Channel Clock Carry Out Bus Operation Data Bus Bit0/ Address/Data Bus Bit 0 Data Bus Bit1/ Address/Data Bus Bit 1 Data Bus Bit 2/Address/Data Bus 2 Data Bus Bit 3/Address/Data Bus Bit 3 Digital Signal Ground Digital Positive Supply Data Bus Bit4/Address/Data Bus Bit 4 Data Bus Bit 5/Address/Data Bus Bit 5 Data Bus Bit 6/Address/Data Bus Bit 6 Data Bus Bit 7/Address/Data Bus Bit 7 Address Bus Bit 0 Address Bus Bit 1 Address Bus Bit 2 Address Bus Bit 3 Address Bus Bit 4 Address Bus Bit 5 Address Bus Bit 6 Address Latch Enable /Address Bus Bit 7 Read Input(Data Strobe) Chip Select Framer Mode Select Write Input(Read/Write) Receive Link Data Receive Link Clock Digital Signal Ground Digital Positive Supply Receive Clock Digital Positive Supply Digital Signal Ground Receive Data Receive Positive Data Input Receive Negative Data Input Receive Clock Input Receive Clock Output Receive Negative Data Output Receive Positive Data Output Receive Channel Clock Receive Signaling Freeze Output Receive Signaling Output Receive Serial Data Page 10 of 109 12799 Preliminary 96 97 98 99 100 RMSYNC RFSYNC RSYNC RLOS/LOTC RSYSCLK DS21354 & DS21554 O O I/O O I Receive Multiframe Sync Receive Frame Sync Receive Sync Receive Loss Of Sync/ Loss Of Transmit Clock Receive System Clock Pin Description by Symbol Table 2-2 PIN 3 13 66 67 68 69 70 71 72 73 11 36 54 75 56 57 58 59 62 63 64 65 44 81 61 83 45 60 80 84 76 25 4 7 10 2 5 12 21 55 SYMBOL 8MCLK 8XCLK A0 A1 A2 A3 A4 A5 A6 ALE(AS)/A7 BTS CI CO CS* D0/AD0 D1/AD1 D2/AD2 D3/AD3 D4/AD4 D5/AD5 D6/AD6 D7/AD7 DVDD DVDD DVDD DVDD DVSS DVSS DVSS DVSS FMS INT* JTCLK JTDI JTDO JTMS JTRST* LIUC MCLK MUX TYPE O O I I I I I I I I I I O I I/O I/O I/O I/O I/O I/O I/O I/O - - - - - - - - I O I I O I I I I I DESCRIPTION 8.192 MHz Clock Eight Times Clock Address Bus Bit 0 Address Bus Bit 1 Address Bus Bit 2 Address Bus Bit 3 Address Bus Bit 4 Address Bus Bit 5 Address Bus Bit 6 Address Latch Enable/ Address Bus Bit 7 Bus Type Select Carry In Carry Out Chip Select Data Bus Bit0/ Address/Data Bus Bit 0 Data Bus Bit1/ Address/Data Bus Bit 1 Data Bus Bit 2/Address/Data Bus 2 Data Bus Bit 3/Address/Data Bus Bit 3 Data Bus Bit4/Address/Data Bus Bit 4 Data Bus Bit 5/Address/Data Bus Bit 5 Data Bus Bit 6/Address/Data Bus Bit 6 Data Bus Bit 7/Address/Data Bus Bit 7 Digital Positive Supply Digital Positive Supply Digital Positive Supply Digital Positive Supply Digital Signal Ground Digital Signal Ground Digital Signal Ground Digital Signal Ground Framer Mode Select Interrupt IEEE 1149.1 Test Clock Signal IEEE 1149.1 Test Data Input IEEE 1149.1 Test Data Output IEEE 1149.1 Test Mode Select IEEE 1149.1 Test Reset Line Interface Connect Master Clock Input Bus Operation Page 11 of 109 12799 Preliminary 8 9 15 23 26 27 28 1 92 6 82 88 89 74 85 97 79 78 99 96 87 90 86 91 17 95 94 93 98 100 16 18 19 20 24 33 53 46 40 41 50 49 14 34 35 39 42 38 43 32 NC NC NC NC NC NC NC RCHBLK RCHCLK RCL RCLK RCLKI RCLKO RD*(DS*) RDATA RFSYNC RLCLK RLINK RLOS/LOTC RMSYNC RNEGI RNEGO RPOSI RPOSO RRING RSER RSIG RSIGF RSYNC RSYSCLK RTIP RVDD RVSS RVSS RVSS TCHBLK TCHCLK TCLK TCLKI TCLKO TDATA TESO TEST TLCLK TLINK TNEGI TNEGO TPOSI TPOSO TRING DS21354 & DS21554 - - - - - - - O O O O I O I O O O O O O I O I O I O O O I/O I I - - - - O O I I O I O I O I I O I O O No Connect (do not connect any signal to this pin) No Connect (do not connect any signal to this pin) No Connect (do not connect any signal to this pin) No Connect (do not connect any signal to this pin) No Connect (do not connect any signal to this pin) No Connect (do not connect any signal to this pin) No Connect (do not connect any signal to this pin) Receive Channel Block Receive Channel Clock Receive Carrier Loss Receive Clock Receive Clock Input Receive Clock Output Read Input(Data Strobe) Receive Data Receive Frame Sync Receive Link Clock Receive Link Data Receive Loss Of Sync/ Loss Of Transmit Clock Receive Multiframe Sync Receive Negative Data Input Receive Negative Data Output Receive Positive Data Input Receive Positive Data Output Receive Analog Ring Input Receive Serial Data Receive Signaling Output Receive Signaling Freeze Output Receive Sync Receive System Clock Receive Analog Tip Input Receive Analog Positive Supply Receive Analog Signal Ground Receive Analog Signal Ground Receive Analog Signal Ground Transmit Channel Block Transmit Channel Clock Transmit Clock Transmit Clock Input Transmit Clock Output Transmit Data Transmit Elastic Store Output Test Transmit Link Clock Transmit Link Data Transmit Negative Data Input Transmit Negative Data Output Transmit Positive Data Input Transmit Positive Data Output Transmit Analog Ring Output Page 12 of 109 12799 Preliminary 47 48 52 37 51 29 31 30 77 22 TSER TSIG TSSYNC TSYNC TSYSCLK TTIP TVDD TVSS WR*(R/W*) XTALD DS21354 & DS21554 I I I I/O I O - - I O Transmit Serial Data Transmit Signaling Input Transmit System Sync Transmit Sync Transmit System Clock Transmit Analog Tip Output Transmit Analog Positive Supply Transmit Analog Signal Ground Write Input(Read/Write) Quartz Crystal Driver Page 13 of 109 12799 Preliminary 2.1 DS21354 & DS21554 PIN FUNCTION DESCRIPTION 2.1.1 Transmit Side Pins Signal Name: TCLK Signal Description: Transmit Clock Signal Type: Input A 2.048 MHz primary clock. Used to clock data through the transmit side formatter. Signal Name: TSER Signal Description: Transmit Serial Data Signal Type: Input Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled. Signal Name: TCHCLK Signal Description: Transmit Channel Clock Signal Type: Output A 256 kHz clock which pulses high during the LSB of each channel. Synchronous with TCLK when the transmit side elastic store is disabled. Synchronous with TSYSCLK when the transmit side elastic store is enabled. Useful for parallel to serial conversion of channel data. Signal Name: TCHBLK Signal Description: Transmit Channel Block Signal Type: Output A user programmable output that can be forced high or low during any of the 32 E1 channels. Synchronous with TCLK when the transmit side elastic store is disabled. Synchronous with TSYSCLK when the transmit side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD controller in applications where not all E1 channels are used such as Fractional E1, 384 kbps (H0), 768 kbps or ISDN-PRI . Also useful for locating individual channels in drop-and-insert applications, for external per-channel loopback, and for per-channel conditioning. See Section 10 for details. Signal Name: TSYSCLK Signal Description: Transmit System Clock Signal Type: Input 1.544 MHz , 2.048 MHz , 4.096 MHz or 8.192 MHz clock. Only used when the transmit side elastic store function is enabled. Should be tied low in applications that do not use the transmit side elastic store. See section 16 on page 85 for details on 4.096 MHz and 8.192 MHz operation using the Interleave Bus Option. Signal Name: TLCLK Signal Description: Transmit Link Clock Signal Type: Output 4 kHz to 20 kHz demand clock (Sa bits) for the TLINK input. See Section 12.1 for details. Signal Name: TLINK Signal Description: Transmit Link Data Signal Type: Input If enabled, this pin will be sampled on the falling edge of TCLK for data insertion into any combination of the Sa bit positions (Sa4 to Sa8). See Section 12.1 for details. Page 14 of 109 12799 Preliminary DS21354 & DS21554 Signal Name: TSYNC Signal Description: Transmit Sync Signal Type: Input / Output A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Via TCR2.2, the DS21352/552 can be programmed to output either a frame or multiframe pulse at this pin. If this pin is set to output pulses at frame boundaries, it can also be set via TCR2.4 to output double-wide pulses at signaling frames. See Section 17 for details. Signal Name: TSSYNC Signal Description: Transmit System Sync Signal Type: Input Only used when the transmit side elastic store is enabled. A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Should be tied low in applications that do not use the transmit side elastic store. Signal Name: TSIG Signal Description: Transmit Signaling Input Signal Type: Input When enabled, this input will sample signaling bits for insertion into outgoing PCM E1 data stream. Sampled on the falling edge of TCLK when the transmit side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled. Signal Name: TESO Signal Description: Transmit Elastic Store Data Output Signal Type: Output Updated on the rising edge of TCLK with data out of the transmit side elastic store whether the elastic store is enabled or not. This pin is normally tied to TDATA. Signal Name: TDATA Signal Description: Transmit Data Signal Type: Input Sampled on the falling edge of TCLK with data to be clocked through the transmit side formatter. This pin is normally tied to TESO. Signal Name: TPOSO Signal Description: Transmit Positive Data Output Signal Type: Output Updated on the rising edge of TCLKO with the bipolar data out of the transmit side formatter. Can be programmed to source NRZ data via the Output Data Format (CCR1.6) control bit. This pin is normally tied to TPOSI. Signal Name: TNEGO Signal Description: Transmit Negative Data Output Signal Type: Output Updated on the rising edge of TCLKO with the bipolar data out of the transmit side formatter. This pin is normally tied to TNEGI. Signal Name: TCLKO Signal Description: Transmit Clock Output Signal Type: Output Buffered output of signal that is clocking data through the transmit side formatter. This pin is normally tied to TCLKI. Page 15 of 109 12799 Preliminary DS21354 & DS21554 Signal Name: TPOSI Signal Description: Transmit Positive Data Input Signal Type: Input Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected to TPOSO by tying the LIUC pin high. TPOSI and TNEGI can be tied together in NRZ applications. Signal Name: TNEGI Signal Description: Transmit Negative Data Input Signal Type: Input Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected to TNEGO by tying the LIUC pin high. TPOSI and TNEGI can be tied together in NRZ applications. Signal Name: TCLKI Signal Description: Transmit Clock Input Signal Type: Input Line interface transmit clock. Can be internally connected to TCLKO by tying the LIUC pin high. 2.1.2 Receive Side Pins Signal Name: RLINK Signal Description: Receive Link Data Signal Type: Output Updated with the full recovered E1 data stream on the rising edge of RCLK. Signal Name: RLCLK Signal Description: Receive Link Clock Signal Type: Output 4 kHz to 20 kHz clock (Sa bits) for the RLINK output. See Section 13 for details. Signal Name: RCLK Signal Description: Receive Clock Signal Type: Output 2.048 MHz clock that is used to clock data through the receive side framer. Signal Name: RCHCLK Signal Description: Receive Channel Clock Signal Type: Output A 192 kHz clock which pulses high during the LSB of each channel. Synchronous with RCLK when the receive side elastic store is disabled. Synchronous with RSYSCLK when the receive side elastic store is enabled. Useful for parallel to serial conversion of channel data. Signal Name: RCHBLK Signal Description: Receive Channel Block Signal Type: Output A user programmable output that can be forced high or low during any of the 30 E1 channels. Synchronous with RCLK when the receive side elastic store is disabled. Synchronous with RSYSCLK when the receive side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD controller in applications where not all E1 channels are used such as Fractional E1, 384 kbps service, 768 Page 16 of 109 12799 Preliminary DS21354 & DS21554 kbps, or ISDN-PRI. Also useful for locating individual channels in drop-and-insert applications, for external per-channel loopback, and for per-channel conditioning. See Section 10 for details. Signal Name: RSER Signal Description: Receive Serial Data Signal Type: Output Received NRZ serial data. Updated on rising edges of RCLK when the receive side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled. Signal Name: RSYNC Signal Description: Receive Sync Signal Type: Input/Output An extracted pulse, one RCLK wide, is output at this pin which identifies either frame or CAS/CRC multiframe boundaries. If the receive side elastic store is enabled, then this pin can be enabled to be an input at which a frame or multiframe boundary pulse synchronous with RSYSCLK is applied. Signal Name: RFSYNC Signal Description: Receive Frame Sync Signal Type: Output An extracted 8 kHz pulse, one RCLK wide, is output at this pin which identifies frame boundaries. Signal Name: RMSYNC Signal Description: Receive Multiframe Sync Signal Type: Output If the receive side elastic store is enabled, an extracted pulse, one RSYSCLK wide, is output at this pin which identifies multiframe boundaries. If the receive side elastic store is disabled, then this output will output multiframe boundaries associated with RCLK. Signal Name: RDATA Signal Description: Receive Data Signal Type: Output Updated on the rising edge of RCLK with the data out of the receive side framer. Signal Name: RSYSCLK Signal Description: Receive System Clock Signal Type: Input 1.544 MHz , 2.048 MHz , 4.096 MHz or 8.192 MHz clock. Only used when the receive side elastic store function is enabled. Should be tied low in applications that do not use the receive side elastic store. See section 16 on page 85 for details on 4.096 MHz and 8.192 MHz operation using the Interleave Bus Option. Signal Name: RSIG Signal Description: Receive Signaling Output Signal Type: Output Outputs signaling bits in a PCM format. Updated on rising edges of RCLK when the receive side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled. Signal Name: RLOS/LOTC Signal Description: Receive Loss of Sync / Loss of Transmit Clock Signal Type: Output A dual function output that is controlled by the TCR2.0 control bit. This pin can be programmed to either toggle high when the synchronizer is searching for the frame and multiframe or to toggle high if the TCLK pin has not been toggled for 5 sec. Page 17 of 109 12799 Preliminary DS21354 & DS21554 Signal Name: RCL Signal Description: Receive Carrier Loss Signal Type: Output Set high when the line interface detects a carrier loss. Signal Name: RSIGF Signal Description: Receive Signaling Freeze Signal Type: Output Set high when the signaling data is frozen via either automatic or manual intervention. Used to alert downstream equipment of the condition. Signal Name: 8MCLK Signal Description: 8 MHz Clock Signal Type: Output An 8.192MHz clock output that is referenced to the clock that is output at the RCLK pin. Signal Name: RPOSO Signal Description: Receive Positive Data Input Signal Type: Output Updated on the rising edge of RCLKO with bipolar data out of the line interface. This pin is normally tied to RPOSI. Signal Name: RNEGO Signal Description: Receive Negative Data Input Signal Type: Output Updated on the rising edge of RCLKO with the bipolar data out of the line interface. This pin is normally tied to RPOSI. Signal Name: RCLKO Signal Description: Receive Clock Output Signal Type: Output Buffered recovered clock from the T1 line. This pin is normally tied to RCLKI. Signal Name: RPOSI Signal Description: Receive Positive Data Input Signal Type: Input Sampled on the falling edge of RCLKI for data to be clocked through the receive side framer. RPOSI and RNEGI can be tied together for a NRZ interface. Can be internally connected to RPOSO by tying the LIUC pin high. Signal Name: RNEGI Signal Description: Receive Negative Data Input Signal Type: Input Sampled on the falling edge of RCLKI for data to be clocked through the receive side framer. RPOSI and RNEGI can be tied together for a NRZ interface. Can be internally connected to RNEGO by tying the LIUC pin high. Signal Name: Signal Description: Signal Type: RCLKI Receive Clock Input Input Page 18 of 109 12799 Preliminary DS21354 & DS21554 Clock used to clock data through the receive side framer. This pin is normally tied to RCLKO. Can be internally connected to RCLKO by tying the LIUC pin high. 2.1.3 Parallel Control Port Pins Signal Name: INT* Signal Description: Interrupt Signal Type: Output Flags host controller during conditions and change of conditions defined in the Status Registers 1 and 2 and the HDLC Status Register. Active low, open drain output Signal Name: FMS Signal Description: Framer Mode Select Signal Type: Input Selects the DS2154 mode when high or the DS21354/554 mode when low. If high, the JTRST* is internally pulled low. If low, JTRST* has normal JTAG functionality. This pin has a 10k pull up resistor. Signal Name: TEST Signal Description: 3-State Control Signal Type: Input Set high to 3-state all output and I/O pins (including the parallel control port). Set low for normal operation. Useful in board level testing. Signal Name: MUX Signal Description: Bus Operation Signal Type: Input Set low to select non-multiplexed bus operation. Set high to select multiplexed bus operation. Signal Name: AD0 TO AD7 Signal Description: Data Bus [D0 to D7] or Address/Data Bus Signal Type: Input In non-multiplexed bus operation (MUX = 0), serves as the data bus. In multiplexed bus operation (MUX = 1), serves as a 8-bit multiplexed address / data bus. Signal Name: A0 TO A6 Signal Description: Address Bus Signal Type: Input In non-multiplexed bus operation (MUX = 0), serves as the address bus. In multiplexed bus operation (MUX = 1), these pins are not used and should be tied low. Signal Name: BTS Signal Description: Bus Type Select Signal Type: Input Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the function of the RD*(DS*), ALE(AS), and WR*(R/W*) pins. If BTS = 1, then these pins assume the function listed in parenthesis (). Signal Name: RD*(DS*) Signal Description: Read Input - Data Strobe Signal Type: Input RD* and DS* are active low signals. DS active HIGH when MUX = 0. See bus timing diagrams. Page 19 of 109 12799 Preliminary DS21354 & DS21554 Signal Name: CS* Signal Description: Chip Select Signal Type: Input Must be low to read or write to the device. CS* is an active low signal. Signal Name: ALE(AS)/A7 Signal Description: Address Latch Enable(Address Strobe) or A7 Signal Type: Input In non-multiplexed bus operation (MUX = 0), serves as the upper address bit. In multiplexed bus operation (MUX = 1), serves to de-multiplex the bus on a positive-going edge. Signal Name: WR*(R/W*) Signal Description: Write Input(Read/Write) Signal Type: Input WR* is an active low signal. 2.1.4 JTAG Test Access Port Pins Signal Name: JTRST* Signal Description: IEEE 1149.1 Test Reset Signal Type: Input This signal is used to asynchronously reset the test access port controller. At power up, JTRST* must be toggled from low to high. This action will set the device into the DEVICE ID mode allowing normal device operation. This pin has a 10k pull up resistor. When FMS=1, this pin is tied low internally. Tie JTRST* low if JTAG is not used and the framer is in DS21352/552 mode (FMS low). Signal Name: JTMS Signal Description: IEEE 1149.1 Test Mode Select Signal Type: Input This pin is sampled on the rising edge of JTCLK and is used to place the test access port into the various defined IEEE 1149.1 states. This pin has a 10k pull up resistor. Signal Name: JTCLK Signal Description: IEEE 1149.1 Test Clock Signal Signal Type: Input This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. Signal Name: JTDI Signal Description: IEEE 1149.1 Test Data Input Signal Type: Input Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin has a 10k pull up resistor. Signal Name: JTDO Signal Description: IEEE 1149.1 Test Data Output Signal Type: Output Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin should be left unconnected. Page 20 of 109 12799 Preliminary DS21354 & DS21554 2.1.5 Interleave Bus Operation Pins Signal Name: CI Signal Description: Carry In Signal Type: Input A rising edge on this pin causes RSER and RSIG to come out of high Z state and TSER and TSIG to start sampling on the next rising edge of RSYSCLK/TSYSCLK beginning an I/O sequence of 8 or 256 bits of data. This pin has a 10k pull up resistor. Signal Name: CO Signal Description: Carry Out Signal Type: Output An output that is set high when the last bit of the 8 or 256 IBO output sequence has occurred on RSER and RSIG. 2.1.6 Line Interface Pins Signal Name: MCLK Signal Description: Master Clock Input Signal Type: Input A 2.048 MHz (50 ppm) clock source with TTL levels is applied at this pin. This clock is used internally for both clock/data recovery and for jitter attenuation. A quartz crystal of 2.048 MHz may be applied across MCLK and XTALD instead of the TTL level clock source. Signal Name: XTALD Signal Description: Quartz Crystal Driver Signal Type: Output A quartz crystal of 2.048 MHz may be applied across MCLK and XTALD instead of a TTL level clock source at MCLK. Leave open circuited if a TTL clock source is applied at MCLK. Signal Name: 8XCLK Signal Description: Eight Times Clock Signal Type: Output A 16.384 MHz clock that is frequency locked to the 2.048 MHz clock provided from the clock/data recovery block (if the jitter attenuator is enabled on the receive side) or from the TCLKI pin (if the jitter attenuator is enabled on the transmit side). Can be internally disabled via TEST2 register if not needed. Signal Name: LIUC Signal Description: Line Interface Connect Signal Type: Input Tie low to separate the line interface circuitry from the framer/formatter circuitry and activate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. Tie high to connect the line interface circuitry to the framer/formatter circuitry and deactivate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. When LIUC is tied high, the TPOSI/TNEGI/TCLKI/ RPOSI/RNEGI/RCLKI pins should be tied low. Signal Name: Signal Description: Signal Type: RTIP & RRING Receive Tip and Ring Input Page 21 of 109 12799 Preliminary DS21354 & DS21554 Analog inputs for clock recovery circuitry. These pins connect via a 1:1 transformer to the E1 line. See Section 14 for details. Signal Name: TTIP & TRING Signal Description: Transmit Tip and Ring Signal Type: Output Analog line driver outputs. These pins connect via a 1:2 step-up transformer to the E1 line. See Section 14 for details. 2.1.7 Supply Pins Signal Name: DVDD Signal Description: Digital Positive Supply Signal Type: Supply 5.0 volts +/-5% (DS21554) or 3.3 volts +/-5% (DS21354). Should be tied to the RVDD and TVDD pins. Signal Name: RVDD Signal Description: Receive Analog Positive Supply Signal Type: Supply 5.0 volts +/-5% (DS21554) or 3.3 volts +/-5% (DS21354). Should be tied to the DVDD and TVDD pins. Signal Name: TVDD Signal Description: Transmit Analog Positive Supply Signal Type: Supply 5.0 volts +/-5% (DS21554) or 3.3 volts +/-5% (DS21354). Should be tied to the RVDD and DVDD pins. Signal Name: DVSS Signal Description: Digital Signal Ground Signal Type: Supply Should be tied to the RVSS and TVSS pins. Signal Name: RVSS Signal Description: Receive Analog Signal Ground Signal Type: Supply 0.0 volts. Should be tied to DVSS and TVSS. Signal Name: TVSS Signal Description: Transmit Analog Signal Ground Signal Type: Supply 0.0 volts. Should be tied to DVSS and RVSS. Page 22 of 109 12799 Preliminary DS21354 & DS21554 3. PARALLEL PORT The DS21354/554 is controlled via either a non-multiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by an external microcontroller or microprocessor. The device can operate with either Intel or Motorola bus timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in the A.C. Electrical Characteristics in Section 19 for more details. 3.1 REGISTER MAP Register Map Sorted by Address Table 3-1 ADDRESS R/W 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 R R R R R R R/W R/W R/W - - - - - - R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W REGISTER NAME BPV or Code Violation Count 1 BPV or Code Violation Count 2 CRC4 Error Count 1 / FAS Error Count 1 CRC4 Error Count 2 E-Bit Count 1 / FAS Error Count 2 E-Bit Count 2 Status 1 Status 2 Receive Information Not used Not used Not used Not used Not used Not used Device ID Receive Control 1 Receive Control 2 Transmit Control 1 Transmit Control 2 Common Control 1 Test 1 Interrupt Mask 1 Interrupt Mask 2 Line Interface Control Register Test 2 Common Control 2 Common Control 3 Transmit Sa Bit Control Common Control 6 Synchronizer Status Receive Non-Align Frame Transmit Align Frame Transmit Non-Align Frame Page 23 of 109 REGISTER ABBREVIATION VCR1 VCR2 CRCCR1 CRCCR2 EBCR1 EBCR2 SR1 SR2 RIR (set to 00h) (set to 00h) (set to 00h) (set to 00h) (set to 00h) (set to 00h) IDR RCR1 RCR2 TCR1 TCR2 CCR1 TEST1 (set to 00h) IMR1 IMR2 LICR TEST2 (set to 00h) CCR2 CCR3 TSaCR CCR6 SSR RNAF TAF TNAF 12799 Preliminary 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 DS21354 & DS21554 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transmit Channel Blocking 1 Transmit Channel Blocking 2 Transmit Channel Blocking 3 Transmit Channel Blocking 4 Transmit Idle 1 Transmit Idle 2 Transmit Idle 3 Transmit Idle 4 Transmit Idle Definition Receive Channel Blocking 1 Receive Channel Blocking 2 Receive Channel Blocking 3 Receive Channel Blocking 4 Receive Align Frame Receive Signaling 1 Receive Signaling 2 Receive Signaling 3 Receive Signaling 4 Receive Signaling 5 Receive Signaling 6 Receive Signaling 7 Receive Signaling 8 Receive Signaling 9 Receive Signaling 10 Receive Signaling 11 Receive Signaling 12 Receive Signaling 13 Receive Signaling 14 Receive Signaling 15 Receive Signaling 16 Transmit Signaling 1 Transmit Signaling 2 Transmit Signaling 3 Transmit Signaling 4 Transmit Signaling 5 Transmit Signaling 6 Transmit Signaling 7 Transmit Signaling 8 Transmit Signaling 9 Transmit Signaling 10 Transmit Signaling 11 Transmit Signaling 12 Transmit Signaling 13 Transmit Signaling 14 Transmit Signaling 15 Transmit Signaling 16 Transmit Si Bits Align Frame Transmit Si Bits Non-Align Frame Transmit Remote Alarm Bits Transmit Sa4 Bits Page 24 of 109 TCBR1 TCBR2 TCBR3 TCBR4 TIR1 TIR2 TIR3 TIR4 TIDR RCBR1 RCBR2 RCBR3 RCBR4 RAF RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12 RS13 RS14 RS15 RS16 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15 TS16 TSiAF TSiNAF TRA TSa4 12799 Preliminary 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 DS21354 & DS21554 R/W R/W R/W R/W R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transmit Sa5 Bits Transmit Sa6 Bits Transmit Sa7 Bits Transmit Sa8 Bits Receive Si bits Align Frame Receive Si bits Non-Align Frame Receive Remote Alarm Bits Receive Sa4 Bits Receive Sa5 Bits Receive Sa6 Bits Receive Sa7 Bits Receive Sa8 Bits Transmit Channel 1 Transmit Channel 2 Transmit Channel 3 Transmit Channel 4 Transmit Channel 5 Transmit Channel 6 Transmit Channel 7 Transmit Channel 8 Transmit Channel 9 Transmit Channel 10 Transmit Channel 11 Transmit Channel 12 Transmit Channel 13 Transmit Channel 14 Transmit Channel 15 Transmit Channel 16 Transmit Channel 17 Transmit Channel 18 Transmit Channel 19 Transmit Channel 20 Transmit Channel 21 Transmit Channel 22 Transmit Channel 23 Transmit Channel 24 Transmit Channel 25 Transmit Channel 26 Transmit Channel 27 Transmit Channel 28 Transmit Channel 29 Transmit Channel 30 Transmit Channel 31 Transmit Channel 32 Receive Channel 1 Receive Channel 2 Receive Channel 3 Receive Channel 4 Receive Channel 5 Receive Channel 6 Page 25 of 109 TSa5 TSa6 TSa7 TSa8 RSiAF RSiNAF RRA RSa4 RSa5 RSa6 RSa7 RSa8 TC1 TC2 TC3 TC4 TC5 TC6 TC7 TC8 TC9 TC10 TC11 TC12 TC13 TC14 TC15 TC16 TC17 TC18 TC19 TC20 TC21 TC22 TC23 TC24 TC25 TC26 TC27 TC28 TC29 TC30 TC31 TC32 RC1 RC2 RC3 RC4 RC5 RC6 12799 Preliminary 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 DS21354 & DS21554 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W Receive Channel 7 Receive Channel 8 Receive Channel 9 Receive Channel 10 Receive Channel 11 Receive Channel 12 Receive Channel 13 Receive Channel 14 Receive Channel 15 Receive Channel 16 Receive Channel 17 Receive Channel 18 Receive Channel 19 Receive Channel 20 Receive Channel 21 Receive Channel 22 Receive Channel 23 Receive Channel 24 Receive Channel 25 Receive Channel 26 Receive Channel 27 Receive Channel 28 Receive Channel 29 Receive Channel 30 Receive Channel 31 Receive Channel 32 Transmit Channel Control 1 Transmit Channel Control 2 Transmit Channel Control 3 Transmit Channel Control 4 Receive Channel Control 1 Receive Channel Control 2 Receive Channel Control 3 Receive Channel Control 4 Common Control 4 Transmit DS0 Monitor Common Control 5 Receive DS0 Monitor Test 3 Not used Not used Not used HDLC Control Register HDLC Status Register HDLC Interrupt Mask Register Receive HDLC Information Register Receive HDLC FIFO Register Interleave Bus Operation Register Transmit HDLC Information Register Transmit HDLC FIFO Register Page 26 of 109 RC7 RC8 RC9 RC10 RC11 RC12 RC13 RC14 RC15 RC16 RC17 RC18 RC19 RC20 RC21 RC22 RC23 RC24 RC25 RC26 RC27 RC28 RC29 RC30 RC31 RC32 TCC1 TCC2 TCC3 TCC4 RCC1 RCC2 RCC3 RCC4 CCR4 TDS0M CCR5 RDS0M TEST3 (set to 00h) (set to 00h) (set to 00h) (set to 00h) HCR HSR HIMR RHIR RHFR IBO THIR THFR 12799 Preliminary B8 B9 BA BB BC BD BE BF DS21354 & DS21554 R/W R/W R/W R/W - Receive HDLC DS0 Control Register 1 Receive HDLC DS0 Control Register 2 Transmit HDLC DS0 Control Register 1 Transmit HDLC DS0 Control Register 2 Not used Not used Not used Not used RDC1 RDC2 TDC1 TDC2 (set to 00h) (set to 00h) (set to 00h) (set to 00h) NOTES: 1. Test Registers are used only by the factory; these registers must be cleared (set to all zeros) on power- up initialization to insure proper operation. 2. Register banks Cxh, Dxh, Exh, and Fxh are not accessible. Page 27 of 109 12799 Preliminary DS21354 & DS21554 4. CONTROL, ID, AND TEST REGISTERS The operation of the DS21354/554 is configured via a set of ten control registers. Typically, the control registers are only accessed when the system is first powered up. Once the device has been initialized, the control registers will only need to be accessed when there is a change in the system configuration. There are two Receive Control Register (RCR1 and RCR2), two Transmit Control Registers (TCR1 and TCR2), and six Common Control Registers (CCR1 to CCR6). Each of the ten registers are described in this section. There is a device Identification Register (IDR) at address 0Fh. The MSB of this read-only register is fixed to a one indicating that an E1 SCT is present. The next 3 MSBs are used to indicate which E1 device is present; DS2154, DS21354, or DS21554. The T1 pin-for-pin compatible SCTs will have a logic zero in the MSB position with the following 3 MSBs indicating which T1 SCT is present; DS2152, DS21352, or DS21552. DEVICE ID BIT MAP Table 4-1 represents the possible variations of these bits and the associated SCT. DEVICE ID BIT MAP Table 4-1 SCT T1/E1 bit 6 bit 5 DS2152 0 0 0 DS21352 0 0 0 DS21552 0 0 1 DS2154 1 0 0 DS21354 1 0 0 DS21554 1 0 1 The lower four bits of the IDR are used to display the die revision of the chip. bit 4 0 1 0 0 1 0 The Test registers at addresses 09, 15, 19, and AC hex are used by the factory in testing the DS21354/554. On power-up, the Test registers should be set to 00h in order for the DS21354/554 to operate properly. 4.1 Power-Up Sequence On power-up, after the supplies are stable the DS21354/554 should be configured for operation by writing to all of the internal registers (this includes setting the Test Registers to 00h) since the contents of the internal registers cannot be predicted on power-up. The LIRST (CCR5.7) should be toggled from zero to one to reset the line interface circuitry (it will take the device about 40ms to recover from the LIRST bit being toggled). Finally, after the TSYSCLK and RSYSCLK inputs are stable, the ESR bits (CCR6.0 & CCR6.1) should be toggled from a zero to a one (this step can be skipped if the elastic stores are disabled). IDR: DEVICE IDENTIFICATION REGISTER (Address=0F Hex) (MSB) T1E1 Bit 6 Bit 5 SYMBOL POSITION T1E1 IDR.7 Bit 4 ID3 ID2 ID1 (LSB) ID0 NAME AND DESCRIPTION T1 or E1 Chip Determination Bit. Set to 1. 0=T1 chip 1=E1 chip Page 28 of 109 12799 Preliminary DS21354 & DS21554 Bit 6 Bit 5 Bit 4 ID3 IDR.6 IDR.5 IDR.4 IDR.3 ID2 ID1 ID0 IDR.1 IDR.2 IDR.0 Bit 6. Bit 5. Bit 4. Chip Revision Bit 3. MSB of a decimal code that represents the chip revision. Chip Revision Bit 2. Chip Revision Bit 1. Chip Revision Bit 0. LSB of a decimal code that represents the chip revision. RCR1: RECEIVE CONTROL REGISTER 1 (Address=10 Hex) (MSB) RSMF RSM RSIO SYMBOL POSITION RSMF RCR1.7 RSM RCR1.6 RSIO RCR1.5 - - FRC RCR1.4 RCR1.3 RCR1.2 SYNCE RCR1.1 RESYNC RCR1.0 - - FRC SYNCE (LSB) RESYNC NAME AND DESCRIPTION RSYNC Multiframe Function. Only used if the RSYNC pin is programmed in the multiframe mode (RCR1.6=1). 0 = RSYNC outputs CAS multiframe boundaries 1 = RSYNC outputs CRC4 multiframe boundaries RSYNC Mode Select. 0 = frame mode (see the timing in Section17.1) 1 = multiframe mode (see the timing in Section17.1) RSYNC I/O Select. (note: this bit must be set to zero when RCR2.1=0). 0 = RSYNC is an output (depends on RCR1.6) 1 = RSYNC is an input (only valid if elastic store enabled) Not Assigned. Should be set to zero when written. Not Assigned. Should be set to zero when written. Frame Resync Criteria. 0 = resync if FAS received in error 3 consecutive times 1 = resync if FAS or bit 2 of non-FAS is received in error 3 consecutive times Sync Enable. 0 = auto resync enabled 1 = auto resync disabled Resync. When toggled from low to high, a resync is initiated. Must be cleared and set again for a subsequent resync. Page 29 of 109 12799 Preliminary DS21354 & DS21554 SYNC/RESYNC CRITERIA Table 4-2 FRAME OR MULTIFRAME LEVEL FAS SYNC CRITERIA FAS present in frame N and N + 2, and FAS not present in frame N + 1 CRC4 Two valid MF alignment words found within 8 ms Valid MF alignment word found and previous timeslot 16 contains code other than all zeros CAS RESYNC CRITERIA ITU SPEC. Three consecutive incorrect FAS received Alternate (RCR1.2=1) the above criteria is met or three consecutive incorrect bit 2 of non-FAS received 915 or more CRC4 code words out of 1000 received in error Two consecutive MF alignment words received in error G.706 4.1.1 4.1.2 G.706 4.2 and 4.3.2 G.732 5.2 RCR2: RECEIVE CONTROL REGISTER 2 (Address=11 Hex) (MSB) Sa8S Sa7S Sa6S SYMBOL POSITION Sa8S RCR2.7 Sa7S RCR2.6 Sa6S RCR2.5 Sa5S RCR2.4 Sa4S RCR2.3 RBCS RCR2.2 RESE RCR2.1 - RCR2.0 Sa5S Sa4S RBCS RESE (LSB) - NAME AND DESCRIPTION Sa8 Bit Select. Set to one to have RLCLK pulse at the Sa8 bit position; set to zero to force RLCLK low during Sa8 bit position. See Section 17.1 for timing details. Sa7 Bit Select. Set to one to have RLCLK pulse at the Sa7 bit position; set to zero to force RLCLK low during Sa7 bit position. See Section 17.1 for timing details. Sa6 Bit Select. Set to one to have RLCLK pulse at the Sa6 bit position; set to zero to force RLCLK low during Sa6 bit position. See Section 17.1 for timing details. Sa5 Bit Select. Set to one to have RLCLK pulse at the Sa5 bit position; set to zero to force RLCLK low during Sa5 bit position. See Section 17.1 for timing details. Sa4 Bit Select. Set to one to have RLCLK pulse at the Sa4 bit position; set to zero to force RLCLK low during Sa4 bit position. See Section 17.1 for timing details. Receive Side Backplane Clock Select. 0 = if RSYSCLK is 1.544 MHz 1 = if RSYSCLK is 2.048/4.096/8.192 MHz Receive Side Elastic Store Enable. 0 = elastic store is bypassed 1 = elastic store is enabled Not Assigned. Should be set to zero when written. Page 30 of 109 12799 Preliminary DS21354 & DS21554 TCR1: TRANSMIT CONTROL REGISTER 1 (Address=12 Hex) (MSB) ODF TFPT T16S SYMBOL POSITION ODF TCR1.7 TFPT TCR1.6 T16S TCR1.5 TUA1 TCR1.4 TSiS TCR1.3 TSA1 TCR1.2 TSM CR1.1 TSIO TCR1.0 TUA1 TSiS TSA1 TSM (LSB) TSIO NAME AND DESCRIPTION Output Data Format. 0 = bipolar data at TPOSO and TNEGO 1 = NRZ data at TPOSO; TNEGO=0 Transmit Timeslot 0 Pass Through. 0 = FAS bits/Sa bits/Remote Alarm sourced internally from the TAF and TNAF registers 1 = FAS bits/Sa bits/Remote Alarm sourced from TSER Transmit Timeslot 16 Data Select. 0 = sample timeslot 16 at TSER pin 1 = source timeslot 16 from TS0 to TS15 registers Transmit Unframed All Ones. 0 = transmit data normally 1 = transmit an unframed all one's code at TPOSO and TNEGO Transmit International Bit Select. 0 = sample Si bits at TSER pin 1 = source Si bits from TAF and TNAF registers (in this mode, TCR1.6 must be set to 0) Transmit Signaling All Ones. 0 = normal operation 1 = force timeslot 16 in every frame to all ones TSYNC Mode Select. 0 = frame mode (see the timing in Section 17.2) 1 = CAS and CRC4 multiframe mode (see the timing in Section 17.2) TSYNC I/O Select. 0 = TSYNC is an input 1 = TSYNC is an output NOTE: See DS21354/554 TRANSMIT DATA FLOW Figure 17-15for more details about how the Transmit Control Registers affect the operation of the DS21354/554. TCR2: TRANSMIT CONTROL REGISTER 2 (Address=13 Hex) (MSB) Sa8S Sa7S Sa6S SYMBOL POSITION Sa8S TCR2.7 Sa7S TCR2.6 Sa5S Sa4S ODM AEBE (LSB) PF NAME AND DESCRIPTION Sa8 Bit Select. Set to one to source the Sa8 bit from the TLINK pin; set to zero to not source the Sa8 bit. See Section 17.2 for timing details. Sa7 Bit Select. Set to one to source the Sa7 bit from the TLINK pin; set to zero to not source the Sa7 bit. See Section 17.2 for timing details. Page 31 of 109 12799 Preliminary DS21354 & DS21554 Sa6S TCR2.5 Sa5S TCR2.4 Sa4S TCR2.3 ODM TCR2.2 AEBE TCR2.1 PF TCR2.0 Sa6 Bit Select. Set to one to source the Sa6 bit from the TLINK pin; set to zero to not source the Sa6 bit. See Section 17.2 for timing details. Sa5 Bit Select. Set to one to source the Sa5 bit from the TLINK pin; set to zero to not source the Sa5 bit. See Section 17.2 for timing details. Sa4 Bit Select. Set to one to source the Sa4 bit from the TLINK pin; set to zero to not source the Sa4 bit. See Section 17.2 for timing details. Output Data Mode. 0 = pulses at TPOSO and TNEGO are one full TCLKO period wide 1 = pulses at TPOSO and TNEGO are 1/2 TCLKO period wide Automatic E-Bit Enable. 0 = E-bits not automatically set in the transmit direction 1 = E-bits automatically set in the transmit direction Function of RLOS/LOTC Pin. 0 = Receive Loss of Sync (RLOS) 1 = Loss of Transmit Clock (LOTC) CCR1: COMMON CONTROL REGISTER 1 (Address=14 Hex) (MSB) FLB THDB3 TG802 SYMBOL POSITION FLB CCR1.7 THDB3 CCR1.6 TG802 CCR1.5 TCRC4 CCR1.4 RSM CCR1.3 RHDB3 CCR1.2 RG802 CCR1.1 RCRC4 CCR1.0 TCRC4 RSM RHDB3 RG802 (LSB) RCRC4 NAME AND DESCRIPTION Framer Loopback. 0=loopback disabled 1=loopback enabled Transmit HDB3 Enable. 0=HDB3 disabled 1=HDB3 enabled Transmit G.802 Enable. See Section 17 for details. 0=do not force TCHBLK high during bit 1 of timeslot 26 1=force TCHBLK high during bit 1 of timeslot 26 Transmit CRC4 Enable. 0=CRC4 disabled 1=CRC4 enabled Receive Signaling Mode Select. 0=CAS signaling mode 1=CCS signaling mode Receive HDB3 Enable. 0=HDB3 disabled 1=HDB3 enabled Receive G.802 Enable. See Section 17 for details. 0=do not force RCHBLK high during bit 1 of timeslot 26 1=force RCHBLK high during bit 1 of timeslot 26 Receive CRC4 Enable. 0=CRC4 disabled 1=CRC4 enabled Page 32 of 109 12799 Preliminary DS21354 & DS21554 4.2 Framer Loopback When CCR1.7 is set to a one, the DS21354/554 will enter a Framer LoopBack (FLB) mode. See DS21354/554 Single-Chip Transceiver Figure 1-1for more details. This loopback is useful in testing and debugging applications. In FLB, the SCT will loop data from the transmit side back to the receive side. When FLB is enabled, the following will occur: 1. Data will be transmitted as normal at TPOSO and TNEGO. 2. Data input via RPOSI and RNEGI will be ignored. 3. The RCLK output will be replaced with the TCLK input. CCR2: COMMON CONTROL REGISTER 2 (Address=1A Hex) (MSB) ECUS VCRFS AAIS SYMBOL POSITION ECUS CCR2.7 VCRFS CCR2.6 AAIS CCR2.5 ARA CCR2.4 RSERC CCR2.3 LOTCMC CCR2.2 RFF CCR2.1 RFE CCR2.0 ARA RSERC LOTCMC RFF (LSB) RFE NAME AND DESCRIPTION Error Counter Update Select. See Section 6 for details. 0=update error counters once a second 1=update error counters every 62.5 ms (500 frames) VCR Function Select. See Section 6.1 for details. 0=count BiPolar Violations (BPVs) 1=count Code Violations (CVs) Automatic AIS Generation. 0=disabled 1=enabled Automatic Remote Alarm Generation. 0=disabled 1=enabled RSER Control. 0=allow RSER to output data as received under all conditions 1=force RSER to one under loss of frame alignment conditions Loss of Transmit Clock Mux Control. Determines whether the transmit side formatter should switch to the ever present RCLKO if the TCLK should fail to transition (see Figure 1-1). 0=do not switch to RCLKO if TCLK stops 1=switch to RCLKO if TCLK stops Receive Force Freeze. Freezes receive side signaling at RSIG (and RSER if CCR3.3=1); will override Receive Freeze Enable (RFE). See Section 8.2 or details. 0=do not force a freeze event 1=force a freeze event Receive Freeze Enable. See Section 8.2 for details. 0=no freezing of receive signaling data will occur 1=allow freezing of receive signaling data at RSIG (and RSER if CCR3.3=1). 4.3 Automatic Alarm Generation Page 33 of 109 12799 Preliminary DS21354 & DS21554 The device can be programmed to automatically transmit AIS or Remote Alarm. When automatic AIS generation is enabled (CCR2.5 = 1), the device monitors the receive side framer to determine if any of the following conditions are present: loss of receive frame synchronization, AIS alarm (all one's) reception, or loss of receive carrier (or signal). If any one (or more) of the above conditions is present, then the framer will either force an AIS alarm. When automatic RAI generation is enabled (CCR2.4 = 1), the framer monitors the receive side to determine if any of the following conditions are present: loss of receive frame synchronization, AIS alarm (all one's) reception, or loss of receive carrier (or signal) or if CRC4 multiframe synchronization cannot be found within 128ms of FAS synchronization (if CRC4 is enabled). If any one (or more) of the above conditions is present, then the framer will either transmit a RAI alarm. RAI generation conforms to ETS 300 011 specifications and a constant Remote Alarm will be transmitted if the DS21354/554 cannot find CRC4 multiframe synchronization within 400 ms as per G.706. CCR3: COMMON CONTROL REGISTER 3 (Address=1B Hex) (MSB) TESE TCBFS TIRFS SYMBOL POSITION TESE CCR3.7 TCBFS CCR3.6 TIRFS CCR3.5 RSRE CCR3.4 CCR3.3 TSRE CCR3.2 TBCS CCR3.1 RCLA CCR3.0 - RSRE TSRE TBCS (LSB) RCLA NAME AND DESCRIPTION Transmit Side Elastic Store Enable. 0=elastic store is bypassed 1=elastic store is enabled Transmit Channel Blocking Registers (TCBR) Function Select. 0=TCBRs define the operation of the TCHBLK output pin 1=TCBRs define which signaling bits are to be inserted Transmit Idle Registers (TIR) Function Select. See Section 9.1 for details. 0=TIRs define in which channels to insert idle code 1=TIRs define in which channels to insert data from RSER (i.e., Per=Channel Loopback function) Not Assigned. Should be set to zero when written to. Receive Side Signaling Re-Insertion Enable. See Section 8.2.1 for details. 0=do not re-insert signaling bits into the data stream presented at the RSER pin 1=re-insert the signaling bits into data stream presented at the RSER pin Transmit Side Signaling Re-Insertion Enable. See Section 8.2.2 for details. 0=do not re-insert signaling bits into the data stream presented at the TSER pin 1=re-insert the signaling bits into data stream presented at the TSER pin Transmit Side Backplane Clock Select. 0=if TSYSCLK is 1.544 MHz 1=if TSYSCLK is 2.048/4.096/8.192 MHz Receive Carrier Loss (RCL) Alternate Criteria. 0=RCL declared upon 255 consecutive zeros (125 us) 1=RCL declared upon 2048 consecutive zeros (1 ms) Page 34 of 109 12799 Preliminary DS21354 & DS21554 CCR4: COMMON CONTROL REGISTER 4 (Address=A8 Hex) (MSB) RLB LLB LIAIS SYMBOL POSITION RLB CCR4.7 LLB CCR4.6 LIAIS CCR4.5 TCM4 CCR4.4 TCM3 TCM2 TCM1 TCM0 CCR4.3 CCR4.2 CCR4.1 CCR4.0 TCM4 TCM3 TCM2 TCM1 (LSB) TCM0 NAME AND DESCRIPTION Remote Loopback. 0 = loopback disabled 1 = loopback enabled Local Loopback. 0=loopback disabled 1=loopback enabled Line Interface AIS Generation Enable. See Figure 1-1 for details. 0=allow normal data from TPOSI/TNEGI to be transmitted at TTIP and TRING 1=force unframed all ones to be transmitted at TTIP and TRING at the MCLK rate Transmit Channel Monitor Bit 4. MSB of a channel decode that determines which transmit channel data will appear in the TDS0M register. See Section 7 or details. Transmit Channel Monitor Bit 3. Transmit Channel Monitor Bit 2. Transmit Channel Monitor Bit 1. Transmit Channel Monitor Bit 0. LSB of the channel decode. 4.4 Remote Loopback When CCR4.7 is set to a one, the SCT will be forced into Remote LoopBack (RLB). In this loopback, data input via the RPOSI and RNEGI pins will be transmitted back to the TPOSO and TNEGO pins. Data will continue to pass through the receive side framer of the SCT as it would normally and the data from the transmit side formatter will be ignored. Please see Figure 1-1 for more details. 4.5 Local Loopback When CCR4.6 is set to a one, the SCT will be forced into Local LoopBack (LLB). In this loopback, data will continue to be transmitted as normal through the transmit side of the SCT. Data being received at RTIP and RRING will be replaced with the data being transmitted. Data in this loopback will pass through the jitter attenuator. Please see Figure 1-1 for more details. CCR5: COMMON CONTROL REGISTER 5 (Address=AA Hex) (MSB) LIRST RESALG N TESALG N SYMBOL POSITION LIRST CCR5.7 RCM4 RCM3 RCM2 RCM1 (LSB) RCM0 NAME AND DESCRIPTION Line Interface Reset. Setting this bit from a zero to a one will initiate an internal reset that affects the clock recovery state machine and jitter attenuator. Normally this bit is only toggled on power-up. Must be cleared and set again for a subsequent reset. Page 35 of 109 12799 Preliminary DS21354 & DS21554 RESALGN CCR5.6 TESALGN CCR5.5 RCM4 CCR5.4 RCM3 RCM2 RCM1 RCM0 CCR5.3 CCR5.2 CCR5.1 CCR5.0 Receive Elastic Store Align. Setting this bit from a zero to a one may force the receive elastic store's write/read pointers to a minim separation of half a frame. No action will be taken if the pointer separation is already greater or equal to half a frame. If pointer separation is less then half a frame, the command will be executed and data will be disrupted. Should be toggled after RSYSCLK has been applied and is stable. Must be cleared and set again for a subsequent align. See Section 11 for details. Transmit Elastic Store Align. Setting this bit from a zero to a one may force the transmit elastic store's write/read pointers to a minim separation of half a frame. No action will be taken if the pointer separation is already greater or equal to half a frame. If pointer separation is less then half a frame, the command will be executed and data will be disrupted. Should be toggled after TSYSCLK has been applied and is stable. Must be cleared and set again for a subsequent align. See Section 11 for details. Receive Channel Monitor Bit 4. MSB of a channel decode that determines which receive channel data will appear in the RDS0M register. See Section 7 for details. Receive Channel Monitor Bit 3. Receive Channel Monitor Bit 2. Receive Channel Monitor Bit 1. Receive Channel Monitor Bit 0. LSB of the channel decode. CCR6: COMMON CONTROL REGISTER 6 (Address=1D Hex) (MSB) LIUODO CDIG LIUSI SYMBOL POSITION LIUODO CCR6.7 CDIG CCR6.6 LIUSI CCR6.5 - - TCLKSR C RESR (LSB) TESR NAME AND DESCRIPTION Line Interface Open Drain Option. This control bit determines whether the TTIP and TRING outputs will be open drain or not. The line driver outputs can be forced open drain to allow 6Vpeak pulses to be generated or to allow the creation of a very low power interface. 0 = allow TTIP and TRING to operate normally 1 = force the TTIP and TRING outputs to be open drain Customer Disconnect Indication Generator. This control bit determines whether the Line Interface will generate an unframed ...1010... pattern at TTIP and TRING instead of the normal data pattern. 0 = generate normal data at TTIP & TRING as input via TPOSI & TNEGI 1 = generate a ...1010... pattern at TTIP and TRING Line Interface G.703 Synchronization Interface Enable. This control bit determines whether the line receiver should handle a normal E1 signal (Section 6 of G.703) or a 2.048MHz synchronization signal (Section 10 of G.703). This control has no affect on the line interface transmitter. 0 = line receiver configured to support a normal E1 signal 1 = line receiver configured to support a synchronization signal Page 36 of 109 12799 Preliminary DS21354 & DS21554 - - TCLKSRC CCR6.4 CCR6.3 CCR6.2 RESR CCR6.1 TESR CCR6.0 Not Assigned. Should be set to zero when written. Not Assigned. Should be set to zero when written. Transmit Clock Source Select. This function allows the user to internally select RCLK as the clock source for the transmit side formatter. 0 = Source of transmit clock determined by TCR1.7 (LOTCMC) 1 = Force transmitter to internally switch to RCLK as source of transmit clock. Signal at TCLK pin is ignored Receive Elastic Store Reset. Setting this bit from a zero to a one will force the receive elastic store to a depth of one frame. Receive data is lost during the reset. Should be toggled after RSYSCLK has been applied and is stable. Must be cleared and set again for a subsequent reset. Transmit Elastic Store Reset. Setting this bit from a zero to a one will force the transmit elastic store to a depth of one frame. Transmit data is lost during the reset. Should be toggled after TSYSCLK has been applied and is stable. Must be cleared and set again for a subsequent reset. Page 37 of 109 12799 Preliminary DS21354 & DS21554 5. STATUS AND INFORMATION REGISTERS There is a set of seven registers that contain information on the current real time status of a framer in the DS21354/554, Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register (RIR), Synchronizer status Register (SSR) and a set of three registers for the onboard HDLC controller. The specific details on the four registers pertaining to the HDLC controller are covered in Section 13 but they operate the same as the other status registers in the device and this operation is described below. When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers will be set to a one. All of the bits in SR1, SR2, and RIR1 registers operate in a latched fashion. The Synchronizer Status Register contents are not latched. This means that if an event or an alarm occurs and a bit is set to a one in any of the registers, it will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the event has occurred again (or in the case of the RUA1, RRA, RCL, and RLOS alarms, the bit will remain set if the alarm is still present). The user will always proceed a read of any of the SR1, SR2 and RIR registers with a write. The byte written to the register will inform the framer which bits the user wishes to read and have cleared. The user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read and a zero in the bit positions he or she does not wish to obtain the latest information on. When a one is written to a bit location, the read register will be updated with the latest information. When a zero is written to a bit position, the read register will not be updated and the previous value will be held. A write to the status and information registers will be immediately followed by a read of the same register. The read result should be logically AND'ed with the mask byte that was just written and this value should be written back into the same register to insure that bit does indeed clear. This second write step is necessary because the alarms and events in the status registers occur asynchronously in respect to their access via the parallel port. This write-read- write scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register. This operation is key in controlling the DS21354/554 with higher-order software languages. The SSR register operates differently than the other three. It is a read only register and it reports the status of the synchronizer in real time. This register is not latched and it is not necessary to precede a read of this register with a write. The SR1, SR2, and HSR registers have the unique ability to initiate a hardware interrupt via the INT* output pin. Each of the alarms and events in the SR1, SR2, and HSR can be either masked or unmasked from the interrupt pin via the Interrupt Mask Register 1 (IMR1), Interrupt Mask Register 2 (IMR2), and HDLC Interrupt Mask Register (HIMR) respectively. The HIMR register is covered in Section 13. The interrupts caused by alarms in SR1 (namely RUA1, RRA, RCL, and RLOS) act differently than the interrupts caused by events in SR1 and SR2 (namely RSA1, RDMA, RSA0, RSLIP, RMF, TMF, SEC, TAF, LOTC, RCMF, and TSLIP). The alarm caused interrupts will force the INT* pin low whenever the alarm changes state (i.e., the alarm goes active or inactive according to the set/clear criteria in ALARM CRITERIA Table 5-1). The INT* pin will be allowed to return high (if no other interrupts are present) when the user reads the alarm bit that caused the interrupt to occur even if the alarm is still present. The event caused interrupts will force the INT* pin low when the event occurs. The INT* pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur. Page 38 of 109 12799 Preliminary DS21354 & DS21554 RIR: RECEIVE INFORMATION REGISTER (Address=08 Hex) (MSB) TESF TESE JALT SYMBOL POSITION TESF RIR.7 TESE RIR.6 JALT RIR.5 RESF RIR.4 RESE RIR.3 CRCRC RIR.2 FASRC RIR.1 CASRC RIR.0 RESF RESE CRCRC FASRC (LSB) CASRC NAME AND DESCRIPTION Transmit Side Elastic Store Full. Set when the transmit side elastic store buffer fills and a frame is deleted. Transmit Side Elastic Store Empty. Set when the transmit side elastic store buffer empties and a frame is repeated. Jitter Attenuator Limit Trip. Set when the jitter attenuator FIFO reaches to within 4-bits of its limit; useful for debugging jitter attenuation operation. Receive Side Elastic Store Full. Set when the receive side elastic store buffer fills and a frame is deleted. Receive Side Elastic Store Empty. Set when the receive side elastic store buffer empties and a frame is repeated. CRC Resync Criteria Met. Set when 915/1000 code words are received in error. FAS Resync Criteria Met. Set when 3 consecutive FAS words are received in error. CAS Resync Criteria Met. Set when 2 consecutive CAS MF alignment words are received in error. SSR: SYNCHRONIZER STATUS REGISTER (Address=1E Hex) (MSB) CSC5 CSC4 CSC3 SYMBOL POSITION CSC5 CSC4 CSC3 CSC2 CSC0 SSR.7 SSR.6 SSR.5 SSR.4 SSR.3 FASSA SSR.2 CASSA SSR.1 CRC4SA SSR.0 CSC2 CSC0 FASSA CASSA (LSB) CRC4SA NAME AND DESCRIPTION CRC4 Sync Counter Bit 5. MSB of the 6-bit counter. CRC4 Sync Counter Bit 4. CRC4 Sync Counter Bit 3. CRC4 Sync Counter Bit 2. CRC4 Sync Counter Bit 0. LSB of the 6-bit counter. The next to LSB is not accessible. FAS Sync Active. Set while the synchronizer is searching for alignment at the FAS level. CAS MF Sync Active. Set while the synchronizer is searching for the CAS MF alignment word. CRC4 MF Sync Active. Set while the synchronizer is searching for the CRC4 MF alignment word. 5.1 CRC4 Sync Counter The CRC4 Sync Counter increments each time the 8 ms CRC4 multiframe search times out. The counter is cleared when the framer has successfully obtained synchronization at the CRC4 level. The counter can also be cleared by disabling the CRC4 mode (CCR1.0=0). This counter is useful for determining the Page 39 of 109 12799 Preliminary DS21354 & DS21554 amount of time the framer has been searching for synchronization at the CRC4 level. ITU G.706 suggests that if synchronization at the CRC4 level cannot be obtained within 400 ms, then the search should be abandoned and proper action taken. The CRC4 Sync Counter will rollover. SR1: STATUS REGISTER 1 (Address=06 Hex) (MSB) RSA1 RDMA RSA0 SYMBOL POSITION RSA1 SR1.7 RDMA SR1.6 RSA0 SR1.5 RSLIP SR1.4 RUA1 SR1.3 RRA SR1.2 RCL SR1.1 RLOS SR1.0 RSLIP RUA1 RRA RCL (LSB) RLOS NAME AND DESCRIPTION Receive Signaling All Ones / Signaling Change. Set when the contents of timeslot 16 contains less than three zeros over 16 consecutive frames. This alarm is not disabled in the CCS signaling mode. Both RSA1 and RSA0 will be set if a change in signaling is detected. Receive Distant MF Alarm. Set when bit-6 of timeslot 16 in frame 0 has been set for two consecutive multiframes. This alarm is not disabled in the CCS signaling mode. Receive Signaling All Zeros / Signaling Change. Set when over a full MF, timeslot 16 contains all zeros. Both RSA1 and RSA0 will be set if a change in signaling is detected. Receive Side Elastic Store Slip. Set when the elastic store has either repeated or deleted a frame of data. Receive Unframed All Ones. Set when an unframed all ones code is received at RPOSI and RNEGI. Receive Remote Alarm. Set when a remote alarm is received at RPOSI and RNEGI. Receive Carrier Loss. Set when 255 (or 2048 if CCR3.0=1) consecutive zeros have been detected at RTIP and RRING. (note: a receiver carrier loss based on data received at RPOSI and RNEGI is available in the HSR register) Receive Loss of Sync. Set when the device is not synchronized to the receive E1 stream. ALARM CRITERIA Table 5-1 ALARM SET CRITERIA CLEAR CRITERIA RSA1 (receive signaling all ones) over 16 consecutive frames (one full MF) timeslot 16 contains less than three zeros over 16 consecutive frames (one full MF) timeslot 16 contains all zeros bit 6 in timeslot 16 of frame 0 set to one for two consecutive MF less than three zeros in two frames (512-bits) bit 3 of non-align frame set to one for three consecutive occasions over 16 consecutive frames (one full MF) timeslot 16 contains three or more zeros over 16 consecutive frames (one full MF) timeslot 16 contains at least a single one bit 6 in timeslot 16 of frame 0 set to zero for two consecutive MF more than two zeros in two frames (512-bits) bit 3 of non-align frame set to zero for three consecutive occasions RSA0 (receive signaling all zeros) RDMA (receive distant multiframe alarm) RUA1 (receive unframed all ones) RRA (receive remote alarm) Page 40 of 109 ITU SPEC. G.732 4.2 G.732 5.2 O.162 2.1.5 O.162 1.6.1.2 O.162 2.1.4 12799 Preliminary DS21354 & DS21554 255 (or 2048) consecutive zeros received RCL (receive carrier loss) in 255-bit times, at least 32 ones are received G.775 / G.962 SR2: STATUS REGISTER 2 (Address=07 Hex) (MSB) RMF RAF TMF SYMBOL POSITION RMF SR2.7 RAF SR2.6 TMF SR2.5 SEC SR2.4 TAF SR2.3 LOTC SR2.2 RCMF SR2.1 TSLIP SR2.0 SEC TAF LOTC RCMF (LSB) TSLIP NAME AND DESCRIPTION Receive CAS Multiframe. Set every 2 ms (regardless if CAS signaling is enabled or not) on receive multiframe boundaries. Used to alert the host that signaling data is available. Receive Align Frame. Set every 250 s at the beginning of align frames. Used to alert the host that Si and Sa bits are available in the RAF and RNAF registers. Transmit Multiframe. Set every 2 ms (regardless if CRC4 is enabled) on transmit multiframe boundaries. Used to alert the host that signaling data needs to be updated. One Second Timer. Set on increments of one second based on RCLK. If CCR2.7=1, then this bit will be set every 62.5 ms instead of once a second. Transmit Align Frame. Set every 250 s at the beginning of align frames. Used to alert the host that the TAF and TNAF registers need to be updated. Loss of Transmit Clock. Set when the TCLK pin has not transitioned for one channel time (or 3.9 s). Will force the LOTC pin high if enabled via TCR2.0. Receive CRC4 Multiframe. Set on CRC4 multiframe boundaries; will continue to be set every 2 ms on an arbitrary boundary if CRC4 is disabled. Transmit Elastic Store Slip. Set when the elastic store has either repeated or deleted a frame of data. IMR1: INTERRUPT MASK REGISTER 1 (Address=16 Hex) (MSB) RSA1 RDMA RSA0 SYMBOL POSITION RSA1 IMR1.7 RDMA IMR1.6 RSA0 IMR1.5 RSLIP RUA1 RRA RCL (LSB) RLOS NAME AND DESCRIPTION Receive Signaling All Ones / Signaling Change. 0=interrupt masked 1=interrupt enabled Receive Distant MF Alarm. 0=interrupt masked 1=interrupt enabled Receive Signaling All Zeros / Signaling Change. 0=interrupt masked 1=interrupt enabled Page 41 of 109 12799 Preliminary DS21354 & DS21554 RSLIP IMR1.4 RUA1 IMR1.3 RRA IMR1.2 RCL IMR1.1 RLOS IMR1.0 Receive Elastic Store Slip Occurrence. 0=interrupt masked 1=interrupt enabled Receive Unframed All Ones. 0=interrupt masked 1=interrupt enabled Receive Remote Alarm. 0=interrupt masked 1=interrupt enabled Receive Carrier Loss. 0=interrupt masked 1=interrupt enabled Receive Loss of Sync. 0=interrupt masked 1=interrupt enabled IMR2: INTERRUPT MASK REGISTER 2 (Address=17 Hex) (MSB) RMF RAF TMF SYMBOL POSITION RMF IMR2.7 RAF IMR2.6 TMF IMR2.5 SEC IMR2.4 TAF IMR2.3 LOTC IMR2.2 RCMF IMR2.1 TSLIP IMR2.0 SEC TAF LOTC RCMF (LSB) TSLIP NAME AND DESCRIPTION Receive CAS Multiframe. 0=interrupt masked 1=interrupt enabled Receive Align Frame. 0=interrupt masked 1=interrupt enabled Transmit Multiframe. 0=interrupt masked 1=interrupt enabled One Second Timer. 0=interrupt masked 1=interrupt enabled Transmit Align Frame. 0=interrupt masked 1=interrupt enabled Loss Of Transmit Clock. 0=interrupt masked 1=interrupt enabled Receive CRC4 Multiframe. 0=interrupt masked 1=interrupt enabled Transmit Side Elastic Store Slip Occurrence. 0=interrupt masked 1=interrupt enabled Page 42 of 109 12799 Preliminary DS21354 & DS21554 6. ERROR COUNT REGISTERS There are a set of four counters in the DS21354/554 that record bipolar or code violations, errors in the CRC4 SMF code words, E bits as reported by the far end, and word errors in the FAS. Each of these four counters are automatically updated on either one second boundaries (CCR2.7=0) or every 62.5 ms (CCR2.7=1) as determined by the timer in Status Register 2 (SR2.4). Hence, these registers contain performance data from either the previous second or the previous 62.5 ms. The user can use the interrupt from the one second timer to determine when to read these registers. The user has a full second (or 62.5 ms) to read the counters before the data is lost. All four counters will saturate at their respective maximum counts and they will not rollover. 6.1 BPV or Code Violation Counter Violation Count Register 1 (VCR1) is the most significant word and VCR2 is the least significant word of a 16-bit counter that records either BiPolar Violations (BPVs) or Code Violations (CVs). If CCR2.6=0, then the VCR counts bipolar violations. Bipolar violations are defined as consecutive marks of the same polarity. In this mode, if the HDB3 mode is set for the receive side via CCR1.2, then HDB3 code words are not counted as BPVs. If CCR2.6=1, then the VCR counts code violations as defined in ITU O.161. Code violations are defined as consecutive bipolar violations of the same polarity. In most applications, the framer should be programmed to count BPVs when receiving AMI code and to count CVs when receiving HDB3 code. This counter increments at all times and is not disabled by loss of sync conditions. The counter saturates at 65,535 and will not rollover. The bit error rate on an E1 line would have to be greater than 10** -2 before the VCR would saturate. VCR1: UPPER BIPOLAR VIOLATION COUNT REGISTER 1 (Address=00 Hex) VCR2: LOWER BIPOLAR VIOLATION COUNT REGISTER 2 (Address=01 Hex) (MSB) V15 V7 SYMBOL V15 V0 V14 V6 V13 V5 POSITION VCR1.7 VCR2.0 V12 V4 V11 V3 V10 V2 V9 V1 (LSB) V8 V0 VCR1 VCR2 NAME AND DESCRIPTION MSB of the 16-bit code violation count LSB of the 16-bit code violation count 6.2 CRC4 Error Counter CRC4 Count Register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant word of a 10-bit counter that records word errors in the Cyclic Redundancy Check 4 (CRC4). Since the maximum CRC4 count in a one second period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it will continue to count if loss of multiframe sync occurs at the CAS level. Page 43 of 109 12799 Preliminary DS21354 & DS21554 CRCCR1: CRC4 COUNT REGISTER 1 (Address=02 Hex) CRCCR2: CRC4 COUNT REGISTER 2 (Address=03 Hex) (MSB) (note 1) CRC7 (note 1) CRC6 (note 1) CRC5 (note 1) CRC4 (note 1) CRC/3 (note 1) CRC2 CRC9 CRC1 SYMBOL POSITION NAME AND DESCRIPTION CRC9 CRC0 CRCCR1.1 CRCCR2.0 MSB of the 10-Bit CRC4 error count LSB of the 10-Bit CRC4 error count (LSB) CRC8 CRC0 CRCCR1 CRCCR2 NOTE: 1. The upper six bits of CRCCR1 at address 02 are the most significant bits of the 12-bit FAS error counter. 6.3 E-Bit Counter E-bit Count Register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of a 10-bit counter that records Far End Block Errors (FEBE) as reported in the first bit of frames 13 and 15 on E1 lines running with CRC4 multiframe. These count registers will increment once each time the received E-bit is set to zero. Since the maximum E-bit count in a one second period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it will continue to count if loss of multiframe sync occurs at the CAS level. EBCR1: E-BIT COUNT REGISTER 1 (Address=04 Hex) EBCR2: E-BIT COUNT REGISTER 2 (Address=05 Hex) (MSB) (note 1) EB7 (note 1) EB6 (note 1) EB5 SYMBOL POSITION EB9 EB0 EBCR1.1 EBCR2.0 (note 1) EB4 (note 1) EB3 (note 1) EB2 EB9 EB1 (LSB) EB8 EB0 EBCR1 EBCR2 NAME AND DESCRIPTION MSB of the 10-Bit E-Bit Error Count LSB of the 10-Bit E-Bit Error Count NOTE: The upper six bits of EBCR1 at address 04 are the least significant bits of the 12-bit FAS error counter. 6.4 FAS Error Counter FAS Count Register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word of a 12-bit counter that records word errors in the Frame Alignment Signal in timeslot 0. This counter is disabled when RLOS is high. FAS errors will not be counted when the framer is searching for FAS alignment and/or synchronization at either the CAS or CRC4 multiframe level. Since the maximum FAS word error count in a one second period is 4000, this counter cannot saturate. Page 44 of 109 12799 Preliminary DS21354 & DS21554 FASCR1: FAS ERROR COUNT REGISTER 1 (Address=02 Hex) FASCR2: FAS ERROR COUNT REGISTER 2 (Address=04 Hex) (MSB) FAS11 FAS5 FAS10 FAS4 FAS9 FAS3 FAS8 FAS2 FAS7 FAS1 FAS6 FAS0 (note 2) (note 1) SYMBOL POSITION NAME AND DESCRIPTION FAS11 FAS0 FASCR1.7 FASCR2.2 MSB of the 12-Bit FAS Error Count LSB of the 12-Bit FAS Error Count (LSB) (note 2) (note 1) FASCR1 FASCR2 NOTES: 1. The lower two bits of FASCR1 at address 02 are the most significant bits of the 10-bit CRC4 error counter. 2. The lower two bits of FASCR2 at address 04 are the most significant bits of the 10-bit E-Bit counter. Page 45 of 109 12799 Preliminary DS21354 & DS21554 7. DS0 MONITORING FUNCTION Each framer in the DS21354/554 has the ability to monitor one DS0 (64kbps) channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction the user will determine which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the CCR4 register. In the receive direction, the RCM0 to RCM4 bits in the CCR5 register need to be properly set. The DS0 channel pointed to by the TCM0 to TCM4 bits will appear in the Transmit DS0 Monitor (TDS0M) register and the DS0 channel pointed to by the RCM0 to RCM4 bits will appear in the Receive DS0 (RDS0M) register. The TCM4 to TCM0 and RCM4 to RCM0 bits should be programmed with the decimal decode of the appropriate E1 channel. For example, if DS0 channel 6 in the transmit direction and DS0 channel 15 in the receive direction needed to be monitored, then the following values would be programmed into CCR5 and CCR6: TCM4 = 0 TCM3 = 0 TCM2 = 1 TCM1 = 0 TCM0 = 1 RCM4 = 0 RCM3 = 1 RCM2 = 1 RCM1 = 1 RCM0 = 0 CCR4: COMMON CONTROL REGISTER 4 (Address=A8 Hex) [Repeated here from section 4 for convenience] (MSB) RLB LLB LIAIS SYMBOL POSITION RLB LLB LIAIS TCM4 CCR4.7 CCR4.6 CCR4.5 CCR4.4 TCM3 TCM2 TCM1 TCM0 CCR4.3 CCR4.2 CCR4.1 CCR4.0 TCM4 TCM3 TCM2 TCM1 (LSB) TCM0 NAME AND DESCRIPTION Remote Loopback. Local Loopback. Line Interface AIS Generation Enable. Transmit Channel Monitor Bit 4. MSB of a channel decode that determines which transmit channel data will appear in the TDS0M register. See Section 7 or details. Transmit Channel Monitor Bit 3. Transmit Channel Monitor Bit 2. Transmit Channel Monitor Bit 1. Transmit Channel Monitor Bit 0. LSB of the channel decode. TDS0M: TRANSMIT DS0 MONITOR REGISTER (Address=A9 Hex) (MSB) B1 B2 SYMBOL POSITION B1 TDS0M.7 B2 B3 B4 B5 TDS0M.6 TDS0M.5 TDS0M.4 TDS0M.3 B3 B4 B5 B6 B7 (LSB) B8 NAME AND DESCRIPTION Transmit DS0 Channel Bit 1. MSB of the DS0 channel (first bit to be transmitted). Transmit DS0 Channel Bit 2. Transmit DS0 Channel Bit 3. Transmit DS0 Channel Bit 4. Transmit DS0 Channel Bit 5. Page 46 of 109 12799 Preliminary B6 B7 B8 DS21354 & DS21554 TDS0M.2 TDS0M.1 TDS0M.0 Transmit DS0 Channel Bit 6. Transmit DS0 Channel Bit 7. Transmit DS0 Channel Bit 8. LSB of the DS0 channel (last bit to be transmitted). CCR5: COMMON CONTROL REGISTER 5 (Address=AA Hex) [Repeated here from section 4 for convenience] (MSB) LIRST RESALG N TESALG N SYMBOL POSITION LIRST RESALGN TESALGN RCM4 CCR5.7 CCR5.6 CCR5.5 CCR5.4 RCM3 RCM2 RCM1 RCM0 CCR5.3 CCR5.2 CCR5.1 CCR5.0 RCM4 RCM3 RCM2 RCM1 (LSB) RCM0 NAME AND DESCRIPTION Line Interface Reset. Receive Elastic Store Align. Transmit Elastic Store Align. Receive Channel Monitor Bit 4. MSB of a channel decode that determines which receive channel data will appear in the RDS0M register. See Section 7 for details. Receive Channel Monitor Bit 3. Receive Channel Monitor Bit 2. Receive Channel Monitor Bit 1. Receive Channel Monitor Bit 0. LSB of the channel decode. RDS0M: RECEIVE DS0 MONITOR REGISTER (Address=AB Hex) (MSB) B1 B2 SYMBOL POSITION B1 RDS0M.7 B2 B3 B4 B5 B6 B7 B8 RDS0M.6 RDS0M.5 RDS0M.4 RDS0M.3 RDS0M.2 RDS0M.1 RDS0M.0 B3 B4 B5 B6 B7 (LSB) B8 NAME AND DESCRIPTION Receive DS0 Channel Bit 1. MSB of the DS0 channel (first bit received). Receive DS0 Channel Bit 2. Receive DS0 Channel Bit 3. Receive DS0 Channel Bit 4. Receive DS0 Channel Bit 5. Receive DS0 Channel Bit 6. Receive DS0 Channel Bit 7. Receive DS0 Channel Bit 8. LSB of the DS0 channel (last bit received). Page 47 of 109 12799 Preliminary DS21354 & DS21554 8. SIGNALING OPERATION The DS21354/554 contains provisions for both processor based (i.e., software based) signaling bit access and for hardware based access. Both the processor based access and the hardware based access can be used simultaneously if necessary. The processor based signaling is covered in Section 8.1 and the hardware based signaling is covered in Section 8.2. 8.1 Processor Based Signaling The Channel Associated Signaling (CAS) bits embedded in the E1 stream can be extracted from the receive stream and inserted into the transmit stream by the framer. Each of the 30 voice channels has four signaling bits (A/B/C/D) associated with it. The numbers in parenthesis () are the voice channel associated with a particular signaling bit. The voice channel numbers have been assigned as described in the ITU documents. Please note that this is different than the channel numbering scheme (1 to 32) that is used in the rest of the data sheet. For example, voice channel 1 is associated with timeslot 1 (Channel 2) and voice Channel 30 is associated with timeslot 31 (Channel 32). There is a set of 16 registers for the receive side (RS1 to RS16) and 16 registers on the transmit side (TS1 to TS16). The signaling registers are detailed below. RS1 TO RS16: RECEIVE SIGNALING REGISTERS (Address=30 to 3F Hex) (MSB) 0 A(1) A(2) A(3) A(4) A(5) A(6) A(7) A(8) A(9) A(10) A(11) A(12) A(13) A(14) A(15) 0 B(1) B(2) B(3) B(4) B(5) B(6) B(7) B(8) B(9) B(10) B(11) B(12) B(13) B(14) B(15) 0 C(1) C(2) C(3) C(4) C(5) C(6) B(7) C(8) C(9) C(10) C(11) C(12) C(13) C(14) C(15) SYMBOL POSITION X Y A(1) D(30) RS1.0/1/3 RS1.2 RS2.7 1. RS16.0 0 D(1) D(2) D(3) D(4) D(5) D(6) B(7) D(8) D(9) D(10) D(11) D(12) D(13) D(14) D(15) X A(16) A(17) A(18) A(19) A(20) A(21) B(22) A(23) A(24) A(25) A(26) A(27) A(28) A(29) A(30) Y B(16) B(17) B(18) B(19) B(20) B(21) B(22) B(23) B(24) B(25) B(26) B(27) B(28) B(29) B(30) X C(16) C(17) C(18) C(19) C(20) C(21) B(22) C(23) C(24) C(25) C(26) C(27) C(28) C(29) C(30) (LSB) X D(16) D(17) D(18) D(19) D(20) D(21) B(22) D(23) D(24) D(25) D(26) D(27) D(28) D(29) D(30) RS1 (30) RS2 (31) RS3 (32) RS3 (33) RS5 (34) RS6 (35) RS7 (36) RS8 (37) RS9 (38) RS10 (39) RS11 (3A) RS12 (3B) RS13 (3C) RS14 (3D) RS15 (3E) RS16 (3F) NAME AND DESCRIPTION Spare Bits. Remote Alarm Bit (integrated and reported in SR1.6). Signaling Bit A for Channel 1 Signaling Bit D for Channel 30. Each Receive Signaling Register (RS1 to RS16) reports the incoming signaling from two timeslots. The bits in the Receive Signaling Registers are updated on multiframe boundaries so the user can utilize the Receive Multiframe Interrupt in the Receive Status Register 2 (SR2.7) to know when to retrieve the signaling bits. The user has a full 2 ms to retrieve the signaling bits before the data is lost. The RS Page 48 of 109 12799 Preliminary DS21354 & DS21554 registers are updated under all conditions. Their validity should be qualified by checking for synchronization at the CAS level. In CCS signaling mode, RS1 to RS16 can also be used to extract signaling information. Via the SR2.7 bit, the user will be informed when the signaling registers have been loaded with data. The user has 2 ms to retrieve the data before it is lost. The signaling data reported in RS1 to RS16 is also available at the RSIG and RSER pins. A change in the signaling bits from one multiframe to the next will cause the RSA1 (SR1.7) and RSA0 (SR1.5) status bits to be set at the same time. The user can enable the INT* pin to toggle low upon detection of a change in signaling by setting either the IMR1.7 or IMR1.5 bit. Once a signaling change has been detected, the user has at least 1.75 ms to read the data out of the RS1 to RS16 registers before the data will be lost. TS1 TO TS16: TRANSMIT SIGNALING REGISTERS (Address=40 to 4F Hex) (MSB) 0 A(1) A(2) A(3) A(4) A(5) A(6) A(7) A(8) A(9) A(10) A(11) A(12) A(13) A(14) A(15) 0 B(1) B(2) B(3) B(4) B(5) B(6) B(7) B(8) B(9) B(10) B(11) B(12) B(13) B(14) B(15) 0 C(1) C(2) C(3) C(4) C(5) C(6) B(7) C(8) C(9) C(10) C(11) C(12) C(13) C(14) C(15) SYMBOL POSITION X Y A(1) D(30) TS1.0/1/3 TS1.2 TS2.7 1. TS16.0 0 D(1) D(2) D(3) D(4) D(5) D(6) B(7) D(8) D(9) D(10) D(11) D(12) D(13) D(14) D(15) X A(16) A(17) A(18) A(19) A(20) A(21) B(22) A(23) A(24) A(25) A(26) A(27) A(28) A(29) A(30) Y B(16) B(17) B(18) B(19) B(20) B(21) B(22) B(23) B(24) B(25) B(26) B(27) B(28) B(29) B(30) X C(16) C(17) C(18) C(19) C(20) C(21) B(22) C(23) C(24) C(25) C(26) C(27) C(28) C(29) C(30) (LSB) X D(16) D(17) D(18) D(19) D(20) D(21) B(22) D(23) D(24) D(25) D(26) D(27) D(28) D(29) D(30) TS1 (40) TS2 (41) TS3 (42) TS4 (43) TS5 (44) TS6 (45) TS7 (46) TS8 (47) TS9 (48) TS10 (49) TS11 (4A) TS12 (4B) TS13 (4C) TS14 (4D) TS15 (4E) TS16 (4F) NAME AND DESCRIPTION Spare Bits. Remote Alarm Bit (integrated and reported in SR1.6). Signaling Bit A for Channel 1 Signaling Bit D for Channel 30. Each Transmit Signaling Register (TS1 to TS16) contains the CAS bits for two timeslots that will be inserted into the outgoing stream if enabled to do so via TCR1.5. On multiframe boundaries, the framer will load the values present in the Transmit Signaling Register into an outgoing signaling shift register that is internal to the device. The user can utilize the Transmit Multiframe bit in Status Register 2 (SR2.5) to know when to update the signaling bits. The bit will be set every 2 ms and the user has 2 ms to update the TSR's before the old data will be retransmitted. ITU specifications recommend that the ABCD signaling not be set to all zeros because they will emulate a CAS multiframe alignment word. Page 49 of 109 12799 Preliminary DS21354 & DS21554 The TS1 register is special because it contains the CAS multiframe alignment word in its upper nibble. The upper nibble must always be set to 0000 or else the terminal at the far end will lose multiframe synchronization. If the user wishes to transmit a multiframe alarm to the far end, then the TS1.2 bit should be set to a one. If no alarm is to be transmitted, then the TS1.2 bit should be cleared. The three remaining bits in TS1 are the spare bits. If they are not used, they should be set to one. In CCS signaling mode, TS1 to TS16 can also be used to insert signaling information. Via the SR2.5 bit, the user will be informed when the signaling registers need to be loaded with data. The user has 2 ms to load the data before the old data will be retransmitted. Via the CCR3.6 bit, the user has the option to use the Transmit Channel Blocking Registers (TCBRs) to determine on a channel by channel basis, which signaling bits are to be inserted via the TSRs (the corresponding bit in the TCBRs=1) and which are to be sourced from the TSER or TSIG pin (the corresponding bit in the TCBRs=0). See DS21354/554 TRANSMIT DATA FLOW Figure 17-15 for more details. 8.2 Hardware Based Signaling 8.2.1 Receive Side In the receive side of the hardware based signaling, there are two operating modes for the signaling buffer; signaling extraction and signaling re-insertion. Signaling extraction involves pulling the signaling bits from the receive data stream and buffering them over a four multiframe buffer and outputting them in a serial PCM fashion on a channel-by-channel basis at the RSIG output. This mode is always enabled. In this mode, the receive elastic store may be enabled or disabled. If the receive elastic store is enabled, then the backplane clock (RSYSCLK) must be 2.048/4.096/8.192 MHz. The ABCD signaling bits are output on RSIG in the lower nibble of each channel. The RSIG data is updated once a multiframe (2 ms) unless a freeze is in effect. See the timing diagrams in Section 17.1 for some examples. The other hardware based signaling operating mode called signaling re-insertion can be invoked by setting the RSRE control bit high (CCR3.3=1). In this mode, the user will provide a multiframe sync at the RSYNC pin and the signaling data be re-aligned at the RSER output according to this applied multiframe boundary. in this mode, the elastic store must be enabled the backplane clock must be 2.048/4.096/8.192 MHz. The signaling data in the two multiframe buffer will be frozen in a known good state upon either a loss of synchronization (OOF event), carrier loss, or frame slip. To allow this freeze action to occur, the RFE control bit (CCR2.0) should be set high. The user can force a freeze by setting the RFF control bit (CCR2.1) high. Setting the RFF bit high causes the same freezing action as if a loss of synchronization, carrier loss, or slip has occurred. The 2 multiframe buffer provides an approximate 1 multiframe delay in the signaling bits provided at the RSIG pin (and at the RSER pin if RSRE=1 via CCR3.3). When freezing is enabled (RFE=1), the signaling data will be held in the last known good state until the corrupting error condition subsides. When the error condition sub-sides, the signaling data will be held in the old state for an additional 3 ms to 5 ms before being allowed to be updated with new signaling data. 8.2.2 Transmit Side Via the TSRE control bit (CCR3.2), the DS21354/554 can be set up to take the signaling data presented at the TSIG pin and re-insert the signaling data into the PCM data stream that is being input at the TSER pin. The signaling re-insertion capabilities of each framer are available whether the transmit side elastic store is enabled or disabled. If the transmit side elastic store is enabled, the backplane clock (TSYSCLK) must be 2.048/4.096/8.192 MHz. Page 50 of 109 12799 Preliminary DS21354 & DS21554 When signaling re-insertion is enabled on a framer (TSRE=1), then the user must enable the Transmit Channel Blocking Register Function Select (TCBFS) control bit (CCR3.6=1). This is needed so that the CAS multiframe alignment word, multiframe remote alarm, and spare bits can be added to timeslot 16 in frame 0 of the multiframe. The TS1 register should be programmed with the proper information. If CCR3.6=1, then a zero in the TCBRs implies that signaling data is to be sourced from TSER (or TSIG if CCR3.2=1) and a one implies that signaling data for that channel is to be sourced from the Transmit Signaling (TS) registers. See definition below. TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3.6=1 (MSB) CH20 CH24 CH28 CH32 CH4 CH8 CH12 CH16 CH19 CH23 CH27 CH31 CH3 CH7 CH11 CH15 CH18 CH22 CH26 CH30 CH2 CH6 CH10 CH14 CH17* CH21 CH25 CH29 (LSB) CH1* CH5 CH9 CH13 TCBR1(22) TCBR2(23) TCBR3(24) TCBR4(25) *=CH1 and CH17 should be set to one to allow the internal TS1 register to create the CAS Multiframe Alignment Word and Spare/Remote Alarm bits. The user can also take advantage of this functionality to intermix signaling data from the TSIG pin and from the internal Transmit Signaling Registers (TS1 to TS16). As an example, assume that the user wishes to source all the signaling data except for voice channels 5 and 10 from the TSIG pin. In this application, the following bits and registers would be programmed as follows: CONTROL BITS TSRE = 1 (CCR3.2) TCBFS = 1 (CCR3.6) T16S = 0 (TCR1.5) REGISTER VALUES TS1=0Bh (MF alignment word, remote alarm etc.) TCBR1=03h (source timeslot 16, frame 1 data) TCBR2=01h (source voice Channel 5 signaling data from TS6) CBR3=04h (source voice Channel 10 signaling data from TS11) TCBR4=00h Page 51 of 109 12799 Preliminary DS21354 & DS21554 9. PER-CHANNEL CODE GENERATION AND LOOPBACK The DS21354/554 can replace data on a channel-by-channel basis in both the transmit and receive directions. The transmit direction is from the backplane to the E1 line and is covered in Section 9.1. The receive direction is from the E1 line to the backplane and is covered in Section 9.2. 9.1 Transmit Side Code Generation In the transmit direction there are two methods by which channel data from the backplane can be overwritten with data generated by the framer. The first method which is covered in Section 9.1.1was a feature contained in the original DS2153 while the second method which is covered in Section 9.1.2 is a new feature of the DS2154/354/554. 9.1.1 Simple Idle Code Insertion and Per-Channel Loopback The first method involves using the Transmit Idle Registers (TIR1/2/3/4) to determine which of the 32 E1 channels should be overwritten with the code placed in the Transmit Idle Definition Register (TIDR). This method allows the same 8-bit code to be placed into any of the 32 E1 channels. If this method is used, then the CCR3.5 control bit must be set to zero. Each of the bit position in the Transmit Idle Registers (TIR1/TIR2/TIR3/TIR4) represent a DS0 channel in the outgoing frame. When these bits are set to a one, the corresponding channel will transmit the Idle Code contained in the Transmit Idle Definition Register (TIDR). The Transmit Idle Registers (TIRs) have an alternate function that allow them to define a Per-Channel LoopBack (PCLB). If the TIRFS control bit (CCR3.5) is set to one, then the TIRs will determine which channels (if any) from the backplane should be replaced with the data from the receive side or in other words, off of the E1 line. If this mode is enabled, then transmit and receive clocks and frame syncs must be synchronized. One method to accomplish this would be to tie RCLK to TCLK and RFSYNC to TSYNC. There are no restrictions on which channels can be looped back or on how many channels can be looped back. TIR1/TIR2/TIR3: TRANSMIT IDLE REGISTERS (Address=26 to 29 Hex) [Also used for Per-Channel Loopback] (MSB) CH8 CH16 CH24 CH32 CH7 CH15 CH23 CH31 CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 (LSB) CH1 CH9 CH17 CH25 SYMBOLS POSITIONS NAME AND DESCRIPTION CH1 - 32 TIR1.0 - 4.7 Transmit Idle Code Insertion Control Bits. 0 = do not insert the Idle Code in the TIDR into this channel 1 = insert the Idle Code in the TIDR into this channel TIR1 (26) TIR2 (27) TIR3 (28) TIR4 (29) NOTE: If CCR3.5=1, then a zero in the TIRs implies that channel data is to be sourced from TSER and a one implies that channel data is to be sourced from the output of the receive side framer (i.e., Per-Channel Loopback; see Figure 1-1). Page 52 of 109 12799 Preliminary DS21354 & DS21554 TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address=2A Hex) (MSB) TIDR7 TIDR6 TIDR5 SYMBOL POSITION TIDR7 TIDR0 TIDR.7 TIDR.0 TIDR4 TIDR3 TIDR2 TIDR1 (LSB) TIDR0 NAME AND DESCRIPTION MSB of the Idle Code (this bit is transmitted first) LSB of the Idle Code (this bit is transmitted last) 9.1.2 Per-Channel Code Insertion The second method involves using the Transmit Channel Control Registers (TCC1/2/3/4) to determine which of the 32 E1 channels should be overwritten with the code placed in the Transmit Channel Registers (TC1 to TC32). This method is more flexible than the first in that it allows a different 8-bit code to be placed into each of the 32 E1 channels. TC1 TO TC32: TRANSMIT CHANNEL REGISTERS (Address=60 to 7F Hex) (for brevity, only channel one is shown; see for other register address) (MSB) C7 C6 C5 SYMBOL POSITION C7 C0 TC1.7 TC1.0 C4 C3 C2 C1 (LSB) C0 TC1 (60) NAME AND DESCRIPTION MSB of the Code (this bit is transmitted first) LSB of the Code (this bit is transmitted last) TCC1/TCC2/TCC3/TCC4: TRANSMIT CHANNEL CONTROL REGISTER (Address=A0 to A3 Hex) (MSB) CH8 CH16 CH24 CH32 CH7 CH15 CH23 CH31 CH6 CH14 CH22 CH30 SYMBOL POSITION CH 32 TCC4.7 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 (LSB) CH1 CH9 CH17 CH25 TCC1 (A0) TCC2 (A1) TCC3 (A2) TCC4 (A3) NAME AND DESCRIPTION Transmit Channel 32Code Insertion Control Bits 0=do not insert data from the TC register into the transmit data stream 1 = insert data from the TC register into the transmit data stream 9.2 Receive Side Code Generation On the receive side, the Receive Channel Control Registers (RCC1/2/3/4) are used to determine which of the 32 E1 channels off of the E1 line and going to the backplane should be overwritten with the code placed in the Receive Channel Registers (RC1 to RC32). This method allows a different 8-bit code to be placed into each of the 32 E1 channels. Page 53 of 109 12799 Preliminary DS21354 & DS21554 RC1 TO RC32: RECEIVE CHANNEL REGISTERS (Address = 80 to 9F Hex) (for brevity, only channel one is shown; see Register Map Sorted by Address Table 3-1 for other register address) (MSB) C7 SYMBOL C7 C0 C6 C5 POSITION RC1.7 RC1.0 C4 C3 C2 C1 (LSB) C0 RC1 (80) NAME AND DESCRIPTION MSB of the Code (this bit is sent first to the backplane) LSB of the Code (this bit is sent last to the backplane) RCC1/RCC2/RCC3/RCC4: RECEIVE CHANNEL CONTROL REGISTER (Address = A4 to A7 Hex) (MSB) CH8 CH16 CH24 CH32 SYMBOL CH1 CH7 CH15 CH23 CH31 CH6 CH14 CH22 CH30 POSITION RCC1.0 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 (LSB) CH1 CH9 CH17 CH25 RCC1 (A4) RCC2 (A5) RCC3 (A6) RCC4 (A7) NAME AND DESCRIPTION Receive Channel 1 Code Insertion Control Bits 0 = do not insert data from the RC1 register into the receive data stream 1 = insert data from the RC1 register into the receive data stream Page 54 of 109 12799 Preliminary DS21354 & DS21554 10. CLOCK BLOCKING REGISTERS The Receive Channel blocking Registers (RCBR1 / RCBR2 / RCBR3 / RCBR4) and the Transmit Channel Blocking Registers (TCBR1 / TCBR2 / TCBR3 / TCBR4) control RCHBLK and TCHBLK pins respectively. (The RCHBLK and TCHBLK pins are user programmable outputs that can be forced either high or low during individual channels). These outputs can be used to block clocks to a USART or LAPD controller in ISDN-PRI applications. When the appropriate bits are set to a one, the RCHBLK and TCHBLK pin will be held high during the entire corresponding channel time. See the timing in Section 17 for an example. The TCBRs have alternate mode of use. Via the CCR3.6 bit, the user has the option to use the TCBRs to determine on a channel by channel basis, which signaling bits are to be inserted via the TSRs (the corresponding bit in the TCBRs=1) and which are to be sourced from the TSER or TSIG pins (the corresponding bit in the TCBR=0). See the timing in Section 17.2 for an example. RCBR1/RCBR2/RCBR3/RCBR4: RECEIVE CHANNEL BLOCKING REGISTERS (Address=2B to 2E Hex) (MSB) CH8 CH16 CH24 CH32 SYMBOLS CH1 - 32 CH7 CH15 CH23 CH31 CH6 CH14 CH22 CH30 POSITIONS RCBR1.0 - 4.7 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 (LSB) CH1 CH9 CH17 CH25 RCBR1 (2B) RCBR2 (2C) RCBR3 (2D) RCBR4 (2E) NAME AND DESCRIPTION Receive Channel Blocking Control Bits. 0 = force the RCHBLK pin to remain low during this channel time 1 = force the RCHBLK pin high during this channel time TCBR1/TCBR2/TCBR3/TCBR4: TRANSMIT CHANNEL BLOCKING REGISTERS (Address=22 to 25 Hex) (MSB) CH8 CH16 CH24 CH32 SYMBOLS CH1 - 32 CH7 CH15 CH23 CH31 CH6 CH14 CH22 CH30 POSITIONS TCBR1.0 - 4.7 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 (LSB) CH1 CH9 CH17 CH25 TCBR1 (22) TCBR2 (23) TCBR3 (24) TCBR4 (25) NAME AND DESCRIPTION Transmit Channel Blocking Control Bits. 0 = force the TCHBLK pin to remain low during this channel time 1 = force the TCHBLK pin high during this channel time NOTE: If CCR3.6=1, then a zero in the TCBRs implies that signaling data is to be sourced from TSER (or TSIG if CCR3.2=1) and a one implies that signaling data for that channel is to be sourced from the Transmit Signaling (TS) registers. See definition below. Page 55 of 109 12799 Preliminary DS21354 & DS21554 TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3.6=1 (MSB) CH20 CH24 CH28 CH32 CH4 CH8 CH12 CH16 CH19 CH23 CH27 CH31 CH3 CH7 CH11 CH15 CH18 CH22 CH26 CH30 CH2 CH6 CH10 CH14 CH17* CH21 CH25 CH29 (LSB) CH1* CH5 CH9 CH13 TCBR1 (22) TCBR2 (23) TCBR3 (24) TCBR4 (25) *=CH1 and CH17 should be set to one to allow the internal TS1 register to create the CAS Multiframe Alignment Word and Spare/Remote Alarm bits. Page 56 of 109 12799 Preliminary DS21354 & DS21554 11. ELASTIC STORES OPERATION The DS21354/554 contains dual two-frame (512 bits) elastic stores, one for the receive direction, and one for the transmit direction. These elastic stores have two main purposes. First, they can be used to rate convert the E1 data stream to 1.544 Mbps (or a multiple of 1.544 Mbps) which is the T1 rate. Secondly, they can be used to absorb the differences in frequency and phase between the E1 data stream and an asynchronous (i.e., not frequency locked) backplane clock which can be 1.544 MHz or 2.048/4.096/8.192 MHz. The backplane clock can burst at rates up to 8.192 MHz. Both elastic stores contain full controlled slip capability which is necessary for this second purpose. The elastic stores can be forced to a known depth via the Elastic Store Reset bits (CCR6.0 & CCR6.1). Toggling these bits forces the read and write pointers into opposite frames. Both elastic stores within a framer are fully independent and no restrictions apply to the sourcing of the various clocks that are applied to them. The transmit side elastic store can be enabled whether the receive elastic store is enabled or disabled and vice versa. Also, each elastic store can interface to either a 1.544 MHz or 2.048/4.096/8.192 MHz backplane without regard to the backplane rate the other elastic store is interfacing. 11.1 Receive Side If the receive side elastic store is enabled (RCR2.1=1), then the user must provide either a 1.544 MHz (RCR2.2 =0) or 2.048/4.096/8.192 MHz (RCR2.2=1) clock at the RSYSCLK pin. The user has the option of either providing a frame/multiframe sync at the RSYNC pin (RCR1.5=1) or having the RSYNC pin provide a pulse on frame/multiframe boundaries (RCR1.5=0). If the user wishes to obtain pulses at the frame boundary, then RCR1.6 must be set to zero and if the user wishes to have pulses occur at the multiframe boundary, then RCR1.6 must be set to one. The DS21354/554 will always indicate frame boundaries via the RFSYNC output whether the elastic store is enabled or not. If the elastic store is enabled, then either CAS (RCR1.7=0) or CRC4 (RCR1.7=1) multiframe boundaries will be indicated via the RMSYNC output. If the user selects to apply a 1.544 MHz clock to the RSYSCLK pin, then every fourth channel of the received E1 data will be deleted and a F-bit position (which will be forced to one) will be inserted. Hence Channels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will be deleted from the received E1 data stream. Also, in 1.544 MHz applications, the RCHBLK output will not be active in Channels 25 through 32 (or in other words, RCBR4 is not active). See Section 17.1 for timing details. If the 512-bit elastic buffer either fills or empties, a controlled slip will occur. If the buffer empties, then a full frame of data (256-bits) will be repeated at RSER and the SR1.4 and RIR.3 bits will be set to a one. If the buffer fills, then a full frame of data will be deleted and the SR1.4 and RIR.4 bits will be set to a one. 11.2 Transmit Side The operation of the transmit elastic store is very similar to the receive side. The transmit side elastic store is enabled via CCR3.7. A 1.544 MHz (CCR3.1=0) or 2.048/4.096/8.192 MHz (CCR3.1=1) clock can be applied to the TSYSCLK input. The TSYSCLK can be a bursty clock with rates up to 8.192 MHz. The user must supply either an 8 kHz frame sync pulse or a multiframe sync pulse to the TSSYNC input. See Section 17.2 for timing details. Controlled slips in the transmit elastic store are reported in the SR2.0 bit and the direction of the slip is reported in the RIR.6 and RIR.7 bits. Page 57 of 109 12799 Preliminary DS21354 & DS21554 12. ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION The DS21354/554 provides for access to both the Sa and the Si bits via three different methods. The first is via a hardware scheme using the RLINK/RLCLK and TLINK/ TLCLK pins. The first method is discussed in Section 12.1. The second involves using the internal RAF/RNAF and TAF/TNAF registers and is discussed in Section 12.2 The third method which is covered in Section 12.3 involves an expanded version of the second method and is one of the features added to the DS2154/354/554 from the original DS2153 definition. 12.1 Hardware Scheme On the receive side, all of the received data is reported at the RLINK pin. Via RCR2, the user can control the RLCLK pin to pulse during any combination of Sa bits. This allows the user to create a clock that can be used to capture the needed Sa bits. If RSYNC is programmed to output a frame boundary, it will identify the Si bits. See Section 17.1 for detailed timing. On the transmit side, the individual Sa bits can be either sourced from the internal TNAF register (see Section 12.2 for details) or from the external TLINK pin. Via TCR2, the framer can be programmed to source any combination of the additional bits from the TLINK pin. If the user wishes to pass the Sa bits through the framer without them being altered, then the device should be set up to source all five Sa bits via the TLINK pin and the TLINK pin should be tied to the TSER pin. Si bits can be inserted through the TSER pin via the clearing of the TCR1.3 bit. Please see the timing diagrams and the transmit data flow diagram in Section 17.2 for examples. 12.2 Internal Register Scheme Based On Double-Frame On the receive side, the RAF and RNAF registers will always report the data as it received in the Additional and International bit locations. The RAF and RNAF registers are updated with the setting of the Receive Align Frame bit in Status Register 2 (SR2.6). The host can use the SR2.6 bit to know when to read the RAF and RNAF registers. It has 250 us to retrieve the data before it is lost. On the transmit side, data is sampled from the TAF and TNAF registers with the setting of the Transmit Align Frame bit in Status Register 2 (SR2.3). The host can use the SR2.3 bit to know when to update the TAF and TNAF registers. It has 250 us to update the data or else the old data will be retransmitted. Data in the Si bit position will be overwritten if either the framer is programmed: (1) to source the Si bits from the TSER pin, (2) in the CRC4 mode, or (3) have automatic E-bit insertion enabled. Data in the Sa bit position will be overwritten if any of the TCR2.3 to TCR2.7 bits are set to one (please see Section 12.1 for details). Please see the register descriptions for TCR1 and TCR2 and DS21354/554 TRANSMIT DATA FLOW Figure 17-15 for more details. RAF: RECEIVE ALIGN FRAME REGISTER (Address=2F Hex) (MSB) Si 0 SYMBOL POSITION NAME AND DESCRIPTION Si 0 0 1 1 0 RAF.7 RAF.6 RAF.5 RAF.4 RAF.3 RAF.2 International Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. 0 1 Page 58 1 of 109 0 1 (LSB) 1 12799 Preliminary DS21354 & DS21554 1 1 RAF.1 RAF.0 Frame Alignment Signal Bit Frame Alignment Signal Bit. RNAF: RECEIVE NON-ALIGN FRAME REGISTER (Address=1F Hex) (MSB) Si 1 SYMBOL POSITION Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8 RNAF.7 RNAF.6 RNAF.5 RNAF.4 RNAF.3 RNAF.2 RNAF.1 RNAF.0 A Sa4 Sa5 Sa6 Sa7 (LSB) Sa8 NAME AND DESCRIPTION International Bit. Frame Non-Alignment Signal Bit. Remote Alarm. Additional Bit 4. Additional Bit 5. Additional Bit 6. Additional Bit 7. Additional Bit 8. TAF: TRANSMIT ALIGN FRAME REGISTER (Address=20 Hex) (MSB) (LSB) Si 0 0 1 1 0 1 1 [Must be programmed with the seven bit FAS word; the DS21354/554 does not automatically set these bits] SYMBOL POSITION NAME AND DESCRIPTION Si 0 0 1 1 0 1 1 TAF.7 TAF.6 TAF.5 TAF.4 TAF.3 TAF.2 TAF.1 TAF.0 International Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. TNAF: TRANSMIT NON-ALIGN FRAME REGISTER (Address=21 Hex) (MSB) Si 1 A Sa4 Sa5 Sa6 Sa7 [Bit 2 must be programmed to one; the DS21354/554 does not automatically set this bit] SYMBOL POSITION Si 1 A Sa4 Sa5 TNAF.7 TNAF.6 TNAF.5 TNAF.4 TNAF.3 (LSB) Sa8 NAME AND DESCRIPTION International Bit. Frame Non-Alignment Signal Bit. Remote Alarm (used to transmit the alarm). Additional Bit 4. Additional Bit 5. Page 59 of 109 12799 Preliminary Sa6 Sa7 Sa8 DS21354 & DS21554 TNAF.2 TNAF.1 TNAF.0 Additional Bit 6. Additional Bit 7. Additional Bit 8. 12.3 Internal Register Scheme Based On CRC4 Multiframe On the receive side, there is a set of eight registers (RSiAF, RSiNAF, RRA, RSa4 to RSa8) that report the Si and Sa bits as they are received. These registers are updated with the setting of the Receive CRC4 Multiframe bit in Status Register 2 (SR2.1). The host can use the SR2.1 bit to know when to read these registers. The user has 2 ms to retrieve the data before it is lost. The MSB of each register is the first received. Please see the register descriptions below for more details. On the transmit side, there is also a set of eight registers (TSiAF, TSiNAF, TRA, TSa4 to TSa8) that via the Transmit Sa Bit Control Register (TSaCR), can be programmed to insert both Si and Sa data. Data is sampled from these registers with the setting of the Transmit Multiframe bit in Status Register 2 (SR2.5). The host can use the SR2.5 bit to know when to update these registers. It has 2 ms to update the data or else the old data will be retransmitted. The MSB of each register is the first bit transmitted. Please see the register descriptions below and DS21354/554 TRANSMIT DATA FLOW Figure 17-15 for more details. REGISTER RSiAF RSiNAF RRA RSa4 RSa5 RSa6 RSa7 RSa8 TSiAF TSiNAF TRA TSa4 TSa5 TSa6 TSa7 TSa8 ADDRESS (HEX) 58 59 5A 5B 5C 5D 5E 5F 50 51 52 53 54 55 56 57 FUNCTION The eight Si bits in the align frame The eight Si bits in the non-align frame The eight reportings of the receive remote alarm (RA) The eight Sa4 reported in each CRC4 multiframe The eight Sa5 reported in each CRC4 multiframe The eight Sa6 reported in each CRC4 multiframe The eight Sa7 reported in each CRC4 multiframe The eight Sa8 reported in each CRC4 multiframe The eight Si bits to be inserted into the align frame The eight Si bits to be inserted into the non-align frame The eight settings of remote alarm (RA) The eight Sa4 settings in each CRC4 multiframe The eight Sa5 settings in each CRC4 multiframe The eight Sa6 settings in each CRC4 multiframe The eight Sa7 settings in each CRC4 multiframe The eight Sa8 settings in each CRC4 multiframe TSaCR: TRANSMIT Sa BIT CONTROL REGISTER (Address=1C Hex) (MSB) SiAF SiNAF RA SYMBOL POSITION SiAF TSaCR.7 Sa4 Sa5 Sa6 Sa7 (LSB) Sa8 NAME AND DESCRIPTION International Bit in Align Frame Insertion Control Bit. 0=do not insert data from the TSiAF register into the transmit data stream 1=insert data from the TSiAF register into the transmit data stream Page 60 of 109 12799 Preliminary DS21354 & DS21554 SiNAF TSaCR.6 RA TSaCR.5 Sa4 TSaCR.4 Sa5 TSaCR.3 Sa6 TSaCR.2 Sa7 TSaCR.1 Sa8 TSaCR.0 International Bit in Non-Align Frame Insertion Control Bit. 0=do not insert data from the TSiNAF register into the transmit data stream 1=insert data from the TSiNAF register into the transmit data stream Remote Alarm Insertion Control Bit. 0=do not insert data from the TRA register into the transmit data stream 1=insert data from the TRA register into the transmit data stream Additional Bit 4 Insertion Control Bit. 0=do not insert data from the TSa4 register into the transmit data stream 1=insert data from the TSa4 register into the transmit data stream Additional Bit 5 Insertion Control Bit. 0=do not insert data from the TSa5 register into the transmit data stream 1=insert data from the TSa5 register into the transmit data stream Additional Bit 6 Insertion Control Bit. 0=do not insert data from the TSa6 register into the transmit data stream 1=insert data from the TSa6 register into the transmit data stream Additional Bit 7 Insertion Control Bit. 0=do not insert data from the TSa7 register into the transmit data stream 1=insert data from the TSa7 register into the transmit data stream Additional Bit 8 Insertion Control Bit. 0=do not insert data from the TSa8 register into the transmit data stream 1=insert data from the TSa8 register into the transmit data stream Page 61 of 109 12799 Preliminary DS21354 & DS21554 13. HDLC Controller for the Sa Bits or DS0 The DS21354/554 has the ability to extract/insert data from/into the Sa bit positions (Sa4 to Sa8) or from/to any multiple of DS0 or sub DS0 channels. The SCT contains a complete HDLC controller and this operation is covered in Section 13.1. 13.1 General Overview The DS21354/554 contains a complete HDLC controller with 64-byte buffers in both the transmit and receive directions The HDLC controller performs all the necessary overhead for generating and receiving an HDLC formatted message. The HDLC controller automatically generates and detects flags, generates and checks the CRC check sum, generates and detects abort sequences, stuffs and destuffs zeros (for transparency), and byte aligns to the HDLC data stream. There are eleven registers that the host will use to operate and control the operation of the HDLC controller. A brief description of the registers is shown in HDLC CONTROLLER REGISTER LIST Table 13-1. HDLC CONTROLLER REGISTER LIST Table 13-1 NAME HDLC Control Register (HCR) HDLC Status Register (HSR) HIMR Interrupt Mask Register (HIMR) Receive HDLC Information register (RHIR) Receive HDLC FIFO Register (RHFR) Receive HDLC DS0 Control Register 1 (RDC1) Receive HDLC DS0 Control Register 2 (RDC2) Transmit HDLC Information register (THIR) Transmit HDLC FIFO Register (THFR) Transmit HDLC DS0 Control Register 1 (TDC1) Transmit HDLC DS0 Control Register 2 (TDC2) FUNCTION general control over the HDLC controller key status information for both transmit and receive directions allows/stops status bits to/from causing an interrupt status information on receive HDLC controller access to 64-byte HDLC FIFO in receive direction controls the HDLC function when used on DS0 channels controls the HDLC function when used on DS0 channels status information on transmit HDLC controller access to 64-byte HDLC FIFO in transmit direction controls the HDLC function when used on DS0 channels controls the HDLC function when used on DS0 channels 13.2 HDLC Status Registers Three of the HDLC controller registers (HSR, RHIR, and THIR) provide status information. When a particular event has occurred (or is occurring), the appropriate bit in one of these three registers will be set to a one. Some of the bits in these three status registers are latched and some are real time bits that are not latched. Section 13.4 contains register descriptions that list which bits are latched and which are not. With the latched bits, when an event occurs and a bit is set to a one, it will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the event has occurred again. The real time bits report the current instantaneous conditions that are occurring and the history of these bits is not latched. Page 62 of 109 12799 Preliminary DS21354 & DS21554 Like the other status registers in the framer, the user will always proceed a read of any of the three registers with a write. The byte written to the register will inform the framer which of the latched bits the user wishes to read and have cleared (the real time bits are not affected by writing to the status register). The user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read and a zero in the bit positions he or she does not wish to obtain the latest information on. When a one is written to a bit location, the read register will be updated with current value and it will be cleared. When a zero is written to a bit position, the read register will not be updated and the previous value will be held. A write to the status and information registers will be immediately followed by a read of the same register. The read result should be logically AND'ed with the mask byte that was just written and this value should be written back into the same register to insure that bit does indeed clear. This second write step is necessary because the alarms and events in the status registers occur asynchronously in respect to their access via the parallel port. This write-read-write (for polled driven access) or write-read (for interrupt driven access) scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register. This operation is key in controlling the DS21354/554 with higher-order software languages. Like the SR1 and SR2 status registers, the HSR register has the unique ability to initiate a hardware interrupt via the INT* output pin. Each of the events in the HSR can be either masked or unmasked from the interrupt pin via the HDLC Interrupt Mask Register (HIMR). Interrupts will force the INT* pin low when the event occurs. The INT pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur. 13.3 Basic Operation Details As a basic guideline for interpreting and sending HDLC messages, the following sequences can be applied: 13.3.1 Receive a HDLC Message 1. enable RPS interrupts 2. wait for interrupt to occur 3. disable RPS interrupt and enable either RPE, RNE, or RHALF interrupt 4. read RHIR to obtain REMPTY status a. if REMPTY=0, then record OBYTE, CBYTE, and POK bits and then read the FIFO a1. if CBYTE=0 then skip to step 5 a2. if CBYTE=1 then skip to step 7 b. if REMPTY=1, then skip to step 6 5. repeat step 4 6. wait for interrupt, skip to step 4 7 if POK=0, then discard whole packet, if POK=1, accept the packet 8. disable RPE, RNE, or RHALF interrupt, enable RPS interrupt and return to step 1. 13.3.2 Transmit an HDLC Message 1. make sure HDLC controller is done sending any previous messages and is current sending flags by checking that the FIFO is empty by reading the TEMPTY status bit in the THIR register 2. enable either the THALF or TNF interrupt 3. read THIR to obtain TFULL status Page 63 of 109 12799 Preliminary DS21354 & DS21554 a. if TFULL=0, then write a byte into the FIFO and skip to next step (special case occurs when the last byte is to be written, in this case set TEOM=1 before writing the byte and then skip to step 6) b. if TFULL=1, then skip to step 5 4. repeat step 3 5. wait for interrupt, skip to step 3 6. disable THALF or TNF interrupt and enable TMEND interrupt 7. wait for an interrupt, then read TUDR status bit to make sure packet was transmitted correctly. 13.4 HDLC Register Description HCR: HDLC CONTROL REGISTER (Address=B0 Hex) (MSB) - RHR TFS SYMBOL POSITION - RHR HCR.7 HCR.6 TFS HCR.5 THR HCR.4 TABT HCR.3 TEOM HCR.2 TZSD HCR.1 TCRCD HCR.0 THR TABT TEOM TZSD (LSB) TCRCD NAME AND DESCRIPTION Not Assigned. Should be set to zero when written. Receive HDLC Reset. A 0 to 1 transition will reset the HDLC controller. Must be cleared and set again for a subsequent reset. Transmit Flag/Idle Select. 0 = 7Eh 1 = FFh Transmit HDLC Reset. A 0 to 1 transition will reset the HDLC controller. Must be cleared and set again for a subsequent reset. Transmit Abort. A 0 to 1 transition will cause the FIFO contents to be dumped and one FEh abort to be sent followed by 7Eh or FFh flags/idle until a new packet is initiated by writing new data into the FIFO. Must be cleared and set again for a subsequent abort to be sent. Transmit End of Message. Should be set to a one just before the last data byte of a HDLC packet is written into the transmit FIFO at THFR. This bit will be cleared by the HDLC controller when the last byte has been transmitted. Transmit Zero Stuffer Defeat. Overrides internal enable. 0 = enable the zero stuffer (normal operation) 1 = disable the zero stuffer Transmit CRC Defeat. 0 = enable CRC generation (normal operation) 1 = disable CRC generation HSR: HDLC STATUS REGISTER (Address=B1 Hex) (MSB) FRCL RPE RPS SYMBOL POSITION FRCL HSR.7 RPE HSR.6 RHALF RNE THALF TNF (LSB) TMEND NAME AND DESCRIPTION Framer Receive Carrier Loss. Set when 255 (or 2048 if CCR3.0 = 1) consecutive zeros have been detected at RPOSI and RNEGI. Receive Packet End. Set when the HDLC controller detects either the finish of a valid message (i.e., CRC check complete) or when the Page 64 of 109 12799 Preliminary DS21354 & DS21554 RPS HSR.5 RHALF HSR.4 RNE HSR.3 THALF HSR.2 TNF HSR.1 TMEND HSR.0 controller has experienced a message fault such as a CRC checking error, or an overrun condition, or an abort has been seen. The setting of this bit prompts the user to read the RHIR register for details. Receive Packet Start. Set when the HDLC controller detects an opening byte. The setting of this bit prompts the user to read the RHIR register for details. Receive FIFO Half Full. Set when the receive 64-byte FIFO fills beyond the half way point. The setting of this bit prompts the user to read the RHIR register for details. Receive FIFO Not Empty. Set when the receive 64-byte FIFO has at least one byte available for a read. The setting of this bit prompts the user to read the RHIR register for details. Transmit FIFO Half Empty. Set when the transmit 64-byte FIFO empties beyond the half way point. The setting of this bit prompts the user to read the THIR register for details. Transmit FIFO Not Full. Set when the transmit 64-byte FIFO has at least one byte available. The setting of this bit prompts the user to read the THIR register for details. Transmit Message End. Set when the transmit HDLC controller has finished sending a message. The setting of this bit prompts the user to read the THIR register for details. NOTE: The RPE, RPS, and TMEND bits are latched and will be cleared when read. HIMR: HDLC INTERRUPT MASK REGISTER (Address=B2 Hex) (MSB) FRCL RPE RPS RHALF RNE SYMBOL POSITION NAME AND DESCRIPTION FRCL HIMR.7 RPE HIMR.6 RPS HIMR.5 RHALF HIMR.4 RNE HIMR.3 THALF HIMR.2 TNF HIMR.1 Framer Receive Carrier Loss. 0 = interrupt masked 1 = interrupt enabled Receive Packet End. 0 = interrupt masked 1 = interrupt enabled Receive Packet Start. 0 = interrupt masked 1 = interrupt enabled Receive FIFO Half Full. 0 = interrupt masked 1 = interrupt enabled Receive FIFO Not Empty. 0 = interrupt masked 1 = interrupt enabled Transmit FIFO Half Empty. 0 = interrupt masked 1 = interrupt enabled Transmit FIFO Not Full. 0 = interrupt masked Page 65 of 109 THALF TNF (LSB) TMEND 12799 Preliminary TMEND DS21354 & DS21554 HIMR.0 1 = interrupt enabled Transmit Message End. 0 = interrupt masked 1 = interrupt enabled RHIR: RECEIVE HDLC INFORMATION REGISTER (Address=B3 Hex) (MSB) RABT RCRCE ROVR SYMBOL RABT POSITION RHIR.7 RCRCE ROVR RHIR.6 RHIR.5 RVM RHIR.4 REMPTY RHIR.3 POK RHIR.2 CBYTE RHIR.1 OBYTE RHIR.0 RVM REMPTY POK CBYTE (LSB) OBYTE NAME AND DESCRIPTION Abort Sequence Detected. Set whenever the HDLC controller sees 7 or more ones in a row. CRC Error. Set when the CRC checksum is in error. Overrun. Set when the HDLC controller has attempted to write a byte into an already full receive FIFO. Valid Message. Set when the HDLC controller has detected and checked a complete HDLC packet. Empty. A real-time bit that is set high when the receive FIFO is empty. Packet OK. Set when the byte available for reading in the receive FIFO at RHFR is the last byte of a valid message (and hence no abort was seen, no overrun occurred, and the CRC was correct). Closing Byte. Set when the byte available for reading in the receive FIFO at RHFR is the last byte of a message (whether the message was valid or not). Opening Byte. Set when the byte available for reading in the receive FIFO at RHFR is the first byte of a message. NOTE: The RABT, RCRCE, ROVR, and RVM bits are latched and will be cleared when read. RHFR: RECEIVE HDLC FIFO REGISTER (Address=B4 Hex) (MSB) HDLC7 HDLC6 HDLC5 SYMBOL POSITION HDLC7 HDLC6 HDLC5 HDLC4 HDLC3 HDLC2 HDLC1 HDLC0 RHFR.7 RHFR.6 RHFR.5 RHFR.4 RHFR.3 RHFR.2 RHFR.1 RHFR.0 HDLC4 HDLC3 HDLC2 HDLC1 (LSB) HDLC0 NAME AND DESCRIPTION HDLC Data Bit 7. MSB of a HDLC packet data byte. HDLC Data Bit 6. HDLC Data Bit 5. HDLC Data Bit 4. HDLC Data Bit 3. HDLC Data Bit 2. HDLC Data Bit 1. HDLC Data Bit 0. LSB of a HDLC packet data byte. THIR: TRANSMIT HDLC INFORMATION REGISTER (Address=B6 Hex) Page 66 of 109 12799 Preliminary DS21354 & DS21554 (MSB) - - SYMBOL POSITION - - - - - TEMPTY THIR.7 THIR.6 THIR.5 THIR.4 THIR.3 THIR.2 TFULL THIR.1 UDR THIR.0 - - - EMPTY TFULL (LSB) UDR NAME AND DESCRIPTION Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Transmit FIFO Empty. A real-time bit that is set high when the FIFO is empty. Transmit FIFO Full. A real-time bit that is set high when the FIFO is full. Underrun. Set when the transmit FIFO unwantedly empties out and an abort is automatically sent. NOTE: The UDR bit is latched and will be cleared when read. THFR: TRANSMIT HDLC FIFO REGISTER (Address=B7 Hex) (MSB) HDLC7 HDLC6 HDLC5 SYMBOL POSITION HDLC7 HDLC6 HDLC5 HDLC4 HDLC3 HDLC2 HDLC1 HDLC0 THFR.7 THFR.6 THFR.5 THFR.4 THFR.3 THFR.2 THFR.1 THFR.0 HDLC4 HDLC3 HDLC2 HDLC1 (LSB) HDLC0 NAME AND DESCRIPTION HDLC Data Bit 7. MSB of a HDLC packet data byte. HDLC Data Bit 6. HDLC Data Bit 5. HDLC Data Bit 4. HDLC Data Bit 3. HDLC Data Bit 2. HDLC Data Bit 1. HDLC Data Bit 0. LSB of a HDLC packet data byte. RDC1: RECEIVE HDLC DS0 CONTROL REGISTER 1 (Address=B8 Hex) (MSB) RHS RSaDS RDS0M SYMBOL POSITION RHS RDC1.7 RSaDS RDC1.6 RD4 RD3 RD2 RD1 (LSB) RD0 NAME AND DESCRIPTION Receive HDLC source 0 = Sa bits defined by RCR2.3 to RCR2.7. 1 = Sa bits or DS0 channels defined by RDC1 (see bits defined below). Receive Sa Bit / DS0 Select. 0 = route Sa bits to the HDLC controller. RD0 to RD4 defines which Sa bits are to be routed. RD4 corresponds to Sa4, RD3 to Sa5, RD2 to Sa6, RD1 to Sa7 and RD0 to Sa8. 1 = route DS0 channels into the HDLC controller. RDC1.5 is used to Page 67 of 109 12799 Preliminary DS21354 & DS21554 RDS0M RDC1.5 RD4 RD3 RD2 RD1 RD0 RDC1.4 RDC1.3 RDC1.2 RDC1.1 RDC1.0 determine how the DS0 channels are selected. DS0 Selection Mode. 0 = utilize the RD0 to RD4 bits to select which single DS0 channel to use. 1 = utilize the RCHBLK control registers to select which DS0 channels to use. DS0 Channel Select Bit 4. MSB of the DS0 channel select. DS0 Channel Select Bit 3. DS0 Channel Select Bit 2. DS0 Channel Select Bit 1. DS0 Channel Select Bit 0. LSB of the DS0 channel select. RDC2: RECEIVE HDLC DS0 CONTROL REGISTER 2 (Address=B9 Hex) (MSB) RDB8 RDB7 RDB6 SYMBOL POSITION RDB8 RDC2.7 RDB7 RDC2.6 RDB6 RDC2.5 RDB5 RDC2.4 RDB4 RDC2.3 RDB3 RDC2.2 RDB2 RDC2.1 RDB1 RDC2.0 RDB5 RDB4 RDB3 RDB2 (LSB) RDB1 NAME AND DESCRIPTION DS0 Bit 8 Suppress Enable. MSB of the DS0. Set to one to stop this bit from being used. DS0 Bit 7 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 6 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 5 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 4 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 3 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 2 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 1 Suppress Enable. LSB of the DS0. Set to one to stop this bit from being used. TDC1: TRANSMIT HDLC DS0 CONTROL REGISTER 1 (Address=BA Hex) (MSB) THE TSaDS TDS0M SYMBOL POSITION THE TDC1.7 TSaDS TDC1.6 TD4 TD3 TD2 TD1 (LSB) TD0 NAME AND DESCRIPTION Transmit HDLC Enable. 0 = disable HDLC controller (no data inserted by HDLC controller into the transmit data stream) 1 = enable HDLC controller to allow insertion of HDLC data into either the Sa position or multiple DS0 channels as defined by TDC1 (see bit definitions below). Transmit Sa Bit / DS0 Select. This bit is ignored if TDC1.7 is set to zero. Page 68 of 109 12799 Preliminary DS21354 & DS21554 TDS0M TDC1.5 TD4 TD3 TD2 TD1 TD0 TDC1.4 TDC1.3 TDC1.2 TDC1.1 TDC1.0 0 = route Sa bits from the HDLC controller. TD0 to TD4 defines which Sa bits are to be routed. TD4 corresponds to Sa4, TD3 to Sa5, TD2 to Sa6, TD1 to Sa7 and TD0 to Sa8. 1 = route DS0 channels from the HDLC controller. TDC1.5 is used to determine how the DS0 channels are selected. DS0 Selection Mode. 0 = utilize the TD0 to TD4 bits to select which single DS0 channel to use. 1 = utilize the TCHBLK control registers to select which DS0 channels to use. DS0 Channel Select Bit 4. MSB of the DS0 channel select. DS0 Channel Select Bit 3. DS0 Channel Select Bit 2. DS0 Channel Select Bit 1. DS0 Channel Select Bit 0. LSB of the DS0 channel select. TDC2: TRANSMIT HDLC DS0 CONTROL REGISTER 2 (Address=BB Hex) (MSB) TDB8 TDB7 TDB6 SYMBOL POSITION TDB8 TDC2.7 TDB7 TDC2.6 TDB6 TDC2.5 TDB5 TDC2.4 TDB4 TDC2.3 TDB3 TDC2.2 TDB2 TDC2.1 TDB1 TDC2.0 TDB5 TDB4 TDB3 TDB2 (LSB) TDB1 NAME AND DESCRIPTION DS0 Bit 8 Suppress Enable. MSB of the DS0. Set to one to stop this bit from being used. DS0 Bit 7 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 6 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 5 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 4 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 3 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 2 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 1 Suppress Enable. LSB of the DS0. Set to one to stop this bit from being used. Page 69 of 109 12799 Preliminary DS21354 & DS21554 14. LINE INTERFACE FUNCTIONS The line interface function in the DS21354/554 contains three sections; (1) the receiver which handles clock and data recovery, (2) the transmitter which waveshapes and drives the E1 line, and (3) the jitter attenuator. Each of the these three sections is controlled by the Line Interface Control Register (LICR) which is described below. LICR: LINE INTERFACE CONTROL REGISTER (Address=18 Hex) (MSB) L2 L1 L0 SYMBOL L2 POSITION LICR.7 L1 LICR.6 L0 LICR.5 EGL LICR.4 JAS LICR.3 JABDS LICR.2 DJA LICR.1 TPD LICR.0 EGL JAS JABDS DJA (LSB) TPD NAME AND DESCRIPTION Line Build Out Select Bit 2. Sets the transmitter build out; see LINE BUILD OUT SELECT IN LICR FOR THE DS21554 Table 14-1. Line Build Out Select Bit 1. Sets the transmitter build out; see LINE BUILD OUT SELECT IN LICR FOR THE DS21554 Table 14-1. Line Build Out Select Bit 0. Sets the transmitter build out; see LINE BUILD OUT SELECT IN LICR FOR THE DS21554 Table 14-1. Receive Equalizer Gain Limit. 0 = -12 dB 1 = -43 dB Jitter Attenuator Select. 0 = place the jitter attenuator on the receive side 1 = place the jitter attenuator on the transmit side Jitter Attenuator Buffer Depth Select. 0 = 128 bits 1 = 32 bits (use for delay sensitive applications) Disable Jitter Attenuator. 0 = jitter attenuator enabled 1 = jitter attenuator disabled Transmit Power Down. 0 = normal transmitter operation 1 = powers down the transmitter and 3-states the TTIP and TRING pins 14.1 Receive Clock And Data Recovery The DS21354/554 contains a digital clock recovery system. See DS21354/554 Single-Chip Transceiver Figure 1-1 and External Analog Connections Figure 14-1 for more details. The device couples to the receive E1 shielded twisted pair or COAX via a 1:1 transformer. See TRANSFORMER SPECIFICATIONS Table 14-3 for transformer details. The 2.048 MHz clock attached at the MCLK pin is internally multiplied by 16 via an internal PLL and fed to the clock recovery system. The clock recovery system uses the clock from the PLL circuit to form a 16 times over-sampler which is used to recover the clock and data. This over-sampling technique offers outstanding jitter tolerance (see Jitter Tolerance Figure 14-3). Normally, the clock that is output at the RCLKO pin is the recovered clock from the E1 AMI/HDB3 waveform presented at the RTIP and RRING inputs. When no AMI signal is present at RTIP and RRING, a Receive Carrier Loss (RCL) condition will occur and the RCLKO will be sourced from the clock applied at the MCLK pin. If the jitter attenuator is either placed in the transmit path or is disabled, the RCLKO Page 70 of 109 12799 Preliminary DS21354 & DS21554 output can exhibit slightly shorter high cycles of the clock. This is due to the highly over-sampled digital clock recovery circuitry. If the jitter attenuator is placed in the receive path (as is the case in most applications), the jitter attenuator restores the RCLK to being close to 50% duty cycle. Please see the Receive AC Timing Characteristics in Section 19.3 for more details. 14.2 Transmit Waveshaping And Line Driving The DS21354/554 uses a set of laser-trimmed delay lines along with a precision Digital-to-Analog Converter (DAC) to create the waveforms that are transmitted onto the E1 line. The waveforms meet the ITU G.703 specifications. See Transmit Waveform Template Figure 14-5. The user will select which waveform is to be generated by properly programming the L2/L1/L0 bits in the Line Interface Control Register (LICR). The DS21354/554 can set up in a number of various configurations depending on the application. See tables below and Transmit Waveform Template Figure 14-5. LINE BUILD OUT SELECT IN LICR FOR THE DS21554 Table 14-1 L2 L1 L0 APPLICATION TRANSFORMER 0 0 0 75 ohm normal 1:1.15 step-up 0 0 1 120 ohm normal 1:1.15 step-up 0 1 0 75 ohm w/ protection resistors 1:1.15 step-up 0 1 1 120 ohm w/ protection resistors 1:1.15 step-up 1 0 0 75 ohm w/ high return loss 1:1.15 step-up 1 1 0 75 ohm w/ high return loss 1:1.36 step-up 1 0 0 120 ohm w/ high return loss 1:1.36 step-up * NM = Not Meaningful (Return Loss value too low for significance) ** See separate application note for details on E1 line interface design RETURN LOSS* NM NM NM NM 21dB 21dB 21dB RT** 0 ohms 0 ohms 8.2 ohms 8.2 ohms 27 ohms 18 ohms 27 ohms LINE BUILD OUT SELECT IN LICR FOR THE DS21354 Table 14-2 L2 L1 L0 APPLICATION TRANSFORMER 0 0 0 75 ohm normal 1:2 step-up 0 0 1 120 ohm normal 1:2 step-up 0 1 0 75 ohm w/ protection resistors 1:2 step-up 0 1 1 120 ohm w/ protection resistors 1:2 step-up 1 0 0 75 ohm w/ high return loss 1:2 step-up 1 0 1 120 ohm w/ high return loss 1:2 step-up * NM = Not Meaningful (Return Loss value too low for significance) ** See separate application note for details on E1 line interface design RETURN LOSS* NM NM NM NM 21dB 21dB RT** 0 ohms 0 ohms 2.5 ohms 2.5 ohms 6.2 ohms 11.6 ohms Due to the nature of the design of the transmitter in the DS21354/554, very little jitter (less then 0.005 UIpp broadband from 10 Hz to 100 kHz) is added to the jitter present on TCLK. Also, the waveform created is independent of the duty cycle of TCLK. The transmitter in the device couples to the E1 transmit shielded twisted pair or COAX via a 1:1.15 or 1:1.36 step up transformer as shown in External Analog Connections Figure 14-1. In order for the devices to create the proper waveforms, the transformer used must meet the specifications listed in TRANSFORMER SPECIFICATIONS Table 14-3. The line driver in the device contains a current limiter that will prevent more than 50 mA (rms) from being sourced in a 1 ohm load. Page 71 of 109 12799 Preliminary DS21354 & DS21554 TRANSFORMER SPECIFICATIONS Table 14-3 SPECIFICATION Turns Ratio DS21354 Turns Ratio DS21554 Primary Inductance Leakage Inductance Intertwining Capacitance DC Resistance RECOMMENDED VALUE 1:1(receive) and1:2(transmit)3% 1:1(receive) and1:1.15 or1:1.36(transmit)3% 600H minimum 1.0H maximum 40 pF maximum 1.2 Ohms maximum 14.3 Jitter Attenuator The DS21354/554 contains an onboard jitter attenuator that can be set to a depth of either 32 or 128 bits via the JABDS bit in the Line Interface Control Register (LICR). The 128-bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used in delay sensitive applications. The characteristics of the attenuation are shown in Jitter Attenuation Figure 14-4. The jitter attenuator can be placed in either the receive path or the transmit path by appropriately setting or clearing the JAS bit in the LICR. Also, the jitter attenuator can be disabled (in effect, removed) by setting the DJA bit in the LICR. In order for the jitter attenuator to operate properly, a 2.048 MHz clock (50 ppm) must be applied at the MCLK pin or a crystal with similar characteristics must be applied across the MCLK and XTALD pins. If a crystal is applied across the MCLK and XTALD pins, then the maximum effective series resistance should be 30 ohms and capacitors should be placed from each leg of the crystal to ground as shown in Optional Crystal Connection Figure 14-2. Onboard circuitry adjusts either the recovered clock from the clock/data recovery block or the clock applied at the TCLKI pin to create a smooth jitter free clock which is used to clock data out of the jitter attenuator FIFO. It is acceptable to provide a gapped/bursty clock at the TCLKI pin if the jitter attenuator is placed on the transmit side. If the incoming jitter exceeds either 120 UIpp (buffer depth is 128 bits) or 28 UIpp (buffer depth is 32 bits), then the DS21354/554 will divide the internal nominal 32.768 MHz clock by either 15 or 17 instead of the normal 16 to keep the buffer from overflowing. When the device divides by either 15 or 17, it also sets the Jitter Attenuator Limit Trip (JALT) bit in the Receive Information Register (RIR.5). Page 72 of 109 12799 Preliminary DS21354 & DS21554 External Analog Connections Figure 14-1 0.47uF (nonpolarized) +5V 0.1uF DS21354 / 554 Rt E1 Transmit Line TTIP TRING Rt N:1 (see table below) 1:1 DVDD DVSS 0.01uF RVDD RVSS 0.1uF TVDD TVSS 0.1uF XTALD NC MCLK 2.048 MHz RTIP E1 Receive Line RRING Rr Rr 0.1uF Optional Crystal Connection Figure 14-2 DS21554/354 XTALD 2.048 MHz MCLK C1 Page 73 of 109 C2 12799 Preliminary DS21354 & DS21554 Jitter Tolerance Figure 14-3 UNIT INTERVALS (UIpp) 1K DS21354/ DS21554 Tolerance 100 40 10 1.5 1 Minimum Tolerance Level as per ITU G.823 0.1 1 20 10 0.2 100 1K FREQUENCY (Hz) 2.4K 10K 18K 100K Jitter Attenuation Figure 14-4 ITU G.7XX Prohibited Area Ji tte rA -20dB tte nu at io ETS 300 011 & TBR12 Prohibited Area n C ur ve JITTER ATTENUATION (dB) 0dB -40dB -60dB 40 1 10 100 1K FREQUENCY (Hz) Page 74 of 109 10K 100K 12799 Preliminary DS21354 & DS21554 Transmit Waveform Template Figure 14-5 1.2 1.1 269ns SCALED AMPLITUDE (in 75 ohm systems, 1.0 on the scale = 2.37Vpeak in 120 ohm systems, 1.0 on the scale = 3.00Vpeak) 1.0 0.9 0.8 0.7 G.703 Template 194ns 0.6 0.5 219ns 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 -200 -150 -100 -50 0 50 100 150 200 250 TIME (ns) Page 75 of 109 12799 Preliminary DS21354 & DS21554 15. JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT 15.1 Description The DS21354/554 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. See JTAG Functional Block Diagram Figure 15-1. The device contains the following as required by IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Test Access Port (TAP) TAP Controller Instruction Register Bypass Register Boundary Scan Register Device Identification Register The DS21354/554 are enhanced versions of the DS2152 and are backward pin-compatible. The JTAG feature uses pins that had no function in the DS2152. When using the JTAG feature, be sure FMS (pin 4) is tied HIGH enabling the newly defined pins of the DS21354/554. Details on Boundary Scan Architecture and the Test Access Port can be found in IEEE 1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994. The Test Access Port has the necessary interface pins; JTRST, JTCLK, JTMS, JTDI, and JTDO. See the pin descriptions for details. JTAG Functional Block Diagram Figure 15-1 Boundary Scan Register Identification Register Bypass Register MUX Instruction Register Test Access Port Controller +V 10K +V Output Enable +V 10K JTDI Select 10K JTMS JTCLK Page 76 JTRST of 109 JTDO 12799 Preliminary DS21354 & DS21554 TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. See TAP Controller State Diagram Figure 15-2. Test-Logic-Reset Upon power up, the TAP Controller will be in the Test-Logic-Reset state. The Instruction register will contain the IDCODE instruction. All system logic of the device will operate normally. Run-Test-Idle The Run-Test-Idle is used between scan operations or during specific tests. The Instruction register and test registers will remain idle. Select-DR-Scan All test registers retain their previous state. With JTMS LOW, a rising edge of JTCLK moves the controller into the Capture-DR state and will initiate a scan sequence. JTMS HIGH during a rising edge on JTCLK moves the controller to the Select-IR-Scan state. Capture-DR Data may be parallel-loaded into the test data registers selected by the current instruction. If the instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register will remain at its current value. On the rising edge of JTCLK, the controller will go to the ShiftDR state if JTMS is LOW or it will go to the Exit1-DR state if JTMS is HIGH. Shift-DR The test data register selected by the current instruction will be connected between JTDI and JTDO and will shift data one stage towards its serial output on each rising edge of JTCLK. If a test register selected by the current instruction is not placed in the serial path, it will maintain its previous state. Exit1-DR While in this state, a rising edge on JTCLK will put the controller in the Update-DR state, which terminates the scanning process, if JTMS is HIGH. A rising edge on JTCLK with JTMS LOW will put the controller in the Pause-DR state. Pause-DR Shifting of the test registers is halted while in this state. All test registers selected by the current instruction will retain their previous state. The controller will remain in this state while JTMS is LOW. A rising edge on JTCLK with JTMS HIGH will put the controller in the Exit2-DR state. Exit2-DR A rising edge on JTCLK with JTMS HIGH while in this state will put the controller in the Update-DR state and terminate the scanning process. A rising edge on JTCLK with JTMS LOW will enter the ShiftDR state. Page 77 of 109 12799 Preliminary DS21354 & DS21554 Update-DR A falling edge on JTCLK while in the Update-DR state will latch the data from the shift register path of the test registers into the data output latches. This prevents changes at the parallel output due to changes in the shift register. Select-IR-Scan All test registers retain their previous state. The instruction register will remain unchanged during this state. With JTMS LOW, a rising edge on JTCLK moves the controller into the Capture-IR state and will initiate a scan sequence for the instruction register. JTMS HIGH during a rising edge on JTCLK puts the controller back into the Test-Logic-Reset state. Capture-IR The Capture-IR state is used to load the shift register in the instruction register with a fixed value. This value is loaded on the rising edge of JTCLK. If JTMS is HIGH on the rising edge of JTCLK, the controller will enter the Exit1-IR state. If JTMS is LOW on the rising edge of JTCLK, the controller will enter the Shift-IR state. Shift-IR In this state, the shift register in the instruction register is connected between JTDI and JTDO and shifts data one stage for every rising edge of JTCLK towards the serial output. The parallel register, as well as all test registers, remain at their previous states. A rising edge on JTCLK with JTMS HIGH will move the controller to the Exit1-IR state. A rising edge on JTCLK with JTMS LOW will keep the controller in the Shift-IR state while moving data one stage thorough the instruction shift register. Exit1-IR A rising edge on JTCLK with JTMS LOW will put the controller in the Pause-IR state. If JTMS is HIGH on the rising edge of JTCLK, the controller will enter the Update-IR state and terminate the scanning process. Pause-IR Shifting of the instruction shift register is halted temporarily. With JTMS HIGH, a rising edge on JTCLK will put the controller in the Exit2-IR state. The controller will remain in the Pause-IR state if JTMS is LOW during a rising edge on JTCLK. Exit2-IR A rising edge on JTCLK with JTMS LOW will put the controller in the Update-IR state. The controller will loop back to Shift-IR if JTMS is HIGH during a rising edge of JTCLK in this state. Update-IR The instruction code shifted into the instruction shift register is latched into the parallel output on the falling edge of JTCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising edge on JTCLK with JTMS LOW, will put the controller in the Run-TestIdle state. With JTMS HIGH, the controller will enter the Select-DR-Scan state. Page 78 of 109 12799 Preliminary DS21354 & DS21554 TAP Controller State Diagram Figure 15-2 1 Test Logic Reset 0 0 Run Test/ Idle 1 Select DR-Scan 1 Select IR-Scan 0 1 0 1 Capture DR Capture IR 0 0 Shift DR Shift IR 0 1 0 1 Exit DR 1 Exit IR 0 1 0 Pause DR Pause IR 0 1 0 1 0 1 Exit2 DR 0 Exit2 IR 1 1 Update DR Update IR 1 1 0 0 15.2 Instruction Register The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register will be connected between JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS LOW will shift the data one stage towards the serial output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2IR state with JTMS HIGH will move the controller to the Update-IR state The falling edge of that same JTCLK will latch the data in the instruction shift register to the instruction parallel output. Instructions supported by the DS21354/554 with their respective operational binary codes are shown in Instruction Codes For IEEE 1149.1 Architecture Table 15-1. Page 79 of 109 12799 Preliminary DS21354 & DS21554 Instruction Codes For IEEE 1149.1 Architecture Table 15-1 Instruction Selected Register Instruction Codes SAMPLE/PRELOAD BYPASS EXTEST CLAMP HIGHZ IDCODE Boundary Scan Bypass Boundary Scan Bypass Bypass Device Identification 010 111 000 011 100 001 SAMPLE/PRELOAD This is a mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The digital I/Os of the device can be sampled at the boundary scan register without interfering with the normal operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows the device to shift data into the boundary scan register via JTDI using the Shift-DR state. BYPASS When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO through the one-bit bypass test register. This allows data to pass from JTDI to JTDO not affecting the device's normal operation. EXTEST This allows testing of all interconnections to the device. When the EXTEST instruction is latched in the instruction register, the following actions occur. Once enabled via the Update-IR state, the parallel outputs of all digital output pins will be driven. The boundary scan register will be connected between JTDI and JTDO. The Capture-DR will sample all digital inputs into the boundary scan register. CLAMP All digital outputs of the device will output data from the boundary scan parallel output while connecting the bypass register between JTDI and JTDO. The outputs will not change during the CLAMP instruction. HIGHZ All digital outputs of the device will be placed in a high impedance state. The BYPASS register will be connected between JTDI and JTDO. IDCODE When the IDCODE instruction is latched into the parallel instruction register, the identification test register is selected. The device identification code will be loaded into the identification register on the rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially via JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register's parallel output. The ID code will always have a `1' in the LSB position. The next 11 bits identify the manufacturer's JEDEC number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version. See ID Code Structure Table 15-2. Device ID Codes Table 15-3 lists the device ID codes for the SCT devices. Page 80 of 109 12799 Preliminary DS21354 & DS21554 ID Code Structure Table 15-2 MSB Version Contact Factory 4 bits Device ID JEDEC LSB 1 16bits 00010100001 1 Device ID Codes Table 15-3 DEVICE DS21354 DS21554 DS21352 DS21552 16-BIT ID 0005h 0003h 0004h 0002h 15.3 Test Registers IEEE 1149.1 requires a minimum of two test registers; the bypass register and the boundary scan register. An optional test register has been included with the DS21354/554 design. This test register is the identification register and is used in conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller. Boundary Scan Register This register contains both a shift register path and a latched parallel output for all control cells and digital I/O cells and is n bits in length. See Boundary Scan Control Bits Table 15-4 for all of the cell bit locations and definitions. Bypass Register This is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ instructions which provides a short path between JTDI and JTDO. Identification Register The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is selected during the IDCODE instruction and when the TAP controller is in the Test-LogicReset state. See ID Code Structure Table 15-2 and Device ID Codes Table 15-3 for more information on bit usage. Page 81 of 109 12799 Preliminary DS21354 & DS21554 Boundary Scan Control Bits Table 15-4 BIT 2 1 0 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 - SYMBOL RCHBLK JTMS 8MCLK JTCLK JTRST RCL JTDI N/C N/C JTDO BTS LIUC 8XCLK TEST NC RTIP RRING RVDD RVSS RVSS MCLK XTALD NC RVSS INT N/C N/C N/C TTIP TVSS TVDD TRING TCHBLK TLCLK TLINK CI TSYNC.cntl TYPE O I O I I O I - - O I I O I - I I - - - I O - - O - - - O - - O O O I I - 37 38 39 40 41 42 43 44 45 TSYNC TPOSI TNEGI TCLKI TCLKO TNEGO TPOSO DVDD DVSS I/O I I I O O O - - Page 82 CONTROL BIT DESCRIPTION 0 = TSYNC an input 1 = TSYNC an output of 109 12799 Preliminary DS21354 & DS21554 53 52 51 50 49 48 47 46 45 44 43 46 47 48 49 50 51 52 53 54 55 - TCLK TSER TSIG TESO TDATA TSYSCLK TSSYNC TCHCLK CO MUX BUS.cntl I I I O I I I O O I - 42 41 40 39 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 D0/AD0 D1/AD1 D2/AD2 D3/AD3 DVSS DVDD D4/AD4 D5/AD5 D6/AD6 D7/AD7 A0 A1 A2 A3 A4 A5 A6 ALE(AS)/A7 RD*(DS*) CS* FMS WR*(R/W*) RLINK RLCLK DVSS DVDD RCLK DVDD DVSS RDATA RPOSI RNEGI RCLKI RCLKO RNEGO RPOSO RCHCLK RSIGF I/O I/O I/O I/O - - I/O I/O I/O I/O I I I I I I I I I I I I O O - 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 0 = D0-D7/AD0-AD7 are inputs 1 = D0-D7/AD0-AD7 are outputs O - - O I I I O O O O O Page 83 of 109 12799 Preliminary DS21354 & DS21554 10 9 8 7 6 94 95 96 97 - RSIG RSER RMSYNC RFSYNC RSYNC.cntl O O O O - 5 4 3 98 99 100 RSYNC RLOS/LOTC RSYSCLK I/O O I Page 84 0 = RSYNC an input 1 = RSYNC an output of 109 12799 Preliminary DS21354 & DS21554 16. INTERLEAVED PCM BUS OPERATION In many architectures, the outputs of individual framers are combined into higher speed serial buses to simplify transport across the system. The DS21354/554 can be configured to allow data and signaling buses to be multiplexed into higher speed data and signaling buses eliminating external hardware saving board space and cost. The interleaved PCM bus option (IBO) supports two bus speeds. The 4.096 MHz bus speed allows two SCTs to share a common bus. The 8.192 MHz bus speed allows four SCTs to share a common bus. See IBO Basic Configuration Using 4 SCTs Figure 16-1 for an example of 4 devices sharing a common 8.192MHz PCM bus. Each SCT that shares a common bus must be configured through software and requires the use of one or two device pins. The elastic stores of each SCT must be enabled and configured for 2.048 MHz operation. See IBO Basic Configuration Using 4 SCTs Figure 16-1 and IBO Master Device Select Table 16-1. For all bus configurations, one SCT will be configured as the master device and the remaining SCTs will be configured as slave devices. In the 4.096 MHz bus configuration there is one master and one slave. In the 8.192 MHz bus configuration there is one master and three slaves. Refer to the IBO register description for more detail. IBO: INTERLEAVE BUS OPERATION REGISTER (Address = 94 Hex) (MSB) - - SYMBOL POSITION IBOEN IBO.6 IBO.6 IBO.5 IBO.4 IBO.3 INTSEL IBO.2 MSEL0 IBO.1 MSEL1 IBO.0 - - IBOEN INTSEL MSEL0 (LSB) MSEL1 NAME AND DESCRIPTION Not Assigned. Should be set to 0. Not Assigned. Should be set to 0. Not Assigned. Should be set to 0. Not Assigned. Should be set to 0. Interleave Bus Operation Enable 0 = Interleave Bus Operation disabled. 1 = Interleave Bus Operation enabled. Interleave Type Select 0 = Byte interleave. 1 = Frame interleave. Master Device Bus Select Bit 0 See IBO Master Device Select Table 16-1. Master Device Bus Select Bit 1 See IBO Master Device Select Table 16-1. IBO Master Device Select Table 16-1 MSEL1 0 0 1 1 MSEL0 0 1 0 1 Function Slave device. Master device with 1 slave device (4.096 MHz bus rate) Master device with 3 slave devices (8.192 MHz bus rate) Reserved Page 85 of 109 12799 Preliminary DS21354 & DS21554 IBO Basic Configuration Using 4 SCTs Figure 16-1 CI RSYSCLK TSYSCLK MASTER SCT CI RSYNC TSSYNC RSYNC TSSYNC RSIG TSIG TSER RSER CO RSYSCLK TSYSCLK SLAVE #2 RSIG TSIG TSER RSER CO 8.192MHz System Clock In System 8KHz Frame Sync In PCM Signaling Out PCM Signaling In PCM Data In PCM Data Out CI RSYSCLK TSYSCLK CI RSYNC TSSYNC SLAVE #1 CO RSIG TSIG TSER RSER RSYSCLK TSYSCLK RSYNC TSSYNC SALVE #3 CO RSIG TSIG TSER RSER 16.1 Channel Interleave In channel interleave mode data is output to the PCM Data Out bus one channel at a time from each of the connected SCTs until all channels of frame n from all each SCT has been place on the bus. This mode can be used even when the connected SCTs are operating asynchronous to each other. The elastic stores will manage slip conditions. See TRANSMIT SIDE INTERLEAVE BUS OPERATION, BYTE MODE Figure 17-11 and RECEIVE SIDE INTERLEAVE BUS OPERATION, BYTE MODE Figure 17-5for details. 16.2 Frame Interleave In frame interleave mode data is output to the PCM Data Out bus one frame at a time from each of the connected SCTs. This mode is used only when all connected SCTs are synchronous. In this mode, slip conditions are not allowed. See TRANSMIT SIDE INTERLEAVE BUS OPERATION, FRAME MODE Figure 17-12 and RECEIVE SIDE INTERLEAVE BUS OPERATION, FRAME MODE Figure 17-6 for details. Page 86 of 109 12799 Preliminary DS21354 & DS21554 17. FUNCTIONAL TIMING DIAGRAMS 17.1 Receive RECEIVE SIDE TIMING Figure 17-1 FRAME# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 RFSYNC RSYNC 1 RSYNC 2 RLCLK RLINK 3 4 Notes: 1. RSYNC in frame mode (RCR1.6 = 0) 2. RSYNC in multiframe mode (RCR1.6 = 1) 3. RLCLK is programmed to output just the Sa bits 4. RLINK will always output all 5 Sa bits as well as the rest of the receive data stream 5. This diagram assumes the CAS MF begins in the RAF frame RECEIVE SIDE BOUNDARY TIMING (with elastic store disabled) Figure 17-2 RCLK CHANNEL 32 RSER LSB Si 1 A CHANNEL 1 Sa4 Sa5 Sa6 Sa7 Sa8 MSB CHANNEL 2 RSYNC RFSYNC CHANNEL 32 RSIG A B CHANNEL 1 C D CHANNEL 2 A B Note 4 RCHCLK 1 RCHBLK RLCLK RLINK 2 Sa4 Sa5 Sa6 Sa7 Sa8 Notes: 1. RCHBLK is programmed to block channel 1 2. RLCLK is programmed to mark the Sa4 bit in RLINK 3. Shown isa RNAF frame boundary 4. RSIG normally contains the CAS multiframe alignment nibble (0000) in channel 1 Page 87 of 109 12799 Preliminary DS21354 & DS21554 RECEIVE SIDE 1.544 MHz BOUNDARY TIMING (with elastic store enabled) Figure 17-3 RSYSCLK CHANNEL 23/31 RSER1 CHANNEL 24/32 CHANNEL 1/2 LSB LSB MSB F MSB RSYNC2 RMSYNC 3 RSYNC RCHCLK 4 RCHBLK Notes: 1. Data from the E1 channels 1. 5. 9, 13, 17, 21, 25, and 29 is dropped (channel 2 from the E1 link is (mapped to channel 1 of the T1 link, etc.) and the F-bit position is added (forced to on1) 2. RSYNC in the output mode (RCR1.5 = 0) 3. RSYNC in the input mode (RCR1.5 = 1) 4. RCHBLK is programmed to block channel 24 RECEIVE SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled) Figure 17-4 RSYSCLK CHANNEL 31 CHANNEL 32 RSER CHANNEL 1 LSB MSB LSB MSB RSYNC1 RMSYNC RSYNC 2 RSIG A CHANNEL 31 C B D A CHANNEL 32 C B D CHANNEL 1 Note 4 RCHCLK RCHBLK 3 Notes: 1. RSYNC is in the output mode (RCR1.5 = 0) 2. RSYNC is in the input mode (RCR1.5 = 1) 3. RCHBLK is programmed to block channel 1 4. RSIG normally contains the CAS multiframe alignment nibble (0000) in Channel 1 Page 88 of 109 12799 Preliminary DS21354 & DS21554 RECEIVE SIDE INTERLEAVE BUS OPERATION, BYTE MODE Figure 17-5 RSYNC 1 RSER FR1 CH32 FR0 CH1 FR1 CH1 FR0 CH2 FR1 CH2 RSIG1 FR1 CH32 FR0 CH1 FR1 CH1 FR0 CH2 FR1 CH2 RSER2 FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0 CH2 FR1 CH2 FR2 CH2 FR3 CH2 RSIG2 FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0 CH2 FR1 CH2 FR2 CH2 FR3 CH2 BIT DETAIL SYSCLK 3 RSYNC FRAMER 3, CHANNEL 32 RSER FRAMER 3, CHANNEL 32 RSIG A B C FRAMER 1, CHANNEL 1 FRAMER 0, CHANNEL 1 LSB MSB LSB MSB FRAMER 0, CHANNEL 1 D A B C LSB FRAMER 1, CHANNEL 1 D A B C D Notes: 1. 4.096 MHz bus configuration. 2. 8.192 MHz bus configuration. 3. RSYNC is in the input mode (RCR1.5 = 0). RECEIVE SIDE INTERLEAVE BUS OPERATION, FRAME MODE Figure 17-6 RSYNC 1 RSER FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 RSIG1 FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 RSER2 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 RSIG2 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 BIT DETAIL SYSCLK 3 RSYNC FRAMER 3, CHANNEL 32 RSER FRAMER 3, CHANNEL 32 RSIG FRAMER 0, CHANNEL 1 A B FRAMER 0, CHANNEL 2 LSB MSB LSB MSB FRAMER 0, CHANNEL 1 C/A D/B A B C/A D/B LSB FRAMER 0, CHANNEL 2 A B C/A D/B Notes: 1. 4.096 MHz bus configuration. 2. 8.192 MHz bus configuration. 3. RSYNC is in the input mode (RCR1.5 = 0). Page 89 of 109 12799 Preliminary DS21354 & DS21554 17.2 Transmit TRANSMIT SIDE TIMING Figure 17-7 FRAME# 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 1 TSYNC TSSYNC TSYNC TLCLK TLINK 2 3 3 Notes: 1. TSYNC in frame mode (TCR1.1 = 0) 2. TSYNC in multiframe mode (TCR1.1 = 1) 3. TLINK is programmed to source just the Sa4 bit 4. This diagram assumes both the CAS MF and the CRC4 MF begin with the TAF frame 5. TLINK and TLCLK are not synchronous with TSSYNC TRANSMIT SIDE BOUNDARY TIMING (with elastic store disabled) Figure 17-8 TCLK CHANNEL 1 LSB TSER Si 1 A CHANNEL 2 Sa4 Sa5 Sa6 Sa7 Sa8 MSB LSB MSB TSYNC1 TSYNC2 CHANNEL 1 TSIG CHANNEL 2 D A B C D TCHCLK TCHBLK 3 TLCLK TLINK 4 4 DON'T CARE DON'T CARE Notes: 1. TSYNC is in the output mode (TCR1.0 = 1) 2. TSYNC is in the input mode (TCR1.0 = 0) 3. TCHBLK is programmed to block channel 2 4. TLINK is programmed to source the Sa4 bit 5. The signaling data at TSIG during channel 1 is normally overwritten in the transmit formatter with the CAS MF alignment nibble (0000) 6. Shown is a TNAF frame boundary Page 90 of 109 12799 Preliminary DS21354 & DS21554 TRANSMIT SIDE 1.544 MHz BOUNDARY TIMING (with elastic store enabled) Figure 17-9 TSYSCLK CHANNEL 23 CHANNEL 24 1 CHANNEL 1 LSB MSB TSER LSB F MSB TSSYNC TCHCLK TCHBLK 2 Notes: 1. The F bit position in the TSER data is ignored 2. TCHBLK is programmed to block channel 24 TRANSMIT SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled) Figure 17-10 TSYSCLK CHANNEL 31 TSER CHANNEL 32 1 CHANNEL 1 LSB MSB LSB F 4 TSSYNC CHANNEL 31 TSIG A B CHANNEL 32 C D A B CHANNEL 1 C D A TCHCLK TCHBLK 2,3 Notes: 1. TCHBLK is programmed to block channel 31 Page 91 of 109 12799 Preliminary DS21354 & DS21554 TRANSMIT SIDE INTERLEAVE BUS OPERATION, BYTE MODE Figure 17-11 TSYNC 1 TSER TSIG1 FR1 CH32 FR0 CH1 FR1 CH1 FR0 CH2 FR1 CH2 FR1 CH32 FR0 CH1 FR1 CH1 FR0 CH2 FR1 CH2 TSER2 FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0 CH2 FR1 CH2 FR2 CH2 FR3 CH2 TSIG2 FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0 CH2 FR1 CH2 FR2 CH2 FR3 CH2 BIT DETAIL SYSCLK 3 TSYNC FRAMER 3, CHANNEL 32 TSER FRAMER 3, CHANNEL 32 TSIG A B FRAMER 1, CHANNEL 1 FRAMER 0, CHANNEL 1 LSB MSB LSB MSB FRAMER 1, CHANNEL 1 FRAMER 0, CHANNEL 1 C/A D/B A B LSB C/A D/B A B C/A D/B Notes: 1. 4.096 MHz bus configuration. 2. 8.192 MHz bus configuration. 3. TSYNC is in the input mode (TCR1.0 = 0). TRANSMIT SIDE INTERLEAVE BUS OPERATION, FRAME MODE Figure 17-12 TSYNC 1 TSER TSIG1 FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 TSER2 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 TSIG2 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 BIT DETAIL SYSCLK 3 TSYNC FRAMER 3, CHANNEL 32 TSER FRAMER 3, CHANNEL 32 TSIG FRAMER 0, CHANNEL 1 A B FRAMER 0, CHANNEL 2 LSB MSB LSB MSB FRAMER 0, CHANNEL 1 C/A D/B A B C/A D/B LSB FRAMER 0, CHANNEL 2 A B C/A D/B Notes: 1. 4.096 MHz bus configuration. 2. 8.192 MHz bus configuration. 3. TSYNC is in the input mode (TCR1.0 = 0). Page 92 of 109 12799 Preliminary DS21354 & DS21554 G.802 TIMING Figure 17-13 TS # 31 32 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 RSYNC TSYNC RCHCLK TCHCLK RCHBLK TCHBLK RCLK / RSYSCLK TCLK / TSYSCLK CHANNEL 25 RSER / TSER CHANNEL 26 LSB MSB RCHCLK / TCHCLK RCHBLK / TCHBLK Notes: 1. RCHBLK or TCHBLK programmed to pulse high during timeslots 1 through 15, 17 through 25, and bit 1 of timeslot 26 Page 93 of 109 12799 Preliminary DS21354 & DS21554 DS21354/554 FRAMER SYNCHRONIZATION FLOWCHART Figure 17-14 Power Up RLOS = 1 FAS Search FASSA = 1 RLOS = 1 FAS Sync Criteria Met FASSA = 0 Resync if RCR1.0 = 0 Increment CRC4 Sync Counter; CRC4SA = 0 8ms Time Out CRC4 Multiframe Search (if enabled via CCR1.0) CRC4SA = 1 CRC4 Sync Criteria Met; CRC4SA = 0; Reset CRC4 Sync Counter Set FASRC (RIR.1) CRC4 Resync Criteria Met (RIR.2) CAS Resync Criteria Met; Set CASRC (RIR.0) FAS Resync Criteria Met CAS Multiframe Search (if enabled via CCR1.3) CASSA = 1 Sync Declared RLOS = 0 CAS Sync Criteria Met CASSA = 0 Check for FAS Framing Error (depends on RCR1.2) Check for >=915 Out of 1000 CRC4 Word Errors If CRC4 is on (CCR1.0 = 1) Check for CAS MF Word Error If CAS is on (CCR1.3 = 0) Page 94 of 109 12799 Preliminary DS21354 & DS21554 DS21354/554 TRANSMIT DATA FLOW Figure 17-15 TSER & TDATA HDLC ENGINE TNAF.0-4 0 0 1 SaDataSource MUX (TDC1) 1 DS0Data SourceMUX (TDC1/2) TAF 0 RSER (note #1) TLINK TNAF.5-7 TC1toTC32 1 0 TAF/TNAFBit MUX 1 Per-Channel Code Generation (TCC1/2/3/4) 0 1 Timeslot 0 Pass-Through (TCR1.6) 1 0 Si Bit Insertion Control (TCR1.3) Receive Side CRC4Error Detector CRC4Multiframe AlignmentWord Generation(CCR.4) 0 1 E-Bit Generation (TCR2.1) 0 1 Sa Bit Insertion Control (TCR2.3 thru TCR2.7) TSiAF TSiNAF TIDR TRA AutoRemoteAlarm Generation(CCR2.4) 0 TSa4toTSa8 1 TIRFunctionSelect (CCR3.5) 0 1 SaBit Insertion Control Register (TSaCR) AIS Generation TS1 to TS16 0 1 Idle Code / Channel Insertion Control via TIR1/2/3/4 0 1 Transmit Signaling All Ones (TCR1.2) TCBR1/2/3/4 0 CCR3.6 TCR1.5 KEY: 1 Signaling Bit Insertion Control = Register 0 CodeWord Generation 1 CRC4 Enable (CCR.4) AIS Generation = Device Pin 0 1 TransmitUnframedAll Ones(TCR1.4)or AutoAIS(CCR2.5) = Selector NOTES: 1.TCLKshouldbetiedtoRCLKandTSYNCshouldbetiedtoRFSYNCfor data to be properly sourced fromRSER. 2. Auto Remote Alarm if enabled will only overwrite bit 3 of timeslot 0 in the Not Align Frames if the alarm needs to be sent. CCR1.6 AMI orHDB3 Converter ToWaveshaping and Line DriversTPOS, Page 95 of 109 12799 Preliminary DS21354 & DS21554 18. OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature for DS21354L / DS21554L Operating Temperature for DS21354LN / DS21554LN Storage Temperature Soldering Temperature -1.0V to +6.0V 0C to 70C -40C to +85C -55C to +125C 260C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER SYMBOL Logic 1 VIH Logic 0 VIL Supply for DS21354 VDD Supply for DS21554 VDD CAPACITANCE PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT DC CHARACTERISTICS PARAMETER Supply Current @ 5V Supply Current @ 3.3V Input Leakage Output Leakage Output Current (2.4V) Output Current (0.4V) SYMBOL IDD IDD IIL ILO IOH IOL MIN 2.0 -0.3 3.135 4.75 MIN (0C to 70C for DS21354L/DS21554L; -40C to +85C for DS21354LN/DS21554LN) TYP MAX UNITS NOTES 5.5 V +0.8 V 3.3 3.465 V 1 5 5.25 V 1 TYP 5 7 MAX UNITS pF pF (tA =25C) NOTES (0C to 70C; VDD = 3.3V 5% for DS21354L; 0C to 70C; VDD = 5.0V 5% for DS21554L; -40C to +85C; VDD = 3.3V 5% for DS21354LN; -40C to +85C; VDD = 5.0V 5% for DS21554LN) MIN TYP MAX UNITS NOTES 75 mA 2 75 mA 2 -1.0 +1.0 3 A 1.0 4 A -1.0 mA +4.0 mA NOTES: 1. Applies to RVDD, TVDD, and DVDD. 1. TCLK = TCLKI = RCLKI = TSYSCLK = RSYSCLK = MCLK = 2.048 MHz; outputs open circuited. 2. 0.0V < VIN < VDD. 3. Applied to INT* when 3-stated. Page 96 of 109 12799 Preliminary DS21354 & DS21554 19. AC TIMING PARAMETERS AND DIAGRAMS 19.1 Multiplexed Bus AC Characteristics AC CHARACTERISTICS - MULTIPLEXED PARALLEL PORT (MUX = 1) [See Figures 19-1 to 19-3 for details] PARAMETER SYMBOL Cycle Time tCYC Pulse Width, DS low or RD* PWEL high Pulse Width, DS high or PWEH RD* low Input Rise/Fall times tR , tF R/W* Hold Time tRWH R/W* Set Up time before DS tRWS high CS* Set Up time before DS, tCS WR* or RD* active CS* Hold time tCH Read Data Hold time tDHR Write Data Hold time tDHW Muxed Address valid to AS tASL or ALE fall Muxed Address Hold time tAHL Delay time DS, WR* or RD* tASD to AS or ALE rise Pulse Width AS or ALE PWASH high Delay time, AS or ALE to tASED DS, WR* or RD* Output Data Delay time from tDDR DS or RD* Data Set Up time tDSW (0C to 70C; VDD = 3.3V 5% for DS21354L; 0C to 70C; VDD = 5.0V 5% for DS21554L; -40C to +85C; VDD = 3.3V 5% for DS21354LN; -40C to +85C; VDD = 5.0V 5% for DS21554LN) MIN TYP MAX UNITS NOTES 200 ns 100 ns 100 ns 10 50 20 ns ns ns 20 ns 0 10 0 15 50 ns ns ns ns 10 20 ns ns 30 ns 10 ns 20 80 50 Page 97 ns ns of 109 12799 Preliminary DS21354 & DS21554 INTEL BUS READ AC TIMING (BTS=0 / MUX = 1) Figure 19-1 t CYC ALE PWASH t ASD WR* t ASD RD* t ASED PWEH t CH t CS PWEL CS* t ASL t DHR t DDR AD0-AD7 t AHL INTEL BUS WRITE TIMING (BTS=0 / MUX=1) Figure 19-2 t CYC ALE PWASH t ASD RD* WR* t ASD PWEL t ASED PWEH t CH t CS CS* t ASL t DHW AD0-AD7 t AHL Page 98 of 109 t DSW 12799 Preliminary DS21354 & DS21554 MOTOROLA BUS AC TIMING (BTS = 1 / MUX = 1) Figure 19-3 PWASH AS DS PWEH t ASED t ASD PWEL t CYC t RWS t RWH R/W* AD0-AD7 (read) t DDR t ASL t AHL t DHR t CH t CS CS* AD0-AD7 (write) t DSW t ASL t DHW t AHL Page 99 of 109 12799 Preliminary DS21354 & DS21554 19.2 Non-Multiplexed Bus AC Characteristics AC CHARACTERISTICS - (0C to 70C; VDD = 3.3V 5% for DS21354L; NON-MULTIPLEXED PARALLEL PORT 0C to 70C; VDD = 5.0V 5% for DS21554L; (MUX = 0) -40C to +85C; VDD = 3.3V 5% for DS21354LN; [See Figures 19-4 to 19-7 for details] -40C to +85C; VDD = 5.0V 5% for DS21554LN) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Set Up Time for A0 to A7, t1 0 ns Valid to CS* Active Set Up Time for CS* Active t2 0 ns to either RD*, WR*, or DS* Active Delay Time from either RD* t3 75 ns or DS* Active to Data Valid Hold Time from either RD*, t4 0 ns WR*, or DS* Inactive to CS* Inactive Hold Time from CS* t5 5 20 ns Inactive to Data Bus 3-state Wait Time from either WR* t6 75 ns or DS* Active to Latch Data Data Set Up Time to either t7 10 ns WR* or DS* Inactive Data Hold Time from either t8 10 ns WR* or DS* Inactive Address Hold from either t9 10 ns WR* or DS* inactive Page 100 of 109 12799 Preliminary DS21354 & DS21554 INTEL BUS READ AC TIMING (BTS=0 / MUX=0) Figure 19-4 A0 to A7 Address Valid Data Valid D0 to D7 5ns min. / 20ns max. t5 WR* t1 0ns min. CS* 0ns min. t2 t3 t4 0ns min. 75ns max. RD* INTEL BUS WRITE AC TIMING (BTS=0 / MUX=0) Figure 19-5 A0 to A7 Address Valid D0 to D7 t7 RD* t1 t8 10ns 10ns min. min. 0ns min. CS* 0ns min. t2 t6 t4 0ns min. 75ns min. WR* Page 101 of 109 12799 Preliminary DS21354 & DS21554 MOTOROLA BUS READ AC TIMING (BTS=1 / MUX=0) Figure 19-6 A0 to A7 Address Valid Data Valid D0 to D7 t5 5ns min. / 20ns max. R/W* t1 0ns min. CS* 0ns min. t2 t3 t4 0ns min. 75ns max. DS* MOTOROLA BUS WRITE AC TIMING (BTS=1 / MUX=0) Figure 19-7 A0 to A7 Address Valid D0 to D7 10ns min. R/W* t1 t7 t8 10ns min. 0ns min. CS* 0ns min. t2 t6 t4 0ns min. 75ns min. DS* Page 102 of 109 12799 Preliminary DS21354 & DS21554 19.3 Receive Side AC Characteristics AC CHARACTERISTICS - RECEIVE SIDE [See Figures 19-8 to 19-10 for details] PARAMETER SYMBOL RCLKO Period tLP RCLKO Pulse Width tLH tLL RCLKO Pulse Width tLH tLL RCLKI Period tCP RCLKI Pulse Width tCH tCL RSYSCLK Period tSP tSP RSYSCLK Pulse Width tSH tSL RSYNC Set Up to RSYSCLK tSU Falling RSYNC Pulse Width tPW RPOSI/RNEGI Set Up to tSU RCLKI Falling RPOSI/RNEGI Hold From tHD RCLKI Falling RSYSCLK/RCLKI Rise and tR, tF Fall Times Delay RCLKO to RPOSO, tDD RNEGO Valid Delay RCLK to RSER, RDATA, tD1 RSIG, RLINK Valid Delay RCLK to RCHCLK, tD2 RSYNC, RCHBLK, RFSYNC, RLCLK Delay RSYSCLK to RSER, tD3 RSIG Valid Delay RSYSCLK to RCHCLK, tD4 RCHBLK, RMSYNC, RSYNC, CO CI Set Up to RSYSCLK Rising tSC CI Pulse Width tWC (0C to 70C; VDD = 3.3V 5% for DS21354L; 0C to 70C; VDD = 5.0V 5% for DS21554L; -40C to +85C; VDD = 3.3V 5% for DS21354LN; -40C to +85C; VDD = 5.0V 5% for DS21554LN) MIN TYP MAX UNITS NOTES 488 ns 200 244 ns 1 200 244 ns 1 150 244 ns 2 150 244 ns 2 488 ns 75 ns 75 ns 122 648 ns 3 122 488 ns 4 50 ns 50 ns 20 tSH -5 ns 50 20 ns ns 20 ns 20 50 25 ns 50 ns 50 ns 50 ns 50 ns 50 ns ns ns NOTES: 1. Jitter attenuator enabled in the receive path. 2. Jitter attenuator disabled or enabled in the transmit path. 3. RSYSCLK = 1.544 MHz. 4. RSYSCLK = 2.048 MHz. Page 103 of 109 12799 Preliminary DS21354 & DS21554 RECEIVE SIDE AC TIMING Figure 19-8 RCLK t D1 MSB of Channel 1 RSER / RDATA / RSIG t D2 RCHCLK t D2 RCHBLK t D2 RFSYNC / RMSYNC t D2 RSYNC1 t D2 2 RLCLK t D1 RLINK Sa4 to Sa8 Bit Position Notes: 1. RSYNC is in the output mode (RCR1.5 = 0). 2. RLCLK will only pulse high during Sa bit locations as defined in RCR2; no relationship between RLCLK and RSYNC or RFSYNC is implied. Page 104 of 109 12799 Preliminary DS21354 & DS21554 RECEIVE SYSTEM SIDE AC TIMING Figure 19-9 t SL tF tR t SH RSYSCLK t SP t D3 MSB of Channel 1 RSER / RSIG t D4 RCHCLK t D4 RCHBLK t D4 RMSYNC / CO t D4 RSYNC1 t HD t SU RSYNC2 t WC t SC CI Notes: 1. RSYNC is in the output mode (RCR1.5 = 0) 2. RSYNC is in the input mode (RCR1.5 = 1) RECEIVE LINE INTERFACE AC TIMING Figure 19-10 t LL t LH RCLKO t LP t DD RPOSO, RNEGO tR t CL tF t CH RCLKI t CP t SU RPOSI, RNEGI t HD Page 105 of 109 12799 Preliminary DS21354 & DS21554 19.4 Transmit AC Characteristics AC CHARACTERISTICS - TRANSMIT SIDE [See Figures 19-11 to 19-13 for details] PARAMETER SYMBOL TCLK Period tCP TCLK Pulse Width tCH tCL TCLKI Period tLP TCLKI Pulse Width tLH tLL TSYSCLK Period tSP tSP TSYSCLK Pulse Width tSH tSL TSYNC or TSSYNC Set Up to tSU TCLK or TSYSCLK falling TSYNC or TSSYNC Pulse tPW Width TSER, TSIG, TDATA, TLINK, tSU TPOSI, TNEGI Set Up to TCLK, TSYSCLK, TCLKI Falling TSER, TSIG, TDATA, TLINK, tHD TPOSI, TNEGI Hold from TCLK, TSYSCLK, TCLKI Falling TCLK, TCLKI or TSYSCLK tR , tF Rise and Fall Times Delay TCLKO to TPOSO, tDD TNEGO Valid Delay TCLK to TESO Valid tD1 Delay TCLK to TCHBLK, tD2 TCHCLK, TSYNC, TLCLK Delay TSYSCLK to TCHCLK, tD3 TCHBLK, CO CI Set Up to TSYSCLK Rising tSC CI Pulse Width tWC (0C to 70C; VDD = 3.3V 5% for DS21354L; 0C to 70C; VDD = 5.0V 5% for DS21554L; -40C to +85C; VDD = 3.3V 5% for DS21354LN; -40C to +85C; VDD = 5.0V 5% for DS21554LN) MIN TYP MAX UNITS NOTES 488 ns 75 ns 75 ns 488 ns 75 ns 75 ns 122 648 ns 1 122 448 ns 2 50 ns 50 ns 20 tCH -5 or ns tSH -5 50 ns 20 ns 20 ns 20 50 25 ns 50 ns 50 50 ns ns 75 ns ns ns NOTES: 1. TSYSCLK = 1.544 MHz. 2. TSYSCLK = 2.048 MHz. Page 106 of 109 12799 Preliminary DS21354 & DS21554 TRANSMIT SIDE AC TIMING Figure 19-11 t CP t CL tF tR t CH TCLK t D1 TESO t SU TSER / TSIG / TDATA t HD t D2 TCHCLK t D2 TCHBLK t D2 TSYNC1 t SU t HD TSYNC2 5 TLCLK t D2 t HD TLINK t SU Notes: 1. TSYNC is in the output mode (TCR1.0 = 1). 2. TSYNC is in the input mode (TCR1.0 = 0). 3. TSER is sampled on the falling edge of TCLK when the transmit side elastic store is disabled. 4. TCHCLK and TCHBLK are synchronous with TCLK when the transmit side elastic store is disabled. 5. TLINK is only sampled during Sa bit locations as defined in TCR2; no relationship between TLCLK/TLINK and TSYNC is implied. Page 107 of 109 12799 Preliminary DS21354 & DS21554 TRANSMIT SYSTEM SIDE AC TIMING Figure 19-12 t SP t SH t SL tF tR TSYSCLK t SU TSER t D3 t HD TCHCLK / CO t D3 TCHBLK t HD t SU TSSYNC t WC t SC CI Notes: 1. TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled. 2. TCHCLK and TCHBLK are synchronous with TSYSCLK when the transmit side elastic store is enabled. TRANSMIT LINE INTERFACE SIDE AC TIMING Figure 19-13 TCLKO TPOSO, TNEGO t DD tR t LP t LL tF t LH TCLKI t SU TPOSI, TNEGI t HD Page 108 of 109 12799 Preliminary DS21354 & DS21554 20. MECHANICAL DESCRIPTION Page 109 of 109 12799