LM555QML www.ti.com SNOSAP2C - AUGUST 2005 - REVISED APRIL 2013 LM555QML Timer Check for Samples: LM555QML FEATURES DESCRIPTION * * * The LM555 is a highly stable device for generating accurate time delays or oscillation. Additional terminals are provided for triggering or resetting if desired. In the time delay mode of operation, the time is precisely controlled by one external resistor and capacitor. For astable operation as an oscillator, the free running frequency and duty cycle are accurately controlled with two external resistors and one capacitor. The circuit may be triggered and reset on falling waveforms, and the output circuit can source or sink up to 200mA or drive TTL circuits. 1 2 * * * * * Direct Replacement for SE555/NE555 Timing from Microseconds through Hours Operates in Both Astable and Monostable Modes Adjustable Duty Cycle Output can Source or Sink 200 mA Output and Supply TTL Compatible Temperature Stability Better than 0.005% per C Normally On and Normally Off Output APPLICATIONS * * * * * * * Precision Timing Pulse Generation Sequential Timing Time Delay Generation Pulse Width Modulation Pulse Position Modulation Linear Ramp Generator CONNECTION DIAGRAM Figure 1. Dual-In-Line Package Figure 2. Metal Can Package 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2005-2013, Texas Instruments Incorporated LM555QML SNOSAP2C - AUGUST 2005 - REVISED APRIL 2013 www.ti.com SCHEMATIC DIAGRAM These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) Supply Voltage +18V Power Dissipation (2) Metal Can 760 mW CDIP 1180 mW -55C TA +125C Operating Temperature Range Maximum Junction Temperature (TJmax) +150C -65C TA +150C Storage Temperature Range Soldering Information (Soldering 10 Seconds) Thermal Resistance JA JC ESD Tolerance (1) (2) (3) 2 260C CDIP Still Air 125C/W CDIP 500LF / Min Air Flow 71C/W Metal Can Still Air 176C/W Metal Can 500LF / Min Air Flow 96C/W CDIP 20C/W Metal Can 42C/W (3) 500V Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), JA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax - TA)/JA or the number given in the Absolute Maximum Ratings, whichever is lower. Human body model, 1.5K in series with 100pF. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM555QML LM555QML www.ti.com SNOSAP2C - AUGUST 2005 - REVISED APRIL 2013 Table 1. QUALITY CONFORMANCE INSPECTION Subgroup Description Temp C 1 Static tests at 25 2 Static tests at 125 3 Static tests at -55 4 Dynamic tests at 25 5 Dynamic tests at 125 6 Dynamic tests at -55 7 Functional tests at 25 8A Functional tests at 125 8B Functional tests at -55 9 Switching tests at 25 10 Switching tests at 125 11 Switching tests at -55 12 Settling time at 25 13 Settling time at 125 14 Settling time at -55 ELECTRICAL CHARACTERISTICS- DC PARAMETERS The following conditions apply to all the following parameters, unless otherwise specified. DC: +5V VCC +15V Symbol ICCL Max Unit Subgroups VCC = 5V, RL = 5.0 mA 1 VCC = 15V, RL = 12.0 mA 1 VCC = 18V, RL = , V2 = V6 = 18V 18.5 mA 1 100 nA 1 Parameter Supply Current Low State Conditions Notes Min IL7 Leakage Current Pin 7 VCC = 18V, V7 = 18V, V2 = V6 = 0 VSat Saturation Voltage Pin 7 VCC = 15V, I7 = 15mA, V2 = V6 = 12V See (1) 240 mV 1 VCC = 4.5V, I7 = 4.5mA See (1) 80 mV 1 VCO Control Voltage VCC = 5V, V2 = V6 = 4V 2.9 3.8 V 1, 2, 3 VCC = 15V, V2 = V6 = 12V 9.6 10.4 V 1, 2, 3 9.5 10.5 V 1 250 nA 1 1 VTh Threshold Voltage ITh Threshold Current V6 = VTh, V2 = 7.5V, VTh = VTh Test Measured Value ITrig Trigger Current V2 = 0 VTrig Trigger Voltage VCC = 15V VCC = 5V IReset Reset Current VReset Reset Voltage (1) (2) (3) See See (2) (3) 500 nA 4.8 5.2 V 1 3.0 6.0 V 2, 3 1.45 1.9 V 1, 2, 3 0.4 mA 1 1.0 V 1 V2 = V6 = Gnd 0.4 No protection against excessive pin 7 current is necessary providing the package dissipation rating will not be exceeded. This will determine the maximum value of RA + RB for 15V operation. The maximum total (RA + RB) is 20M. Ensured by tests at VCC = 15V. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM555QML 3 LM555QML SNOSAP2C - AUGUST 2005 - REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS- DC PARAMETERS (continued) The following conditions apply to all the following parameters, unless otherwise specified. DC: +5V VCC +15V Symbol VOL Max Unit Subgroups 250 mV 1, 2, 3 VCC = 15V, ISink = +10mA, V2 = V6 = 15V 150 mV 1 250 mV 2, 3 VCC = 15V, ISink = +50mA, V2 = V6 = 15V 500 mV 1 800 mV 2, 3 2.2 V 1, 2, 3 Parameter Output Voltage Drop Low Conditions Notes Min VCC = 5V, ISink = +8mA, V7 = 5V, V6 = 5V VCC = 15V, ISink = +85mA, V2 = V6 = 15V VOH Output Voltage Drop High VCC = 15V, ISource= 85mA VCC = 5V, ISource = 85mA A Timing Error tE / VCC (4) Timing Drift with Supply V 1 V 2, 3 3 V 1 2.75 V 2, 3 See (4) 51 KHz 1 VCC = 5V See (4) 2 % 1, 2, 3 VCC = 15V, 1K RA 100K, Timing error decreases with an increase in VCC See (4) 2 % 1, 2, 3 5V VCC 15V See (4) 0.2 %/V 1, 2, 3 Max Unit Subgroups 9, 10 A Stable Frequency tE 13 12.7 5 45 Ensured parameter, not tested. ELECTRICAL CHARACTERISTICS AC PARAMETERS The following conditions apply to all the following parameters, unless otherwise specified. AC: +5V VCC +15V Symbol tR tF (1) 4 Parameter Rise Time Fall Time Conditions VTrig = 5V VTrig = 5V Notes Min See (1) 250 nS See (1) 400 nS 11 See (1) 250 nS 9, 10 See (1) 400 nS 11 Ensured parameter, not tested. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM555QML LM555QML www.ti.com SNOSAP2C - AUGUST 2005 - REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS Minimum Pulse Width Required for Triggering Supply Current vs. Supply Voltage Figure 3. Figure 4. High Output Voltage vs. Output Source Current Low Output Voltage vs. Output Sink Current Figure 5. Figure 6. Low Output Voltage vs. Output Sink Current Low Output Voltage vs. Output Sink Current Figure 7. Figure 8. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM555QML 5 LM555QML SNOSAP2C - AUGUST 2005 - REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) 6 Output Propagation Delay vs. Voltage Level of Trigger Pulse Output Propagation Delay vs. Voltage Level of Trigger Pulse Figure 9. Figure 10. Discharge Transistor (Pin 7) Voltage vs. Sink Current Discharge Transistor (Pin 7) Voltage vs. Sink Current Figure 11. Figure 12. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM555QML LM555QML www.ti.com SNOSAP2C - AUGUST 2005 - REVISED APRIL 2013 APPLICATIONS INFORMATION MONOSTABLE OPERATION In this mode of operation, the timer functions as a one-shot (Figure 13). The external capacitor is initially held discharged by a transistor inside the timer. Upon application of a negative trigger pulse of less than 1/3 VCC to pin 2, the flip-flop is set which both releases the short circuit across the capacitor and drives the output high. Figure 13. Monostable The voltage across the capacitor then increases exponentially for a period of t = 1.1 RA C, at the end of which time the voltage equals 2/3 VCC. The comparator then resets the flip-flop which in turn discharges the capacitor and drives the output to its low state. Figure 14 shows the waveforms generated in this mode of operation. Since the charge and the threshold level of the comparator are both directly proportional to supply voltage, the timing interval is independent of supply. VCC = 5V TIME = 0.1 ms/DIV. RA = 9.1k C = 0.01F Top Trace: Input 5V/Div. Middle Trace: Output 5V/Div. Bottom Trace: Capacitor Voltage 2V/Div. Figure 14. Monostable Waveforms During the timing cycle when the output is high, the further application of a trigger pulse will not effect the circuit so long as the trigger input is returned high at least 10s before the end of the timing interval. However the circuit can be reset during this time by the application of a negative pulse to the reset terminal (pin 4). The output will then remain in the low state until a trigger pulse is again applied. When the reset function is not in use, it is recommended that it be connected to VCC to avoid any possibility of false triggering. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM555QML 7 LM555QML SNOSAP2C - AUGUST 2005 - REVISED APRIL 2013 www.ti.com Figure 15 is a nomograph for easy determination of R, C values for various time delays. NOTE In monostable operation, the trigger should be driven high before the end of timing cycle. Figure 15. Time Delay ASTABLE OPERATION If the circuit is connected as shown in Figure 16 (pins 2 and 6 connected) it will trigger itself and free run as a multivibrator. The external capacitor charges through RA + RB and discharges through RB. Thus the duty cycle may be precisely set by the ratio of these two resistors. Figure 16. Astable In this mode of operation, the capacitor charges and discharges between 1/3 VCC and 2/3 VCC. As in the triggered mode, the charge and discharge times, and therefore the frequency are independent of the supply voltage. Figure 17 shows the waveforms generated in this mode of operation. 8 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM555QML LM555QML www.ti.com VCC = 5V TIME = 20s/DIV. RA = 3.9k RB = 3k C = 0.01F SNOSAP2C - AUGUST 2005 - REVISED APRIL 2013 Top Trace: Output 5V/Div. Bottom Trace: Capacitor Voltage 1V/Div. Figure 17. Astable Waveforms The charge time (output high) is given by: t1 = 0.693 (RA + RB) C (1) And the discharge time (output low) by: t2 = 0.693 (RB) C (2) Thus the total period is: T = t1 + t2 = 0.693 (RA +2RB) C (3) The frequency of oscillation is: (4) Figure 18 may be used for quick determination of these RC values. The duty cycle is: (5) Figure 18. Free Running Frequency Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM555QML 9 LM555QML SNOSAP2C - AUGUST 2005 - REVISED APRIL 2013 www.ti.com FREQUENCY DIVIDER The monostable circuit of Figure 13 can be used as a frequency divider by adjusting the length of the timing cycle. Figure 19 shows the waveforms generated in a divide by three circuit. VCC = 5V Top Trace: Input 4V/Div. TIME = 20s/DIV. Middle Trace: Output 2V/Div. RA = 9.1k Bottom Trace: Capacitor 2V/Div. C = 0.01F Figure 19. Frequency Divider PULSE WIDTH MODULATOR When the timer is connected in the monostable mode and triggered with a continuous pulse train, the output pulse width can be modulated by a signal applied to pin 5. Figure 20 shows the circuit, and in Figure 21 are some waveform examples. Figure 20. Pulse Width Modulator 10 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM555QML LM555QML www.ti.com SNOSAP2C - AUGUST 2005 - REVISED APRIL 2013 VCC = 5V Top Trace: Modulation 1V/Div. TIME = 0.2 ms/DIV. Bottom Trace: Output Voltage 2V/Div. RA = 9.1k C = 0.01F Figure 21. Pulse Width Modulator PULSE POSITION MODULATOR This application uses the timer connected for astable operation, as in Figure 22, with a modulating signal again applied to the control voltage terminal. The pulse position varies with the modulating signal, since the threshold voltage and hence the time delay is varied. Figure 23 shows the waveforms generated for a triangle wave modulation signal. Figure 22. Pulse Position Modulator VCC = 5V TIME = 0.1 ms/DIV. RA = 3.9k RB = 3k C = 0.01F Top Trace: Modulation Input 1V/Div. Bottom Trace: Output 2V/Div. Figure 23. Pulse Position Modulator Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM555QML 11 LM555QML SNOSAP2C - AUGUST 2005 - REVISED APRIL 2013 www.ti.com LINEAR RAMP When the pullup resistor, RA, in the monostable circuit is replaced by a constant current source, a linear ramp is generated. Figure 24 shows a circuit configuration that will perform this function. Figure 24. Linear Ramp Circuit Configuration Figure 25 shows waveforms generated by the linear ramp. The time interval is given by: (6) (7) VBE 0.6V VCC = 5V Top Trace: Input 3V/Div. TIME = 20s/DIV. Middle Trace: Output 5V/Div. R1 = 47k Bottom Trace: Capacitor Voltage 1V/Div. R2 = 100k RE = 2.7 k C = 0.01 F Figure 25. Linear Ramp 50% DUTY CYCLE OSCILLATOR For a 50% duty cycle, the resistors RA and RB may be connected as in Figure 26. The time period for the output high is the same as previous, t1 = 0.693 RA C. For the output low it is t2 = (8) Thus the frequency of oscillation is (9) 12 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM555QML LM555QML www.ti.com SNOSAP2C - AUGUST 2005 - REVISED APRIL 2013 Figure 26. 50% Duty Cycle Oscillator Note that this circuit will not oscillate if RB is greater than 1/2 RA because the junction of RA and RB cannot bring pin 2 down to 1/3 VCC and trigger the lower comparator. ADDITIONAL INFORMATION Adequate power supply bypassing is necessary to protect associated circuitry. Minimum recommended is 0.1F in parallel with 1F electrolytic. Lower comparator storage time can be as long as 10s when pin 2 is driven fully to ground for triggering. This limits the monostable pulse width to 10s minimum. Delay time reset to output is 0.47s typical. Minimum reset pulse width must be 0.3s, typical. Pin 7 current switches within 30ns of the output (pin 3) voltage. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM555QML 13 LM555QML SNOSAP2C - AUGUST 2005 - REVISED APRIL 2013 www.ti.com Table 2. REVISION HISTORY Date Released 14 Revision Section Originator New Release to corporate format L. Lytle Changes 08/04/05 A 1 MDS datasheet converted into once datasheet in the corporate format. Removed drift endpoints since not performed on 883 product. MNLM555-X Rev 0B0 to be archived 04/10/06 B Ordering Information Table R. Malone NS Package Number and Description was referenced incorrectly. Revision A will be Archived. 07/25/06 C APPLICATIONS INFORMATION R. Malone Correct a typo in the paragraph after Figure 13(change the word internal to interval) to reflect same change made to Commercial data sheet. Revision B will be Archived. 04/01/13 C All Changed layout of National Data Sheet to TI format. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM555QML PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Top-Side Markings (3) (4) LM555H/883 ACTIVE TO-99 LMC 8 20 TBD Call TI Call TI -55 to 125 LM555H/883 Q ACO LM555H/883 Q >T LM555J/883 ACTIVE CDIP NAB 8 40 TBD Call TI Call TI -55 to 125 LM555J /883 Q ACO /883 Q >T (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. 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