1. General description
The HEF4043B is a quad R/S latch with 3-state outputs with a common output enable
input (OE). Each latch has an active HIGH se t input (1S to 4S), an active HIGH reset input
(1R to 4R) and an active HIGH 3-state output (1Q to 4Q).
When OE is HIGH, the latch output (nQ) is d eter mined by the nR an d nS inpu t s as shown
in Table 3. When OE is LOW, the latch outputs are in the high impedance OFF-state. OE
does not affect the state of the latch. The high impedance of f-state fea ture allows common
bussing of the outputs.
It operates over a recommended VDD power supply r ange of 3 V to 15 V r eferenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C
Complies with JEDEC standard JESD 13-B
3. Applications
Four-bit storage with output enable
4. Ordering information
HEF4043B
Quad R/S latch with 3-state outputs
Rev. 10 — 18 November 2011 Product data sheet
Table 1. Ordering information
All types operate from
40
C to +85
C.
Type number Package
Name Description Version
HEF4043BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
HEF4043BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
HEF4043B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 10 — 18 November 2011 2 of 14
NXP Semiconductors HEF4043B
Quad R/S latch with 3-state outputs
5. Functional diagram
6. Pinning information
6.1 Pinning
Fig 1. Functional diagram Fig 2. Logic diagram for one latch
001aae616
1S
3-STATE
OUTPUTS
4
32
1R 1Q
2S6
79
2R 2Q
3S12
11 10
3R 3Q
4S14
15 1
4R 4Q
5 OE
001aae618
nR
OE
nS nQ
to other latches
Fig 3. Pin configuration
HEF4043B
4Q VDD
1Q 4R
1R 4S
1S n.c.
OE 3S
2S 3R
2R 3Q
VSS 2Q
001aae617
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
HEF4043B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 10 — 18 November 2011 3 of 14
NXP Semiconductors HEF4043B
Quad R/S latch with 3-state outputs
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high impedance state.
8. Limiting values
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
Table 2. Pin description
Symbol Pin Description
1Q to 4Q 2, 9, 10, 1 3-state buffered latch output
1R to 4R 3, 7, 11, 15 reset input (active HIGH)
1S to 4S 4, 6, 12, 14 set input (active HIGH)
OE 5 common output enable input
VSS 8 ground supply voltage
n.c. 13 not connected
VDD 16 supply voltage
Table 3. Function table[1]
Inputs Output
OE nS nR nQ
LXXZ
HLHL
HHXH
HLLlatched
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 0.5 +18 V
IIK input clam pi n g cu rre nt VI<0.5 V or VI>V
DD + 0.5 V - 10 mA
VIinput voltage 0.5 VDD + 0.5 V
IOK output clamping current VO<0.5 V or VO>V
DD + 0.5 V - 10 mA
II/O input/out pu t cu rren t - 10 mA
IDD supply current - 50 mA
Tstg storage temperature 65 +150 C
Tamb ambient temp erature 40 +85 C
Ptot total power dissipation Tamb 40 C to +85 C
DIP16 package [1] -750mW
SO16 package [2] -500mW
P power dissipation per output - 100 mW
HEF4043B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 10 — 18 November 2011 4 of 14
NXP Semiconductors HEF4043B
Quad R/S latch with 3-state outputs
9. Recommended operating conditions
10. Static characteristics
Table 5. Recommended operating con ditions
Symbol Parameter Conditions Min Typ Max Unit
VDD supply voltage 3 - 15 V
VIinput voltage 0 - VDD V
Tamb ambient temperature in free air 40 - +85 C
t/V input transition rise and fall rate VDD = 5 V - - 3.75 s/V
VDD = 10 V - - 0.5 s/V
VDD = 15 V - - 0.08 s/V
Table 6. Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter Conditions VDD Tamb = 40 C Tamb = 25 C Tamb = 85 CUnit
Min Max Min Max Min Max
VIH HIGH-level input voltage IO < 1 A 5 V 3.5 - 3.5 - 3.5 - V
10 V 7.0 - 7.0 - 7.0 - V
15 V 11.0 - 11.0 - 11.0 - V
VIL LOW-level input voltage IO < 1 A 5 V - 1.5 - 1.5 - 1.5 V
10 V - 3.0 - 3.0 - 3.0 V
15 V - 4.0 - 4.0 - 4.0 V
VOH HIGH-level output voltage IO < 1 A 5 V 4.95 - 4.95 - 4.95 - V
10 V 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - V
VOL LOW- l e vel output voltage IO < 1 A 5 V - 0.05 - 0.05 - 0.05 V
10 V - 0.05 - 0.05 - 0.05 V
15 V - 0.05 - 0.05 - 0.05 V
IOH HIGH-level output current VO = 2.5 V 5 V - 1.7 - 1.4 - 1.1 mA
VO = 4.6 V 5 V - 0.52 - 0.44 - 0.36 mA
VO = 9.5 V 10 V - 1.3 - 1.1 - 0.9 mA
VO = 13.5 V 15 V - 3.6 - 3.0 - 2.4 mA
IOL LOW - l evel output current VO = 0.4 V 5 V 0.52 - 0.44 - 0.36 - mA
VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA
VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA
IIinput leakage current 15 V - 0.3 - 0.3 - 1.0 A
IOZ OFF-state output current nQ output HIGH;
returned to VDD
15 V - 1.6 - 1.6 - 12.0 A
nQ output LOW;
returned to VSS
15 V - 1.6 - 1.6 - 12.0 A
HEF4043B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 10 — 18 November 2011 5 of 14
NXP Semiconductors HEF4043B
Quad R/S latch with 3-state outputs
11. Dynamic characteristics
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
[2] tt is the same as tTHL and tTLH.
IDD supply current IO = 0 A 5 V - 20 - 20 - 1 50 A
10 V - 40 - 40 - 300 A
15 V - 80 - 80 - 600 A
CIinput capacitance - - - 7.5 - - pF
Table 6. Static characteristics …continued
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter Conditions VDD Tamb = 40 C Tamb = 25 C Tamb = 85 CUnit
Min Max Min Max Min Max
Table 7. Dynamic characteristics
VSS = 0 V; Tamb = 25
C; For waveforms and test circuit see Section 12; unless otherwise specified.
Symbol Parameter Conditions VDD Extrapolation formula Min Typ Max Unit
tPHL HIGH to LOW
propagation delay nR nQ;
see Figure 4 5 V [1] 63 ns + (0.55 ns/pF)CL-90180ns
10 V 24 ns + (0.23 ns/pF)CL-3570ns
15 V 17 ns + (0.16 ns/pF)CL-2550ns
tPLH LOW to HIGH
propagation delay nS nQ;
see Figure 4 5 V [1] 38 ns + (0.55 ns/pF)CL-65135ns
10 V 14 ns + (0.23 ns/pF)CL-2550ns
15 V 7 ns + (0.16 ns/pF)CL-1535ns
tttransition time nQ output;
see Figure 4 5 V [1] [2] 10 ns + (1.00 ns/pF)CL-60120ns
10 V 9 ns + (0.42 ns/pF)CL-3060ns
15 V 6 ns + (0.28 ns/pF)CL-2040ns
tPHZ HIGH to OFF-state
propagation delay OE nQ;
see Figure 5 5 V - 45 90 ns
10 V - 20 35 ns
15 V - 10 25 ns
tPLZ LOW to OFF-state
propagation delay OE nQ;
see Figure 5 5 V - 50 100 ns
10 V - 20 40 ns
15 V - 10 25 ns
tPZH OFF-state to HIGH
propagation delay OE nQ;
see Figure 5 5 V - 25 50 ns
10 V - 15 30 ns
15 V - 10 25 ns
tPZL OFF-state to LOW
propagation delay OE nQ;
see Figure 5 5 V - 40 80 ns
10 V - 20 45 ns
15 V - 15 35 ns
tWpulse width nS input HIGH;
minimum width;
see Figure 4
5 V 30 15 - ns
10 V 20 10 - ns
15 V 16 8 - ns
nR input HIGH;
minimum width;
see Figure 4
5 V 30 15 - ns
10 V 20 10 - ns
15 V 16 8 - ns
HEF4043B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 10 — 18 November 2011 6 of 14
NXP Semiconductors HEF4043B
Quad R/S latch with 3-state outputs
12. Waveforms
Table 8. Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf
20 ns; Tamb = 25
C.
Symbol Parameter VDD Typical formula for PD (W) where:
PDdynamic power
dissipation 5 V PD = 1100 fi + (fo CL) VDD2fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VDD = supply voltage in V;
(fo CL) = sum of the outputs.
10 V PD = 4400 fi + (fo CL) VDD2
15 V PD = 11400 fi + (fo CL) VDD2
tr and tf are the input rise and fall times.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Transition times: transition time (tt) = HIGH LOW (tTHL) or LOW HIGH (tTLH) transition times.
Measurement points are given in Table 9 and test data is given in Table 10.
Fig 4. Input minimum set (nS) and reset (nR) pulse wid ths, inputs nS or nR to latch output (nQ) propagation
delay and nQ transition time
001aai286
input nR
output nQ
t
PHL
t
PLH
0 V
V
I
V
M
V
OH
V
OL
t
THL
t
TLH
input nS
0 V
V
I
V
M
V
M
t
W
t
W
10 %
10 %
90 %
90 %
t
r
t
f
HEF4043B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 10 — 18 November 2011 7 of 14
NXP Semiconductors HEF4043B
Quad R/S latch with 3-state outputs
Measurement points are given in Table 9.
Fig 5. Output enable (OE) to latch output (nQ) enable time (tPZL and tPZH) and disable time (tPLZ and tPHZ)
001aag355
tPLZ
tPHZ
outputs off outputs onoutputs on
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
OE input
VDD
VDD
VSS
VSS
VDD
VSS tPZL
tPZH
VY
VY
VX
VX
Table 9. Measurement points
Supply voltage Input Output
VDD VIVMVMVXVY
5 V to 15 V VDD or 0 V 0.5VDD 0.5VDD 0.1VDD 0.9VDD
HEF4043B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 10 — 18 November 2011 8 of 14
NXP Semiconductors HEF4043B
Quad R/S latch with 3-state outputs
a. Input waveform
b. Test circuit
Test and measurement data is given in Table 10.
Definitions test circuit:
DUT = Device Under Test.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
Fig 6. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
90 %
10 %
t
f
t
r
t
r
t
f
001aaj781
001aaj915
VEXT
VDD
VIVO
DUT
CL
RT
RL
G
Table 10. Test data
Supply voltage Input Load VEXT
VItr, tfCLRLtPLH, tPHL tPLZ, tPZL tPHZ, tPZH
5 V to 15 V VDD 20 ns 50 pF 1 kopen VDD GND
HEF4043B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 10 — 18 November 2011 9 of 14
NXP Semiconductors HEF4043B
Quad R/S latch with 3-state outputs
13. Package outline
Fig 7. Package outline SOT38-4 (DIP16)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT38-4 95-01-14
03-02-13
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
b2
e
D
A2
Z
16
1
9
8
E
pin 1 index
b
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
UNIT A
max. 12 b1(1) (1) (1)
b2cD E e M Z
H
L
mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
min. A
max. bmax.
w
ME
e1
1.73
1.30 0.53
0.38 0.36
0.23 19.50
18.55 6.48
6.20 3.60
3.05 0.2542.54 7.62 8.25
7.80 10.0
8.3 0.764.2 0.51 3.2
inches 0.068
0.051 0.021
0.015 0.014
0.009
1.25
0.85
0.049
0.033 0.77
0.73 0.26
0.24 0.14
0.12 0.010.1 0.3 0.32
0.31 0.39
0.33 0.030.17 0.02 0.13
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
HEF4043B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 10 — 18 November 2011 10 of 14
NXP Semiconductors HEF4043B
Quad R/S latch with 3-state outputs
Fig 8. Package outline SOT109-1 (SO16)
HEF4043B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 10 — 18 November 2011 11 of 14
NXP Semiconductors HEF4043B
Quad R/S latch with 3-state outputs
14. Revision history
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
HEF4043B v.10 20111118 Product data sheet - HEF4043B v.9
Modifications: •Table 6: IOH minimu m values changed to maximum
HEF4043B v.9 20091216 Product data sheet - HEF4043B v.8
HEF4043B v.8 20091127 Product data sheet - HEF4043B v.7
HEF4043B v.7 20090710 Product data sheet - HEF4043B v.6
HEF4043B v.6 20081111 Produ ct data sheet - HEF4043B v.5
HEF4043B v.5 20080729 Product data sheet - HEF4043B v.4
HEF4043B v.4 20080710 Product data sheet - HEF4043B_CNV v.3
HEF4043B_CNV v.3 19950101 Product specification - HEF4043B_CNV v.2
HEF4043B_CNV v.2 19950101 Product specification - -
HEF4043B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 10 — 18 November 2011 12 of 14
NXP Semiconductors HEF4043B
Quad R/S latch with 3-state outputs
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short dat a sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full dat a
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conf lict with the short data sheet, the
full data sheet shall pre vail.
Product specificatio n — The information and data provided in a Product
data sheet shall define the specification of the product as agr eed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental ,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are no t designed,
authorized or warranted to be suit able for use in life support, life-crit ical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors pro duct can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for il lustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liabili ty related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessa ry
testing for th e customer’s applications and pro ducts using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by cust omer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Not hing in this document may be interpret ed or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyri ghts, paten ts or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulatio ns. Export might require a prior
authorization from competent authorities.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contain s data from the objective specification for product development .
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
HEF4043B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 10 — 18 November 2011 13 of 14
NXP Semiconductors HEF4043B
Quad R/S latch with 3-state outputs
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for aut omo tive use. It i s neit her qua lif ied nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever cust omer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting f rom customer design an d
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specif ications.
15.4 Trademarks
Notice: All refe renced brands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors HEF4043B
Quad R/S latch with 3-state outputs
© NXP B.V. 2011. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 18 November 2011
Document iden tifier: HEF4 043B
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Functional description . . . . . . . . . . . . . . . . . . . 3
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
9 Recommended operating conditions. . . . . . . . 4
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
16 Contact information. . . . . . . . . . . . . . . . . . . . . 13
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14