®
Alt er a Cor pora t ion 1
FLEX 8000
Programmable Logic
Device Family
Jan uary 2003, ve r. 11.1 Data Sheet
DS-F8000-11.1
FLEX 8000
3
1
Features... ■Low-cost, high-density, register-rich CMOS programmable logic
device (PLD) family (see Table 1)
– 2,500 to 16,000 usable gates
– 282 to 1,500 registers
■System-level features
– In-circuit reconfigurability (ICR) via external configuration
devices or intelligent controller
– Fully compliant with the peripheral component interconnect
Special Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2 for 5.0-V operation
– Built-in Joint Test Action Group (JTAG) boundary-scan test (BST)
circuitry compliant with IEEE Std. 1149.1-1990 on selected devices
–MultiVolt
TM I/O interface enabling device core to run at 5.0 V,
while I/O pins are compatible with 5.0-V and 3.3-V logic levels
– Low power consumption (typical specification is 0.5 mA or less in
standby mode)
■Flexible interconnect
–FastTrack
® Interconnect continuous routing structure for fast,
predictable interconnect delays
– Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
– Dedicated cascade chain that implements high-speed, high-fan-in
logic functions (automatically used by software tools and
megafunctions)
– Tri-state emulation that implements internal tri-state nets
■Powerful I/O pins
■Programmable output slew-rate control reduces switching noise
Table 1. FLEX 8000 Device Features
Feature EPF8282A
EPF8282AV
EPF8452A EPF8636A EPF8820A EPF81188A EPF81500A
Usable gates 2,500 4,000 6,000 8,000 12,000 16,000
Flipflops 282 452 636 820 1,188 1,500
Logic array blocks (LABs) 26 42 63 84 126 162
Logic elements (LEs) 208 336 504 672 1,008 1,296
Maximum us er I /O pins 78 120 136 152 184 208
2Altera Corporation
FLEX 8000 Programmable Logic Device Family Data Sheet
...and More
Features
■Peripheral register for fast setup and clock-to-output delay
■Fabricated on an advanced SRAM process
■Available in a variety of packages with 84 to 304 pins (see Table 2)
■Software design support and automatic place-and-route provided by
the Altera® MAX+PLUS® II development system for Windows-based
PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM
RISC System/6000 workstations
■Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,
OrCAD, Synopsys, Synplicity, and Veribest
Note:
(1) FLEX 8000 device package types include plastic J-lead chip carrier (PLCC), thin quad flat pack (TQFP), plastic quad
flat pack (PQFP), power quad flat pack (RQFP), ball-grid array (BGA), and pin-grid array (PGA) packages.
General
Description
Altera’s Flexible Logic Element MatriX (FLEX®) family combines the
benefits of both erasable programmable logic devices (EPLDs) and field-
programmable gate arrays (FPGAs). The FLEX 8000 device family is ideal
for a variety of applications because it combines the fine-grained
architecture and high register count characteristics of FPGAs with the
high speed and predictable interconnect delays of EPLDs. Logic is
implemented in LEs that include compact 4-input look-up tables (LUTs)
and programmable registers. High performance is provided by a fast,
continuous network of routing resources.
JTAG BST circuitry Yes No Yes Yes No Yes
Table 2. FLEX 8000 Package Options & I/O Pin Count Note (1)
Device 84-
Pin
PLCC
100-
Pin
TQFP
144-
Pin
TQFP
160-
Pin
PQFP
160-
Pin
PGA
192-
Pin
PGA
208-
Pin
PQFP
225-
Pin
BGA
232-
Pin
PGA
240-
Pin
PQFP
280-
Pin
PGA
304-
Pin
RQFP
EPF8282A 68 78
EPF8282AV 78
EPF8452A 68 68 120 120
EPF8636A 68 118 136 136
EPF8820A 112 120 152 152 152
EPF81188A 148 184 184
EPF81500A 181 208 208
Altera Corporation 3
FLEX 8000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
FLEX 8000
3
FLEX 8000 devices provide a large number of storage elements for
applications such as digital signal processing (DSP), wide-data-path
manipulation, and data transformation. These devices are an excellent
choice for bus interfaces, TTL integration, coprocessor functions, and
high-speed controllers. The high-pin-count packages can integrate
multiple 32-bit buses into a single device. Table 3 shows FLEX 8000
performance and LE requirements for typical applications.
All FLEX 8000 device packages provide four dedicated inputs for
synchronous control signals with large fan-outs. Each I/O pin has an
associated register on the periphery of the device. As outputs, these
registers provide fast clock-to-output times; as inputs, they offer quick
setup times.
The logic and interconnections in the FLEX 8000 architecture are
configured with CMOS SRAM elements. FLEX 8000 devices are
configured at system power-up with data stored in an industry-standard
parallel EPROM or an Altera serial configuration devices, or with data
provided by a system controller. Altera offers the EPC1, EPC1213,
EPC1064, and EPC1441 configuration devices, which configure
FLEX 8000 devices via a serial data stream. Configuration data can also be
stored in an industry-standard 32 K × 8 bit or larger configuration device,
or downloaded from system RAM. After a FLEX 8000 device has been
configured, it can be reconfigured in-circuit by resetting the device and
loading new data. Because reconfiguration requires less than 100 ms, real-
time changes can be made during system operation. For information on
how to configure FLEX 8000 devices, go to the following documents:
■Configuration Devices for APEX & FLEX Devices Data Sheet
■BitBlaster Serial Download Cable Data Sheet
■ByteBlasterMV Parallel Port Download Cable Data Sheet
■Application Note 33 (Configuring FLEX 8000 Devices)
■Application Note 38 (Configuring Multiple FLEX 8000 Devices)
Table 3. FLEX 8000 Performance
Application LEs Used Speed Grade Units
A-2 A-3 A-4
16-bit loadable count er 16 125 95 83 MHz
16-bit up/ dow n c ount er 16 125 95 83 MHz
24-bit ac cumulator 24 87 67 58 MHz
16-bit address decode 44.2 4.9 6.3 ns
16-t o-1 m ult iplex er 10 6.6 7.9 9.5 ns
4Altera Corporation
FLEX 8000 Programmable Logic Device Family Data Sheet
FLEX 8000 devices contain an optimized microprocessor interface that
permits the microprocessor to configure FLEX 8000 devices serially, in
parallel, synchronously, or asynchronously. The interface also enables the
microprocessor to treat a FLEX 8000 device as memory and configure the
device by writing to a virtual memory location, making it very easy for the
designer to create configuration software.
The FLEX 8000 family is supported by Altera’s MAX+PLUS II
development system, a single, integrated package that offers schematic,
text—including the Altera Hardware Description Language (AHDL),
VHDL, and Verilog HDL—and waveform design entry, compilation and
logic synthesis, simulation and timing analysis, and device programming.
The MAX+PLUS II software provides EDIF 2 0 0 and 3 0 0, library of
parameterized modules (LPM), VHDL, Verilog HDL, and other interfaces
for additional design entry and simulation support from other industry-
standard PC- and UNIX workstation-based EDA tools. The
MAX+PLUS II software runs on Windows-based PCs and Sun
SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000
workstations.
The MAX+PLUS II software interfaces easily with common gate array
EDA tools for synthesis and simulation. For example, the MAX+PLUS II
software can generate Verilog HDL files for simulation with tools such as
Cadence Verilog-XL. Additionally, the MAX+PLUS II software contains
EDA libraries that use device-specific features such as carry chains, which
are used for fast counter and arithmetic functions. For instance, the
Synopsys Design Compiler library supplied with the MAX+PLUS II
development system includes DesignWare functions that are optimized
for the FLEX 8000 architecture.
fFor more information on the MAX+PLUS II software, go to the
MAX+PLUS II Programmable Logic Development System & Software Data
Sheet.
Functional
Description
The FLEX 8000 architecture incorporates a large matrix of compact
building blocks called logic elements (LEs). Each LE contains a 4-input
LUT that provides combinatorial logic capability and a programmable
register that offers sequential logic capability. The fine-grained structure
of the LE provides highly efficient logic implementation.
Eight LEs are grouped together to form a logic array block (LAB). Each
FLEX 8000 LAB is an independent structure with common inputs,
interconnections, and control signals. The LAB architecture provides a
coarse-grained structure for high device performance and easy routing.
Altera Corporation 5
FLEX 8000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
FLEX 8000
3
Figure 1 shows a block diagram of the FLEX 8000 architecture. Each group
of eight LEs is combined into an LAB; LABs are arranged into rows and
columns. The I/O pins are supported by I/O elements (IOEs) located at
the ends of rows and columns. Each IOE contains a bidirectional I/O
buffer and a flipflop that can be used as either an input or output register.
Figure 1. FLEX 8000 Device Block Diagram
Signal interconnections within FLEX 8000 devices and between device
pins are provided by the FastTrack Interconnect, a series of fast,
continuous channels that run the entire length and width of the device.
IOEs are located at the end of each row (horizontal) and column (vertical)
FastTrack Interconnect path.
IOEIOE IOEIOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOEIOE IOEIOE
I/O Element
(IOE)
Logic Array
Block (LAB)
Logic
Element (LE)
FastTrack
Interconnect
6Altera Corporation
FLEX 8000 Programmable Logic Device Family Data Sheet
Logic Array Block
A logic array block (LAB) consists of eight LEs, their associated carry and
cascade chains, LAB control signals, and the LAB local interconnect. The
LAB provides the coarse-grained structure of the FLEX 8000 architecture.
This structure enables FLEX 8000 devices to provide efficient routing,
high device utilization, and high performance. Figure 2 shows a block
diagram of the FLEX 8000 LAB.
Figure 2. FLEX 8000 Logic Array Block
Carry-In and
Cascade-In
from LAB
on Left
Dedicated
Inputs
LE1
4
LE8
4
4
LE2
4
4
4
2
2
LE3
4
LE4
4
LE5
4
LE6
4
LE7
4
Column
Interconnect
Row Interconnect
8
24
LAB Local
Interconnect
(32 channels)
8
Column-to-Row
Interconnect
Carry-Out and
Cascade-Out
to LAB on Right
8
16
LAB Control
Signals
See Figure 8
for details.
Altera Corporation 7
FLEX 8000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
FLEX 8000
3
Each LAB provides four control signals that can be used in all eight LEs.
Two of these signals can be used as clocks, and the other two for
clear/preset control. The LAB control signals can be driven directly from
a dedicated input pin, an I/O pin, or any internal signal via the LAB local
interconnect. The dedicated inputs are typically used for global clock,
clear, or preset signals because they provide synchronous control with
very low skew across the device. FLEX 8000 devices support up to four
individual global clock, clear, or preset control signals. If logic is required
on a control signal, it can be generated in one or more LEs in any LAB and
driven into the local interconnect of the target LAB.
Logic Element
The logic element (LE) is the smallest unit of logic in the FLEX 8000
architecture, with a compact size that provides efficient logic utilization.
Each LE contains a 4-input LUT, a programmable flipflop, a carry chain,
and cascade chain. Figure 3 shows a block diagram of an LE.
Figure 3. FLEX 8000 LE
The LUT is a function generator that can quickly compute any function of
four variables. The programmable flipflop in the LE can be configured for
D, T, JK, or SR operation. The clock, clear, and preset control signals on the
flipflop can be driven by dedicated input pins, general-purpose I/O pins,
or any internal logic. For purely combinatorial functions, the flipflop is
bypassed and the output of the LUT goes directly to the output of the LE.
LABCTRL3
LABCTRL4
DATA1
DATA2
DATA3
DATA4
LABCTRL1
LABCTRL2
Carry-In
LE-Out
Clock
Select
Carry-Out
PRN
CLRN
DQ
DFF
Look-Up
Table
(LUT)
Clear/
Preset
Logic
Carry
Chain Cascade
Chain
Cascade-In
Cascade-Out
8Altera Corporation
FLEX 8000 Programmable Logic Device Family Data Sheet
The FLEX 8000 architecture provides two dedicated high-speed data
paths—carry chains and cascade chains—that connect adjacent LEs
without using local interconnect paths. The carry chain supports high-
speed counters and adders; the cascade chain implements wide-input
functions with minimum delay. Carry and cascade chains connect all LEs
in an LAB and all LABs in the same row. Heavy use of carry and cascade
chains can reduce routing flexibility. Therefore, the use of carry and
cascade chains should be limited to speed-critical portions of a design.
Carry Chain
The carry chain provides a very fast (less than 1 ns) carry-forward
function between LEs. The carry-in signal from a lower-order bit moves
forward into the higher-order bit via the carry chain, and feeds into both
the LUT and the next portion of the carry chain. This feature allows the
FLEX 8000 architecture to implement high-speed counters and adders of
arbitrary width. The MAX+PLUS II Compiler can create carry chains
automatically during design processing; designers can also insert carry
chain logic manually during design entry.
Figure 4 shows how an n-bit full adder can be implemented in n+ 1 LEs
with the carry chain. One portion of the LUT generates the sum of two bits
using the input signals and the carry-in signal; the sum is routed to the
output of the LE. The register is typically bypassed for simple adders, but
can be used for an accumulator function. Another portion of the LUT and
the carry chain logic generate the carry-out signal, which is routed directly
to the carry-in signal of the next-higher-order bit. The final carry-out
signal is routed to another LE, where it can be used as a general-purpose
signal. In addition to mathematical functions, carry chain logic supports
very fast counters and comparators.
Altera Corporation 9
FLEX 8000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
FLEX 8000
3
Figure 4. FLEX 8000 Carry Chain Operation
Cascade Chain
With the cascade chain, the FLEX 8000 architecture can implement
functions that have a very wide fan-in. Adjacent LUTs can be used to
compute portions of the function in parallel; the cascade chain serially
connects the intermediate values. The cascade chain can use a logical AND
or logical OR (via De Morgan’s inversion) to connect the outputs of
adjacent LEs. Each additional LE provides four more inputs to the
effective width of a function, with a delay as low as 0.6 ns per LE.
LU
a1
b1
Carry
s1
LE1
Register
a2
b2
Carry Chain
s2
LE2
Register
Carry Chain
s
n
LE
n
Register
a
n
b
n
Carry Chain
Carry-Out
LE
n
+ 1
Register
Carry-In
LUT
LUT
LUT
10 Altera Corporation
FLEX 8000 Programmable Logic Device Family Data Sheet
The MAX+PLUS II Compiler can create cascade chains automatically
during design processing; designers can also insert cascade chain logic
manually during design entry. Cascade chains longer than eight LEs are
automatically implemented by linking LABs together. The last LE of an
LAB cascades to the first LE of the next LAB.
Figure 5 shows how the cascade function can connect adjacent LEs to
form functions with a wide fan-in. These examples show functions of 4n
variables implemented with n LEs. For a device with an A-2 speed grade,
the LE delay is 2.4 ns; the cascade chain delay is 0.6 ns. With the cascade
chain, 4.2 ns is needed to decode a 16-bit address.
Figure 5. FLEX 8000 Cascade Chain Operation
LE Operating Modes
The FLEX 8000 LE can operate in one of four modes, each of which uses
LE resources differently. See Figure 6. In each mode, seven of the ten
available inputs to the LE—the four data inputs from the LAB local
interconnect, the feedback from the programmable register, and the
carry-in and cascade-in from the previous LE—are directed to different
destinations to implement the desired logic function. The three remaining
inputs to the LE provide clock, clear, and preset control for the register.
The MAX+PLUS II software automatically chooses the appropriate mode
for each application. Design performance can also be enhanced by
designing for the operating mode that supports the desired application.
d[3..0]
LE1
LUT
d[7..4]
LE2
LUT
d[(4
n-
1)..4(
n-
1)]
LE
n
LUT
d[3..0] LUT
d[7..4] LUT
d[(4
n-
1)..4(
n-
1)] LUT
LE1
LE2
LE
n
AND Cascade Chain OR Cascade Chain
Altera Corporation 11
FLEX 8000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
FLEX 8000
3
Figure 6. FLEX 8000 LE Operating Modes
PRN
CLRN
DQ
4-Input
LUT
Carry-In
Cascade-Out
LE-Out
Cascade-In
data1
data2
data3
data4
PRN
CLRN
DQ
Cascade-Out
LE-Out
Cascade-In
3-Input
LUT
Carry-In
3-Input
LUT
Carry-Out
data1
data2
PRN
CLRN
DQ
3-Input
LUT
Carry-In Cascade-In
LE-Out
3-Input
LUT
Carry-Out
1
0
Cascade-Out
(ena)
(nclr)
(data)
(nload)
data1
data2
data3
data4
PRN
CLRN
DQ
3-Input
LUT
Carry-In
LE-Out
3-Input
LUT
Carry-Out
1
0
Cascade-Out
(ena)
(nclr)
(data)
(nload)
data1
data2
data3
data4
Normal Mode
Arithmetic Mode
Up/Down Counter Mode
Clearable Counter Mode
12 Altera Corporation
FLEX 8000 Programmable Logic Device Family Data Sheet
Normal Mode
The normal mode is suitable for general logic applications and wide
decoding functions that can take advantage of a cascade chain. In normal
mode, four data inputs from the LAB local interconnect and the carry-in
signal are the inputs to a 4-input LUT. Using a configurable SRAM bit, the
MAX+PLUS II Compiler automatically selects the carry-in or the DATA3
signal as an input. The LUT output can be combined with the cascade-in
signal to form a cascade chain through the cascade-out signal. The LE-Out
signal—the data output of the LE—is either the combinatorial output of
the LUT and cascade chain, or the data output (Q)of the programmable
register.
Arithmetic Mode
The arithmetic mode offers two 3-input LUTs that are ideal for
implementing adders, accumulators, and comparators. One LUT
provides a 3-bit function; the other generates a carry bit. As shown in
Figure 6, the first LUT uses the carry-in signal and two data inputs from
the LAB local interconnect to generate a combinatorial or registered
output. For example, in an adder, this output is the sum of three bits: a, b,
and the carry-in. The second LUT uses the same three signals to generate
a carry-out signal, thereby creating a carry chain. The arithmetic mode
also supports a cascade chain.
Up/Down Counter Mode
The up/down counter mode offers counter enable, synchronous
up/down control, and data loading options. These control signals are
generated by the data inputs from the LAB local interconnect, the carry-in
signal, and output feedback from the programmable register. Two 3-input
LUTs are used: one generates the counter data, and the other generates the
fast carry bit. A 2-to-1 multiplexer provides synchronous loading. Data
can also be loaded asynchronously with the clear and preset register
control signals, without using the LUT resources.
Clearable Counter Mode
The clearable counter mode is similar to the up/down counter mode, but
supports a synchronous clear instead of the up/down control; the clear
function is substituted for the cascade-in signal in the up/down counter
mode. Two 3-input LUTs are used: one generates the counter data, and
the other generates the fast carry bit. Synchronous loading is provided by
a 2-to-1 multiplexer, and the output of this multiplexer is ANDed with a
synchronous clear.
Altera Corporation 13
FLEX 8000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
FLEX 8000
3
Internal Tri-State Emulation
Internal tri-state emulation provides internal tri-stating without the
limitations of a physical tri-state bus. In a physical tri-state bus, the
tri-state buffers’ output enable signals select the signal that drives the bus.
However, if multiple output enable signals are active, contending signals
can be driven onto the bus. Conversely, if no output enable signals are
active, the bus will float. Internal tri-state emulation resolves contending
tri-state buffers to a low value and floating buses to a high value, thereby
eliminating these problems. The MAX+PLUS II software automatically
implements tri-state bus functionality with a multiplexer.
Clear & Preset Logic Control
Logic for the programmable register’s clear and preset functions is
controlled by the DATA3, LABCTRL1, and LABCTRL2 inputs to the LE. The
clear and preset control structure of the LE is used to asynchronously load
signals into a register. The register can be set up so that LABCTRL1
implements an asynchronous load. The data to be loaded is driven to
DATA3; when LABCTRL1 is asserted, DATA3 is loaded into the register.
During compilation, the MAX+PLUS II Compiler automatically selects
the best control signal implementation. Because the clear and preset
functions are active-low, the Compiler automatically assigns a logic high
to an unused clear or preset.
The clear and preset logic is implemented in one of the following six
asynchronous modes, which are chosen during design entry. LPM
functions that use registers will automatically use the correct
asynchronous mode. See Figure 7.
■Clear only
■Preset only
■Clear and preset
■Load with clear
■Load with preset
■Load without clear or preset
14 Altera Corporation
FLEX 8000 Programmable Logic Device Family Data Sheet
Figure 7. FLEX 8000 LE Asynchronous Clear & Preset Modes
Asynchronous Load with Preset
NOT
NOT
LABCTRL1
(Asynchronous
Load)
LABCTRL2
(Preset)
DATA3
(Data)
PRN
CLRN
DQ
Asynchronous Load without Clear or Preset
LABCTRL1
(Asynchronous
Load)
DATA3
(Data)
NOT
NOT
PRN
CLRN
DQ
LABCTRL1
(Asynchronous
Load)
Asynchronous Load with Clear
DATA3
(Data)
LABCTRL2
(Clear)
NOT
NOT
PRN
CLRN
DQ
LABCTRL1 or
LABCTRL2
LABCTRL1 or
LABCTRL2
LABCTRL1
LABCTRL2
Asynchronous Clear Asynchronous Preset Asynchronous Clear & Preset
PRN
CLRN
DQ
VCC
PRN
CLRN
DQ
PRN
CLRN
DQ
Altera Corporation 15
FLEX 8000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
FLEX 8000
3
Asynchronous Clear
A register is cleared by one of the two LABCTRL signals. When the CLRn
port receives a low signal, the register is set to zero.
Asynchronous Preset
An asynchronous preset is implemented as either an asynchronous load
or an asynchronous clear. If DATA3 is tied to VCC, asserting LABCTRLl
asynchronously loads a 1 into the register. Alternatively, the
MAX+PLUS II software can provide preset control by using the clear and
inverting the input and output of the register. Inversion control is
available for the inputs to both LEs and IOEs. Therefore, if a register is
preset by only one of the two LABCTRL signals, the DATA3 input is not
needed and can be used for one of the LE operating modes.
Asynchronous Clear & Preset
When implementing asynchronous clear and preset, LABCTRL1 controls
the preset and LABCTRL2 controls the clear. The DATA3 input is tied to VCC;
therefore, asserting LABCTRL1 asynchronously loads a 1 into the register,
effectively presetting the register. Asserting LABCTRL2 clears the register.
Asynchronous Load with Clear
When implementing an asynchronous load with the clear, LABCTRL1
implements the asynchronous load of DATA3 by controlling the register
preset and clear. LABCTRL2 implements the clear by controlling the
register clear.
Asynchronous Load with Preset
When implementing an asynchronous load in conjunction with a preset,
the MAX+PLUS II software provides preset control by using the clear and
inverting the input and output of the register. Asserting LABCTRL2 clears
the register, while asserting LABCTRL1 loads the register. The
MAX+PLUS II software inverts the signal that drives the DATA3 signal to
account for the inversion of the register’s output.
Asynchronous Load without Clear or Preset
When implementing an asynchronous load without the clear or preset,
LABCTRL1 implements the asynchronous load of DATA3 by controlling the
register preset and clear.
16 Altera Corporation
FLEX 8000 Programmable Logic Device Family Data Sheet
FastTrack Interconnect
In the FLEX 8000 architecture, connections between LEs and device I/O
pins are provided by the FastTrack Interconnect, a series of continuous
horizontal (row) and vertical (column) routing channels that traverse the
entire FLEX 8000 device. This device-wide routing structure provides
predictable performance even in complex designs. In contrast, the
segmented routing structure in FPGAs requires switch matrices to
connect a variable number of routing paths, which increases the delays
between logic resources and reduces performance.
The LABs within FLEX 8000 devices are arranged into a matrix of
columns and rows. Each row of LABs has a dedicated row interconnect
that routes signals both into and out of the LABs in the row. The row
interconnect can then drive I/O pins or feed other LABs in the device.
Figure 8 shows how an LE drives the row and column interconnect.
Figure 8. FLEX 8000 LAB Connections to Row & Column Interconnect
LE1
LE2
Row Channels
16 Column
Channels
Each LE drives up to
two column channels.
to Local
Feedback to Local
Feedback
Each LE drives one
row channel.
(1)
Note:
(1) See Table 4 for the number of row channels.
Altera Corporation 17
FLEX 8000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
FLEX 8000
3
Each LE in an LAB can drive up to two separate column interconnect
channels. Therefore, all 16 available column channels can be driven by the
LAB. The column channels run vertically across the entire device, and
share access to LABs in the same column but in different rows. The
MAX+PLUS II Compiler chooses which LEs must be connected to a
column channel. A row interconnect channel can be fed by the output of
the LE or by two column channels. These three signals feed a multiplexer
that connects to a specific row channel. Each LE is connected to one 3-to-1
multiplexer. In an LAB, the multiplexers provide all 16 column channels
with access to 8 row channels.
Each column of LABs has a dedicated column interconnect that routes
signals out of the LABs into the column. The column interconnect can then
drive I/O pins or feed into the row interconnect to route the signals to
other LABs in the device. A signal from the column interconnect, which
can be either the output of an LE or an input from an I/O pin, must
transfer to the row interconnect before it can enter an LAB. Table 4
summarizes the FastTrack Interconnect resources available in each
FLEX 8000 device.
Figure 9 shows the interconnection of four adjacent LABs, with row,
column, and local interconnects, as well as the associated cascade and
carry chains.
Table 4. FLEX 8000 FastTrack Interconnect Resources
Device Rows Channels per Row Columns Channels per Column
EPF8282A
EPF8282AV 2 168 13 16
EPF8452A 2 168 21 16
EPF8636A 3 168 21 16
EPF8820A 4 168 21 16
EPF81188A 6 168 21 16
EPF81500A 6 216 27 16
18 Altera Corporation
FLEX 8000 Programmable Logic Device Family Data Sheet
Figure 9. FLEX 8000 Device Interconnect Resources
Each LAB is named according to its physical row (A, B, C, etc.) and column (1, 2, 3, etc.) position within the device.
I/O Element
An IOE contains a bidirectional I/O buffer and a register that can be used
either as an input register for external data that requires a fast setup time,
or as an output register for data that requires fast clock-to-output
performance. IOEs can be used as input, output, or bidirectional pins. The
MAX+PLUS II Compiler uses the programmable inversion option to
automatically invert signals from the row and column interconnect where
appropriate. Figure 10 shows the IOE block diagram.
IOEIOE IOEIOE
LAB
A1 LAB
A2
LAB
B1 LAB
B2
LAB Local
Interconnect
Column
Interconnect Row
Interconnect
Cascade &
Carry Chain
IOE
IOE
IOE
IOE
IOE
IOE
IOEIOE
See Figure 11
for details.
See Figure 12
for details.
1
8
1
8
1
8
IOE
IOE
1
8
IOEIOE
Altera Corporation 19
FLEX 8000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
FLEX 8000
3
Figure 10. FLEX 8000 IOE
Numbers in parentheses are for EPF81500A devices only.
Row-to-IOE Connections
Figure 11 illustrates the connection between row interconnect channels
and IOEs. An input signal from an IOE can drive two separate row
channels. When an IOE is used as an output, the signal is driven by an
n-to-1 multiplexer that selects the row channels. The size of the
multiplexer varies with the number of columns in a device. EPF81500A
devices use a 27-to-1 multiplexer; EPF81188A, EPF8820A, EPF8636A, and
EPF8452A devices use a 21-to-1 multiplexer; and EPF8282A and
EPF8282AV devices use a 13-to-1 multiplexer. Eight IOEs are connected to
each side of the row channels.
From Row or Column
Interconnect
Slew-Rate
Control
To Row or Column
Interconnect
I/O Controls
6
(6)
CLRN
DQ
Programmable
Inversion
CLR0
CLR1/OE0
CLK1/OE1
CLK0
(OE [4..9])
OE2
OE3
VCC
VCC
20 Altera Corporation
FLEX 8000 Programmable Logic Device Family Data Sheet
Figure 11. FLEX 8000 Row-to-IOE Connections
Note:
(1) n = 13 for EPF8282A and EPF8282AV devices.
n = 21 for EPF8452A, EPF8636A, EPF8820A, and EPF81188A devices.
n = 27 for EPF81500A devices.
Column-to-IOE Connections
Two IOEs are located at the top and bottom of the column channels (see
Figure 12). When an IOE is used as an input, it can drive up to two
separate column channels. The output signal to an IOE can choose from 8
of the 16 column channels through an 8-to-1 multiplexer.
IOE 1
IOE 2
IOE 3
IOE 4
IOE 5
IOE 6
IOE 7
IOE 8
n
n
n
n
n
n
n
n
2
2
2
2
2
2
2
2
2222
2222
Row Interconnect 168
(216) 168
(216)
Each IOE can drive
up to two row
channels.
Each IOE is
driven by an
n-to-1
multiplexer.
Numbers in parentheses are for EPF81500A devices. See Note (1).
Altera Corporation 21
FLEX 8000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
FLEX 8000
3
Figure 12. FLEX 8000 Column-to-IOE Connections
In addition to general-purpose I/O pins, FLEX 8000 devices have four
dedicated input pins. These dedicated inputs provide low-skew, device-
wide signal distribution, and are typically used for global clock, clear, and
preset control signals. The signals from the dedicated inputs are available
as control signals for all LABs and I/O elements in the device. The
dedicated inputs can also be used as general-purpose data inputs because
they can feed the local interconnect of each LAB in the device.
Signals enter the FLEX 8000 device either from the I/O pins that provide
general-purpose input capability or from the four dedicated inputs. The
IOEs are located at the ends of the row and column interconnect channels.
I/O pins can be used as input, output, or bidirectional pins. Each I/O pin
has a register that can be used either as an input register for external data
that requires fast setup times, or as an output register for data that
requires fast clock-to-output performance. The MAX+PLUS II Compiler
uses the programmable inversion option to invert signals automatically
from the row and column interconnect when appropriate.
The clock, clear, and output enable controls for the IOEs are provided by
a network of I/O control signals. These signals can be supplied by either
the dedicated input pins or by internal logic. The IOE control-signal paths
are designed to minimize the skew across the device. All control-signal
sources are buffered onto high-speed drivers that drive the signals around
the periphery of the device. This “peripheral bus” can be configured to
provide up to four output enable signals (10 in EPF81500A devices), and
up to two clock or clear signals. Figure 13 on page 22 shows how two
output enable signals are shared with one clock and one clear signal.
IOE IOE
88
16
Column Interconnect
Each IOE is
driven by an
8-to-1
multiplexer.
Each IOE can drive
up to two column
signals.
22 Altera Corporation
FLEX 8000 Programmable Logic Device Family Data Sheet
The signals for the peripheral bus can be generated by any of the four
dedicated inputs or signals on the row interconnect channels, as shown in
Figure 13. The number of row channels in a row that can drive the
peripheral bus correlates to the number of columns in the FLEX 8000
device. EPF8282A and EPF8282AV devices use 13 channels; EPF8452A,
EPF8636A, EPF8820A, and EPF81188A devices use 21 channels; and
EPF81500A devices use 27 channels. The first LE in each LAB is the source
of the row channel signal. The six peripheral control signals (12 in
EPF81500A devices) can be accessed by each IOE.
Figure 13. FLEX 8000 Peripheral Bus
Note:
(1) n = 13 for EPF8282A and EPF8282AV devices.
n = 21 for EPF8452A, EPF8636A, EPF8820A, and EPF81188A devices.
n = 27 for EPF81500A devices.
Dedicated
Inputs 4
1
2
n
Peripheral
C
ontrol
Signals
CLR0
CLR1/OE0
CLK0
CLK1/OE1
Row Channels
Programmable
Inversion
OE2
OE3
(OE[4..9])
(1)
Numbers in parentheses are for EPF81500A devices.
Altera Corporation 23
FLEX 8000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
FLEX 8000
3
Table 5 lists the source of the peripheral control signal for each FLEX 8000
device by row.
Output
Configuration
This section discusses slew-rate control and MultiVolt I/O interface
operation for FLEX 8000 devices.
Slew-Rate Control
The output buffer in each IOE has an adjustable output slew rate that can
be configured for low-noise or high-speed performance. A slow slew rate
reduces system noise by slowing signal transitions, adding a maximum
delay of 3.5 ns. The slow slew-rate setting affects only the falling edge of
a signal. The fast slew rate should be used for speed-critical outputs in
systems that are adequately protected against noise. Designers can specify
the slew rate on a pin-by-pin basis during design entry or assign a default
slew rate to all pins on a global basis.
fFor more information on high-speed system design, go to Application
Note 75 (High-Speed Board Designs).
Table 5. Row Sources of FLEX 8000 Peripheral Control Signals
Peripheral
Control Signal
EPF8282A
EPF8282AV EPF8452A EPF8636A EPF8820A EPF81188A EPF81500A
CLK0 Row A Row A Row A Row A Row E Row E
CLK1/OE1 Row B Row B Row C Row C Row B Row B
CLR0 Row A Row A Row B Row B Row F Row F
CLR1/OE0 Row B Row B Row C Row D Row C Row C
OE2 R ow A Row A Row A Row A Row D Row A
OE3 R ow B Row B Row B Row B Row A Row A
OE4 –––––Row B
OE5 –––––Row C
OE6 –––––Row D
OE7 –––––Row D
OE8 –––––Row E
OE9 –––––Row F
24 Altera Corporation
FLEX 8000 Programmable Logic Device Family Data Sheet
MultiVolt I/O Interface
The FLEX 8000 device architecture supports the MultiVolt I/O interface
feature, which allows EPF81500A, EPF81188A, EPF8820A, and EPF8636A
devices to interface with systems with differing supply voltages. These
devices in all packages—except for EPF8636A devices in 84-pin PLCC
packages—can be set for 3.3-V or 5.0-V I/O pin operation. These devices
have one set of VCC pins for internal operation and input buffers
(VCCINT), and another set for I/O output drivers (VCCIO).
The VCCINT pins must always be connected to a 5.0-V power supply. With
a 5.0-V VCCINT level, input voltages are at TTL levels and are therefore
compatible with 3.3-V and 5.0-V inputs.
The VCCIO pins can be connected to either a 3.3-V or 5.0-V power supply,
depending on the output requirements. When the VCCIO pins are
connected to a 5.0-V power supply, the output levels are compatible with
5.0-V systems. When the VCCIO pins are connected to a 3.3-V power
supply, the output high is at 3.3 V and is therefore compatible with 3.3-V
or 5.0-V systems. Devices operating with VCCIO levels lower than 4.75 V
incur a nominally greater timing delay of tOD2 instead of tOD1. See Table 8
on page 26.
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
The EPF8282A, EPF8282AV, EPF8636A, EPF8820A, and EPF81500A
devices provide JTAG BST circuitry. FLEX 8000 devices with JTAG
circuitry support the JTAG instructions shown in Table 6.
Table 6. EPF8282A, EPF8282AV, EPF8636A, EPF8820A & EPF81500A JTAG Instructions
JTAG Instruction Description
SAMPL E/P R ELOAD Allow s a snap sh ot of the sign als at the dev ic e pins to be capt ured and exam ined during
normal device operation, and permits an initial data pattern to be output at the device pins.
EXTEST Allows the external circuitry and board-level interconnections to be tested by forcing a test
pat ter n at the out put pins and c apt uring test resu lts at the input pins.
BYPASS Plac es the 1-b it bypass regist er bet w een t he TDI and TDO pin s, wh ich allow s the BST
dat a to pass sync hronously thro ugh t he s elec te d dev ic e to ad jac ent dev ice s dur ing
norm al dev ic e operation.
Altera Corporation 25
FLEX 8000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
FLEX 8000
3
The instruction register length for FLEX 8000 devices is three bits. Table 7
shows the boundary-scan register length for FLEX 8000 devices.
FLEX 8000 devices that support JTAG include weak pull-ups on the JTAG
pins. Figure 14 shows the timing requirements for the JTAG signals.
Figure 14. EPF8282A, EPF8282AV, EPF8636A, EPF8820A & EPF81500A
JTAG Waveforms
Table 8 shows the timing parameters and values for EPF8282A,
EPF8282AV, EPF8636A, EPF8820A, and EPF81500A devices.
Table 7. FLEX 8000 Boundary-Scan Register Length
Device Boundary-Scan Register Length
EPF8 282A, EPF82 82AV 273
EPF8636A 417
EPF8820A 465
EPF81500A 645
TDO
TCK
tJPZX tJPCO
tJPH
tJPXZ
tJCP
tJPSU
tJCL
tJCH
TDI
TMS
Signal
to Be
Captured
Signal
to Be
Driven
tJSZX
tJSSU tJSH
tJSCO tJSXZ
26 Altera Corporation
FLEX 8000 Programmable Logic Device Family Data Sheet
fFor detailed information on JTAG operation in FLEX 8000 devices, refer to
Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera
Devices).
Generic Testing Each FLEX 8000 device is functionally tested and specified by Altera.
Complete testing of each configurable SRAM bit and all logic
functionality ensures 100% configuration yield. AC test measurements for
FLEX 8000 devices are made under conditions equivalent to those shown
in Figure 15. Designers can use multiple test patterns to configure devices
during all stages of the production flow.
Table 8. JTAG Timing Parameters & Values
Symbol Parameter EPF8282A
EPF8282AV
EPF8636A
EPF8820A
EPF81500A
Unit
Min Max
tJCP TCK clock per iod 100 ns
tJCH TCK clock hig h time 50 ns
tJCL TCK clock low time 50 ns
tJPSU J T AG port setup ti me 20 ns
tJPH JTAG port hold time 45 ns
tJPCO JTAG port clock to output 25 ns
tJPZX JTAG port high-impedance to valid output 25 ns
tJPXZ J T AG port valid outp ut to high-impedance 25 ns
tJSSU C apture regis t er se tu p time 20 ns
tJSH Ca ptu re regis t er hold time 45 ns
tJSCO U pdate regis t er clo ck to outp ut 35 ns
tJSZX U pdate regis t er high-impedance to valid out put 35 ns
tJSXZ U pdate regis t er va lid out put to hig h-im pedance 35 ns
Altera Corporation 27
FLEX 8000 Pr o grammabl e Log i c Dev ic e Fam ily D ata Sh eet
FLEX 8000
3
Figure 15. FLEX 8000 AC Test Conditions
Operating
Conditions
Tables 9 through 12 provide information on absolute maximum ratings,
recommended operating conditions, operating conditions, and
capacitance for 5.0-V FLEX 8000 devices.
VCC
To T est
System
C1 (includes
JIG capacitance)
Device input
rise and fall
times < 3 ns
464 Ω
(703 Ω)
Device
Output
250 Ω
(8.06 KΩ)
Power supply transients can affect AC
measurements. Simultaneous transitions
of multiple outputs should be avoided for
accurate measurement. Threshold tests
must not be performed under AC
conditions. Large-amplitude, fast-ground-
current transients normally occur as the
device outputs discharge the load
capacitances. When these transients flow
through the parasitic inductance between
the device ground pin and the test system
ground, significant reductions in
observable noise immunity can result.
Numbers in parentheses are for 3.3-V
devices or outputs. Numbers without
parentheses are for 5.0-V devices or
outputs.
Table 9. FLEX 8000 5.0-V Device Absolute Maximum Ratings Note (1)
Symbol Parameter Conditions Min Max Unit
VCC Supply vol tag e With res pec t to ground (2) –2.0 7.0 V
VIDC input voltage –2.0 7.0 V
IOUT DC output current, per pin –25 25 mA
TSTG Stora ge te mp erat ure No bias –65 150 ° C
TAMB Ambient temperature Under bias –65 135 ° C
TJJunct ion te m perat ure Ceramic pac k ages , under bias 150 ° C
PQFP and R QF P, under bias 135 ° C