MT9M025: 1/3-Inch CMOS Digital Image Sensor Features 1/3-Inch CMOS Digital Image Sensor MT9M025 Datasheet, Rev. C For the latest datasheet, please visit www.onsemi.com Features * * * * * * * * * Table 1: Superior low-light performance HD video (720p60) Linear or high dynamic range capture Video/Single Frame modes On-chip AE and statistics engine Parallel and serial output Auto black level calibration Context switching Temperature Sensor Parameter Typical Value Optical format 1/3-inch (6 mm) Active pixels 1280 x 960 = 1.2 Mp Pixel size 3.75m Color filter array RGB Bayer or monochrome Shutter type Electronic rolling shutter Input clock range 6 - 50 MHz Output clock maximum 74.25 MHz Applications Output * * * * Frame rate Video surveillance Automotive imaging 720p60 video applications High dynamic range imaging Serial HiSPi 12-, 14-, or 20-bit Parallel 12-bit Full resolution 45 fps 720p 60 fps Responsivity 43.9 dB Maximum dynamic range >115 dB Supply voltage ON Semiconductor's MT9M025 is a 1/3-inch CMOS digital image sensor with an active-pixel array of 1280H x 960V. It captures images in either linear or high dynamic range modes, with a rolling-shutter readout. It includes sophisticated camera functions such as auto exposure control, windowing, and both video and single frame modes. It is designed for both low light and high dynamic range scene performance. It is programmable through a simple two-wire serial interface. The MT9M025 produces extraordinarily clear, sharp digital pictures, and its ability to capture both continuous video and single frames makes it the perfect choice for a wide range of applications, including surveillance and HD video. 5.48 V/lux-sec SNRMAX General Description MT9M025_DS C Pub. 6/15 EN Key Parameters I/O 1.8 or 2.8V* Digital 1.8 V Analog 2.8 V HiSPi 0.4V or 1.8V Power consumption (typical) 270mW (1280x720 60 fps Parallel output Linear Mode) 460mW (1280x720 60 fps Parallel output HDR Mode) Operating temperature (ambient) -TA -40C to + 105 C (automotive) Package options 9x9 mm iBGA Bare die Note: *1.8V VDD_IO is recommended for better row noise performance 1 (c)Semiconductor Components Industries, LLC 2015, MT9M025: 1/3-Inch CMOS Digital Image Sensor Ordering Information Ordering Information Table 2: Available Part Numbers Part Number Product Description Orderable Product Attribute Description MT9M025IA3XTC-DRBR RGB, 0deg CRA, iBGA Package Drypack, Anti-Reflective Glass MT9M025IA3XTC-TRBR RGB, 0deg CRA, iBGA Package Tape & Reel, Anti-Reflective Glass MT9M025IA3XTM-DRBR Mono, 0deg CRA, iBGA Package Drypack, Anti-Reflective Glass MT9M025IA3XTC-TRBR Mono, 0deg CRA, iBGA Package Tape & Reel, Anti-Reflective Glass MT9M025IX3STCD-GEVK RGB Demo Kit MT9M025IX3STCH-GEVB RGB Head Board MT9M025IX3STMD-GEVK Mono Demo Kit MT9M025IX3STMH-GEVB Mono Head Board See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com. MT9M025_DS Rev. C Pub. 6/15 EN 2 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Table of Contents Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Pixel Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Output Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 High Dynamic Range Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Real-Time Context Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Two-Wire Serial Register Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Spectral Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Power-On Reset and Standby Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 MT9M025_DS Rev. C Pub. 6/15 EN 3 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor List of Figures List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Typical Configuration: Serial Four-Lane HiSPi Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Typical Configuration: Parallel Pixel Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 9 x 9 mm 64-Ball IBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Pixel Array Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Pixel Color Pattern Detail (Top Right Corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Imaging a Scene . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Spatial Illustration of Image Readout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Default Pixel Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 LV Format Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 HiSPi Transmitter and Receiver Interface Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Line Timing and FRAME_VALID/LINE_VALID Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 HDR Data Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 PLL-Generated Master Clock PLL Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Six Pixels in Normal and Column Mirror Readout Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Six Rows in Normal and Row Mirror Readout Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Frame Format with Embedded Data Lines Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Format of Embedded Statistics Output within a Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Single READ from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Single READ from Current Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Sequential READ, Start from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Sequential READ, Start from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Single WRITE to Random Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Sequential WRITE, Start at Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Quantum Efficiency - Color Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Estimated Quantum Efficiency - Monochrome Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Two-Wire Serial Bus Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 I/O Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Differential Output Voltage for Clock or Data Pairs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Eye Diagram for Clock and Data Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Skew Within the PHY and Output Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Power Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 64-Ball iBGA Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 MT9M025_DS Rev. C Pub. 6/15 EN 4 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor List of Tables List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Key Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Available Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Pin Descriptions, 9 x 9 mm, 64-ball iBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Frame Time (Example Based on 1280 x 960, 45 Frames Per Second) . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Frame Time: Long Integration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Knee Points for Compression to 14 Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Knee Points for Compression to 12 Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Real-Time Context-Switch Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Test Pattern Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Two-Wire Serial Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 I/O Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Operating Current Consumption in Parallel Output and Linear Mode . . . . . . . . . . . . . . . . . . . . . . . .47 Operating Current Consumption in Parallel Output and HDR Mode . . . . . . . . . . . . . . . . . . . . . . . . . .47 Operating Currents in HiSPi Output and Linear Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Operating Current in HiSPi Output and HDR Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Standby Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Input Voltage and Current (HiSPi Power Supply 0.4 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Input Voltage and Current (HiSPi Power Supply 1.8 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Power-Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 MT9M025_DS Rev. C Pub. 6/15 EN 5 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor General Description General Description The ON Semiconductor MT9M025 can be operated in its default mode or programmed for frame size, exposure, gain, and other parameters. The default mode output is a 960presolution image at 45 frames per second (fps). In linear mode, it outputs 12-bit raw data, using either the parallel or serial (HiSPiTM) output ports. In high dynamic range mode, it outputs 12-bit compressed data using parallel output, or 12-bit or 14-bit compressed or 20-bit linearized data using the HiSPi port. The device may be operated in video (master) mode or in single frame trigger mode. FRAME_VALID and LINE_VALID signals are output on dedicated pins, along with a synchronized pixel clock in parallel mode. The MT9M025 includes additional features to allow application-specific tuning: windowing and offset, adjustable auto-exposure control, auto black level correction, and on-board temperature sensor. Optional register information and histogram statistic information can be embedded in first and last 2 lines of the image frame. The sensor is designed to operate in a wide temperature range (-40C to +105C). Functional Overview The MT9M025 is a progressive-scan sensor that generates a stream of pixel data at a constant frame rate. It uses an on-chip, phase-locked loop (PLL) that can be optionally enabled to generate all internal clocks from a single master input clock running between 6 and 50 MHz The maximum output pixel rate is 74.25 Mp/s, corresponding to a clock rate of 74.25 MHz. Figure 1 shows a block diagram of the sensor. Figure 1: Block Diagram OTPM Active Pixel Sensor (APS) Array Timing and Control (Sequencer) Power Memory External Clock Auto Exposure and Stats Engine Pixel Data Path (Signal Processing) Analog Processing and A/D Conversion PLL Serial Output Parallel Output Trigger Two-Wire Serial Interface Control Registers User interaction with the sensor is through the two-wire serial bus, which communicates with the array control, analog signal chain, and digital signal chain. The core of the sensor is a 1.2 Mp Active- Pixel Sensor array. The timing and control circuitry sequences through the rows of the array, resetting and then reading each row in turn. In the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. The exposure is controlled by varying the time interval between reset and MT9M025_DS Rev. C Pub. 6/15 EN 6 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Functional Overview readout. Once a row has been read, the data from the columns is sequenced through an analog signal chain (providing offset correction and gain), and then through an analogto-digital converter (ADC). The output from the ADC is a 12-bit value for each pixel in the array. The ADC output passes through a digital processing signal chain (which provides further data path corrections and applies digital gain). The sensor also offers a high dynamic range mode of operation where multiple images are combined on-chip to produce a single image at 20-bit per pixel value. A compressing mode is further offered to allow this 20-bit pixel value to be transmitted to the host system as a 12- or 14-bit value with close to zero loss in image quality. The pixel data are output at a rate of up to 74.25 Mp/s, in parallel to frame and line synchronization signals. Typical Configuration: Serial Four-Lane HiSPi Interface VDD_IO 1.5k2, 3 1.5k2 Digital Digital I/O Core power1 power1 Master clock (6-50 MHz) EXTCLK SADDR SDATA SCLK TRIGGER OUTPUT_EN_BAR STANDBY RESET_BAR TEST From controller VDD_IO VDD Notes: MT9M025_DS Rev. C Pub. 6/15 EN VDD_SLVS VDD HiSPi power1 VDD_SLVS Figure 2: VDD_PLL VAA Analog Analog PLL power1 power1 power1 VDD_PLL VAA VAA_PIX SLVS0P SLVS0N SLVS1P SLVS1N SLVS2P SLVS2N SLVS3P SLVS3N SLVSCP SLVSCN DGND AGND Digital ground Analog ground To controller VAA_PIX 1. All power supplies must be adequately decoupled. 2. ON Semiconductor recommends a resistor value of 1.5k, but a greater value may be used for slower two-wire speed. 3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times. 4. The parallel interface output pads can be left unconnected if the serial output interface is used. 5. ON Semiconductor recommends that 0.1F and 10F decoupling capacitors for each power supply are mounted as close as possible to the pad. Actual values and results may vary depending on layout and design considerations. Check the MT9M025 demo headboard schematics for circuit recommendations. 6. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is minimized. 7. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents. 7 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Functional Overview Figure 3: Typical Configuration: Parallel Pixel Data Interface 1.5k2, 3 1.5k2 Digital Digital core I/O power1 power1 VDD_IO PLL Analog Analog power1 power1 power1 VDD Master clock (6-50 MHz) EXTCLK From Controller SADDR SDATA SCLK TRIGGER OUTPUT_EN_BAR STANDBY RESET_BAR VDD_PLL VAA VAA_PIX DOUT [11:0] PIXCLK LINE_VALID FRAME_VALID To controller TEST DGND VDD_IO VDD VDD_PLL VAA VAA_PIX Digital ground Notes: MT9M025_DS Rev. C Pub. 6/15 EN AGND Analog ground 1. All power supplies must be adequately decoupled. 2. ON Semiconductor recommends a resistor value of 1.5k, but a greater value may be used for slower two-wire speed. 3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times. 4. The serial interface output pads and VDDSLVS can be left unconnected if the parallel output interface is used. 5. ON Semiconductor recommends that 0.1F and 10F decoupling capacitors for each power supply are mounted as close as possible to the pad. Actual values and results may vary depending on layout and design considerations. Check the MT9M025 demo headboard schematics for circuit recommendations. 6. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is minimized. 7. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents. 8 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Functional Overview Figure 4: 9 x 9 mm 64-Ball IBGA Package 1 A 2 3 4 SLVS0N SLVS0P SLVS1N 5 6 7 8 SLVS1P VDD VDD STANDBY B VDD_PLL SLVSCN SLVSCP SLVS2N SLVS2P VDD VAA VAA C EXTCLK VDD_ SLVS SLVS3N SLVS3P DGND VDD AGND AGND D SADDR SCLK SDATA DGND DGND VDD VAA_PIX VAA_PIX E LINE_ VALID FRAME_ VALID PIXCLK FLASH DGND VDD_IO NC F DOUT8 DOUT9 DOUT10 DOUT11 DGND VDD_IO TEST G DOUT4 DOUT5 DOUT6 DOUT7 DGND VDD_IO TRIGGER OE_BAR H DOUT0 DOUT1 DOUT2 DOUT3 DGND VDD_IO VDD_IO RESET_ BAR NC Reserved Top View (Ball Down) MT9M025_DS Rev. C Pub. 6/15 EN 9 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Functional Overview Table 1: Pin Descriptions, 9 x 9 mm, 64-ball iBGA Name iBGA Pin SLVS0N A2 Type Description Output HiSPi serial data, lane 0, differential N. SLVS0P A3 Output HiSPi serial data, lane 0, differential P. SLVS1N A4 Output HiSPi serial data, lane 1, differential N. SLVS1P A5 Output HiSPi serial data, lane 1, differential P. STANDBY A8 Input Standby-mode enable pin (active HIGH). VDD_PLL B1 Power PLL power. SLVSCN B2 Output HiSPi serial DDR clock differential N. SLVSCP B3 Output HiSPi serial DDR clock differential P. SLVS2N B4 Output HiSPi serial data, lane 2, differential N. SLVS2P B5 Output HiSPi serial data, lane 2, differential P. VAA B7, B8 Power Analog power. EXTCLK C1 Input External input clock. VDD_SLVS C2 Power HiSPi power. SLVS3N C3 Output HiSPi serial data, lane 3, differential N. SLVS3P C4 Output HiSPi serial data, lane 3, differential P. DGND Power Digital ground. VDD C5, D4, D5, E5, F5, G5, H5 A6, A7, B6, C6, D6 Power Digital power. AGND C7, C8 Power Analog ground. SADDR D1 Input Two-Wire Serial address select. SCLK D2 Input Two-Wire Serial clock input. SDATA D3 I/O Two-Wire Serial data I/O. VAA_PIX D7, D8 Power Pixel power. LINE_VALID E1 Output Asserted when DOUT line data is valid. FRAME_VALID E2 Output Asserted when DOUT frame data is valid. PIXCLK E3 Output Pixel clock out. DOUT is valid on rising edge of this clock. VDD_IO E6, F6, G6, H6, H7 Power I/O supply power. DOUT8 F1 Output Parallel pixel data output. DOUT9 F2 Output Parallel pixel data output. DOUT10 F3 Output Parallel pixel data output. DOUT11 F4 Output Parallel pixel data output (MSB) TEST F7 Input. Manufacturing test enable pin (connect to DGND). DOUT4 G1 Output Parallel pixel data output. DOUT5 G2 Output Parallel pixel data output. DOUT6 G3 Output Parallel pixel data output. DOUT7 G4 Output Parallel pixel data output. TRIGGER G7 Input Exposure synchronization input. OE_BAR G8 Input Output enable (active LOW). DOUT0 H1 Output Parallel pixel data output (LSB) DOUT1 H2 Output Parallel pixel data output. DOUT2 H3 Output Parallel pixel data output. DOUT3 H4 Output Parallel pixel data output. MT9M025_DS Rev. C Pub. 6/15 EN 10 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Pixel Data Format Table 1: Pin Descriptions, 9 x 9 mm, 64-ball iBGA Name iBGA Pin Type Description RESET_BAR H8 Input Asynchronous reset (active LOW). All settings are restored to factory default. FLASH E4 Output Flash control output. NC E7, E8 No connection. Reserved F8 No connection. Pixel Data Format Pixel Array Structure The MT9M025 pixel array is configured as 1412 columns by 1028 rows, (see Figure 5). The dark pixels are optically black and are used internally to monitor black level. Of the right 108 columns, 64 are dark pixels used for row noise correction. Of the top 24 rows of pixels, 12 of the dark rows are used for black level correction. There are 1296 columns by 976 rows of optically active pixels. While the sensor's format is 1280 x 960, the additional active columns and active rows are included for use when horizontal or vertical mirrored readout is enabled, to allow readout to start on the same pixel. The pixel adjustment is always performed for monochrome or color versions. The active area is surrounded with optically transparent dummy pixels to improve image uniformity within the active area. Not all dummy pixels or barrier pixels can be read out. Figure 5: Pixel Array Description 1412 2 light dummy + 4 barrier + 24 dark + 4 barrier + 6 dark dummy 1296 x 976 (1288 x 968 active) 4.86 x 3.66 mm2 (4.83 x 3.63 mm2) 1028 2 light dummy + 4 barrier + 100 dark + 4 barrier 2 light dummy + 4 barrier 2 light dummy + 4 barrier + 6 dark dummy Dark pixel MT9M025_DS Rev. C Pub. 6/15 EN Barrier pixel 11 Light dummy pixel Active pixel (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Pixel Data Format Figure 6: Pixel Color Pattern Detail (Top Right Corner) Column Readout Direction Row Readout Direction Active Pixel (0,0) Array Pixel (110, 40) R G R G R G R G G B G B G B G B R G R G R G R G G B G B G B G B R G R G R G R G G B G B G B G B Default Readout Order By convention, the sensor core pixel array is shown with pixel (0,0) in the top right corner (see Figure 6). This reflects the actual layout of the array on the die. Also, the first pixel data read out of the sensor in default condition is that of pixel (110, 40). When the sensor is imaging, the active surface of the sensor faces the scene as shown in Figure 7. When the image is read out of the sensor, it is read one row at a time, with the rows and columns sequenced as shown in Figure 7 on page 7. Figure 7: Imaging a Scene Lens Scene Sensor (rear view) Row Readout Order Column Readout Order MT9M025_DS Rev. C Pub. 6/15 EN Pixel (0,0) 12 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Output Data Format Output Data Format The MT9M025 image data is read out in a progressive scan. Valid image data is surrounded by horizontal and vertical blanking (see Figure 8). The amount of horizontal row time (in clocks) is programmable through R0x300C. The amount of vertical frame time (in rows) is programmable through R0x300A. Line_Valid (LV) is HIGH during the shaded region of Figure 8. Optional Embedded Register setup information and Histogram statistic information are available in first 2 and last row of image data. Figure 8: Spatial Illustration of Image Readout P0,0 P0,1 P0,2.....................................P0,n-1 P0,n P1,0 P1,1 P1,2.....................................P1,n-1 P1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 HORIZONTAL BLANKING VALID IMAGE Pm-1,0 Pm-1,1.....................................Pm-1,n-1 Pm-1,n Pm,0 Pm,1.....................................Pm,n-1 Pm,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 VERTICAL/HORIZONTAL BLANKING VERTICAL BLANKING 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 Readout Sequence Typically, the readout window is set to a region including only active pixels. The user has the option of reading out dark regions of the array, but if this is done, consideration must be given to how the sensor reads the dark regions for its own purposes. MT9M025_DS Rev. C Pub. 6/15 EN 13 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Output Data Format Parallel Output Data Timing The output images are divided into frames, which are further divided into lines. By default, the sensor produces 968 rows of 1284 columns each. The FV and LV signals indicate the boundaries between frames and lines, respectively. PIXCLK can be used as a clock to latch the data. For each PIXCLK cycle, with respect to the falling edge, one 12-bit pixel datum outputs on the DOUT pins. When both FV and LV are asserted, the pixel is valid. PIXCLK cycles that occur when FV is de-asserted are called vertical blanking. PIXCLK cycles that occur when only LV is de-asserted are called horizontal blanking. Figure 9: Default Pixel Output Timing PIXCLK FV LV DOUT[11:0] P0 Vertical Blanking P1 Horiz Blanking P2 P3 P4 Valid Image Data Pn Horiz Blanking Vertical Blanking LV and FV The timing of the FV and LV outputs is closely related to the row time and the frame time. FV will be asserted for an integral number of row times, which will normally be equal to the height of the output image. LV will be asserted during the valid pixels of each row. The leading edge of LV will be offset from the leading edge of FV by 6 PIXCLKs. Normally, LV will only be asserted if FV is asserted; this is configurable as described below. LV Format Options The default situation is for LV to be de-asserted when FV is de-asserted. By configuring R0x306E[1:0], the LV signal can take two different output formats. The formats for reading out four lines and two vertical blanking lines are shown in Figure 10. Figure 10: LV Format Options FV Default LV FV Continuous LV MT9M025_DS Rev. C Pub. 6/15 EN LV 14 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Output Data Format The timing of an entire frame is shown in Figure 13: "Line Timing and FRAME_VALID/ LINE_VALID Signals," on page 12. Serial Output Data Timing The MT9M024 also uses ON Semiconductor's High-Speed Serial Pixel Interface ("HiSPi"). The physical interface comprises differential serial data lines and a differential clock line. The protocol layer formats the data and synchronization signals separately, with Sync codes defined for active image boundaries. Figure 11 shows the configuration between the HiSPi transmitter and the receiver. There are two options for HiSPi output SLVS or HiVCM mode selectable through register 0x306E bit 9. Setting this bit to 0 selects SLVS; setting the bit to 1 selects HiVCM. Figure 11: HiSPi Transmitter and Receiver Interface Block Diagram A camera containing the HiSPi transmitter Tx PHY0 A host (DSP) containing the HiSPi receiver Dp0 Dp0 Dn0 Dn0 Dp1 Dp1 Dn1 Dn1 Dp2 Dp2 Dn2 Dn2 Dp3 Dp3 Dn3 Dn3 Cp0 Cp0 Cn0 Cn0 Rx PHY0 HiSPi Physical Layer The HiSPi physical layer has four data lanes and an associated clock lane. Depending on the sensor operating mode and data rate, it can be configured to use either 2, 3, or 4 lanes. The PHY will serialize a 12- to 20-bit data word and transmit each bit of data centered on a rising edge of the clock, the second on the following falling edge of clock. Figure 12 shows bit transmission. In this example, the word is transmitted in order of MSB to LSB. The receiver latches data at the rising and falling edge of the clock. MT9M025_DS Rev. C Pub. 6/15 EN 15 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Output Data Format Figure 12: Timing Diagram TxPost cp .... cn TxPre dp dn .... MSB LSB 1 UI MT9M025_DS Rev. C Pub. 6/15 EN 16 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Output Data Format Frame Time The pixel clock (PIXCLK) represents the time needed to sample 1 pixel from the array. The sensor outputs data at the maximum rate of 1 pixel per PIXCLK. One row time (tROW) is the period from the first pixel output in a row to the first pixel output in the next row. The row time and frame time are defined by equations in Table 4. Figure 13: Line Timing and FRAME_VALID/LINE_VALID Signals ... FRAME_VALID ... LINE_VALID ... Number of master clocks Table 2: P1 A Q A Q A P2 Frame Time (Example Based on 1280 x 960, 45 Frames Per Second) Parameter Name Equation Default Timing at 74.25 MHz A Active data time Context A: R0x3008 - R0x3004 + 1 Context B: R0x308E - R0x308A + 1 1280 pixel clocks = 17.23s P1 Frame start blanking 6 (fixed) 6 pixel clocks = 0.08s P2 Frame end blanking 6 (fixed) 6 pixel clocks = 0.08s Q Horizontal blanking R0x300C - A 370 pixel clocks = 4.98s A+Q (tROW) Line (Row) time R0x300C 1650 pixel clocks = 22.22s V Vertical blanking Context A: (R0x300A-(R0x3006-R0x3002+1)) x (A + Q) Context B: ((R0x30AA-(R0x3090-R0x308C+1)) x (A + Q) 49,500 pixel clocks = 666.66s Nrows x (A + Q) Frame valid time Context A: ((R0x3006-R0x3002+1)*(A+Q))-Q+P1+P2 Context B: ((R0x3090-R0x308C+1)*(A+Q))-Q+P1+P2 1,584,000 pixel clocks = 21.33ms F Total frame time V + (Nrows x (A + Q)) 1,633,500 pixel clocks = 22.22ms Sensor timing is shown in terms of pixel clock cycles (see Figure 8 on page 8). The recommended pixel clock frequency is 74.25 MHz. The vertical blanking and the total frame time equations assume that the integration time (coarse integration time plus fine integration time) is less than the number of active lines plus the blanking lines: Window Height + Vertical Blanking (EQ 1) If this is not the case, the number of integration lines must be used instead to determine the frame time, (see Table 5). In this example, it is assumed that the coarse integration time control is programmed with 2000 rows and the fine shutter width total is zero. For Master mode, if the integration time registers exceed the total readout time, then the vertical blanking time is internally extended automatically to adjust for the additional integration time required. This extended value is not written back to the frame_length_lines register. The frame_length_lines register can be used to adjust frame-to-frame readout time. This register does not affect the exposure time but it may extend the readout time. MT9M025_DS Rev. C Pub. 6/15 EN 17 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Output Data Format Table 3: Parameter F' Frame Time: Long Integration Time Name Equation (Number of Pixel Clock Cycles) Default Timing at 74.25 MHz Total frame time (long integration time) Context A: (R0x3012 x (A + Q)) + R0x3014 + P1 + P2 Context B: (R0x3016 x (A + Q)) + V R0x3018 + P1 + P2 3,300,012 pixel clocks = 44.44ms Note: The MT9M025 uses column parallel analog-digital converters; thus short line timing is not possible. The minimum total line time is 1650 columns (horizontal width + horizontal blanking). The minimum horizontal blanking is 370. Exposure Total integration time is the result of Coarse_Integration_Time and Fine_Integration_Time registers, and depends also on whether manual or automatic exposure is selected. The actual total integration time, tINT is defined as: tINT = tINTCoarse - tINTFine (EQ 2) = (number of lines of integration x line time) + (number of pixels of integration x pixel time) where: - Number of Lines of Integration (Auto Exposure Control: Enabled) When automatic exposure control (AEC) is enabled, the number of lines of integration may vary from frame to frame, with the limits controlled by R0x311E (minimum auto exposure time) and R0x311C (maximum auto exposure time). - Number of Lines of Integration (Auto Exposure Control: Disabled) If AEC is disabled, the number of lines of integration equals the value in R0x3012 (context A) or R0x3016 (context B). - Number of Pixels of Integration The number of fine shutter width pixels is independent of AEC mode (enabled or disabled): * Context A: the number of pixels of integration equals the value in R0x3014. * Context B: the number of pixels of integration equals the value in R0x3018. Maximum value for tINTFine is line length pixel clocks - 750. Typically, the value of the Coarse_Integration_Time register is limited to the number of lines per frame (which includes vertical blanking lines), such that the frame rate is not affected by the integration time. For more information on coarse and fine integration time settings limits, please refer to the Register Reference document. Note: MT9M025_DS Rev. C Pub. 6/15 EN In HDR mode, there are specific limitations on coarse_integration_time due to the number of line buffers available. Please refer to the section called "HDR Specific Exposure Settings" on page 16. 18 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor High Dynamic Range Mode High Dynamic Range Mode By default, the sensor powers up in Linear Mode, however, the MT9M025 can be configured to run in HDR mode. The HDR scheme used is multi-exposure HDR. This allows the sensor to handle 120dB of dynamic range. The sensor also features a linear mode. In HDR mode, the sensor sequentially captures three exposures by maintaining 3 separate read and reset pointers that are interleaved within the rolling shutter readout. The intermediate pixel values are stored in line buffers while waiting for the 3 exposures values to be present. As soon as a pixel's 3 exposure values are available, they are combined to create a linearized 20-bit value for each pixel's response. This 20-bit value is then optionally compressed back to a 12- or 14-bit value for output. For 14-bit mode, the compressing is lossless. In 12-bit mode, there is minimal data loss. Figure 14 shows the HDR data compression: Figure 14: HDR Data Compression Digital output code Decompressed linear output ADC max code K2 = knee point 2 K1 = knee point 1 Piece-wise Compressed Signal Output From Sensor Pout = P Signal Response to Light Intensity The HDR mode is selected when Operation_Mode_Ctrl, R0x3082[1:0] = 0. Further controls on exposure time limits and compressing are controlled by R0x3082[5:2], R0x3073, and R0x31D0. More details can be found in the MT9M025 Register Reference. In HDR mode, when compression is used, there are two types of knee-points: (i) T1/T2 and T2/T3 capture knee-points and (ii) POUT and POUT2 compression knee-points (Figure 14). Aligning the capture knee-points on top of the compression knee-points, MT9M025_DS Rev. C Pub. 6/15 EN 19 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor High Dynamic Range Mode can avoid code losses (SNR loss) in the compression. Table 6 and Table 7 below show the knee points for the different modes. Alternatively, the sensor automatically reports the knee points and can be read directly from registers R0x319A and R0x319C. Table 4: Knee Points for Compression to 14 Bits T1/T2 Exposure Ratio (R1) R0x3082[3:2] P1 = P1 P2 POUT2 = (P2 - P1)/ R1 + POUT1 4x 212 4096 214 7168 8x 212 4096 215 7680 16x 212 4096 216 7936 Table 5: POUT1 T2/T3 Exposure Ratio (R2) R0x3082[5:4] PMAX POUTMAX = (PMAX - P2)/ (R1*R2) + POUT2 4x 8x 16x 4x 8x 16x 4x 8x 16x 216 217 218 217 218 219 218 219 220 10240 10752 11008 10752 11264 11520 11008 11520 11776 Knee Points for Compression to 12 Bits T1/T2 Exposure Ratio (R1) R0x3082[3:2] POUT1 = P1 P2 POUT2 = (P2 - P1)/ (R1* 4)+ POUT1 4x 11 2 2048 214 2944 8x 211 2048 215 3008 16x 211 2048 216 3040 MT9M025_DS Rev. C Pub. 6/15 EN P1 20 T2/T3 Exposure Ratio (R2) R0x3082[5:4] PMAX POUTMAX = (PMAX - P2)/ (R1*R2*4) + POUT2 4x 8x 16x 4x 8x 16x 4x 8x 16x 216 217 218 217 218 219 218 219 220 3712 3840 3904 3776 3904 3968 3808 3936 4000 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor High Dynamic Range Mode HDR Specific Exposure Settings In HDR mode, pixel values are stored in line buffers while waiting for all 3 exposures to be available for final pixel data combination. There are 42 line buffers used to store intermediate T1 data. Due to this limitation, the maximum coarse integration time possible is equal to 42*T1/T2 lines. For example, if R0x3082[3:2] = 2, the sensor is set to have T1/T2 ratio = 16x. Therefore the maximum number of integration lines is 42*16 = 672 lines. If coarse integration time is greater than this, the T2 integration time will stay at 42. The sensor will calculate the ratio internally, enabling the linearization to be performed. If companding is being than relinearization would still follow the programmed ratio. For example if the T1/T2 ratio was programmed to 16x but coarse integration was increased beyond 672 than one would still use the 16x relinearization formulas. An additional limitation is the maximum number of exposure lines in relation to the frame_length_lines register. In Linear mode, as described on page 20, maximum coarse_integration_time = frame_length_lines - 1. However in HDR mode, since the coarse integration time register controls T1, the max coarse_integration time is frame_length_lines - 45. Putting the two criteria listed above together, it can be summarized as follows: maximum coarse_integration_time = minimum 42 T1 T2, frame_length_lines - 45 (EQ 3) In HDR mode, subline integration is not utilized. As such, fine integration time register changes will have no effect on the image. There is also a limitation of the minimum number of exposure lines that can be used. This is summarized in the following formula: minimum coarse_integration_time = 0.5* T1 T2 T2 T3 (EQ 4) Motion Compensation In typical multi-exposure HDR systems, motion artifacts can be created when objects move during the T1, T2 or T3 integration time. When this happens, edge artifacts can potentially be visible and might look like a ghosting effect. To correct this feature, the MT9M025 has special 2D motion compensation circuitry that detects motion artifacts and corrects the image accordingly. There are two motion compensation options available. One using the default HDR combination set R0x318C[14] = 1. The motion compensation feature can be enabled by setting R0x318C[14] = 1. Additional parameters are available to control the extent of motion detection and correction as per the requirements of the specific application. These can be set in R0x318C-R0x3190. The other is using the DLO method of HDR combination. When using DLO, R0x318C[14] is ignored. DLO is enabled by setting R0x3190[13] = 1. Noise filtering is enabled by setting R0x3190[14] = 1. For more information, please refer to the MT9M025 Register Reference document. MT9M025_DS Rev. C Pub. 6/15 EN 21 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Real-Time Context Switching Real-Time Context Switching In the MT9M025, the user may switch between two full register sets (listed in Table 8) by writing to a context switch change bit in R0x30B0[13]. This context switch will change all registers (no shadowing) at the frame start time and have the new values apply to the immediate next exposure and readout time. Table 6: . Real-Time Context-Switch Registers Register Number Register Description Context A Context B Y_Addr_Start R0x3002 R0x308C X_Addr_Start R0x3004 R0x308A Y_Addr_End R0x3006 R0x3090 X_Addr_End R0x3008 R0x308E Coarse_Integration_Time R0x3012 R0x3016 Fine_Integration_Time R0x3014 R0x3018 Y_Odd_Inc R0x30A6 R0x30A8 Green1_Gain (GreenR) R0x3056 R0x30BC Blue_Gain R0x3058 R0x30BE Red_Gain R0x305A R0x30C0 Green2_Gain (GreenB) R0x305C R0x30C2 Global_Gain R0x305E R0x30C4 Frame_Length_Lines Digital_Binning Operation_Mode_Ctrl R0x300A R0x30AA R0x3032[1:0] R0x3032[5:4] 0x3082 0x3084 Features See the MT9M025 Register Reference for additional details. Reset The MT9M025 may be reset by using RESET_BAR (active LOW) or the reset register. Hard Reset of Logic The RESET_BAR pin can be connected to an external RC circuit for simplicity. The recommended RC circuit uses a 10k resistor and a 0.1F capacitor. The rise time for the RC circuit is 1s maximum. Soft Reset of Logic Soft reset of logic is controlled by the R0x301A Reset register. Bit 0 is used to reset the digital logic of the sensor while preserving the existing two-wire serial interface configuration. Furthermore, by asserting the soft reset, the sensor aborts the current frame it is processing and starts a new frame. This bit is a self-resetting bit and also returns to "0" during two-wire serial interface reads. Clocks The MT9M025 requires one clock input (EXTCLK). MT9M025_DS Rev. C Pub. 6/15 EN 22 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Features PLL-Generated Master Clock The PLL contains a prescaler to divide the input clock applied on EXTCLK, a VCO to multiply the prescaler output, and two divider stages to generate the output clock. The clocking structure is shown in Figure 15. PLL control registers can be programmed to generate desired master clock frequency. Note: Figure 15: The PLL control registers must be programmed while the sensor is in the software Standby state. The effect of programming the PLL divisors while the sensor is in the streaming state is undefined. PLL-Generated Master Clock PLL Setup PLL Input Clock EXTCLK Pre PLL Div (PFD) Pre_pll_clk_div PLL Output Clock SYSCLK PLL Multiplier (VCO) PLL Output Div 1 PLL Output Div 2 pll_multiplier vt_sys_clk_div vt_pix_clk_div PIXCLK The PLL is enabled by default on the MT9M025. To configure and use the PLL: 1. Bring the MT9M025 up as normal; make sure that fEXTCLK is between 6 and 50MHz and ensure the sensor is in software standby (R0x301A-B[2]= 0). PLL control registers must be set in software standby. 2. Set pll_multiplier, pre_pll_clk_div, vt_sys_clk_siv, and vt_pix_clk_div based on the desired input (fEXTCLK) and output (fPIXCLK) frequencies. Determine the M, N, P1, and P2 values to achieve the desired fPIXCLK using this formula: fPIXCLK= (fEXTCLK x M) / (N x P1 x P2) where M = PLL_Multiplier N = Pre_PLL_Clk_Div P1 = Vt_Sys_Clk_Div P2 = Vt_PIX_Clk_Div 3. Wait 1ms to ensure that the VCO has locked. 4. Set R0x301A[2]=1 to enable streaming and to switch from EXTCLK to the PLL-generated clock. Notes: 1. The PLL can be bypassed at any time (sensor will run directly off EXTCLK) by setting R0x30B0[15]=1. However, only the parallel data interface is supported with the PLL bypassed. The PLL is always bypassed in software standby mode. To disable the PLL, the sensor must be in standby mode (R0x301A[2] = 0) 2. The following restrictions apply to the PLL tuning parameters: 32 M 384 1 N 64 1 P1 16 4 P2 16 MT9M025_DS Rev. C Pub. 6/15 EN 23 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Features 3. The VCO frequency, defined as f VCO = f EXTCLK M N must be within 384-768 MHz. 4. If using HiSPi output mode, use the following settings for P2 (Vt_Pix_Clk_Div). 4a. If 20-bit mode (4 lanes): set P2 (R0x302A) = 5 4b. If 12-/14-bit mode (3 lanes): set P2 (R0x302A) = 5 4c. If 12-bit mode (2 lanes): set P2 (R0x302A) = 6 4d. If 14-bit mode (2 lanes): set P2 (R0x302A) = 7 The user can utilize the Register Wizard tool accompanying DevWare to generate PLL settings given a supplied input clock and desired output frequency. Spread-Spectrum Clocking To facilitate improved EMI performance, the external clock input allows for spread spectrum sources, with no impact on image quality. Limits of the spread spectrum input clock are: * 5% maximum clock modulation * 35 KHz maximum modulation frequency * Accepts triangle wave modulation, as well as sine or modified triangle modulations. Stream/Standby Control The sensor supports two standby modes: Hard Standby and Soft Standby. In both modes, external clock can be optionally disabled to further minimize power consumption. If this is done, then the "Power-Up Sequence" on page 48 must be followed. Soft Standby Soft Standby is a low power state that is controlled through register R0x301A[2]. Depending on the value of R0x301A[4], the sensor will go to standby after completion of the current frame readout (default behavior) or after the completion of the current row readout. When the sensor comes back from Soft Standby, previously written register settings are still maintained. Soft standby will not occur if the TRIGGER pin is held high. A specific sequence needs to be followed to enter and exit from Soft Standby. Entering Soft Standby: 1. R0x301A[12] = 1 if serial mode was used 2. Set R0x301A[2] = 0 and drive the TRIGGER pin LOW. 3. External clock can be turned off to further minimize power consumption (Optional) Exiting Soft Standby: 1. Enable external clock if it was turned off 2. R0x301A[2] = 1 or drive the TRIGGER pin HIGH. 3. R0x301A[12] = 0 if serial mode is used MT9M025_DS Rev. C Pub. 6/15 EN 24 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Features Hard Standby Hard Standby puts the sensor in lower power state; previously written register settings are still maintained. A specific sequence needs to be followed to enter and exit from Hard Standby. Entering Hard Standby: 1. R0x301A[8] = 1 2. R0x301A[12] = 1 if serial mode was used 3. Assert STANDBY pin 4. External clock can be turned off to further minimize power consumption (Optional) Exiting Hard Standby: 1. Enable external clock if it was turned off 2. De-assert STANDBY pin 3. Set R0x301A[8] = 0 Window Control Registers x_addr_start, x_addr_end, y_addr_start, and y_addr_end control the size and starting coordinates of the image window. The exact window height and width out of the sensor is determined by the difference between the Y address start and end registers or the X address start and end registers, respectively. The MT9M025 allows different window sizes for context A and context B. Blanking Control Horizontal blank and vertical blank times are controlled by the line_length_pck and frame_length_lines registers, respectively. * Horizontal blanking is specified in terms of pixel clocks. It is calculated by subtracting the X window size from the line_length_pck register. The minimum horizontal blanking is 370 pixel clocks. * Vertical blanking is specified in terms of numbers of lines. It is calculated by subtracting the Y window size from the frame_length_lines register. The minimum vertical blanking is 26 lines. The actual imager timing can be calculated using Table 4 on page 12 and Table 5 on page 13, which describe the Line Timing and FV/LV signals. When in HDR mode, the maximum size is 1280 x 960. MT9M025_DS Rev. C Pub. 6/15 EN 25 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Features Readout Modes Digital Binning By default, the resolution of the output image is the full width and height of the FOV as defined above. The output resolution can be reduced by digital binning. For RGB and monochrome mode, this is set by the register R0x3032. For Context A, use bits [1:0], for Context B, use bits [5:4]. Available settings are: 00 = No binning 01 = Horizontal binning 10 = Horizontal and vertical binning Binning gives the advantage of reducing noise at the cost of reduced resolution. When both [horizontal and vertical binning are used, a 2x improvement in SNR is achieved, therefore improving low light performance Bayer Space Resampling All of the pixels in the FOV contribute to the output image in digital binning mode. This can result in a more pleasing output image with reduced subsampling artifacts. It also improves low-light performance. For RGB and monochrome mode, the digital binning factor is set by the register DIGITAL_BINNING (R0x3032). For Context A, use bits [1:0], for Context B, use bits [5:4]. Available settings are: 00 = No binning; 01 = Horizontal binning; 10 = Horizontal and vertical binning. For RGB mode, resampling can be enabled by setting of register 0x306E[4] = 1. Mirror Column Mirror Image By setting R0x3040[14] = 1, the readout order of the columns is reversed, as shown in Figure 16. The starting color, and therefore the Bayer pattern, is preserved when mirroring the columns. When using horizontal mirror mode, the user must retrigger column correction. Please refer to the column correction section to see the procedure for column correction retriggering. Bayer resampling must be enabled, by setting bit 4 of register 0 x 306E[4] = 1. Figure 16: Six Pixels in Normal and Column Mirror Readout Modes LV Normal readout DOUT[11:0] G0[11:0] R0[11:0] G1[11:0] R1[11:0] G2[11:0] R2[11:0] G3[11:0] R3[11:0] Reverse readout DOUT[11:0] MT9M025_DS Rev. C Pub. 6/15 EN G4[11:0] R4[11:0] G3[11:0] R3[11:0] G2[11:0] R2[11:0] G1[11:0] R1[11:0] 26 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Features Row Mirror Image By setting R0x3040[15] = 1, the readout order of the rows is reversed as shown in Figure 17. The starting Bayer color pixel is maintained in this mode by a 1-pixel shift in the imaging array. When using horizontal mirror mode, the user must retrigger column correction. Please refer to the column correction section to see the procedure for column correction retriggering. Figure 17: Six Rows in Normal and Row Mirror Readout Modes FV Normal readout Row0 [11:0] Row1 [11:0] Row2 [11:0] Row3 [11:0] Row4 [11:0] Row5 [11:0] DOUT[11:0] Reverse readout DOUT[11:0] Row6 [11:0] Row5 [11:0] Row4 [11:0] Row3 [11:0] Row2 [11:0] Row1 [11:0] Maintaining a Constant Frame Rate Maintaining a constant frame rate while continuing to have the ability to adjust certain parameters is the desired scenario. This is not always possible, however, because register updates are synchronized to the read pointer, and the shutter pointer for a frame is usually active during the readout of the previous frame. Therefore, any register changes that could affect the row time or the set of rows sampled causes the shutter pointer to start over at the beginning of the next frame. By default, the following register fields cause a "bubble" in the output rate (that is, the vertical blank increases for one frame) if they are written in video mode, even if the new value would not change the resulting frame rate. The following list shows only a few examples of such registers; a full listing can be seen in the MT9M025 Register Reference. * x_addr_start * x_addr_end * y_addr_start * y_addr_end * frame_length_lines * line_length_pclk * coarse_integration_time * fine_integration_time * read_mode The size of this bubble is (Integration_Time x tROW ), calculating the row time according to the new settings. The Coarse_Integration_Time and Fine_Integration_Time fields may be written to without causing a bubble in the output rate under certain circumstances. Because the shutter sequence for the next frame often is active during the output of the current frame, this would not be possible without special provisions in the hardware. Writes to these registers take effect two frames after the frame they are written, which allows the integration time to increase without interrupting the output or producing a corrupt frame (as long as the change in integration time does not affect the frame time). MT9M025_DS Rev. C Pub. 6/15 EN 27 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Features Synchronizing Register Writes to Frame Boundaries Changes to most register fields that affect the size or brightness of an image take effect on two frames after the one during which they are written. These fields are noted as "synchronized to frame boundaries" in the MT9M025 Register Reference. To ensure that a register update takes effect on the next frame, the write operation must be completed after the leading edge of FV and before the trailing edge of FV. As a special case, in single frame mode, register writes that occur after FV but before the next trigger will take effect immediately on the next frame, as if there had been a Restart. However, if the trigger for the next frame occurs during FV, register writes take effect as with video mode. Fields not identified as being frame-synchronized are updated immediately after the register write is completed. The effect of these registers on the next frame can be difficult to predict if they affect the shutter pointer. Restart To restart the MT9M025 at any time during the operation of the sensor, write a "1" to the Restart register (R0x301A[1] = 1). This has two effects: first, the current frame is interrupted immediately. Second, any writes to frame-synchronized registers and the shutter width registers take effect immediately, and a new frame starts (in video mode). The current row completes before the new frame is started, so the time between issuing the Restart and the beginning of the next frame can vary by about tROW. Image Acquisition Modes The MT9M025 supports two image acquisition modes: video and single frame. Video The video mode takes pictures by scanning the rows of the sensor twice. On the first scan, each row is released from reset, starting the exposure. On the second scan, the row is sampled, processed, and returned to the reset state. The exposure for any row is therefore the time between the first and second scans. Each row is exposed for the same duration, but at slightly different point in time, which can cause a shear in moving subjects as is typical with electronic rolling shutter sensors. Single Frame The single-frame mode operates similar to the video mode. It also scans the rows of the sensor twice, first to reset the rows and second to read the rows. Unlike video mode where a continuous stream of images are output from the image sensor, the single-frame mode outputs a single frame in response to a high state placed on the TRIGGER input pin. As long as the TRIGGER pin is held in a high state, new images will be read out. After the TRIGGER pin is returned to a low state, the image sensor will not output any new images and will wait for the next high state on the TRIGGER pin. The TRIGGER pin state is detected during the vertical blanking period (i.e. the FV signal is low). The pin is level sensitive rather than edge sensitive. As such, image integration will only begin when the sensor detects that the TRIGGER pin has been held high for 3 consecutive clock cycles. If the trigger signal is applied to multiple sensors at the same time, the single frame output of the sensors will be synchronized to within 1 PIXCLK if is PLL disabled or 2 PIXCLKs if PLL is enabled. MT9M025_DS Rev. C Pub. 6/15 EN 28 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Features The TRIGGER pin state is detected during the vertical blanking period (i.e. the FV signal is low). The pin is level sensitive rather than edge sensitive. As such, image integration will only begin when the sensor detects that the TRIGGER pin has been held high for 3 consecutive clock cycles.During integration time of single-frame mode and video mode, the FLASH output pin is at high. Stereo Timing Synchronization In certain applications, multiple sensors need to have their video streams synchronized (E.g. surround view or panorama view applications). The TRIGGER pin can also be used to synchronize output of multiple image sensors together and still get a video stream. This is called continuous trigger mode. Continuous trigger is enabled by holding the TRIGGER pin high. Alternatively, the TRIGGER pin can be held high until the stream bit is enabled (R0x301A[2]=1) then can be released for continuous synchronized video streaming. If the TRIGGER pins for all connected MT9M025 sensors are connected to the same control signal, all sensors will receive the trigger pulse at the same time. If they are configured to have the same frame timing, then the usage of the TRIGGER pin guarantees that all sensors will be synchronized within 1 PIXCLK cycle if PLL is disabled, or 2 PIXCLK cycles if PLL is enabled. With continuous trigger mode, the application can now make use of the video streaming mode while guaranteeing that all sensor outputs are synchronized. As long as the initial trigger for the sensors takes place at the same time, all subsequent video streams will be synchronous. Temperature Sensor The MT9M025 sensor has a built-in PTAT-based temperature sensor, accessible through registers, that is capable of measuring die junction temperature. The temperature sensor can be enabled by writing R0x30B4[0]=1 and R0x30B4[4]=1. After this, the temperature sensor output value can be read from R0x30B2[10:0]. The value read out from the temperature sensor register is an ADC output value that needs to be converted downstream to a final temperature value in degrees Celsius. Since the PTAT device characteristic response is quite linear in the temperature range of operation required, a simple linear function in the format of listed in the equation below can be used to convert the ADC output value to the final temperature in degrees Celsius. Temperature = slope R0x30B2 10:0 + T 0 (EQ 5) For this conversion, a minimum of 2 known points are needed to construct the line formula by identifying the slope and y-intercept "T0". These calibration values can be read from registers R0x30C6 and R0x30C8 which correspond to value read at 70C and 55C respectively. Once read, the slope and y-intercept values can be calculated and used in the above equation. For more information on the temperature sensor registers, refer to the MT9M025 Register Reference. MT9M025_DS Rev. C Pub. 6/15 EN 29 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Features Automatic Exposure Control The integrated automatic exposure control (AEC) is responsible for ensuring that optimal settings of exposure and gain are computed and updated every other frame. AEC can be enabled or disabled by R0x3100[0]. When AEC is disabled (R0x3100[0] = 0), the sensor uses the manual exposure value in coarse and fine shutter width registers and the manual gain value in the gain registers. When AEC is enabled (R0x3100[0]=1), the target luma value in linear mode is set by R0x3102. For the MT9M025 this target luma has a default value of 0x0800 or about half scale. For HDR mode, the luma target maximum auto exposure value is limited by R0x311C; the minimum auto exposure is limited by R0x311E. These values are in units of line-times. The exposure control measures current scene luminosity by accumulating a histogram of pixel values while reading out a frame. It then compares the current luminosity to the desired output luminosity. Finally, the appropriate adjustments are made to the exposure time and gain. All pixels are used, regardless of color or mono mode. In HDR mode, the coarse and fine integration time is the longest integration time of the three integration, the other two shorter integration are generated automatically base on the predefined exposure ratios. Embedded Data and Statistic The MT9M025 has the capability to output image data and statistics embedded within the frame timing. There are 2 types of information embedded within the frame readout: 1. Embedded Data: If enabled, these are displayed on the 2 rows immediately before the first active pixel row is displayed. 2. Embedded Statistics: If enabled, these are displayed on the 2 rows immediately after the last active pixel row is displayed. Note: Figure 18: One must have both embedded data and embedded statistics enabled or disabled together. Frame Format with Embedded Data Lines Enabled Register Data Image HBlank Status & Statistics Data VBlank MT9M025_DS Rev. C Pub. 6/15 EN 30 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Features Embedded Data The embedded data contains the configuration of the image being displayed. This includes all register settings used to capture the current frame. The registers embedded in these rows are as follows: Line 1: Registers R0x3000 to R0x312F Line 2: Registers R0x3136 to R0x31BF, R0x31D0 to R0x31FF Note: All non-defined registers will have a value of 0. The format of the embedded register data transmission is defined per the embedded data section of the SMIA Function Specification. In parallel mode, since the pixel word depth is 12-bits/pixel, the sensor 16-bit register data will be transferred over 2 pixels where the register data will be broken up into 8msb and 8lsb. The alignment of the 8bit data will be on the 8MSB bits of the 12-bit pixel word. For example, of a register value of 0x1234 is to be transmitted, it will be transmitted over 2, 12-bit pixels as follows: 0x120, 0x340. Embedded Statistics The embedded statistics contain frame identifiers and histogram information of the image in the frame. This can be used by downstream auto-exposure algorithm blocks to make decisions about exposure adjustment. This histogram is divided into 244 bins with a bin spacing of 64 evenly spaced bins for digital code values 0 to 212, 120 evenly spaced bins for values 212 to 216, 60 evenly spaced bins for values 216 to 220. In HDR with a 16x exposure ratio, this approximately corresponds to the T1, T2, T3 exposures respectively. The first pixel of each line in the embedded statistics is a tag value of 0x0B0. This signifies that all subsequent statistics data is 10 bit data aligned to the MSB of the 12-bit pixel. The figure below summarizes how the embedded statistics transmission looks like. It should be noted that data, as shown in Figure 19, is aligned to the msb of each word: Figure 19: Format of Embedded Statistics Output within a Frame data_format_ code = 8'h0B # words = 10'h1EC stats line 1 data_format_ code = 8'h0B # words = 10'h00C {2'b00,frame _count MSB} {2'b00,frame _count LSB} histogram bin1 [19:0] histogram bin1 [9:0] mean [19:10] mean [9:0] lowEndMean [19:10] lowEndMean [9:0] {2'b00,frame _ID MSB} {2'b00,frame _ID LSB} histogram bin0 [19:10] histogram bin0 [9:0] histogram bin243 [19:0] histogram bin243 [9:0] 8'h07 histBegin [19:10] histBegin [9:0] histEnd [19:10] histEnd [9:0] perc_lowEnd [19:10] perc_lowEnd [9:0] norm_abs_ dev [19:10] norm_abs_ dev [9:0] 8'h07 stats line 2 8'h07 The statistics embedded in these rows are as follows: Line 1: * 0x0B0 - identifier * Register 0x303A - frame_count * Register 0x31D2 - frame ID MT9M025_DS Rev. C Pub. 6/15 EN 31 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Features * Histogram data - histogram bins 0-243 Line 2: * 0x0B0 (TAG) * Mean * Histogram Begin * Histogram End * Low End Histogram Mean * Percentage of Pixels Below Low End Mean * Normal Absolute Deviation Gain Digital Gain Digital gain can be controlled globally by R0x305E (Context A) or R0x30C4 (Context B). There are also registers that allow individual control over each Bayer color (GreenR, GreenB, Red, Blue). The format for digital gain setting is xxx.yyyyy where 0b00100000 represents a 1x gain setting and 0b00110000 represents a 1.5x gain setting. The step size for yyyyy is 0.03125 while the step size for xxx is 1. Therefore to set a gain of 2.09375 one would set digital gain to 01000011. Analog Gain The MT9M025 has a column parallel architecture and therefore has an Analog gain stage per column. There are 2 stages of analog gain, the first stage can be set to 1x, 2x, 4x or 8x. This is can be set in R0x30B0[5:4](Context A) or R0x30B0[9:8] (Context B). The second stage is capable of setting an additional 1x or 1.25x gain which can be set in R0x3EE4[9:8]. This allows the maximum possible analog gain to be set to 10x. Black Level Correction Black level correction is handled automatically by the image sensor. No adjustments are provided except to enable or disable this feature. Setting R0x30EA[15] disables the automatic black level correction. Default setting is for automatic black level calibration to be enabled. The automatic black level correction measures the average value of pixels from a set of optically black lines in the image sensor. The pixels are averaged as if they were lightsensitive and passed through the appropriate gain. This line average is then digitally low-pass filtered over many frames to remove temporal noise and random instabilities associated with this measurement. The new filtered average is then compared to a minimum acceptable level, low threshold, and a maximum acceptable level, high threshold. If the average is lower than the minimum acceptable level, the offset correction value is increased by a predetermined amount. If it is above the maximum level, the offset correction value is decreased by a predetermined amount. The high and low thresholds have been calculated to avoid oscillation of the black level from below to above the targeted black level. MT9M025_DS Rev. C Pub. 6/15 EN 32 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Features Row-wise Noise Correction Row (Line)-wise Noise Correction is handled automatically by the image sensor. No adjustments are provided except to enable or disable this feature. Clearing R0x3044[10] disables the row noise correction. Default setting is for row noise correction to be enabled. Row-wise noise correction is performed by calculating an average from a set of optically black pixels at the start of each line and then applying each average to all the active pixels of the line. Column Correction The MT9M025 uses column parallel readout architecture to achieve fast frame rate. Without any corrections, the consequence of this architecture is that different column signal paths have slightly different offsets that might show up on the final image as structured fixed pattern noise. The MT9M025 has column correction circuitry that measures this offset and removes it from the image before output. This is done by sampling dark rows containing tied pixels and measuring an offset coefficient per column to be corrected later in the signal path. Column correction can be enabled/disabled via R0x30D4[15]. Additionally, the number of rows used for this offset coefficient measurement is set in R0x30D4[3:0]. By default this register is set to 0x7, which means that 8 rows are used. This is the recommended value. Other control features regarding column correction can be viewed in the MT9M025 Register reference. Any changes to column correction settings need to be done when the sensor streaming is disabled and the appropriate triggering sequence must be followed as described below. Column Correction Triggering Column correction requires a special procedure to trigger depending on which state the sensor is in. Column Triggering on Startup When streaming the sensor for the first time after powerup, a special sequence needs to be followed to make sure that the column correction coefficients are internally calculated properly. 1. Follow proper power up sequence for power supplies and clocks. 2. Apply sequencer settings if needed (Linear or. HDR mode). 3. Apply frame timing and PLL settings as required by application. 4. Set analog gain to 1x and low conversion gain. 5. Enable column correction and settings. 6. Enable streaming (R0x301A[2]=1)or drive the TRIGGER pin HIGH. 7. Wait 8 frames to settle. 8. Disable streaming (R0x301A[2]=0) or drive the TRIGGER pin LOW. After this, the sensor has calculated the proper column correction coefficients and the sensor is ready for streaming. Any other settings (including gain, integration time and conversion gain etc.) can be done afterwards without affecting column correction. MT9M025_DS Rev. C Pub. 6/15 EN 33 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Features Column Correction Retriggering due to Mode Change Since column offsets is sensitive to changes in the analog signal path, such changes require column correction circuitry to be retriggered for the new path. Examples of such mode changes include: horizontal mirror, vertical mirror, changes to column correction settings. When such changes take place, the following sequence needs to take place: 1. Disable streaming (R0x301A[2]=0) and drive the TRIGGER pin LOW. 2. Disable column correction (0x30D4[15]= 0). 3. Enable streaming (R0x301A[2]=1) or drive the TRIGGER pin HIGH. 4. Wait one frame time, or more. 5. Disable streaming (R0x301A[2]= 0)and drive the TRIGGER pin LOW. 6. Enable column correction (0x30D4[15]= 0). 7. Enable Streaming (R0x301A[2]=1) or drive the TRIGGER pin HIGH. Note: The above steps are not needed if the sensor is being reset (soft or hard reset) upon the mode change. Defective Pixel Correction Defective Pixel Correction is intended to compensate for defective pixels by replacing their value with a value based on the surrounding pixels, making the defect less noticeable to the human eye. The defect pixel correction feature supports up to 200 defects. The locations of defective pixels are stored in a table on chip during the manufacturing process; this table is accessible through the two-wire serial interface. There is no provision for later augmenting the defect table entries. The DPC algorithm is one-dimensional, calculating the resulting averaged pixel value based on nearby pixels within a row. The algorithm distinguishes between color and monochrome parts; for color parts, the algorithm uses nearest neighbor in the same color plane. Test Patterns The MT9M025 has the capability of injecting a number of test patterns into the top of the datapath to debug the digital logic. With one of the test patterns activated, any of the datapath functions can be enabled to exercise it in a deterministic fashion. Test patterns are selected by Test_Pattern_Mode register (R0x3070). Only one of the test patterns can be enabled at a given point in time by setting the Test_Pattern_Mode register according to Table 9. When test patterns are enabled the active area will receive the value specified by the selected test pattern and the dark pixels will receive the value in Test_Pattern_Green (R0x3074 and R0x3078) for green pixels, Test_Pattern_Blue (R0x3076) for blue pixels, and Test_Pattern_Red (R0x3072) for red pixels. Note: Table 7: Turn off black level calibration (BLC) when Test Pattern is enabled. Test Pattern Modes MT9M025_DS Rev. C Pub. 6/15 EN Test_Pattern_Mode Test Pattern Output 0 1 2 3 256 No test pattern (normal operation) Solid color test pattern 100% color bar test pattern Fade-to-gray color bar test pattern Walking 1s test pattern (12-bit) 34 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Features Color Field When the color field mode is selected, the value for each pixel is determined by its color. Green pixels will receive the value in Test_Pattern_Green, red pixels will receive the value in Test_Pattern_Red, and blue pixels will receive the value in Test_Pattern_Blue. Vertical Color Bars When the vertical color bars mode is selected, a typical color bar pattern will be sent through the digital pipeline. Walking 1s When the walking 1s mode is selected, a walking 1s pattern will be sent through the digital pipeline. The first value in each row is 1. MT9M025_DS Rev. C Pub. 6/15 EN 35 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Two-Wire Serial Register Interface Two-Wire Serial Register Interface The two-wire serial interface bus enables read/write access to control and status registers within the MT9M025.The interface protocol uses a master/slave model in which a master controls one or more slave devices. The sensor acts as a slave device. The master generates a clock (SCLK) that is an input to the sensor and is used to synchronize transfers. Data is transferred between the master and the slave on a bidirectional signal (SDATA). SDATA is pulled up to VDD_IO off-chip by a 1.5k resistor. Either the slave or master device can drive SDATA LOW--the interface protocol determines which device is allowed to drive SDATA at any given time. The protocols described in the two-wire serial interface specification allow the slave device to drive SCLK LOW; the MT9M025 uses SCLK as an input only and therefore never drives it LOW. Protocol Data transfers on the two-wire serial interface bus are performed by a sequence of lowlevel protocol elements: 1. a (repeated) start condition 2. a slave address/data direction byte 3. an (a no) acknowledge bit 4. a message byte 5. a stop condition The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with a start condition, and the bus is released with a stop condition. Only the master can generate the start and stop conditions. Start Condition A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH. At the end of a transfer, the master can generate a start condition without previously generating a stop condition; this is known as a "repeated start" or "restart" condition. Stop Condition A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH. Data Transfer Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer mechanism is used for the slave address/data direction byte and for message bytes. One data bit is transferred during each SCLK clock period. SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. MT9M025_DS Rev. C Pub. 6/15 EN 36 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Two-Wire Serial Register Interface Slave Address/Data Direction Byte Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. A "0" in bit [0] indicates a WRITE, and a "1" indicates a READ. The default slave addresses used by the MT9M025 are 0x20(write address) and0x21 (read address) in accordance with the specification. Alternate slave addresses of 0x30 (write address) and 0x31 (read address) can be selected by enabling and asserting the SADDR input. An alternate slave address can also be programmed through R0x31FC. Message Byte Message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. Acknowledge Bit Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the SCLK clock period following the data transfer. The transmitter (which is the master when writing, or the slave when reading) releases SDATA. The receiver indicates an acknowledge bit by driving SDATA LOW. As for data transfers, SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. No-Acknowledge Bit The no-acknowledge bit is generated when the receiver does not drive SDATA LOW during the SCLK clock period following a data transfer. A no-acknowledge bit is used to terminate a read sequence. Typical Sequence A typical READ or WRITE sequence begins by the master generating a start condition on the bus. After the start condition, the master sends the 8-bit slave address/data direction byte. The last bit indicates whether the request is for a read or a write, where a "0" indicates a write and a "1" indicates a read. If the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowledge bit on the bus. If the request was a WRITE, the master then transfers the 16-bit register address to which the WRITE should take place. This transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequence to indicate that the byte has been received. The master then transfers the data as an 8-bit sequence; the slave sends an acknowledge bit at the end of the sequence. The master stops writing by generating a (re)start or stop condition. If the request was a READ, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, the same way as with a WRITE request. The master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, eight bits at a time. The master generates an acknowledge bit after each 8-bit transfer. The slave's internal register address is automatically incremented after every 8 bits are transferred. The data transfer is stopped when the master sends a no-acknowledge bit. MT9M025_DS Rev. C Pub. 6/15 EN 37 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Two-Wire Serial Register Interface Single READ from Random Location This sequence (Figure 20) starts with a dummy WRITE to the 16-bit address that is to be used for the READ. The master terminates the WRITE by generating a restart condition. The master then sends the 8-bit read slave address/data direction byte and clocks out one byte of register data. The master terminates the READ by generating a no-acknowledge bit followed by a stop condition. Figure 20 shows how the internal register address maintained by the MT9M025 is loaded and incremented as the sequence proceeds. Figure 20: Single READ from Random Location Previous Reg Address, N S Slave Address 0 A Reg Address[15:8] S = start condition P = stop condition Sr = restart condition A = acknowledge A = no-acknowledge A Reg Address, M Reg Address[7:0] A Sr Slave Address 1 A M+1 Read Data A P slave to master master to slave Single READ from Current Location This sequence (Figure 21) performs a read using the current value of the MT9M025 internal register address. The master terminates the READ by generating a no-acknowledge bit followed by a stop condition. The figure shows two independent READ sequences. Figure 21: Single READ from Current Location Previous Reg Address, N S Slave Address 1 A Reg Address, N+1 Read Data A P S Slave Address N+2 1 A Read Data A P Sequential READ, Start from Random Location This sequence (Figure 22) starts in the same way as the single READ from random location (Figure 20). Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte READs until "L" bytes have been read. Figure 22: Sequential READ, Start from Random Location Previous Reg Address, N S Slave Address 0 A Reg Address[15:8] M+1 Read Data MT9M025_DS Rev. C Pub. 6/15 EN M+2 A A Reg Address, M Reg Address[7:0] A Sr M+3 Read Data A 38 Slave Address M+L-2 Read Data 1 A M+L-1 A Read Data M+1 Read Data A M+L A P (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Two-Wire Serial Register Interface Sequential READ, Start from Current Location This sequence (Figure 23) starts in the same way as the single READ from current location (Figure 21). Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte READs until "L" bytes have been read. Figure 23: Sequential READ, Start from Current Location Previous Reg Address, N S Slave Address 1 A N+1 Read Data A N+2 Read Data A N+L-1 Read Data A Read Data N+L A P Single WRITE to Random Location This sequence (Figure 24) begins with the master generating a start condition. The slave address/data direction byte signals a WRITE and is followed by the HIGH then LOW bytes of the register address that is to be written. The master follows this with the byte of write data. The WRITE is terminated by the master generating a stop condition. Figure 24: Single WRITE to Random Location Previous Reg Address, N S 0 A Reg Address[15:8] Slave Address A Reg Address, M Reg Address[7:0] Write Data A M+1 A P A Sequential WRITE, Start at Random Location This sequence (Figure 25) starts in the same way as the single WRITE to random location (Figure 24). Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte WRITEs until "L" bytes have been written. The WRITE is terminated by the master generating a stop condition. Figure 25: Sequential WRITE, Start at Random Location Previous Reg Address, N S Slave Address 0 A Reg Address[15:8] M+1 Write Data MT9M025_DS Rev. C Pub. 6/15 EN M+2 A A Reg Address, M Reg Address[7:0] M+3 Write Data 39 A A Write Data M+L-2 Write Data M+1 A M+L-1 A Write Data M+L A P A (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Spectral Characteristics Spectral Characteristics Figure 26: Quantum Efficiency - Color Sensor 70 Quantum Efficiency (%) 60 red green blue 50 40 30 20 10 0 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 Wavelength (nm) MT9M025_DS Rev. C Pub. 6/15 EN 40 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Spectral Characteristics Figure 27: Estimated Quantum Efficiency - Monochrome Sensor MT9M025_DS Rev. C Pub. 6/15 EN 41 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Electrical Specifications Electrical Specifications Unless otherwise stated, the following specifications apply to the following conditions: VDD = 1.8V - 0.10/+0.15; VDD_IO = VDD_PLL = VAA = VAA_PIX = 2.8V 0.3V; VDD_SLVS = 0.4V - 0.1/+0.2; TA = -30C to +70C; output load = 10pF; frequency = 74.25 MHz; HiSPi off. Two-Wire Serial Register Interface The electrical characteristics of the two-wire serial register interface (SCLK, SDATA) are shown in Figure 28 and Table 10. Figure 28: Two-Wire Serial Bus Timing Parameters SDATA tLOW tf tSU;DAT tr tf tHD;STA tr tBUF SCLK S tHD;STA tHD;DAT Note: MT9M025_DS Rev. C Pub. 6/15 EN tHIGH tSU;STA Sr tSU;STO P S Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are issued. 42 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Electrical Specifications Table 8: Two-Wire Serial Bus Characteristics f EXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V; VDD_PLL = 2.8V; VDD_DAC = 2.8V; TA = 25C Standard-Mode Parameter Symbol f SCLK Clock Frequency SCL Fast-Mode Min Max 0 100 8*EXTCLK+SCLK rise time 6*EXTCLK+SCLK rise time SCLK High SCLK Low Min Max Unit 0 400 KHz s 8*EXTCLK+EXTCL K rise time 6*EXTCLK+SCLK rise time s Hold time (repeated) START condition HD;STA 4.0 - 0.6 - s LOW period of the SCLK clock tLOW 4.7 - 1.3 - s HIGH period of the SCLK clock tHIGH 4.0 - 0.6 - s Set-up time for a repeated START condition tSU;STA 4.7 - 0.6 - s Data hold time: tHD;DAT 04 3.455 06 0.95 s Data set-up time tSU;DAT 250 - 1006 - ns Rise time of both SDATA and SCLK signals tr - 1000 20 + 0.1Cb7 300 ns Fall time of both SDATA and SCLK signals tf - 300 20 + 0.1Cb7 300 ns Set-up time for STOP condition tSU;STO 4.0 - 0.6 - s tBUF 4.7 - 1.3 - s Cb - 400 - 400 pF CIN_SI - 3.3 - 3.3 pF After this period, the first clock pulse is generated Bus free time between a STOP and START condition Capacitive load for each bus line Serial interface input pin capacitance SDATA max load capacitance SDATA pull-up resistor Notes: MT9M025_DS Rev. C Pub. 6/15 EN t CLOAD_SD - 30 - 30 pF RSD 1.5 4.7 1.5 4.7 K This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor. Two-wire control is I2C-compatible. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. Sensor EXCLK = 27 MHz. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK. 5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal. 6. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCLK line is released. 7. Cb = total capacitance of one bus line in pF8. 1. 2. 3. 4. 43 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Electrical Specifications I/O Timing By default, the MT9M025 launches pixel data, FV, and LV with the rising edge of PIXCLK. The expectation is that the user captures DOUT[11:0], FV, and LV using the falling edge of PIXCLK. See Figure 29 and Table 11 for I/O timing (AC) characteristics. Figure 29: I/O Timing Diagram tR t RP tF t FP 90% 90% 10% 10% t EXTCLK EXTCLK t CP PIXCLK t PD t PD Data[11:0] Pxl _0 Pxl _1 Pxl _2 Pxl _n t PFH t PFL t PLH FRAME_VALID/ LINE_VALID t PLL FRAME_VALID trails LINE_VALID by 16 PIXCLKs. FRAME_VALID leads LINE_VALID by 609 PIXCLKs. *PLL disabled for tCP Table 9: I/O Timing Characteristics Symbol Definition Condition Min Typ Max Unit fEXTCLK1 Input clock frequency PLL enabled 6 - 50 MHz tEXTCLK1 Input clock period PLL enabled 20 - 166 ns fEXTCLK2 Input clock frequency PLL disabled 6 - 50 MHz tEXTCLK2 Input clock period PLL disabled 20 - 166 ns tR Input clock rise time Slew setting = 3 - 3 - ns tF Input clock fall time Slew setting = 3 t Pixclk rise time RP tFP t (PIX JITTER) - 3 - ns 2 4 7 ns Pixclk fall time 3 4 8 ns Clock duty cycle 45 50 55 % Jitter on PIXCLK - 1 tJITTER2 Input clock jitter 74.25 MHz - 600 - ps tCP EXTCLK to PIXCLK propagation delay Nominal voltages, PLL Disabled 12 - 18 ns fPIXCLK PIXCLK frequency Default, Nominal Voltages 6 74.25 MHz tPD PIXCLK to data valid Default, Nominal Voltages -2 2.3 4 ns tPFH PIXCLK to FV HIGH Default, Nominal Voltages -2 1.5 4 ns tPLH PIXCLK to LV HIGH Default, Nominal Voltages -3 2.3 4 ns tPFL PIXCLK to FV LOW Default, Nominal Voltages -3 1.5 4 ns tPLL PIXCLK to LV LOW Default, Nominal Voltages -2 2 4 ns MT9M025_DS Rev. C Pub. 6/15 EN 44 ns (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Electrical Specifications Table 9: I/O Timing Characteristics (continued) Symbol Definition CLOAD CIN Min Typ Max Unit Output load capacitance - <10 - pF Input pin capacitance - 2.5 - pF MT9M025_DS Rev. C Pub. 6/15 EN Condition 45 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Electrical Specifications DC Electrical Characteristics The DC electrical characteristics are shown in the tables below. Table 10: DC Electrical Characteristics Symbol Definition VDD Core digital voltage Condition Min Typ Max Unit 1.7 1.8 1.95 V VDD_IO I/O digital voltage 1.7/2.5 1.9/3.1 V 2.5 1.8/ 2.8 2.8 VAA Analog voltage VAA_PIX 2.9 V VDD_PLL Pixel supply voltage 2.5 2.8 2.9 V PLL supply voltage 2.5 2.8 3.1 V VDD_SLVS HiSPi supply voltage for SLVS mode 0.3 0.4 0.6 V VDD_SLVS HiSPi supply voltage for HiVcm mode 1.7 1.8 1.95 V VIH Input HIGH voltage VDD_IO*0.7 - - V VIL Input LOW voltage No pull-up resistor; VIN = VDD_IO or DGND - - VDD_IO*0.3 V 20 - - A IIN Input leakage current VOH Output HIGH voltage VDD_IO-0.3 - - V VOL Output LOW voltage - - 0.4 V IOH Output HIGH current At specified VOH -22 - - mA IOL Output LOW current At specified VOL - - 22 mA Caution Table 11: Stresses greater than those listed in Table 14 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Absolute Maximum Ratings Symbol Parameter VSUPPLY Power supply voltage (all supplies) ISUPPLY Total power supply current IGND Total ground current VIN DC input voltage VOUT DC output voltage -0.3 TSTG1 Storage temperature -40 Notes: MT9M025_DS Rev. C Pub. 6/15 EN Minimum Maximum Unit Symbol -0.3 4.3 V VSUPPLY - 200 mA ISUPPLY - 200 mA IGND -0.3 VDD_IO + 0.3 V VIN VDD_IO + 0.3 V VOUT +150 C TSTG1 1. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. To keep dark current and shot noise artifacts from impacting image quality, keep operating temperature at a minimum. 46 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Electrical Specifications Table 12: Operating Current Consumption in Parallel Output and Linear Mode Definition Condition Digital operating current Streaming, 1280x960 45fps I/O digital operating current Streaming, 1280x960 45fps Symbol Min Typ Max Unit IDD1 - 63 90 mA IDD_IO - 35 40 mA Analog operating current Streaming, 1280x960 45fps IAA - 30 45 mA Pixel supply current Streaming, 1280x960 45fps IAA_PIX - 10 15 mA PLL supply current Streaming, 1280x960 45fps IDD_PLL - 7 15 mA Digital operating current Streaming, 720p 60 fps IDD1 - 63 90 mA I/O digital operating current Streaming, 720p 60 fps IDD_IO - 35 40 mA Analog operating current Streaming, 720p 60 fps IAA - 30 45 mA Pixel supply current Streaming, 720p 60 fps IAA_PIX - 10 15 mA PLL supply current Streaming, 720p 60f ps IDD_PLL - 7 15 mA Notes: Table 13: 1. Operating currents are measured at the following conditions: VAA = VAA_PIX = VDD_IO = VDD_PLL = 2.8V VDD =1.8V PLL Enabled and PIXCLK =7 4.25 MHz TA = 25C Cload = 10pF Measured in dark Operating Current Consumption in Parallel Output and HDR Mode Definition Condition Symbol Min Typ Max Unit Digital operating current Streaming, 1280x960 45fps IDD - 95 115 mA I/O digital operating current Streaming, 1280x960 45fps IDD_IO - 35 40 mA Analog operating current Streaming, 1280x960 45fps IAA - 65 75 mA Pixel supply current Streaming, 1280x960 45fps IAA_PIX - 15 20 mA PLL supply current Streaming, 1280x960 45fps IDD_PLL - 7 15 mA Digital operating current Streaming, 720p 60 fps IDD - 95 115 mA I/O digital operating current Streaming, 720p 60 fps IDD_IO - 35 40 mA Analog operating current Streaming, 720p 60 fps IAA - 61 75 mA Pixel supply current Streaming, 720p 60 fps IAA_PIX - 65 20 mA PLL supply current Streaming, 720p 60 fps IDD_PLL - 7 15 mA Notes: MT9M025_DS Rev. C Pub. 6/15 EN 1. Operating currents are measured at the following conditions: VAA = VAA_PIX = VDD_IO = VDD_PLL = 2.8V VDD = 1.8V PLL Enabled and PIXCLK = 74.25 MHz TA= 25C Cload = 10pF Measured in dark 47 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Electrical Specifications Table 14: Operating Currents in HiSPi Output and Linear Mode Definition Condition Symbol Min Typ Max Unit Digital Operating Current Streaming 1280x960 45fps IDD - 95 115 mA I/O digital operating current Streaming 1280x960 45fps IDD_IO - 100 150 A Analog operating current Streaming 1280x960 45fps IAA - 30 45 mA Pixel Supply Current Streaming 1280x960 45fps IAA_PIX - 10 15 mA PLL Supply Current Streaming 1280x960 45fps IDD_PLL - 7 15 mA Current LoVCM Mode Streaming 1280x960 45fps IDD_SLVS - 8 15 mA - 16 25 mA SLVS Supply Current Current HiVCM Mode Streaming 1280x960 45fps Digital Operating Current Streaming 720p 60 fps IDD - 95 115 mA I/O digital operating current Streaming 720p 60 fps IDD_IO - 100 150 A Analog operating current Streaming 720p 60 fps IAA - 30 45 mA Pixel Supply Current Streaming 720p 60 fps IAA_PIX - 10 15 mA PLL Supply Current Streaming 720p 60 fps IDD_PLL - 7 15 mA Current LoVCM Mode Streaming 720p 60 fps IDD_SLVS - 8 15 mA - 16 25 mA SLVS Supply Current Current HiVCM Mode Streaming 1280x960 60fps Notes: Table 15: 1. Operating currents are measured at the following conditions: VAA = VAA_PIX = VDD_IO = VDD_PLL = 2.8V VDD = 1.8V VDD_SLVS = 0.4V (LoVCM) VDD_SLVS = 1.8V (HiVCM) PLL Enabled and PIXCLK = 74.25 MHz TA = 25C Cload = 10pF Measured in dark Operating Current in HiSPi Output and HDR Mode Definition Condition Symbol Min Digital Operating Current Streaming 1280x960 45 fps IDD - I/O digital operating current Streaming 1280x960 45 fps IDD_IO - Typ Max Unit 115 130 mA 100 150 A Analog operating current Streaming 1280x960 45 fps IAA - 65 75 mA Pixel Supply Current Streaming 1280x960 45 fps IAA_PIX - 15 20 mA PLL Supply Current Streaming 1280x960 45 fps IDD_PLL - 7 15 mA IDD_SLVS - 8 15 mA SLVS Supply Current Current LoVCM Mode Streaming 1280x960 45 fps - 16 25 mA Current HiVCM Mode Streaming 1280x960 45 fps Digital Operating Current Streaming 720p 60 fps IDD - 115 130 mA I/O digital operating current Streaming 720p 60 fps IDD_IO - 100 150 A MT9M025_DS Rev. C Pub. 6/15 EN 48 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Electrical Specifications Table 15: Operating Current in HiSPi Output and HDR Mode (continued) Analog operating current Streaming 720p 60 fps IAA - 65 75 mA Pixel Supply Current Streaming 720p 60 fps IAA_PIX - 15 20 mA PLL Supply Current SLVS Supply Current IDD_PLL - 7 15 mA IDD_SLVS - 8 15 mA - 16 25 mA Current HiVCM Mode Streaming 1280x960 60fps Notes: Table 16: Streaming 720p 60 fps Current LoVCM Mode Streaming 720p 60 fps 1. Operating currents are measured at the following conditions: VAA=VAA_PIX=VDD_IO=VDD_PLL=2.8V VDD=1.8V VDD_SLVS = 0.4V (LoVCM) VDD_SLVS = 1.8V (HiVCM) PLL Enabled and PIXCLK=74.25MHz TA = 25C Cload = 10pF Measured in dark Standby Current Consumption Definition Condition Hard standby (clock off) Hard standby (clock on) Soft standby (clock off) Soft standby (clock on) Notes: MT9M025_DS Rev. C Pub. 6/15 EN Symbol Min Typ Max Unit Analog, 2.8V - - 30 - A Digital, 1.8V - - 85 - A Analog, 2.8V - - 30 - A Digital, 1.8V - - 1.55 - mA Analog, 2.8V - - 85 - A Digital, 1.8V - - 85 - A Analog, 2.8V - - 30 - A Digital, 1.8V - - 1.55 - mA 1. Analog - VAA + VAA_PIX + VDD_PLL 2. Digital - VDD + VDD_IO + VDD_SLVS 49 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Electrical Specifications HiSPi Electrical Specifications The HiSPi transmitter electrical specifications are listed at 700 MHz. Table 17: Input Voltage and Current (HiSPi Power Supply 0.4 V) Measurement Conditions: Max Freq 700 MHz Parameter Symbol Min Typ Max Unit IDD_SLVS - 10 15 A HiSPi common mode voltage (driving 100 load) VCMD VDD_SLVS x 0.45 VDD_SLVS/2 VDD_SLVS x 0.55 V HiSPi differential output voltage (driving 100 load) |VOD| VDD_SLVS x 0.36 VDD_SLVS/2 VDD_SLVS x 1.64 V Change in VCM between logic 1 and 0 VCM 25 mV Change in |VOD| between logic 1 and 0 |VOD| 25 mV Supply current (PWRHiSPi) (driving 100 load) Vod noise margin NM -30 30 Difference in VCM between any two channels |VCM| 50 mV Difference in VOD between any two channels |VOD| 100 mV Common-mode AC voltage (pk) without VCM cap termination VCM_ac 50 mV Common-mode AC voltage (pk) with VCM cap termination VCM_ac 25 mV Max overshoot peak |VOD| VOD_ac 1.2*|VOD| V Max overshoot Vdiff pk-pk Vdiff_pkpk 2.4*|VOD| V Eye Height Veye 0.5*VDD_SLVS Ro 35 Single-ended output impedance Output impedance mismatch Table 18: 50 Ro 70 20 % Input Voltage and Current (HiSPi Power Supply 1.8 V) Measurement Conditions: Max Freq 700 MHz Symbol Min Typ Max Unit IDD_HiVCM - 15 25 mA HiSPi common mode voltage (driving 100 load) VCMD 0.76 0.9 1.07 V HiSPi differential output voltage (driving 100 load) |VOD| 200 280 350 V Parameter Supply current (PWRHiSPi) (driving 100 load) Change in VCM between logic 1 and 0 VCM 25 Change in |VOD| between logic 1 and 0 VOD| 25 VOD noise margin Difference in VCM between any two channels NM -30 30 VCM| 50 VOD| 100 Common-mode AC voltage (pk) without VCMcap termination VCM_ac 50 Common-mode AC voltage (pk) with VCM cap termination VCM_ac 30 Difference in VOD between any two channels MT9M025_DS Rev. C Pub. 6/15 EN 50 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Electrical Specifications Table 18: Input Voltage and Current (HiSPi Power Supply 1.8 V) Measurement Conditions: Max Freq 700 MHz Symbol Parameter Min Typ Max Max overshoot peak |VOD| VOD_ac 1.2*|VOD| Max overshoot Vdiff pk-pk Vdiff_pkpk 2.4*|VOD| Eye Height Single-ended Output impedance 320 Ro 40 70 V 100 Ro Output impedance mismatch Figure 30: Veye Unit 20 % Differential Output Voltage for Clock or Data Pairs VDIFFmax VDIFFmin 0V Diff) Output Signal is 'Cp - Cn' or 'Dp - D Table 19: Rise and Fall Times Measurement Conditions: HiSPi Power Supply 0.4V or 1.8V, Max Freq 700 MHz Parameter Symbol Min Data Rate 1/UI Max setup time from transmitter TxPRE TxPost 0.3 - - UI CLKJITTER - 50 - ps Max hold time from transmitter Clock jitter (RMS) Typ Max Unit 280 - 700 Mb/s 0.3 - - UI1 Rise time (20% - 80%) RISE - 0.325UI - Fall time (20% - 80%) FALL 150ps 0.3 UI - 50 Clock duty PLL_DUTY 45 Bitrate Period tpw 1.43 Eye Width teye 0.3 55 % 3.57 ns1 UI1, 2 totaljit 0.2 UI1, 2 Clock Period Jitter (RMS) tckjit 50 ps2 Clock cycle to cycle jitter (RMS) tcyjit 100 ps2 0.1 UI1, 2 2.1 UI1, 5 Data Total jitter (pk pk)@1e-9 Clock to Data Skew tchskew PHY-to-PHY Skew tPHYskew Notes: MT9M025_DS Rev. C Pub. 6/15 EN -0.1 1. One UI is defined as the normalized mean time between one edge and the following edge of the clock. 2. Taken from 0V crossing point w/ DLL off. 3. Also defined with a maximum loading capacitance of 10pF on any pin. The loading capacitance may also need to be less for higher bit rates so the rise and fall times do not exceed the maximum 0.3UI. 4. The absolute mean skew between the Clock lane and any Data Lane in the same PHY between any edges. 5. The absolute mean skew between any Clock in one PHY and any Data lane in any other PHY between any edges. 6. Differential skew is defined as the skew between complementary outputs. It is measured as the absolute time between the two complementary edges at mean VCM point. 51 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Electrical Specifications Figure 31: Eye Diagram for Clock and Data Signals RISE 80% D A T A M A SK V d i ff 20% T x Pr e T x Po s t FALL UI/ 2 UI/ 2 V d i ff M a x V d i ff C L O C K M A SK T r i g ge r/ R efe re nce C L K JIT T ER Figure 32: Skew Within the PHY and Output Channels V C MD t C M PSK EW MT9M025_DS Rev. C Pub. 6/15 EN t C HSKEW1 PHY 52 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Power-On Reset and Standby Timing Power-On Reset and Standby Timing Power-Up Sequence The recommended power-up sequence for the MT9M025 is shown in Figure 33. The available power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have the separation specified below. 1. Turn on VDD_PLL power supply. 2. After 0-10s, turn on VAA and VAA_PIX power supply. 3. After 0-10s, turn on VDD_IO power supply. 4. After the last power supply is stable, enable EXTCLK. 5. Assert RESET_BAR for at least 1ms. 6. Wait 150000 EXTCLKs (for internal initialization into software standby. 7. Configure PLL, output, and image settings to desired values. 8. Wait 1ms for the PLL to lock. 9. Set streaming mode (R0x301a[2] = 1). Figure 33: Power Up VDD_PLL (2.8) VAA_PIX VAA (2.8) VDD_IO (1.8/2.8) VDD (1.8) t0 t1 t2 t3 VDD_SLVS (0.4) EXTCLK t4 RESET_B tx t5 Hard Reset MT9M025_DS Rev. C Pub. 6/15 EN 53 Internal Initialization t6 Software Standby PLL Lock Streaming (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Power-On Reset and Standby Timing Table 20: Power-Up Sequence Definition 3 VDD_PLL to VAA/VAA_PIX VAA/VAA_PIX to VDD_IO VDD_IO to VDD VDD to VDD_SLVS Xtal settle time Hard Reset Internal Initialization PLL Lock Time Notes: MT9M025_DS Rev. C Pub. 6/15 EN Symbol Minimum Typical Maximum Unit t0 t1 t2 t3 tx t4 t5 t6 0 0 0 0 - 12 150000 1 10 10 10 10 301 - - - - - - - - - - - s s s s ms mS EXTCLKs ms 1. Xtal settling time is component-dependent, usually taking about 10 - 100 ms. 2. Hard reset time is the minimum time required after power rails are settled. In a circuit where Hard reset is held down by RC circuit, then the RC time must include the all power rail settle time and Xtal settle time. 3. It is critical that VDD_PLL is not powered up after the other power supplies. It must be powered before or at least at the same time as the others. If the case happens that VDD_PLL is powered after other supplies then sensor may have functionality issues and will experience high current draw on this supply. 54 (c)Semiconductor Components Industries, LLC, 2015. MT9M025: 1/3-Inch CMOS Digital Image Sensor Power-On Reset and Standby Timing Power-Down Sequence The recommended power-down sequence for the MT9M025 is shown in Figure 34. The available power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have the separation specified below. 1. Disable streaming if output is active by setting standby R0x301a[2] = 0 2. The soft standby state is reached after the current row or frame, depending on configuration, has ended. 3. Turn off VDD_SLVS. 4. Turn off VDD. 5. Turn off VDD_IO 6. Turn off VAA/VAA_PIX. 7. Turn off VDD_PLL. Figure 34: Power Down VDD_SLVS (0.4) t0 VDD (1.8) t1 V DD_IO (1.8/2.8) t2 VAA_PIX VAA (2.8) t3 VDD_PLL (2.8) EXTCLK t4 Power Down until next Power up cycle Table 21: Power-Down Sequence Definition Symbol Minimum Typical Maximum Unit VDD_SLVS to VDD VDD to VDD_IO VDD_IO to VAA/VAA_PIX VAA/VAA_PIX to VDD_PLL PwrDn until Next PwrUp Time t0 t1 t2 t3 t4 0 0 0 0 100 - - - - - - - - - - s s s s ms Note: MT9M025_DS Rev. C Pub. 6/15 EN t4 is required between power down and next power up time; all decoupling caps from regulators must be completely discharged. 55 (c)Semiconductor Components Industries, LLC, 2015. 64-Ball iBGA Package Outline Drawing Figure 35: MT9M025_DS Rev. C Pub. 6/15 EN Package Dimensions 56 (c)Semiconductor Components Industries, LLC, 2015 MT9M025: 1/3-Inch CMOS Digital Image Sensor Package Dimensions All dimensions are in millimeters. Note: MT9M025: 1/3-Inch CMOS Digital Image Sensor Revision History Revision History Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6/9/15 * Updated "Ordering Information" on page 2 Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/4/15 * Updated to ON Semiconductor template * Removed Confidential marking * Updated "Ordering Information" on page 2 Rev. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. MT9M025_DS Rev. C Pub. 6/15 EN 57 (c)Semiconductor Components Industries, LLC, 2015 .