LTC3728
1
3728fg
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
Dual, 550kHz, 2-Phase
Synchronous Step-Down
Switching Regulator
The LTC
®
3728 is a dual high performance step-down
switching regulator controller that drives all N-channel
synchronous power MOSFET stages. A constant-frequency
current mode architecture allows phase-lockable frequency
of up to 550kHz. Power loss and noise due to the ESR of
the input capacitors are minimized by operating the two
controller output stages out of phase.
OPTI-LOOP compensation allows the transient response to
be optimized over a wide range of output capacitance and
ESR values. The precision 0.8V reference and power good
output indicator are compatible with future microprocessor
generations, and a wide 3.5V to 30V (36V maximum) input
supply range encompasses all battery chemistries.
A RUN/SS pin for each controller provides both soft-
start and optional timed, short-circuit shutdown. Current
foldback limits MOSFET dissipation during short-circuit
conditions when overcurrent latchoff is disabled. Output
overvoltage protection circuitry latches on the bottom
MOSFET until VOUT returns to normal. The FCB mode
pin can select among Burst Mode, constant-frequency
mode and continuous inductor current mode or regulate
a secondary winding. The LTC3728 includes a power good
output pin that indicates when both outputs are within
7.5% of their designed set point.
Figure 1. High Effi ciency Dual 5V/3.3V Step-Down Converter
n Dual, 180° Phased Controllers Reduce Required
Input Capacitance and Power Supply Induced Noise
n OPTI-LOOP
®
Compensation Minimizes COUT
n ±1% Output Voltage Accuracy
n Power Good Output Voltage Indicator
n Phase-Lockable Fixed Frequency 250kHz to 550kHz
n Dual N-Channel MOSFET Synchronous Drive
n Wide VIN Range: 3.5V to 36V Operation
n Very Low Dropout Operation: 99% Duty Cycle
n Adjustable Soft-Start Current Ramping
n Foldback Output Current Limiting
n Latched Short-Circuit Shutdown with Defeat Option
n Output Overvoltage Protection
n Remote Output Voltage Sense
n Low Shutdown IQ: 20µA
n 5V and 3.3V Regulators
n 3 Selectable Operating Modes: Constant-Frequency,
Burst Mode
®
Operation and PWM
n Available in 32-Pin 5mm × 5mm QFN and
28-Pin SSOP Packages
n Notebook and Palmtop Computers
n Telecom Systems
n Portable Instruments
n Battery-Operated Digital Devices
n DC Power Distribution Systems
+
4.7μFD3 D4
M1
CB1, 0.1μF
R2
105k
1%
1000pF
L1
3.2μH
CC1
220pF
1μF
CIN
22μF
50V
+COUT1
47μF
6V
SP
RSENSE1
0.01Ω
R1
20k
1%
RC1
15k
VOUT1
5V
5A
M2
CB2, 0.1μF
R4
63.4k
1%
L2
3.2μH
CC2
220pF
1000pF
+
COUT
56μF
6V
SP
RSENSE2
0.01Ω
R3
20k
1%
RC2
15k
VOUT2
3.3V
5A
TG1 TG2
BOOST1 BOOST2
SW1 SW2
BG1 BG2
SGND
PGND
SENSE1+SENSE2+
SENSE1–SENSE2–
VOSENSE1 VOSENSE2
ITH1 ITH2
VIN PGOOD INTVCC
RUN/SS1 RUN/SS2
VIN
5.2V TO 28V
M1, M2: FDS6982S 3728 F01
CSS1
0.1μF
CSS2
0.1μF
LTC3728
PLLIN
fIN
500kHz
L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode and OPTI-LOOP are
registered trademarks of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents including 5481178, 5929620, 6177787,
6144194, 6100678, 5408150, 6580258, 5705919.
LTC3728
2
3728fg
ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage (VIN) .........................36V to –0.3V
Topside Driver Voltages
(BOOST1, BOOST2) ............................... 42V to –0.3V
Switch Voltage (SW1, SW2) ......................... 36V to –5V
INTVCC, EXTVCC, RUN/SS1, RUN/SS2,
(BOOST1-SW1), (BOOST2-SW2), PGOOD ..... 7V to –0.3V
SENSE1+, SENSE2+, SENSE1–,
SENSE2– Voltages .........................(1.1)INTVCC to –0.3V
PLLIN, PLLFLTR, FCB Voltages ............ INTVCC to –0.3V
(Note 1)
PIN CONFIGURATION
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3728EG#PBF LTC3728EG#TRPBF LTC3728EG 28-Lead Plastic SSOP –40°C to 85°C
LTC3728IG#PBF LTC3728IG#TRPBF LTC3728IG 28-Lead Plastic SSOP –40°C to 85°C
LTC3728EUH#PBF LTC3728EUH#TRPBF 3728 32-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C
LTC3728IUH#PBF LTC3728IUH#TRPBF 3728 32-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C
LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3728EG LTC3728EG#TR LTC3728EG 28-Lead Plastic SSOP –40°C to 85°C
LTC3728IG LTC3728IG#TR LTC3728IG 28-Lead Plastic SSOP –40°C to 85°C
LTC3728EUH LTC3728EUH#TR 3728 32-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C
LTC3728IUH LTC3728IUH#TR 3728 32-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
ITH1, ITH2, VOSENSE1, VOSENSE2 Voltages ... 2.7V to –0.3V
Peak Output Current <10µs (TG1, TG2, BG1, BG2) .....3A
INTVCC Peak Output Current ................................. 50mA
Operating Temperature Range (Note 7).... –40°C to 85°C
Junction Temperature (Note 2) ............................. 125°C
Storage Temperature Range ................... –65°C to 125°C
Lead Temperature (Soldering, 10 sec)
(G Package Only) .................................................. 300°C
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD IS SGND (MUST BE SOLDERED TO PCB)
TJMAX = 125°C, θJA = 90°C/W - SINGLE LAYER BOARD
68º C/W - 4 LAYER
32
33
31 30 29 28 27 26 25
9 10 11 12 13
TOP VIEW
14 15 16
17
18
19
20
21
22
23
24
8
7
6
5
4
3
2
1VOSENSE1
PLLFLTR
PLLIN
FCB
ITH1
SGND
3.3VOUT
ITH2
BOOST1
VIN
BG1
EXTVCC
INTVCC
PGND
BG2
BOOST2
NC
SENSE1–
SENSE1+
NC
RUN/SS1
PGOOD
TG1
SW1
VOSENSE2
NC
SENSE2–
SENSE2+
RUN/SS2
TG2
SW2
NC
UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
G PACKAGE
28-LEAD PLASTIC SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RUN/SS1
SENSE1+
SENSE1–
VOSENSE1
PLLFLTR
PLLIN
FCB
ITH1
SGND
3.3VOUT
ITH2
VOSENSE2
SENSE2–
SENSE2+
PGOOD
TG1
SW1
BOOST1
VIN
BG1
EXTVCC
INTVCC
PGND
BG2
BOOST2
SW2
TG2
RUN/SS2
LTC3728
3
3728fg
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loops
VOSENSE1, 2 Regulated Feedback Voltage (Note 3); ITH1, 2 Voltage = 1.2V l0.792 0.800 0.808 V
IOSENSE1, 2 Feedback Current (Note 3) –5 –50 nA
VREFLNREG Reference Voltage Line Regulation VIN = 3.6V to 30V (Note 3) 0.002 0.02 %/V
VLOADREG Output Voltage Load Regulation (Note 3)
Measured in Servo Loop; ∆ITH Voltage = 1.2V to 0.7V
Measured in Servo Loop; ∆ITH Voltage = 1.2V to 2.0V
l
l
0.1
–0.1
0.5
–0.5
%
%
gm1, 2 Transconductance Amplifi er gmITH1, 2 = 1.2V; Sink/Source 5µA (Note 3) 1.3 mmho
gmGBW1, 2 Transconductance Amplifi er GBW ITH1, 2 = 1.2V (Note 3) 3 MHzIQ
Input DC Supply Current
Normal Mode
Shutdown
(Note 4)
VIN = 15V; EXTVCC Tied to VOUT1; VOUT1 = 5V
VRUN/SS1, 2 = 0V
450
20 35
µA
µA
VFCB Forced Continuous Threshold l0.76 0.800 0.84 V
IFCB Forced Continuous Pin Current VFCB = 0.85V –0.50 –0.18 –0.1 µA
VBINHIBIT Burst Inhibit (Constant-Frequency)
Threshold
Measured at FCB Pin 4.3 4.8 V
UVLO Undervoltage Lockout VIN Ramping Down l3.5 4 V
VOVL Feedback Overvoltage Lockout Measured at VOSENSE1, 2 l0.84 0.86 0.88 V
ISENSE Sense Pins Total Source Current (Each Channel); VSENSE1–, 2– = VSENSE1+, 2+ = 0V –85 –60 µA
DFMAX Maximum Duty Factor In Dropout 98 99.4 %
IRUN/SS1, 2 Soft-Start Charge Current VRUN/SS1, 2 = 1.9V 0.5 1.2 µA
VRUN/SS1, 2 ON RUN/SS Pin ON Threshold VRUN/SS1, VRUN/SS2 Rising 1.0 1.5 1.9 V
VRUN/SS1, 2 LT RUN/SS Pin Latchoff Arming
Threshold
VRUN/SS1, VRUN/SS2 Rising from 3V 3.8 4.5 V
ISCL1, 2 RUN/SS Discharge Current Soft-Short Condition VOSENSE1, 2 = 0.5V;
VRUN/SS1, 2 = 4.5V
0.5 2 4 µA
ISDLHO Shutdown Latch Disable Current VOSENSE1, 2 = 0.5V 1.6 5 µA
VSENSE(MAX) Maximum Current Sense Threshold VOSENSE1, 2 = 0.7V, VOSENSE1–, 2– = 5V
VOSENSE1, 2 = 0.7V, VOSENSE1–, 2– = 5V l
65
62
75
75
85
88
mV
mV
TG1, 2 tr
TG1, 2 tf
TG Transition Time:
Rise Time
Fall Time
(Note 5)
CLOAD = 3300pF
CLOAD = 3300pF
50
50
90
90
ns
ns
BG1, 2 tr
BG1, 2 tf
BG Transition Time:
Rise Time
Fall Time
(Note 5)
CLOAD = 3300pF
CLOAD = 3300pF
40
40
90
80
ns
ns
TG/BG t1D Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time CLOAD = 3300pF Each Driver 90 ns
BG/TG t2D Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time CLOAD = 3300pF Each Driver 90 ns
tON(MIN) Minimum On-Time Tested with a Square Wave (Note 6) 100 ns
INTVCC Linear Regulator
VINTVCC Internal VCC Voltage 6V < VIN < 30V, VEXTVCC = 4V 48 5.0 5.2 V
VLDOINT INTVCC Load Regulation ICC = 0 to 20mA, VEXTVCC = 4V 0.2 1.0 %
VLDOEXT EXTVCC Voltage Drop ICC = 20mA, VEXTVCC = 5V 80 160 mV
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted.
LTC3728
4
3728fg
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formulas:
LTC3728: TJ = TA + (PD • 95 °C/W)
Note 3: The LTC3728 is tested in a feedback loop that servos VITH1, 2 to a
specifi ed voltage and measures the resultant VOSENSE1, 2.
Note 4: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VEXTVCC EXTVCC Switchover Voltage ICC = 20mA, EXTVCC Ramping Positive l4.5 4.7 V
VLDOHYS EXTVCC Hysteresis 0.2 V
Oscillator and Phase-Locked Loop
fNOM Nominal Frequency VPLLFLTR = 1.2V 360 400 440 kHz
fLOW Lowest Frequency VPLLFLTR = 0V 230 260 290 kHz
fHIGH Highest Frequency VPLLFLTR ≥ 2.4V 480 550 590 kHz
RPLLIN PLLIN Input Resistance 50 k
IPLLFLTR Phase Detector Output Current
Sinking Capability
Sourcing Capability
fPLLIN < fOSC
fPLLIN > fOSC
–15
15
µA
µA
3.3V Linear Regulator
V3.3OUT 3.3V Regulator Output Voltage No Load l3.25 3.35 3.45 V
V3.3IL 3.3V Regulator Load Regulation I3.3 = 0 to 10mA 0.5 2 %
V3.3VL 3.3V Regulator Line Regulation 6V < VIN < 30V 0.05 0.2 %
I3.3LEAK Leakage Current of 3.3V Regulator in
Shutdown
VRUN/SS1, 2 = 0V, VIN = 25V 10 50 µA
PGOOD Output
VPGL PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V
IPGOOD PGOOD Leakage Current VPGOOD = 5V ±1 µA
VPG PGOOD Trip Level, Either Controller VOSENSE with Respect to Set Output Voltage
VOSENSE Ramping Negative
VOSENSE Ramping Positive
–6
6
–7.5
7.5
–9.5
9.5
%
%
Note 5: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 6: The IC minimum on-time is tested under an ideal condition
without external power FETs. It can be different when the IC is working in
an actual circuit. See Minimum On-Time Considerations in the Application
Information section.
Note 7: The LTC3728E is guaranteed to meet performance specifi cations
from 0°C to 85°C. Specifi cations over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3728I is guaranteed to meet
performance specifi cations over the full –40°C to 85°C operating
temperature range.
LTC3728
5
3728fg
TYPICAL PERFORMANCE CHARACTERISTICS
Effi ciency vs Output Current and
Mode (Figure 13)
Effi ciency vs Output Current
(Figure 13)
Effi ciency vs Input Voltage
(Figure 13)
Supply Current vs Input Voltage
and Mode (Figure 13) EXTVCC Voltage Drop
INTVCC and EXTVCC Switch
Voltage vs Temperature
Internal 5V LDO Line Regulation
Maximum Current Sense
Threshold vs Duty Factor
Maximum Current Sense
Threshold vs Percent of Nominal
Output Voltage (Foldback)
OUTPUT CURRENT (A)
0.001
0
EFFICIENCY (%)
10
30
40
50
100
70
0.01 0.1 1
3728 G01
20
80
90
60
10
FORCED
CONTINUOUS
MODE (PWM)
CONSTANT
FREQUENCY
(BURST DISABLE)
Burst Mode
OPERATION
VIN = 15V
VOUT = 5V
f = 250kHz
OUTPUT CURRENT (A)
0.001
EFFICIENCY (%)
70
80
10
3728 G02
60
50 0.01 0.1 1
100
90
VIN = 10V
VIN = 15V
VIN = 7V
VIN = 20V
VOUT = 5V
f = 250kHz
INPUT VOLTAGE (V)
5
EFFICIENCY (%)
70
80
3728 G03
60
50 15 25 35
100
VOUT = 5V
IOUT = 3A
f = 250kHz
90
INPUT VOLTAGE (V)
05
0
SUPPLY CURRENT (μA)
400
1000
10 20 25
3728 G04
200
800
600
15 30 35
BOTH
CONTROLLERS ON
SHUTDOWN
CURRENT (mA)
0
EXTVCC VOLTAGE DROP (mV)
150
200
250
40
3728 G05
100
50
010 20 30 50
TEMPERATURE (°C)
–50
INTVCC AND EXTVCC SWITCH VOLTAGE (V)
4.95
5.00
5.05
25 75
3728 G06
4.90
4.85
–25 0 50 100 125
4.80
4.70
4.75
INTVCC VOLTAGE
EXTVCC SWITCHOVER THRESHOLD
INPUT VOLTAGE (V)
0
4.8
4.9
5.1
15 25
3728 G07
4.7
4.6
510 20 30 35
4.5
4.4
5.0
INTVCC VOLTAGE (V)
ILOAD = 1mA
DUTY FACTOR (%)
0
0
VSENSE (mV)
25
50
75
20 40 60 80
3728 G08
100
PERCENT ON NOMINAL OUTPUT VOLTAGE (%)
0
VSENSE (mV)
40
50
60
100
3728 G09
30
20
025 50 75
10
80
70
LTC3728
6
3728fg
TYPICAL PERFORMANCE CHARACTERISTICS
Maximum Current Sense Threshold
vs VRUN/SS (Soft-Start)
Maximum Current Sense Threshold
vs Sense Common Mode Voltage
Current Sense Threshold
vs ITH Voltage
Load Regulation VITH vs VRUN/SS SENSE Pins Total Source Current
Maximum Current Sense
Threshold vs Temperature
Dropout Voltage vs Output Current
(Figure 14) RUN/SS Current vs Temperature
VRUN/SS (V)
0
0
VSENSE (mV)
20
40
60
80
1234
3728 G10
56
VSENSE(CM) = 1.6V
COMMON MODE VOLTAGE (V)
0
VSENSE (mV)
72
76
80
4
3728 G11
68
64
60 1235
VITH (V)
0
VSENSE (mV)
30
50
70
90
2
3728 G12
10
–10
20
40
60
80
0
–20
–30 0.5 11.5 2.5
LOAD CURRENT (A)
0
NORMALIZED VOUT (%)
–0.2
–0.1
4
3728 G13
–0.3
–0.4 1235
0.0 FCB = 0V
VIN = 15V
VRUN/SS (V)
0
0
VITH (V)
0.5
1.0
1.5
2.0
2.5
1234
3728 G14
56
VOSENSE = 0.7V
VSENSE COMMON MODE VOLTAGE (V)
0
ISENSE (μA)
0
3728 G15
–50
–100 24
50
100
6
TEMPERATURE (°C)
–50 –25
70
VSENSE (mV)
74
80
050 75
3728 G17
72
78
76
25 100 125
OUTPUT CURRENT (A)
0
0
DROPOUT VOLTAGE (V)
1
2
3
4
0.5 1.0 1.5 2.0
3728 G18
2.5 3.0 3.5 4.0
RSENSE = 0.015Ω
RSENSE = 0.010Ω
VOUT = 5V
TEMPERATURE (°C)
–50 –25
0
RUN/SS CURRENT (μA)
0.2
0.6
0.8
1.0
75 10050
1.8
3728 G25
0.4
0 25 125
1.2
1.4
1.6
LTC3728
7
3728fg
TYPICAL PERFORMANCE CHARACTERISTICS
Soft-Start Up (Figure 13) Load Step (Figure 13) Load Step (Figure 13)
Input Source/Capacitor
Instantaneous Current (Figure 13) Burst Mode Operation (Figure 13)
Constant-Frequency (Burst
Inhibit) Operation (Figure 13)
Current Sense Pin Input Current
vs Temperature
EXTVCC Switch Resistance
vs Temperature
Oscillator Frequency
vs Temperature
TEMPERATURE (°C)
–50 –25
25
CURRENT SENSE INPUT CURRENT (μA)
29
35
050 75
3728 G26
27
33
31
25 100 125
VOUT = 5V
TEMPERATURE (°C)
–50 –25
0
EXTVCC SWITCH RESISTANCE (Ω)
4
10
050 75
3728 G27
2
8
6
25 100 125
TEMPERATURE (°C)
–50
400
500
700
25 75
3728 G28
300
200
–25 0 50 100 125
100
0
600
FREQUENCY (kHz)
VPLLFLTR = 5V
VPLLFLTR = 1.2V
VPLLFLTR = 0V
VIN = 15V
VOUT = 5V
5ms/DIV 3728 G19
VRUN/SS
5V/DIV
VOUT
5V/DIV
IL
2A/DIV
VIN = 15V
VOUT = 5V
VPLLFLTR = 0V
LOAD STEP = 0A to 3A
Burst Mode OPERATION
20µs/DIV 3728 G20
VOUT
200mV/DIV
IL
2A/DIV
VIN = 15V
VOUT = 5V
VPLLFLTR = 0V
LOAD STEP = 0A to 3A
CONTINUOUS OPERATION
20µs/DIV 3728 G21
VOUT
200mV/DIV
IL
2A/DIV
VIN = 15V
VOUT = 5V
VPLLFLTR = 0V
IOUT = IOUT3.3A = 2A
1µs/DIV 3728 G22
VSW1
10V/DIV
VSW2
10V/DIV
IIN
2A/DIV
VIN
200mV/DIV
VIN = 15V
VOUT = 5V
VPLLFLTR = 0V
VFCB = OPEN
IOUT = 20mA
10µs/DIV 3728 G23
VOUT
20mV/DIV
IL
0.5A/DIV
VIN = 15V
VOUT = 5V
VPLLFLTR = 0V
VFCB = 5V
IOUT = 20mA
2µs/DIV 3728 G24
VOUT
20mV/DIV
IL
0.5A/DIV
LTC3728
8
3728fg
RUN/SS1, RUN/SS2 (Pins 1, 15/Pins 28, 13): Combination
of soft-start, run control inputs and short-circuit detection
timers. A capacitor to ground at each of these pins sets the
ramp time to full output current. Forcing either of these pins
back below 1.0V causes the IC to shut down the circuitry
required for that particular controller. Latchoff overcurrent
protection is also invoked via this pin as described in the
Applications Information section.
SENSE1+, SENSE2+ (Pins 2, 14/Pins 30, 12): The (+)
Input to the Differential Current Comparators. The ITH pin
voltage and controlled offsets between the SENSE– and
SENSE+ pins in conjunction with RSENSE set the current
trip threshold.
SENSE1–, SENSE2– (Pins 3, 13/Pins 31, 11): The (–)
Input to the Differential Current Comparators.
VOSENSE1, VOSENSE2 (Pins 4, 12/Pins 1, 9): Receives the
remotely-sensed feedback voltage for each controller from
an external resistive divider across the output.
PLLFLTR (Pin 5/Pin 2): The Phase-Locked Loop’s Lowpass
Filter is Tied to This Pin. Alternatively, this pin can be driven
with an AC or DC voltage source to vary the frequency of
the internal oscillator.
PLLIN (Pin 6/Pin 3): External Synchronization Input to
Phase Detector. This pin is internally terminated to SGND
with 50k. The phase-locked loop will force the rising
top gate signal of controller 1 to be synchronized with
the rising edge of the PLLIN signal.
FCB (Pin 7/Pin 4): Forced Continuous Control Input.
This input acts on both controllers and is normally used
to regulate a secondary winding. Pulling this pin below
0.8V will force continuous synchronous operation.
ITH1, ITH2 (Pins 8, 11/Pins 5, 8): Error Amplifi er Output
and Switching Regulator Compensation Point. Each as-
sociated channels’ current comparator trip point increases
with this control voltage.
SGND (Pin 9/Pin 6): Small Signal Ground common to
both controllers, must be routed separately from high
current grounds to the common (–) terminals of the
COUT capacitors.
3.3VOUT (Pin 10/Pin 7): Output of a linear regulator ca-
pable of supplying 10mA DC with peak currents as high
as 50mA.
NC (Pins 10, 16, 29, 32 UH Package Only): No Connect.
PGND (Pin 20/Pin 19): Driver Power Ground. Connects to
the sources of bottom (synchronous) N-channel MOSFETs,
anodes of the Schottky rectifi ers and the (–) terminal(s)
of CIN.
G Package/UH Package
TYPICAL PERFORMANCE CHARACTERISTICS
Undervoltage Lockout
vs Temperature
Shutdown Latch Thresholds
vs Temperature
TEMPERATURE (°C)
–50
UNDERVOLTAGE LOCKOUT (V)
3.40
3.45
3.50
25 75
3728 G29
3.35
3.30
–25 0 50 100 125
3.25
3.20
TEMPERATURE (°C)
–50 –25
0
SHUTDOWN LATCH THRESHOLDS (V)
0.5
1.5
2.0
2.5
75 10050
4.5
3728 G30
1.0
0 25 125
3.0
3.5
4.0 LATCH ARMING
LATCHOFF
THRESHOLD
PIN FUNCTIONS
LTC3728
9
3728fg
PIN FUNCTIONS
INTVCC (Pin 21/Pin 20): Output of the Internal 5V Linear
Low Dropout Regulator and the EXTVCC Switch. The driver
and control circuits are powered from this voltage source.
Must be decoupled to power ground with a minimum of
4.7µF tantalum or other low ESR capacitor.
EXTVCC (Pin 22/Pin 21): External Power Input to an
Internal Switch Connected to INTVCC. This switch closes
and supplies VCC power, bypassing the internal low drop-
out regulator, whenever EXTVCC is higher than 4.7V. See
EXTVCC connection in Applications section. Do not exceed
7V on this pin.
BG1, BG2 (Pins 23, 19/Pins 22, 18): High Current Gate
Drives for Bottom (Synchronous) N-Channel MOSFETs.
Voltage swing at these pins is from ground to INTVCC.
VIN (Pin 24/Pin 23): Main Supply Pin. A bypass capaci-
tor should be tied between this pin and the signal ground
pin.
BOOST1, BOOST2 (Pins 25, 18/Pins 24, 17): Bootstrapped
Supplies to the Topside Floating Drivers. Capacitors
are connected between the boost and switch pins and
Schottky diodes are tied between the boost and INTVCC
pins. Voltage swing at the boost pins is from INTVCC to
(VIN + INTVCC).
SW1, SW2 (Pins 26, 17/Pins 25, 15): Switch Node
Connections to Inductors. Voltage swing at these pins
is from a Schottky diode (external) voltage drop below
ground to VIN.
TG1, TG2 (Pins 27, 16/Pins 26, 14): High Current Gate
Drives for Top N-Channel MOSFETs. These are the out-
puts of fl oating drivers with a voltage swing equal to
INTVCC – 0.5V superimposed on the switch node voltage
SW.
PGOOD (Pin 28/Pin 27): Open-Drain Logic Output. PGOOD
is pulled to ground when the voltage on either VOSENSE
pin is not within ±7.5% of its set point.
Exposed Pad (Pin 33) SGND: The Exposed Pad must be
soldered to PCB ground for electrical contact and rated
thermal performance.
LTC3728
10
3728fg
FUNCTIONAL DIAGRAM
SWITCH
LOGIC
–
+
0.8V
4.7V
5V
VIN
VIN
4.5V BINH
CLK2
CLK1
0.18μA
R6
R5
+
–
FCB
+
–
–
+
–
+
–
+
VREF
INTERNAL
SUPPLY
3.3VOUT
VSEC
RLP
CLP
1.5V
FCB
EXTVCC
INTVCC
SGND
+
5V
LDO
REG
SW
SHDN
0.55V
TOP
BOOST
TG CB
CIN
D1
DB
PGND
BOT BG
INTVCC
INTVCC
VIN
+
CSEC
COUT
VOUT
3728 FD/F02
DSEC
RSENSE
R2
+
+
VOSENSE
DROP
OUT
DET
RUN
SOFT
START
BOT
TOP ON
S
R
Q
Q
OSCILLATOR
PHASE DET
PLLFLTR
PLLIN
FCB
EA
0.86V
0.80V
OV
VFB
1.2μA
6V
R1
–
+
RC
4(VFB)
RST
SHDN
RUN/SS
ITH CC
CC2
CSS
4(VFB)
0.86V
SLOPE
COMP
3mV
+
–
–
+
SENSE–
SENSE+
INTVCC
30k
45k
2.4V
45k
30k
I1 I2
B
DUPLICATE FOR SECOND
CONTROLLER CHANNEL
+– –+
50k
FIN
+
–
+
–
+
–
+
–
PGOOD VOSENSE1
VOSENSE2
0.86V
0.74V
0.86V
0.74V
Figure 2
LTC3728
11
3728fg
OPERATION
Main Control Loop
The LTC3728 uses a constant-frequency, current mode
step-down architecture with the two controller channels
operating 180 degrees out of phase. During normal opera-
tion, each top MOSFET is turned on when the clock for
that channel sets the RS latch, and turned off when the
main current comparator, I1, resets the RS latch. The peak
inductor current at which I1 resets the RS latch is controlled
by the voltage on the ITH pin, which is the output of each
error amplifi er EA. The VOSENSE pin receives the voltage
feedback signal, which is compared to the internal refer-
ence voltage by the EA. When the load current increases,
it causes a slight decrease in VOSENSE relative to the 0.8V
reference, which in turn causes the ITH voltage to increase
until the average inductor current matches the new load
current. After the top MOSFET has turned off, the bottom
MOSFET is turned on until either the inductor current
starts to reverse, as indicated by current comparator I2,
or the beginning of the next cycle.
The top MOSFET drivers are biased from fl oating bootstrap
capacitor CB, which normally is recharged during each off
cycle through an external diode when the top MOSFET
turns off. As VIN decreases to a voltage close to VOUT
, the
loop may enter dropout and attempt to turn on the top
MOSFET continuously. The dropout detector detects this
and forces the top MOSFET off for about 400ns every tenth
cycle to allow CB to recharge.
The main control loop is shut down by pulling the RUN/
SS pin low. Releasing RUN/SS allows an internal 1.2µA
current source to charge soft-start capacitor CSS. When
CSS reaches 1.5V, the main control loop is enabled with
the ITH voltage clamped at approximately 30% of its
maximum value. As CSS continues to charge, the ITH
pin voltage is gradually released allowing normal, full-
current operation. When both RUN/SS1 and RUN/SS2
are low, all LTC3728 controller functions are shut down,
including the 5V and 3.3V regulators.
Low Current Operation
The FCB pin is a multifunction pin providing two func-
tions: 1) to provide regulation for a secondary winding
by temporarily forcing continuous PWM operation on
both controllers; and 2) select between
two
modes of
low current operation. When the FCB pin voltage is below
0.8V, the controller forces continuous PWM current mode
operation. In this mode, the top and bottom MOSFETs
are alternately turned on to maintain the output voltage
independent of direction of inductor current. When the
FCB pin is below VINTVCC – 1V but greater than 0.8V,
the controller enters Burst Mode operation. Burst Mode
operation sets a minimum output current level before
inhibiting the top switch and turns off the synchronous
MOSFET(s) when the inductor current goes negative. This
combination of requirements will, at low currents, force
the ITH pin below a voltage threshold that will temporarily
inhibit turn-on of both output MOSFETs until the output
voltage drops. There is 60mV of hysteresis in the burst
comparator B tied to the ITH pin. This hysteresis produces
output signals to the MOSFETs that turn them on for several
cycles, followed by a variable “sleep” interval depending
upon the load current. The resultant output voltage ripple
is held to a very small value by having the hysteretic
comparator after the error amplifi er gain block.
Frequency Synchronization
The phase-locked loop allows the internal oscillator to
be synchronized to an external source via the PLLIN pin.
The output of the phase detector at the PLLFLTR pin is
also the DC frequency control input of the oscillator that
operates over a 250kHz to 550kHz range corresponding
to a DC voltage input from 0V to 2.4V. When locked, the
PLL aligns the turn on of the top MOSFET to the rising
edge of the synchronizing signal. When PLLIN is left
open, the PLLFLTR pin goes low, forcing the oscillator to
minimum frequency.
Constant-Frequency Operation
When the FCB pin is tied to INTVCC, Burst Mode opera-
tion is disabled and the forced minimum output current
requirement is removed. This provides constant-frequency,
discontinuous (preventing reverse inductor current)
current operation over the widest possible output current
range. This constant-frequency operation is not as effi cient
as Burst Mode operation, but does provide a lower noise,
constant-frequency operating mode down to approximately
1% of designed maximum output current.
(Refer to Functional Diagram)
LTC3728
12
3728fg
OPERATION
Continuous Current (PWM) Operation
Tying the FCB pin to ground will force continuous current
operation. This is the least effi cient operating mode, but
may be desirable in certain applications. The output can
source or sink current in this mode. When sinking current
while in forced continuous operation, current will be forced
back into the main power supply.
INTVCC/EXTVCC Power
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTVCC
pin. When
the EXTVCC pin is left open, an internal 5V low dropout
linear regulator supplies INTVCC power. If EXTVCC is taken
above 4.7V, the 5V regulator is turned off and an internal
switch is turned on connecting EXTVCC to INTVCC. This al-
lows the INTVCC power to be derived from a high effi ciency
external source such as the output of the regulator itself
or a secondary winding, as described in the Applications
Information section.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (>7.5%) as well as other more serious condi-
tions that may overvoltage the output. In this case, the top
MOSFET is turned off and the bottom MOSFET is turned
on until the overvoltage condition is cleared.
Power Good (PGOOD) Pin
The PGOOD pin is connected to an open drain of an internal
MOSFET. The MOSFET turns on and pulls the pin low when
either output is not within ±7.5% of the nominal output
level as determined by the resistive feedback divider. When
both outputs meet the ±7.5% requirement, the MOSFET is
turned off within 10µs and the pin is allowed to be pulled
up by an external resistor to a source of up to 7V.
Foldback Current, Short-Circuit Detection
and Short-Circuit Latchoff
The RUN/SS capacitors are used initially to limit the inrush
current of each switching regulator. After the controller
has been started and been given adequate time to charge
up the output capacitors and provide full load current, the
RUN/SS capacitor is used in a short-circuit time-out circuit.
If the output voltage falls to less than 70% of its nominal
output voltage, the RUN/SS capacitor begins discharging
on the assumption that the output is in an overcurrent
and/or short-circuit condition. If the condition lasts for
a long enough period as determined by the size of the
RUN/SS capacitor, the controller will be shut down until
the RUN/SS pin(s) voltage(s) are recycled. This built-in
latchoff can be overridden by providing a >5µA pull-up
at a compliance of 5V to the RUN/SS pin(s). This current
shortens the soft start period but also prevents net dis-
charge of the RUN/SS capacitor(s) during an overcurrent
and/or short-circuit condition. Foldback current limiting
is also activated when the output voltage falls below
70% of its nominal level whether or not the short-circuit
latchoff circuit is enabled. Even if a short is present and
the short-circuit latchoff is not enabled, a safe, low output
current is provided due to internal current foldback and
actual power wasted is low due to the effi cient nature of
the current mode switching regulator.
THEORY AND BENEFITS OF 2-PHASE OPERATION
The LTC1628 and the LTC3728 dual high effi ciency DC/DC
controllers bring the considerable benefi ts of 2-phase op-
eration to portable applications for the fi rst time. Notebook
computers, PDAs, handheld terminals and automotive
electronics will all benefi t from the lower input fi lter-
ing requirement, reduced electromagnetic interference
(EMI) and increased effi ciency associated with 2-phase
operation.
(Refer to Functional Diagram)
LTC3728
13
3728fg
OPERATION
Figure 3. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for Dual Switching Regulators
Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripple with the LTC1628 2-Phase Regulator Allows
Less Expensive Input Capacitors, Reduces Shielding Requirements for EMI and Improves Effi ciency
IIN(MEAS) = 1.55ARMS
IIN(MEAS) = 2.53ARMS 3728 F03b3728 F03a
3.3V SWITCH
20V/DIV
5V SWITCH
20V/DIV
INPUT CURRENT
5A/DIV
INPUT VOLTAGE
500mV/DIV
(a) (b)
Why the need for 2-phase operation? Up until the 2-
phase family, constant-frequency dual switching regula-
tors operated both channels in phase (i.e., single-phase
operation). This means that both switches turned on at
the same time, causing current pulses of up to twice the
amplitude of those for one regulator to be drawn from the
input capacitor and battery. These large amplitude current
pulses increased the total RMS current fl owing from the
input capacitor, requiring the use of more expensive input
capacitors and increasing both EMI and losses in the input
capacitor and battery.
With 2-phase operation, the two channels of the dual-
switching regulator are operated 180 degrees out of phase.
This effectively interleaves the current pulses drawn by the
switches, greatly reducing the overlap time where they add
together.
The result is a signifi cant reduction in total RMS
input current, which in turn allows less expen
sive input
capacitors to be used, reduces shielding requirements for
EMI and improves real world operating effi ciency.
Figure 3 compares the input waveforms for a representa-
tive single-phase dual switching regulator to the LTC1628
2-phase dual switching regulator. An actual measurement
of the RMS input current under these conditions shows
that 2-phase operation dropped the input current from
2.53ARMS to 1.55ARMS. While this is an impressive
reduction in itself, remember that the power losses are
proportional to IRMS2, meaning that the actual power wasted
is reduced by a factor of 2.66. The reduced input ripple
voltage also means less power is lost in the input power
path, which could include batteries, switches, trace/con-
nector resistances and protection circuitry. Improvements
in both conducted and radiated EMI also directly accrue as
a result of the reduced RMS input current and voltage.
Of course, the improvement afforded by 2-phase opera-
tion is a function of the dual switching regulator’s relative
duty cycles which, in turn, are dependent upon the input
voltage VIN (Duty Cycle = VOUT/VIN). Figure 4 shows how
the RMS input current varies for single-phase and 2-phase
operation for 3.3V and 5V regulators over a wide input
voltage range.
It can readily be seen that the advantages of 2-phase opera-
tion are not just limited to a narrow operating range, but
in fact extend over a wide region. A good rule of thumb
for most applications is that 2-phase operation will reduce
the input capacitor requirement to that for just one channel
operating at maximum current and 50% duty cycle.
(Refer to Functional Diagram)
LTC3728
14
3728fg
OPERATION
A fi nal question: If 2-phase operation offers such an ad-
vantage over single-phase operation for dual switching
regulators, why hasn’t it been done before? The answer
is that, while simple in concept, it is hard to implement.
Constant-frequency current mode switching regulators
require an oscillator derived slope compensation signal
to allow stable operation of each regulator at over 50%
duty cycle. This signal is relatively easy to derive in
single-phase dual switching regulators, but required the
development of a new and proprietary technique to allow
2-phase operation. In addition, isolation between the two
channels becomes more critical with 2-phase operation
because switch transitions in one channel could potentially
disrupt the operation of the other channel.
These 2-phase parts are proof that these hurdles have
been surmounted. They offer unique advantages for the
ever-expanding number of high effi ciency power supplies
required in portable electronics.
INPUT VOLTAGE (V)
0
INPUT RMS CURRENT (A)
3.0
2.5
2.0
1.5
1.0
0.5
010 20 30 40
3728 F04
SINGLE PHASE
DUAL CONTROLLER
2-PHASE
DUAL CONTROLLER
VO1 = 5V/3A
VO2 = 3.3V/3A
Figure 4. RMS Input Current Comparison
(Refer to Functional Diagram)
LTC3728
15
3728fg
Figure 1 on the fi rst page is a basic LTC3728 application
circuit. External component selection is driven by the
load requirement, and begins with the selection of RSENSE
and the inductor value. Next, the power MOSFETs and
D1 are selected. Finally, CIN and COUT are selected. The
circuit shown in Figure 1 can be confi gured for operation
up to an input voltage of 28V (limited by the external
MOSFETs).
RSENSE Selection for Output Current
RSENSE is chosen based on the required output current. The
LTC3728 current comparator has a maximum threshold
of 75mV/RSENSE and an input common mode range of
SGND to 1.1(INTVCC). The current comparator threshold
sets the peak of the inductor current, yielding a maximum
average output current IMAX equal to the peak value less
half the peak-to-peak ripple current, ∆IL.
Allowing a margin for variations in the LTC3728 and external
component values yields:
RSENSE =50mV
IMAX
Because of possible PCB noise in the current sensing loop,
the AC current sensing ripple of ∆VSENSE = ∆I • RSENSE
also needs to be checked in the design to get good sig-
nal-to-noise ratio. In general, for a reasonable good PCB
layout, a 15mV ∆VSENSE voltage is recommended as a
conservative number to start with.
When using the controller in very low dropout conditions,
the maximum output current level will be reduced due to the
internal compensation required to meet stability criterion
for buck regulators operating at greater than 50% duty
factor. A curve is provided to estimate this reduction in
peak output current level depending upon the operating
duty factor.
Operating Frequency
The LTC3728 uses a constant-frequency, phase-lockable
architecture with the frequency determined by an internal
capacitor. This capacitor is charged by a fi xed current plus
an additional current which is proportional to the voltage
applied to the PLLFLTR pin. Refer to Phase-Locked Loop
APPLICATIONS INFORMATION
and Frequency Synchronization in the Applications Infor-
mation section for additional information.
A graph for the voltage applied to the PLLFLTR pin vs
frequency is given in Figure 5. As the operating frequency
is increased the gate charge losses will be higher, reducing
effi ciency (see Effi ciency Considerations). The maximum
switching frequency is approximately 550kHz.
Inductor Value Calculation
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is effi ciency. A higher
frequency generally results in lower effi ciency because
of MOSFET gate charge losses. In addition to this basic
trade-off, the effect of inductor value on ripple current and
low current operation must also be considered.
The inductor value has a direct effect on ripple current.
The inductor ripple current ∆IL decreases with higher
inductance or frequency and increases with higher VIN:
IL=1
(f)(L)VOUT 1– VOUT
VIN
Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆IL=0.3(IMAX) or higher for good
Figure 5. PPLFLTR Pin Voltage vs Frequency
OPERATING FREQUENCY (kHz)
200 250 300 350 550400 450 500
PLLFLTR PIN VOLTAGE (V)
3728 F05
2.5
2.0
1.5
1.0
0.5
0
LTC3728
16
3728fg
load transient response and suffi cient ripple current sig-
nal in the current loop. The maximum ∆IL occurs at the
maximum input voltage.
The inductor value also has secondary effects. The tran-
sition to Burst Mode operation begins when the average
inductor current required results in a peak current below
25% of the current limit determined by RSENSE. Lower
inductor values (higher ∆IL) will cause this to occur at
lower load currents, which can cause a dip in effi ciency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High effi ciency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy,
or Kool Mµ
®
cores. Actual core loss is independent of core
size for a fi xed inductor value, but it is very dependent
on inductance selected. As inductance increases, core
losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates hard, which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive
than ferrite. A reasonable compromise from the same
manufacturer is Kool Mµ. Toroids are very space effi cient,
especially when you can use several layers of wire. Because
they generally lack a bobbin, mounting is more diffi cult.
However, designs for surface mount are available that do
not increase the height signifi cantly.
APPLICATIONS INFORMATION
Power MOSFET and D1 Selection
Two external power MOSFETs must be selected for each
controller in the LTC3728: One N-channel MOSFET for
the top (main) switch, and one N-channel MOSFET for
the bottom (synchronous) switch.
The peak-to-peak drive levels are set by the INTVCC
voltage. This voltage is typically 5V during start-up
(see EXTVCC Pin Connection). Consequently, logic-level
threshold MOSFETs must be used in most applications.
The only exception is if low input voltage is expected
(VIN < 5V); then, sublogic level threshold MOSFETs (VGS(TH)
< 3V) should be used. Pay close attention to the BVDSS
specifi cation for the MOSFETs as well; most of the logic
level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the
on-resistance RDS(ON), reverse-transfer capacitance CRSS,
input voltage and maximum output current. When the
LTC3728 is operating in continuous mode the duty cycles
for the top and bottom MOSFETs are given by:
Main Switch Duty Cycle =VOUT
VIN
Synchronous Switch Duty Cycle =VIN –V
OUT
VIN
The MOSFET power dissipations at maximum output
current are given by:
P
MAIN =VOUT
VIN
IMAX
()
21+
()
RDS(ON) +
kV
IN
()
2IMAX
()
CRSS
()
f
()
PSYNC =VIN –V
OUT
VIN
IMAX
()
21+
()
RDS(ON)
where δ is the temperature dependency of RDS(ON) and k
is a constant inversely related to the gate drive current.
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
LTC3728
17
3728fg
APPLICATIONS INFORMATION
which are highest at high input voltages. For VIN < 20V
the high current effi ciency generally improves with larger
MOSFETs, while for VIN > 20V the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CRSS actually provides higher effi ciency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs. CRSS is usually specifi ed in the MOSFET
characteristics. The constant k = 1.7 can be used to esti-
mate the contributions of the two terms in the main switch
dissipation equation.
The Schottky diode D1 shown in Figure 1 conducts dur-
ing the dead time between the conduction of the two
power MOSFETs. This prevents the body diode of the
bottom MOSFET from turning on, storing charge during
the dead time and requiring a reverse recovery period
that could cost as much as 3% in effi ciency at high VIN.
A 1A to 3A Schottky is generally a good compromise for
both regions of operation due to the relatively small aver-
age current. Larger diodes result in additional transition
losses due to their larger junction capacitance. Schottky
diodes should be placed in parallel with the synchronous
MOSFETs when operating in pulse-skip mode or in Burst
Mode operation.
CIN and COUT Selection
The selection of CIN is simplifi ed by the multiphase ar-
chitecture and its impact on the worst-case RMS current
drawn through the input network (battery/fuse/capacitor).
It can be shown that the worst case RMS current occurs
when only one controller is operating. The controller with
the highest (VOUT)(IOUT) product needs to be used in the
formula below to determine the maximum RMS current
requirement. Increasing the output current, drawn from
the other out-of-phase controller, will actually decrease the
input RMS ripple current from this maximum value (see
Figure 4). The out-of-phase technique typically reduces
the input capacitor’s RMS ripple current by a factor of
30% to 70% when compared to a single phase power
supply solution.
The type of input capacitor, value and ESR rating have
effi ciency effects that need to be considered in the selec-
tion process. The capacitance value chosen should be
suffi cient to store adequate charge to keep high peak
battery currents down. 20µF to 40µF is usually suffi cient
for a 25W output supply operating at 200kHz. The ESR of
the capacitor is important for capacitor power dissipation
as well as overall battery effi ciency. All of the power (RMS
ripple current • ESR) not only heats up the capacitor but
wastes power from the battery.
Medium voltage (20V to 35V) ceramic, tantalum, OS-CON
and switcher-rated electrolytic capacitors can be used
as input capacitors, but each has drawbacks: ceramic
voltage coeffi cients are very high and may have audible
piezoelectric effects; tantalums need to be surge-rated;
OS-CONs suffer from higher inductance, larger case size
and limited surface-mount applicability; electrolytics’
higher ESR and dryout possibility require several to be
used. Multiphase systems allow the lowest amount of
capacitance overall. As little as one 22µF or two to three
10µF ceramic capacitors are an ideal choice in a 20W to
35W power supply due to their extremely low ESR. Even
though the capacitance at 20V is substantially below their
rating at zero-bias, very low ESR loss makes ceramics
an ideal candidate for highest effi ciency battery operated
systems. Also consider parallel ceramic and high quality
electrolytic capacitors as an effective means of achieving
ESR and bulk capacitance goals.
In continuous mode, the source current of the top N-channel
MOSFET is a square wave of duty cycle VOUT/VIN. To prevent
large voltage transients, a low ESR input capacitor sized for
LTC3728
18
3728fg
APPLICATIONS INFORMATION
the maximum RMS current of one channel must be used.
The maximum RMS capacitor current is given by:
CIN RequiredIRMS IMAX
VOUT VIN VOUT
()
1/ 2
VIN
This formula has a maximum at VIN = 2VOUT
, where
IRMS = IOUT/2. This simple worst case condition is com-
monly used for design because even signifi cant deviations
do not offer much relief. Note that capacitor manufacturer’s
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the capaci-
tor, or to choose a capacitor rated at a higher temperature
than required. Several capacitors may also be paralleled
to meet size or height requirements in the design. Always
consult the manufacturer if there is any question.
The benefi t of the LTC3728 multiphase can be calculated by
using the equation above for the higher power controller
and then calculating the loss that would have resulted if
both controller channels switch on at the same time. The
total RMS power lost is lower when both controllers are
operating due to the interleaving of current pulses through
the input capacitor’s ESR. This is why the input capacitor’s
requirement calculated above for the worst-case controller
is adequate for the dual controller design. Remember that
input protection fuse resistance, battery resistance and PC
board trace resistance losses are also reduced due to the
reduced peak currents in a multiphase system.
The overall
benefi t of a multiphase design will only be fully realized
when the source impedance of the power supply/battery
is included in the effi ciency testing.
The drains of the
two top MOSFETs should be placed within 1cm of each
other and share a common CIN(s). Separating the drains
and CIN may produce undesirable voltage and current
resonances at VIN.
The selection of COUT is driven by the required effective
series resistance (ESR). Typically, once the ESR require-
ment is satisfi ed the capacitance is adequate for fi ltering.
The output ripple (∆VOUT) is determined by:
VOUT ILESR +1
8fCOUT
Where f = operating frequency, COUT = output capacitance,
and ∆IL= ripple current in the inductor. The output ripple is
highest at maximum input voltage since ∆IL increases with
input voltage. With ∆IL = 0.3IOUT(MAX) the output ripple
will typically be less than 50mV at max VIN assuming:
C
OUT Recommended ESR < 2 RSENSE
and COUT > 1/(8fRSENSE)
The fi rst condition relates to the ripple current into the ESR
of the output capacitance while the second term guarantees
that the output capacitance does not signifi cantly discharge
during the operating frequency period due to ripple current.
The choice of using smaller output capacitance increases
the ripple voltage due to the discharging term but can be
compensated for by using capacitors of very low ESR to
maintain the ripple voltage at or below 50mV. The ITH pin
OPTI-LOOP compensation components can be optimized
to provide stable, high performance transient response
regardless of the output capacitors selected.
Manufacturers such as Nichicon, United Chemicon and
Sanyo can be considered for high performance through-
hole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo has the lowest (ESR)(size)
product of any aluminum electrolytic at a somewhat
higher price. An additional ceramic capacitor in parallel
with OS-CON capacitors is recommended to reduce the
inductance effects.
In surface mount applications multiple capacitors may
need to be used in parallel to meet the ESR, RMS current
handling and load step requirements of the application.
Aluminum electrolytic, dry tantalum and special polymer
capacitors are available in surface mount packages. Special
polymer surface mount capacitors offer very low ESR but
LTC3728
19
3728fg
APPLICATIONS INFORMATION
have lower storage capacity per unit volume than other
capacitor types. These capacitors offer a very cost-effec-
tive output capacitor solution and are an ideal choice when
combined with a controller having high loop bandwidth.
Tantalum capacitors offer the highest capacitance density
and are often used as output capacitors for switching
regulators having controlled soft-start. Several excellent
surge-tested choices are the AVX TPS, AVX TPSV or the
KEMET T510 series of surface mount tantalums, available
in case heights ranging from 2mm to 4mm. Aluminum
electrolytic capacitors can be used in cost-driven ap-
plications providing that consideration is given to ripple
current ratings, temperature and long term reliability. A
typical application will require several to many aluminum
electrolytic capacitors in parallel. A combination of the
aforementioned capacitors will often result in maximizing
performance and minimizing overall cost. Other capacitor
types include Nichicon PL series, NEC Neocap, Cornell
Dubilier ESRE and Sprague 595D series. Consult manu-
facturers for other specifi c recommendations.
INTVCC Regulator
An internal P-channel low dropout regulator produces 5V
at the INTVCC pin from the VIN supply pin. INTVCC pow-
ers the drivers and internal circuitry within the LTC3728.
The INTVCC pin regulator can supply a peak current of
50mA and must be bypassed to ground with a minimum
of 4.7F tantalum, 10µF special polymer, or low ESR type
electrolytic capacitor. A 1µF ceramic capacitor placed di-
rectly adjacent to the INTVCC and PGND IC pins is highly
recommended. Good bypassing is necessary to supply
the high transient currents required by the MOSFET gate
drivers and to prevent interaction between channels.
Higher input voltage applications in which large MOS-
FETs are being driven at high frequencies may cause the
maximum junction temperature rating for the LTC3728
to be exceeded. The system supply current is normally
dominated by the gate charge current. Additional external
loading of the INTVCC and 3.3V linear regulators also
needs to be taken into account for the power dissipation
calculations. The total INTVCC current can be supplied by
either the 5V internal linear regulator or by the EXTVCC
input pin. When the voltage applied to the EXTVCC pin is
less than 4.7V, all of the INTVCC current is supplied by
the internal 5V linear regulator. Power dissipation for the
IC in this case is highest: (VIN)(IINTVCC), and overall ef-
fi ciency is lowered. The gate charge current is dependent
on operating frequency, as discussed in the Effi ciency
Considerations section. The junction temperature can be
estimated by using the equations given in Note 2 of the
Electrical Characteristics. For example, the LTC3728 VIN
current is limited to less than 24mA from a 24V supply
when not using the EXTVCC pin, as follows:
T
J = 70°C + (24mA)(24V)(95°C/W) = 125°C
Use of the EXTVCC input pin reduces the junction tem-
perature to:
T
J = 70°C + (24mA)(5V)(95°C/W) = 81°C
Dissipation should be calculated to also include any added
current drawn from the internal 3.3V linear regulator.
To prevent maximum junction temperature from being
exceeded, the input supply current must be checked op-
erating in continuous mode at maximum VIN.
EXTVCC Connection
The LTC3728 contains an internal P-channel MOSFET
switch connected between the EXTVCC and INTVCC pins.
When the voltage applied to EXTVCC rises above 4.7V,
the internal regulator is turned off and the switch closes,
connecting the EXTVCC pin to the INTVCC pin thereby
supplying internal power. The switch remains closed as
long as the voltage applied to EXTVCC remains above 4.5V.
This allows the MOSFET driver and control power to be
derived from the output during normal operation (4.7V
< VOUT < 7V) and from the internal regulator when the
output is out of regulation (start-up, short-circuit). If more
current is required through the EXTVCC switch than is
specifi ed, an external Schottky diode can be added between
the EXTVCC and INTVCC pins. Do not apply greater than 7V
to the EXTVCC pin and ensure that EXTVCC < VIN.
Signifi cant effi ciency gains can be realized by powering
INTVCC from the output, since the VIN current resulting
from the driver and control currents will be scaled by a
LTC3728
20
3728fg
APPLICATIONS INFORMATION
factor of (Duty Cycle)/(Effi ciency). For 5V regulators this
supply means connecting the EXTVCC pin directly to VOUT
.
However, for 3.3V and other lower voltage regulators,
additional circuitry is required to derive INTVCC power
from the output.
The following list summarizes the four possible connec-
tions for EXTVCC:
1. EXTVCC Left Open (or Grounded). This will cause INTVCC
to be powered from the internal 5V regulator resulting in
an effi ciency penalty of up to 10% at high input voltages.
2. EXTVCC Connected Directly to VOUT. This is the normal
connection for a 5V regulator and provides the highest
effi ciency.
3. EXTVCC Connected to an External Supply. If an external
supply is available in the 5V to 7V range, it may be used
to power EXTVCC providing it is compatible with the
MOSFET gate drive requirements.
4. EXTVCC Connected to an Output-Derived Boost Network.
For 3.3V and other low voltage regulators, effi ciency
gains can still be realized by connecting EXTVCC to an
output-derived voltage that has been boosted to greater
than 4.7V. This can be done with either the inductive
boost winding as shown in Figure 6a or the capacitive
charge pump shown in Figure 6b. The charge pump
has the advantage of simple magnetics.
Topside MOSFET Driver Supply (CB, DB)
External bootstrap capacitors CB connected to the BOOST
pins supply the gate drive voltages for the topside MOS-
FETs. Capacitor CB in the Functional Diagram is charged
though external diode DB from INTVCC when the SW pin
is low. When one of the topside MOSFETs is to be turned
on, the driver places the CB voltage across the gate-source
of the desired MOSFET. This enhances the MOSFET and
turns on the topside switch. The switch node voltage, SW,
rises to VIN and the BOOST pin follows. With the topside
MOSFET on, the boost voltage is above the input supply:
VBOOST = VIN + VINTVCC. The value of the boost capacitor
CB needs to be 100 times that of the total input capacitance
of the topside MOSFET(s). The reverse breakdown of the
external Schottky diode must be greater than VIN(MAX).
When adjusting the gate drive level, the fi nal arbiter is the
total input current for the regulator. If a change is made
and the input current decreases, then the effi ciency has
improved. If there is no change in input current, then there
is no change in effi ciency.
Output Voltage
The LTC3728 output voltages are each set by an exter-
nal feedback resistive divider carefully placed across
the output capacitor. The resultant feedback signal is
compared with the internal precision 0.800V voltage
EXTVCC
FCB
SGND
VIN
TG1
SW
BG1
PGND
LTC3728
RSENSE
VOUT
VSEC
+
COUT
+
1MF
3728 F06a
N-CH
N-CH
R6
+CIN
VIN
T1
1:N
OPTIONAL EXTVCC
CONNECTION
5V < VSEC < 7V
R5
EXTVCC
VIN
TG1
SW
BG1
PGND
LTC3728
RSENSE
VOUT
VN2222LL
+
COUT
3728 F06b
N-CH
N-CH
+
CIN
+1MF
VIN
L1
BAT85 BAT85
BAT85
0.22MF
Figure 6a. Secondary Output Loop and EXTVCC Connection Figure 6b. Capacitive Charge Pump for EXTVCC
LTC3728
21
3728fg
APPLICATIONS INFORMATION
reference by the error amplifi er. The output voltage is given
by the equation:
VOUT =0.8V 1+R2
R1
where R1 and R2 are defi ned in Figure 2.
SENSE+/SENSE– PINS
The common mode input range of the current comparator
sense pins is from 0V to (1.1)INTVCC. Continuous linear
operation is guaranteed throughout this range allowing
output voltage setting from 0.8V to 7.7V, depending upon
the voltage applied to EXTVCC. A differential NPN input
stage is biased with internal resistors from an internal 2.4V
source, as shown in the Functional Diagram. This requires
that current either be sourced or sunk from the SENSE
pins depending on the output voltage. If the output voltage
is below 2.4V, current will fl ow out of both SENSE pins to
the main output. The output can be easily preloaded by
the VOUT resistive divider to compensate for the current
comparator’s negative input bias current. The maximum
current fl owing out of each pair of SENSE pins is:
I
SENSE+ + ISENSE– = (2.4V – VOUT)/24k
Since VOSENSE is servoed to the 0.8V reference voltage,
we can choose R1 in Figure 2 to have a maximum value
to absorb this current.
R1(MAX) =24k 0.8V
2.4V – VOUT
for VOUT < 2.4V
Regulating an output voltage of 1.8V, the maximum value
of R1 should be 32k. Note that for an output voltage above
2.4V, R1 has no maximum value necessary to absorb the
sense currents; however, R1 is still bounded by the VOSENSE
feedback current.
Soft-Start/Run Function
The RUN/SS1 and RUN/SS2 pins are multipurpose pins
that provide a soft-start function and a means to shut down
the LTC3728. Soft-start reduces the input power source’s
surge currents by gradually increasing the controller’s
current limit (proportional to VITH). This pin can also be
used for power supply sequencing.
An internal 1.2µA current source charges up the CSS
capacitor. When the voltage on RUN/SS1 (RUN/SS2)
reaches 1.5V, the particular controller is permitted to start
operating. As the voltage on RUN/SS increases from 1.5V
to 3.0V, the internal current limit is increased from 25mV/
RSENSE to 75mV/RSENSE. The output current limit ramps
up slowly, taking an additional 1.25s/F to reach full cur-
rent. The output current thus ramps up slowly, reducing
the starting surge current required from the input power
supply. If RUN/SS has been pulled all the way to ground
there is a delay before starting of approximately:
tDELAY =1.5V
1.2μACSS =1.25s / μF
()
CSS
tIRAMP =3V 1.5V
1.2μACSS =1.25s / μF
()
CSS
By pulling both RUN/SS pins below 1V, the LTC3728 is put
into low current shutdown (IQ = 20µA). The RUN/SS pins
can be driven directly from logic, as shown in Figure 7.
Diode D1 in Figure 7 reduces the start delay but allows
CSS to ramp up slowly providing the soft-start function.
Each RUN/SS pin has an internal 6V Zener clamp (see
the Functional Diagram).
LTC3728
22
3728fg
APPLICATIONS INFORMATION
Fault Conditions: Overcurrent Latchoff
The RUN/SS pins also provide the ability to latch off the
controller(s) when an overcurrent condition is detected. The
RUN/SS capacitor, CSS, is used initially to turn on and limit
the inrush current. After the controller has been started and
given adequate time to charge up the output capacitor and
provide full load current, the RUN/SS capacitor is used for
a short-circuit timer. If the regulator’s output voltage falls
to less than 70% of its nominal value after CSS reaches
4.1V, CSS begins discharging on the assumption that the
output is in an overcurrent condition. If the condition lasts
for a long enough period, as determined by the size of the
CSS and the specifi ed discharge current, the controller will
be shut down until the RUN/SS pin voltage is recycled.
If the overload occurs during start-up, the time can be
approximated by:
t
LO1 ≈ [CSS(4.1 – 1.5 + 4.1 – 3.5)]/(1.2µA)
= 2.7 • 106 (CSS)
If the overload occurs after start-up, the voltage on CSS
will begin discharging from the Zener clamp voltage:
t
LO2 ≈ [CSS (6 – 3.5)]/(1.2µA) = 2.1 • 106 (CSS)
This built-in overcurrent latchoff can be overridden by
providing a pull-up resistor to the RUN/SS pin, as shown
in Figure 7. This resistance shortens the soft-start period
and prevents the discharge of the RUN/SS capacitor during
an over current condition. Tying this pull-up resistor to
VIN (as in Figure 7) defeats overcurrent latchoff.
Why should you defeat overcurrent latchoff? During the
prototyping stage of a design there may be a problem
with noise pickup or poor layout, causing the protection
circuit to latch off. Defeating this feature will easily allow
troubleshooting of the circuit and PC layout. The internal
short-circuit and foldback current limiting still remains
active, thereby protecting the power supply system from
failure. After the design is complete, a decision can be
made whether to enable the latchoff feature.
The value of the soft-start capacitor CSS may need to be
scaled with output voltage, output capacitance and load
current characteristics. The minimum soft-start capaci-
tance is given by:
C
SS > (COUT )(VOUT) (10–4) (RSENSE)
The minimum recommended soft-start capacitor of
CSS = 0.1µF will be suffi cient for most applications.
Fault Conditions: Current Limit and Current Foldback
The LTC3728 current comparator has a maximum sense
voltage of 75mV, resulting in a maximum MOSFET cur-
rent of 75mV/RSENSE. The maximum value of current
limit generally occurs with the largest VIN at the highest
ambient temperature—conditions that cause the highest
power dissipation in the top MOSFET.
The LTC3728 includes current foldback to help further
limit load current when the output is shorted to ground.
The foldback circuit is active even when the overload
shutdown latch previously described is overridden. If the
output falls below 70% of its nominal output level, then
the maximum sense voltage is progressively lowered from
75mV to 25mV. Under short-circuit conditions with very
low duty cycles, the LTC3728 will begin cycle skipping in
order to limit the short-circuit current. In this situation,
the bottom MOSFET will be dissipating most of the power
but less than in normal operation. The short-circuit ripple
current is determined by the minimum on-time tON(MIN)
of the LTC3728 (less than 200ns), the input voltage and
inductor value:
∆IL(SC) = tON(MIN) (VIN/L)
The resulting short-circuit current is:
ISC =25mV
RSENSE
+1
2IL(SC)
3.3V OR 5V RUN/SS
VIN
D1
CSS
RSS*
3728 F07
*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF
Figure 7. RUN/SS Pin Interfacing
LTC3728
23
3728fg
APPLICATIONS INFORMATION
Fault Conditions: Overvoltage Protection (Crowbar)
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes
huge currents to fl ow that blow the fuse to protect against
a shorted top MOSFET, if the short occurs while the con-
troller is operating.
A comparator monitors the output for overvoltage con-
ditions. The comparator (OV) detects overvoltage faults
greater than 7.5% above the nominal output voltage. When
this condition is sensed, the top MOSFET is turned off
and the bottom MOSFET is turned on until the overvolt-
age condition is cleared. The output of this comparator
is only latched by the overvoltage condition itself and
will, therefore, allow a switching regulator system hav-
ing a poor PC layout to function while the design is being
debugged. The bottom MOSFET remains on continuously
for as long as the OV condition persists. If VOUT returns
to a safe level, normal operation automatically resumes. A
shorted top MOSFET will result in a high current condition
which will open the system fuse. The switching regulator
will regulate properly with a leaky top MOSFET by altering
the duty cycle to accommodate the leakage.
Phase-Locked Loop and Frequency Synchronization
The LTC3728 has a phase-locked loop comprised of an
internal voltage controlled oscillator and phase detector.
This allows the top MOSFET turn-on to be locked to the
rising edge of an external source. The frequency range
of the voltage controlled oscillator is ±50% around the
center frequency, fO. A voltage applied to the PLLFLTR
pin of 1.2V corresponds to a frequency of approximately
400kHz. The nominal operating frequency range of the
LTC3728 is 250kHz to 550kHz.
The phase detector used is an edge-sensitive digital
type which provides zero degrees phase shift between
the external and internal oscillators. This type of phase
detector will not lock up on input frequencies close to the
harmonics of the VCO center frequency. The PLL hold-in
range, ∆fH, is equal to the capture range, ∆fC:
∆fH = ∆fC = ±0.5 fO (250kHz-550kHz)
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
fi lter network on the PLLFLTR pin.
If the external frequency (fPLLIN) is greater than the oscil-
lator frequency, fOSC, current is sourced continuously,
pulling up the PLLFLTR pin. When the external frequency is
less than fOSC, current is sunk continuously, pulling down
the PLLFLTR pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to the
phase difference. Thus, the voltage on the PLLFLTR pin is
adjusted until the phase and frequency of the external and
internal oscillators are identical. At this stable operating
point, the phase comparator output is open and the fi lter
capacitor CLP holds the voltage. The LTC3728 PLLIN pin
must be driven from a low impedance source such as a
logic gate located close to the pin. When using multiple
LTC3728’s (or LTC3729’s, as shown in Figure 14) for a
phase-locked system, the PLLFLTR pin of the master
oscillator should be biased at a voltage that will guarantee
the slave oscillator(s) ability to lock onto the master’s
frequency. A DC voltage of 0.7V to 1.7V applied to the
master oscillator’s PLLFLTR pin is recommended in order
to meet this requirement. The resultant operating frequency
can range from 300kHz to 470kHz.
The loop fi lter components (CLP , RLP) smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The fi lter
components, CLP and RLP, determine how fast the loop
acquires lock. Typically, RLP =10k, and CLP is 0.01µF
to 0.1µF.
LTC3728
24
3728fg
APPLICATIONS INFORMATION
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest time duration
that the LTC3728 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
tON(MIN) <VOUT
VIN(f)
If the duty cycle falls below what can be accommodated
by the minimum on-time, the LTC3728 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The typical tested minimum on-time of the LTC3728 is
100ns under an ideal condition without switching noise.
However, the minimum on-time can be affected by PCB
switching noise in the voltage and current loops. With
reasonably good PCB layout, minimum 30% inductor
current ripple and about 15mV sensing ripple voltage,
200ns minimum on-time is a conservative number to
start with.
FCB Pin Operation
The FCB pin can be used to regulate a secondary winding
or as a logic-level input. Continuous operation is forced
on both controllers when the FCB pin drops below 0.8V.
During continuous mode, current fl ows continuously in
the transformer primary. The secondary winding(s) draw
current only when the bottom, synchronous switch is on.
When primary load currents are low and/or the VIN/VOUT
ratio is low, the synchronous switch may not be on for a
suffi cient amount of time to transfer power from the output
capacitor to the secondary load. Forced continuous opera-
tion will support secondary windings providing there is
suffi cient synchronous switch duty factor. Thus, the FCB
input pin removes the requirement that power must be
drawn from the inductor primary in order to extract power
from the auxiliary windings. With the loop in continuous
mode, the auxiliary outputs may nominally be loaded
without regard to the primary output load.
The secondary output voltage, VSEC, is normally set (as
shown in Figure 6a) by the turns ratio N of the trans-
former:
V
SEC ≅ (N + 1) VOUT
However, if the controller goes into Burst Mode operation
and halts switching due to a light primary load current, then
VSEC will droop. An external resistive divider from VSEC to
the FCB pin sets a minimum voltage VSEC(MIN):
VSEC(MIN) 0.8V 1+R6
R5
where R5 and R6 are shown in Figure 2.
If VSEC drops below this level, the FCB voltage forces
temporary continuous switching operation until VSEC is
again above its minimum.
In order to prevent erratic operation if no external connec-
tions are made to the FCB pin, the FCB pin has a 0.18A
internal current source pulling the pin high. Include this
current when choosing resistor values R5 and R6.
Table 1 summarizes the possible states available on the
FCB pin:
Table 1
FCB Pin Condition
0V to 0.75V Forced Continuous Both Controllers
(Current Reversal Allowed—Burst
Inhibited)
0.85V < VFCB < 4.0V Minimum Peak Current Induces
Burst Mode Operation
No Current Reversal Allowed
Feedback Resistors Regulating a Secondary Winding
>4.8V Burst Mode Operation Disabled
Constant-Frequency Mode Enabled
No Current Reversal Allowed
No Minimum Peak Current
LTC3728
25
3728fg
APPLICATIONS INFORMATION
Voltage Positioning
Voltage positioning can be used to minimize peak-to-peak
output voltage excursions under worst-case transient
loading conditions. The open-loop DC gain of the control
loop is reduced depending upon the maximum load step
specifi cations. Voltage positioning can easily be added to
the LTC3728 by loading the ITH pin with a resistive divider
having a Thevenin equivalent voltage source equal to the
midpoint operating voltage range of the error amplifi er, or
1.2V (see Figure 8).
The resistive load reduces the DC loop gain while main-
taining the linear control range of the error amplifi er. The
maximum output voltage deviation can theoretically be
reduced to half, or alternatively, the amount of output
capacitance can be reduced for a particular application.
A complete explanation is included in Design Solutions
10 (see www.linear.com).
Effi ciency Considerations
The percent effi ciency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the effi ciency and which change would
produce the most improvement. Percent effi ciency can
be expressed as:
%Effi ciency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
ITH
RC
RT1
INTVCC
CC
3728 F08
LTC3728
RT2
Figure 8. Active Voltage Positioning
Applied to the LTC3728
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most
of the losses in LTC3728 circuits: 1) LTC3728 VIN cur-
rent (including loading on the 3.3V internal regulator),
2) INTVCC regulator current, 3) I2R losses, 4) Topside
MOSFET transition losses.
1. The VIN current has two components: the fi rst is the
DC supply current given in the Electrical Characteristics
table, which excludes MOSFET driver and control cur-
rents; the second is the current drawn from the 3.3V
linear regulator output. VIN current typically results in
a small (<0.1%) loss.
2. INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ
moves from INTVCC to ground. The resulting dQ/dt is
a current out of INTVCC that is typically much larger
than the control circuit current. In continuous mode,
IGATECHG = f(QT QB), where QT and QB are the gate
charges of the topside and bottom side MOSFETs.
Supplying INTVCC power through the EXTVCC switch
input from an output-derived source will scale the VIN
current required for the driver and control circuits by
a factor of (Duty Cycle)/(Effi ciency). For example, in a
20V to 5V application, 10mA of INTVCC current results
in approximately 2.5mA of VIN current. This reduces
the mid-current loss from 10% or more (if the driver
was powered directly from VIN) to only a few percent.
3. I2R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resis-
tor, and input and output capacitor ESR. In continuous
mode, the average output current fl ows through L and
RSENSE, but is “chopped” between the topside MOSFET
and the synchronous MOSFET. If the two MOSFETs
have approximately the same RDS(ON), then the resis-
tance of one MOSFET can simply be summed with the
resistances of L, RSENSE and ESR to obtain I2R losses.
For example, if each RDS(ON) = 30m, RL = 50m,
LTC3728
26
3728fg
APPLICATIONS INFORMATION
RSENSE = 10m and RESR = 40m (sum of both input
and output capacitance losses), then the total resistance
is 130m. This results in losses ranging from 3% to
13% as the output current increases from 1A to 5A for
a 5V output, or a 4% to 20% loss for a 3.3V output.
Effi ciency varies as the inverse square of VOUT for the
same external components and output power level. The
combined effects of increasingly lower output voltages
and higher currents required by high performance digital
systems is not doubling but quadrupling the importance
of loss terms in the switching regulator system!
4. Transition losses apply only to the topside MOSFET(s),
and become signifi cant only when operating at high
input voltages (typically 15V or greater). Transition
losses can be estimated from:
Transition Loss = (1.7) VIN2 IO(MAX) CRSS f
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% effi ciency degradation in portable systems. It is very
important to include these system level losses during the
design phase. The internal battery and fuse resistance
losses can be minimized by ensuring CIN has adequate
charge storage and very low ESR at the switching frequency.
A 25W supply will typically require a minimum of 20µF
to 40µF of capacitance having a maximum of 20m to
50m of ESR. The LTC3728 2-phase architecture typically
halves this input capacitance requirement over competing
solutions. Other losses, including Schottky conduction
losses during dead time and inductor core losses, generally
account for less than 2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT shifts by
an amount equal to ∆ILOAD (ESR), where ESR is the ef-
fective series resistance of COUT. ∆ILOAD also begins to
charge or discharge COUT, generating the feedback error
signal that forces the regulator to adapt to the current
change and return VOUT to its steady-state value. During
this recovery time, VOUT can be monitored for excessive
overshoot or ringing, which would indicate a stability
problem. OPTI-LOOP compensation allows the transient
response to be optimized over a wide range of output
capacitance and ESR values. The availability of the ITH pin
not only allows optimization of control loop behavior but
also provides a DC-coupled and AC-fi ltered closed loop
response test point. The DC step, rise time and settling
at this test point truly refl ects the closed loop response.
Assuming a predominantly second order system, phase
margin and/or damping factor can be estimated using the
percentage of overshoot seen at this pin. The bandwidth
can also be estimated by examining the rise time at the
pin. The ITH external components shown in the Figure 1
circuit will provide an adequate starting point for most
applications.
The ITH series RC-CC fi lter sets the dominant pole-zero
loop compensation. The values can be modifi ed slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the fi nal PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1µs to 10µs will
produce output voltage and ITH pin waveforms that will
give a sense of the overall loop stability without break-
ing the feedback loop. Placing a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This
is why it is better to look at the ITH pin signal, which is
in the feedback loop and is the fi ltered and compensated
control loop response. The gain of the loop will be in-
creased by increasing RC and the bandwidth of the loop
will be increased by decreasing CC. If RC is increased by
the same factor that CC is decreased, the zero frequency
will be kept the same, thereby keeping the phase shift the
same in the most critical frequency range of the feedback
LTC3728
27
3728fg
APPLICATIONS INFORMATION
loop. The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT
. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited to
approximately 25 • CLOAD. Thus, a 10µF capacitor would
require a 250µs rise time, limiting the charging current
to about 200mA.
Automotive Considerations: Plugging into the
Cigarette Lighter
As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserve or even recharge battery packs during opera-
tion. But before you connect, be advised: you are plug-
ging into the supply from hell. The main power line in an
automobile is the source of a number of nasty potential
transients, including load-dump, reverse-battery and
double-battery.
Load-dump is the result of a loose battery cable. When the
cable breaks connection, the fi eld collapse in the alterna-
tor can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse-battery is
just what it says, while double-battery is a consequence of
tow truck operators fi nding that a 24V jump start cranks
cold engines faster than 12V.
The network shown in Figure 9 is the most straight for-
ward approach to protect a DC/DC converter from the
ravages of an automotive power line. The series diode
prevents current from fl owing during reverse-battery,
while the transient suppressor clamps the input voltage
during load-dump. Note that the transient suppressor
should not conduct during double-battery operation, but
must still clamp the input voltage below breakdown of the
converter. Although the LTC3728 has a maximum input
voltage of 36V, most applications will be limited to 30V
by the MOSFET BVDSS.
Figure 9. Automotive Application Protection
VIN
3728 F09
LTC3728
TRANSIENT VOLTAGE
SUPPRESSOR
GENERAL INSTRUMENT
1.5KA24A
50A IPK RATING
12V
LTC3728
28
3728fg
APPLICATIONS INFORMATION
Design Example
As a design example for one channel, assume VIN = 12V
(nominal), VIN = 22V(max), VOUT = 1.8V, IMAX = 5A, and
f = 300kHz.
The inductance value is chosen fi rst based on a 30% ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the PLLFLTR
pin to a resistive divider using the INTVCC pin generating
1V for 300kHz operation. The minimum inductance for
30% ripple current is:
IL=VOUT
(f)(L)1– VOUT
VIN
A 4.7µH inductor will produce 23% ripple current and a
3.3µH will result in 33%. The peak inductor current will
be the maximum DC value plus one-half the ripple cur-
rent, or 5.84A, for the 3.3µH value. Increasing the ripple
current will also help ensure that the minimum on-time
of 100ns is not violated. The minimum on-time occurs at
maximum VIN:
tON(MIN) =VOUT
VIN(MAX)f=1.8V
22V(300kHz) =273ns
The RSENSE resistor value can be calculated by using the
maximum current sense voltage specifi cation with some
accommodation for tolerances:
RSENSE 60mV
5.84A 0.01
Since the output voltage is below 2.4V the output resis-
tive divider will need to be sized to not only set the output
voltage but also to absorb the SENSE pins specifi ed input
current.
R1(MAX) =24k 0.8V
2.4V – VOUT
=24K 0.8V
2.4V – 1.8V
=32k
Choosing 1% resistors; R1 = 25.5k and R2 = 32.4k yields
an output voltage of 1.816V.
The power dissipation on the topside MOSFET can be
easily estimated. Choosing a Siliconix Si4412DY results
in RDS(ON) = 0.042, CRSS = 100pF. At maximum input
voltage with T(estimated) = 50°C:
P
MAIN =1.8V
22V 5
()
21+(0.005)(50°C–25°C)
[]
0.042
()
+1.7 22V
()
25A
()
100pF
()
300kHz
(
=220mW
A short-circuit to ground will result in a folded back cur-
rent of:
ISC =25mV
0.01+1
2
200ns(22V)
3.3μH
=3.2A
with a typical value of RDS(ON) and δ = (0.005/°C)(20) =
0.1. The resulting power dissipated in the bottom MOSFET
is:
PSYNC =22V – 1.8V
22V 3.2A
()
21.1
()
0.042
()
=434mW
which is less than under full-load conditions.
CIN is chosen for an RMS current rating of at least 3A at
temperature assuming only this channel is on. COUT is
chosen with an ESR of 0.02 for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
V
ORIPPLE = RESR (∆IL) = 0.02(1.67A) = 33mVP–P
LTC3728
29
3728fg
APPLICATIONS INFORMATION
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3728. These items are also illustrated graphically
in the layout diagram of Figure 10. Figure 11 illustrates
the current waveforms present in the various branches
of the 2-phase synchronous regulators operating in the
continuous mode. Check the following in your layout:
1. Are the top N-channel MOSFETs M1 and M3 located
within 1cm of each other with a common drain connec-
tion at CIN? Do not attempt to split the input decoupling
for the two channels as it can cause a large resonant
loop.
2. Are the signal and power grounds kept separate? The
combined LTC3728 signal ground pin and the ground
return of CINTVCC must return to the combined COUT
(–) terminals. The path formed by the top N-channel
MOSFET, Schottky diode and the CIN capacitor should
have short leads and PC trace lengths. The output
capacitor (–) terminals should be connected as close
as possible to the (–) terminals of the input capacitor
by placing the capacitors next to each other and away
from the Schottky loop described above.
3. Do the LTC3728 VOSENSE pins resistive dividers connect
to the (+) terminals of COUT? The resistive divider must
be connected between the (+) terminal of COUT and
Figure 10. LTC3728 Recommended Printed Circuit Layout Diagram
CB2
CB1
RPU
PGOOD
VPULL-UP
(<7V)
CINTVCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+
CIN
D1
M1 M2
M3 M4
D2
+
CVIN
VIN
RIN
INTVCC
3.3V
R4R3
R2
R1
RUN/SS1
SENSE1+
SENSE1–
VOSENSE1
PLLFLTR
PLLIN
FCB
ITH1
SGND
3.3VOUT
ITH2
VOSENSE2
SENSE2–
SENSE2+
PGOOD
TG1
SW1
BOOST1
VIN
BG1
EXTVCC
INTVCC
PGND
BG2
BOOST2
SW2
TG2
RUN/SS2
LTC3728
L1
L2
COUT1
VOUT1
GND
VOUT2
3728 F10
+
COUT2
+
RSENSE
RSENSE
fIN
LTC3728
30
3728fg
APPLICATIONS INFORMATION
signal ground. The R2 and R4 connections should not
be along the high current input feeds from the input
capacitor(s).
4. Are the SENSE – and SENSE+ leads routed together
with minimum PC trace spacing? The fi lter capacitor
between SENSE+ and SENSE– should be as close as
possible to the IC. Ensure accurate current sensing
with Kelvin connections at the SENSE resistor.
5. Is the INTVCC decoupling capacitor connected close
to the IC, between the INTVCC and the power ground
pins? This capacitor carries the MOSFET drivers current
peaks. An additional 1µF ceramic capacitor placed im-
mediately next to the INTVCC and PGND pins can help
improve noise performance substantially.
6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2), and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from
the opposites channel’s voltage and current sensing
feedback pins. All of these nodes have very large and
fast moving signals and therefore should be kept on
the output side of the LTC3728 and occupy minimum
PC trace area.
7. Use a modifi ed “star ground” technique: a low imped-
ance, large copper area central grounding point on
the same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTVCC
decoupling capacitor, the bottom of the voltage feedback
resistive divider and the SGND pin of the IC.
Figure 11. Branch Current Waveforms
RL1
D1
L1
SW1 RSENSE1 VOUT1
COUT1
+
VIN
CIN
RIN +
RL2
D2
BOLD LINES INDICATE
HIGH, SWITCHING
CURRENT LINES.
KEEP LINES TO A
MINIMUM LENGTH.
L2
SW2
3728 F11
RSENSE2 VOUT2
COUT2
+
LTC3728
31
3728fg
APPLICATIONS INFORMATION
PC Board Layout Debugging
Start with one controller on at a time. It is helpful to use
a DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output volt-
age. Check for proper performance over the operating
voltage and current range expected in the application. The
frequency of operation should be maintained over the input
voltage range down to dropout and until the output load
drops below the low current operation threshold—typically
10% to 20% of the maximum designed current level in
Burst Mode operation.
The duty cycle percentage should be maintained from cycle
to cycle in a well designed, low noise PCB implementation.
Variation in the duty cycle at a subharmonic rate can sug-
gest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required. Only after each
controller is checked for their individual performance
should both controllers be turned on at the same time.
A particularly diffi cult region of operation is when one
controller channel is nearing its current comparator trip
point when the other channel is turning on its top MOSFET.
This occurs around 50% duty cycle on either channel due
to the phasing of the internal clocks and may cause minor
duty cycle jitter.
Short-circuit testing can be performed to verify proper
overcurrent latchoff, or 5µA can be provided to the RUN/SS
pin(s) by resistors from VIN to prevent the short-circuit
latchoff from occurring.
Reduce VIN from its nominal level to verify operation
of the regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering VIN while
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
for inductive coupling between CIN, Schottky and the top
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
SGND pin of the IC.
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still
be maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
LTC3728
32
3728fg
TYPICAL APPLICATIONS
Figure 12. LTC3728 High Effi ciency Low Noise 5V/3A, 3.3V/5A, 12V/120mA Regulator
0.1MF
0.1MF
4.7MF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+
22MF
50V
D1
MBRM
140T3
MBRS1100T3
D2
MBRM
140T3
M1 M2
M3 M4
1MF
10V
CMDSH-3TR
CMDSH-3TR
0.1MF
107
0.017
0.0157
3.3V
0.1MF
20k
1%
105k, 1%
33pF
15k
33pF
15k 1000pF
1000pF
1000pF
1000pF
0.1MF
20k
1%
63.4k
1%
RUN/SS1
SENSE1+
SENSE1–
VOSENSE1
PLLFLTR
PLLIN
FCB
ITH1
SGND
3.3VOUT
ITH2
VOSENSE2
SENSE2–
SENSE2+
PGOOD
TG1
SW1
BOOST1
VIN
BG1
EXTVCC
INTVCC
PGND
BG2
BOOST2
SW2
TG2
RUN/SS2
LTC3728
T1, 1:1.8
10MH
L1
6.3MH
150MF, 6.3V
PANASONIC SP 1MF
25V
180MF, 4V
PANASONIC SP
GND
ON/OFF
8
5
123
VOUT2
3.3V
5A; 6A PEAK
VOUT3
12V
120mA
33MF
25V
VOUT1
5V
3A; 4A PEAK
VIN
7V TO
28V
3728 F12
+ +
VIN: 7V TO 28V
VOUT: 5V, 3A/3.3V, 5A/12V, 120mA
SWITCHING FREQUENCY = 250kHz
MI, M2, M3, M4: NDS8410A
L1: SUMIDA CEP123-6R3MC
T1: 10MH 1:1.8 — DALE LPE6562-A262 GAPPED E-CORE OR BH ELECTRONICS #501-0657 GAPPED TOROID
LT1121
+
+
220k
100k
1M
PGOOD
100k VPULL-UP
(<7V)
59k
180pF
180pF
LTC3728
33
3728fg
TYPICAL APPLICATIONS
Figure 13. LTC3728 5V/4A, 3.3V/4A Regulator with External Frequency Synchronization
0.1MF
4.7MF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+
22MF
50V
M1
M2
1MF
10V
0.1MF
107
0.0157
0.0157
fSYNC
3.3V
0.1MF
10k
105k
1%
33pF
15k
33pF
15k 220pF
220pF
0.01MF1000pF
1000pF
1000pF
0.1MF
20k
1%
63.4k
1%
20k
1%
RUN/SS1
SENSE1+
SENSE1–
VOSENSE1
PLLFLTR
PLLIN
FCB
ITH1
SGND
3.3VOUT
ITH2
VOSENSE2
SENSE2–
SENSE2+
PGOOD
TG1
SW1
BOOST1
VIN
BG1
EXTVCC
INTVCC
PGND
BG2
BOOST2
SW2
TG2
RUN/SS2
LTC3728
L1
8MH
L2
8MH
47MF
6.3V
56MF, 4V
GND
VOUT2
3.3V
3A; 4A PEAK
VOUT1
5V
3A; 4A PEAK
VIN
5.2V TO
28V
3728 F13
+ +
VIN: 5.2V TO 28V
VOUT: 5V, 4A/3.3V, 4A
SWITCHING FREQUENCY = 250kHz TO 550kHz
MI, M2: FDS6982S
L1, L2: 8MH SUMIDA CEP1238R0MC
OUTPUT CAPACITORS: PANASONIC SP SERIES
27pF
27pF
0.1MF
CMDSH-3TR
CMDSH-3TR
PGOOD
VPULL-UP
(<7V)
LTC3728
34
3728fg
G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
PACKAGE DESCRIPTION
G28 SSOP 0204
0.09 – 0.25
(.0035 – .010)
0° – 8°
0.55 – 0.95
(.022 – .037)
5.00 – 5.60**
(.197 – .221)
7.40 – 8.20
(.291 – .323)
12345678 9 10 11 12 1413
9.90 – 10.50*
(.390 – .413)
2526 22 21 20 19 18 17 16 1523242728
2.0
(.079)
MAX
0.05
(.002)
MIN
0.65
(.0256)
BSC 0.22 – 0.38
(.009 – .015)
TYP
MILLIMETERS
(INCHES)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
*
**
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
0.42 ±0.03 0.65 BSC
5.3 – 5.7
7.8 – 8.2
RECOMMENDED SOLDER PAD LAYOUT
1.25 ±0.12
LTC3728
35
3728fg
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
UH32 Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
5.00 ± 0.10
(4 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
31
1
2
32
BOTTOM VIEW—EXPOSED PAD
3.50 REF
(4-SIDES)
3.45 ± 0.10
3.45 ± 0.10
0.75 ± 0.05 R = 0.115
TYP
0.25 ± 0.05
(UH32) QFN 0406 REV D
0.50 BSC
0.200 REF
0.00 – 0.05
0.70 ±0.05
3.50 REF
(4 SIDES)
4.10 ±0.05
5.50 ±0.05
0.25 ± 0.05
PACKAGE OUTLINE
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 × 45° CHAMFER
R = 0.05
TYP
3.45 ± 0.05
3.45 ± 0.05
LTC3728
36
3728fg
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2006
LT 0909 REV G • PRINTED IN USA
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, Power Good Output Signal, Synchronizable,
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Mobile Pentium III Processors, 550kHz, VIN ≤ 7V
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Output Fault Protection, 16-Pin SSOP
LTC1736 High Effi ciency Synchronous Controller with
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LTC1778 No RSENSE Current Mode Synchronous
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Up to 97% Effi ciency, 4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ (0.9)(VIN),
IOUT Up to 20A
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Controller with Digital 5-Bit Interface
Up to 97% Effi ciency, Ideal for Pentium III Processors, 0.925V ≤ VOUT ≤ 2V,
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LTC3729 20A to 200A, 550kHz PolyPhase Synchronous
Controller
Expandable from 2-Phase to 12-Phase, Uses All Surface Mount
Components, VIN Up to 36V
PolyPhase is a registered trademark of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation.
Figure 14. Multioutput PolyPhase Application
PHASMD
CLKOUT
TG1
TG2
0°
I1
I3
I2
I4
90°
OPEN
180°
U1
LTC3729
BUCK: 2.5V/15A
BUCK: 2.5V/15A
PLLIN
TG1
TG2
90°
90°
270°
U2
LTC3728
BUCK: 1.5V/15A
2.5VO/30A
CIN
IIN
12VIN
*INPUT RIPPLE CURRENT CANCELLATION
INCREASES THE RIPPLE FREQUENCY AND
REDUCES THE RMS INPUT RIPPLE CURRENT
THUS, SAVING INPUT CAPACITORS
IIN*
1.5VO/15A
1.8VO/15A
3728 F14
BUCK: 1.8V/15A
I1
I2
I3
I4
