General Description
The MAX1960/MAX1961/MAX1962 high-current, high-
efficiency voltage-mode step-down DC-DC controllers
operate from a 2.35V to 5.5V input and generate output
voltages down to 0.8V at up to 20A. An on-chip charge
pump generates a regulated 5V for MOSFET drive.
Additionally, adaptive dead-time drivers allow a
wide variety of MOSFETs to be used without risking
shoot-through.
Fixed-frequency PWM operation and external synchro-
nization make these controllers suitable for telecom
and datacom applications. The operating frequency is
programmable to either 500kHz or 1MHz, or from
450kHz to 1.2MHz with an external clock. A clock output
is provided to synchronize another converter for 180°
out-of-phase operation. A high closed-loop bandwidth
provides excellent transient response for applications
with dynamic loads.
Lossless current sensing in the MAX1960 and
MAX1961 is achieved by monitoring the drain-to-source
voltage of the low-side external FET. The current limit is
scalable to accommodate a wide variety of MOSFETs
and load currents. The MAX1962 has 10% accurate
sense-resistor-based current limiting.
The MAX1960 and MAX1962 have an adjustable output
voltage from 0.8V to 4.95V. The MAX1961 and
MAX1962 have four preset output voltages (1.5V, 1.8V,
2.5V, and 3.3V) and feature 0.5% voltage accuracy
over temperature, line, and load variations. The
MAX1960 and MAX1961 also feature voltage-margining
control inputs that shift the output voltage up or down
by 4% for system testing.
Applications
ASIC, FPGA, DSP, and CPU Core and I/O Voltages
Cellular Base Stations
Telecom and Network Equipment
Server and Storage Systems
Features
0.5% Accurate Output
Operates from 2.35V to 5.5V Supply
Generates Low Output Voltage Down to 0.8V
On-Chip Charge Pump Provides 5V Gate Drive
Ceramic or Electrolytic Capacitors
94% Efficiency
External Synchronization from 450kHz to 1.2MHz
500kHz/1MHz Fixed-Frequency PWM Operation
Fast Transient Response
Two Converters Can Operate 180° Out-of-Phase
±4% Voltage Margining for System Test
10% Accurate Current Sensing (MAX1962)
Adaptive Dead Time Prevents Shoot-Through
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
19-2740; Rev 1; 6/09
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
PART TEMP RANGE PIN-PACKAGE
MAX1960EEP -40°C to +85°C 20 QSOP
MAX1961EEP -40°C to +85°C 20 QSOP
MAX1962EEP -40°C to +85°C 20 QSOP
Pin Configurations and Selector Guide appear at the end
of the data sheet.
MAX1960
VCC
CTL1
COMP
REF
GND
FSET/SYNC
CLKOUT
AVDD
VDD
BST
DH
LX
DL
PGND
FB
C+ C-
INPUT
2.35V TO 5.5V
CLKOUT
180° OUT-OF-PHASE
OUTPUT
0.8 TO 0.87 ✕ VIN
UP TO 20A
CTL2
ILIM
OPTIONAL
SYNCHRONIZATION
VOLTAGE
MARGINING
AND ON/OFF
Typical Operating Circuit
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC, CTL_, CS, FSET/SYNC, SEL, EN,
OUT to GND ..........................................................-0.3V to +6V
ILIM, COMP, REF, FB, CLKOUT,
C- to GND ..............................................-0.3V to VAVDD + 0.3V
C+ to GND.............-0.3V to higher of VVCC + 1V or VVDD + 0.3V
VDD, AVDD to GND..............-0.3V to higher of VVCC - 0.3V or 6V
DL to PGND ................................................-0.3V to VVDD + 0.3V
BST to GND ............................................................-0.3V to +12V
DH to LX ...................................................................-0.3V to +6V
LX to BST..................................................................-6V to +0.3V
PGND to GND, or VDD to AVDD ............................-0.3V to +0.3V
Continuous Power Dissipation (TA= +70°C)
20-Pin QSOP (derate up to +70°C)..............................727mW
20-Pin QSOP (derate above +70°C)........................9.1mW/°C
Operating Temperature Range (Extended).........-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
ELECTRICAL CHARACTERISTICS
(VVCC = 3.3V, Circuits of Figures 9–12, TA= 0°C to +85°C. Typical values are at TA= +25°C, unless otherwise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC Input Voltage Range 2.35 5.5 V
VCC Input Voltage UVLO Rising or falling, hysteresis = 33mV (typ) 1.95 2.3 V
VDD Input Voltage UVLO Rising or falling, hysteresis = 44mV (typ) 3.9 4.45 V
Output Voltage 0.8 V
MAX1960/MAX1962 (measured at FB) 0.796 0.800 0.804
SEL = GND 1.492 1.500 1.508
SEL = REF 1.791 1.800 1.809
SEL not connected 2.487 2.500 2.514
DC Output Accuracy MAX1961/
MAX1962 (FB = VDD),
measured at output
SEL = VDD 3.272 3.300 3.336
V
Positive Voltage-Margining Shift MAX1960/MAX1961 +3.8 +4 +4.2 %
Negative Voltage-Margining Shift MAX1960/MAX1961 -3.8 -4 -4.2 %
Load Regulation Error 0V to full load 0.08 %
Line Regulation Error VVCC = 2.7V to 5.5V 0.1 %
FB Input Bias Current -0.2 +0.2 µA
Feedback Transconductance 1 2 3 mS
COMP Discharge Resistance In shutdown 10 100 Ω
DC-DC Soft-Start Time 1280 cycles
FSET/SYNC = GND 450 500 550
Switching Frequency FSET/SYNC = VCC 880 1000 1120 kHz
SYNC Frequency Range 450 1200 kHz
Maximum Duty Cycle f = 1MHz 80 83 %
Maximum Duty Cycle f = 500kHz 90 92 %
Quiescent Supply Current 11 15 mA
Shutdown Supply Current 15 µA
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VVCC = 3.3V, Circuits of Figures 9–12, TA= 0°C to +85°C. Typical values are at TA= +25°C, unless otherwise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
2.7V ≤ VVCC ≤ 5.5V, ILOAD = 1mA to 50mA 4.75 5.25 V
2.35V ≤ VVCC ≤ 2.7V, ILOAD = 1mA to 35mA, C1
= 4.7µF, C6 = 22µF (Note 1) 4.45 5.25 V
VDD Output Voltage
2.35V ≤ VVCC ≤ 3.6V with tripler, ILOAD = 1 to
50mA (circuit of Figure 12) (Note 1) 4.75 5.25 V
Reference Voltage (No Load) 1.269 1.280 1.291 V
Reference Load Regulation -50µA to +50µA3mV
VOUT = 0.8V 44 53 62
VOUT = 2.0V 45 50 55
Positive Current-Limit Threshold
(VPGND - VLX)MAX1962
VOUT = 3.3V 38 48 58
mV
Negative Current-Limit Threshold
(VLX - VPGND)MAX1962, VOUT = 0.8V to 3.3V 38 50 68 mV
CS Bias Current MAX1962, VCS = 3.3V 20 50 µA
OUT Bias Current MAX1961/MAX1962, VOUT = 3.3V 30 50 µA
Current-Limit Threshold (Positive
Direction, Fixed, VPGND - VLX)MAX1960/MAX1961, ILIM = VDD 58 74 90 mV
Current-Limit Threshold (Negative
Direction, Fixed, VLX - VPGND)MAX1960/MAX1961, ILIM = VDD 50 67 85 mV
MAX1960/MAX1961, RILIM = 160kΩ100 114 135
Current-Limit Threshold (Positive
Direction, Adjustable, VPGND - VLX)RILIM = 400kΩ250 279 306 mV
MAX1960/MAX1961, RILIM = 160kΩ90 107 125
Current-Limit Threshold (Negative
Direction, Adjustable, VLX - VPGND)RILIM = 400kΩ245 271 296 mV
Thermal-Shutdown Threshold 15°C hysteresis +160 °C
DH Gate-Driver On-Resistance VBST - VLX = 5V, pulling up or down 1.8 3.5 Ω
DL Gate-Driver On-Resistance (Pullup) DL high state 1.8 3.5 Ω
DL Gate-Driver On-Resistance (Pulldown) DL low state 0.5 1.6 Ω
DH falling to DL rising 35
Minimum Adaptive Dead Time DH rising to DL falling 26 ns
Minimum high time (Note 1) 200
FSET/SYNC Pulse Width Minimum low time (Note 1) 200 ns
FSET/SYNC Rise/Fall Time (Note 1) 100 ns
CTL_, FSET/SYNC, EN Input High Voltage VVCC = 2.35V to 5.5V 2.0 V
CTL_, FSET/SYNC, EN Input Low Voltage VVCC = 2.35V to 5.5V 0.8 V
CTL_, FSET/SYNC, EN Input Current -1 +1 µA
CLKOUT VOL Sinking 1mA 0.01 0.1 V
CLKOUT VOH Sourcing 1mA VVCC -
0.2V
VVCC -
0.01V V
CLKOUT Rise/Fall Time CLOAD = 100pF (Note 1) 40 ns
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS
(VVCC = 3.3V, Circuits of Figures 9–12, TA= -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC Input Voltage Range 2.35 5.50 V
VCC Input Voltage UVLO Rising or falling 1.95 2.3 V
VDD Input Voltage UVLO Rising or falling 3.90 4.45 V
Output Voltage 0.8 V
MAX1960/MAX1962 (measured at FB) 0.795 0.805
SEL = GND 1.492 1.508
SEL = REF 1.789 1.809
SEL not connected 2.482 2.517
DC Output Accuracy MAX1961/MAX1962
(FB = VDD),
measured at output
SEL = VDD 3.272 3.339
V
Positive Voltage-Margining Shift MAX1960/MAX1961 3.8 4.2 %
Negative Voltage-Margining Shift MAX1960/MAX1961 -3.8 -4.2 %
FB Input Bias Current -0.2 +0.2 µA
Feedback Transconductance 1 3 mS
COMP Discharge Resistance In shutdown 100 Ω
FSET/SYNC = GND 450 550
Switching Frequency FSET/SYNC = VCC 880 1120 kHz
SYNC Frequency Range 450 1200 kHz
Maximum Duty Cycle f = 1MHz 80 %
Maximum Duty Cycle f = 500kHz 90 %
Quiescent Supply Current 15 mA
Shutdown Supply Current 15 µA
2.7V ≤ VVCC ≤ 5.5V, ILOAD = 1mA to 50mA 4.75 5.25
2.35V ≤ VVCC ≤ 2.7V, ILOAD = 1mA to 35mA,
C1 = 4.7µF, C6 = 22µF 4.45 5.25
VDD Output Voltage
2.35V ≤ VVCC ≤ 3.6V with tripler, ILOAD = 1mA
to 50mA (circuit of Figure 12) 4.75 5.25
V
Reference Voltage (No Load) 1.267 1.291 V
Positive Current-Limit Threshold
(VCS - VOUT)MAX1962, VOUT = 2V 45 56 mV
Negative Current-Limit Threshold
(VOUT - VCS)MAX1962, VOUT = 2V 42 64 mV
CS Bias Current MAX1962, VCS = 3.3V 50 µA
OUT Bias Current MAX1961/MAX1962, VOUT = 3.3V 50 µA
Current-Limit Threshold (Positive
Direction, Fixed, VPGND - VLX)MAX1960/MAX1961, ILIM = VDD 58 90 mV
Current-Limit Threshold (Negative
Direction, Fixed, VLX - VPGND)MAX1960/MAX1961, ILIM = VDD 50 85 mV
MAX1960/MAX1961, RILIM = 160kΩ100 135
Current-Limit Threshold (Positive
Direction, Adjustable, VPGND - VLX)RILIM = 400kΩ250 306 mV
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(VVCC = 3.3V, Circuits of Figures 9–12, TA= -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER CONDITIONS MIN TYP MAX UNITS
MAX1960/MAX1961, RILIM = 160kΩ90 125
Current-Limit Threshold (Negative
Direction, Adjustable, VLX - VPGND)RILIM = 400kΩ245 296 mV
DH Gate-Driver On-Resistance VBST - VLX = 5V, pulling up or down 3.5 Ω
DL Gate-Driver On-Resistance (Pullup) DL high state 3.5 Ω
DL Gate-Driver On-Resistance (Pulldown) DL low state 1.6 Ω
Minimum high time 200
FSET/SYNC Pulse Width Minimum low time 200 ns
FSET/SYNC Rise/Fall Time 100 ns
CTL_, FSET/SYNC, EN Input High Voltage VVCC = 2.35V to 5.5V 2.0 V
CTL_, FSET/SYNC, EN Input Low Voltage VVCC = 2.35V to 5.5V 0.8 V
CTL_, FSET/SYNC, EN Input Current -1 +1 µA
CLKOUT VOL Sinking 1mA 0.1 V
CLKOUT VOH Sourcing 1mA VVCC -
0.2V V
CLKOUT Rise/Fall Time CLOAD = 100pF 40 ns
Note 1: Guaranteed by design.
Note 2: Specifications at -40°C are guaranteed by design, and not production tested.
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
6 _______________________________________________________________________________________
Typical Operating Characteristics
(Circuit of Figure 9, TA = +25°C, unless otherwise noted.)
EFFICIENCY vs. LOAD CURRENT WITH
15A 1MHz CIRCUIT, 3.3V INPUT
MAX1960 toc01
LOAD CURRENT (A)
EFFICIENCY (%)
101
60
70
80
90
100
50
0.1 100
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.5V
EFFICIENCY vs. LOAD CURRENT WITH
15A 1MHz CIRCUIT, 5V INPUT
MAX1960 toc02
LOAD CURRENT (A)
EFFICIENCY (%)
101
60
70
80
90
100
50
0.1 100
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.5V
VOUT = 1.8V
EFFICIENCY vs. LOAD CURRENT WITH
15A 500kHz CIRCUIT, 3.3V INPUT
MAX1960 toc03
LOAD CURRENT (A)
EFFICIENCY (%)
101
60
70
80
90
100
50
0.1 100
VOUT = 2.5V
VOUT = 1.5V
VOUT = 1.8V
EFFICIENCY vs. LOAD CURRENT WITH
15A 500kHz CIRCUIT, 5V INPUT
MAX1960 toc04
LOAD CURRENT (A)
EFFICIENCY (%)
101
60
70
80
90
100
50
0.1 100
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.5V
VOUT = 1.8V
OUTPUT VOLTAGE
vs. INPUT VOLTAGE, 1MHz
MAX1960 toc05
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
5.14.74.33.93.53.1
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
2.7 5.5
3.3V OUTPUT
2.5V OUTPUT
1.8V OUTPUT
1.5V OUTPUT
1.2V OUTPUT
15A LOAD
DROPOUT
OUTPUT VOLTAGE
vs. INPUT VOLTAGE, 500kHz
MAX1960 toc06
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
5.14.74.33.93.53.1
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
2.7 5.5
3.3V OUTPUT
2.5V OUTPUT
1.8V OUTPUT
1.5V OUTPUT
1.2V OUTPUT
15A LOAD
DROPOUT
FB REGULATION VOLTAGE
vs. LOAD CURRENT
MAX1960 toc07
LOAD CURRENT (A)
FB VOLTAGE (V)
15105
0.798
0.799
0.800
0.801
0.802
0.803
0.797
020
FREQUENCY
vs. INPUT VOLTAGE
MAX1960 toc08
INPUT VOLTAGE (V)
FREQUENCY (kHz)
5.04.53.5 4.0
500
600
700
800
1000
900
1100
1200
400
3.0 5.5
FSET/SYNC = VCC
FSET/SYNC = GND
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
_______________________________________________________________________________________
7
FREQUENCY vs. TEMPERATURE
MAX1960 toc09
TEMPERATURE (°C)
FREQUENCY (kHz)
603510-15
100
200
300
400
500
600
700
800
900
1000
1100
0
-40 85
FSET/SYNC = VCC
FSET/SYNC = GND
CHARGE-PUMP OUTPUT VOLTAGE
vs. CHARGE-PUMP LOAD CURRENT, 1MHz
MAX1960 toc10
CHARGE-PUMP LOAD CURRENT (mA)
CHARGE-PUMP OUTPUT VOLTAGE (V)
15010050
4.6
4.7
4.8
VIN = 3.3V
VIN = 2.5V
4.9
5.0
5.1
5.2
4.5
0 200
C1 = 0.47µF
C6 = 2.2µF
CHARGE-PUMP OUTPUT VOLTAGE
vs. CHARGE-PUMP LOAD CURRENT, 500kHz
MAX1960 toc11
CHARGE-PUMP LOAD CURRENT (mA)
CHARGE-PUMP OUTPUT VOLTAGE (V)
15010050
4.6
4.7
4.8
VIN = 3.3V
VIN = 2.5V
4.9
5.0
5.1
5.2
4.5
0200
C1 = 1µF
C6 = 4.7µF
TRIPLER CHARGE-PUMP OUTPUT VOLTAGE
vs. CHARGE-PUMP LOAD CURRENT, 1MHz
MAX1960 toc12
CHARGE-PUMP LOAD CURRENT (mA)
CHARGE-PUMP OUTPUT VOLTAGE (V)
302010
4.6
4.7
4.8
4.9
5.0
5.1
5.2
4.5
04050
VIN = 2.5V
CIRCUIT OF FIGURE 12
C10, C11, C12 = 0.47µF
C6 = 2.2µF
TRIPLER CHARGE-PUMP OUTPUT VOLTAGE
vs. CHARGE-PUMP LOAD CURRENT, 500kHz
MAX1960 toc13
CHARGE-PUMP LOAD CURRENT (mA)
CHARGE-PUMP OUTPUT VOLTAGE (V)
302010
4.6
4.7
4.8
4.9
5.0
5.1
5.2
4.5
04050
VIN = 2.5V
C10, C11, C12 = 1µF
C6 = 4.7µF
CIRCUIT OF FIGURE 12
MAX1960/MAX1961
CURRENT-LIMIT THRESHOLD
VOLTAGE vs. TEMPERATURE
MAX1960 toc14
TEMPERATURE
(
°C
)
CURRENT-LIMIT THRESHOLD VOLTAGE (mV)
603510-15
100
50
150
200
250
300
350
0
-40 85
RILIM = 390kΩ
ILIM = VDD
MAX1962
CURRENT-LIMIT THRESHOLD
VOLTAGE vs. TEMPERATURE
MAX1960 toc15
TEMPERATURE (°C)
CURRENT-LIMIT THRESHOLD VOLTAGE (mV)
603510-15
47.5
48.0
48.5
49.0
49.5
50.0
50.5
51.0
51.5
52.0
47.0
-40 85
Typical Operating Characteristics (continued)
(Circuit of Figure 9, TA = +25°C, unless otherwise noted.)
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
8 _______________________________________________________________________________________
7.5A TO 15A TO 7.5A LOAD TRANSIENT
MAX1960 toc16
20µs/div
VOUT 50mV/div
5A/div
ILOAD
VOLTAGE-MARGINING STEP RESPONSE
MAX1960 toc17
50µs/div
CTL2
IIN
CTL1 5V/div
5V/div
200mA/div
200mV/div
VOUT
CIRCUIT OF FIGURE 13
STARTUP/SHUTDOWN WAVEFORMS
MAX1960 toc18
1ms/div
IL
IIN 10A/div
10A/div
1V/div
VOUT
MAX1960/MAX1961
SHORT-CIRCUIT WAVEFORMS
MAX1960 toc19
50µs/div
IL
IIN
2V/div
20A/div
5A/div
VOUT CIRCUIT OF FIGURE 13
MAX1962
SHORT-CIRCUIT WAVEFORMS
MAX1960 toc20
50µs/div
IL
IIN 10A/div
10A/div
2V/div
VOUT
VIN = 5V
VOUT = 3.3V
SYNC TIMING WAVEFORMS
MAX1960 toc21
200ns/div
DH
MASTER
DL
MASTER
DL
SLAVE
DH
SLAVE
CLKOUT
MASTER/
SYNC
SLAVE
Typical Operating Characteristics (continued)
(Circuit of Figure 9, TA = +25°C, unless otherwise noted.)
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
_______________________________________________________________________________________ 9
Pin Description
PIN
MAX1960 MAX1961 MAX1962
NAME FUNCTION
1 1 1 CLKOUT
Clock Output. Connect to FSET/SYNC of a second converter to operate 180° out-of-
phase. CLKOUT swings from VCC to GND. CLKOUT is low in shutdown (see the
Operating Frequency and Synchronization section).
2 2 2 FSET/SYNC
Frequency Set and Synchronization. Connect to GND for 500kHz operation,
connect to VCC for 1MHz operation, or drive with clock signal to synchronize
(between 450kHz and 1200kHz).
3 3 — ILIM Current Limit. Connect a resistor from ILIM to GND to set the current-sense
threshold voltage. Connect ILIM to VDD to select the default threshold of 75mV.
—— 3 ENE nab l e. D r i ve hi g h for nor m al op er ati on. D r i ve l ow or connect to GN D for shutd ow n m od e.
— 4 4 SEL
Preset Output Voltage Select. Allows the output to be set to one of four preset
voltages (1.5V, 1.8V, 2.5V, and 3.3V). For the MAX1962, FB must be connected to
VDD if SEL is to be used (see the Setting the Output Voltage section).
4 — — N.C. No Connection. Not internally connected.
— 8 5 OUT Output. Connect to the output. Used to sense the output voltage for internal
feedback and current sense.
5 5 — CTL1
6 6 — CTL2
Control Pins. Controls voltage margining and shutdown. Connect both CTL1 and
CTL2 high for normal operation. Connect both CTL1 and CTL2 low for shutdown.
Connect CTL1 high and CTL2 low for +4% voltage margining. Connect CTL1 low
and CTL2 high for -4% voltage margining. If voltage margining is not to be used,
connect CTL1 and CTL2 together and use to enable/shutdown the device.
—— 6 CS
C ur r ent- S ense Inp ut. C onnect to the j uncti on of the cur r ent- sense r esi stor and the
i nd uctor . The M AX 1962 cur r ent- sense thr eshol d i s 50m V m easur ed fr om C S to O U T.
777AV
DD Filtered Supply from VDD. Connect a 1µF bypass capacitor. AVDD is forced to VCC
in shutdown. Do not apply an external load to AVDD.
8—8 FB
Feed b ack Inp ut. The feed b ack thr eshol d i s 0.8V . C onnect to the center of a r esi sti ve
vol tag e- d i vi d er fr om the outp ut to GN D to set the outp ut vol tag e to 0.8V or g r eater . On
the M AX 1962, connect FB to V
DD to sel ect p r eset outp ut vol tag es ( see S E L) .
9 9 9 COMP Compensation Pin. COMP is forced to GND in shutdown, UVLO, or thermal fault.
10 10 10 REF Reference Output. VREF = 1.28V. Bypass with a 0.22µF capacitor to GND.
11 11 11 GND Analog Ground. Connect to the PC board analog ground plane. Connect the PC
board analog ground plane and power ground planes with a single connection.
12 12 12 VDD
C har g e- P um p O utp ut. P r ovi d es r eg ul ated 5V to p ow er the IC and g ate d r i ver s.
Byp ass w i th a 4.7µF cer am i c cap aci tor for op er ati ng fr eq uenci es b etw een 450kH z
and 950kH z. Byp ass w i th a 2.2µF cer am i c cap aci tor for 1M H z op er ati on. V
DD i s
i nter nal l y for ced to V
CC i n shutd ow n. D o not ap p l y an exter nal l oad to V
DD.
13 13 13 DL Low-Side MOSFET Synchronous Rectifier Gate-Driver Output. DL is high in
shutdown.
14 14 14 PGND Power Ground. Connect to the PC board power ground plane.
MAX1960/MAX1961/MAX1962
Detailed Description
The MAX1960/MAX1961/MAX1962 are high-current,
high-efficiency voltage-mode step-down DC-DC con-
trollers that operate from 2.35V to 5.5V input and gener-
ate adjustable voltages down to 0.8V at up to 20A. An
on-chip charge pump generates a regulated 5V for dri-
ving a variety of external N-channel MOSFETs.
Constant frequency PWM operation and external syn-
chronization make these controllers suitable for telecom
and datacom applications. The operating frequency is
programmed externally to either 500kHz or 1MHz, or
from 450kHz to 1.2MHz with an external clock. A clock
output is provided to synchronize another converter for
180° out-of-phase operation.
A high closed-loop bandwidth provides excellent tran-
sient response for applications with dynamic loads.
Internal Charge Pump
An on-chip regulated charge pump develops 5V at
50mA (max) with input voltages as low as 2.35V. The
output of this charge pump provides power for the
internal circuitry, bias for the low-side driver (DL), and
the bias for the boost diode, which supplies the high-
side MOSFET gate driver (DH). The charge pump is
synchronized with the DL driver signal and operates at
1/2 the PWM frequency.
The external MOSFET gate charge is the dominant load
for the charge pump and is proportional to the PWM
switching frequency. The charge pump must supply
chip-operating current plus adequate gate current for
both MOSFETs at the selected operating frequency.
The required charge-pump output current is given by
the formula:
ITOTAL = IAVDD + fOSC (QG1 + QG2)
where IAVDD is the current supplied to the IC through
AVDD (typically 2mA), fOSC is the PWM switching
frequency, QG1 is the gate charge of the high-side
MOSFET, and QG2 is the gate charge of the low-side
MOSFET. The MOSFETs must be chosen such that
ITOTAL does not exceed 50mA. For example, with 1MHz
operation, QG1 + QG2 should be less than 48nC.
Voltage Margining and Shutdown
The voltage-margining feature on the MAX1960/
MAX1961 shifts the output voltage up or down by 4%.
This is useful for the automatic testing of systems at high
and low supply conditions to find potential hardware fail-
ures. CTL1 and CTL2 control voltage margining as out-
lined in Table 1.
A shutdown feature is included on all three parts, which
stops switching the output drivers and the charge
pump, reducing the supply current to less than 15µA.
For the MAX1962, drive EN high for normal operation,
or low for shutdown. For the MAX1960/MAX1961, drive
both CTL1 and CTL2 high for normal operation, or drive
CTL1 and CTL2 low for shutdown. For a simple
enable/shutdown function with no voltage margining,
connect CTL1 and CTL2 together and drive as one
input.
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
10 ______________________________________________________________________________________
Pin Description (continued)
PIN
MAX1960 MAX1961 MAX1962
NAME FUNCTION
15 15 15 C- Charge-Pump Flying Capacitor Negative Connection. Use a 0.47µF ceramic
capacitor at 1MHz, and 1µF between 450kHz and 950kHz.
16 16 16 C+ Charge-Pump Flying Capacitor Positive Connection. Use a 0.47µF ceramic
capacitor at 1MHz and 1µF between 450kHz and 950kHz.
17 17 17 VCC Input Supply to Charge Pump
18 18 18 BST Boost Capacitor Connection. Connect a 0.1µF ceramic capacitor from BST to LX.
19 19 19 DH High-Side MOSFET Gate-Driver Output. DH is low in shutdown.
20 20 20 LX Inductor Connection
CTL1 CTL2 FUNCTION
High High Normal operation
High Low +4% output-voltage shift
Low High -4% output-voltage shift
Low Low Shutdown
Table 1. Voltage Margining Truth Table
MOSFET Gate Drivers
The DH and DL drivers are designed to drive logic-level
N-channel MOSFETs to optimize system cost and effi-
ciency. MOSFETs with RDSON rated at VGS 4.5V are
recommended. An adaptive dead-time circuit monitors
the DL output and prevents the high-side MOSFET from
turning on until DL is fully off. There must be a low-resis-
tance, low-inductance path from the DL driver to the
MOSFET gate for the adaptive dead-time circuit to work
properly. Otherwise, the internal sense circuitry could
interpret the MOSFET gate as “off” while there is actually
still charge left on the gate. Use very short, wide traces
measuring no more than 20 squares (50mils to 100mils
wide if the MOSFET is 1in from the IC).
Undervoltage Lockout and Soft-Start
There are two undervoltage lockout (UVLO) circuits on
the MAX1960/MAX1961/MAX1962. The first UVLO cir-
cuit monitors VCC, which must be above 2.15V (typ) in
order for the charge pump to operate. The second
UVLO circuit monitors the output of the charge pump.
The charge-pump output, VDD, must be above 4.2V
(typ) in order for the PWM converter to operate. Both
UVLO circuits inhibit switching and force DL high and DH
low when either VCC or VDD are below their threshold.
When the monitored voltages are above their thresh-
olds, an internal soft-start timer ramps up the error-
amplifier reference voltage. The ramp occurs in eighty
10mV steps. Full output voltage is reached 1.28ms after
activation with a 1MHz operating frequency.
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
______________________________________________________________________________________ 11
S
R
Q
Q
CURRENT
SENSE
OSC
UVLO
SOFT-START
DAC
CHARGE
PUMP
OSC
VDD
REF
ILIM
(MAX1960/MAX1961)
FSET/SYNC
CLKOUT
COMP
FB
(MAX1960/MAX1962)
OUT
(MAX1961/MAX1962)
FEEDBACK
SELECT
VSEL
(MAX1961/MAX1962)
C+
C-
VDD
VCC
REF
AVDD
PGND
GND
DL
LX
DH
BST
SHUTDOWN
AND VOLTAGE
MARGINING
CTL1
(MAX1960/MAX1961)
CTL2
(MAX1960/MAX1961)
EN
(MAX1962)
PGND
LX
CS
(MAX1962)
OSC
OUT
MAX1960/
MAX1961/
MAX1962
COMP
ERROR
AMP
Figure 1. Functional Diagram
MAX1960/MAX1961/MAX1962
Operating Frequency and Synchronization
The MAX1960/MAX1961/MAX1962 operating frequency
is set externally to either 500kHz or 1MHz. For 500kHz
operation, connect FSET/SYNC to GND, or for 1MHz
operation, connect FSET/SYNC to VDD. Alternately, an
external clock from 450kHz to 1.2MHz can be applied
to SYNC.
A clock output (CLKOUT) that is 180° out-of-phase with
the internal clock is also provided. This allows a second
converter to be synchronized, and operate 180° out-of-
phase with the first. To do this, simply connect CLKOUT
of the first converter to FSET/SYNC of the second con-
verter. The first converter can be set internally to 500kHz
or 1MHz for this mode of operation. When the first con-
verter is synchronized to an external clock, CLKOUT is
the inverse of external clock. See the SYNC Timing
Waveform in the
Typical Operating Characteristics
.
Lossless Current Limit
(MAX1960/MAX1961)
To prevent damage in the case of excessive load cur-
rent or a short circuit, the MAX1960/MAX1961 use the
low-side MOSFET’s on-resistance (RDS(ON)) for current
sensing. The current is monitored during the on-time of
the low-side MOSFET. If the current-sense voltage
(VPGND - VLX) rises above the current-limit threshold for
more than 128 clock cycles, the controller turns off. The
controller remains off until the input voltage is removed
or the device is re-enabled with CTL1 and CTL2 (see
the
Setting the Current Limit
section).
Current-Sense Resistor (MAX1962)
The MAX1962 uses a standard current-sense resistor in
series with the inductor for a 10% accurate current-limit
measurement. The current-sense threshold is 50mV. This
provides accurate current sensing at all duty cycles with-
out relying on MOSFET on-resistance. CS connects to
the high-side (inductor side) of the current-sense resistor
and OUT connects to the low-side (output side) of the
current-sense resistor.
The current-sense resistor for the MAX1962 may also be
replaced with a series RC network across the inductor.
This method uses the parasitic resistance of the inductor
for current sensing. This method is less accurate than
using a current-sense resistor, but is lower cost and pro-
vides slightly higher efficiency. See the
Design
Procedure
section for instructions on using this method.
Dropout Performance
The MAX1960/MAX1961/MAX1962 enter dropout when
the input voltage is not sufficiently high to maintain output
regulation. As input voltage is lowered, the duty cycle
increases until it reaches its maximum value, where the
part enters dropout. With a switching frequency of
1MHz, the maximum duty cycle is about 83%. At
500kHz, the duty cycle can increase to about 92%,
resulting in a lower dropout voltage. The duty cycle is
dependent on the input voltage (VIN), the output volt-
age (VOUT), and the parasitic voltage drops in the
MOSFETs and the inductor (VDROP(N1), VDROP(N2),
VDROP(L)). Note that VDROP(L) includes the voltage
drop due to the inductor’s resistance, the drop across
the current-sense resistor (if used), and any other resis-
tive voltage drop from the LX switching node to the
point where the output voltage is sensed. The duty
cycle is found from:
Adaptive Dead Time
The MAX1960/MAX1961/MAX1962 DL and DH MOSFET
drivers have an adaptive dead-time circuit to prevent
shoot-through current caused by high- and low-side
MOSFET overlap. This allows a wide variety of MOSFETs
to be used without matching FET dynamic characteris-
tics. The DL driver will not go high until DH drives the
high-side MOSFET gate to within 1V of its source (LX).
The DH output will not go high until DL drives the low-side
MOSFET gate to within 1V of ground.
Design Procedure
Component selection is primarily dictated by the following
criteria:
Input voltage range. The maximum value
(VIN(MAX)) must accommodate the worst-case high
input voltage. The minimum value (VIN(MIN)) must
account for the lowest input voltage after drops due
to connectors, fuses, and selector switches are con-
sidered.
Maximum load current. There are two values to con-
sider: The
peak load current
(ILOAD(MAX)) determines
the instantaneous component stresses and filtering
requirements and is key in determining output capac-
itor requirements. ILOAD(MAX) also determines the
inductor saturation rating and the design of the cur-
rent-limit circuit. The
continuous load current
(ILOAD)
determines the thermal stresses and is key in deter-
mining input capacitor requirements, MOSFET
requirements, as well as those of other critical heat-
contributing components.
DVV
VV V
OUT DROP L
IN DROP N DROP N
=+()
() ( )
--
12
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
12 ______________________________________________________________________________________
Inductor operating point. This choice provides
tradeoffs between size, transient response, and effi-
ciency. Choosing higher inductance values results
in lower inductor ripple current, lower peak current,
lower switching losses, and, therefore, higher effi-
ciency at the cost of slower transient response and
larger size. Choosing lower inductance values
results in large ripple currents, smaller size, and
poorer efficiency, but have faster transient response.
Setting the Output Voltage
The MAX1961 has four output voltage presets selected
by SEL. Table 2 shows how each of the preset voltages
are selected. The MAX1962 also has four preset output
voltages, but also is adjustable down to 0.8V. To use the
preset voltages on the MAX1962, FB must be connected
to VDD. SEL then selects the output voltage as shown in
Table 2.
Both the MAX1960/MAX1962 feature an adjustable out-
put that can be set down to 0.8V. To set voltages greater
than 0.8V, Connect FB to a resistor-divider from the out-
put (Figures 9 and 11). Use a resistor up to 10kΩfor R2
and select R1 according to the following equation:
where the feedback threshold, VFB = 0.8V, and VOUT is
the output voltage.
Input Voltage Range
The MAX1960/MAX1961/MAX1962 have an input volt-
age range of 2.35V to 5.5V but cannot operate at both
extremes with one application circuit. The standard
charge-pump doubler application circuit operates with
an input range of 2.7V to 5.5V (Figures 9, 10, and 11).
In order to operate down to 2.35V, the charge pump
must be configured as a tripler. This circuit, however,
limits the maximum input voltage to 3.6V. The schematic
for the tripler charge pump is shown in Figure 2. Note
that the flying capacitor between C+ and C- has been
removed and C+ is not connected.
Inductor Selection
Determine an appropriate inductor value with the fol-
lowing equation:
The inductor current ripple, LIR, is the ratio of peak-to-
peak inductor ripple current to the average continuous
inductor current. An LIR between 20% and 40% pro-
vides a good compromise between efficiency and
economy. Choose a low-loss inductor having the lowest
possible DC resistance. Ferrite core type inductors are
often the best choice for performance. The inductor
saturation current rating must exceed IPEAK:
Setting the Current Limit
Lossless Current Limit (MAX1960/MAX1961)
The MAX1960/MAX1961 use the low-side MOSFET’s on-
resistance (RDS(ON)) for current sensing. This method of
current limit sets the maximum value of the inductor’s
“valley” current (Figure 3). If the inductor current is higher
than the valley current-limit setting at the end of the
clock period, the controller skips the DH pulse. When
the first current-limit event is detected, the controller initi-
II LIR I
PEAK LOAD MAX LOAD MAX
() ()
=+
⎛
⎝
⎜⎞
⎠
⎟×
2
LV VV
V f LIR I
OUT IN OUT
IN OSC LOAD MAX
=×
×××
()
-
RR V
V
OUT
FB
12 1=×
⎛
⎝
⎜⎞
⎠
⎟
-
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
______________________________________________________________________________________ 13
PRESET OUTPUT VOLTAGE SEL
1.5V GND
1.8V REF
2.5V No connection
3.3V VDD
Table 2. Preset Voltages—
MAX1961/MAX1962
MAX1960/
MAX1961/
MAX1962
C10
C11
C12
C6
D2 D3 D4 D5
R5
10Ω
C4
1µF
VCC
C-
C+
VDD
AVDD
C10, C11, C12
C6
500kHz
1µF
4.7µF
1MHz
0.47µF
2.2µF
Figure 2. Tripler Charge-Pump Configuration.
MAX1960/MAX1961/MAX1962
ates a 128 clock cycle counter. If the current limit is pre-
sent at the end of this count, the controller remains off
until the input voltage is removed and re-applied, or the
device is re-enabled with CTL1 and CTL2. The 128-cycle
counter is reset when four successive DH pulses are
observed, without activating the current limit.
At maximum load, the low excursion of inductor current,
IVALLEY(MAX), is:
The current-limit threshold (VCLT) is set by connecting a
resistor (RILIM) from ILIM to GND. The range for this
resistor is 100kΩto 400kΩ. Set current-limit threshold as
follows:
VCLT = RILIM ×0.714µA
Connecting ILIM to VDD sets the threshold to a default
value of 75mV.
To prevent the current limit from falsely triggering, VCLT
divided by the low-side MOSFET RDS(ON) must exceed
the maximum value of IVALLEY. The maximum value of
low-side MOSFET RDS(ON) should be used:
VCLT > RDS(ON)MAX x IVALLEY(MAX)
A limitation of sensing current across MOSFET on-resis-
tance is that the MOSFET on-resistance varies signifi-
cantly from MOSFET to MOSFET and over temperature.
Consequently, this current-sensing method may not be
suitable if a precise current limit is required. If better
accuracy is needed, use the MAX1962 with a current-
sense resistor.
Current-Sense Resistor (MAX1962)
The MAX1962 uses a current-sense resistor connected
from the inductor to the output with Kelvin sense connec-
tions. The current-sense voltage is measured from CS to
OUT, and has a fixed threshold of 50mV. The MAX1962
current limit is triggered when the peak voltage across
the current-sense resistor, IPEAK ×RSENSE, exceeds
50mV. Once current sense is triggered, the controller
does not turn off, but continues to operate at the current
limit. This method of current sensing is more precise due
to the accuracy of the current-sense resistor. The cost of
this precision is that it requires an extra component and
is slightly less efficient due to the loss in the current-
sense resistance.
Inductor Resistance Current Sense (MAX1962)
Alternately, the inductor resistance can be used to
sense current in place of a current-sense resistor. To
do this, connect a series RC network in parallel with the
inductor (Figure 4). Choose a resistor value less than
40Ωto avoid offsets due to CS input current. Calculate
the capacitor value from the formula C = 2L / (RL ×R).
The effective current-sense resistance (RSENSE) equals
RL. Current-sense accuracy then depends on the accu-
racy of the inductor resistance. Note that the current-
sense signal is delayed due to the RC filter time
constant. Consequently, inductor current may over-
shoot (by as much as 2x) when a fast short occurs.
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
14 ______________________________________________________________________________________
IPEAK
ILOAD
IVALLEY
INDUCTOR CURRENT
TIME
Figure 3. Inductor Current Waveform
DH
L
RL
R
R = 33Ω
0.22µH, 2.8mW,
ILIMIT = 18A
C
C = 4.7µF
LX
DL
CS
OUT
MAX1962
Figure 4. Using the Inductor Resistance as a Current-Sense
Resistor with the MAX1962
Output Capacitor Selection
The output filter capacitor must have low enough effective
series resistance (ESR) to meet output ripple and load
transient requirements. In addition, the capacitance value
must be high enough to absorb the inductor energy
during load steps.
In applications where the output is subject to large load
transients, low ESR is needed to prevent the output
from dipping too low (VDIP) during a load step:
In applications with less severe load steps, maximum
ESR may be governed by what is needed to maintain
acceptable output voltage ripple:
To satisfy both load step and ripple requirements,
select the lowest value from the above two equations.
The capacitor is usually selected by physical size, ESR,
and voltage rating, rather than by capacitance value.
With current tantalum, electrolytic, and polymer capaci-
tor technology, the bulk capacitance will also be suffi-
cient once the ESR requirement is satisfied.
When using low-capacity filter capacitors such as
ceramic, capacitor size is usually determined by the
capacitance needed to prevent voltage undershoot
and overshoot during load transients. The overshoot
voltage (VSOAR) is given by:
Generally, once enough capacitance is in place to meet
the overshoot requirement, undershoot at the rising load
edge is no longer a problem.
Input Capacitor Selection
The input capacitor (CIN) reduces the current peaks
drawn from the input supply and reduces noise injec-
tion. The source impedance to the input supply largely
determines the value of CIN. High source impedance
requires high input capacitance. The input capacitor
must meet the ripple current requirement (IRMS)
imposed by the switching currents.
The RMS input ripple current is given by:
For optimal circuit reliability, choose a capacitor that
has less than 10°C temperature rise at the peak ripple
current.
Compensation and Stability
Compensation with Ceramic Output Capacitors
The high switching frequency range of the
MAX1960/MAX1961/MAX1962 allows the use of ceramic
output capacitors. Since the ESR of ceramic capacitors
is very low typically, the frequency of the associated
transfer function zero is higher than the unity-gain
crossover frequency and the zero cannot be used to
compensate for the double pole created by the output
inductor and capacitor. The solution is Type 3 compen-
sation (Figure 5), which takes advantage of local feed-
back to create two zeros and three poles (Figure 6). The
frequency of the poles and zeros are described below:
Unity-gain crossover frequency:
fRC
ZESR ESR
=××
1
20
π
fRR C
Z2
1
2233
=×+×π ()
fRC
Z1
1
211
=××π
f
LC
LC =×
1
200
π
f
RCC
CC
P3
1
21
12
12
=
×× ×
+
π
fRC
P2
1
223
=××π
f
P1 0=
II VVV
V
RMS LOAD
OUT IN OUT
IN
=× ×()-
VLI
VC
SOAR PEAK
OUT OUT
=×
()
××
2
2
RV
I
ESR DIP
LOADSTEP MAX
≤
()
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
______________________________________________________________________________________ 15
MAX1960/MAX1961/MAX1962
where:
VIN(MAX) = Maximum input voltage
VRAMP = Oscillator ramp voltage = 0.85 x 106/fS,
where fS= switching frequency
LO= Output inductance
CO= Output capacitance
The goal is to place the two zeros below crossover and
the two poles above crossover so that crossover
occurs with a single-pole slope. The compensation pro-
cedure is as follows:
Select the crossover frequency such that:
f0 < fZESR and f0<1/5 fS
Select R1 such that:
where gmEA = 2mS.
Place the first zero before the double pole:
Place the third pole at half the switching frequency:
If C2 < 10pF, it can be omitted.
Place the second pole after the ESR zero:
If:
where gmEA = 2mS
increase R1 and recalculate C1, C2, and C3.
Place the second zero at the double-pole frequency:
Set the output voltage:
RV
VVRV V
FB
OUT FB FB
4308=×=
- ,.
RfC
R
LC
31
23
2≥××π -
RgmEA
21
<,
RfC
ZESR
21
23
≤××π
CfL C V
RV
RAMP
IN
32
1
00 0
≤×× × ×
×
π
CfR
S
21
205 1
≥×××π .
CfR
LC
11
2 0 75 1
≥×××π .
RgmEA
12
>>
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
16 ______________________________________________________________________________________
DH
VIN
LO
C0
R3
R4
R2
R1
C1C2
C3
VOUT
LX
DL
FB
COMP
MAX1960
Figure 5. Type 3 Compensation Network
fp1 fz1 fz2 fp2 fp3
GAIN (dB)
FREQUENCY
Figure 6. Transfer Function for Type 3 Compensation
Compensation with Electrolytic Output Capacitors
The MAX1960/MAX1961/MAX1962 use a voltage-mode
control scheme that regulates the output voltage by
comparing the error-amplifier output (COMP) with a
fixed internal ramp to produce the required duty cycle.
The inductor and output capacitor create a double pole
at the resonant frequency, which has gain drop of 40dB
per decade, and phase shift of 180°. The error amplifier
must compensate for this gain drop and phase shift in
order to achieve a stable high-bandwidth, closed-loop
system.
The basic regulator loop consists of a power modulator,
an output feedback divider and an error amplifier. The
power modulator has DC gain set by VIN/VRAMP, with a
double pole set by the inductor and output capacitor,
and a single zero set by the output capacitor (CO) and
its equivalent series resistance (ESR). Below are equa-
tions that define the power modulator:
The DC gain of the power modulator is:
where VRAMP = 0.85 × 106/ fS. The pole frequency due
to the inductor and output capacitor is:
The zero frequency due to the output capacitor’s ESR
is:
The output capacitor is usually comprised of several
same value capacitors connected in parallel. With n
capacitors in parallel, the output capacitance is:
The total ESR is:
The ESR zero (fZESR) for a parallel combination of
capacitors is the same as for an individual capacitor.
The feedback divider has a gain of GFB = VFB/VOUT,
where VFB is 0.8V.
The transconductance error amplifier has DC gain
GEA(dc) of 80dB. A dominant pole is set by the com-
pensation capacitor (CC), the amplifier output resis-
tance (RO), and the compensation resistor (RC):
A zero is set by the compensation resistor and the
compensation capacitor:
The total closed-loop gain must equal to unity at the
crossover frequency, where the crossover frequency
should be higher than fZESR, so that the -1 slope is
used to cross over at unity gain. Also, the crossover
frequency should be less than or equal to 1/5 the
switching frequency.
The loop-gain equation at the crossover frequency is:
where:
and:
The compensation resistor, RC, is calculated from:
where gmEA = 2mS.
Due to the under-damped (Q > 1) nature of the output
LC double pole, the error-amplifier compensation zero
should be approximately 0.2fPMOD to provide good
phase boost. CCis calculated from:
RV
gVG
COUT
mEA FB MOD fC
=××
()
GG f
ff
MOD f MOD DC PMOD
ESR C
C
() ( )
()
=×
×
2
GgR
EA f mEA C
C
()
=×
V
VGG
FB
OUT EA f MOD f
CC
() ()
×× =1
ff
f
ZESR C S
<≤
5
fCR
ZEA CC
=××
1
2π
fCRR
PEA CC
=××+
1
20
π ( )
RR
n
ESR ESR EACH
=()
CnC
O EACH
=×
fRC
ZESR ESR O
=××
1
2π
f
LC
PMOD
OO
=1
2π
GV
V
MOD DC IN
RAMP
()
=
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
______________________________________________________________________________________ 17
MAX1960/MAX1961/MAX1962
A small capacitor CF, can also be added from COMP to
GND to provide high-frequency decoupling. CFwill add
another high-frequency pole (fPHF) to the error-amplifier
response. This pole should be greater than 100 times
the error-amplifier zero frequency to have negligible
impact on the phase margin. This pole should also be
less than half the switching frequency for effective
decoupling:
100fZEA < fPHF < 0.5fS
Select a value for fPHF in the range given above, then
solve for CFusing the following equation:
Below is a numerical example to calculate compensa-
tion values:
VIN = 3.3V
VRAMP = 0.85V
VOUT = 1.8V
VFB = 0.8V
IOUT(max) = 15A
CO= 2 x 680µF = 1360µF
ESR = 0.008Ω/ 2 = 0.004Ω
LO= 0.22µH
gmEA = 2mS
fS= 1MHz
Choose the crossover frequency (fC) in the range fZESR
< fC < fS/5:
29.3kHz < fC< 200kHz
Select fC= 100kHz, this meets the criteria above, and the
bandwidth is high enough for good transient response.
The power modulator gain at fCis:
Choose R1= 8.06kΩ, then R2= 10kΩ(see the
Setting
the Output Voltage
section):
Select CC= 8200pF (nearest standard capacitor
value).
Select fPHF in the range 100fZEA < fPHF < 0.5fS.
184kHz < fPHF < 500kHz
Select fPHF
=
250kHz, then solve for CF:
Select the nearest standard capacitor value CF= 56pF.
Summary of feedback divider and compensation com-
ponents:
R1= 8.06kΩ
R2= 10kΩ
RC= 11kΩ
CC= 8200pF
CF= 56pF
Power MOSFET Selection
When selecting a MOSFET, essential parameters
include:
(1) Total gate charge (QG)
(2) Reverse transfer capacitance (CRSS)
(3) On-resistance (RDS(ON))
CR f k kHz pF
FC PHF
=×× =×× =
1
2
1
2 11 250 58
ππ Ω
CRf k pF
CC PMOD
=×× =××
=
5
2
5
2 11 9201 7863
ππ Ω
V
gVG
k
COUT
mEA FB MOD fC
=×× =××
=
.
. . .
()
18
0 002 0 8 0 102
11 Ω
GV
V
f
ff
kk
MOD fc IN
RAMP
PMOD
ZESR C
()
()
. ()
. .
=×
×
=× ×=
2
2
3
085
9201
29 3 100 0 102
ΩΩ
fCR
kHz
ZESR O ESR
=××
=×××
=
−
1
2
1
2 1360 10 0 004
29 3
6
π
π
.
.
f
LC
kHz
PMOD
OO
=××
=
××××
=
−−
1
2
1
2 0 22 10 1360 10
9 201
66
π
π
.
.
CRf
FC PHF
=××
1
2π
CRf
CC PMOD
=××
5
2π
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
18 ______________________________________________________________________________________
(4) Gate threshold voltage (VTH(MIN))
(5) Turn-on/turn-off times
(6) Turn-on/turn-off delays
At high switching rates, dynamic characteristics (para-
meters 1, 2, 5, and 6) that predict switching losses may
have more impact on efficiency than RDS(ON), which pre-
dicts DC losses. QGincludes all capacitance associated
with charging the gate, and best performance is
achieved with a low total gate charge. QG also helps
predict the current needed to drive the gate at the
selected operating frequency. This is very important
because the output current from the charge pump is
finite (50mA, max) and is used to drive the gates of the
MOSFETs as well as provide bias for the IC. RDS(ON) is
important as well, as it is used for current sensing in the
MAX1960/MAX1961. RDS(ON) also causes power dissi-
pation during the on-time of the MOSFET.
Choose QGto be as low as possible. Ensure that:
Choose RDS(ON) to provide the desired ILOAD(MAX) at
the desired current-limit threshold voltage (see the
Setting the Current Limit
section).
MOSFET RC Snubber Circuit
Fast-switching transitions can cause ringing due to res-
onating circuit parasitic inductance and capacitance at
the switching nodes. This high-frequency ringing
occurs at LX rising and falling transitions, and may
introduce current-sensing errors and generate EMI. To
dampen this ringing, a series RC snubber circuit can
be added across each MOSFET switch (Figure 8).
Typical values for the snubber components are CSNUB
= 4700pF and RSNUB = 1Ω, however, the ideal values
for snubber components will depend on circuit para-
sitics. Below is the procedure for selecting the compo-
nent values of the series RC snubber circuit:
1) Connect a scope probe to measure VLX to GND,
and observe the ringing frequency, fR.
2) Find the capacitor value (connected from LX to
GND) that reduces the ringing frequency by half.
3) The circuit parasitic capacitance, CPAR, at LX is then
equal to 1/3 of the value of the added capacitance
above.
QQ mA
f
GG
S
12
50
+≤
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
______________________________________________________________________________________ 19
FEEDBACK DIVIDER ERROR AMPLIFIER
V1
R1
R2 R3
C9
RS
L1
V2
RESR
COUT
RLOAD
0.8V
MODULATOR OUTPUT FILTER
Gm VIN/VRAMP
Figure 7. Open-Loop Transfer Model
MAX1960/MAX1961/MAX1962
4) The circuit parasitic inductance, LPAR, is calculated
by:
5) The resistor for critical dampening, RSNUB = 2πx
fRx LPAR. The resistor value can be adjusted up
or down to tailor the desired damping and the
peak voltage excursion.
6) The capacitor, CSNUB, should be at least 2 to 4
times the value of the CPAR to be effective.
7) The snubber circuit power loss is dissipated in the
resistor, PRSNUB, and can be calculated as:
where VIN is the input voltage, and fSis the
switching frequency. Choose RSNUB power rating
that exceeds the calculated power dissipation.
MOSFET Power Dissipation
Worst-case power dissipation occurs at duty factor
extremes. For the high-side MOSFET, the worst-case
power dissipation due to resistance occurs at minimum
input voltage (VIN(MIN)):
The following formula calculates switching losses for
the high-side MOSFET, but is only an approximation
and not a substitute for evaluation:
where VIN(MAX) is the maximum value of the input volt-
age, tFALL and tRISE are the fall and rise time of the
MOSFET, IL(PEAK) and IL(VALLEY) are the maximum
peak and valley inductor current, and fSis the PWM
switching frequency:
IL(PEAK) = IOUT(MAX) ×(1 + 0.5 ×LIR) and IL(VALLEY) =
IOUT(MAX) ×(1 - 0.5 ×LIR)
where LIR is the peak-to-peak inductor ripple current
divided by the load current.
The total power dissipation in the high-side MOSFET is
the sum of these two power losses:
PD(N1) = PD(N1RESISTIVE) + PD(N1SWITCHING)
For the low-side MOSFET, the worst-case power dissi-
pation occurs at maximum input voltage:
Applications Information
PC Board Layout Guidelines
A properly designed PC board layout is important in
any switching DC-DC converter circuit. If possible,
mount the MOSFETs, inductor, input/output capacitors,
and current-sense resistor on the top side. Connect the
ground for these devices close together on a power-
ground trace. Make all other ground connections to a
separate analog ground plane. Connect the analog
ground plane to power ground at a single point.
To help dissipate heat, place high-power components
(MOSFETs, inductor, and current-sense resistor) on a
large PC board area. Keep high-current traces short and
wide to reduce the resistance in these traces. Also make
the gate drive connections (DH and DL) short and wide,
measuring 10 to 20 squares (50mils to 100mils wide if the
MOSFET is 1in from the controller IC).
For the MAX1960/MAX1961, connect LX and PGND to
the low-side MOSFET using Kelvin sense connections.
For the MAX1962, connect CS and OUT to the current-
sense resistor using Kelvin sense connections.
Place the REF capacitor, the BST diode and capacitor,
and the charge-pump components as close as possible
to the IC. If the IC is far from the input capacitors, bypass
VCC to GND with a 0.1µF or greater ceramic capacitor
close to the VCC pin.
For an example PC board layout, see the MAX1960
evaluation kit.
PV
VIR
D N RESISTIVE OUT
IN MAX LOAD DS ON()
() ()
22
1=⎛
⎝
⎜⎞
⎠
⎟××-
P
ItI t
Vf
D N SWITCHING
L PEAK FALL L VALLEY RISE IN MAX S
()
() ( ) ()
1
2
=
×+ ×
()
××
PD V
VIR
N RESISTIVE OUT
IN MIN LOAD DS ON()
() ()
12
=××
PCVf
RSNUB SNUB IN S
() =××
2
L
fC
PAR
R PAR
=××
1
22
( ) π
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
20 ______________________________________________________________________________________
DL
LX
DH
PGND
MAX1960
N2
RSNUB
CSNUB
CSNUB
RSNUB
L1
N1
INPUT
Figure 8. RC Snubber Circuit
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
______________________________________________________________________________________ 21
PART APP. CIRCUIT 15A OUTPUT 1MHz 15A OUTPUT 500kHz
C1 1, 2, 3 0.47µF ceramic capacitor 1µF ceramic capacitor
C2 1, 2, 3, 4 5 × 10µF ceramic capacitors 5 × 10µF ceramic capacitors
C3 1, 2, 3, 4 2 x 680µF POSCAPs Sanyo 2R5TPD680M8 2 x 680µF POSCAPs Sanyo 2R5TPD680M8
C4 1, 2, 3, 4 1µF ceramic capacitor 1µF ceramic capacitor
C5 1, 2, 3, 4 0.1µF ceramic capacitor 0.1µF ceramic capacitor
C6 1, 2, 3, 4 2.2µF ceramic capacitor 4.7µF ceramic capacitor
C8 1, 2, 3, 4 0.22µF ceramic capacitor 0.22µF ceramic capacitor
C9 1, 2, 3, 4 (Table 4) (Table 5)
C10, C11, C12 4 0.47µF ceramic capacitors 1µF ceramic capacitors
C13, C14 1, 2, 3, 4 4700pF ceramic capacitors 4700pF ceramic capacitors
D1 1, 2, 3, 4 Schottky diode
Central CMSSH-3
Schottky diode
Central CMSSH-3
D2–D5 4 Schottky diodes
Central CMHSH5-2L
Schottky diodes
Central CMHSH5-2L
L1 1, 2, 3, 4 0.22µH, 1.7mΩ inductor
Sumida CDEP1040R2NC-50
0.45µH inductor
Sumida CDEP1040R4MC-50
N1 1, 2, 3, 4 N-channel MOSFET
International Rectifier IRLR7821
N-channel MOSFET
International Rectifier IRLR7821
N2 1, 2, 3, 4 N-channel MOSFET
International Rectifier IRLR7833
N-channel MOSFET
International Rectifier IRLR7833
R1 1, 3 Sets output voltage Sets output voltage
R2 1, 3 10kΩ ±1% resistor 10kΩ ±1% resistor
R3 1, 2, 3, 4 (Table 4) (Table 5)
R4 1, 2 390kΩ ±5% resistor 390kΩ ±5% resistor
R5 1, 2, 3, 4 10Ω ±5% resistor 10Ω ±5% resistor
R6 3, 4 1.5mΩ ±5%, 1W resistor
Panasonic ERJM1WTJ1M5U
1.5mΩ ±5%, 1W resistor
Panasonic ERJM1WTJ1M5U
R7, R8 1, 2, 3, 4 1Ω ±5% resistors 1Ω ±5% resistors
Table 3. Component List for Application Circuits
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
22 ______________________________________________________________________________________
VOUT = 3.3V VOUT = 2.5V VOUT = 1.8V VOUT = 1.5V
VIN R1 (kΩ) R3 (kΩ) C9 (µF) R1 (kΩ) R3 (kΩ) C9 (µF) R1 (kΩ) R3 (kΩ) C9 (µF) R1 (Ω) R3 (kΩ) C9 (µF)
5V 3.12 1.2 0.0068 2.13 9.1 0.01 1.24 6.8 0.01 876 5.5 0.01
3.3V — — — — — — 1.24 2.7 0.01 876 2.4 0.01
2.5V — — — — — — 1.24 3.9 0.01 876 3.3 0.01
Table 4. R1, R3, and C9 Component Values for 1MHz Operation
SUPPLIER PHONE WEBSITE
C entr al S em i cond uctor 631- 435- 1110 w w w .centr al sem i .com
International Rectifier 310-322-3331 www.irf.com
Kamaya 260-489-1533 www.kamaya.com
Murata 814-237-1431 www.murata.com
Panasonic 714-373-7939 www.panasonic.com
Sanyo 619-661-6835 www.sanyo.com
Sumida 847-956-0666 www.sumida.com
Taiyo Yuden 408-573-4150 www.t-yuden.com
Table 6. Component Suppliers
PART VOLTAGE
MARGINING
CURRENT
LIMIT
OUTPUT
VOLTAGE
MAX1960 Adjustable
MAX1961 ±4% FET VDS
Sensing 4 Presets
MAX1962 No ±10% with
RSENSE
4 Presets or
Adjustable
Selector Guide
VOUT = 3.3V VOUT = 2.5V VOUT = 1.8V VOUT = 1.5V
VIN R1 (kΩ) R3 (kΩ) C9 (µF) R1 (kΩ) R3 (kΩ) C9 (µF) R1 (kΩ) R3 (kΩ) C9 (µF) R1 (Ω) R3 (kΩ) C9 (µF)
5V 3.12 36 0.0033 2.13 27 0.0047 1.24 20 0.0068 876 16 0.0068
3.3V — — — 2.13 47 0.0033 1.24 30 0.0047 876 27 0.0047
2.5V — — — — — — 1.24 39 0.0033 876 33 0.0033
Table 5. R1, R3, and C9 Component Values for 500kHz Operation
MAX1960/MAX1961/MAX1962
DL
LX
DH
BST
VDD
VCC AVDD
C-C+
PGND
ILIM
FB
MAX1960
N2
R8
C14
C13
R7
L1
N1
D1
R5
C6
C4
C5
CTL1
INPUT
2.7V TO 5.5V
CTL2
COMP
REF
GND
FSET/SYNC
CLKOUT
R1
C3
OUTPUT
DOWN TO 0.8V
R2
R4
C1
C2
C8
C9
R3
N.C.
CLKOUT
Figure 9. Application Circuit 1—MAX1960 Adjustable Output Voltage
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
______________________________________________________________________________________ 23
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
24 ______________________________________________________________________________________
DL
LX
DH
BST
VDD
VCC AVDD
C-C+
PGND
ILIM
OUT
MAX1961
N2
R8
C14
C13
R7
L1
N1
D1
R5
C6
C4
C5
CTL1
INPUT
2.7V TO 5.5V
CTL2
COMP
REF
GND
FSET/SYNC
CLKOUT
C3
OUTPUT 2.5V
R4
C1
C2
C8
C9
R3
VSEL
CLKOUT
Figure 10. Application Circuit 2—MAX1961 Preset Output Voltage
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
______________________________________________________________________________________ 25
DL
LX
DH
BST
VDD
VCC AVDD
C-C+
PGND
CS
FB
MAX1962
N2
R8
C14
C13
R7
L1 R6
N1
D1
R5
C6
C4
C5
INPUT
2.7V TO 5.5V
EN
COMP
REF
GND
FSET/SYNC
CLKOUT
R1
C3
OUTPUT
DOWN TO 0.8V
R2
OUT
C1
C2
C8
C9
R3
VSEL
CLKOUT
Figure 11. Application Circuit 3—MAX1962 Adjustable Output Voltage
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
26 ______________________________________________________________________________________
DL
LX
DH
BST
VDD
VCC AVDD
C-C+
PGND
CS
FB VDD
MAX1962
N2
R8
C14
C13
R7
L1 R6
N1
D1
R5
C6
C4
D2
C5
INPUT
2.35V TO 3.6V
EN
COMP
REF
GND
FSET/SYNC
CLKOUT
D3
C3
OUTPUT 1.5V
OUT
C2
C8
C9
R3
VSEL
C11
C10
D4 D5
C12
CLKOUT
Figure 12. Application Circuit 4—MAX1962 Tripler Configuration, Preset Output
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
______________________________________________________________________________________ 27
DL
LX
DH
BST
VDD
VCC AVDD
C-C+
PGND
ILIM
FB
MAX1960
N2
R8
1Ω
C14
4700pF
C13
4700pF
R7
1Ω
L1
N1
D1
R5
10ΩC6
2.2µF
C4
1µF
C5
0.1µF
CTL1
INPUT
2.7V TO 5.5V
CTL2
COMP
REF
GND
FSET/SYNC
CLKOUT
N1 – IRLR7821
N2 – IRLR7833
R1
6.84kΩ
C3
4 x 47µF
TAIYO-YUDEN
JMK325BJ476MN
OUTPUT 2.5V, 15A
R2
3.22kΩ
R4
390kΩ
C1
0.47µF
C2
5 x 10µF
C8
0.22µF
C9
820pF
C10
33pF
R3
10kΩ
N.C.
CLKOUT C7
560pF
R9
680Ω
Figure 13. Application Circuit—Ceramic Output Capacitors with Type 3 Compensation
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
28 ______________________________________________________________________________________
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
LX
DH
BST
VCC
N.C. (SEL)
ILIM
FSET/SYNC
CLKOUT
TOP VIEW
C+
C-
PGND
DLFB (OUT)
AVDD
CTL2
CTL1
12
11
9
10
VDD
GNDREF
COMP
MAX1960
MAX1961
QSOP
( ) ARE FOR MAX1961.
Pin Configurations
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
LX
DH
BST
VCC
SEL
EN
FSET/SYNC
CLKOUT
TOP VIEW
C+
C-
PGND
DLFB
AVDD
CS
OUT
12
11
9
10
VDD
GNDREF
COMP
MAX1962
QSOP
Chip Information
TRANSISTOR COUNT: 4476
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package draw-
ings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
20 QSOP E20-1 21-0055
MAX1960/MAX1961/MAX1962
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM
Step-Down Controllers with Voltage Margining
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
29
© 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 1/03 Initial release —
1 6/09 Updated Electrical Characteristics and Compensation with Ceramic Output
Capacitors sections.4, 16