MAX5800/MAX5801/MAX5802
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DACs with Internal Reference and I2C Interface
General Description
The MAX5800/MAX5801/MAX5802 2-channel, low-power,
8-/10-/12-bit, voltage-output digital-to-analog converters
(DACs) include output buffers and an internal reference
that is selectable to be 2.048V, 2.500V, or 4.096V. The
MAX5800/MAX5801/MAX5802 accept a wide supply
voltage range of 2.7V to 5.5V with extremely low power
(1.5mW) consumption to accommodate most low-voltage
applications. A precision external reference input allows
rail-to-rail operation and presents a 100kI (typ) load to
an external reference.
The
MAX5800/MAX5801/MAX5802 have an I2C-compatible,
2-wire interface that operates at clock rates up to
400kHz. The DAC output is buffered and has a low sup-
ply current of less than 250FA per channel and a low
offset error of Q0.5mV (typ). On power-up, the MAX5800/
MAX5801/MAX5802 reset the DAC outputs to zero, pro-
viding additional safety for applications that drive valves
or other transducers which need to be off on power-up.
The internal reference is initially powered down to allow
use of an external reference. The MAX5800/MAX5801/
MAX5802 allow simultaneous output updates using soft-
ware LOAD commands.
A clear logic input (CLR) allows the contents of the CODE
and the DAC registers to be cleared asynchronously and
sets the DAC outputs to zero. The MAX5800/MAX5801/
MAX5802 are available in a small 10-pin µMAXM and an
ultra-small, 10-pin TDFN package and are specified over
the -40NC to +125NC temperature range.
Applications
Programmable Voltage and Current Sources
Gain and Offset Adjustment
Automatic Tuning and Optical Control
Power Amplifier Control and Biasing
Process Control and Servo Loops
Portable Instrumentation
Data Acquisition
Benefits and Features
S Two High-Accuracy DAC Channels
12-Bit Accuracy Without Adjustment
±1 LSB INL Buffered Voltage Output
Monotonic Over All Operating Conditions
Independent Mode Settings for Each DAC
S Three Precision Selectable Internal References
2.048V, 2.500V, or 4.096V
S Internal Output Buffer
Rail-to-Rail Operation with External Reference
4.5µs Settling Time
Outputs Directly Drive 2kI Loads
S Small 5mm x 3mm 10-Pin µMAX or Ultra-Small
3mm x 3mm 10-Pin TDFN Package
S Wide 2.7V to 5.5V Supply Range
S Separate 1.8V to 5.5V VDDIO Power-Supply Input
S Fast 400kHz I2C-Compatible, 2-Wire Serial
Interface
S Power-On-Reset to Zero-Scale DAC Output
S CLR For Asynchronous Control
S Three Software-Selectable Power-Down Output
Impedances
1kI, 100kI, or High Impedance
S Low 350µA Supply Current at 3V VDD
19-6461; Rev 2; 8/13
Ordering Information appears at end of data sheet.
Functional Diagram
EVALUATION KIT AVAILABLE
ADDR
SDA
SCL
OUTA
BUFFER
POR
VDD
GND
DAC CONTROL LOGIC POWER-DOWN
REF
OUTB
VDDIO
CLR
I2C SERIAL
INTERFACE
1kI100kI
CODE LOAD
CLEAR/
RESET
CLEAR/
RESET
CODE
REGISTER
DAC
LATCH
8-/10-/12-BIT
DAC
1 OF 2 DAC CHANNELS
INTERNAL REFERENCE/
EXTERNAL BUFFER
MAX5800
MAX5801
MAX5802
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
For related parts and recommended products to use with this part, refer to: www.maximintegrated.com/MAX5800.related
µMAX is a registered trademark of Maxim Integrated Products,
Inc.
2Maxim Integrated
MAX5800/MAX5801/MAX5802
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DACs with Internal Reference and I2C Interface
VDD, VDDIO to GND ................................................ -0.3V to +6V
OUT_, REF to GND .................................... -0.3V to the lower of
(VDD + 0.3V) and +6V
SCL, SDA, CLR to GND .......................................... -0.3V to +6V
ADDR to GND .............................................-0.3V to the lower of
(VDDIO + 0.3V) and +6V
Continuous Power Dissipation (TA = +70NC)
µMAX (derate at 8.8mW/NC above 70NC) ....................707mW
TDFN (derate at 24.4mW/NC above 70NC) ................1951mW
Maximum Continuous Current into Any Pin .................... Q50mA
Operating Temperature Range ........................ -40NC to +125NC
Storage Temperature Range ............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) .................................... +260NC
µMAX
Junction-to-Ambient Thermal Resistance (θJA) .......113NC/W
Junction-to-Case Thermal Resistance (θJC) ..............42NC/W
TDFN
Junction-to-Ambient Thermal Resistance (θJA) ..........41NC/W
Junction-to-Case Thermal Resistance (θJC) ................9NC/W
ABSOLUTE MAXIMUM RATINGS
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
ELECTRICAL CHARACTERISTICS
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC PERFORMANCE (Note 3)
Resolution and Monotonicity N
MAX5800 8
BitsMAX5801 10
MAX5802 12
Integral Nonlinearity (Note 4) INL
MAX5800 -0.25 Q0.05 +0.25
LSBMAX5801 -0.5 Q0.25 +0.5
MAX5802 -1 Q0. 5 +1
Differential Nonlinearity (Note 4) DNL
MAX5800 -0.25 Q0.05 +0.25
LSBMAX5801 -0.5 Q0.1 +0.5
MAX5802 -1 Q0.2 +1
Offset Error (Note 5) OE -5 Q0.5 +5 mV
Offset Error Drift Q10 FV/NC
Gain Error (Note 5) GE -1.0 Q0.1 +1.0 %FS
Gain Temperature Coefficient With respect to VREF Q3.0 ppm of
FS/NC
Zero-Scale Error 0 10 mV
Full-Scale Error With respect to VREF -0.5 +0.5 %FS
3Maxim Integrated
MAX5800/MAX5801/MAX5802
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DACs with Internal Reference and I2C Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DAC OUTPUT CHARACTERISTICS
Output Voltage Range (Note 6)
No load 0 VDD
V2kI load to GND 0 VDD -
0.2
2kI load to VDD 0.2 VDD
Load Regulation VOUT = VFS/2
VDD = 3V Q10%,
|IOUT| P 5mA 300
FV/mA
VDD = 5V Q10%,
|IOUT| P 10mA 300
DC Output Impedance VOUT = VFS/2
VDD = 3V Q10%,
|IOUT| P 5mA 0.3
I
VDD = 5V Q10%,
|IOUT| P 10mA 0.3
Maximum Capacitive Load
Handling CL500 pF
Resistive Load Handling RL2 kI
Short-Circuit Output Current VDD = 5.5V
Sourcing (output
shorted to GND) 30
mA
Sinking (output
shorted to VDD)50
DC Power-Supply Rejection VDD = 3V Q10% or 5V Q10% 100 FV/V
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate SR Positive and negative 1.0 V/Fs
Voltage-Output Settling Time
¼ scale to ¾ scale, to P 1 LSB, MAX5800 2.2
Fs¼ scale to ¾ scale, to P 1 LSB, MAX5801 2.6
¼ scale to ¾ scale, to P 1 LSB, MAX5802 4.5
DAC Glitch Impulse Major code transition 7 nV*s
Channel-to-Channel
Feedthrough (Note 7)
External reference 3.5 nV*s
Internal reference 3.3
Digital Feedthrough Code = 0, all digital inputs from 0V to
VDDIO 0.2 nV*s
Power-Up Time Startup calibration time (Note 8) 200 Fs
From power-down 50 Fs
4Maxim Integrated
MAX5800/MAX5801/MAX5802
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DACs with Internal Reference and I2C Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Voltage-Noise Density
(DAC Output at Midscale)
External reference f = 1kHz 90
nV/√Hz
f = 10kHz 82
2.048V internal
reference
f = 1kHz 112
f = 10kHz 102
2.5V internal
reference
f = 1kHz 125
f = 10kHz 110
4.096V internal
reference
f = 1kHz 160
f = 10kHz 145
Integrated Output Noise
(DAC Output at Midscale)
External reference
f = 0.1Hz to 10Hz 12
FVP-P
f = 0.1Hz to 10kHz 76
f = 0.1Hz to 300kHz 385
2.048V internal
reference
f = 0.1Hz to 10Hz 14
f = 0.1Hz to 10kHz 91
f = 0.1Hz to 300kHz 450
2.5V internal
reference
f = 0.1Hz to 10Hz 15
f = 0.1Hz to 10kHz 99
f = 0.1Hz to 300kHz 470
4.096V internal
reference
f = 0.1Hz to 10Hz 16
f = 0.1Hz to 10kHz 124
f = 0.1Hz to 300kHz 490
Output Voltage-Noise Density
(DAC Output at Full Scale)
External reference f = 1kHz 114
nV/√Hz
f = 10kHz 99
2.048V internal
reference
f = 1kHz 175
f = 10kHz 153
2.5V internal
reference
f = 1kHz 200
f = 10kHz 174
4.096V internal
reference
f = 1kHz 295
f = 10kHz 255
Integrated Output Noise
(DAC Output at Full Scale)
External reference
f = 0.1Hz to 10Hz 13
FVP-P
f = 0.1Hz to 10kHz 94
f = 0.1Hz to 300kHz 540
2.048V internal
reference
f = 0.1Hz to 10Hz 19
f = 0.1Hz to 10kHz 143
f = 0.1Hz to 300kHz 685
2.5V internal
reference
f = 0.1Hz to 10Hz 21
f = 0.1Hz to 10kHz 159
f = 0.1Hz to 300kHz 705
4.096V internal
reference
f = 0.1Hz to 10Hz 26
f = 0.1Hz to 10kHz 213
f = 0.1Hz to 300kHz 750
5Maxim Integrated
MAX5800/MAX5801/MAX5802
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DACs with Internal Reference and I2C Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
REFERENCE INPUT
Reference Input Range VREF 1.24 VDD V
Reference Input Current IREF VREF = VDD = 5.5V 55 74 FA
Reference Input Impedance RREF 75 100 kI
REFERENCE OUPUT
Reference Output Voltage VREF
VREF = 2.048V, TA = +25NC 2.043 2.048 2.053
VVREF = 2.5V, TA = +25NC 2.494 2.5 2.506
VREF = 4.096V, TA = +25NC 4.086 4.096 4.106
Reference Output Noise Density
VREF = 2.048V f = 1kHz 129
nV/√Hz
f = 10kHz 122
VREF = 2.500V f = 1kHz 158
f = 10kHz 151
VREF = 4.096V f = 1kHz 254
f = 10kHz 237
Integrated Reference Output
Noise
VREF = 2.048V
f = 0.1Hz to 10Hz 12
µVP-P
f = 0.1Hz to 10kHz 110
f = 0.1Hz to 300kHz 390
VREF = 2.500V
f = 0.1Hz to 10Hz 15
f = 0.1Hz to 10kHz 129
f = 0.1Hz to 300kHz 430
VREF = 4.096V
f = 0.1Hz to 10Hz 20
f = 0.1Hz to 10kHz 205
f = 0.1Hz to 300kHz 525
Reference Temperature
Coefficient (Note 9)
MAX5802A Q3.7 Q10 ppm/NC
MAX5800/MAX5801/MAX5802B Q10 Q25
Reference Drive Capacity External load 25 kI
Reference Capacitive Load 200 pF
Reference Load Regulation ISOURCE = 0 to 500FA 2 mV/mA
Reference Line Regulation 0.05 mV/V
POWER REQUIREMENTS
Supply Voltage VDD
VREF = 4.096V 4.5 5.5 V
All other options 2.7 5.5
I/O Supply Voltage VDDIO 1.8 5.5 V
Interface Supply Current
(Note 10) IDDIO 1FA
6Maxim Integrated
MAX5800/MAX5801/MAX5802
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DACs with Internal Reference and I2C Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Current (Note 10) IDD
Internal reference
VREF = 2.048V 0.55 0.75
mA
VREF = 2.5V 0.60 0.80
VREF = 4.096V 0.65 0.90
External reference VREF = 3V 0.40 0.60
VREF = 5V 0.55 0.75
Power-Down Mode Supply
Current IPD
Both DACs off, internal reference ON 140
FA
Both DACs off, internal reference OFF,
TA = -40NC to +85NC0.5 1
Both DACs off, internal reference OFF,
TA = +125NC1.2 2.5
DIGITAL INPUT CHARACTERISTICS (SCL, SDA, ADDR, CLR)
Input High Voltage VIH
2.2V < VDDIO < 5.5V 0.7 x
VDDIO V
1.8V < VDDIO < 2.2V 0.8 x
VDDIO V
Input Low Voltage VIL
2.2V < VDDIO < 5.5V 0.3 x
VDDIO V
1.8V < VDDIO < 2.2V 0.2 x
VDDIO
Hysteresis Voltage VH0.15 V
Input Leakage Current IIN VIN = 0V or VDDIO (Note 10) Q0.1 Q1FA
Input Capacitance (Note 10) CIN 3 pF
ADDR Pullup/Pulldown Strength RPU, RPD (Note 11) 30 50 90 kI
DIGITAL OUTPUT (SDA)
Output Low Voltage VOL ISINK = 3mA 0.2 V
I2C TIMING CHARACTERISTICS (SCL, SDA, CLR)
SCL Clock Frequency fSCL 400 kHz
Bus Free Time Between a STOP
and a START Condition tBUF 1.3 Fs
Hold Time Repeated for a
START Condition tHD;STA 0.6 Fs
SCL Pulse Width Low tLOW 1.3 Fs
SCL Pulse Width High tHIGH 0.6 Fs
Setup Time for Repeated START
Condition tSU;STA 0.6 Fs
Data Hold Time tHD;DAT 0 900 ns
Data Setup Time tSU;DAT 100 ns
7Maxim Integrated
MAX5800/MAX5801/MAX5802
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DACs with Internal Reference and I2C Interface
Figure 1. I2C Serial Interface Timing Diagram
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 2)
Note 2: Electrical specifications are production tested at TA = +25NC. Specifications over the entire operating temperature range
are guaranteed by design and characterization. Typical specifications are at TA = +25NC.
Note 3: DC Performance is tested without load.
Note 4: Linearity is tested with unloaded outputs to within 20mV of GND and VDD.
Note 5: Gain and offset calculated from measurements made with VREF = VDD at codes 30 and 4065 for MAX5802, codes 8 and
1016 for MAX5801, and codes 2 and 254 for MAX5800.
Note 6: Subject to zero and full-scale error limits and VREF settings.
Note 7: Measured with the DAC outputs at midscale with one channel transitioning 0 to full scale.
Note 8: On power-up, the device initiates an internal 200µs (typ) calibration sequence. All commands issued during this time will
be ignored.
Note 9: Guaranteed by design.
Note 10: Both channels active at VFS, unloaded. Static logic inputs with VIL = VGND and VIH = VDDIO.
Note 11: An unconnected condition on the ADDR pin is sensed via a resistive pullup and pulldown operation; for proper
operation, the ADDR pin should be tied to VDDIO, GND, or left unconnected with minimal capacitance.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SDA and SCL Receiving
Rise Time tr20 +
CB/10 300 ns
SDA and SCL Receiving
Fall Time tf20 +
CB/10 300 ns
SDA Transmitting Fall Time tf20 +
CB/10 250 ns
Setup Time for STOP Condition tSU;STO 0.6 Fs
Bus Capacitance Allowed CBVDD = 2.7V to 5.5V 10 400 pF
Pulse Width of Suppressed Spike tsp 50 ns
CLR Removal Time Prior to a
Recognized START tCLRSTA 100 ns
CLR Pulse Width Low tCLPW 20 ns
tSU;STO
tr
tSP
tHD;STA
tSU;STA
tf
tHIGH
tHD;DAT
tLOW
tCLPW
tCLRSTA
tHD;STA
tf
SS SrP
SDA
SCL
CLR
tSU;DAT
tr
tBUF
8Maxim Integrated
MAX5800/MAX5801/MAX5802
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DACs with Internal Reference and I2C Interface
Typical Operating Characteristics
(MAX5802, 12-bit performance, TA = +25°C, unless otherwise noted.)
DNL vs. CODE
MAX5800 toc04
CODE (LSB)
DNL (LSB)
358430722048 25601024 1536512
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0 4096
VDD = VREF = 5V
NO LOAD
INL AND DNL vs. SUPPLY VOLTAGE
MAX5800 toc05
SUPPLY VOLTAGE (V)
ERROR (LSB)
5.14.73.9 4.33.53.1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
MAX INL
VREF = 3V
1.0
-1.0
2.7 5.5
MAX DNL
MIN DNL
MIN INL
INL AND DNL vs. TEMPERATURE
MAX5800 toc06
TEMPERATURE (°C)
110
9565 80-10 5 20 35 50-25-40 125
ERROR (LSB)
-0.8
-0.6
-0.4
-0.2
0.2
0
0.4
0.6
0.8
1.0
-1.0
MAX INL
VDD = VREF = 3V
MAX DNL
MIN DNL
MIN INL
INL vs. CODE
MAX5800 toc01
CODE (LSB)
INL (LSB)
358430722048 25601024 1536512
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0 4096
VDD = VREF = 3V
NO LOAD
INL vs. CODE
MAX5800 toc02
CODE (LSB)
INL (LSB)
358430722048 25601024 1536512
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0 4096
VDD = VREF = 5V
NO LOAD
DNL vs. CODE
MAX5800 toc03
CODE (LSB)
DNL (LSB)
358430722048 25601024 1536512
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0 4096
VDD = VREF = 3V
NO LOAD
9Maxim Integrated
MAX5800/MAX5801/MAX5802
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DACs with Internal Reference and I2C Interface
Typical Operating Characteristics (continued)
(MAX5802, 12-bit performance, TA = +25°C, unless otherwise noted.)
OFFSET AND ZERO-SCALE ERROR
vs. SUPPLY VOLTAGE
MAX5800 toc07
SUPPLY VOLTAGE (V)
ERROR (mV)
5.14.73.9 4.33.53.1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
2.7 5.5
ZERO-SCALE ERROR
OFFSET ERROR
VREF = 2.5V (EXTERNAL)
NO LOAD
OFFSET AND ZERO-SCALE ERROR
vs. TEMPERATURE
MAX5800 toc08
TEMPERATURE (°C)
110
9565 80-10 5 20 35 50-25-40 125
ERROR (mV)
-0.8
-0.6
-0.4
-0.2
0.2
0
0.4
0.6
0.8
1.0
-1.0
VREF = 2.5V (EXTERNAL)
NO LOAD
OFFSET ERROR (VDD = 5V)
OFFSET ERROR (VDD = 3V)
ZERO-SCALE ERROR
FULL-SCALE ERROR AND GAIN ERROR
vs. SUPPLY VOLTAGE
MAX5800 toc09
SUPPLY VOLTAGE (V)
ERROR (%fs)
5.14.73.9 4.33.53.1
-0.016
-0.012
-0.008
-0.004
0
0.004
0.008
0.012
0.016
VREF = 2.5V (EXTERNAL)
NO LOAD
0.020
-0.020
2.7 5.5
FULL-SCALE ERROR
GAIN ERROR
FULL-SCALE ERROR AND GAIN ERROR
vs. TEMPERATURE
MAX5800 toc10
TEMPERATURE (°C)
110
9565 80-10 5 20 35 50-25-40 125
ERROR (%fsr)
-0.05
0
0.05
0.10
-0.10
VREF = 2.5V (EXTERNAL)
NO LOAD
GAIN ERROR (VDD = 3V)
GAIN ERROR (VDD = 5V)
FULL-SCALE ERROR
SUPPLY CURRENT vs. TEMPERATURE
MAX5800 toc11
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
11095-25 -10 5 35 50 6520 80
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.2
-40 125
OUT_ = FULL SCALE
NO LOAD
VREF (EXTERNAL) = VDD = 3V
VREF (EXTERNAL) = VDD = 5V
VREF (INTERNAL) = 4.096V,
VDD = 5V
VREF (INTERNAL) = 2.5V,
VDD = 5V
VREF (INTERNAL) = 2.048V,
VDD = 5V
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
\MAX5800 toc12
VDD (V)
SUPPLY CURRENT (mA)
5.24.73.2 3.7 4.2
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
0.30
2.7
VREF = 4.096V
(INTERNAL)
VREF = 2.500V
(INTERNAL)
VREF = 2.048V
(INTERNAL)
VREF = 2.5V
(EXTERNAL)
10Maxim Integrated
MAX5800/MAX5801/MAX5802
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DACs with Internal Reference and I2C Interface
Typical Operating Characteristics (continued)
(MAX5802, 12-bit performance, TA = +25°C, unless otherwise noted.)
POWER-DOWN MODE SUPPLY CURRENT
vs. TEMPERATURE
MAX5800 toc13
SUPPLY VOLTAGE (V)
5.13.5 3.9 4.3 4.73.12.7 5.5
POWER-DOWN SUPPLY CURRENT (µA)
0.4
0.8
1.6
1.2
0
POWER-DOWN MODE
ALL DACs
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
SUPPLY CURRENT vs. CODE
MAX5800 toc14
CODE (LSB)
SUPPLY CURRENT (mA)
358430722560204815361024512
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.10
0 4096
VDD = 5V
VREF = 4.096V
VDD = 5V
VREF = 2.500V
VDD = 5V
VREF = 5.0V
(EXTERNAL)
VDD = 3V
VREF = 3.0V
(EXTERNAL)
VDD = 5V
VREF = 2.048V
IREF (EXTERNAL) vs. CODE
MAX5800 toc15
CODE (LSB)
REFERENCE CURRENT (µA)
358430722560204815361024
10
20
30
40
50
60
0
5120 4096
VDD = VREF
NO LOAD
VREF = 5V
VREF = 3V
MAX5800 toc17
TRIGGER PULSE
5V/div
VOUT
0.5V/div
ZOOMED VOUT
1 LSB/div
4µs/div
4.3µs
SETTLING TO ±1 LSB
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
3/4 SCALE TO 1/4 SCALE
MAX5800 toc16
TRIGGER PULSE
5V/div
VOUT
0.5V/div
ZOOMED VOUT
1 LSB/div
4µs/div
SETTLING TO ±1 LSB
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
3.75µs
1/4 SCALE TO 3/4 SCALE
MAJOR CODE TRANSITION GLITCH ENERGY
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
MAX5800 toc18
VOUT
3.3mV/div
TRIGGER PULSE
5V/div
1 LSB CHANGE
(MIDCODE TRANSITION
FROM 0x7FF TO 0x800)
GLITCH ENERGY = 6.7nV*s
Maxim Integrated
MAX5800/MAX5801/MAX5802
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DACs with Internal Reference and I2C Interface
11
Typical Operating Characteristics (continued)
(MAX5802, 12-bit performance, TA = +25°C, unless otherwise noted.)
MAJOR CODE TRANSITION GLITCH ENERGY
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
MAX5800 toc19
VOUT
3.3mV/div
TRIGGER PULSE
5V/div
1 LSB CHANGE
(MIDCODE TRANSITION
FROM 0x800 TO 0x7FF)
GLITCH ENERGY = 6nV*s
2µs/div
VOUT vs. TIME TRANSIENT
EXITING POWER-DOWN
MAX5800 toc20
DAC OUTPUT
500mV/div
10µs/div
VSCL
5V/div
0V
0V
VDD = 5V, VREF = 2.5V
EXTERNAL
36TH EDGE
POWER-ON RESET TO 0V
MAX5800 toc21
VOUT
2V/div
20µs/div
VDD
2V/div
0V
0V
VDD = VREF = 5V
10kI LOAD TO VDD
CHANNEL-TO-CHANNEL FEEDTHROUGH
(VDD = VREF = 5V, TA = +25NC, NO LOAD)
MAX5800 toc23
5µs/div
NO LOAD
NO LOAD
TRIGGER PULSE
10V/div
STATIC DAC
1.25mV/div
TRANSITIONING
DAC
1V/div
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 1.8nV*s
CHANNEL-TO-CHANNEL FEEDTHROUGH
(VDD = VREF = 5V, TA = +25NC,
RL = 2kI, CL = 200pF)
MAX5800 toc22
4µs/div
TRIGGER PULSE
10V/div
TRANSITIONING
DAC
1V/div
RL = 2kI
NO LOAD STATIC DAC
1.25mV/div
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 3.5nV*s
CHANNEL-TO-CHANNEL FEEDTHROUGH
(VDD = 5V, VREF = 4.096V (INTERNAL),
TA = +25NC, RL = 2kI, CL = 200pF)
MAX5800 toc24
5µs/div
TRIGGER PULSE
10V/div
NO LOAD STATIC DAC
1.25mV/div
TRANSITIONING
DAC
1V/div
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 3.3nV*s
RL = 2kI
12Maxim Integrated
MAX5800/MAX5801/MAX5802
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DACs with Internal Reference and I2C Interface
Typical Operating Characteristics (continued)
(MAX5802, 12-bit performance, TA = +25°C, unless otherwise noted.)
MAX5800 toc25
TRIGGER PULSE
10V/div
TRANSITIONING DAC
1V/div
STATIC DAC
1.25mV/div
NO LOAD
NO LOAD
4µs/div
CHANNEL-TO-CHANNEL FEEDTHROUGH
(VDD = 5V, VREF = 4.096V (INTERNAL),
TA = +25NC, NO LOAD)
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 1.1nV*S
MAX5800 toc26
40ns/div
DIGITAL FEEDTHROUGH
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
VDD = 5V
VREF = 5V (EXTERNAL)
DACS AT MIDSCALE
VOUT
1.65mV/div
DIGITAL FEEDTHROUGH = 0.1nV·s·
OUTPUT LOAD REGULATION
MAX5800 toc27
IOUT (mA)
DVOUT (mV)
504020 30-10 0 10-20
-8
-6
-4
-2
0
2
4
6
8
10
-10
-30 60
VDD = VREF
VDD = 5V
VDD = 3V
HEADROOM AT RAILS
vs. OUTPUT CURRENT
MAX5800 toc29
IOUT (mA)
VOUT (V)
986 72 3 4 51
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
5.00
0
01
0
VDD = 5V, SOURCING
VDD = 3V, SOURCING
VDD = 3V AND 5V
SINKING
VDD = VREF
DAC = ZERO SCALE
VDD = VREF
DAC = FULL SCALE
OUTPUT CURRENT LIMITING
MAX5800 toc28
IOUT (mA)
DVOUT (mV)
605030 40-10 0 10 20-20
-400
-300
-200
-100
0
100
200
300
400
500
-500
-30 70
VDD = VREF
VDD = 5V
VDD = 3V
NOISE-VOLTAGE DENSITY
VS. FREQUENCY (DAC AT MIDSCALE)
MAX5800 toc30
FREQUENCY (Hz)
NOISE-VOLTAGE DENSITY (nV/√Hz)
10k1k
50
100
150
200
250
300
350
0
100 100k
VDD = 5V, VREF = 2.048V
(INTERNAL)
VDD = 5V, VREF = 4.5V
(EXTERNAL)
VDD = 5V, VREF = 4.096V
(INTERNAL)
VDD = 5V, VREF = 2.5V
(INTERNAL)
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
13Maxim Integrated
MAX5800/MAX5801/MAX5802
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DACs with Internal Reference and I2C Interface
Typical Operating Characteristics (continued)
(MAX5802, 12-bit performance, TA = +25°C, unless otherwise noted.)
0.1Hz TO 10Hz OUTPUT NOISE, EXTERNAL
REFERENCE (VDD = 5V, VREF = 4.5V)
MAX5800 toc31
2µV/div
MIDSCALE UNLOADED
VP-P = 12µV
4s/div
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (VDD = 5V, VREF = 2.048V)
MAX5800 toc32
2µV/div
MIDSCALE UNLOADED
VP-P = 13µV
4s/div
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (VDD = 5V, VREF = 2.5V)
MAX5800 toc33
2µV/div
MIDSCALE UNLOADED
VP-P = 15µV
4s/div
VREF DRIFT vs. TEMPERATURE
MAX5800 toc35
TEMPERATURE DRIFT (ppm/°C)
PERCENT OF POPULATION (%)
4.34.14.03.93.73.63.43.33.23.02.9
5
10
15
20
25
0
0.2 4.4
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (VDD = 5V, VREF = 4.096V)
MAX5800 toc34
2µV/div
MIDSCALE UNLOADED
VP-P = 16µV
4s/div
REFERENCE LOAD REGULATION
MAX5800 toc36
REFERENCE OUTPUT CURRENT (µA)
DVREF (mV)
45040035030025020015010050
-0.8
-0.6
-0.4
-0.2
0
-1.0
0 500
VDD = 5V
INTERNAL REFERENCE
VREF = 2.048V, 2.5V, AND 4.096V
SUPPLY CURRENT vs. INPUT LOGIC VOLTAGE
MAX5800 toc37
INPUT LOGIC VOLTAGE (V)
SUPPLY CURRENT (µA)
4321
200
400
600
800
1000
1200
1400
1600
1800
2000
0
05
VDDIO = 5V
VDDIO = 3V
VDDIO = 1.8V
14Maxim Integrated
MAX5800/MAX5801/MAX5802
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DACs with Internal Reference and I2C Interface
Pin Description
Pin Configurations
PIN NAME FUNCTION
1 REF Reference Voltage Input/Output
2 OUTA Buffered Channel A DAC Output
3 OUTB Buffered Channel B DAC Output
4 GND Ground
5 VDD Supply Voltage Input. Bypass VDD with at least a 0.1FF capacitor to GND.
6 ADDR I2C Interface Address Selection Bit
7 SCL I2C Interface Clock Input
8 SDA I2C Bidirectional Serial Data
9 VDDIO Digital Interface Power-Supply Input
10 CLR Active-Low Clear Input
— EP Exposed Pad (TDFN Only). Connect to ground.
TOP VIEW
1
3
4
10
8
7
CLR
SDA
SCL
MAX5800
MAX5801
MAX5802
29VDDIO
5
+
6ADDR
REF
OUTB
GND
OUTA
VDD EP
TDFN
1
2
3
4
5
10
9
8
7
6
VDDIO
SDA
SCLGND
OUTB
OUTA
REF
MAX5800
MAX5801
MAX5802
µMAX
ADDRVDD
CLR
+
15Maxim Integrated
MAX5800/MAX5801/MAX5802
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DACs with Internal Reference and I2C Interface
Detailed Description
The MAX5800/MAX5801/MAX5802 are 2-channel, low-
power, 8-/10-/12-bit buffered voltage-output DACs. The
2.7V to 5.5V wide supply voltage range and low-power
consumption accommodates most low-power and low-
voltage applications. The devices present a 100kI load
to the external reference. The internal output buffers
allow rail-to-rail operation. An internal voltage reference
is available with software selectable options of 2.048V,
2.5V, or 4.096V. The devices feature a fast 400kHz I2C-
compatible interface. The MAX5800/MAX5801/MAX5802
include a serial-in/parallel-out shift register, internal
CODE and DAC registers, a power-on-reset (POR) cir-
cuit to initialize the DAC outputs to code zero, and con-
trol logic. CLR is available to asynchronously clear the
device independent of the serial interface.
DAC Outputs (OUT_)
The MAX5800/MAX5801/MAX5802 include internal buf-
fers on both DAC outputs. The internal output buffers
provide improved load regulation for the DAC outputs.
The output buffers slew at 1V/Fs (typ) and drive up to
2kI in parallel with 500pF. The analog supply voltage
(VDD) determines the maximum output voltage range
of the devices as VDD powers the output buffer. Under
no-load conditions, the output buffers drive from GND to
VDD, subject to offset and gain errors. With a 2kω load to
GND, the output buffers drive from GND to within 200mV
of VDD. With a 2kω load to VDD, the output buffers drive
from VDD to within 200mV of GND.
The DAC ideal output voltage is defined by:
OUT REF N
D
VV
2
= ×
where D = code loaded into the DAC register, VREF =
reference voltage, N = resolution.
Internal Register Structure
The user interface is separated from the DAC logic to
minimize digital feedthrough. Within the serial interface
is an input shift register, the contents of which can be
routed to control registers, individual, or multiple DACs
as determined by the user command.
Within each DAC channel there is a CODE register
followed by a DAC latch register (see the Detailed
Functional Diagram). The contents of the CODE register
hold pending DAC output settings which can later be
loaded into the DAC registers. The CODE register can be
updated using both CODE and CODE_LOAD user com-
mands. The contents of the DAC register hold the current
DAC output settings. The DAC register can be updated
directly from the serial interface using the CODE_LOAD
commands or can upload the current contents of the
CODE register using LOAD commands.
The contents of both CODE and DAC registers are main-
tained during power-down states, so that when the DACs
are powered on, they return to their previously stored
output settings. Any CODE or LOAD commands issued
during power-down states continue to update the register
contents. SW_CLEAR and SW_RESET commands reset
the contents of all CODE and DAC registers to their zero-
scale defaults.
Internal Reference
The MAX5800/MAX5801/MAX5802 include an internal
precision voltage reference that is software selectable
to be 2.048V, 2.500V, or 4.096V. When an internal refer-
ence is selected, that voltage is available on the REF
pin for other external circuitry (see the Typical Operating
Circuits) and can drive a 25kI load.
External Reference
The external reference input has a typical input
impedance of 100kI and accepts an input voltage
from +1.24V to VDD. Connect an external voltage
supply between REF and GND to apply an exter-
nal reference. The MAX5800/MAX5801/MAX5802
power up and reset to external reference mode. Visit
www.maximintegrated.com/products/references for a
list of available external voltage-reference devices.
Clear Input (CLR)
The MAX5800/MAX5801/MAX5802 feature an asynchro-
nous active-low CLR logic input that simultaneously sets
both DAC outputs to zero. Driving CLR low clears the
contents of both the CODE and DAC registers and also
aborts the on-going I2C command. To allow a new I2C
command, drive CLR high, satisfying the tCLRSTA timing
requirement.
Interface Power Supply (VDDIO)
The MAX5800/MAX5801/MAX5802 feature a separate
supply pin (VDDIO) for the digital interface (1.8V to 5.5V).
Connect VDDIO to the I/O supply of the host processor.
16Maxim Integrated
MAX5800/MAX5801/MAX5802
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DACs with Internal Reference and I2C Interface
I2C Serial Interface
The MAX5800/MAX5801/MAX5802 feature an I2C-/
SMBusK-compatible, 2-wire serial interface consisting of
a serial data line (SDA) and a serial clock line (SCL). SDA
and SCL enable communication between the MAX5800/
MAX5801/MAX5802 and the master at clock rates up
to 400kHz. Figure 1 shows the 2-wire interface timing
diagram. The master generates SCL and initiates data
transfer on the bus. The master device writes data to the
MAX5800/MAX5801/MAX5802 by transmitting the proper
slave address followed by the command byte and then
the data word. Each transmit sequence is framed by a
START (S) or Repeated START (Sr) condition and a STOP
(P) condition. Each word transmitted to the MAX5800/
MAX5801/MAX5802 is 8 bits long and is followed by an
acknowledge clock pulse. A master reading data from
the MAX5800/MAX5801/MAX5802 must transmit the
proper slave address followed by a series of nine SCL
pulses for each byte of data requested. The MAX5800/
MAX5801/MAX5802 transmit data on SDA in sync with
the master-generated SCL pulses. The master acknowl-
edges receipt of each byte of data. Each read sequence
is framed by a START or Repeated START condition, a
not acknowledge, and a STOP condition. SDA operates
as both an input and an open-drain output. A pullup
resistor, typically 4.7kI is required on SDA. SCL oper-
ates only as an input. A pullup resistor, typically 4.7kI, is
required on SCL if there are multiple masters on the bus,
or if the single master has an open-drain SCL output.
Series resistors in line with SDA and SCL are optional.
Series resistors protect the digital inputs of the MAX5800/
MAX5801/MAX5802 from high voltage spikes on the bus
lines and minimize crosstalk and undershoot of the bus
signals. The MAX5800/MAX5801/MAX5802 can accom-
modate bus voltages higher than VDDIO up to a limit of
5.5V; bus voltages lower than VDDIO are not recommend-
ed and may result in significantly increased interface cur-
rents. The MAX5800/MAX5801/MAX5802 digital inputs
are double buffered. Depending on the command issued
through the serial interface, the CODE register(s) can be
loaded without affecting the DAC register(s) using the
write command. To update the DAC registers, use the
software LOAD command.
I2C START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A mas-
ter initiates communication by issuing a START condition.
A START condition is a high-to-low transition on SDA with
SCL high. A STOP condition is a low-to-high transition
on SDA while SCL is high (Figure 2). A START condition
from the master signals the beginning of a transmission
to the MAX5800/MAX5801/MAX5802. The master termi-
nates transmission and frees the bus, by issuing a STOP
condition. The bus remains active if a Repeated START
condition is generated instead of a STOP condition.
I2C Early STOP and
Repeated START Conditions
The MAX5800/MAX5801/MAX5802 recognize a STOP
condition at any point during data transmission except
if the STOP condition occurs in the same high pulse as
a START condition. Transmissions ending in an early
STOP condition will not impact the internal device set-
tings. If the STOP occurs during a readback byte, the
transmission is terminated and a later read mode request
will begin transfer of the requested register data from
the beginning (this applies to combined format I2C read
mode transfers only, interface verification mode transfers
will be corrupted). See Figure 2.
Figure 2. I2C START, Repeated START, and STOP Conditions
SMBus is a trademark of Intel Corp.
Figure 2
SCL
SDA
SS
rP
VALID START, REPEATED START, AND STOP PULSES
PS PSPPS
INVALID START/STOP PULSE PAIRINGS -ALL WILL BE RECOGNIZED AS STARTS
17Maxim Integrated
MAX5800/MAX5801/MAX5802
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DACs with Internal Reference and I2C Interface
I2C Slave Address
The slave address is defined as the seven most sig-
nificant bits (MSBs) followed by the R/W bit. See Figure
4. The five most significant bits are 00011 with the 2
LSBs determined by ADDR as shown in Table 1. Setting
the R/W bit to 1 configures the MAX5800/MAX5801/
MAX5802 for read mode. Setting the R/W bit to 0 config-
ures the MAX5800/MAX5801/MAX5802 for write mode.
The slave address is the first byte of information sent
to the MAX5800/MAX5801/MAX5802 after the START
condition.
The MAX5800/MAX5801/MAX5802 have the ability to
detect an unconnected state on the ADDR input for
additional address flexibility; if leaving the ADDR input
unconnected, be certain to minimize all loading on the
pin (i.e. provide a landing for the pin, but do not allow
any board traces).
I2C Broadcast Address
A broadcast address is provided for the purpose of
updating or configuring all MAX5800/MAX5801/MAX5802
devices on a given I2C bus. All MAX5800/MAX5801/
MAX5802 devices acknowledge and respond to the
broadcast device address 00010000. The devices will
respond to the broadcast address, regardless of the
state of the address pins. The broadcast mode is intend-
ed for use in write mode only (as indicated by R/W = 0 in
the address given).
I2C Acknowledge
In write mode, the acknowledge bit (ACK) is a clocked 9th
bit that the MAX5800/MAX5801/MAX5802 use to hand-
shake receipt of each byte of data as shown in Figure 3.
The MAX5800/MAX5801/MAX5802 pull down SDA during
the entire master-generated 9th clock pulse if the previous
byte is successfully received. Monitoring ACK allows for
detection of unsuccessful data transfers. An unsuccessful
data transfer occurs if a receiving device is busy or if a
system fault has occurred. In the event of an unsuccess-
ful data transfer, the bus master will retry communication.
Figure 3. I2C Acknowledge
Table 1. I2C Slave Address LSBs
Figure 4. I2C Single Register Write Sequence
A[6:2] = 00011
ADDR A1 A0
VDDIO 0 0
N.C. 1 0
GND 1 1
1
SCL
START
CONDITION
SDA
29
CLOCK PULSE
FOR
ACKNOWLEDGMENT
ACKNOWLEDGE
NOT ACKNOWLEDGE
SCL
AW 20 19 18 17 A16 15 14 13 12 11 10 9A8
START
SDA
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS
WRITE COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
WRITE DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
WRITE DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
212223
STOP
7 6 5 4 3 2 1 A0
ACK. GENERATED BY MAX5800/MAX5801/MAX5802
COMMAND EXECUTED
11 A1 A0000
A
18Maxim Integrated
MAX5800/MAX5801/MAX5802
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DACs with Internal Reference and I2C Interface
In read mode, the master pulls down SDA during the
9th clock cycle to acknowledge receipt of data from the
MAX5800/MAX5801/MAX5802. An acknowledge is sent
by the master after each read byte to allow data transfer
to continue. A not-acknowledge is sent when the master
reads the final byte of data from the MAX5800/MAX5801/
MAX5802, followed by a STOP condition.
I2C Command Byte and Data Bytes
A command byte follows the slave address. A command
byte is typically followed by two data bytes unless it is
the last byte in the transmission. If data bytes follow the
command byte, the command byte indicates the address
of the register that is to receive the following two data
bytes. The data bytes are stored in a temporary register
and then transferred to the appropriate register during
the ACK periods between bytes. This avoids any glitch-
ing or digital feedthrough to the DACs while the interface
is active.
I2C Write Operations
A master device communicates with the MAX5800/
MAX5801/MAX5802 by transmitting the proper slave
address followed by command and data words. Each
transmit sequence is framed by a START or Repeated
START condition and a STOP condition as described
above. Each word is 8 bits long and is always followed by an
acknowledge clock (ACK) pulse as shown in the Figure 4
and Figure 5. The first byte contains the address of the
MAX5800/MAX5801/MAX5802 with R/W = 0 to indicate
a write. The second byte contains the register (or com-
mand) to be written and the third and fourth bytes contain
the data to be written. By repeating the register address
plus data pairs (Byte #2 through Byte #4 in Figure 4
and Figure 5), the user can perform multiple register
writes using a single I2C command sequence. There is
no limit as to how many registers the user can write with
a single command. The MAX5800/MAX5801/MAX5802
support this capability for all user-accessible write mode
commands.
Combined Format I2C Readback Operations
Each readback sequence is framed by a START or
Repeated START condition and a STOP condition. Each
word is 8 bits long and is followed by an acknowledge
clock pulse as shown in Figure 6. The first byte contains
the address of the MAX5800/MAX5801/MAX5802 with
R/W = 0 to indicate a write. The second byte contains
the register that is to be read back. There is a Repeated
START condition, followed by the device address with
R/W = 1 to indicate a read and an acknowledge clock.
The master has control of the SCL line but the MAX5800/
MAX5801/MAX5802 take over the SDA line. The final two
bytes in the frame contain the register data readback
followed by a STOP condition. If additional bytes beyond
those required to readback the requested data are pro-
vided, the MAX5800/MAX5801/MAX5802 will continue to
readback ones.
Readback of individual CODE registers is supported for
the CODE command (B[23:20] = 0000). For this com-
mand, which supports a DAC address, the requested
Figure 5. Multiple Register Write Sequence (Standard I2C Protocol)
SCL
AW 20 19 18 17 A
16 15 14 13 12 11 10 9A8
START
SDA
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS
WRITE COMMAND1
BYTE #2: COMMAND1 BYTE
(B[23:16])
WRITE DATA1
BYTE #3: DATA1 HIGH BYTE
(B[15:8])
21
0 0 0 1 1 A1 A0 2223
STOP
76 5 4 3 2 1A0
WRITE DATA1
BYTE #4: DATA1 LOW BYTE
(B[7:0])
20 19 18 17 A16 15 14 13 12 11 10 9A8212223 7 6 5 4 3 2 1A0
ADDITIONAL COMMAND AND
DATA PAIRS (3 BYTE BLOCKS)
COMMAND1
EXECUTED
COMMANDn
EXECUTED
BYTE #5: COMMANDn BYTE
(B[23:16])
BYTE #6: DATAn HIGH BYTE
(B[15:8])
BYTE #7: DATAn LOW BYTE
(B[7:0])
ACK. GENERATED BY MAX5800/MAX5801/MAX5802
A
19Maxim Integrated
MAX5800/MAX5801/MAX5802
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DACs with Internal Reference and I2C Interface
Figure 6. Standard I2C Register Read Sequence
channel CODE register content will be returned; if both
DACs are selected, CODEA content will be returned.
Readback of individual DAC registers is supported for
all LOAD commands (B[23:20] = 0001, 0010, or 0011).
For these commands, which support a DAC address, the
requested DAC register content will be returned. If both
DACs are selected, DACA content will be returned.
Modified readback of the POWER register is supported
for the POWER command (B[23:20] = 0100). The power
status of each DAC is reported in locations B[1:0], with a
1 indicating the DAC is powered down and a 0 indicating
the DAC is operational (see Table 2).
Readback of all other registers is not directly supported.
All requests to read unsupported registers reads back
the device’s reference status and the device ID and revi-
sion information in the format as shown in Table 2.
Interface Verification I2C
Readback Operations
While the MAX5800/MAX5801/MAX5802 support stan-
dard I2C readback of selected registers, it is also
capable of functioning in an interface verification mode.
This mode is accessed any time a readback operation
follows an executed write mode command. In this mode,
the last executed three-byte command is read back in its
entirety. This behavior allows verification of the interface.
Sample command sequences are shown in Figure 7.
The first command transfer is given in write mode with
R/W = 0 and must be run to completion to qualify for
interface verification readback. There is now a STOP/
START pair or Repeated START condition required, fol-
lowed by the readback transfer with R/W = 1 to indicate
a read and an acknowledge clock from the MAX5800/
MAX5801/MAX5802. The master still has control of the
Table 2. Standard I2C User Readback Data
COMMAND BYTE (REQUEST) READBACK DATA HIGH BYTE READBACK DATA LOW BYTE
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0 0 0 0 DAC selection CODEn[11:4] CODEn[3:0] 0 0 0 0
0 0 0 1 DAC selection DACn[11:4] DACn[3:0] 0 0 0 0
0 0 1 0 DAC selection DACn[11:4] DACn[3:0] 0 0 0 0
0 0 1 1 DAC selection DACn[11:4] DACn[3:0] 0 0 0 0
0 1 0 0 0 0 X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWB PWA
1 0 0 0 0 0 0 0 CODEA[11:4] CODEA[3:0] 0 0 0 0
1 0 0 0 0 0 0 1 DACA[11:4] DACA[3:0] 0 0 0 0
1 0 1 0 0 0 1 0 DACA[11:4] DACA[3:0] 0 0 0 0
1 0 1 1 0 0 1 1 DACA[11:4] DACA[3:0] 0 0 0 0
Any other command 1001 1000 000 REV_ID[2:0]
(011)
REF MODE
RF[1:0]
READ DATA
BYTE #4: DATA 1 HIGH
BYTE (B[15:8])
READ DATA
BYTE #5: DATA 1 LOW
BYTE (B[7:0])
REPEATED
START
READ ADDRESS
BYTE #3: I2C SLAVE
ADDRESS
WRITE ADDRESS
BYTE #1: I2C SLAVE
ADDRESS
WRITE COMMAND 1
BYTE #2: COMMAND 1
BYTE
ACK. GENERATED BY MAX5800/MAX5801/MAX5802 ACK. GENERATED BY I2C MASTER
A
START STOP
SCL
SDA 0001 1A1A0W A
A
AN NN 00011A1 A0 RADDDDDDDD DDDDDDDD
~A
ANNNNN
20Maxim Integrated
MAX5800/MAX5801/MAX5802
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DACs with Internal Reference and I2C Interface
Figure 7. Interface Verification I2C Register Read Sequences
SCL
AW 20 19 18 17 A16 15 14 13 12 11 10 9 A8
SDA 0 0 0 1 1 A1 A0 2223 7 6 54 3 2 1 A0
R~A
POINTER UPDATED
(QUALIFIES FOR COMBINED READ BACK)
COMMAND EXECUTED
(QUALIFIES FOR INTERFACE READ BACK)
SCL
SDA
COMMAND EXECUTED
(QUALIFIES FOR INTERFACE READ BACK)
POINTER UPDATED
(QUALIFIES FOR COMBINED READ BACK)
21
AW20191817A16 15 14 13 12 11 10 9A800011A1A02223 7654321A021
START STOP
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS
WRITE COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
WRITE DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
WRITE DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
START STOP
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS
READ COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
READ DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
READ DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
START
REPEATED
START
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS
WRITE COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
WRITE DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
WRITE DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
STOP
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS
READ COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
READ DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
READ DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
ACK. GENERATED BY MAX5800/MAX5801/MAX5802 ACK. GENERATED BY I2C MASTER
A20191817A16 15 14 13 12 11 10 9A80001 1A1A02223 7654321021
AR20191817A16 15 14 13 12 11 10 9A800011A1A02223 7654321~A021
AA
21Maxim Integrated
MAX5800/MAX5801/MAX5802
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DACs with Internal Reference and I2C Interface
SCL line but the MAX5800/MAX5801/MAX5802 take over
the SDA line. The final three bytes in the frame contain
the command and register data written in the first transfer
presented for readback, followed by a STOP condition. If
additional bytes beyond those required to read back the
requested data are provided, the MAX5800/MAX5801/
MAX5802 will continue to read back ones.
It is not necessary for the write and read mode transfers
to occur immediately in sequence. I2C transfers involv-
ing other devices do not impact the MAX5800/MAX5801/
MAX5802 readback mode. Toggling between readback
modes is based on the length of the preceding write
mode transfer. Combined format I2C readback operation
is resumed if a write command greater than two bytes
but less than four bytes is supplied. For commands writ-
ten using multiple register write sequences, only the last
command executed is read back. For each command
written, the readback sequence can only be completed
one time; partial and/or multiple attempts to readback
executed in succession will not yield usable data.
I2C Compatibility
The MAX5800/MAX5801/MAX5802 are fully compatible
with existing I2C systems. SCL and SDA are high-imped-
ance inputs; SDA has an open drain which pulls the data
line low to transmit data or ACK pulses. Figure 8 shows a
typical I2C application.
I2C User-Command Register Map
This section lists the user accessible commands and
registers for the MAX5800/MAX5801/MAX5802. Each
serial operation word is 24-bits long. The DAC data is left
justified as shown in Table 3.
Table 4 provides detailed information about the Command
Registers.
Table 3. Format DAC Data Bit Positions
Figure 8. Typical I2C Application Circuit
PART B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
MAX5800 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X
MAX5801 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X
MAX5802 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
µC
ADDR
SCL
SDA
SCLSDA
ADDR
+5V
SCL
SDA
MAX5800
MAX5801
MAX5802
MAX5800
MAX5801
MAX5802
22Maxim Integrated
MAX5800/MAX5801/MAX5802
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DACs with Internal Reference and I2C Interface
Table 4. I2C Commands Summary
COMMAND B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 DESCRIPTION
DAC COMMANDS
CODEn 0 0 0 0 DAC SELECTION CODE REGISTER
DATA[11:4]
CODE REGISTER
DATA[3:0] X X X X Writes data to the selected
CODE register(s)
LOADn 0 0 0 1 DAC SELECTION X X X X X X X X X X X X X X X X
Transfers data from the
selected CODE register(s)
to the selected DAC
register(s)
CODEn_
LOAD_ALL 0 0 1 0 DAC SELECTION CODE REGISTER
DATA[11:4]
CODE REGISTER
DATA[3:0] X X X X
Simultaneously writes data
to the selected CODE
register(s) while updating
all DAC registers
CODEn_
LOADn 0 0 1 1 DAC SELECTION CODE REGISTER
DATA[11:4]
CODE REGISTER
DATA[3:0] X X X X
Simultaneously writes data
to the selected CODE
register(s) while updating
selected DAC register(s)
CONFIGURATION COMMANDS
POWER 0 1 0 0 0 0
Power
Mode
00 =
Normal
01 = PD
1kI
10 = PD
100kI
11 = PD
Hi-Z
X X X X X X
DAC B
DAC A
X X X X X X X X
Sets the power mode of
the selected DACs (DACs
selected with a 1 in the
corresponding DACn bit
are updated, DACs with
a 0 in the corresponding
DACn bit are not impacted)
SW_CLEAR 0 1 0 1 0 0 0 0 X X X X X X X X X X X X X X X X
Executes a software clear (all
CODE and DAC registers
cleared to their default values)
SW_RESET 0 1 0 1 0 0 0 1 X X X X X X X X X X X X X X X X
Executes a software reset
(all CODE, DAC, and
control registers returned
to their default values)
23Maxim Integrated
MAX5800/MAX5801/MAX5802
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DACs with Internal Reference and I2C Interface
Table 4. I2C Commands Summary (continued)
COMMAND B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 DESCRIPTION
CONFIG 0 1 1 0 0 0 0
LD_EN
X X X X X X
DAC B
DAC A
X X X X X X X X
Sets the DAC Latch Mode
of the selected DACs.
Only DACS with a 1 in the
selection bit are updated
by the command.
LD_EN = 0: DAC latch
is operational (LOAD
controlled)
LD_EN = 1: DAC latch is
transparent
REF 0 1 1 1 0
REF
Power
0 =
DAC
1 =
ON
REF
Mode
00 = EXT
01 = 2.5V
10 = 2.0V
11 = 4.1V
X X X X X X X X X X X X X X X X
Sets the reference
operating mode.
REF Power (B18):
0 = Internal reference is
only powered if at least one
DAC is powered
1 = Internal reference is
always powered
ALL DAC COMMANDS
CODE_ALL 1 0 0 0 0 0 0 0 CODE REGISTER
DATA[11:4]
CODE REGISTER
DATA[3:0] X X X X Writes data to all CODE
registers
LOAD_ALL 1 0 0 0 0 0 0 1 X X X X X X X X X X X X X X X X
Updates all DAC latches
with current CODE register
data
CODE_
ALL_
LOAD_ALL
1 0 0 0 0 0 1 X CODE REGISTER
DATA[11:4]
CODE REGISTER
DATA[3:0] X X X X
Simultaneously writes data
to all CODE registers while
updating all DAC registers
NO OPERATION COMMANDS
No
Operation
1 0 0 1 X X X X X X X X X X X X X X X X X X X X
These commands will have
no effect on the device
1 0 1 X X X X X X X X X X X X X X X X X X X X X
1 1 X X X X X X X X X X X X X X X X X X X X X X
Reserved Commands: Any commands not specifically listed above are reserved for Maxim internal use only.
24Maxim Integrated
MAX5800/MAX5801/MAX5802
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DACs with Internal Reference and I2C Interface
Table 5. DAC Selection
B19 B18 B17 B16 DAC SELECTED
0 0 0 0 DAC A
0 0 0 1 DAC B
0 0 1 X No effect
X 1 X X ALL DACs
1 X X X ALL DACs
CODEn Command
The CODEn command (B[23:20] = 0000) updates the
CODE register contents for the selected DAC(s). Changes
to the CODE register content based on this command will
not affect DAC outputs directly unless the DAC latch has
been configured to be transparent. Issuing the CODEn
command with DAC SELECTION = ALL DACs is equiva-
lent to CODE_ALL (B[23:16] = 10000000). See Table 4
and Table 5.
LOADn Command
The LOADn command (B[23:20] = 0001) updates the
DAC register content for the selected DAC(s) by upload-
ing the current contents of the CODE register. The
LOADn command can be used with DAC SELECTION =
ALL DACs to issue a software load for both DACs, which
is equivalent to the LOAD_ALL (B[23:16] = 10000001)
command. See Table 4 and Table 5.
CODEn_LOAD_ALL Command
The CODEn_LOAD_ALL command (B[23:20] = 0010)
updates the CODE register contents for the selected
DAC(s) as well as the DAC register content of both
DACs. Channels for which the CODE register content
has not been modified since the last load to DAC register
operation will not be updated to reduce digital crosstalk.
Issuing this command with DAC_ADDRESS = ALL is
equivalent to the CODE_ALL_LOAD_ALL command. The
CODEn_LOAD_ALL command by definition will modify at
least one CODE register. To avoid this, use the LOADn
command with DAC SELECTION = ALL DACs or use the
LOAD_ALL command. See Table 4 and Table 5.
CODEn_LOADn Command
The CODEn_LOADn command (B[23:20] = 0011)
updates the CODE register contents for the selected
DAC(s) as well as the DAC register content of the
selected DAC(s). Channels for which the CODE register
content has not been modified since the last load to DAC
register operation will not be updated to reduce digital
crosstalk. Issuing this command with DAC SELECTION
= ALL DACs is equivalent to the CODE_ALL_LOAD_ALL
command. See Table 4 and Table 5.
CODE_ALL Command
The CODE_ALL command (B[23:16] = 10000000)
updates the CODE register contents for both DACs. See
Table 4.
LOAD_ALL Command
The LOAD_ALL command (B[23:16] = 10000001) updates
the DAC register content for both DACs by uploading the
current contents of the CODE registers. See Table 4.
CODE_ALL_LOAD_ALL Command
The CODE_ALL_LOAD_ALL command (B[23:16] =
1000001x) updates the CODE register contents for both
DACs as well as the DAC register content of both DACs.
See Table 4
25Maxim Integrated
MAX5800/MAX5801/MAX5802
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DACs with Internal Reference and I2C Interface
POWER Command
The MAX5800/MAX5801/MAX5802 feature a software-
controlled power-mode (POWER) command (B[23:18]
= 010000). The POWER command updates the power-
mode settings of the selected DACs while the power set-
tings of the rest of the DACs remain unchanged. The new
power setting is determined by bits B[17:16] while the
affected DAC(s) are selected by bits B[9:8]. If all DACs
are powered down, the device enters a STANDBY mode.
In power-down, the DAC output is disconnected from the
buffer and is grounded with either one of the two selectable
internal resistors or set to high impedance. See Table 7 for
the selectable internal resistor values in power-down mode.
In power-down mode, the DAC register retains its value so
that the output is restored when the device powers up. The
serial interface remains active in power-down mode.
In STANDBY mode, the internal reference can be pow-
ered down or it can be set to remain powered-on for
external use. Also, in STANDBY mode, devices using the
external reference do not load the REF pin. See Table 6.
SW_RESET and SW_CLEAR Command
The SW_RESET (B[23:16] = 01010001) and SW_CLEAR
(B[23:16] = 01010000) commands provide a means of
issuing a software reset or software clear operation. Use
SW_CLEAR to issue a software clear operation to return
all CODE and DAC registers to the zero-scale value. Use
SW_RESET to reset all CODE, DAC, and configuration
registers to their default values.
Table 6. POWER Command Format
Table 7. Selectable DAC Output Impedance in Power-Down Mode
PD1 (B17) PD0 (B16) OPERATING MODE
0 0 Normal operation
0 1 Power-down with internal 1kI pulldown resistor to GND.
1 0 Power-down with internal 100kI pulldown resistor to GND.
1 1 Power-down with high-impedance output.
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0 1 0 0 0 0 PD1 PD0 X X X X X X B A X X X X X X X X
POWER Command
Power
Mode:
00 =
Normal
01 = 1kI
10 = 100kI
11 = Hi-Z
Don’t Care
DAC
Select:
1 = DAC
Selected
0 = DAC
Not
Selected
Don’t Care
Default Values (all DACs) →0 0 X X X X X X 1 1 X X X X X X X X
26Maxim Integrated
MAX5800/MAX5801/MAX5802
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DACs with Internal Reference and I2C Interface
CONFIG Command
The CONFIG command (B[23:17] = 0110000) updates
the LOAD functions of selected DACs. Issue the com-
mand with B16 = 0 to allow the DAC latches to operate
normally or with B16 = 1 to disable the DAC latches,
making them perpetually transparent. Mode settings of
the selected DACs are updated while the mode settings
of the rest of the DACs remain unchanged; DAC(s) are
selected by bits B[9:8]. See Table 8.
REF Command
The REF command (B[23:19] = 01110) updates the
global reference setting used for both DAC channels. Set
B[17:16] = 00 to use an external reference for the DACs
or set B[17:16] to 01, 10, or 11 to select either the 2.5V,
2.048V, or 4.096V internal reference, respectively.
If RF2 (B18) is set to zero (default) in the REF command,
the reference will be powered down any time both DAC
channels are powered down (in STANDBY mode). If RF2
(B18 = 1) is set to one, the reference will remain powered
even if both DAC channels are powered down, allowing
continued operation of external circuitry. In this mode,
the 1FA shutdown state is not available. See Table 9.
Table 8. CONFIG Command Format
Table 9. REF Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0 1 1 0 0 0 0 LDB X X X X X X B A X X X X X X X X
CONFIG Command
0 = Normal
1 = Transparent
Don’t Care
DAC
Select:
1 = DAC
Selected
0 = DAC
Not
Selected
Don’t Care
Default Values (all DACs) →0 X X X X X X 1 1 X X X X X X X X
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0 1 1 1 0 RF2 RF1 RF0 X X X X X X X X X X X X X X X X
REF Command
0 = Off in Standby
1 = On in Standby
REF Mode:
00 = EXT
01 = 2.5V
10 = 2.0V
11 = 4.0V
Don’t Care Don’t Care
Default Values →0 0 0 X X X X X X X X X X X X X X X X
27Maxim Integrated
MAX5800/MAX5801/MAX5802
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DACs with Internal Reference and I2C Interface
Applications Information
Power-On Reset (POR)
When power is applied to VDD and VDDIO, the DAC out-
put is set to zero scale. To optimize DAC linearity, wait
until the supplies have settled and the internal setup and
calibration sequence completes (200Fs, typ).
Power Supplies and
Bypassing Considerations
Bypass VDD and VDDIO with high-quality ceramic capac-
itors to a low-impedance ground as close as possible to
the device. Minimize lead lengths to reduce lead induc-
tance. Connect the GND to the analog ground plane.
Layout Considerations
Digital and AC transient signals on GND can create noise
at the output. Connect GND to form the star ground for
the DAC system. Refer remote DAC loads to this system
ground for the best possible performance. Use proper
grounding techniques, such as a multilayer board with a
low-inductance ground plane, or star connect all ground
return paths back to the MAX5800/MAX5801/MAX5802
GND. Carefully layout the traces between channels to
reduce AC cross-coupling. Do not use wire-wrapped
boards and sockets. Use shielding to minimize noise immu-
nity. Do not run analog and digital signals parallel to one
another, especially clock signals. Avoid routing digital lines
underneath the MAX5800/MAX5801/MAX5802 package.
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the measured transfer function
from a straight line drawn between two codes once offset
and gain errors have been nullified.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step height and
the ideal value of 1 LSB. If the magnitude of the DNL P
1 LSB, the DAC guarantees no missing codes and is
monotonic. If the magnitude of the DNL R 1 LSB, the DAC
output may still be monotonic.
Offset Error
Offset error indicates how well the actual transfer function
matches the ideal transfer function. The offset error is
calculated from two measurements near zero code and
near maximum code.
Gain Error
Gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
Zero-Scale Error
Zero-scale error is the difference between the DAC
output voltage when set to code zero and ground. This
includes offset and other die level nonidealities.
Full-Scale Error
Full-scale error is the difference between the DAC output
voltage when set to full scale and the reference voltage.
This includes offset, gain error, and other die level non-
idealities.
Settling Time
The settling time is the amount of time required from the
start of a transition, until the DAC output settles to the new
output value within the converter’s specified accuracy.
Digital Feedthrough
Digital feedthrough is the amount of noise that appears
on the DAC output when the DAC digital control lines are
toggled.
Digital-to-Analog Glitch Impulse
A major carry transition occurs at the midscale point
where the MSB changes from low to high and all other
bits change from high to low, or where the MSB changes
from high to low and all other bits change from low to
high. The duration of the magnitude of the switching
glitch during a major carry transition is referred to as the
digital-to-analog glitch impulse.
The digital-to-analog power-up glitch is the duration of
the magnitude of the switching glitch that occurs as the
device exits power-down mode.
28Maxim Integrated
MAX5800/MAX5801/MAX5802
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DACs with Internal Reference and I2C Interface
Detailed Functional Diagram
OUTA
BUFFER A
DAC CONTROL LOGIC POWER-DOWN
1kI100kI
CODE LOAD
CLEAR/
RESET
CLEAR/
RESET
CODE
REGISTER
A
DAC
LATCH
A
8-/10-/12-BIT
DAC A
OUTB
BUFFER B
DAC CONTROL LOGIC POWER-DOWN
1kI100kI
CODE LOAD
CLEAR/
RESET
CLEAR/
RESET
CODE
REGISTER
B
DAC
LATCH
B
8-/10-/12-BIT
DAC B
ADDR
SDA
SCL
VDDIO
POR
CLR
I2C SERIAL
INTERFACE
REF
100kI RIN
INTERNAL/EXTERNAL REFERENCE (USER OPTION) MAX5800
MAX5801
MAX5802
VDD
GND
29Maxim Integrated
MAX5800/MAX5801/MAX5802
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DACs with Internal Reference and I2C Interface
Typical Operating Circuits
DAC
MICRO-
CONTROLLER
SDA
SCL
ADDR
OUT_
GND
VDDIO VDD
CLR
NOTE: UNIPOLAR OPERATION (ONE CHANNEL SHOWN)
REF
100nF
100nF 4.7µF
RPU =
5kI
RPU =
5kI
MAX5800
MAX5801
MAX5802
VOUT = 0V TO VREF
DAC
MICRO-
CONTROLLER
SDA
SCL
ADDR
OUT
GND
VDDIO VDD
CLR
NOTE: BIPOLAR OPERATION (ONE CHANNEL SHOWN)
REF
100nF
100nF 4.7µF
RPU =
5kI
RPU =
5kI
R1 R2
R1 = R2
MAX5800
MAX5801
MAX5802
VOUT = -VREF TO +VREF
30Maxim Integrated
MAX5800/MAX5801/MAX5802
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DACs with Internal Reference and I2C Interface
Ordering Information
Note: All devices are specified over the -40°C to +125°C temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*EP = Exposed pad.
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PART PIN-PACKAGE RESOLUTION (BIT) INTERNAL REFERENCE TEMPCO (ppm/NC)
MAX5800ATB+T 10 TDFN-EP* 8 10 (typ), 25 (max)
MAX5800AUB+T 10 µMAX 8 10 (typ), 25 (max)
MAX5801ATB+T 10 TDFN-EP* 10 10 (typ), 25 (max)
MAX5801AUB+T 10 µMAX 10 10 (typ), 25 (max)
MAX5802AAUB+T 10 µMAX 12 3 (typ), 10 (max)
MAX5802BATB+T 10 TDFN-EP* 12 10 (typ), 25 (max)
MAX5802BAUB+T 10 µMAX 12 10 (typ), 25 (max)
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
10 µMAX U10+2 21-0061 90-0330
10 TDFN-EP T1033+1 21-0137 90-0003
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 31
© 2013 Maxim Integrated Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
MAX5800/MAX5801/MAX5802
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DACs with Internal Reference and I2C Interface
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 9/12 Initial release —
1 12/12 Updated Electrical Characteristics and Ordering Information 2, 30
2 8/13 Removed future product asterisks for µMAX and TDFN products in the Ordering
Information. Updated Input Capacitance in the Electrical Characteristics.7, 30
