373A AVG semiconductors ; DDi~ Technical Data DV74HC373A Octal 3-State Non-Inverting DV74HCT373A Transparent Latch - Pinout for the 'HC373A and 'HCT373Aare identical to the ; LS$373. The Output Enable input does not affect the state of N Suffix the latches, but when the Output Enable is high, all device out- Plastic DIP puts are forced to the high-impedence state. , data may AVG-005 Case be latched even when the outputs are not enabled. Data is latched at the falling edge of Latch Enable. Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL D Suffix * Operating Voltage Range: 2 to 6 V Plastic SOP Low Input Current: 1 yA AVG-006 Case * DC, AC parameters guaranteed from -55C to 125C Z O, a: 5 . PIN ASSIGNMENT 02 2_ f Q of [fj 1 20/7] vee 9 3 % af] 2 19/] a, TRUTH TABLE Dy 13 12 (Each Flip-Flop) Ds 14 15 Qs Po[] 3 18[] O7 5 18 19g Output/ Latch} D| a 74 i offs 16/] O6 Enable|Enable Latch L "| @ Enable 44 Ql] 6 15[] Oo, L L L LE PIN 20 = Ver o.n 9 ah o L xX NC a ____} PIN 10 = GND . Js n X|_ of H = High Logic Level a8 131] D4 L= Low Logic Level a. 9 127] 4 Z = High Impedance X = Don't Care GND TT) 10 4) ue NC = No Change ABSOLUTE MAXIMUM RATINGS Maximum ratings are those values beyond which damage to the device may occur. _ Symbol Parameter Value Unit Voc DC Supply Voltage (Referenced to GND) - 0.5 to +7.0 V Vin DC Input Voltage (Referenced to GND) - 1.5 to Voc +1.5 V Vout OC Output Voltage (Referenced to GND) - 0.5 to Vec +0.5 V lin DC Input Current, per Pin +20 mA, lout DC Output Sink/Source Current, per Pin +35 mA lec DC VCC or GND Current per Output Pin +75 mi, Po Power Dissipation in Still Air Plastic DIP 750 mW SOP Package 500 | Tstg | Storage Temperature -65to +150 C Te Lead Temperature, 1 mm from Case for 10 Seconds 260 C DV74HC373A, OV74HCT3I73A 5-178 1-800-AVG-SEMIGUARANTEED OPERATING CONDITIONS Symbol Parameter Min Max Unit Vec DC Supply Voltage (Referenced to GND) 2.0 6.0 WV Vin, Vout | DC Input Voltage, Output Voltage (Referenced to GND) o Vee V Ta Ambient Temperature -55 +125 C tr, ty Input Rise and Fall Time: HC: Vec=2.0V 0 1000 ns HOT: Vec=5.5V / HO: Vec=4.5V 0 500 HC: Vec=6.0V 0 400 HC 373A DC ELECTRICAL CHARACTERISTICS _ Symbol Parameter Conditions Vec Guranteed Limit Unit (V) 25C to | < 85C |< 125C -55C ViH Minimum High Level Vout = Vece0.1 V 2.0 1.50 1.50 1.50 V Input Voltage Nour! = 20 wA 4.5 3.15 3.15 3.15 6.0 4.20 4.20 4.20 VIL Maximum Low Level Vout = 0.1V 2.0 0.50 0.50 0.50 Vv input Voltage Nout! = 20 wA 4.5 1.35 1.35 1.35 6.0 1.80 1.80 1.80 Vou Minimum High Level Vin = Vin 2.0 1.90 1.90 1.90 V Qutput Voltage llourl = 20 A 45 440 | 4.40 | 4.40 6.0 6.90 5.90 5.90 Vin = Vin llourl <= 6.0 mA 45 3.98 3.64 3.70 lout! <= 7.8 mA 6.0 5.48 5.34 5.20 Vv VoL Maximum Low Level Vin = Vit 2.0 0.10 0.10 0.10 V Output Voltage llout: = 20 pA 4.5 0.10 0.10 0.10 6.0 0.10 0.10 0.10 Vin = Vit Nout! < 6.0 mA 45 0.26 0.33 0.40 Vv lloytl < 7.8 mA 6.0 0.26 0.33 0.40 lina Maximum Input Leakage Current | Vin=Voc or GND 6.0 +0.1 #1.00 | +1.00 A, loz Maximum 3-State Current Vin=Vitor Vin 6.0 +0.5 +5.0 | +10.0 LA (Output in High Impedence) Vout=Vcc or GND lec Maximum Quiescent Supply Vin = Voc or GND 6.0 4.0 40 160 WA Current llourl = 0 A AC CHARACTERISTICS over full operating conditions (CL =50 pF, Inputt-=tt=6ns) Symbol Parameter Vcc Guranteed Limits Unit (V) +25C to < 85C <125C 55C tptH, | Maximum Propogation Delay, 2.0 125 155 190 ns teH. =| InputD to Q 45 25 31 38 6.0 21 26 a2 tpLH, | Maximum Propogation Delay 2.0 140 175 210 ns teH. | Time, 4.5 28 35 42 Latch Enable to Q 6.0 24 30 36 teLz, | Maximum Propogation Delay 2.0 150 190 225 ns tepHz | Time, 4.5 30 38 45 Output Disable to O 6.0 26 33 38 tpzL, | Maximum Propogation Delay 2.0 150 190 225 ns tp7H | Time, 4.5 30 38 45 Output Enable to 6.0 26 33 38 trun, | Maximum Output Transition Time, 2.0 60 75 90 ns tro. =| any Output 4.5 12 15 18 6.0 10 13 15 1-800-AVG-SEMI 5-179 DV74HC379A, DVT4HCT37TIA VEZLe<{ c N C9 | Symbol a Parameter Vec Guranteed Limits Unit +25C to <65C < 125C 55 C Cin Maximum Input Capacitance 10 10 10 pF Cour | Maximum Three-State Output Capacitance 15 15 16 pF _ Output in High-lmpedance State) _ Power Dissipation Capacitance (Per .Latch) Typical @ 25C, Vec = 5.0 V Cpp | Used to determine the no-load dynamic power consumption: 36 pF Pp = Cep Vec*t + lec Veo TIMING REQUIREMENTS (C_ = 50 pF, Input tr = t}= 6.0 ns) Symbol Parameter Vee Guaranteed Limits Unit 25C to -55C < 85C < 125C Min Max | Min | Max Min teu Minimum Setup Time, 2.0 25 30 40 ns Input D to Latch Enable 4.5 5.0 6.0 8.0 6.0 5.0 6.0 7.0 t | Minimum Hold Time, 2.0 5.0 5.0 5.0 ns | Latch Enable to Input D 4.5 5.0 5.0 5.0 6.0 5.0 5.0 5.0 tw Minimum Pulse Width, 2.0 60 75 90 ns Latch Enable 4.5 12 15 18 6.0 10 13 15 HCT 373A DC ELECTRICAL CHARACTERISTICS Symbol Parameter Conditions Vec Guranteed Limits Unit (V) | 425C | <85C |<125C to 55C Viq | Minimum High Level Vour = 0.1V 4.5 2.0 2.0 2.0 Vv Input Voltage or Vec = 0.1 5.5 2.0 2.0 2.0 Hour! =20 yA VIL Maximum Low Level Vout =0.1V 45 0.8 0.8 0.8 V Input Voltage or Voc - 0.1 V 5.5 0.8 0.8 0.8 llourl <20 yA Vou | Minimum High Level Vin = Vir or Vin 4.5 4.4 4.4 4.4 V Output Voltage llour! <.20 yA 5.5 5.4 5.4 5.4 Vin = Vit or Vin llourl <= 6 mA 4.5 3.98 3.84 3.7 V Vo. | MaximumLow Level Vin = Vic or Vin 4.5 0.1 0.1 0.1 V Output Voltage llourl < 20 pA 5.5 0.1 0.1 0.1 Vin = Vir or Vir llourl = 6 mA 4.5 0.26 0.33 0.4 V lin Maximum Input Leakage Current | Vout=Voec or GND 5.5 +0.1 +1.0 +1.0 uA, loz Maximum 3-State Current Vin=Vit or Vin 5.5 +0.5 +5.0 | +10.0 | mA (Output in High Impedance State) | Vout=Vec or GND lec Maximum Quiescent Vin = Vee or GND 5.5 4.0 40.0 160 WA Supply Current louTi = O A Alec Additional Quiescent Supply | VIN=2.4 V, Any One Input Veco | >-55C 25C to 125C Current Vin= Vec or GND, (V) Other Inputs lourl=OWA | 55 | 29 2.4 mA DV74HC373A, DV74HCT373A 5 = 180 1-800-AVG-SEMIAC CHARACTERISTICS (Vcc =5.0 V+ 10%, C_ = 50pF, Input tr = tf = 6.0 ns) Symbol Parameter | Guranteed Limits | Unit _ 25C | < 85C |< 125C to 55C tet, | Maximum Propogation Delay 28 35 42 ns tpu. | Input D to Output Q tpLH, | Maximum Propogation Delay Time, 32 40 48 ns tpu_ | Latch Enable to Q tpLz, | Maximum Propogation Delay Time, 30 38 45 ns teHz | Output Disable to Q tp7_, | Maximum Propogation Delay Time, oo 44 53 ns tpezH | Output Enable to Q trtH, | Maximum Output Transition Time, 12 15 18 ns bre. | any Output Cin Maximum Input Capacitance 10 10 10 pF Cour | Maximum Three-State Output Capacitance 15 15 15 pF (Output in High -impedance State) Power Dissipation Capacitance (Per Enabled Output) Typical @ 25C, Vcc = 5.0 Ceo | Used to determine the no-load dynamic power consupmption: Vv pF Pp = Cpp Vec*f + loc Voc 65 TIMING REQUIREMENTS (Vcc = 5.0 V 10%, Input ty = tf = 6.0 ns) Symbol Parameter Guaranteed Limits Unit 25C to -55C < 85C < 125C Min Max Min Max Min Max tey Minimum Setup Time, 10 13.0 15.0 ns Input D to Latch Enable th Minimum Hold Time, 10 13.0 15.0 ns Latch Enable to Input D tw Minimum Pulse Width, Latch Enable 12 15.0 18.0 ns SWITCHING WAVEFORMS WH GNo i TH. VH GND High Impedance f 10% Wee ! I Vio 1 V oe WT Nooo Vee High Impedance GND Input threshold voltage, VT = 50% Vee for HC; 1.3V for HCT Vu - Vee for HC, 3 V for HCT 1-800-AVG-SEMI 5-184 DV7T4HC373A, DVT4HCT373A VeZe