Stellaris(R) LM3S9D96 Development Kit User 's Manual DK-LM3S9D9 6-00 Co pyrigh t (c) 2 009- 201 1 Te xas In strumen ts Copyright Copyright (c) 2009-2011 Texas Instruments, Inc. All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments. ARM and Thumb are registered trademarks, and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. Texas Instruments 108 Wild Basin, Suite 350 Austin, TX 78746 http://www.ti.com/stellaris 2 July 3, 2011 Stellaris(R) LM3S9D96 Development Kit User's Manual Table of Contents Chapter 1: Overview ......................................................................................................................................... 7 Features.............................................................................................................................................................. 7 Development Kit Contents ................................................................................................................................ 10 Block Diagram .................................................................................................................................................. 11 Development Board Specifications................................................................................................................... 11 Chapter 2: Hardware Description .................................................................................................................. 13 Microcontroller Overview .................................................................................................................................. 13 Jumpers and GPIO Assignments.................................................................................................................. 13 Clocking ........................................................................................................................................................ 14 Reset............................................................................................................................................................. 15 Power Supplies ............................................................................................................................................. 15 USB............................................................................................................................................................... 15 Debugging..................................................................................................................................................... 16 Color QVGA LCD Touch Panel..................................................................................................................... 17 I2S Audio....................................................................................................................................................... 19 User Switch and LED.................................................................................................................................... 19 Chapter 3: External Peripheral Interface (EPI) ............................................................................................. 21 SDRAM Expansion Board ................................................................................................................................ 21 Flash and SRAM Memory Expansion Board .................................................................................................... 21 FPGA Expansion Board.................................................................................................................................... 21 EM2 Expansion Board ...................................................................................................................................... 21 Chapter 4: Using the In-Circuit Debugger Interface .................................................................................... 23 Appendix A: Schematics................................................................................................................................ 25 Appendix B: Component Locations.............................................................................................................. 33 Appendix C: Connection Details ................................................................................................................... 35 DC Power Jack ................................................................................................................................................. 35 ARM Target Pinout ........................................................................................................................................... 35 Appendix D: Microcontroller GPIO Assignments ........................................................................................ 37 Appendix E: Stellaris(R) LM3S9B96 Flash and SRAM Memory Expansion Board ..................................... 41 Features............................................................................................................................................................ 41 Installation......................................................................................................................................................... 41 Hardware Description ....................................................................................................................................... 43 Functional Description .................................................................................................................................. 43 Memory Map..................................................................................................................................................... 45 Component Locations....................................................................................................................................... 46 Schematics ....................................................................................................................................................... 46 Appendix F: Stellaris(R) LM3S9B96 FPGA Expansion Board....................................................................... 51 Features............................................................................................................................................................ 51 Installation......................................................................................................................................................... 52 Hardware Description ....................................................................................................................................... 54 FPGA ............................................................................................................................................................ 54 Camera ......................................................................................................................................................... 54 July 3, 2011 3 SRAM............................................................................................................................................................ 54 Configuration PROM..................................................................................................................................... 54 Configuration Pushbutton ............................................................................................................................. 55 Test Port ....................................................................................................................................................... 55 Camera Connector........................................................................................................................................ 55 5 V Power Pin ............................................................................................................................................... 55 24-MHz Oscillator ......................................................................................................................................... 55 External Peripheral Interface (EPI) Module .................................................................................................. 55 Using the Widget Interface ............................................................................................................................... 55 Writing Your Own Stellaris Application ......................................................................................................... 56 Memory Map..................................................................................................................................................... 56 Register Descriptions.................................................................................................................................... 57 Loading a New Image to the FPGA .................................................................................................................. 63 Installing the Software................................................................................................................................... 64 Modifying the Default Image ......................................................................................................................... 64 Default FPGA Image Blocks ......................................................................................................................... 64 EPI Signal Descriptions .................................................................................................................................... 66 Component Locations....................................................................................................................................... 67 Schematics ....................................................................................................................................................... 68 Appendix G: Stellaris(R) LM3S9B96 EM2 Expansion Board......................................................................... 73 Features............................................................................................................................................................ 73 Installation......................................................................................................................................................... 73 Installation of EM Modules onto the EM2 Expansion Board ............................................................................. 76 Hardware Description ....................................................................................................................................... 78 Primary EM Header ...................................................................................................................................... 78 Secondary EM Header.................................................................................................................................. 79 CAT24C01 EEPROM.................................................................................................................................... 79 I2S Header .................................................................................................................................................... 79 Analog Audio Header.................................................................................................................................... 79 SDIO Header ................................................................................................................................................ 79 EPI Signal Descriptions .................................................................................................................................... 79 Component Locations....................................................................................................................................... 81 Schematics ....................................................................................................................................................... 81 Appendix H: References ................................................................................................................................ 87 4 July 3, 2011 Stellaris(R) LM3S9D96 Development Kit User's Manual List of Figures Figure 1-1. Figure 1-2. Figure 2-1. Figure 4-1. Figure B-1. Figure E-1. Figure E-2. Figure E-3. Figure E-4. Figure F-1. Figure F-2. Figure F-3. Figure F-4. Figure F-5. Figure F-6. Figure G-1. Figure G-2. Figure G-3. Figure G-4. Figure G-5. Figure G-6. Figure G-7. Figure G-8. DK-LM3S9D96 Development Board ............................................................................................... 9 DK-LM3S9D96 Development Board Block Diagram ..................................................................... 11 Factory Default Jumper Settings ................................................................................................... 14 ICD Interface Out Mode ................................................................................................................ 23 Component Placement Plot for Top .............................................................................................. 34 Flash and SRAM Memory Expansion Board................................................................................. 41 Removing EPI Board from DK-LM3S9D96 Development Board................................................... 42 Flash/SRAM/LCD IF Expansion Board Block Diagram ................................................................. 43 Component Placement Plot for Top and Bottom........................................................................... 46 FPGA Expansion Board ................................................................................................................ 51 Removing EPI Board from DK-LM3S9D96 Development Board................................................... 53 FPGA Expansion Board Block Diagram........................................................................................ 54 FPGA Boundary Scan ................................................................................................................... 64 Component Placement Plot for Top .............................................................................................. 67 Component Placement Plot for Bottom ......................................................................................... 68 EM2 Expansion Board................................................................................................................... 73 Removing EPI Board from DK-LM3S9D96 Development Board................................................... 74 EM2 Expansion Board................................................................................................................... 75 Assembled DK-LM3S9D96 Development Board with EM2 Expansion Board .............................. 75 Connecting an EM Module to the EM2 Expansion Board ............................................................. 76 Fully Assembled DK-LM3S9D96 Board with EM2 Expansion Board and Wireless EM Module ... 77 EM2 Expansion Board Block Diagram .......................................................................................... 78 Component Placement Plot for Top and Bottom........................................................................... 81 July 3, 2011 5 List of Tables Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. Table 2-7. Table C-1. Table D-1. Table E-1. Table E-2. Table F-1. Table F-2. Table F-3. Table F-4. Table F-5. Table F-6. Table F-7. Table F-8. Table G-1. 6 Board Features and Peripherals that are Disconnected in Factory Default Configuration ............ 13 USB-Related Signals..................................................................................................................... 15 Hardware Debugging Configurations ............................................................................................ 16 Debug-Related Signals ................................................................................................................. 17 LCD-Related Signals..................................................................................................................... 18 I2S Audio-Related Signals............................................................................................................. 19 Navigation Switch-Related Signals ............................................................................................... 19 Debug Interface Pin Assignments ................................................................................................. 35 Microcontroller GPIO Assignments ............................................................................................... 37 Flash and SRAM Memory Expansion Board Memory Map........................................................... 45 LCD Latch Register ....................................................................................................................... 45 FPGA Expansion Board Memory Map .......................................................................................... 56 Version Register............................................................................................................................ 58 System Control Register ............................................................................................................... 58 Interrupt Enable Register .............................................................................................................. 59 Interrupt Status Register ............................................................................................................... 60 Test Pad Register.......................................................................................................................... 61 LCD Control Register .................................................................................................................... 61 EPI Signal Descriptions ................................................................................................................ 66 EPI Signal Descriptions................................................................................................................. 79 July 3, 2011 C H A P T E R 1 Overview The Stellaris(R) LM3S9D96 Development Board provides a platform for developing systems around the advanced capabilities of the LM3S9D96 ARM(R) CortexTM-M3-based microcontroller. The LM3S9D96 is a member of the Stellaris Firestorm-class microcontroller family. Firestorm-class devices include capabilities such as 80 MHz clock speeds, an External Peripheral Interface (EPI) and Audio I2S interfaces. In addition to new hardware to support these features, the DK-LM3S9D96 board includes a rich set of peripherals found on other Stellaris boards. The development board includes an on-board in-circuit debug interface (ICDI) that supports both JTAG and SWD debugging. A standard ARM 20-pin debug header supports an array of debugging solutions. The Stellaris(R) LM3S9D96 Development Kit accelerates development of Firestorm-class microcontrollers. The kit also includes extensive example applications and complete source code. Features The Stellaris(R) LM3S9D96 Development Board includes the following features. Simple set-up--USB cable provides debugging, communication, and power Flexible development platform with a wide range of peripherals Color LCD graphics display - TFT LCD module with 320 x 240 resolution - Resistive touch interface 80 MHz LM3S9D96 microcontroller with 512 K Flash, 96 K SRAM, and integrated Ethernet MAC+PHY, USB OTG, and CAN communications - - 8 MB SDRAM (plug-in EPI option board) - - EPI break-out board (plug-in option board) 1 MB serial Flash memory Precision 3.00 V voltage reference SAFERTOSTM operating system in microcontroller ROM I2S stereo audio codec - Line In/Out - Headphone Out - Microphone In Controller Area Network (CAN) Interface 10/100 BaseT Ethernet USB On-The-Go (OTG) Connector - Device, Host, and OTG modes July 3, 2011 7 Overview User LED and push button Thumbwheel potentiometer (can be used for menu navigation) MicroSD card slot Supports a range of debugging options - Integrated In-circuit Debug Interface (ICDI) - JTAG, SWD, and SWO all supported - Standard ARM(R) 20-pin JTAG debug connector USB Virtual COM Port Jumper shunts to conveniently reallocate I/O resources Develop using tools supporting KeilTM RealView(R) Microcontroller Development Kit (MDK-ARM), IAR Embedded Workbench, Sourcery CodeBench development tools, Code Red Technologies development tools, or Texas Instruments' Code Composer StudioTM IDE Supported by StellarisWare(R) software including the graphics library, the USB library, and the peripheral driver library Optional expansion boards that work with the External Peripheral Interface (EPI) of the DK-LM3S9D96 development board extend the capabilities of this development platform (each board sold separately) - Stellaris(R) Flash and SRAM Memory Expansion Board (DK-LM3S9B96-FS8) (sold separately) * Provides Flash memory, SRAM, and an improved performance LCD interface For more information on the DK-LM3S9B96-FS8 memory expansion board, see Appendix E, "Stellaris(R) LM3S9B96 Flash and SRAM Memory Expansion Board," on page 41. - Stellaris(R) FPGA Expansion Board (DK-LM3S9B96-FPGA) (sold separately) * Provides machine-to-machine (M2M), high-bandwidth, parallel interface capability of the Stellaris microcontroller * Allows users to control and display the FPGA expansion board's video on the DK-LM3S9D96 development board's large, 3.5" touchscreen display For more information on the DK-LM3S9B96-FPGA expansion board, see Appendix F, "Stellaris(R) LM3S9B96 FPGA Expansion Board," on page 51. - Stellaris(R) EM2 Expansion Board (DK-LM3S9B96-EM2) (sold separately) * Provides a transition between the Stellaris External Peripheral Interface (EPI) connector and the RF Evaluation Module (EM) connector * Enables wireless application development using Low Power RF and RF ID evaluation modules on the Stellaris DK-LM3S9D96 platform For more information on the DK-LM3S9B96-EM2 expansion board, see Appendix G, "Stellaris(R) LM3S9B96 EM2 Expansion Board," on page 73. 8 July 3, 2011 Stellaris(R) LM3S9D96 Development Kit User's Manual Figure 1-1. DK-LM3S9D96 Development Board 5 VDC supply input Headphone Output Audio Line Output USB Connector for Debug and/ or Power On- board JTAG/ SWD Debug Interface Microphone Input Audio Line Input CAN Bus Interface EPI Expansion Board Reset switch JTAG/ SWD In/ Out Connector Power and Ground Test Points USB connector with Host, Device and On- the- Go modes Stellaris LM3S9D96 Microcontroller 10/ 100 Ethernet User LED Potentiometer User Switch 3.00 V Analog Reference microSD Card Slot 1 MB Serial Flash Memory 3.5 " LCD Touch Panel July 3, 2011 9 Overview Development Kit Contents The Stellaris(R) LM3S9D96 Development Kit contains everything needed to develop and run a range of applications using Stellaris microcontrollers: DK-LM3S9D96 development board 8 MB SDRAM expansion board EPI signal breakout board Retractable Ethernet cable USB Mini-B cable for debugger use USB Micro-B cable for OTG-to-PC connection USB Micro-A to USB A adapter for USB Host USB Flash memory stick microSD Card 20-position ribbon cable CD containing: - A supported version of one of the following (including a toolchain-specific Quickstart guide): * KeilTM RealView(R) Microcontroller Development Kit (MDK-ARM) * IAR Embedded Workbench * Sourcery CodeBench development tools * Code Red Technologies development tools * Texas Instruments' Code Composer StudioTM IDE - Complete documentation - Quickstart application source code - Stellaris(R) Firmware Development Package with example source code 10 July 3, 2011 Stellaris(R) LM3S9D96 Development Kit User's Manual Block Diagram Figure 1-2. DK-LM3S9D96 Development Board Block Diagram Development Board Specifications Board supply voltage: 4.75-5.25 Vdc from one of the following sources: - Debugger (ICDI) USB cable (connected to a PC) - USB Micro-B cable (connected to a PC) - DC power jack (2.1 x 5.5mm from external power supply) July 3, 2011 Break-out power output: 3.3 Vdc (100 mA max) 11 Overview Dimensions (excluding LCD panel): - 4.50" x 4.25" x 0.60" (LxWxH) with SDRAM board - 4.50" x 4.25" x 0.75" (LxWxH) with EPI breakout board Analog Reference: 3.0 V +/-0.2% RoHS status: Compliant NOTE: When the LM3S9D96 Development Board is used in USB Host mode, the host connector is capable of supplying power to the connected USB device. The available supply current is limited to ~200 mA unless the development board is powered from an external 5 V supply with a =600mA rating. 12 July 3, 2011 C H A P T E R 2 Hardware Description In addition to an LM3S9D96 microcontroller, the development board includes a range of useful peripheral features and an integrated in-circuit debug interface (ICDI). This chapter describes how these peripherals operate and interface to the microcontroller Microcontroller Overview The Stellaris LM3S9D96 is an ARM Cortex-M3-based microcontroller with 512-KB flash memory, 80-MHz operation, Ethernet, USB, EPI, SAFERTOSTM in ROM, and a wide range of peripherals. See the LM3S9D96 Microcontroller Data Sheet (order number DS-LM3S9D96) for complete microcontroller details. The LM3S9D96 microcontroller is factory-programmed with a quickstart demo program. The quickstart program resides in on-chip flash memory and runs each time power is applied, unless the quickstart has been replaced with a user program. Jumpers and GPIO Assignments Each peripheral circuit on the development board is interfaced to the LM3S9D96 microcontroller through a 0.1" pitch jumper/shunt. Figure 2-1 on page 14 shows the factory default positions of the jumpers. The jumpers must be in these positions for the quickstart demo program to function correctly. The development board offers capabilities that the LM3S9D96 cannot support simultaneously due to pin count and GPIO multiplexing limitations. For example, as configured, the board does not support SDRAM and I2S receive (microphone or line input) functions at the same time. The jumpers associated with I2S receive are omitted in the default configuration. Table 2-1 lists all features and peripherals that are disconnected in the factory default configuration. Using these peripherals requires that other peripherals be disconnected. Appendix D, "Microcontroller GPIO Assignments," on page 37 lists alternative jumper configurations used in conjunction with some of the StellarisWareTM example applications for this board. Table 2-1. Board Features and Peripherals that are Disconnected in Factory Default Configuration Peripheral Jumpers I2S Receive (Audio Input) JP44, 45, 47, 49 Controller Area Network (CAN) JP14, 15 Ethernet Yellow Status LED (LED2) JP2 Analog 3.0V Reference JP33 See Appendix D, "Microcontroller GPIO Assignments," on page 37, for a complete list of GPIO assignments. The table lists all default and alternate assignments that are supported by the 0.1" jumpers and PCB routing. The LM3S9D96 has additional internal multiplexing that enables additional configurations which may require discrete wiring between peripherals and GPIO pins. July 3, 2011 13 Hardware Description The ICDI section of the board has a GND-GND jumper that serves no function other than to provide a convenient place to `park' a spare jumper. This jumper may be reused as required. Figure 2-1. Factory Default Jumper Settings Clocking The development board uses a 16.0-MHz (Y2) crystal to complete the LM3S9D96 microcontroller's main internal clock circuit. An internal PLL, configured in software, multiples this clock to higher frequencies for core and peripheral timing. A 25.0-MHz (Y1) crystal provides an accurate timebase for the Ethernet PHY. 14 July 3, 2011 Stellaris(R) LM3S9D96 Development Kit User's Manual Reset The RESETn signal into the LM3S9D96 microcontroller connects to the reset switch (SW2) and to the ICDI circuit for a debugger-controlled reset. External reset is asserted (active low) under any one of the three following conditions: Power-on reset (filtered by an R-C network) Reset push switch SW2 held down By the ICDI circuit (U12 FT2232, U13D 74LVC125A) when instructed by the debugger (this capability is optional, and may not be supported by all debuggers) The LCD module has special Reset timing requirements requiring a dedicated control line from the microcontroller. Power Supplies The development board requires a regulated 5.0 V power source. Jumpers JP34-36 select the power source, with the default source being the ICDI USB connector. Only one +5 V source should be selected at any time to avoid conflict between the power sources. When using USB in Host mode, the power source should be set to either ICDI or to EXT if a +5 V power supply (not included in the kit) is available. The development board has two main power rails. A +3.3 V supply powers the microcontroller and most other circuitry. +5 V is used by the OTG USB port and In-circuit Debug Interface (ICDI) USB controller. A low drop-out (LDO) regulator (U5) converts the +5 V power rail to +3.3 V. Both rails are routed to test loops for easy access. USB The LM3S9D96's full-speed USB controller supports On-the-Go, Host, and Device configurations. See Table 2-2 for USB-related signals. The 5-pin microAB OTG connector supports all three interfaces in conjunction with the cables included in the kit. The USB port has additional ESD protection diode arrays (D1, D2,D5) for up to 15 kV of ESD protection. Table 2-2. USB-Related Signals Microcontroller Pin Board Function Jumper Name Pin 70 USB0DM USB Data- - Pin 71 USB0DP USB Data+ - Pin 73 USB0RBIAS USB bias resistor - Pin 66 USB0ID OTG ID signal (input to microcontroller) OTG ID Pin 67 USB0VBUS Vbus Level monitoring +VBUS Pin 34 USB0EPE Host power enable (active high) EPEN Pin 35 USB0PFLT Host power fault signal (active low) PFLT U6, a fault-protected switch, controls and monitors power to the USB host port. USB0EPEN, the control signal from the microcontroller, has a pull-down resistor to ensure host-port power remains off during reset. The power switch will immediately cut power if the attached USB device draws July 3, 2011 15 Hardware Description more than 1 Amp, or if the switches' thermal limits are exceeded by a device drawing more than 500 mA. USB0PFLT indicates the over-current status back to the microcontroller. The development board can be either a bus-powered USB device or self-powered USB device depending on the power-supply configuration jumpers. When using the development board in USB-host mode, power to the EVB should be supplied by the In-circuit Debugger (ICDI) USB cable or by a +5 V source connected to the DC power jack. Note that the LM3S9D96's USB capabilities are completely independent from the In-Circuit Debug Interface USB functionality. Debugging Stellaris microcontrollers support programming and debugging using either JTAG or SWD. JTAG uses the TCK, TMS, TDI, and TDO signals. SWD requires fewer signals (SWCLK, SWDIO, and, optionally, SWO for trace). The debugger determines which debug protocol is used. Debugging Modes The LM3S9D96 development board supports a range of hardware debugging configurations. Table 2-3 summarizes these configurations. Table 2-3. Hardware Debugging Configurations Mode Debug Function Use Selected by... 1 Internal ICDI Debug on-board LM3S9D96 microcontroller over Debug USB interface. Default mode 2 ICDI out to JTAG/ SWD header The development board is used as a USB to SWD/ JTAG interface to an external target. Remove jumpers on TCk, TMS, TDI, TDO, and PIN1 3 In from JTAG/SWD header For users who prefer an external debug interface (ULINK, JLINK, etc.) with the development board. Connecting an external debugger to the JTAG/SWD header Debug In Considerations Debug Mode 3 supports board debugging using an external debug interface such as a Segger J-Link or Keil ULINK. Most debuggers use Pin 1 of the Debug connector to sense the target voltage and, in some cases, power the output logic circuit. Installing the VDD/PIN1 jumper will apply 3.3 V power to this pin in order to support external debuggers. Debug USB Overview An FT2232 device from Future Technology Devices International Ltd implements USB-to-serial conversion. The FT2232 is factory-configured to implement a JTAG/SWD port (synchronous serial) on channel A and a Virtual COM Port (VCP) on channel B. This feature allows two simultaneous communications links between the host computer and the target device using a single USB cable. Separate Windows drivers for each function are provided on the Documentation and Software CD. The In-Circuit Debug Interface USB capabilities are completely independent from the LM3S9D96's on-chip USB functionality. 16 July 3, 2011 Stellaris(R) LM3S9D96 Development Kit User's Manual A small serial EEPROM holds the FT2232 configuration data. The EEPROM is not accessible by the LM3S9D96 microcontroller. For full details on FT2232 operation, go to www.ftdichip.com. USB to JTAG/SWD The FT2232 USB device performs JTAG/SWD serial operations under the control of the debugger. A simple logic circuit multiplexes SWD and JTAG functions and, when working in SWD mode, provides direction control for the bidirectional data line. Virtual COM Port The Virtual COM Port (VCP) allows Windows applications (such as HyperTerminal) to communicate with UART0 on the LM3S9D96 over USB. Once the FT2232 VCP driver is installed, Windows assigns a COM port number to the VCP channel. Table 2-4 shows the debug-related signals. Table 2-4. Debug-Related Signals Microcontroller Pin Board Function Jumper Name Pin 77 TDO/SWO JTAG data out or trace data out TDO Pin 78 TDI JTAG data in TDI Pin 79 TMS/SWDIO JTAG TMS or SWD data in/out TMS Pin 80 TCK/SWCLK JTAG Clock or SWD clock TCK Pin 26 PA0/U0RX Virtual Com port data to LM3S9D96 VCPRX Pin 27 PA1/U0TX Virtual Com port data from LM3S9D96 VCPTX Pin 64 RSTn System Reset RSTn Serial Wire Out (SWO) The development board supports the Cortex-M3 Serial-Wire Output (SWO) trace capabilities. Under debugger control, on-board logic can route the SWO datastream to the VCP transmit channel. The debugger software can then decode and interpret the trace information received from the Virtual Com Port. The normal VCP connection to UART0 is interrupted when using SWO. Not all debuggers support SWO. See the Stellaris LM3S9D96 Microcontroller Data Sheet for additional information on the Trace Port Interface Unit (TPIU). Color QVGA LCD Touch Panel The development board features a TFT Liquid Crystal graphics display with 320 x 240 pixel resolution. The display is protected during shipping by a thin, protective plastic film which should be removed before use. Features Features of the LCD module include: July 3, 2011 Kitronix K350QVG-V1-F display 320 x RGB x 240 dots 3.5" 262 K colors 17 Hardware Description Wide temperature range White LED backlight Integrated RAM Resistive touch panel Control Interface The Color LCD module has a built-in controller IC with a multi-mode parallel interface. The development board uses an 8-bit 8080 type interface with GPIO Port D providing the data bus. Table 2-4 shows the LCD-related signals. Table 2-5. LCD-Related Signals Microcontroller Pin Board Function Jumper Name PE6/ADC1 Touch X+ X+ PE3 Touch Y- Y- PE2 Touch X- X- PE7/ADC0 Touch Y+ Y+ PB7 LCD Reset LRSTn PD0..7 LCD Data Bus 0..7 LD0..7 PH7 LCD Data/Control Select LDC PB5 LCD Read Strobe LRDn PH6 LCD Write Strobe LWRn - Backlight control BLON Backlight The white LED backlight must be powered for the display to be clearly visible. U7 (FAN5331B) implements a 20 mA constant-current LED power source to the backlight. The backlight is not normally controlled by the microcontroller, however, the control signal is available on a header. A jumper may be installed to disable the backlight by connecting it to GND. Alternatively, a wire may be used to control this signal from a spare microcontroller GPIO line. Because the FAN5331B operates in a constant current mode, its output voltage will jump up if the LCD should become disconnected. To prevent over-voltage failure of the IC or diode D3, a zener (D4) clamps the voltage. The current will limit to 20 mA, but the total board current will be higher than when the LCD panel is connected. To avoid over-heating the backlighting circuit, install the BLON jumper to completely shut-down the backlighting circuit. Power The LCD module has internal bias voltage generators and requires only a single 3.3 V dc supply. Resistive Touch Panel The 4-wire resistive touch panel interfaces directly to the microcontroller, using 2 ADC channels and 2 GPIO signals. See the StellarisWareTM source code for additional information on touch panel implementation. 18 July 3, 2011 Stellaris(R) LM3S9D96 Development Kit User's Manual I2S Audio The LM3S9D96 development board has advanced audio capabilities using an I2S-connected Audio TLV320AIC23 CODEC. The factory default configuration has Audio output (Line Out and/or Headphone output) enabled. Four additional I2S signals are required for Audio input (Line Input and/or Microphone). All four audio interfaces are through 1/8" (3.5mm) stereo jacks. Table 2-6 shows the I2S audio-related signals. Table 2-6. I2S Audio-Related Signals Microcontroller Pin Board Function Jumper Name I2C0SDA CODEC Configuration Data SDA I2C0SCL CODEC Configuration Clock SCL I2STXSD Audio Out Serial Data TXSD I2STXWS Audio Out Framing signal TXWS I2STXSCK Audio Out Bit Clock BCLKa I2STXMCLK Audio Out System Clock MCLK I2SRXSD Audio In Serial Data RXSDb I2SRXWS Audio In Framing signal RXWSb I2SRXSCK Audio In Bit Clock BCLKb I2SRXMCLK Audio In System Clock MCLKb a. Shares GPIO line with Analog voltage reference. Jumper installed by default. b. Shares GPIO line with LCD data bus - Port D. Jumper omitted by default. The Audio CODEC has a number of control registers which are configured using the I2C bus signals. CODEC settings can only be written, but not read, using I2C. See the StellarisWareTM example applications for programming information and the TLV320AIX23B data sheet for complete register details. The Headphone output can be connected directly to any standard headphones. The Line Output is suitable for connection to an external amplifier, including PC desktop speaker sets. User Switch and LED The development board provides a user push-switch and LED (see Table 2-7). Table 2-7. Navigation Switch-Related Signals Microcontroller Pin Board Function Jumper Name PJ7 User Switch SWITCH PF3 User LED LEDa a. Shared with Ethernet Jack Yellow LED. This jumper is installed by default. July 3, 2011 19 Hardware Description 20 July 3, 2011 C H A P T E R 3 External Peripheral Interface (EPI) The External Peripheral Interface (EPI) is a high-speed 8/16/32-bit parallel bus for connecting external peripherals or memory without glue logic. Supported modes include SDRAM, SRAM, and Flash memories, as well as Host-bus and FIFO modes. The LM3S9D96 development kit includes an 8 MB SDRAM board in addition to an EPI break-out board. Other EPI expansion boards may be available. SDRAM Expansion Board The SDRAM board provides 8 MB of memory (4M x 16) which, once configured, becomes part of the LM3S9D96's memory map at either 0x6000.0000 or 0x8000.0000. The SDRAM interface multiplexes DQ00..14 and AD/BA0..14 without requiring external latches or buffers. Of the 32 EPI signals, only 24 are used in SDRAM mode, with the remaining signals used for non-EPI functions on the board. Flash and SRAM Memory Expansion Board The optional Flash and SRAM Memory Expansion Board (DK-LM3S9B96-FS8) is a plug-in for the DK-LM3S9D96 development board. This expansion board works with the External Peripheral Interface (EPI) of the Stellaris microcontroller and provides Flash memory, SRAM, and an improved performance LCD interface. For more information on the Flash and SRAM Memory Expansion Board (sold separately), see Appendix E, "Stellaris(R) LM3S9B96 Flash and SRAM Memory Expansion Board," on page 41. FPGA Expansion Board The FPGA Expansion Board (DK-LM3S9B96-FPGA) is an optional expansion board which connects directly to the External Peripheral Interface (EPI) port of the Stellaris DK-LM3S9D96 development board to demonstrate the machine-to-machine (M2M), high-bandwidth, parallel interface capability of the Stellaris microcontroller. Right out of the box, users are able to control and display the FPGA expansion board's video on the DK-LM3S9D96 development board's large, 3.5" touchscreen display. For more information on the FPGA Expansion Board (sold separately), see Appendix F, "Stellaris(R) LM3S9B96 FPGA Expansion Board," on page 51. EM2 Expansion Board The EM2 Expansion Board (DK-LM3S9B96-EM2) is an optional expansion board which connects directly to the External Peripheral Interface (EPI) port of the Stellaris DK-LM3S9D96 development board. The EM2 Expansion Board provides a transition between the Stellaris External Peripheral Interface (EPI) connector and the RF Evaluation Module (EM) connector. The DK-LM3S9B96-EM2 enables wireless application development using Low Power RF and RF ID evaluation modules on the Stellaris DK-LM3S9D96 platform. For more information on the EM2 Expansion Board (sold separately), see Appendix G, "Stellaris(R) LM3S9B96 EM2 Expansion Board," on page 73. July 3, 2011 21 External Peripheral Interface (EPI) 22 July 3, 2011 C H A P T E R 4 Using the In-Circuit Debugger Interface The Stellaris(R) LM3S9D96 Development Kit can operate as an In-Circuit Debugger Interface (ICDI). ICDI acts as a USB to the JTAG/SWD adaptor, allowing debugging of any external target board that uses a Stellaris microcontroller. See "Debugging Modes" on page 16 for a description of how to enter ICDI Out mode. Figure 4-1. ICD Interface Out Mode JTAG or SWD connects to the external microcontroller LM3S9B96 D Dev Board PC with IDE/ debugger TDO Stellaris MCU Stellaris MCU Target Board VDD TDI TCK Target Cable TMS USB to JTAG/ SWD +3.3V Remove jumpers to use ICDI Out Feature The debug interface operates in either serial-wire debug (SWD) or JTAG mode, depending on the configuration in the debugger IDE. The IDE/debugger does not distinguish between the on-board Stellaris microcontroller and an external Stellaris microcontroller. The only requirement is that the correct Stellaris device is selected in the project configuration. The Stellaris target board should have a 2x10 0.1" pin header with signals as indicated in Table C-1 on page 35. This applies to both an external Stellaris microcontroller target (Debug Output mode) and to external JTAG/SWD debuggers (Debug Input mode). ICDI does not control RST (device reset) or TRST (test reset) signals. Both reset functions are implemented as commands over JTAG/SWD, so these signals are usually not necessary. July 3, 2011 23 Using the In-Circuit Debugger Interface 24 July 3, 2011 A P P E N D I X A Schematics This section contains the schematics for the DK-LM3S9D96 development board. July 3, 2011 Micro, EPI connector, USB, and Ethernet on page 26 LCD CAN, Serial Memory, and User I/O on page 27 Power Supplies on page 28 I2S Audio Expansion Board on page 29 EPI and SDRAM Expansion Boards on page 30 In-circuit Debug Interface (ICDI) on page 31 25 Schematic page 1 4 PC0/TCK PC1/TMS PC2/TDI PC3/TDO 80 79 78 77 25 24 23 22 PC4/EPI02 PC5/EPI03 PC6/EPI04 PC7/EPI05 PE0/EPI08 PE1/EPI09 PE2/EPI24 PE3/EPI25 B 74 75 95 96 6 5 2 1 PE4/I2STXWS PE5/I2STXSD PE6/ADC1 PE7/ADC0 PG0/EPI13 PG1/EPI14 PG7/EPI31 19 18 36 PJ0/EPI16 PJ1/EPI17 PJ2/EPI18 PJ3/EPI19 PJ4/EPI28 PJ5/EPI29 PJ6/EPI30 14 87 39 50 52 53 54 55 PJ7 64 RESETn PA0/U0RX PA1/U0TX PA2/SSI0CLK PA3/SSI0FSS PA4/SSI0RX PA5/SSI0TX PA6/USB0EPEN PA7/USB0PFLT PB0/USB0ID PB1/USB0VBUS PB2/CCP0 PB3 PB4/EPI0S23 PB5/EPI0S22 PB6/AVREF PB7/NMI PC0/TCK/SWCLK PC1/TMS/SWDIO PC2/TDI PC3/TDO/SWO PC4/EPI0S02 PC5/EPI0S03 PC6/EPI0S04 PC7/EPI0S05 PD0 PD1 PD2/EPI0S20 PD3/EPI0S21 PD4 PD5 PD6 PD7 PE0/EPI0S08 PE1/EPI0S09 PE2/EPI0S24 PE3/EPI0S25 PE4/ADC3 PE5/ADC2 PE6/ADC1 PE7/ADC0 PF0 PF1 PF2/LED1 PF3/LED0 PF4/EPI0S12 PF5/EPI0S15 PG0/EPI0S13 PG1/EPI0S14 PG7/EPI0S31 PJ0/EPI0S16 PJ1/EPI0S17 PJ2/EPI0S18 PJ3 PJ4 PJ5 PJ6 PJ7 PH0/EPI0S06 PH1/EPI0S07 PH2/EPI0S01 PH3/EPI0S00 PH4/EPI0S10 PH5/EPI0S11 PH6/EPI0S26 PH7/EPI0S27 MDIO TXOP RST_n TXON C 1 Y1 OSC0 OSC1 48 49 XTLN XTLP OSC0 OSC1 10PF C3 10PF 51 C4 10PF R1 33 12.4K NC RXIN 86 85 84 83 76 63 62 15 58 3 4 9 21 45 57 69 82 94 USB0RBIAS USB0DP USB0DM VDDA C5 0.1UF PD2/EPI20 PD3/EPI21 PD4/I2SRXSD PD5/I2SRXMCLK PD6 PD7 PF0 PF1/TXMCLK PF2/LED1 GNDA GND GND GND GND GND GND GND VDD VDD VDD VDD VDD VDD VDD VDD LDO VDDC VDDC 2 LED1 PF3/LED0 PF4/EPI12 PF5/EPI15 10K USB On-the-Go PC4/EPI02 PC5/EPI03 PC6/EPI04 PC7/EPI05 USB Micro AB G1 VBUS +3.3V D- D+ G2 G +VBUS D1 D2 2 PE1/EPI09 PE0/EPI08 PH5/EPI11 PH6/EPI26 1 1 B72590D0050H160 2 B72590D0050H160 +VBUS PB1/USBVBUS B JP3 OTG ID D5 1 PB0/USBID JP2 JP4 2 B72590D0050H160 Note: R60-61 = 10 Ohms for LM3S9B96 Rev B1 (see errata) R60-61 = 0 Ohms for LM3S9B96 Rev C and all LM3S9D96 revs +3.3V Ethernet 10/100baseT J1 +3.3V R4 49.9 R6 49.9 C13 10pF 330 3 +3.3V R60 G- 1CT:1 TX+ 1 TX- 2 5 10 0.1UF 46 G+ 12 11 R8 C16 10pF C18 RX+ 3 4 4 7 40 C19 +3.3V R7 49.9 C14 10pF +3.3V 5 RX- 6 1CT:1 C21 0.01UF 7 6 8 C 8 +3.3V R9 C17 10pF R61 10 0.1UF 37 330 R3 9.10K ID +5V PG7/EPI31 PJ2/EPI18 PF5/EPI15 PF4/EPI12 DF12D-50DP 43 73 A J3 JP1 LED2 PH0/EPI06 PH1/EPI07 PH2/EPI01 PH3/EPI00 PH4/EPI10 PH5/EPI11 PH6/EPI26 PH7/EPI27 M+3.3V R2 2 1 Y- 9 10 NC Y+ GND +3.3V 71 70 J3011G21DNL 8 20 32 44 56 68 81 93 M+3.3V C6 C8 C10 0.01UF 0.01UF 0.1UF C12 0.1UF C15 2.2UF History Revision U16 FAN2558S12X 7 5 38 88 C7 C9 0.01UF 0.1UF VOUT C11 2.2UF U16 Required only for LM3S9B96 Rev B1. See errata. LM3S9B96 or LM3S9D96 1 PD0/I2SRXSCK PD1/I2SRXWS ERBIAS M+3.3V D RXIP 47 61 60 59 42 41 PB6/TXSCK/AVREF PB7/NMI R5 49.9 16.00MHz C2 10PF 17 16 10 11 12 13 97 98 99 100 PB4/ADC10/EPI23 PB5/EPI22 PB0/USBID PB1/USBVBUS PB2/I2C0SCL PB3/I2C0SDA Y2 2 25.00MHz C1 XTLN XTALP 66 67 72 65 92 91 90 89 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 GL GR 26 27 28 29 30 31 34 35 PA0/U0RX PA1/U0TX PA2/SSI0CLK PA3 PA4/SSI0RX PA5/SSI0TX PA6/USBEPE/CAN0RX PA7/USBPFLT/CAN0TX J2 1 2 PG0/EPI13 3 PG1/EPI14 4 PH7/EPI27 5 PJ0/EPI16 6 PD3/EPI21 7 PD2/EPI20 8 PJ6/EPI30 9 PJ5/EPI29 10 PJ4/EPI28 11 PJ3/EPI19 12 PE3/EPI25 13 PE2/EPI24 14 PB4/ADC10/EPI23 15 PB5/EPI22 16 PJ1/EPI17 17 PH0/EPI06 18 PH1/EPI07 19 PH2/EPI01 20 PH3/EPI00 21 PH4/EPI10 22 23 24 25 5 U1 3 +5V VIN GND A EPI Expansion Connector PE2/EPI24 PE3/EPI25 PD2/EPI20 PD3/EPI21 PB4/ADC10/EPI23 PB5/EPI22 PH6/EPI26 PH7/EPI27 4 Stellaris Microcontroller 6 3 PE2/EPI24 PE3/EPI25 PD2/EPI20 PD3/EPI21 PB4/ADC10/EPI23 PB5/EPI22 PH6/EPI26 PH7/EPI27 5 2 3 1 2 EN PG 1 0 A Date Description Indicates factory-default jumper position. 11 Mar 09 Initial Prototype 15 Apr 09 First production release 06 Jun 11 Add LM3S9D96 variant 3 4 D Drawing Title: LM3S9B96/LM3S9D96 Dev Board Page Title: Micro, EPI interface, USB and Ethernet 2 1 Size Date: 4 5 B Document Number: 6/13/2011 DB-LM3S9B96 Sheet 6 1 of 6 Rev A Schematic page 2 2 3 +3.3V GND DO DATA0 RSV DATA1 JP12 LED_A JP16 PE6/ADC1 JP17 PE3/EPI25 JP18 PE2/EPI24 +3.3V 12 11 9 10 RESETn 100 C26 0.1UF JP19 PE7/ADC0 R16 10K LED_K ILED+ R59 SW-B3S1000 CARD JP13 ILED- FR4 MISO PA4/SSI0RX SW2 N/C DATA2 CS DATA3 DI CMD VDD 2908-05WB-MG CLOCK FR3 JP11 MISO R19 10K Reset 1 2 3 4 5 6 7 8 +3.3V SSICLK PA2/SSI0CLK X+ XR YD XL YU TOUCH_XP TOUCH_YN TOUCH_XN TOUCH_YP YX- +3.3V Y+ C28 C30 C31 C33 0.01UF 0.01UF 0.01UF 0.01UF R20 10K C24 0.1UF LCD_RSTn CSn SPICLK SPISDI LRSTn +3.3V +3.3V PB7/NMI R18 JP20 330 LED2 Green 1MB Serial Flash +3.3V B Power FLCSn FLASH_CSn PF0 JP8 3 6 1 2 5 nHOLD VDD JP22 PD1/I2SRXWS +3.3V 7 JP21 PD0/I2SRXSCK U2 +3.3V R13 10K JP23 PD2/EPI20 8 JP24 PD3/EPI21 nWP SCK nCE SO SI C25 0.1UF VSS JP25 PD4/I2SRXSD JP26 PD5/I2SRXMCLK 4 JP27 PD6 W25X80AVSSIG-ND JP28 PD7 LD0 LCD_D0 LD1 R21 10K LCD_D1 LD2 LCD_D2 LD3 LD0 LD1 LD2 LD3 LD4 LD5 LCD_D0 LCD_D1 LCD_D2 LCD_D3 LCD_D4 LCD_D3 LD4 LCD_D5 LD6 LD6 LD7 LD8 LD9 LD10 LD11 LCD_D5 LCD_D6 LCD_D7 LCD_D4 LD5 LCD_D6 LD7 LCD_D7 LD12 LD13 LD14 LD15 LD16 LD17 HSYNC VSYNC DCLK LCD_D[0..7] LED R11 JP5 330 PF3/LED0 +3.3V LED1 Green +3.3V LDC User LED PH7/EPI27 AVDD JP29 LRDn C R10 10K SWITCH PJ7 JP6 PB5/EPI22 PH6/EPI26 User Switch JP31 +3.3V C29 0.1UF CAN Transceiver TXD U3 PA7/USBPFLT/CAN0TX JP14 RXD 1 4 PA6/USBEPE/CAN0RX JP15 8 VREF_3.0V POT R12 50K PB4/ADC10/EPI23 JP7 D R17 10K 2 TXD RXD CANH CANL CANH CANL TERM 120 JP58 +5V RS GND 7 6 R58 VCC VREF 3 5 C27 0.1UF VCC DC RD WR PS0 PS1 PS2 PS3 LCD_DC LCD_RDn LCD_WRn JP30 LWRn SW1 SW-B3S1000 C32 0.1UF OE CAN Connector A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 B C J5 1 3 5 7 9 2 4 6 8 +VCAN 10 M2 +VCAN +5V FPC_Socket_60pin JP32 C22 0.1UF Indicates factory-default jumper position. SN65HVD1050D D C23 0.1UF Thumbwheel Potentiometer Drawing Title: LM3S9B96/LM3S9D96 Dev Board Page Title: LCD, CAN, Serial Memory, User IO Size Date: 1 J6 M1 FR2 JP10 SCLK QVGA LCD Panel with touch interface 8-bit 8080 mode MOSI PA5/SSI0TX 6 +3.3V J4 FR1 JP9 MOSI microSD Card Slot R15 10K SD_CSn PA3 5 +3.3V R14 10K SDCSn A 4 QVGA LCD Panel 1 2 3 4 5 B Document Number: 6/13/2011 DB-LM3S9B96 Sheet 6 2 of 6 Rev A Schematic page 3 1 2 3 4 5 6 TP1 3.3V +3.3V P3V U5 PQ1LA333MSPQ TP3 5.0V DBG+5V +VBUS 4 +5V ICDI 3 C34 0.1UF VOUT A M+3.3V M3V 5 NR 1 C42 2.2UF C39 TP2 GND 0.01UF 2 1 3 2 PJ-002BH-SMT ON C37 2.2UF JP35 EXT J7 VIN JP61 JP34 OTG +5V DC INPUT JP60 +5V GND A GND JP59 JP36 Main +3.3V Supply Power Source Selection +3.3V B EPEN PA6/USBEPE/CAN0RX JP37 PFLT PA7/USBPFLT/CAN0TX U6 TPS2051BDBV +VBUS +5V 5 USB0EPE 4 3 IN EN OCn USB0PFLT B 1 C40 2.2UF 2 JP38 OUT GND R23 10K C20 0.1UF C36 2.2UF C41 2.2UF C43 2.2UF R24 10K VBUS Fault Protected Switch C C +3.3V VREF_3.0V VREF 3.00V R22 1.5K U4 1 PB6/TXSCK/AVREF CATHODE JP33 +5V C35 2.2UF 3 NC +5V 2 ANODE R25 10K LM4040B30IDB Backlight 3.0V 0.2% Voltage Reference ILED+ L1 D3 NR4018T100M 10uH FYV0704SMTF D4 BZT52C24 24V ILED- U7 5 BLON 4 JP39 2 C38 2.2UF VIN SW SHDN FB 1 3 GND R26 15 FAN5333B C44 0.1UF C45 0.1UF C46 0.1UF Indicates factory-default jumper position. D D LED Backlight Controller Drawing Title: LM3S9B96/LM3S9D96 Dev Board Page Title: Power Supplies Size Date: 1 2 3 4 5 B Document Number: 6/13/2011 DB-LM3S9B96 Sheet 6 3 of 6 Rev A Schematic page 4 1 2 J8 3 4.7K R55 STX-3000 0.47UF R56 4.7K R30 10K 1 2 3 Microphone Input C47 R28 10K STX-3000 6 C79 0.47UF 4.7K A J9 5 C77 R54 1 2 3 Line Input 4 C76 27PF C48 2.2UF R57 4.7K A C78 27PF R31 4.7K 27PF C54 R27 4.7K B + +3.3V R29 4.7K SDA 20 19 17 18 PB3/I2C0SDA JP40 SCL MICBIAS MICIN PB2/I2C0SCL JP41 TXSD PE5/I2STXSD TXSD 23 24 22 21 PE4/I2STXWS PD4/I2SRXSD JP44 RXWS PD1/I2SRXWS JP45 PB6/BCLK PB6/TXSCK/AVREF RXSD 4 5 6 7 3 LRC BITCLK 25 26 JP46 PD0/BCLK PD0/I2SRXSCK JP47 PF1/MCLK C PF1/TXMCLK 4V LLINEIN RLINEIN MICBIAS MICIN R32 47K 220UF 1 27 MCLK JP48 PD5/MCLK SDIN SCLK MODE nCS C57 28 JP49 100 R37 R33 47K HPVDD AVDD DGND HPGND AGND Audio Line Output 100 0.47UF R35 47K 2 XTI/MCLK CLKOUT XTO VMID C50 0.1UF PD5/I2SRXMCLK R36 0.47UF C58 DIN LRCIN DOUT LRCOUT BCLK BVDD DVDD 1 J11 2 3 STX-3000 B R34 47K 12 13 LOUT ROUT Audio Headphone Output C55 9 10 LHPOUT RHPOUT 4V JP42 TXWS JP43 RXSD 220UF U8 1 J10 2 3 STX-3000 + +3.3V 16 8 14 C56 0.1UF C59 2.2UF C60 2.2UF C C61 2.2UF C52 0.1UF 11 15 TLV320AIC23BPW Analog +3.3V 50mA Power Supply U9 PQ1LA333MSPQ +5V 4 VIN VOUT 5 NR 1 C51 C53 2.2UF D 0.01UF 2 D ON GND Indicates factory-default jumper position. 3 C49 2.2UF Drawing Title: LM3S9B96/LM3S9D96 Dev Board Page Title: I2S Audio Expansion Board Size Date: 1 2 3 4 5 B Document Number: 6/13/2011 DB-LM3S9B96 Sheet 6 4 of 6 Rev A Schematic page 5 1 2 3 4 5 6 SDRAM Expansion Board U10 A Expansion Connector J12 AD2 AD3 AD4 AD5 +3.3V C62 2.2UF B SDCLK CASn D15 D12 AD9 AD8 AD11 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 BA0/D13 BA1/D14 DQM0 SDCKE CSn WEn RASn DQM1 AD6 AD7 AD1 AD0 AD10 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 23 24 25 26 29 30 31 32 33 34 22 35 BA0/D13 BA1/D14 20 21 CSn WEn RASn CASn 19 16 18 17 SDCLK SDCKE DQM1 DQM0 38 37 39 15 28 41 54 6 12 46 52 DF12A-50DS 8MB SDRAM A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 CS WE RAS CAS CLK CKE DQMH DQML VSS VSS VSS VSSQ VSSQ VSSQ VSSQ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 NC NC VDD VDD VDD VDDQ VDDQ VDDQ VDDQ 2 4 5 7 8 10 11 13 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 42 44 45 47 48 50 51 53 AD8 AD9 AD10 AD11 D12 BA0/D13 BA1/D14 D15 A 36 40 B +3.3V 1 14 27 3 9 43 49 +3.3V C63 0.01UF C64 0.01UF C65 0.1UF C66 0.1UF MT48LC4M16A2 EPI Signal Breakout Board Expansion Connector C C J15 X_PC4/EPI02 X_PC5/EPI03 X_PC6/EPI04 X_PC7/EPI05 X+3.3V X+5V X_PG7/EPI31 X_PJ2/EPI18 X_PF5/EPI15 X_PF4/EPI12 X_PE1/EPI09 X_PE0/EPI08 X_PH5/EPI11 X_PH6/EPI26 D 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 X_PG0/EPI13 X_PG1/EPI14 X_PH7/EPI27 X_PJ0/EPI16 X_PD3/EPI21 X_PD2/EPI20 X_PJ6/EPI30 X_PJ5/EPI29 X_PJ4/EPI28 X_PJ3/EPI19 X_PE3/EPI25 X_PE2/EPI24 X_PB4/EPI23 X_PB5/EPI22 X_PJ1/EPI17 X_PH0/EPI06 X_PH1/EPI07 X_PH2/EPI01 X_PH3/EPI00 X_PH4/EPI10 D DF12A-50DS Drawing Title: LM3S9B96/LM3S9D96 Dev Board Page Title: EPI and SDRAM Expansion Boards Size Date: 1 2 3 4 5 B Document Number: 6/13/2011 DB-LM3S9B96 Sheet 6 5 of 6 Rev A Schematic page 6 2 3 4 5 6 13 1 TCK 11 1 12 Debugger USB Interface 2 54819-0572 D- D+ ID G R43 U13A SN74LVC125A +3.3V 7 USBSH 7 USBDM USBDP R44 1.5K B +5V R39 10K U11 VCC NC ORG GND CS SK DI DO 1 2 3 4 48 1 2 47 R40 1.5K CAT93C46 43 44 1K 64X16 1 Y3 2 4 5 +5V 6.00MHz C68 C69 27PF 27PF EECS EESK EEDATA TEST XTIN XTOUT BDBUS0 BDBUS1 BDBUS2 BDBUS3 BDBUS4 BDBUS5 BDBUS6 BDBUS7 BCBUS0 BCBUS1 BCBUS2 BCBUS3 SI/WUB RESET# RSTOUT# PWREN# GND GND GND GND VCC VCC VCCIOA VCCIOB 15 13 12 11 10 U14C SN74LVC125A 6 U13B SN74LVC125A FT_SRSTN DBGENn DBG_JTAG_EN 2 C 45 2 3 B +3.3V VCP_RX 40 39 38 37 36 35 33 32 12 11 VCP_TX_SWO R53 10K 5 AGND AVCC U15B SN74LVC126A SRSTN 30 29 28 27 26 8 +3.3V 3 42 14 31 +3.3V 6 5 C R45 46 330 C72 C73 C74 C75 0.1UF 0.1UF 0.1UF 0.1UF U14B SN74LVC125A 0.1UF Channel A : JTAG / SW Debug 11 12 Channel B : Virtual Com Port PC3/TDO JP53 RSTn RESETn JP54 VCPTX PA1/U0TX JP55 VCPRX PA0/U0RX 10 R46 J14 20 18 16 14 12 10 8 6 4 2 TDO_SWO SRSTN VCP_TX 19 17 15 13 11 9 7 5 3 1 27 R47 27 R48 27 R49 PIN1 2X10 HDR-SHRD VCP_RX JP57 JP56 +3.3V 27 R50 SRSTN 8 TDO_SWO +3.3V +3.3V +3.3V TCK TMS_SWDIO VCC TDI U13E SN74LVC125A VCC U14E SN74LVC125A 14 JP52 TDO JTAG/SWD In/Out TDI VCC GND GND GND 7 PC2/TDI TMS_SWDIO 14 JP51 TDI U15D SN74LVC126A 7 PC1/TMS TCK 14 JP50 TMS 7 TCK PC0/TCK D TDO_SWO 9 U15C SN74LVC126A 41 FT2232D R38 10K 6 SN74LVC125A U13D SN74LVC125A SWO_EN C71 +3.3v TMS_SWDIO 3 U15A SN74LVC126A U14A +5V 9 18 25 34 TDI 13 +5V 4 ACBUS0 ACBUS1 ACBUS2 ACBUS3 SI/WUA 5 8 10 8 R42 27 0.01UF 3V3OUT 0.1UF R41 27 FT_TCK FT_TDI/DI FT_TDO/DO FT_TMS/OUTEN 24 23 22 21 20 19 17 16 A 4 C67 ADBUS0 ADBUS1 ADBUS2 ADBUS3 ADBUS4 ADBUS5 ADBUS6 ADBUS7 1 6 R51 10K 13 C70 8 7 6 5 9 U12 5 4 3 1 2 USB Device Controller DBG+5V R52 10K 1 5V 6 U14D SN74LVC125A 3 4 J13 10 A 27 VCP_TX 9 U13C SN74LVC125A Indicates factory-default jumper position. +3.3V U15E SN74LVC126A D C80 Drawing Title: LM3S9B96/LM3S9D96 Dev Board Page Title: In-circuit Debug Interface (ICDI) 0.1UF Size Date: 1 2 3 4 5 B Document Number: 6/13/2011 DK-LM3S9B96/LM3S9D96 Sheet 6 6 of 6 Rev A Schematics 32 July 3, 2011 A P P E N D I X B Component Locations This appendix contains details on component locations for the DK-LM3S9D96 development board, including: July 3, 2011 Component placement plot for top (Figure B-1) 33 Component Locations Figure B-1. Component Placement Plot for Top 34 July 3, 2011 A P P E N D I X C Connection Details This appendix contains the connection details for the DK-LM3S9D96 development board including the following sections: DC Power Jack (see page 35) ARM Target Pinout (see page 35) DC Power Jack The EVB provides a DC power jack for connecting an external +5 V regulated (+/-5%) power source. Center Positive (+) The socket is 5.5 mm dia with a 2.1 mm pin. ARM Target Pinout In ICDI input and output mode, the Stellaris(R) LM3S9D96 Development Kit supports ARM's standard 20-pin JTAG/SWD configuration. The same pin configuration can be used for debugging over serial-wire debug (SWD) and JTAG interfaces. Table C-1. Debug Interface Pin Assignments Function Pin Number TDI 5 TDO/SWO 13 TMS/SWDIO 7 TCK/SWCLK 9 System Reset 15 VDD 1 GND 4, 6, 8, 10, 12, 14, 16, 18, 20 No Connect 2, 3, 11, 17, 19 Insert Jumper VDD/PIN1 Jumper (JP57) only when using the development board with an external debug interface such as a ULINK or JLINK. July 3, 2011 35 Connection Details 36 July 3, 2011 A P P E N D I X D Microcontroller GPIO Assignments Table D-1 shows the pin assignments for the LM3S9D96 microcontroller. Table D-1. Microcontroller GPIO Assignments LM3S9D96 GPIO Pin Number July 3, 2011 Development Board Use Description Default Function Default Use Alt. Function 26 PA0 U0Rx Virtual Com Port 27 PA1 U0Tx Virtual Com Port 28 PA2 SSI0Clk SPI 29 PA3 SSI0Fss SD Card CSn 30 PA4 SSI0Rx SPI 31 PA5 SSI0Tx SPI 34 PA6 USB0EPEN USB Pwr Enable CAN0RX 35 PA7 USB0PFLT USB Pwr Fault CAN0TX 66 PB0 USB0ID USB OTG ID 67 PB1 USB0VBUS USB Vbus 72 PB2 I2C0SCL Audio I2C 65 PB3 I2C0SDA Audio I2C 92 PB4 ADC10 Potentiometer EPI0S23 EPI Breakout 91 PB5 PB5 LCD RDn EPI0S22 EPI Breakout 90 PB6 PB6 I2STXSCK AVREF Ext Volt Ref 89 PB7 PB7 LCD RST 80 PC0 TCK/SWCLK JTAG 79 PC1 TMS/SWDIO JTAG 78 PC2 TDI JTAG 77 PC3 TDO/SWO JTAG 25 PC4 EPI0S2 SDRAM D02 EPI0S02 24 PC5 EPI0S3 SDRAM D03 EPI0S03 23 PC6 EPI0S4 SDRAM D04 EPI0S04 22 PC7 EPI0S5 SDRAM D05 EPI0S05 10 PD0 PD0 LCD Data 0 I2SRXSCK Alternate Use I2S Audio In 37 Microcontroller GPIO Assignments Table D-1. Microcontroller GPIO Assignments (Continued) LM3S9D96 GPIO Pin Number 38 Development Board Use Description Default Function 11 PD1 PD1 12 PD2 13 Default Use Alt. Function Alternate Use LCD Data 1 I2S0RXWS I2S Audio In PD2 LCD Data 2 EPI0S20 EPI Breakout PD3 PD3 LCD Data 3 EPI0S21 EPI Breakout 97 PD4 PD4 LCD Data 4 I2SRXSD I2S Audio In 98 PD5 PD5 LCD Data 5 I2SRXMCLK I2S Audio In 99 PD6 PD6 LCD Data 6 100 PD7 PD7 LCD Data 7 74 PE0 EPI0S8 SDRAM D8 EPI0S08 75 PE1 EPI0S9 SDRAM D9 EPI0S09 95 PE2 PE2 Touch XN EPI0S24 96 PE3 PE3 Touch YN EPI0S25 6 PE4 I2STXWS I2S Audio Out 5 PE5 I2STXSD I2S Audio Out 2 PE6 ADC1 ADC Touch XP 1 PE7 ADC0 ADC Touch YP 47 PF0 PF0 Flash CSn 61 PF1 I2STXMCLK I2S Audio Out 60 PF2 LED1 Green Enet LED 59 PF3 PF3 User LED 42 PF4 EPI0S12 SDRAM D12 41 PF5 EPI0S15 SDRAM D15 19 PG0 EPI0S13 SDRAM D13 18 PG1 EPI0S14 SDRAM D14 36 PG7 EPI0S31 SDRAM CLK 86 PH0 EPI0S06 SDRAM D06 85 PH1 EPI0S07 SDRAM D07 84 PH2 EPI0S01 SDRAM D01 83 PH3 EPI0S00 SDRAM D00 76 PH4 EPI0S10 SDRAM D10 63 PH5 EPI0S11 SDRAM D11 LED0 Yw Enet LED July 3, 2011 Stellaris(R) LM3S9D96 Development Kit User's Manual Table D-1. Microcontroller GPIO Assignments (Continued) LM3S9D96 GPIO Pin Number July 3, 2011 Development Board Use Description Default Function 62 PH6 EPI0S26 15 PH7 14 Default Use Alt. Function Alternate Use LCD_WRn EPI0S26 EPI Breakout EPI0S27 LCD_DC EPI0S27 EPI Breakout PJ0 EPI0S16 SDRAM DQM 87 PJ1 EPI0S17 SDRAM DQM 39 PJ2 EPI0S18 SDRAM CAS 50 PJ3 EPI0S19 SDRAM RAS 52 PJ4 EPI0S28 SDRAM WEn 53 PJ5 EPI0S29 SDRAM CSn 54 PJ6 EPI0S30 SDRAM SDCKE 55 PJ7 PJ7 User Switch 39 Microcontroller GPIO Assignments 40 July 3, 2011 A P P E N D I X E Stellaris(R) LM3S9B96 Flash and SRAM Memory Expansion Board This document describes the Flash and SRAM memory expansion board (DK-LM3S9B96-EXP-FS8) plug-in for the Stellaris(R) LM3S9B96 and LM3S9D96 Development Boards. This expansion board works with the External Peripheral Interface (EPI) port of the Stellaris microcontroller and provides Flash memory, SRAM, and an improved performance LCD interface. Figure E-1. Flash and SRAM Memory Expansion Board Features The DK-LM3S9B96-EXP-FS8 memory expansion board has the following features: 8 Megabytes of Flash memory 1 Megabyte of SRAM Memory-mapped LCD I/F for improved LCD performance 1 kilobit of I2C memory for storing configuration data Power LED indicator Installation To install the expansion board on the DK-LM3S9D96 development board, do the following: 1. Remove the DK-LM3S9B96-EXP-FS8 memory expansion board from the antistatic bag. 2. On the DK-LM3S9D96 board, remove any installed board on EPI connector J2. July 3, 2011 41 Stellaris(R) LM3S9B96 Flash and SRAM Memory Expansion Board 3. On the DK-LM3S9D96 board remove the shunt jumpers on JP16-JP31 and the JP39 headers as shown in Figure E-1 on page 41. Figure E-2. Removing EPI Board from DK-LM3S9D96 Development Board Remove board Remove jumpers 4. Install the two snap-in nylon standoffs on mounting holes above the EPI connector J2. 5. Place the expansion board on top of the DK-LM3S9D96 board and align the standoffs, the EPI connector, and the 2x17 J2 header. 6. Press firmly downward until the board snaps in, then verify that the board is firmly seated on the EPI connector, the 2x17 header, and the standoffs. 7. When powering up the board, verify that the power indicator LED D1 is lit. 42 July 3, 2011 Stellaris(R) LM3S9D96 Development Kit User's Manual Hardware Description The Flash and SRAM memory expansion board is designed for use with the Stellaris EPI module configured in Host Bus 8 address/data multiplexed mode. This mode requires the use of an external 8-bit latch for storing the lower 8 address lines A[7:0] transmitted during the address phase of an EPI transfer. This latch can be seen on the expansion board block diagram shown in Figure E-3. Figure E-3. Flash/SRAM/LCD IF Expansion Board Block Diagram EPI Connector EPI[7:0] EPI[27:8] EPI30 MAD[7:0] D Q L MA[27:8] MA[7:0] FLASH A D MAD[7:0] ALE 8MB MA27 EPI28 EPI29 OEn WRn CS OE WE SRAM A D MA26 MA27 1MB CE1 CE2 OE WE LCD DECODE LCD Control LCD Data FLASH/SRAM/LCD IF Board LCD Connector Functional Description The Flash and SRAM memory expansion board schematics are described in this section. The first page of the schematics shows the memory devices and address latch part of the design. The second page shows the LCD I/F and regulator. Flash/SRAM (Schematic 1 on page 48) Page 1 of the schematics shows the EPI connector, address latch, and memory devices. EPI Connector The EPI connector J1 is a 50-pin receptacle with 0.5 mm pitch that plugs into the EPI header on the DK-LM3S9D96 board. The 32 EPI signals and the 2 I2C0 signals from the LM3S9D96 are provided on this connector. It also provides 5 V for the on-board DC regulator. Note that not all EPI signals are used in this design. July 3, 2011 43 Stellaris(R) LM3S9B96 Flash and SRAM Memory Expansion Board 8-bit Latch This 8-bit latch is used to store the lower 8-bits of the address, which are transmitted during the address phase of an EPI transfer. The EPI must be configured in Host bus 8 mode 0 mode (HB8 ADMUX), with EPI30 configured as an Address Latch Enable (ALE) signal to control this latch. Flash Memory The Flash memory used is a 64 Mbit, 90-nsec Spansion S29GL064N90TFI040. This 8/16 bit memory is used in 8-bit mode. Note that MA27 is used as a chip select signal for this memory. SRAM The SRAM used is an 8 Mbit, 45 nsec Cypress Semiconductor CY62158EV30LL-45ZSX, which is an 8-bit memory. Note that MA27 and MA26 are used as chip selects for this memory. I2C Memory This I2C serial memory is used for storing configuration data. This is a 1 kilobit On-Semiconductor memory. LCD I/F, Power (Schematic 2 on page 49) Page 2 of the schematics shows the LCD_DECODE CPLD, LCD interface connector, and the 3.3 V regulator. LCD_DECODE CPLD The LCD DECODE CPLD provides address latch and decode for the LCD interface. The LCD Command and Data registers are mapped on the EPI memory space to streamline access to these registers. The LCD panel control signals L_RDn, L_RWn, and L_DC and the L_D bus are controlled by decode logic on the CPLD with timing derived from EPI signals and do not require direct control from the microcontroller. The LCD latch register is provided to control the XN and YN signals used for the touchscreen and also the reset signal to the LCD. The LCD backlight signal L_BL is controlled by the Stellaris GPIO PE2 (MA[24]). PE2 can be programmed as a GPIO for ON/OFF control of the LCD. A second option is to configure PE2 for use as CCP2 or CCP4 with a PWM output for brightness control. The TP1-TP4 testpoints connect to the CPLD JTAG signals and, along with TP5 and TP6, provide an interface for test and programming of the CPLD. LCD Interface Connector The LCD Interface Connector J2 is a 2x17 socket that connects to headers JP16-JP31 and JP39 on the DK-LM3S9D96. All signals previously driven to the LCD from the Stellaris MCU are replaced by equivalent signals driven from the LCD_DECODE CPLD. DC Regulator DC regulator U4 receives 5 V from the EPI connector and provides 3.3 V for the board. LED D1 provides a power indicator and lights when the regulator is providing power to the board. 44 July 3, 2011 Stellaris(R) LM3S9D96 Development Kit User's Manual Memory Map The DK-LM3S9B96-EXP-FS8 expansion board memory map is shown in Table E-1 and Table E-2 shows the LCD Latch register. Table E-1. Flash and SRAM Memory Expansion Board Memory Map Device A[27:26] A[2:0] FLASH 0X XXX Flash memory (8 Megabytes) R/W 0x6000.0000 SRAM 10 XXX SRAM (1 Megabyte) R/W 0x6800.0000 11 000 LCD latch set R/W 0x6C00.0000 11 001 LCD latch clear R/W 0x6C00.0001 CPLD LCD LCD Description Access a Base address 11 010 LCD command port R /W 0x6C00.0002 11 011 LCD data port Ra/W 0x6C00.0003 11 110 LCD command port read start R 0x6C00.0006 11 111 LCD data port read start R 0x6C00.0007 a. For reads to the LCD Command and Data Port registers, the corresponding LCD Port Read Start register must be read first, followed by a 500 nsec delay before reading this register. Table E-2. LCD Latch Register 7 6 5 4 3 Reserved 0 0 0 0 0 2 1 0 RST YN XN R/W R/W R/W The LCD Latch register is implemented as a set/clear register. To set a bit, the corresponding bit must be set when writing to the LCD Latch Set register. To clear a bit, the corresponding bit must be set when writing to the LCD Latch Clear register. July 3, 2011 XN When clear, the L_XN signal is set to clear. When set, the L_XN signal is tri-stated. This signal is used for the X- input to the touchscreen. YN When clear, the L_YN signal is set to clear. When set, the L_YN signal is tri-stated. This signal is used for the Y- input to the touchscreen. RST When clear, the L_RSTN signal is set to clear. When set, the L_RSTN signal is reset. This signal is used to reset the LCD panel. 45 Stellaris(R) LM3S9B96 Flash and SRAM Memory Expansion Board Component Locations Figure E-4 shows the details of the component locations. Figure E-4. Component Placement Plot for Top and Bottom Top Bottom Schematics This section shows the schematics for the DK-LM3S9B96-EXP-FS8 memory expansion board: 46 Flash, SRAM on page 48 LCD Interface on page 49 July 3, 2011 Stellaris(R) LM3S9D96 Development Kit User's Manual July 3, 2011 47 Flash, SRAM 1 2 3 4 5 Revision History MAD[7..0] Revision MA[27..0] J1 3.3V A R5 2.80k R6 2.80k MAD2 MAD3 MAD4 MAD5 PC4/EPI2 PC5/EPI3 PC6/EPI4 PC7/EPI5 U5 1 2 3 7 4 A0 SCL A1 SDA A2 WP GND VCC 6 5 I2CSCL I2CSDA 3.3V 5V 3.3V 8 R1 CAT24C01 1K - 128X8 0 Note: R1 is not fitted C10 0.1uF TP7 MA18 MA15 MA12 PG7/EPI31 PJ2/EPI18 PF5/EPI15 PF4/EPI12 MA9 MA8 MA11 MA26 PE1/EPI9 PE0/EPI8 PH5/EPI11 PH6/EPI26 B 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 EPI I/F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 U1 PG0/EPI13 PG1/EPI14 PH7/EPI27 PJ0/EPI16 PD3/EPI21 PD2/EPI20 PJ6/EPI30 PJ5/EPI29 PJ4/EPI28 PJ3/EPI19 PE3/EPI25 PE2/EPI24 PB4/EPI23 PB5/EPI22 PJ1/EPI17 PH0/EPI6 PH1/EPI7 PH2/EPI1 PH3/EPI0 PH4/EPI10 MA13 MA14 MA27 MA16 MA21 MA20 ALE MA19 MA25 MA24 MA23 MA22 MA17 3.3V MAD6 MAD7 MAD1 MAD0 MA10 DF12A-50DS R3 10K MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 MA15 MA16 MA17 MA18 MA19 MA20 MA21 MA22 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 9 10 13 MA27 MOEn MWEn 26 28 11 12 47 U3 MAD0 MAD1 MAD2 MAD3 MAD4 MAD5 MAD6 MAD7 3 4 7 8 13 14 17 18 11 1 10 D1 D2 D3 D4 D5 D6 D7 D8 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 2 5 6 9 12 15 16 19 LE OE 27 46 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 GND VCC C12 0.1uF ALE C MOEn MWEn MA[27..0] MAD[7..0] F_RSTn Decode Table Device MA[27:26] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15/A-1 RDY 29 31 33 35 38 40 42 44 Description FLASH 0X Flash memory SRAM 10 SRAM memory LCD 11 LCD Latch/Port MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 MA15 MA16 MA17 MA18 MA19 5 4 3 2 1 44 43 42 39 28 27 26 25 24 23 22 21 20 19 18 MA26 MA27 MOEn MWEn 6 40 41 17 12 34 Date Description A 5/29/2009 Released for manufacturing. B 7/17/2009 Changed J2 to top entry, moved to bottom. Added R9-R11. A MAD0 MAD1 MAD2 MAD3 MAD4 MAD5 MAD6 MAD7 30 32 34 36 39 41 43 45 3.3V 15 R2 3.3V 10K TP8 B R4 10K CE OE WE RP BYTE VPP/WP 14 3.3V VSS VSS U2 20 74LVC373 FLASH VCC 37 C1 0.1uF S29GL064N 64Mbit 3.3V 6 C11 0.1uF SRAM A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 NC NC NC NC NC NC NC NC 9 10 13 14 31 32 35 36 MAD0 MAD1 MAD2 MAD3 MAD4 MAD5 MAD6 MAD7 C 7 8 15 16 29 30 37 38 CE1 CE2 OE WE VSS VSS 3.3V VCC VCC 11 33 TI AEC - Austin C4 0.1uF CY62158EV30 8Mbit C5 0.1uF 108 Wild Basin Rd. Suite 350 Austin, TX 78746 Designer: D Drawing Title: Drawn by: Page Title: FLASH, SRAM Arnaldo Cruz Approved: Size Date: 2 3 4 Document Number: B * 1 D FLASH / SRAM / LCD IF board for DK-LM3S9B96 Arnaldo Cruz 5 Rev 0001 7/21/2009 B Sheet 1 6 of 2 LCD Interface 1 2 3 4 5 6 A A MAD[7..0] MA[27..0] MAD[7..0] MA[27..0] L_D[7..0] LCD_DECODE CPLD U6 MAD0 MAD1 MAD2 MAD3 MAD4 MAD5 MAD6 MAD7 MA24 MA25 MA26 MA27 B ALE MOEn MWEn TP1 TP2 TP3 TP4 TP5 TP6 44 45 46 47 48 2 3 4 7 8 9 10 14 15 16 17 43 18 19 42 CPLD_TCK CPLD_TMS CPLD_TDI CPLD_TDO 1 11 25 35 3.3V R9 R10 R11 5 29 13 37 10K 10K 10K A0/GOE0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15/GOE1 20 21 22 23 24 26 27 28 31 32 33 34 38 39 40 41 L_D0 L_D1 L_D2 L_D3 L_D4 L_D5 L_D6 L_D7 L_DC L_RDn L_WRn L_YN L_XN L_BL L_RSTn F_RSTn F_RSTn J2 L_D4 L_D1 L_D0 L_D3 L_D6 L_D7 L_D2 L_D5 CLK0/IN0 CLK1/IN1 CLK2/IN2 CLK3/IN3 TDI TCK TMS TDO VCC01 VCC11 VCC1 VCC2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 B SMT Socket 2x17 LCD I/F 3.3V GND01 GND11 GND1 GND2 L_BL L_XN L_YP L_YN L_XP L_D4 L_D1 L_DC L_D0 L_D3 L_D6 L_D7 L_D2 L_D5 L_RDn L_WRn L_RSTn 6 30 12 36 C2 0.1uF C3 0.1uF C7 0.1uF C13 0.1uF LC4032V C C 3.3V 5V U4 1 R8 10K 3 2 C8 4.7uF VIN VOUT 5 R7 330 SHDN GND NR C6 4.7uF 4 TPS73033 C9 0.1uF D1 GREEN_LED PWR Drawing Title: D D FLASH / SRAM / LCD IF board for DK-LM3S9B96 Page Title: LCD Interface Size Document Number: B Date: 1 2 3 4 5 Rev B 0001 7/18/2009 Sheet 2 6 of 2 Stellaris(R) LM3S9B96 Flash and SRAM Memory Expansion Board 50 July 3, 2011 A P P E N D I X F Stellaris(R) LM3S9B96 FPGA Expansion Board This chapter describes the Flash and SRAM memory expansion board for the Stellaris(R) LM3S9B96 and LM3S9D96 Development Boards.The Flash and SRAM memory expansion board provides a quick start platform to evaluate the capabilities of the Stellaris External Peripheral Interface (EPI) using the highly integrated DK-LM3S9D96 development platform. This combination adds full-screen motion video to the powerful, easy-to-use StellarisWare(R) GUI tools. Figure F-1 shows a photo of the Flash and SRAM memory expansion board. Figure F-1. FPGA Expansion Board Features The DK-LM3S9B96-EXP-FS8 memory expansion board has the following features: Xilinx Spartan 3E FPGA with 100k system gates 1/13" CMOS VGA (640 x 480) Color Camera Module 1 MB of asynchronous 10 nsec SRAM for graphics/video buffers Standard 1 x 6 and 2 x 5 JTAG headers for FPGA programming 1 kilobit of I2C memory for storing configuration data 8 FPGA test pads provide 5 inputs and 3 I/Os All necessary power regulation The default FPGA image adds the following features: July 3, 2011 EPI operation in GPM D16-A12 mode at 50 MHz, up to 100 MB/s Graphical on-screen-display (OSD) overlaid on moving QVGA video 51 Stellaris(R) LM3S9B96 FPGA Expansion Board Widget-based touchscreen user interface Screen capture to SDCard or USB stick in Windows bitmap (BMP) format Brightness, saturation, tint/hue, and sharpness picture controls Mirror/Flip/Normal Picture controls Installation To install the expansion board on the DK-LM3S9D96 development board, do the following: 1. Remove the DK-LM3S9B96-EXP-FS8 memory expansion board from the antistatic bag. 2. On the DK-LM3S9D96 board, remove any installed board on EPI connector J2. 3. On the DK-LM3S9D96 board, remove the shunt jumpers on JP16-JP31 and the JP39 headers as shown in Figure F-1 on page 51. 4. Place the expansion board on top of the DK-LM3S9D96 board and press firmly downward until the board snaps in. 5. Connect the the male EPI expansion connector on the bottom side of the Flash and SRAM memory expansion board to the female EPI expansion connector on the DK-LM3S9D96 development board (J2). The LCD header pins should fit through the holes on the PCB. 6. Use the included jumper wire to provide 5 V power to J5 from any of the three upper pins immediately below and to the right of the EXT+5V connector on the development board. 7. When powering up the board, verify that the power indicator LED D1 is lit. 52 July 3, 2011 Stellaris(R) LM3S9D96 Development Kit User's Manual Figure F-2. Removing EPI Board from DK-LM3S9D96 Development Board 5 V Power Remove board Remove POT/PB4 jumper Remove JP16-31 jumpers July 3, 2011 53 Stellaris(R) LM3S9B96 FPGA Expansion Board Hardware Description The Flash and SRAM memory expansion board is designed for use with the Stellaris EPI module. Figure F-3 shows a simplified system block diagram. Components of the default FPGA board are shown in half-tone outline. Figure F-3. FPGA Expansion Board Block Diagram Stellaris(R) FPGA The Flash and SRAM memory expansion board features a Xilinx Spartan 3e FPGA, which interfaces to the Stellaris(R) microcontroller through its EPI port and acts as a crossbar to the rest of the peripherals. Camera The Omnivision OV7690 camera provides color VGA images at up to 30 frames per second to the FPGA over an 8-bit wide parallel interface. It is configured by the Stellaris microcontroller via I2C. SRAM The 1 MB, 8-bit wide, 10 ns SRAM is nominally used as a set of frame buffers. 16 bits of the 20-bit address space are latched and multiplexed with its data. Access time may be dependent on the previous address. Configuration PROM A Xilinx standard configuration PROM holds the default FPGA image and automatically uploads it at power-on. 54 July 3, 2011 Stellaris(R) LM3S9D96 Development Kit User's Manual Configuration Pushbutton To reload the configuration PROM image to the FPGA, press the configuration pushbutton. This allows you to load a new image via JTAG without resetting the rest of the system. Test Port Eight uncommitted FPGA pins are brought to test pads. Five of the FPGA pins can only be used as inputs. The remaining three FPGA pins can be used as inputs or outputs. Camera Connector The camera is hosted by the FPC Connector P1 located to the left of the FPGA. To insert or remove the camera, first open the latch by grasping either side of the connector and gently lifting straight up. With the latch open, the camera moves easily; do not force. The camera faces away from the FPGA. Close the latch by pushing down on it gently before use. Caution - Handle the camera carefully when inserting or removing it from the board. Never force the camera into a different position, doing so could damage the camera. 5 V Power Pin J5 is used to provide 5-V power to the Flash and SRAM memory expansion board's regulators. This must be connected for successful board operation. Connect the the male EPI expansion connector on the bottom side of the Flash and SRAM memory expansion board to the female EPI expansion connector on the DK-LM3S9D96 development board (J2). The LCD header pins should fit through the holes on the PCB. 24-MHz Oscillator The camera and the camera interface portion of the FPGA are clocked by a 24-MHz external oscillator. External Peripheral Interface (EPI) Module The External Peripheral Interface (EPI) module provides a slave interface for use with the Stellaris microcontroller's EPI controller configured in general-purpose mode A12-D16. The direction of the signal allocation is in relation to the FPGA (for example, a signal labeled In is an input to the FPGA, a signal labelled Out is an output from the FPGA). See Table F-8 on page 66 for a list of the EPI signals. NOTE: Only 16-bit or 32-bit transfers are allowed for this interface. Using the Widget Interface This section provides information about writing your own graphics using the widget interface for the Flash and SRAM memory expansion board. July 3, 2011 55 Stellaris(R) LM3S9B96 FPGA Expansion Board Writing Your Own Stellaris Application The Stellaris microcontroller communicates with the default FPGA image through a memory-mapped interface. To get started, you must first configure the EPI port by doing the following: 1. Configure the GPIO. 2. Configure the EPI port and map it into memory at 0xA000.0000. Code Example F-1 Configuring the EPI Port EPIModeSet(EPI0_BASE, EPI_MODE_GENERAL); EPIDividerSet(EPI0_BASE, 1); EPIConfigGPModeSet(EPI0_BASE, (EPI_GPMODE_DSIZE_16 | EPI_GPMODE_ASIZE_12 | EPI_GPMODE_WORD_ACCESS | EPI_GPMODE_READWRITE | EPI_GPMODE_READ2CYCLE | EPI_GPMODE_CLKPIN | EPI_GPMODE_RDYEN ), 0, 0); EPIAddressMapSet(EPI0_BASE, EPI_ADDR_PER_SIZE_64KB | EPI_ADDR_PER_BASE_A); //General Purpose mode //Divide system clock by 2 //16 Bit data //12 Bit address //Use Word Access Mode //Use read and write strobe pins //Reads take two cycles //EPI outputs clock to peripheral //Peripheral emits a ready signal //Not using frame signal, so ignore //Not using clock enable, so ignore //64kB memory space //EPI base address is 0xA0000000 Memory Map The DK-LM3S9B96-FPGA expansion board memory map is shown in Table F-1. The default Stellaris code maps this into the 0xA000.0XXX memory space. Detailed descriptions for each register are provide in "Register Descriptions" on page 57. NOTE: Ten bits are used for addressing, but the EPI controller allocates a 12-bit address space. The result is that 0x0A00.0000 is equivalent to 0x0A00.0400, 0x0A00.0800, and 0x0A00.0C00. Table F-1. FPGA Expansion Board Memory Map Register A[10:1] Size Register Name Access See Page VERSION 000 [15:0] Board and FPGA Design Version R 58 SYSCTRL 002 [15:0] System Control R/W 58 IRQEN 004 [15:0] Interrupt Enable R/W 59 IRQSTAT 006 [15:0] Interrupt Status R/W 60 MEMPAGE 008 [10:0] Memory Page R/W 60 TPAD 00A [7:0] Test Pad R/W 61 010 [3:0] LCD Control Set R/W 012 [3:0] LCD Control Clear R/W 022 [15:0] Chroma Key R/W LCTRL CHRMKEY 56 61 62 July 3, 2011 Stellaris(R) LM3S9D96 Development Kit User's Manual Table F-1. FPGA Expansion Board Memory Map (Continued) Register A[10:1] Size VCRM 026 [8:0] VML 030 VMH Register Name Access See Page Video Capture Row Match R/W 62 [15:0] Video Memory Address Low R/W 62 032 [4:0] Video Memory Address High R/W 62 VMS 034 [11:0] Video Memory Stride R/W 62 LRM 036 [7:0] LCD Row Match R/W 62 LVML 040 [15:0] LCD Video Memory Address Low R/W 62 LVMH 042 [4:0] LCD Video Memory Address High R/W 62 LVMS 044 [11:0] LCD Video Memory Stride register (in bytes). R/W 62 LGML 050 [15:0] LCD Graphics Memory Address Low R/W 62 LGMH 052 [4:0] LCD Graphics Memory Address High R/W 63 LGMS 054 [11:0] LCD Graphics Memory Stride R/W 63 MPNC 056 [9:0] Memory Port Number of Columns R/W 63 MPR 058 [8:0] Memory Port Current Row R/W 63 MPC 05A [9:0] Memory Port Current Column R/W 63 MPML 05C [15:0] Memory Port Address Low R/W 63 MPMH 05E [4:0] Memory Port Address High R/W 63 MPMS 060 [11:0] Memory Port Stride R/W 63 MPORT 080 [15:0] Memory Port R/W 63 MEMWIN 400 [15:0] Memory Window R/W 63 Register Descriptions This section provides the detailed register information for the Flash and SRAM memory expansion board. July 3, 2011 57 Stellaris(R) LM3S9B96 FPGA Expansion Board Version Register The Version register communicates the revision numbers of the PCB, the FPGA RTL, and the Stellaris silicon. A dummy write of 0x0000 to this register determines if the Stellaris silicon is revision C (or higher) and configures the EPI clocking circuit appropriately. This is required during initialization for proper operation. Table F-2. Version Register VERSION: 0xA000.0000 15 14 13 12 11 PCB Board Version 10 9 8 0 0 RevC R R R R R R R R 7 6 5 4 3 2 1 0 RTL Major Version R R Bit Name R RTL Minor Version R R R R R Description PCB Board Version: Revision level of the Flash and SRAM memory expansion board. RevC: This bit is high if the FPGA believes it is communicating with Revision C of the silicon (or higher). This bit is only valid after being initialized as described above. RTL Version Revision level of the code running in the Flash and SRAM memory expansion board. System Control Register The System Control register provides access to configuration bits for the video capture and display system. It is implemented as a read-modify-write register and includes LCD and capture modes. Table F-3. System Control Register SYSCTRL: 0xA000.0002 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 PCBrA R R R R R R R R/W 7 6 5 4 3 2 1 0 VCTES T VCQV GA MPRI VSCAL E CMKE N LGDEN LVDEN VCEN R/W R/W R/W R/W R/W R/W R/W R/W Bit Name 58 Description July 3, 2011 Stellaris(R) LM3S9D96 Development Kit User's Manual VCEN Video capture DMA enable. Enables video capture to memory. Disabling this bit captures the remainder of the current frame, and then stops. LVDEN LCD Video DMA enable. Enables DMA from the video memory region to the LCD. LGDEN LCD Graphics DMA enable. Enables DMA from the graphics memory region to the LCD. CMKEN Chroma key enable. VSCALE Video scale control. Scales the video during output to the LCD. If set, the LCD DMA engine skips every other pixel and every other row during LCD video DMA output (Graphics DMA is not affected). As a result, the video object displays at 1/4 its normal size. MPRI Memory port row increment. If set to 0, any read or write to the memory port auto increments the MPC register at the end of the transfer by 1. If MPC is at the last column (MPNR-1), then it sets to 0 and the MPR increments by 1. If the end of the row is reached, then it increments by columns. If set to 1, any read or write increments by rows. VCQVGA Video Capture is QVGA/VGA. If set to 0, the video capture controller assumes that the camera is configured for VGA capture. If set to 1, it assumes that the camera is configured for QVGA. This only affects video capture; the camera's I2C and LCD settings must be reconfigured manually. VCTEST Video Capture Test. When set to 1, the incoming pixel stream is ignored and replaced with a test pattern. PCBrA PCB is Revision A. An early internal revision of the PCB had a different pin configuration for the camera data port. Setting this bit to 1 provides backwards compatibility. Interrupt Enable Register The Interrupt Enable register masks or enables interrupts from the FPGA to the Stellaris LM3S9D96 microcontroller. Masked interrupts will not assert the IRQ line, but they will still appear in the Interrupt Status Register. Table F-4. Interrupt Enable Register IRQEN: 0xA000.0004 July 3, 2011 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R R R R R R R R 7 6 5 4 3 2 1 0 0 0 LRMIE LTEIE LTSIE VRMIE VCFEIE VCFSIE R R R/W R/W R/W R/W R/W R/W Bit Name Description VCFSIE Video capture frame start interrupt enable. VCFEIE Video capture frame end interrupt enable. 59 Stellaris(R) LM3S9B96 FPGA Expansion Board VRMIE Video capture row match interrupt enable. LTSIE LCD transfer start interrupt enable. LTEIE LCD transfer end interrupt enable. LRMIE LCD display row match interrupt enable. Interrupt Status Register The Interrupt Status register reports and clears interrupts from the camera and LCD systems. An interrupt latches its corresponding bit high until cleared by writing a 1 to it. Table F-5. Interrupt Status Register IRQSTAT: 0xA000.0006 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R R R R R R R R 7 6 5 4 3 2 1 0 0 0 LRMI LTEI LTSI VRMI VCFEI VCFSI R R R/W R/W R/W R/W R/W R/W Bit Name Description VCFSI Video capture frame start interrupt. Clear the interrupt by setting the corresponding bit to 1. Setting the bit to 0 has no effect. VCFEI Video capture frame end interrupt. Clear the interrupt by setting the corresponding bit to 1. Setting the bit to 0 has no effect. VRMI Video capture row match interrupt. Clear the interrupt by setting the corresponding bit to 1. Setting the bit to 0 has no effect. LTSI LCD transfer start interrupt. Clear the interrupt by setting the corresponding bit to 1. Setting the bit to 0 has no effect. LTEI LCD transfer end interrupt. Set to 1 to clear the corresponding bit. Clear the interrupt by setting the corresponding bit to 1. Setting the bit to 0 has no effect. LRMI LCD display row match interrupt. Clear the interrupt by setting the corresponding bit to 1. Setting the bit to 0 has no effect. Memory Page Register The Memory Page register selects to memory page to access. 60 July 3, 2011 Stellaris(R) LM3S9D96 Development Kit User's Manual Test PadRegister The Test Pad register is used to access the on-board test pads TP1-TP8, which are connected to unused FPGA pins. Table F-6. Test Pad Register TXPAD: 0xA000.000A 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R R R R R R R R 7 6 5 4 3 2 1 0 TP8 TP7 TP6 TP5 TP4 TP3 TP2 TP1 R R R R R R/W R/W R/W Bit Name Description TP1-TP3 Test Pins 1-3. These are connected to FPGA I/O pins. Writing a 1 sets the corresponding test pin output to 1. Writing a 0 sets the corresponding test pint output to 0. Reading these bits returns the value at the corresponding test pin input. NOTE: The FPGA output driver for these signals is always enabled. TP4-TP8 Test Pins 4-8.These are connected to FPGA input pins. Writing these bits has no effect. Reading these bits returns the value at the corresponding test pin input. LCD Control Register The LCD Control register is implemented as a set/clear register and contains four bits for LCD panel control. To set a bit, set the corresponding bit to 1 when writing to the LCD Control Set register. To clear a bit, set the corresponding bit when writing to the LCD Control Clear register. Table F-7. LCD Control Register LCDCTRL: 0xA000.0012 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R R R R R R R R 7 6 5 4 3 2 1 0 BL RST YN XN R/2 R/W R/W R/W 0 R July 3, 2011 R R R Bit Name Description XN LCD panel touchscreen X control. When set to 0, the LCD Xn signal is set to 0. When set to 1, the LCD Xn signal is tri-stated. 61 Stellaris(R) LM3S9B96 FPGA Expansion Board YN LCD panel touchscreen Y control. When set to 0, the LCD Yn signal is set to 0. When set to 1, the LCD Yn signal is tri-stated. RST LCD panel reset control. When set to 0, the LCD RSTn signal is set to 0. When set to 1 the LCD RSTn signal is set to 1. BL LCD backlight control. When set to 0, the LCD panel backlight is turned off. When set to 1, the LCD panel backlight is turned on. Chroma Key Register The CHRMKEY register contains the RGB values to compare for graphics overlay operation. During LCD screen updates, data from graphics memory is compared with this register, if a match occurs, the corrsponding frame video pixel is sent to the output instead. Video Capture Row Match Register During video capture, at the start of a row, the current row value is compared with the VCRM register. A match generates an interrupt if enabled. Video Memory Address Low Register The VML register provides a pointer to the start of video capture memory and contains the lower 16-bits of the address. Video Memory Address High Register The VMH register provides a pointer to the start of video capture memory and contains the higher 16-bits of the address. Video Memory Stride Register The VMS register specifies the number of locations in video memory between successive array elements (stride) and is measured in bytes. Using stride enables better processing time. LCD Row Match Register During LCD display DMA output, at the start of each row, the current row value is compared with the LRM register. A match generates an interrupt if enabled. LCD Video Memory Address Low Register The LVML register provides a pointer to the start of video data for transfer to the LCD. This contains the lower 16-bits of the address. LCD Video Memory Address High Register The LVMH register provides a pointer to the start of video data for transfer to the LCD. This contains the higher 16-bits of the address. LCD Video Memory Stride Register The LVMS register specifies the number of bytes between the first pixels on adjacent rows in LCD video memory. Recommended to be either the length of a row (in bytes), or the next highest power of two. LCD Graphics Memory Address Low Register The LGML register provides a pointer to the start of graphics memory for output to the LCD and contains the lower 16-bits of the address. 62 July 3, 2011 Stellaris(R) LM3S9D96 Development Kit User's Manual LCD Graphics Memory Address High Register The LGMH register provides a pointer to the start of graphics memory for output to the LCD and contains the higher 16-bits of the address. LCD Graphics Memory Stride Register The LGMS register specifies the number of bytes between the first pixels on adjacent rows in LCD graphics memory. Recommended to be either the length of a row (in bytes), or the next highest power of two. Memory Port Number of Columns Register The MPNC register specifies the number of columns (in pixels) of the memory port. Memory Port Current Row Register The MPR register identifies the selected row in the memory port. Memory Port Current Column Register The MPC register identifies the selected column in the memory port. Memory Port Address Low Register The MPML register contains the lower address bits of the memory region accessed by the memory port. Memory Port Address High Register The MPMH register contains the upper address bits of the memory region accessed by the memory port. Memory Port Stride Register The MPMS register specifies the number of bytes between the first pixels on adjacent rows in the memory port. Recommended to be either the length of a row (in bytes), or the next highest power of two. Memory Port Register The MPORT register allows sequential video/graphics memory plane access. A write (read) to this port generates a memory write (read) to the memory location calculated as follows: Mem address = {MPH:MPL} + MPR x MPS + MPC. After the transfer, if the MPC is not at the last pixel of the row, it automatically increments by 1. If the MPC is at the last pixel of the row, it sets to 0 and the MPR is incremented by MPS. Memory Window Register Use the MEMPAGE register to select the active page (1 Kbyte page). Loading a New Image to the FPGA The FPGA can be re-imaged using any of the JTAG tool chains that support the Xilinx Spartan 3e XC3S100e. Two standard JTAG interfaces are provided with the Flash and SRAM memory expansion board: 2 x 7 with 2mm pitch and 1 x 6 with .1" pitch. Once connected, your JTAG scan chain should show an XC3S100e FPGA and an XCF01S PROM. NOTE: Images loaded into the PROM must be set to use CCLK as the startup clock. Images loaded direct to the FPGA may use either CCLK or JTAG CLK. July 3, 2011 63 Stellaris(R) LM3S9B96 FPGA Expansion Board Figure F-4. FPGA Boundary Scan NOTE: The DK-LM3S9B96-EXP-FS8 boots in JTAG mode, but transitions to serial mode once configured by the PROM. If your programmer is JTAG-only, you may need to clear the PROM and power cycle before you can directly program the FPGA via JTAG. This issue is rare since most tools support both modes. Check with your tool manufacturer for updates. Installing the Software To install the software, do the following: 1. Plug the provided cable into J4 (on the right side of the board), taking care to ensure proper alignment and orientation. The silk-screened signal names should match, with the exception that 2.5 V corresponds to VDD. When correctly aligned, the "JTAG-SPI Full Speed" text should face in toward the FPGA. Modifying the Default Image This section provides the descriptions for the default FPGA image blocks. Default FPGA Image Blocks Configuration Registers The configuration registers are transparently mapped into the Stellaris microcontroller's memory, and are used to control the flow of the video streams. "Register Descriptions" on page 57 provides the detailed register maps. This is contained within the vregs.v file. 64 July 3, 2011 Stellaris(R) LM3S9D96 Development Kit User's Manual Memory Windower The memory windower allows the Stellaris microcontroller to work with a rectangular portion of a frame buffer. For example, this can be used to pull macro-cells for JPEG compression. This is contained within the mport.v file. Memory Arbiter The memory arbiter negotiates access to the external SRAM. The camera capture block is given highest priority. This is contained within the arb.v file. Video Compositor The video compositor assembles the final image from the video and graphics frame buffers, and passes it directly to the LCD Interface. It also converts the camera's VGA resolution to the LCD's QVGA resolution by either downsampling. This is contained within the vlcd.v file. LCD I/F The LCD interface connects to the Kitronix 3.5" LCD display using an 8-bit parallel mode. This is usually driven by the Video Compositor, but can also be driven directly by the EPI interface. This is contained within the vregs.v file. Camera I/F The camera interface block captures pixel data from the Omnivision OV7690's 8-bit digital video port and synchronization signals. This is contained within vcapture.v Camera FIFO The Camera FIFO serves two main purposes: reclocking and flow control. The camera and camera interface run in their own 12-/24-MHz clock domain, whereas the rest of the system runs off of the EPI clock or twice the EPI clock. The FIFO bridges these difference clock domains. The camera does not support any flow control functions; once triggered, it proceeds through an entire image. In order to prevent loss of pixels, this FIFO is 64 elements deep. This is contained within the vcapture.v and async_fifo_64.v files. July 3, 2011 65 Stellaris(R) LM3S9B96 FPGA Expansion Board EPI Signal Descriptions Table F-8 provides the EPI module's signal descriptions. Table F-8. EPI Signal Descriptions EPI Signal Port FPGA Signal Direction Description EPIOS[31] PG7 CLK In EPIOS[30] PJ6 E_IRQn Out EPIOS[29] PJ5 E_RD In EPI Read Strobe EPIOS[28] PJ4 E_WR In EPI Write Strobe EPIOS[27] PH7 E_RDY Out EPI Ready Signal EPIOS[26] PH6 E_RSTn In FPGA Reset Signal b EPIOS[25:16] PE3,PE2,PB4, PB5,PD3,PD2,PJ3, PJ2,PJ1,PJ0 E_ADDR[10:1] In EPI Address Bus EPIOS[15:0] PF5,PG1,PG0,PF4, PH5,PH4,PE1,PE0, PH1,PH0,PC7,PC6, PC5,PC4,PH2,PH3 E_DATA[15:0] I/O EPI Data Bus EPI Clock Interrupt Signal to Microcontrollera a. Configure as Stellaris GPIO input with negative level sensitive interrupts. During power up/reset is used for PLL lock status. b. Configure as Stellaris GPIO output. 66 July 3, 2011 Stellaris(R) LM3S9D96 Development Kit User's Manual Component Locations Figure F-5 shows the details of the component locations from the top view and Figure F-6 shows the details of the component locations from the bottom view. Figure F-5. July 3, 2011 Component Placement Plot for Top 67 Stellaris(R) LM3S9B96 FPGA Expansion Board Figure F-6. Component Placement Plot for Bottom Schematics This section shows the schematics for the DK-LM3S9B96-FPGA memory expansion board: 68 EPI, LCD, Camera I/F on page 70 SRAM, Power, JTAG on page 71 July 3, 2011 Stellaris(R) LM3S9D96 Development Kit User's Manual July 3, 2011 69 EPI, LCD, Camera I/F 1 2 3 4 5 6 3.3V Revision History EPI[31..0] R2 2.80k U1A J1 U9 A 1 2 3 7 4 6 5 A0 SCL A1 SDA A2 WP GND VCC EPI2 EPI3 EPI4 EPI5 3.3V 8 CAT24C01 1K - 128X8 PC4/EPI2 PC5/EPI3 PC6/EPI4 PC7/EPI5 C49 0.1uF I2CSCL I2CSDA 2.8VD R19 2.80k R20 2.80k 3.3V EPI31 EPI18 EPI15 EPI12 3.3V 3.3V 5V PG7/EPI31 PJ2/EPI18 PF5/EPI15 PF4/EPI12 EPI9 EPI8 EPI11 EPI26 PE1/EPI9 PE0/EPI8 PH5/EPI11 PH6/EPI26 U7 B 3 4 8 1 SCL1 SDA1 EN GND 6 5 SCL2 SDA2 2.8VD EPI I/F 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 112 113 116 117 122 123 124 125 126 130 PXLCLK 131 132 EPI28 134 EPI19 135 EPI25 139 PWDN 140 XVCLK 142 143 EPI16 EPI27 EPI14 EPI13 EPI31 EPI21 EPI20 EPI30 EPI29 EPI13 EPI14 EPI27 EPI16 EPI21 EPI20 EPI30 EPI29 EPI28 EPI19 EPI25 EPI24 EPI23 EPI22 EPI17 EPI6 EPI7 EPI1 EPI0 EPI10 PG0/EPI13 PG1/EPI14 PH7/EPI27 PJ0/EPI16 PD3/EPI21 PD2/EPI20 PJ6/EPI30 PJ5/EPI29 PJ4/EPI28 PJ3/EPI19 PE3/EPI25 PE2/EPI24 PB4/EPI23 PB5/EPI22 PJ1/EPI17 PH0/EPI6 PH1/EPI7 PH2/EPI1 PH3/EPI0 PH4/EPI10 L_RSTn 3.3V DF12A-50DS R23 10K R3 10 U8 PCA9306 C23 C24 1 0.1uF 0.1uF 2 OE OUT GND VDD 3.3V 3 4 C48 24.000MHz 0.1uF DVP[7..0] 2.8VD 2.8VA P1 U1E DVP1 DVP3 DVP0 DVP4 DVP5 DVP6 DVP7 DVP2 1 2 SIOD 3 4 SIOC 5 VSYNC 7 C 6 8 HREF 95 107 101 89 84 78 PWDNR 9 10 11 XVCLKR 12 DVP7 14 DVP6 16 DVP5 18 DVP4 20 DVP3 22 DVP2 13 15 PXLCLK HREF VSYNC 17 DVP0 19 DVP1 21 23 TP8 TP7 TP6 TP5 TP4 TP8 TP7 TP6 TP5 TP4 24 M2 66 69 57 56 48 47 41 38 31 36 24 18 12 6 M1 FPC_Socket_24pin D 136 129 128 120 119 114 111 141 IP IP_L06N_0/GCLK9 IP_L06P_0/GCLK8 IP_L03N_0 IP_L03P_0 IP IP IP B 8/19/2009 Changed camera connector P1 to vertical connector. 4 1A 2A 1B 2B 3 6 1OE 2OE GND XVCLKR PWDNR IO_L01P_2/CSO_B IO_L01N_2/INIT_B IO_L02P_2/DOUT/BUSY IO_L02N_2/MOSI/CSI_B IO_L04P_2/D7/GCLK12 IO_L04N_2/D6/GCLK13 IO/D5 IO_L05P_2/D4/GCLK14 IO_L05N_2/D3/GCLK15 IO_L07P_2/D2/GCLK2 IO_L07N_2/D1/GCLK3 IO/M1 IO_L08P_2/M0 IO_L08N_2/DIN/D0 IO_L09P_2/VS2/A19 IO_L09N_2/VS1/A18 IO_L10P_2/VS0/A17 IO_L10N_2/CCLK 39 40 43 44 50 51 52 53 54 58 59 60 62 63 67 68 70 71 FID2 40 Mil Pad 100 Mil Mask FID3 40 Mil Pad 100 Mil Mask FID4 40 Mil Pad 100 Mil Mask FID5 40 Mil Pad 100 Mil Mask FID6 40 Mil Pad 100 Mil Mask 2.8VD VCC 8 C50 B 0.1uF Bottom Fiducials J2 X_INIT_B L_RDn L_D5 L_D2 L_D7 L_D6 L_D3 L_D0 L_DC L_D1 L_DC L_RDn L_WRn L_YN L_D4 L_D1 L_XN L_BLQ L_RSTn L_D0 L_D3 L_D6 L_D7 L_D2 L_D5 X_DAT L_D4 L_XN L_YN L_BL L_XN L_YP L_YN L_XP L_D4 L_D1 L_DC L_D0 L_D3 L_D6 L_D7 L_D2 L_D5 L_RDn L_WRn L_RSTn 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 C SMT Socket 2x17 LCD I/F X_CCLK R4 R5 1.0K 1.0K IP/VREF_3 IP IP IP IP/VREF_3 IP TI AEC - Austin 108 Wild Basin Rd. Suite 350 Austin, TX 78746 R24 2.80k Designer: Q3 MMBT3904 1 2 1.0K Drawing Title: Drawn by: Page Title: EPI, LCD, Camera I/F Arnaldo Cruz Size Date: 4 Document Number: B * 3 D FPGA board for DK-EPI Arnaldo Cruz Approved: 2 A SN74CB3T3306 L_WRn XC3S100E-4TQG144C L_BL 1 Top FID1 40 Mil Pad 100 Mil Mask XC3S100E-4TQG144C XC3S100E-4TQG144C R6 1 7 IO_L01P_1/A16 IO_L01N_1/A15 IO_L02P_1/A14 IO_L02N_1/A13 IO_L03P_1/A12 IO_L03N_1/A11 IO/VREF_1 IO_L04P_1/A10/RHCLK0 IO_L04N_1/A9/RHCLK1 IO_L05P_1/A8/RHCLK2 IO_L05N_1/A7/RHCLK3/TRDY1 IO_L06P_1/A6/RHCLK4/IRDY1 IO_L06N_1/A5/RHCLK5 IO_L07P_1/A4/RHCLK6 IO_L07N_1/A3/RHCLK7 IO_L08P_1/A2 IO_L08N_1/A1 IO/A0 IO_L09P_1/HDC IO_L09N_1/LDC0 IO_L10P_1/LDC1 IO_L10N_1/LDC2 U1C IP/VREF_1 IP IP IP IP IP IP/VREF_2 IP IP_L06N_2/M2/GCLK1 IP_L06P_2/RDWR_B/GCLK0 IP_L03N_2/VREF_2 IP_L03P_2 IP IP Released for manufacturing. U10 2 5 3 M3 BANK 2 M4 Description 6/24/2009 Released for manufacturing. U1B EPI26 74 EPI11 75 76 EPI8 77 EPI9 EPI12 81 EPI15 82 EPI18 83 EPI10 85 86 EPI0 87 EPI1 88 EPI7 91 EPI6 EPI17 92 EPI22 93 EPI23 94 EPI24 96 I2CSDA 97 I2CSCL 98 EPI5 103 EPI4 104 EPI3 105 EPI2 106 Date A Board width increased by 110mils. Added test pads. R22 330 CLK24M 3.3V IO_L01P_0 IO_L01N_0 IO_L02P_0 IO_L02N_0 IO_L04P_0/GCLK4 IO_L04N_0/GCLK5 IO/VREF_0 IO_L05P_0/GCLK6 IO_L05N_0/GCLK7 IO_L07P_0/GCLK10 IO_L07N_0/GCLK11 IO IO_L08P_0 IO_L08N_0/VREF_0 IO_L09P_0 IO_L09N_0 IO_L10P_0 IO_L10N_0/HSWAP XC3S100E-4TQG144C R21 10K 3.3V 2 7 VREF1L VREF2H Revision BANK 0 2.80k BANK 1 R1 5 Rev 0001 8/21/2009 B Sheet 1 6 of 2 SRAM, Power, JTAG 1 2 3.3V 3 4 5 6 2.5V U1G 100 79 A 28 13 49 64 42 VCCO_0 VCCO_0 137 65 30 102 VCCAUX VCCAUX VCCAUX VCCAUX VCCO_1 VCCO_1 80 9 45 115 VCCINT VCCINT VCCINT VCCINT VCCO_3 VCCO_3 U1D 1.2V VCCO_2 VCCO_2 VCCO_2 C25 0.1uF C26 0.1uF C27 0.1uF C28 0.1uF C29 0.1uF C30 0.1uF C31 0.1uF C32 0.1uF BANK 3 138 121 C46 10uF XC3S100E-4TQG144C C33 0.1uF C34 0.1uF C35 0.1uF C36 0.1uF C37 0.1uF C38 0.1uF C47 10uF IO_L01P_3 IO_L01N_3 IO_L02P_3 IO_L02N_3/VREF_3 IO_L03P_3 IO_L03N_3 IO_L04P_3/LHCLK0 IO_L04N_3/LHCLK1 IO_L05P_3/LHCLK2 IO_L05N_3/LHCLK3/IRDY2 IO_L06P_3/LHCLK4/TRDY2 IO_L06N_3/LHCLK5 IO_L07P_3/LHCLK6 IO_L07N_3/LHCLK7 IO_L08P_3 IO_L08N_3 IO_L09P_3 IO_L09N_3 IO_L10P_3 IO_L10N_3 IO IO 2 3 4 5 7 8 14 15 16 17 20 21 22 23 25 26 32 33 34 35 29 10 MCS_n MAD0 MAD1 MAD2 MAD3 MWE_n MA20 MA18 MA17 MA16 MOE_n MAD7 MAD6 MAD5 MAD4 MA19 ALE1 ALE2 MA[20..0] A MAD[7..0] U4 U3 47 46 44 43 41 40 38 37 MAD0 MAD1 MAD2 MAD3 MAD4 MAD5 MAD6 MAD7 48 1 C40 0.1uF C41 0.1uF C42 10uF 3.3V TP2 TP3 TP1 TP2 TP3 TP1 R7 10K B L_BL 73 127 118 99 90 61 55 U2 3 X_CCLK 10 7 8 X_INIT_B 5 6 4 17 SW1 DO CEO CE CF OE/RESET NC NC NC NC NC NC TMS TCK TDI TDO 11 R9 330 R8 10K GND VCCINT VCCO VCCJ 2.5V MA15 MA14 MA13 MA12 MA11 MA10 MA9 MA8 GND GND GND GND GND GND GND GND 3.3V 7 42 18 31 VCC VCC VCC VCC 144 109 110 108 J5 HDR-1X1 5V C43 0.1uF C44 0.1uF C2 C3 C4 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF B 3.3V VSS VSS VDD VDD 11 33 C5 0.1uF IS61WV10248 1Mx8 L3 3.3uH L4 3.3uH 2.8V 5V 1 2 DONE Q1 FDN338P 1 PROG_B TDI TDO TCK TMS R13 6.8uH D2 SS22 + C12 68uF C13 C14 C15 0.1uF 0.1uF 0.1uF 17 4 3 16 5 19 2X7 HDR-SHRD Xilinx JTAG C19 1500pF HDR-1X6 JTAG C20 1500pF C21 1500pF 6 15 PAD C6 0.1uF 3.3V C EN1 EN2 EN3 IS2 SW2 FB2 SS1 SS2 SS3 VOUT3 FB3 GND GND GND AGND 2 C8 0.1uF VIN VOUT R12 330 SHDN GND NR C11 68uF C7 4.7uF 4 D1 GREEN_LED PWR TPS79228 C10 0.1uF R14 0.033 12 14 11 Q2 FDN338P 1 9 7 10 R15 61.9K L2N 2.5V 1 2 18 3 5 2 IS1 SW1 FB1 C9 4.7uF 5V + 5V VIN1 VIN2 VIN3 10K 1.2V L1 L1N J3 C17 1 2 21 22 23 24 43 44 U6 2.5V TMS TDI TDO TCK MAD0 MAD1 MAD2 MAD3 MAD4 MAD5 MAD6 MAD7 CE OE WE 12 34 C1 NC NC NC NC NC NC NC NC 9 10 13 14 31 32 35 36 2.8VA U5 J4 8 37 15 D0 D1 D2 D3 D4 D5 D6 D7 R10 0.033 C45 0.1uF 13 8 20 13 11 9 7 5 3 1 MCS_n MOE_n MWE_n A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 NC_A20 5V 1 XC3S100E-4TQG144C 14 12 10 8 6 4 2 3 4 5 6 7 16 17 18 19 20 26 27 28 29 30 38 39 40 41 25 42 74LVC16373 3 1 1 2 3 4 5 6 13 14 16 17 19 20 22 23 U1F 72 D 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 MA15 MA16 MA17 MA18 MA19 MA20 5V 18 19 20 XCF01S R11 10 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 2.8VD 1Mbit C 4 45 10 39 15 34 21 28 46 37 27 19 11 133 XC3S100E-4TQG144C 3.3V 2.5V 2 4 Tactile Switch 2 9 12 14 15 16 GND GND GND GND GND GND 2 3 5 6 8 9 11 12 2LE 2OE 3 1 3 CLK 1 13 GND GND GND GND GND GND GND 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 25 24 U1H X_DAT 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1LE 1OE 36 35 33 32 30 29 27 26 XC3S100E-4TQG144C C39 0.1uF 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 R17 15.4K R18 61.9K C16 10pF R16 36.5K D3 SS22 L2 3.3V 6.8uH + C18 68uF C22 10uF Drawing Title: D FPGA board for DK-EPI Page Title: SRAM, Power, JTAG TPS75003 Size Document Number: Rev B B Date: 1 2 3 4 5 8/20/2009 Sheet 2 6 of 2 Stellaris(R) LM3S9B96 FPGA Expansion Board 72 July 3, 2011 A P P E N D I X G Stellaris(R) LM3S9B96 EM2 Expansion Board This document describes the Stellaris EM2 Expansion Board (DK-LM3S9B96-EXP-FS8) for the Stellaris(R) LM3S9B96 and LM3S9D96 Development Boards. The Flash and SRAM memory expansion board provides a transition between the Stellaris External Peripheral Interface (EPI) connector and the RF Evaluation Module (EM) connector. The DK-LM3S9B96-EXP-FS8 enables wireless application development using Low Power RF (LPRF) and RF ID evaluation modules on the Stellaris DK-LM3S9D96 platform. Figure G-1. EM2 Expansion Board Features The DK-LM3S9B96-EXP-FS8 expansion board has the following features: 2 sets of EM connectors to support up to 2 RF evaluation modules 1 kilobit of I2C memory for storing configuration data and Flash and SRAM memory expansion board detection EM digital and analog audio signal headers EM MOD1 SDIO connection headers 32 Khz oscillator for slow clock source to primary Flash and SRAM memory expansion board connector Installation To install the Flash and SRAM memory expansion board on the DK-LM3S9D96 development board, do the following: July 3, 2011 73 Stellaris(R) LM3S9B96 EM2 Expansion Board 1. On the DK-LM3S9D96 board (shown in Figure G-2 on page 74), remove any installed board on EPI connector J2 (A). 2. On the DK-LM3S9D96 board (shown in Figure G-2), confirm that shunt jumpers on JP16-JP31 (B) are installed to enable the LCD touch screen. JP39 (C), the leftmost jumper indicated, should remain uninstalled. Figure G-2. Removing EPI Board from DK-LM3S9D96 Development Board (A) Remove board (C) Leave JP39 uninstalled (B) Confirm shunt jumpers (JP16-JP31) installed 3. Place the Flash and SRAM memory expansion board on top of the DK-LM3S9D96 board while aligning the male EPI expansion connector on the bottom side of the Flash and SRAM memory expansion board with the female EPI expansion connector on the DK-LM3S9D96 development board (J2). 74 July 3, 2011 Stellaris(R) LM3S9D96 Development Kit User's Manual Figure G-3. EM2 Expansion Board Bottom side of EM2 module Male EPI expansion connector 4. Press firmly downward until the board snaps in place. Figure G-4. Assembled DK-LM3S9D96 Development Board with EM2 Expansion Board EM2 Expansion Board July 3, 2011 75 Stellaris(R) LM3S9B96 EM2 Expansion Board Installation of EM Modules onto the EM2 Expansion Board The Flash and SRAM memory expansion board has a primary EM header (MOD1) and a secondary EM header (MOD2) as indicated on the silk screen (see Figure G-5). The secondary EM header is rotated 180 degrees from the primary EM header. There are many types of EM modules that can be installed onto the Flash and SRAM memory expansion board. See the README First document for the EM module you are installing to determine if there is a specific requirement or recommendation for which header the EM module should be installed in. If installing a single module and if there is no specific requirement or recommendation in the module's README First document indicating which slot it should be installed in, install the single module into the primary EM header (MOD1). To install an EM module into the primary module EM slot of the Flash and SRAM memory expansion board, do the following: 1. Attach any supplied antennas to the EM module. 2. Locate the two 20-pin sockets on the back side of the EM module. Note the tab on the side of each of the 20-pin sockets. This tab denotes pin 1 and aligns with the 20-pin headers on the Flash and SRAM memory expansion board that contain slots near pin 1 for the tab. See Figure G-5 for details. Figure G-5. Connecting an EM Module to the EM2 Expansion Board Top side of EM2 expansion board Bottom side of EM module Pin 1 slot Pin 1 tab 20-pin sockets on EM module Primary EM header (MOD1) - 20-pin headers Secondary EM header (MOD2) - 20-pin headers 3. Align the two 20-pin sockets on the EM module over the 20-pin headers on the Flash and SRAM memory expansion board that are within the primary EM silkscreen. 76 July 3, 2011 Stellaris(R) LM3S9D96 Development Kit User's Manual 4. Use a slight pressure to seat the EM module firmly on the Flash and SRAM memory expansion board. See Figure G-6 on page 77 for fully assembled DK-LM3S9D96 board with Flash and SRAM memory expansion board and wireless EM module. Figure G-6. Fully Assembled DK-LM3S9D96 Board with EM2 Expansion Board and Wireless EM Module Antenna for EM module EM module EM2 expansion board DK-LM3S9D96 board Follow these same steps for installing a second module into the secondary EM header location which will be oriented 180 degrees from the primary EM header location. NOTE: The secondary EM header should only be used when two EM modules are installed in the system or when specifically indicated in the EM module's README First document. July 3, 2011 77 Stellaris(R) LM3S9B96 EM2 Expansion Board Hardware Description The block diagram for the Flash and SRAM memory expansion board is shown in Figure G-7. Figure G-7. EM2 Expansion Board Block Diagram 32 KHZ OSC EPI Connector +3.3 V MOD_I2C UART1 SPI MOD1 SPI_CS /4 /4 AD_I2C PRIMARY EM HEADER (MOD1) /4 I2S Audio Header GPIO Analog Audio Header +3. 3 V I2C UART I2S Audio Header SECONDARY EM SPI HEADER (MOD2) SHUT MOD2 SPI_CS MOD2 SHUTDOWN MOD2 GPIO I2C UART SPI SHUT DOWN MOD1 SHUTDOWN MOD1 GPIO SDIO Header +3. 3 V DOWN GPIO Analog Audio Header CAT24C01 EEPROM Primary EM Header The primary EM header should always be used when only one EM module is installed unless otherwise indicated in the README First document for the EM module you are installing. The primary EM header connects three buses to the EPI connector that are also shared with the secondary EM header. These buses are I2C, UART1, and SPI. NOTE: The primary and secondary EM headers have a unique SPI chip select signal, but share the data and clock signals. The primary EM header contains four GPIO connections to the EPI connector. These GPIOs can be used as inputs or outputs depending upon the EM module installed. In addition, four unique GPIOs are provided to each EM header. 78 July 3, 2011 Stellaris(R) LM3S9D96 Development Kit User's Manual The primary EM header contains one GPIO connection used to shut down and/or reset the EM module. The actual function depends on the EM module installed. The MODx_nSHUTD signal is pulled up to 3.3 V on the EM2 adapter. Each header has its own MODx_nSHUTD signal. The primary EM header contains additional features not found on the secondary EM header including a 32-KHz oscillator input and a header for a 4-bit SDIO module. These features are not currently used by the EM modules available today but are available for future expansion. Secondary EM Header The secondary EM header should only be used when two EM modules are installed in the system or when specifically indicated in the EM module's README First document. CAT24C01 EEPROM The EM2 board contains a 1-Kbit I2C EEPROM which connects to an I2C bus separate from the one connected to the EM headers. This EEPROM contains data that is used by the software drivers to auto detect that the EM2 expansion board is installed in the system. The EEPROM is normally write-protected. To make the EEPROM writeable, install a jumper between pins 2 and 3 of JPS1. I2S Header The primary EM header and the secondary EM header each contain connections to separate 6-pin I2S headers J2 and J4 respectively. These headers connect to the EM modules only and are not connected to the EPI header which connects to the DK-LM3S9D96. See the EM module's documentation for more information on the functionality of this header. Analog Audio Header The primary EM header and the secondary EM header each contain connections to separate 4-pin analog audio headers J3 and J5 respectively. These headers connect to the EM modules only and are not connected to the EPI header which connects to the DK-LM3S9D96. See the EM module's documentation for more information on the functionality of this header. SDIO Header The primary EM header contains a connection to 8-pin SDIO header J1. This header connects to the EM modules only and is not connected to the EPI header which connects to the DK-LM3S9D96. See the EM module's documentation for more information on the functionality of this header. EPI Signal Descriptions Figure G-1 provides the EPI module's signal descriptions. Table G-1. EPI Signal Descriptions LM3S9D96 Function Port EM2 Signal Direction PE1 PE1 SPI_CS1 Out SPI Chip Select for Primary EM Module PJ4 PJ4 SPI_CS2 Out SPI Chip Select for Secondary EM Module SSI1CLK PH4 SPI_CLK Out SPI Clock SSI1Rx PF4 SPI_MISO In July 3, 2011 Description SPI Receive 79 Stellaris(R) LM3S9B96 EM2 Expansion Board Table G-1. EPI Signal Descriptions (Continued) LM3S9D96 Function Port EM2 Signal Direction SSI1TX PF5 SPI_MOSI Out U1RX PC6 MOD_UART_TX In Modulator UART TX, LM3S9D96 RX U1TX PC7 MOD_UART_RX Out Modulator UART RX, LM3S9D96 TX U1RTS PJ6 MOD_UART_CTS Out Modulator UART CTS, LM3S9D96 RTS U1CTS PJ3 MOD_UART_RTS In Modulator UART RTS, LM3S9D96 CTS I2C1SCL PJ0 MOD_I2C_SCL Out I2C Bus to EM Modules I2C1SDA PJ1 MOD_I2C_SDA I/O I2C Bus to EM Modules I2C0SCL PB2 AD_I2C_SCL0 Out I2C Bus to Auto Discovery EEPROM I2C0SDA PB3 AD_I2C_SDA0 I/O I2C Bus to Auto Discovery EEPROM PC4 PC4 MOD1_nSHUTD Out Shutdown/Reset Signal for Primary EM Module PH5 PH5 MOD2_nSHUTD Out Shutdown/Reset Signal for Secondary EM Module PH0 PH0 MOD1_GPIO0 I/O GPIO for Primary EM Module PH1 PH1 MOD1_GPIO1 I/O GPIO for Primary EM Module PH2 PH2 MOD1_GPIO2 I/O GPIO for Primary EM Module PH3 PH3 MOD1_GPIO3 I/O GPIO for Primary EM Module PG0 PG0 MOD2_GPIO0 I/O GPIO for Secondary EM Module PG1 PG1 MOD2_GPIO1 I/O GPIO for Secondary EM Module PG7 PG7 MOD2_GPIO2 I/O GPIO for Secondary EM Module PJ2 PJ2 MOD2_GPIO3 I/O GPIO for Secondary EM Module 80 Description SPI Transmit July 3, 2011 Stellaris(R) LM3S9D96 Development Kit User's Manual Component Locations Figure G-8 shows the details of the component locations. Figure G-8. Component Placement Plot for Top and Bottom Top Bottom Schematics This section shows the schematics for the Flash and SRAM memory expansion board: July 3, 2011 EM2 Expansion Board on page 85 81 Stellaris(R) LM3S9B96 EM2 Expansion Board 82 July 3, 2011 Stellaris(R) LM3S9D96 Development Kit User's Manual July 3, 2011 83 Stellaris(R) LM3S9B96 EM2 Expansion Board 84 July 3, 2011 EM2 Expansion Board 5 4 3 2 1 Primary EM header +3.3V +3.3V INSTALL RESISTOR R7 WHEN 2nd MODULE NEEDS SLOW CLK. SEC_MOD_SCLK 32KHz Clock R7 0 D R8 OSC1 1 2 0 OUT GND 4 3 VCC EN MC_32.768kHz C2 10000pF DNI C3 10nF C4 1uF MOD1_SDIO_D0 MOD_UART_CTS MOD1_SDIO_D1 MOD_SLOWCLK MOD1_SDIO_D2 MOD_UART_RX MOD1_SDIO_D3 MOD_UART_TX MOD1_GPIO0 MOD_I2C_SDA MOD1_GPIO1 MOD_I2C_SCL SPI_CS1 MOD1_SDIO_CLK SPI_CLK MOD1_SDIO_CMD SPI_MOSI Header_1x8_100_430L +3.3V SPI_MISO B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 TFM-110-02-S-D-K-A +3.3V DNI MOD_SLOWCLK J1 RFMOD1_SDIO 1 2MOD1_SDIO_CMD 3MOD1_SDIO_CLK 4MOD1_SDIO_D3 5MOD1_SDIO_D2 6MOD1_SDIO_D1 7MOD1_SDIO_D0 8 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 CC-P1 CC-P2 TFM-110-02-S-D-K-A 32KHz clock for BT boards MOD1 HPA_MB_MODULE_ASSY_RF RF_MODULE-PORT_1A D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 +3.3V D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 MOD1_AUD_ANA_L MOD1_AUD_ANA_R MOD1_AUD_DATA_OUT J2 RFMOD1_I2S 1 2 MOD1_AUD_CLK 3 MOD1_AUD_FSYNC 4 MOD1_AUD_DATA_IN MOD1_AUD_DATA_OUT 5 6 MOD1_AUD_DATA_IN D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D Header_1x6_100_430L MOD1_AUD_FSYNC MOD1_GPIO2 J3 RFMOD1_ANALOG 1 MOD1_AUD_ANA_R 2 MOD1_AUD_ANA_L 3 4 MOD1_nSHUTD MOD1_AUD_CLK MOD_UART_RTS MOD1_nSHUTD MOD1_GPIO3 Header_1x4_100_430L Stellaris LM3S9B96 EPI header J6 LM3S9B96 EPI Header R5 100K C 9 10 11 12 13 14 15 16 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 EPI02 8 7 6 5 4 3 2 1 EPI04 EPI05 PB2 PB3 +3.3V 27 EPI31 EPI18 EPI15 EPI12 EPI09 EPI11 B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 EPI13 EPI14 EPI16 PB2 PB3 EPI30 9 10 11 12 13 14 15 16 EPI28 EPI19 R2 8 7 6 5 4 3 2 1 MOD2_GPIO0 MOD2_GPIO1 MOD_I2C_SCL AD_I2C_SCL0 AD_I2C_SDA0 MOD_UART_CTS SPI_CS2 27 9 10 11 12 13 14 15 16 EPI17 EPI06 EPI07 EPI01 EPI00 EPI10 R3 27 RECT_DF12A-50DS 8 7 6 5 4 3 2 1 +3.3V Secondary EM header MOD_UART_RTS MOD_I2C_SDA MOD1_GPIO0 MOD1_GPIO1 MOD1_GPIO2 MOD1_GPIO3 SPI_CLK MOD2_nSHUTD MOD_UART_CTS SEC_MOD_SCLK MOD_UART_RX MOD_UART_TX MOD2_GPIO0 MOD_I2C_SDA MOD2_GPIO1 MOD_I2C_SCL SPI_CS2 SPI_CLK SPI_MOSI SPI_MISO B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 CC-P1 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 TFM-110-02-S-D-K-A MOD1_nSHUTD MOD_UART_TX MOD_UART_RX MOD2_GPIO2 MOD2_GPIO3 SPI_MOSI SPI_MISO SPI_CS1 R1 R12 2.7K CC-P2 TFM-110-02-S-D-K-A R13 2.7K +3.3V MOD2 HPA_MB_MODULE_ASSY_RF RF_MODULE-PORT_1A D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 C +3.3V MOD2_AUD_ANA_L MOD2_AUD_ANA_R MOD2_AUD_DATA_OUT J4 RFMOD2_I2S 1 2 MOD2_AUD_CLK 3 MOD2_AUD_FSYNC 4 MOD2_AUD_DATA_IN MOD2_AUD_DATA_OUT 5 6 MOD2_AUD_DATA_IN Header_1x6_100_430L D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 MOD2_AUD_FSYNC MOD2_GPIO2 MOD2_nSHUTD J5 RFMOD2_ANALOG 1 MOD2_AUD_ANA_R 2 MOD2_AUD_ANA_L 3 4 MOD2_AUD_CLK MOD_UART_RTS MOD2_nSHUTD MOD2_GPIO3 Header_1x4_100_430L +3.3V B R6 100K I2C chip to enable adapterboard auto discovery. +3.3V 10K R11 U2 A A0 A1 A2 VSS VCC WP SCL SDA 8 7 6 5 R14 2.7K R15 2.7K C5 1uF WP_I2C AD_I2C_SCL0 AD_I2C_SDA0 CAT24C01 I2C_WP XJ1 Title Shunt_100 Size 3 JPS1 1 A 2 1 2 3 4 B Date: 5 4 3 2 LM3S9B96 EM2 Adapter Document Number Rev DK-LM3S9B96_EM2 Monday, July 12, 2010 Sheet 1 C 1 of 1 Stellaris(R) LM3S9B96 EM2 Expansion Board 86 July 3, 2011 A P P E N D I X H References In addition to this document, the following references are included on the Stellaris DK-LM3S9D96 Development Kit Documentation and Software CD and are also available for download at www.ti.com/stellaris: Stellaris LM3S9D96 Microcontroller Data Sheet Kitronix LCD Data Sheet StellarisWare Driver Library StellarisWare Driver Library User's Manual, publication number SW-DRL-UG Additional references include: FT2232D Dual USB/UART FIFO IC Data sheet, version 0.91, 2006, Future Technology Devices International Ltd. Texas Instruments TLV320AIC23BPM Audio CODEC Data Sheet Information on development tool being used: - RealView MDK web site, www.keil.com/arm/rvmdkkit.asp - IAR Embedded Workbench web site, www.iar.com - Sourcery CodeBench development tools web site, www.codesourcery.com/gnu_toolchains/arm - Code Red Technologies development tools web site, www.code-red-tech.com - Texas Instruments' Code Composer StudioTM IDE web site, www.ti.com/ccs July 3, 2011 87 References 88 July 3, 2011 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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