INTEGRATED CIRCUITS DATA SHEET UDA1334ATS Low power audio DAC with PLL Product specification Supersedes data of 2000 Feb 09 2000 Jul 31 NXP Semiconductors Product specification Low power audio DAC with PLL UDA1334ATS CONTENTS 1 FEATURES 1.1 1.2 1.3 1.4 1.5 General Multiple format data interface DAC digital features Advanced audio configuration PLL system clock generation 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 ORDERING INFORMATION 5 QUICK REFERENCE DATA 6 BLOCK DIAGRAM 7 PINNING 8 FUNCTIONAL DESCRIPTION 8.1 8.1.1 8.1.2 8.2 8.3 8.4 8.5 8.6 8.6.1 8.6.2 8.6.3 System clock Audio mode Video mode Interpolation filter Noise shaper Filter stream DAC Power-on reset Feature settings Digital interface format select De-emphasis control Mute control 2000 Jul 31 9 LIMITING VALUES 10 HANDLING 11 THERMAL CHARACTERISTICS 12 QUALITY SPECIFICATION 13 DC CHARACTERISTICS 14 AC CHARACTERISTICS 14.1 14.2 Analog Timing 15 APPLICATION INFORMATION 16 PACKAGE OUTLINE 17 SOLDERING 17.1 Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods 17.2 17.3 17.4 17.5 2 18 DATA SHEET STATUS 19 DISCLAIMERS NXP Semiconductors Product specification Low power audio DAC with PLL 1 UDA1334ATS FEATURES 1.1 General * 2.4 to 3.6 V power supply voltage * On-board PLL to generate the internal system clock: - Operates as an asynchronous DAC, regenerating the internal clock from the WS signal (called audio mode) - Generates audio related system clock (output) based on 32, 48 or 96 kHz sampling frequency (called video mode). 2 * Integrated digital filter plus DAC APPLICATIONS This audio DAC is excellently suitable for digital audio portable application, specially in applications in which an audio related system clock is not present. * Supports sample frequencies from 16 to 100 kHz in asynchronous DAC mode * No analog post filtering required for DAC * Easy application 3 * SSOP16 package. 1.2 * The UDA1334ATS is a single chip 2 channel digital-to-analog converter employing bitstream conversion techniques, including an on-board PLL. The extremely low power consumption and low voltage requirements make the device eminently suitable for use in low-voltage low-power portable digital audio equipment which incorporates a playback function. Multiple format data interface I2S-bus and LSB-justified format compatible * 1fs input data rate. 1.3 DAC digital features The UDA1334ATS supports the I2S-bus data format with word lengths of up to 24 bits and the LSB-justified serial data format with word lengths of 16, 20 and 24 bits. * Digital de-emphasis for 44.1 kHz sampling frequency * Mute function. 1.4 The UDA1334ATS has basic features such as de-emphasis (44.1 kHz sampling frequency, only supported in audio mode) and mute. Advanced audio configuration * High linearity, wide dynamic range and low distortion. 1.5 GENERAL DESCRIPTION PLL system clock generation * Integrated low jitter PLL for use in applications in which there is digital audio data present but the system cannot provide an audio related system clock. This mode is called audio mode. * The PLL can generate 256 x 48 kHz and 384 x 48 kHz from a 27 MHz input clock. This mode is called video mode. 4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION UDA1334ATS SSOP16 plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369-1 2000 Jul 31 3 NXP Semiconductors Product specification Low power audio DAC with PLL 5 UDA1334ATS QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA DAC analog supply voltage VDDD digital supply voltage IDDA DAC analog supply current IDDD Tamb digital supply current 2.4 3.0 3.6 V 2.4 3.0 3.6 V audio mode - 3.5 - mA video mode - 3.5 - mA audio mode - 2.5 - mA video mode - 4.5 - mA -40 - +85 C ambient temperature Digital-to-analog converter (VDDA = VDDD = 3.0 V) Vo(rms) output voltage (RMS value) at 0 dB (FS) digital input; note 1 - 900 - mV (THD+N)/S total harmonic distortion-plus-noise to signal ratio fs = 44.1 kHz; at 0 dB - -90 - dB fs = 44.1 kHz; at -60 dB; A-weighted - -40 - dB fs = 96 kHz; at 0 dB - -85 - dB fs = 96 kHz; at -60 dB; A-weighted - -38 - dB fs = 44.1 kHz; code = 0; A-weighted - 100 - dB fs = 96 kHz; code = 0; A-weighted - 98 - dB - 100 - dB audio mode - 18 - mW video mode - 24 - mW S/N CS signal-to-noise ratio channel separation Power dissipation (at fs = 44.1 kHz) P power dissipation Note 1. The output voltage of the DAC scales proportionally to the power supply voltage. 2000 Jul 31 4 NXP Semiconductors Product specification Low power audio DAC with PLL 6 UDA1334ATS BLOCK DIAGRAM VSSD VDDD handbook, full pagewidth 4 BCK WS DATAI 1 2 3 5 DIGITAL INTERFACE MUTE DEEM/CLKOUT 10 PLL DE-EMPHASIS UDA1334ATS SYSCLK/PLL1 PLL0 6 7 8 11 INTERPOLATION FILTER 9 SFOR1 SFOR0 NOISE SHAPER VOUTL DAC DAC 14 13 15 VDDA VSSA Fig.1 Block diagram. 2000 Jul 31 5 16 12 Vref(DAC) VOUTR MGL973 NXP Semiconductors Product specification Low power audio DAC with PLL 7 UDA1334ATS PINNING SYMBOL PIN PAD TYPE DESCRIPTION BCK 1 5 V tolerant digital input pad bit clock input WS 2 5 V tolerant digital input pad word select input DATAI 3 5 V tolerant digital input pad serial data input VDDD 4 digital supply pad digital supply voltage VSSD 5 digital ground pad digital ground SYSCLK/PLL1 6 5 V tolerant digital input pad system clock input in video mode/PLL mode control 1 input in audio mode SFOR1 7 5 V tolerant digital input pad serial format select 1 input MUTE 8 5 V tolerant digital input pad mute control input DEEM/CLKOUT 9 5 V tolerant digital input/output pad de-emphasis control input in audio mode/clock output in video mode PLL0 10 3-level input pad; note 1 PLL mode control 0 input SFOR0 11 digital input pad; note 1 serial format select 0 input Vref(DAC) 12 analog pad DAC reference voltage VDDA 13 analog supply pad DAC analog supply voltage VOUTL 14 analog output pad DAC output left VSSA 15 analog ground pad DAC analog ground VOUTR 16 analog output pad DAC output right Note 1. Because of test issues these pads are not 5 V tolerant and both pads should be at power supply voltage level or at a maximum of 0.5 V above that level. handbook, halfpage BCK 1 16 VOUTR WS 2 15 VSSA DATAI 3 VDDD 4 14 VOUTL UDA1334ATS VSSD 5 13 VDDA 12 Vref(DAC) SYSCLK/PLL1 6 11 SFOR0 SFOR1 7 10 PLL0 MUTE 8 9 DEEM/CLKOUT MGL972 Fig.2 Pin configuration. 2000 Jul 31 6 NXP Semiconductors Product specification Low power audio DAC with PLL 8 UDA1334ATS FUNCTIONAL DESCRIPTION 8.1 Table 2 System clock The UDA1334ATS incorporates a PLL capable of generating the system clock. The UDA1334ATS can operate in 2 modes: * It operates as an asynchronous DAC, which means the device regenerates the internal clocks using a PLL from the incoming WS signal. This mode is called audio mode. Clock output selection in video mode PLL0 SELECTION MID 12.228 MHz clock; note 1 HIGH 18.432 MHz clock; note 2 LOW audio mode Notes 1. The supported sampling frequencies are: 96, 48 and 24 kHz or 64, 32 and 16 kHz. * It generates the internal clocks from a 27 MHz clock input, based on 32, 48 and 96 kHz sampling frequencies. This mode is called video mode. 2. The supported sampling frequencies are: 96, 48 and 24 kHz; 72 and 36 kHz or 32 kHz. In video mode, the digital audio input is slave, which means that the system must generate the BCK and WS signals from the output clock available at pin CLKOUT of the UDA1334ATS. The digital audio signals should be frequency locked to the CLKOUT signal. 8.2 The interpolation digital filter interpolates from 1fs to 64fs by cascading FIR filters (see Table 3). Table 3 Remarks: 1. The WS edge MUST fall on the negative edge of the BCK at all times for proper operation of the digital I/O data interface Sampling frequency range in audio mode 8.1.2 SELECTION fs = 16 to 50 kHz HIGH fs = 50 to 100 kHz VIDEO MODE In video mode, the master clock is a 27 MHz external clock (as is available in video environment). A clock-out signal is generated at pin DEEM/CLKOUT. The output frequency can be selected using pin PLL0. The output frequency is either 12.228 MHz (256 x 48 kHz) with pin PLL0 being at MID level or 18.432 MHz (384 x 48 kHz) with pin PLL0 being HIGH, as given in Table 2. 2000 Jul 31 VALUE (dB) Pass-band ripple 0fs to 0.45fs 0.02 >0.55fs -50 0fs to 0.45fs >114 Noise shaper The 5th-order noise shaper operates at 64fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a Filter Stream DAC (FSDAC). In audio mode, pin SYSCLK/PLL1 is used to set the sampling frequency range as given in Table 1. LOW CONDITION 8.3 Audio mode is enabled by setting pin PLL0 to LOW. De-emphasis can be activated via pin DEEM/CLKOUT according to Table 5. SYSCLK/PLL1 ITEM Dynamic range AUDIO MODE Table 1 Interpolation filter characteristics Stop band 2. For LSB-justified formats it is important to have a WS signal with a duty factor of 50%. 8.1.1 Interpolation filter 7 NXP Semiconductors Product specification Low power audio DAC with PLL 8.4 UDA1334ATS Filter stream DAC 8.5 The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. No post filter is needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. Power-on reset The UDA1334ATS has an internal Power-on reset circuit (see Fig.3) which resets the test control block. The reset time (see Fig.4) is determined by an external capacitor which is connected between pin Vref(DAC) and ground. The reset time should be at least 1 s for Vref(DAC) < 1.25 V. When VDDA is switched off, the device will be reset again for Vref(DAC) < 0.75 V. During the reset time the system clock should be running. The output voltage of the FSDAC scales proportionally to the power supply voltage. 3.0 VDDD (V) handbook, halfpage 1.5 0 handbook, halfpage 3.0 V t VDDA 13 3.0 VDDA 50 k C1 > 10 F (V) RESET CIRCUIT Vref(DAC) 12 1.5 50 k 0 UDA1334ATS t MGT015 3.0 Vref(DAC) (V) 1.5 1.25 0.75 0 >1 s t MGL984 Fig.3 Power-on reset circuit. 2000 Jul 31 Fig.4 Power-on reset timing. 8 NXP Semiconductors Product specification Low power audio DAC with PLL 8.6 UDA1334ATS Feature settings 8.6.1 DE-EMPHASIS CONTROL 8.6.2 This function is only available in audio mode. In that case, pin DEEM/CLKOUT can be used to activate the digital de-emphasis for 44.1 kHz as given in Table 5. DIGITAL INTERFACE FORMAT SELECT The digital audio interface formats (see Fig.5) can be selected via pins SFOR1 and SFOR0 as shown in Table 4. Table 5 For the digital audio interface holds that the BCK frequency can be maximum 64 times WS frequency. DEEM/CLKOUT The WS signal must change at the negative edge of the BCK signal for all digital audio formats. Table 4 De-emphasis control (audio mode) 8.6.3 Data format selection FUNCTION LOW de-emphasis off HIGH de-emphasis on MUTE CONTROL The output signal can be soft muted by setting pin MUTE to HIGH as given in Table 6. SFOR1 SFOR0 LOW LOW I2S-bus input LOW HIGH LSB-justified 16 bits input HIGH LOW LSB-justified 20 bits input MUTE HIGH HIGH LSB-justified 24 bits input LOW mute off HIGH mute on 2000 Jul 31 INPUT FORMAT Table 6 9 Mute control FUNCTION 2 >=8 3 1 2 3 MSB B2 >=8 DATA MSB B2 MSB I2S-BUS FORMAT WS LEFT RIGHT 16 15 1 16 B15 LSB MSB 2 15 2 1 BCK DATA MSB B2 B2 B15 LSB NXP Semiconductors 1 BCK Low power audio DAC with PLL handbook, full pagewidth 2000 Jul 31 RIGHT LEFT WS LSB-JUSTIFIED FORMAT 16 BITS 10 WS LEFT 20 RIGHT 19 18 17 16 15 2 1 20 B19 LSB MSB 19 18 17 16 15 2 1 BCK DATA MSB B2 B3 B4 B5 B6 B2 B3 B4 B5 B6 B19 LSB LSB-JUSTIFIED FORMAT 20 BITS WS LEFT 24 23 22 21 20 RIGHT 19 18 17 16 15 2 1 24 B23 LSB MSB 23 22 21 20 19 18 17 16 15 2 1 BCK DATA MSB B2 B3 B4 B5 B6 B7 B8 B9 B10 B2 B3 B4 B5 B6 B7 B8 B9 B10 B23 LSB MGS752 Product specification Fig.5 Digital audio formats. UDA1334ATS LSB-JUSTIFIED FORMAT 24 BITS NXP Semiconductors Product specification Low power audio DAC with PLL UDA1334ATS 9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT - 4.0 V maximum crystal temperature - 150 C VDD supply voltage Txtal(max) note 1 Tstg storage temperature -65 +125 C Tamb ambient temperature -40 +85 C Ves electrostatic handling voltage human body model; note 2 -2000 +2000 V -250 +250 V Isc(DAC) short-circuit current of DAC output short-circuited to VSSA - 450 mA output short-circuited to VDDA - 300 mA machine model; note 2 note 3 Notes 1. All supply connections must be made to the same power supply. 2. ESD behaviour is tested according to JEDEC II standard. 3. Short-circuit test at Tamb = 0 C and VDDA = 3 V. DAC operation after short-circuiting cannot be warranted. 10 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. 11 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS thermal resistance from junction to ambient in free air VALUE UNIT 145 K/W 12 QUALITY SPECIFICATION In accordance with "SNW-FQ-611-E". 13 DC CHARACTERISTICS VDDD = VDDA = 3.0 V; Tamb = 25 C; RL = 5 k; all voltages with respect to ground (pins VSSA and VSSD); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA DAC analog supply voltage note 1 2.4 3.0 3.6 V VDDD digital supply voltage note 1 2.4 3.0 3.6 V IDDA DAC analog supply current audio mode - 3.5 - mA video mode - 3.5 - mA audio mode - 2.5 - mA video mode - 4.5 - mA IDDD 2000 Jul 31 digital supply current 11 NXP Semiconductors Product specification Low power audio DAC with PLL SYMBOL PARAMETER UDA1334ATS CONDITIONS MIN. TYP. MAX. UNIT Digital input pins: TTL compatible VIH HIGH-level input voltage 2.0 - 5.0 V VIL LOW-level input voltage -0.5 - +0.8 V ILI input leakage current - - 1 A Ci input capacitance - - 10 pF 3-level input: pin PLL0 VIH HIGH-level input voltage 0.9VDDD - VDDD + 0.5 V VIM MID-level input voltage 0.4VDDD - 0.6VDDD V VIL LOW-level input voltage -0.5 - +0.5 V Digital output pins VOH HIGH-level output voltage IOH = -2 mA 0.85VDDD - - V VOL LOW-level output voltage IOL = 2 mA - - 0.4 V Vref(DAC) reference voltage with respect to VSSA 0.45VDD 0.5VDD 0.55VDD Ro(ref) output resistance on pin Vref(DAC) - 25 - k Io(max) maximum output current - 1.6 - mA RL load resistance 3 - - k CL load capacitance - - 50 pF DAC (THD + N)/S < 0.1%; RL = 5 k note 2 V Notes 1. All supply connections must be made to the same external power supply unit. 2. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 must be used to prevent oscillations in the output operational amplifier. 14 AC CHARACTERISTICS 14.1 Analog VDDD = VDDA = 3.0 V; fi = 1 kHz; Tamb = 25 C; RL = 5 k; all voltages with respect to ground (pins VSSA and VSSD); unless otherwise specified. SYMBOL PARAMETER CONDITIONS TYP. UNIT DAC Vo(rms) output voltage (RMS value) Vo (THD + N)/S at 0 dB (FS) digital input; note 1 900 mV unbalance between channels 0.1 dB total harmonic fs = 44.1 kHz; at 0 dB distortion-plus-noise to signal fs = 44.1 kHz; at -60 dB; A-weighted ratio fs = 96 kHz; at 0 dB -90 dB -40 dB -85 dB -38 dB fs = 96 kHz; at -60 dB; A-weighted 2000 Jul 31 12 NXP Semiconductors Product specification Low power audio DAC with PLL SYMBOL UDA1334ATS PARAMETER S/N signal-to-noise ratio CS channel separation PSRR power supply rejection ratio CONDITIONS TYP. fs = 44.1 kHz; code = 0; A-weighted 100 fs = 96 kHz; code = 0; A-weighted fripple = 1 kHz; Vripple = 30 mV (p-p) UNIT dB 98 dB 100 dB 60 dB Note 1. The output voltage of the DAC scales proportionally to the analog power supply voltage. 14.2 Timing VDDD = VDDA = 2.4 to 3.6 V; Tamb = -20 to +85 C; RL = 5 k; all voltages with respect to ground (pins VSSA and VSSD); unless otherwise specified; note 1. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Output clock timing in video mode (see Fig.6) Tsys tCWL tCWH output clock cycle output clock LOW time output clock HIGH time fo = 12.228 MHz - 81.38 - ns fo = 18.432 MHz - 54.25 - ns fo = 12.228 MHz 0.3Tsys - 0.7Tsys ns fo = 18.432 MHz 0.4Tsys - 0.6Tsys ns fo = 12.228 MHz 0.3Tsys - 0.7Tsys ns fo = 18.432 MHz 0.4Tsys - 0.6Tsys ns Serial input data timing (see Fig.7) fBCK bit clock frequency - - 64fs Hz tBCKH bit clock HIGH time 50 - - ns tBCKL bit clock LOW time 50 - - ns tr rise time - - 20 ns tf fall time - - 20 ns tsu(DATAI) set-up time data input 20 - - ns th(DATAI) hold time data input 0 - - ns tsu(WS) set-up time word select 20 - - ns th(WS) hold time word select 10 - - ns Note 1. The typical value of the timing is specified for a sampling frequency of 44.1 kHz. 2000 Jul 31 13 NXP Semiconductors Product specification Low power audio DAC with PLL UDA1334ATS t CWH handbook, full pagewidth MGR984 t CWL Tsys Fig.6 Output clock timing. handbook, full pagewidth WS th(WS) tBCKH tr tsu(WS) tf BCK tsu(DATAI) tBCKL Tcy(BCK) th(DATAI) DATAI MGL880 Fig.7 Serial interface timing. 2000 Jul 31 14 NXP Semiconductors Product specification Low power audio DAC with PLL UDA1334ATS 15 APPLICATION INFORMATION digital supply voltage analog supply voltage handbook, full pagewidth R7 1 C9 SYSCLK/PLL1 47 F (16 V) 47 F (16 V) C10 C6 100 nF (63 V) VSSA 100 nF (63 V) 15 VDDA 13 R6 1 C5 VSSD 5 VDDD 4 6 14 BCK WS DATAI SFOR1 SFOR0 MUTE DEEM/CLKOUT PLL0 VOUTL C3 47 F (16 V) 1 2 R3 R1 220 k C1 3 7 11 UDA1334ATS 16 8 9 VOUTR C4 47 F (16 V) 12 left output 100 10 nF (63 V) R4 right output 100 R2 220 k C2 10 nF (63 V) Vref(DAC) C8 100 nF (63 V) 10 C7 47 F (16 V) MGL971 In audio mode, the system does not need to supply a system clock. Fig.8 Audio mode application diagram. 2000 Jul 31 15 NXP Semiconductors Product specification Low power audio DAC with PLL UDA1334ATS digital supply voltage analog supply voltage R7 1 C9 27 MHz clock R5 SYSCLK/PLL1 47 47 F (16 V) 47 F (16 V) C10 C6 100 nF (63 V) VSSA 100 nF (63 V) 15 R6 1 C5 VDDA VSSD 13 5 VDDD 4 6 14 BCK WS DATAI I2S-bus (master) SFOR1 SFOR0 VOUTL C3 47 F (16 V) 1 2 MUTE audio clock PLL0 R1 220 k C1 3 7 11 UDA1334ATS 16 VOUTR C4 47 F (16 V) MPEG DECODER DEEM/CLKOUT R3 8 9 12 left output 100 10 nF (63 V) R4 right output 100 R2 220 k C2 10 nF (63 V) Vref(DAC) C8 100 nF (63 V) 10 C7 47 F (16 V) handbook, full pagewidth MGL974 In video mode, a clock output signal is generated by the UDA1334ATS which is master for the audio signals in the system; the digital audio interface is slave, which means the system must generate the BCK and WS signal from the UDA1334ATS output clock. Fig.9 Video mode application diagram. 2000 Jul 31 16 NXP Semiconductors Product specification Low power audio DAC with PLL UDA1334ATS 16 PACKAGE OUTLINE SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm D SOT369-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index Lp L 1 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.5 0.15 0.00 1.4 1.2 0.25 0.32 0.20 0.25 0.13 5.3 5.1 4.5 4.3 0.65 6.6 6.2 1 0.75 0.45 0.65 0.45 0.2 0.13 0.1 0.48 0.18 10 o 0 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT369-1 2000 Jul 31 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-152 17 o NXP Semiconductors Product specification Low power audio DAC with PLL UDA1334ATS 17 SOLDERING 17.1 If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. 17.2 The footprint must incorporate solder thieves at the downstream end. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 17.3 17.4 Wave soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. 2000 Jul 31 Manual soldering When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 18 NXP Semiconductors Product specification Low power audio DAC with PLL 17.5 UDA1334ATS Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO REFLOW(1) suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2000 Jul 31 19 NXP Semiconductors Product specification Low power audio DAC with PLL UDA1334ATS 18 DATA SHEET STATUS DOCUMENT STATUS(1) PRODUCT STATUS(2) DEFINITION Objective data sheet Development This document contains data from the objective specification for product development. Preliminary data sheet Qualification This document contains data from the preliminary specification. Product data sheet Production This document contains the product specification. Notes 1. Please consult the most recently issued document before initiating or completing a design. 2. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19 DISCLAIMERS property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe 2000 Jul 31 20 NXP Semiconductors Product specification Low power audio DAC with PLL UDA1334ATS Limiting values Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Quick reference data The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 2000 Jul 31 21 NXP Semiconductors provides High Performance Mixed Signal and Standard Product solutions that leverage its leading RF, Analog, Power Management, Interface, Security and Digital Processing expertise Customer notification This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content, except for package outline drawings which were updated to the latest version. Contact information For additional information please visit: http://www.nxp.com For sales offices addresses send e-mail to: salesaddresses@nxp.com (c) NXP B.V. 2010 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753503/25/02/pp22 Date of release: 2000 Jul 31 Document order number: 9397 750 07238