UDA1334ATS/N2 - NXP Semiconductors

DATA SH EET

Product specification

Supersedes data of 2000 Feb 09 2000 Jul 31

INTEGRATED CIRCUITS

UDA1334ATS

Low power audio DAC with PLL

2000 Jul 31 2

NXP Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

CONTENTS

1 FEATURES

1.1 General

1.2 Multiple format data interface

1.3 DAC digital features

1.4 Advanced audio configuration

1.5 PLL system clock generation

2 APPLICATIONS

3 GENERAL DESCRIPTION

4 ORDERING INFORMATION

5 QUICK REFERENCE DATA

6 BLOCK DIAGRAM

7 PINNING

8 FUNCTIONAL DESCRIPTION

8.1 System clock

8.1.1 Audio mode

8.1.2 Video mode

8.2 Interpolation filter

8.3 Noise shap er

8.4 Filter stream DAC

8.5 Power-on reset

8.6 Feature settings

8.6.1 Digital interface format select

8.6.2 De-emphasis contr ol

8.6.3 Mute control

9 LIMITING VALUES

10 HANDLING

11 THERMAL CHARACTERISTI CS

12 QUALITY SPECIFICATION

13 DC CHARACTERISTICS

14 AC CHARACTERISTICS

14.1 Analog

14.2 Timing

15 APPLICATION INFORMATION

16 PACKAGE OUTLINE

17 SOLDERING

17.1 Introduction to soldering surface mount

packages

17.2 Reflow soldering

17.3 Wave soldering

17.4 Manual soldering

17.5 Suitability of surface mount IC packages for

wave and reflow soldering methods

18 DATA SHEET STATUS

19 DISCLAIMERS

2000 Jul 31 3

NXP Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

1 FEATURES

1.1 General

•2.4 to 3.6 V power supply voltage

•On-board PLL to generate the internal sy s tem clock:

– Operates as an asynchronous DAC, regenerating the

internal clock from the WS signal (called audio mode)

– Generates audio related system clock (output) based

on 32, 48 or 96 kHz sampling frequency (called video

mode).

•Integrated digital filter plus DAC

•Supports sample frequencies from 16 to 100 kHz in

asynchronous DAC mode

•No analog post filtering required for DAC

•Easy application

•SSOP16 package.

1.2 Multiple for ma t data inter f ac e

•I2S-bus and LSB-justified format compatible

•1fs input data rate.

1.3 DAC digital features

•Digital de-emphasis for 44.1 kHz sampling frequency

•Mute function.

1.4 Advanced audio configuration

•High linearity, wide dynamic range and low distortion.

1.5 PLL system clock generation

•Integrated low jitter PLL for use in applications in which

there is di gital audio data present b ut the system cannot

provide an audio related system clock. T his mode is

called audio mode.

•The PLL can generate 256 ×48 kHz and 384 ×48 kHz

from a 27 MHz input clock. This mode is called video

mode.

2 APPLICATIONS

This audio DAC is excellently suitable for digital audio

portable application, specially in applications in which an

audio related system clock is not present.

3 GENERAL DESCRIPTION

The UDA1334ATS is a single chip 2 ch annel

digital-to-analog co nverter employing bitstream

conversion techniques, including an on-board PLL.

The extremely low power consumptio n and low voltage

requirements make the device eminently suitable for use in

low-voltage low -p o we r po rtable digital audio eq uipment

which incorporates a play back function.

The UDA1334ATS supports the I2S-bus data format with

word lengths of up to 24 bits and the LSB-justified serial

data format with word length s of 16, 20 and 24 bits.

The UDA1334ATS has basic features such as

de-emphasis ( 44.1 kHz sampling frequenc y, only

supported in au dio mode ) and mute.

4 ORDERING INFORMATION

TYPE

NUMBER PACKAGE

NAME DESCRIPTION VERSION

UDA1334ATS SSOP16 plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369-1

2000 Jul 31 4

NXP Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

5 QUICK REFERENCE DATA

Note

1. The output volta ge of the DAC scales proportion ally to the power supply voltage.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

VDDA DAC analog supply voltage 2.4 3.0 3.6 V

VDDD digital supply voltage 2.4 3.0 3.6 V

IDDA DAC analog supply current audio mode −3.5 −mA

video mode −3.5 −mA

IDDD digital supply current audio mode −2.5 −mA

video mode −4.5 −mA

Tamb ambient temperature −40 −+85 °C

Digital-to-analog converter (VDDA =V

DDD =3.0V)

Vo(rms) output voltage (RMS value) at 0 dB (FS) digital input;

note 1 −900 −mV

(THD+N)/S total harmonic distortion-plus-noise to

signal ratio fs= 44.1 kHz ; at 0 dB −−90 −dB

fs= 44.1 kHz ; at −60 dB;

A-weighted −−40 −dB

fs=96kHz; at 0dB −−85 −dB

fs=96kHz; at −60 dB;

A-weighted −−38 −dB

S/N signal-to-noise ratio fs= 44.1 kHz; code = 0;

A-weighted −100 −dB

fs=96kHz; code=0;

A-weighted −98 −dB

αCS channel separation −100 −dB

Power dissipation (at fs=44.1kHz)

P power dissipation audio mode −18 −mW

video mode −24 −mW

2000 Jul 31 5

NXP Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

6 BLOCK DIAGRAM

handbook, full pagewidth

MGL973

DAC

UDA1334ATS

NOISE SHAPER

INTERPOLATION FILTER

DE-EMPHASIS

DAC

DIGITAL INTERFACE PLL

13 12

VOUTR

BCK

VSSA

VOUTL

DATAI

VDDA

VDDD

PLL0

Vref(DAC)

VSSD

SFOR0

SYSCLK/PLL1 8

MUTE 9

DEEM/CLKOUT

SFOR1

Fig.1 Block diagram.

2000 Jul 31 6

NXP Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

7 PINNING

Note

1. Because of test issues these pads are not 5 V tolerant and both pads should be at power supply voltage level or at

a maximum of 0.5 V above that level.

SYMBOL PIN PAD TYPE DESCRIPTION

BCK 1 5 V tolerant digital input pad bit clock input

WS 2 5 V tolerant digital input pad word select input

DATAI 3 5 V tolerant digital input pad serial data input

VDDD 4 digital supply pad digital supply voltage

VSSD 5 digital ground pad digital ground

SYSCLK/PLL1 6 5 V tolerant digital input pad system clock input in video mode/PLL

mode control 1 input in audio mode

SFOR1 7 5 V tolerant digital input pad serial format se lect 1 input

MUTE 8 5 V tolerant digital input pad mute control input

DEEM/CLKOUT 9 5 V tolerant digital input/output pad de-emphasis control input in audio

mode/clock output in video mode

PLL0 10 3-level input pad; note 1 PLL mode control 0 input

SFOR0 11 digital input pad; note 1 serial format select 0 input

Vref(DAC) 12 analog pad DAC referenc e vo ltage

VDDA 13 analog supp ly pad DAC analog supply vo ltage

VOUTL 14 analog output pad DAC output left

VSSA 15 analog ground pad DAC analog ground

VOUTR 16 analog output pad DAC output right

handbook, halfpage

UDA1334ATS

MGL972

VOUTR

BCK

VSSA

VOUTL

DATAI

VDDA

VDDD

Vref(DAC)

VSSD

SFOR0SYSCLK/PLL1

PLL0SFOR1

DEEM/CLKOUTMUTE

Fig.2 Pin configuration.

2000 Jul 31 7

NXP Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

8 FUNCTIONAL DESCRIPTION

8.1 System clock

The UDA1334ATS incor porates a PLL capable of

generating the sys t em clock. The UDA1334ATS can

operate in 2 modes:

•It operates as an asynch ronous D AC, wh ich mean s the

device regene rates the interna l clocks using a PLL f rom

the incoming WS signal. This mode is called audio

mode.

•It generates the internal clocks from a 27 MHz clock

input, based on 32, 48 and 96 kHz sampling

frequencies. This mode is called video mode.

In video mode, the digital audio input is s l av e, which

means that the system must generate the BCK an d

WS signals from the output clock available at pin CLKOUT

of the UDA1334ATS. The digital audio signals should be

frequency locked to the CLKO UT s i gnal.

Remarks:

1. The WS edge MUST fall on the negative edge of the

BCK at all times for proper oper ation of the digital I/O

data interface

2. For LSB-justified formats it is important to have a WS

signal with a duty factor of 50%.

8.1.1 AUDIO MODE

Audio mode is enabled by setting pin PLL0 to LOW.

De-emphasis can be activated via pin DEEM/CLKOUT

according to Table 5.

In audio mode, pin SYSCLK/PLL1 is used to set the

sampling freque ncy range as given in Table 1.

Table 1 Sampling frequency range in audio mode

8.1.2 VIDEO MODE

In video mode, the master clock is a 27 MHz external clock

(as is available in video environment). A clock-out signal is

generated at pin DEEM/CLKOUT. The outpu t fre quency

can be selected using pin PLL0. The output frequency is

either 12.228 MHz (256 ×48 kHz) with pin PLL0 being at

MID level or 18.432 MHz (384 ×48 kHz) with pin PLL0

being HIGH, as given in Table 2.

Table 2 Clock output selection in video mode

Notes

1. The supp or te d sampling frequencies are:

96, 48 and 24 k Hz or 64, 32 and 16 kHz.

2. The supp or te d sampling frequencies are:

96, 48 and 24 kHz; 72 and 36 kHz or 32 kHz.

8.2 Interpolation filter

The interpolation digital filter interpolates from 1fsto 64fs

by cascading FIR filters (see Table 3).

Table 3 Interpola tio n filter characteristics

8.3 Noise shaper

The 5th-order noise shaper op erates at 64fs. It shifts

in-band quantization noise to frequenc ie s w ell above the

audio band. This noise shaping technique enables high

signal-to-noise ratios to be achiev ed. The noise sha per

output is converted into an analog signal using a

Filter Stream DAC (FSDAC).

SYSCLK/PLL1 SELECTION

LOW fs=16to50kHz

HIGH fs=50to100kHz

PLL0 SELECTION

MID 12.228 MHz clock; note 1

HIGH 18.432 MHz clock; note 2

LOW audio mode

ITEM CONDITION VALUE (dB)

Pass-band ripp le 0fsto 0.45fs±0.02

Stop band >0.55fs−50

Dynamic range 0fsto 0.45fs>114

2000 Jul 31 8

NXP Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

8.4 Filter strea m D AC

The FSDAC is a semi-digital reconstruction filter that

converts the 1-bit data stream of the noise shaper to an

analog output vo ltage. The filter coefficients are

implemented as current sources and are summed at virtual

ground of th e output opera tional amplifier. In t his way very

high signal-to-noise performance and low clock jitter

sensitivity is achieved . No post filter is needed due to the

inherent filter function of the D A C. On-board amplifiers

convert the FSDAC output current to an output voltage

signal capable of driving a line output.

The output voltage of the FSDAC scales proportionally to

the power supply voltage.

8.5 Power-on reset

The UDA1334ATS has an inte rnal Power-on reset circuit

(see Fig.3) which resets the test control block.

The reset time (see Fig.4) is determined by an external

capacitor which is connected between pin Vref(DAC) and

ground. The reset time should be at least 1 μs for

Vref(DAC) < 1.25 V. When VDDA is s witched off, the device

will be reset again for Vref(DAC) <0.75 V.

During the reset time the system clock sh ould be running.

handbook, halfpage VDDA

Vref(DAC)

3.0 V 13

MGT015

UDA1334ATS

C1 >

10 μF

RESET

CIRCUIT

50 kΩ

Fig.3 Power-on reset circuit.

handbook, halfpage

3.0

VDDD

(V)

1.5

3.0

VDDA

(V)

1.5

3.0

Vref(DAC)

(V)

1.5

1.25

0.75

MGL984

>1 μs

Fig.4 Power-on reset timing.

2000 Jul 31 9

NXP Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

8.6 Feature settings

8.6.1 DIGITAL INTERFACE FORMAT SELECT

The digital audio interface formats (see Fig.5) can be

selected via pins SFOR1 and SFOR0 as shown in

Table 4.

For the digital audio interface holds that the

BCK frequency can be maximum 64 times WS frequency.

The WS signal must change at the negative edge of the

BCK signal for all digital audio formats.

Table 4 Data format selection

8.6.2 DE-EMPHASIS CONTROL

This function is only available in audio mode. In that case,

pin DEEM/CLKOUT can be used to activate the digital

de-emphasis for 44.1 kHz as given in Table 5.

Table 5 De-emphasis control (audio mode)

8.6.3 MUTE CONTROL

The output signal can be soft muted by setting pin MUTE

to HIGH as given in Table 6.

Table 6 Mute control

SFOR1 SFOR0 INPUT FORMAT

LOW LOW I2S-bus input

LOW HIGH LSB-justified 16 bits input

HIGH LOW LSB-justified 20 bits input

HIGH HIGH LSB-justified 24 bits input

DEEM/CLKOUT FUNCTION

LOW de-emphasis off

HIGH de-emphasis on

MUTE FUNCTION

LOW mute off

HIGH mute on

2000 Jul 31 10

NXP Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

ndbook, full pagewidth

MGS75

B5 B6 B7 B8 B9 B10

LEFT

LSB-JUSTIFIED FORMAT 24 BITS

ATA

RIGHT

1518 1720 1922 212324 21

B3 B4

MSB B2 B23 LSB

B5 B6 B7 B8 B9 B10

1518 1720 1922 212324 21

B3 B4

MSB B2 B23 LSB

MSB B2 B3 B4 B5 B6

LEFT

LSB-JUSTIFIED FORMAT 20 BITS

ATA

RIGHT

1518 1720 19 2 1

B19 LSB

MSB B2 B3 B4 B5 B6

1518 1720 19 2 1

B19 LSB

MSB B2

LEFT

LSB-JUSTIFIED FORMAT 16 BITS

ATA

RIGHT

15 2 1

B15 LSB

MSB B2

15 2 1

B15 LSB

MSB MSBB2

21> = 812 3

LEFT

I2S-BUS FORMAT

BCK

ATA

RIGHT

3> = 8

MSB B2

Fig.5 Digital audio formats.

2000 Jul 31 11

NXP Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

9 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

Notes

1. All supply conn ec tions must be made to the same power supply.

2. ESD behaviour is tested ac cording to JEDEC II standard.

3. Short-circuit test at Tamb =0°C and VDDA = 3 V. DAC operation after short-circuiting cannot be warranted.

10 HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is

desirabl e to tak e no rmal precautions ap pr opriate to handlin g MOS de vice s.

11 THERMAL CHARACTERISTICS

12 QUALITY SPECIFICATION

In accordance with “SNW-FQ-611-E”.

13 DC CHARACTERISTICS

VDDD =V

DDA =3.0V; T

amb =25°C; RL=5kΩ; all voltages with respec t to ground (pins VSSA and VSSD); unless

otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VDD supply voltage note 1 −4.0 V

Txtal(max) maximum crystal

temperature −150 °C

Tstg storage temperature −65 +125 °C

Tamb ambient temperature −40 +85 °C

Ves electrostatic handling voltage human body model; note 2 −2000 +2000 V

machine model; note 2 −250 +250 V

Isc(DAC) short-circuit current of DAC note 3

output short-circuited to VSSA −450 mA

output short-circuited to VDDA −300 mA

SYMBOL PARAMETER CONDITIONS VALUE UNIT

Rth(j-a) thermal resistance from junction to ambient in free air 145 K/W

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

VDDA DAC analog supply vo ltage note 1 2.4 3.0 3.6 V

VDDD digital supply voltage note 1 2.4 3.0 3.6 V

IDDA DAC analog supply current audio mode −3.5 −mA

video mode −3.5 −mA

IDDD digital supply current audio mode −2.5 −mA

video mode −4.5 −mA

2000 Jul 31 12

NXP Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

Notes

1. All supply connections must be made to the same external power supply unit.

2. When the DAC drives a capacitive load above 50 pF, a series resist ance of 100 Ω must be used to prevent

oscillations in the output operational amplifier.

14 AC CHARACTERISTICS

14.1 Analog

VDDD =V

DDA =3.0V; f

i=1kHz; T

amb =25°C; RL=5kΩ; all voltages with respect to ground (pins VSSA and VSSD);

unless otherwise sp ecified.

Digital input pins: TTL compatible

VIH HIGH-level input voltage 2.0 −5.0 V

VIL LOW-level input voltage −0.5 −+0.8 V

⎪ILI⎪input leakage current −−1μA

Ciinput capacitance −−10 pF

3-level input: pin PLL0

VIH HIGH-level input voltage 0.9VDDD −VDDD +0.5 V

VIM MID-level input voltage 0.4VDDD −0.6VDDD V

VIL LOW-level input voltage −0.5 −+0.5 V

Digital output pins

VOH HIGH-level output voltage IOH =−2mA 0.85V

DDD −− V

VOL LOW-level output voltage IOL =2mA −−0.4 V

DAC

Vref(DAC) re ference voltage with respect to VSSA 0.45VDD 0.5VDD 0.55VDD V

Ro(ref) output resistance on

pin Vref(DAC)

−25 −kΩ

Io(max) maximum output current (THD + N)/S < 0.1%;

RL=5kΩ

−1.6 −mA

RLload resistance 3 −− kΩ

CLload capacitance note 2 −−50 pF

SYMBOL PARAMETER CONDITIONS TYP. UNIT

DAC

Vo(rms) output voltage (RMS value) at 0 dB (FS) dig ital input; note 1 900 mV

ΔVounbalance between channels 0.1 dB

(THD + N)/S total harmonic

distortion-plus-noise to signal

ratio

fs=44.1kHz; at 0dB −90 dB

fs=44.1kHz; at −60 dB; A-weighted −40 dB

fs=96kHz; at 0dB −85 dB

fs=96kHz; at −60 dB; A-weighted −38 dB

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

2000 Jul 31 13

NXP Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

Note

1. The output volta ge of the DAC scales proportionally to the ana log power supply voltage .

14.2 Timing

VDDD =V

DDA = 2.4 to 3.6 V; Tamb =−20 to +85 °C; RL=5kΩ; all voltages with respect to ground (pins VSSA and VSSD);

unless otherwise specified; note 1.

Note

1. The typical value of the timing is sp ecified for a sampling frequency of 44.1 kHz.

S/N signal-to-noise ratio fs= 44.1 kHz; code = 0; A-weighted 100 dB

fs= 96 kHz; code = 0; A-weighted 98 dB

αCS channel separation 100 dB

PSRR power supply rejection ratio fripple = 1 kHz; Vripple = 30 mV (p-p) 60 dB

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Output clock timing in video mode (see Fig.6)

Tsys output clock cycle fo= 12.228 MHz −81.38 −ns

fo= 18.432 MHz −54.25 −ns

tCWL output clock LOW time fo= 12.228 MHz 0.3Tsys −0.7Tsys ns

fo= 18.432 MHz 0.4Tsys −0.6Tsys ns

tCWH output clock HIGH time fo= 12.228 MHz 0.3Tsys −0.7Tsys ns

fo= 18.432 MHz 0.4Tsys −0.6Tsys ns

Serial input data timing (see Fig.7)

fBCK bit clock frequency −−64fsHz

tBCKH bit clock HIGH time 50 −−ns

tBCKL bit clock LOW time 50 −−ns

trrise time −−20 ns

tffall time −−20 ns

tsu(DATAI) set-up time data input 20 −−ns

th(DATAI) hold time data input 0 −−ns

tsu(WS) set-up time word select 20 −−ns

th(WS) hold time word select 10 −−ns

SYMBOL PARAMETER CONDITIONS TYP. UNIT

2000 Jul 31 14

NXP Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

handbook, full pagewidth

MGR984

Tsys

tCWH

tCWL

Fig.6 Output clock timing.

handbook, full pagewidth

MGL880

th(WS)

tsu(WS)

tsu(DATAI) th(DATAI)

tBCKH

tBCKL

Tcy(BCK)

BCK

DATAI

Fig.7 Serial interface timing.

2000 Jul 31 15

NXP Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

15 APPLICATION INFORMATION

handbook, full pagewidth

MGL971

UDA1334ATS

SYSCLK/PLL1

BCK

DATAI

14 VOUTL R3

100 Ω

220 kΩ

16 VOUTR R4

100 Ω

220 kΩ

SFOR1

SFOR0

DEEM/CLKOUT

PLL0

MUTE

47 μF

(16 V)

47 μF

(16 V)

C3 left

output

right

output

12 Vref(DAC)

47 μF

(16 V)

100 nF

(63 V)

VDDD

VSSD

1 Ω

digital

supply voltage

15 13

VSSA VDDA

1 Ω

47 μF

(16 V)

C10

100 nF

(63 V) 100 nF

(63 V)

analog

supply voltage

47 μF

(16 V)

C1 10 nF

(63 V)

10 nF

(63 V)

Fig.8 Audio mode application diagram.

In audio mode, the system does not need to supply a system clock.

2000 Jul 31 16

NXP Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

handbook, full pagewidth

MGL974

47 Ω

UDA1334ATS

SYSCLK/PLL1

27 MHz

clock

BCK

DATAI

14 VOUTL R3

100 Ω

220 kΩ

16 VOUTR R4

100 Ω

220 kΩ

SFOR1

SFOR0

audio clock

I2S-bus

(master)

DEEM/CLKOUT

PLL0

MUTE

MPEG

DECODER 47 μF

(16 V)

47 μF

(16 V)

C3 left

outp

right

outp

12 Vref(DAC)

47 μF

(16 V)

100 nF

(63 V)

VDDD

VSSD

1 Ω

digital

supply voltage

15 13

VSSA VDDA

1 Ω

47 μF

(16 V)

C10

100 nF

(63 V) 100 nF

(63 V)

analog

supply voltage

47 μF

(16 V)

C1 10 nF

(63 V)

10 nF

(63 V)

Fig.9 Video mode application dia gr am.

In video mode, a clock outpu t signal is gen erated by the UDA1334ATS which is master for the audio signals in the system; the digital audio interface is

slave, which means the system must generate the BCK and WS signal from the UDA1334ATS output clock.

2000 Jul 31 17

NXP Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

16 PACKAGE OUTLINE

UNIT A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.00 1.4

1.2 0.32

0.20 0.25

0.13 5.3

5.1 4.5

4.3 0.65 6.6

6.2 0.65

0.45 0.48

0.18 10

0.130.2 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.

0.75

0.45

SOT369-1 MO-152 99-12-27

03-02-19

yHE

detail X

vMA

(A )

0.25

16 9

pin 1 index

0 2.5 5 mm

scale

SOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369

-1

max.

1.5

2000 Jul 31 18

NXP Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

17 SOLDERING

17.1 Introduction to soldering surface mount

packages

This text gives a very brief insight to a complex technology.

A more in-depth acco un t of sold er ing ICs can be found in

our “Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).

There is no soldering method tha t is idea l for all surface

mount IC packages. Wave soldering is not always suitable

for surface mount ICs, or for printed-circuit boards with

high population dens ities. In these situations reflow

soldering is often used.

17.2 Reflow solderin g

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-s yringe dispensin g before package placement.

Several methods exist for reflowing; for example,

infrared/convection heating in a conveyor ty pe oven.

Throughput times (preheating, soldering and cooling) vary

between 100 and 200 sec onds depending on heating

method.

Typical reflow peak temperatur es range from

215to250°C. The top-surface temperature of the

packages sh ould preferable be kept below 230 °C.

17.3 W ave soldering

Conventional single wave soldering is not recommended

for surface mount devices (SMDs) or printed-circuit boards

with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering

method was specifically developed.

If wave soldering is used the following conditions must be

observed for optimal results:

•Use a double-wa ve soldering meth od comprising a

turbulent wave with high up ward pressure followed by a

smooth laminar wave.

•For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint

longitudinal axi s is preferred to be parallel to the

transport direction of the printed-circuit board;

– smaller than 1.27 mm, the foo tprint longitudinal axis

must be parallel to the transport direction of the

printed-circuit board .

The footprint must incorporate solder thieves at the

downstream end.

•For packages with leads on four sides, the footprint must

be plac ed at a 45° angle to the transp ort direction of the

printed-circuit board. The footprint must incorporate

solder thieves downstream and at the s id e corners.

During placement and before soldering, the package must

be fixed with a droplet of adh esive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

17.4 Manual soldering

Fix the component by first soldering two

diagonally-opposite end leads. Use a low voltage (24 V or

less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 seconds at up to

300 °C.

When using a dedicated tool, all other leads can be

soldered in one ope ration within 2 t o 5 seconds between

270 and 320 °C.

2000 Jul 31 19

NXP Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

17.5 Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with res pect to time) and body size of the package, there is a risk that internal or external pack age

cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Pac king Methods”.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be place d a t a 4 5° angle to the s old er wave direction.

The package footprint must incorporate solder thieves downstre am and at the side corne rs .

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

PACKAGE SOLDERING METHOD

WAVE REFLOW(1)

BGA, LFBGA, SQFP, TFBGA not suitable suitable

HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable(2) suitable

PLCC(3), SO, SOJ suitable suitable

LQFP, QFP, TQFP not recommended(3)(4) suitable

SSOP, TSSOP, VSO not recommended(5) suitable

2000 Jul 31 20

NXP Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

18 DATA SHEET STATUS

Notes

1. Please consult the most recently issued document before initiating or completing a design.

2. The product s ta tus of device(s) described in this document may have changed since this document was published

and may differ in case of multiple devices. The latest product status information is available on the Internet at

URL http://www.nxp.com.

DOCUMENT

STATUS(1) PRODUCT

STATUS(2) DEFINITION

Objective data sheet Development This document contains data from the objective specification for product

development.

Preliminary data sheet Qualification This document contains data from the preliminary specification.

Product data sheet Produc tio n This document contains the pr oduct specification.

19 DISCLAIMERS

Limited warranty and liability ⎯ Information in this

document is believed to be accurate and reliab le .

However, NXP Semiconduc tors does not give any

representations or warranties, expressed or implied, as to

the accuracy or completeness of such information and

shall have no liability for the consequences of use of such

information.

In no event shall NXP Semiconductors be liable for any

indirect, incidental, punitive, special or conseq uential

damages (including - without limitation - lost profits, lost

savings, busin es s interru ption, costs related to the

removal or replacement of any products or rework

charges) whether or not such damages are based on tort

(including negligence), warranty, breach of contract or any

other legal theory.

Notwithstanding any damages that customer might incur

for any reason whatsoever, NXP Semiconductors’

aggregate and cu mulative liability towards customer for

the products described herein shall be limited in

accordance with the Terms and conditions of commercial

sale of NXP Semiconductors.

Right to make changes ⎯ NXP Semiconductors

reserves the right to make changes to informa t ion

published in this doc ument, including without limitation

specifications and product descriptions, at any time and

without notice. This document supersedes and replaces all

information supplied prior to the publication hereof.

Suitability for use ⎯ NXP Semiconduct ors pr oduc ts are

not designed, au thorized or warran ted to be suitable for

use in life support, life-critical or safety-critical systems or

equipment, nor in applications where failure or malfunction

of an NXP Semiconductors product can reason ably be

expected to result in pe rs onal injury, death or severe

property or environmental damage. NXP Semiconductors

accepts no liability for inclusion and/or use of NXP

Semiconductor s pr oducts in such equipme nt or

application s and therefore suc h inclusion and/o r us e i s at

the customer’s own risk.

Applications ⎯ Applications that are described herein for

any of these products are for illustrative purposes only.

NXP Semiconductors makes no representation or

warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of

their applications and products using NXP

Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or

customer product design. It is customer’s sole

responsibility to determine whether the NXP

Semiconductors pro du ct is su itable and fit for the

customer’s applications and products planned, as well as

for the planned a pplication and use of custom er’s third

party customer(s). Customers should provide appropriate

design and opera t ing saf eg ua rd s to minimize the risks

associated with their applications and products.

NXP Semiconduc tors does n ot a ccept any liabil ity rela ted

to any default, damage, costs or problem which is based

on any weakne ss or default in t he customer’s applic ations

or products, or the application or use by customer’s third

party customer( s) . C us to m er is responsible for doin g all

necessary testing for the customer’s applications and

products using NXP Semiconductors products in order to

avoid a default of the applic ations and the products or of

the application or use by customer’s third p arty

customer(s). NXP does not accept any liability in this

respect.

2000 Jul 31 21

NXP Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

Limiting values ⎯ Stress above one or more limiting

values (as defined in the Absolute Maximum Ratings

System of IEC 60134) will cause permanent damage to

the device. Limiting values are stress ratin gs only and

(proper) operation of the device at these or any other

conditions abo ve those given in the Recommended

operating conditions section (if present) or the

Characteristics sections of this document is not warranted.

Constant or repeated exposure to limiting values will

permanently and irreversibly affect the qua l ity and

reliability of the device.

Terms and conditions of commercial sale ⎯ NXP

Semiconductors products are sold subject to the general

terms and conditio ns of commercial sale, as published at

http://www.nxp.com/profile/terms, unless other wis e

agreed in a valid written ind i vidual agreement. I n cas e an

individual agreeme nt is co nc luded only the terms and

conditions of the resp ective agreement shall apply. NXP

Semiconductors hereby expressly objects to apply i ng the

customer’s general terms and conditions with regard to the

purchase of NXP Semicon ductors produc ts by customer.

No offer to sell or license ⎯ Nothing in this document

may be interpreted or construed as an offer to sell products

that is open for acceptance or the grant, conveyan ce or

implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control ⎯ This document as well as the item(s)

described he re in may be subject to export con t ro l

regulations. Export might require a prior authorization from

national auth or itie s.

Quick refer ence data ⎯ The Quick reference data is an

extract of th e product data given in the Limiting values an d

Characteristics sections of this document, an d as such is

not complete, exhaus tive or legally binding.

Non-automotive qualified products ⎯ Unless this data

sheet expressly states that this specific NXP

Semiconductors product is au tomotive qualified, the

product is not suitable for automotive use. It is neither

qualified nor te sted in accordanc e with automot ive testing

or application requirements. NXP Semiconductors accepts

no liability for inclusion and/or use of non-automotive

qualified prod ucts in automotive equip ment or

applications.

In the event that customer uses the product for design-in

and use in automotive applications to automotive

specifications and standards, customer (a) shall use the

product without NXP Semiconductors’ warranty of the

product for such au t omo tive applications, us e and

specifications, and (b) whenever customer uses the

product for automotive applications be yond NXP

Semiconductors’ specifications such use shall be solely at

customer’s own ris k, and (c) customer fully inde m nif i es

NXP Semiconductors for any liability, damages or failed

product clai ms r esult ing fr om custo mer desi gn an d us e o f

the product for automotive ap plic ations beyond NXP

Semiconductors ’ st andard warranty and NXP

Semiconductors’ product specifications.

NXP Semiconductors

provides High Performance Mixed Signal and Standard Product

solutions that leverage its leading RF, Analog, Power Management,

Interface, Security and Digital Processing expertise

Contact information

For additional information p lease visit: http://www.nxp.com

For sales offices addresses send e- mail to: salesaddresses@nxp.com

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information pr e sent ed in this document d oes not form part of an y q uot ation or contract, is believe d to be accurate and re li a ble and may be change d

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Customer notification

This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal

definitions and disclaimer s. No changes were made to the tech nical content, except for package outline

drawings which were updated to the latest version.

Printed in The Netherlands 753503/25/02/pp22 Date of release: 2000 Jul 31 Document order number: 9397 750 07238