KSZ8794CNX Integrated 4-Port 10/100 Managed Ethernet Switch with Gigabit RGMII/MII/RMII Interface Revision 1.0 General Description The KSZ8794CNX is a highly integrated, Layer 2 managed, four-port switch with numerous features designed to reduce system cost. It is intended for costsensitive applications requiring three 10/100Mbps copper ports and one 10/100/1000Mbps Gigabit uplink port. The KSZ8794CNX incorporates a small package outline, lowest power consumption with internal biasing, and onchip termination. Its extensive features set includes enhanced power management, programmable rate limiting and priority ratio, tagged and port-based VLAN, port-based security and ACL rule-based packet filtering technology, QoS priority with four queues, management interfaces, enhanced MIB counters, high-performance memory bandwidth, and a shared memory-based switch fabric with non-blocking support. The KSZ8794CNX provides support for multiple CPU data interfaces to effectively address both current and emerging fast Ethernet and Gigabit Ethernet applications where the GMAC interface can be configured to any of RGMII, MII and RMII modes. The KSZ8794CNX is built on Micrel's latest industryleading Ethernet analog and digital technology, with features designed to offload host processing and streamline your overall design: * Three integrated 10/100Base-T/TX MAC/PHYs. * One integrated 10/100/1000Base-T/TX GMAC with selectable RGMII, MII or RMII interfaces. * Small 64-pin QFN package. A robust assortment of power management features including Energy Efficient Ethernet (EEE), PME and WoL have been designed in to satisfy energy efficient environments. All registers in the MAC and PHY units can be managed through the SPI interface. MIIM PHY registers can be accessed through the MDC/MDIO interface. Datasheets and support documentation are available on Micrel's web site at: www.micrel.com. Functional Diagram KSZ8794CNX Functional Block Diagram (R) LinkMD is a registered trademark of Micrel, Inc. Auto MDI/MDI-XTM is a trademark of Hewlett-Pacard Company, L.P Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com July 24, 2014 Revision 1.0 Micrel, Inc. KSZ8794CNX Highlights and Features Advanced Switch Capabilities * Non-blocking store-and-forward switch fabric assures fast packet delivery by utilizing 1024 entry forwarding table * 64kb frame buffer RAM * IEEE 802.1q VLAN support for up to 128 active VLAN groups (full-range 4096 of VLAN IDs) * IEEE 802.1p/Q tag insertion or removal on a per port basis (egress) * VLAN ID tag/un-tag options on per port basis * Fully compliant with IEEE 802.3/802.3u standards * IEEE 802.3x full-duplex with force mode option and halfduplex back-pressure collision flow control * IEEE 802.1w rapid spanning tree protocol support * IGMP v1/v2/v3 snooping for multicast packet filtering * QoS/CoS packets prioritization support: 802.1p, DiffServ-based and re-mapping of 802.1p priority field per port basis on four priority levels * IPv4/IPv6 QoS support * IPV6 multicast listener discovery (MLD) snooping * Programmable rate limiting at the ingress and egress ports on a per port basis * Jitter-free per packet based rate limiting support * Tail tag mode (1 byte added before FCS) support on Port 4 to inform the processor which ingress port receives the packet * Broadcast storm protection with percentage control (global and per port basis) * 1K entry forwarding table with 64K Byte frame buffer * 4 priority queues with dynamic packet mapping for IEEE 802.1P, IPv4 TOS (DIFFSERV), IPv6 Traffic Class, etc. * Supports Wake on LAN (WoL) using AMD's Magic Packet * VLAN and Address Filtering * Support 802.1x port-based security, authentication and MAC-based authentication via access control lists (ACL) * Provide port-based and rule-based ACLs to support layer 2 MAC SA/DA address, layer 3 IP address and IP mask, layer 4 TCP/UDP port number, IP protocol, TCP flag and their combination for the port security filtering * Ingress and egress rate limit based on bit per second (bps) and packet-based rate limiting (pps) Management Capabilities * The KSZ8794CNX includes all the functions of a 10/100Base-T/TX switch system which combines a switch engine, frame buffer management, address lookup table, queue management, MIB counters, media access controllers (MAC) and PHY transceivers * Non-blocking store-and-forward switch fabric assures fast packet delivery by utilizing 1024 entries forwarding table * Port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port * MIB counters for fully compliant statistics gathering 36 counters per port * Support hardware for port-based flush and freeze command in MIB counter. * Multiple loopback of remote, PHY and MAC modes support for the diagnostics * Rapid Spanning Tree Support (RSTP) for topology management and ring/linear recovery Robust PHY Ports * Four Integrated IEEE 802.3 / 802.3u compliant Ethernet transceivers supporting 10Base-T and 100Base-TX * IEEE 802.1az EEE supported * On-Chip termination resistors and internal biasing for differential pairs to reduce power * HP Auto MDI/MDI-XTM crossover support eliminating the need to differentiate between straight or crossover cables in applications MAC and GMAC Ports * Four internal media access control (MAC1 to MAC3) units and one internal gigabit media access control (GMAC4) unit * RGMII, MII or RMII interfaces support for the port 4 GMAC4 with uplink * 2KByte Jumbo packet support * Tail tagging mode (one byte added before FCS) support on port 4 to inform the processor which ingress port receives the packet and its priority * Supports Reduced Media Independent Interface (RMII) with 50 MHz reference clock output * Supports Media Independent Interface (MII) in either PHY mode or MAC mode on port 4 * Micrel LinkMD(R) cable diagnostic capabilities for determining cable opens, shorts, and length July 24, 2014 2 Revision 1.0 Micrel, Inc. KSZ8794CNX Configuration Registers Access Packaging and Environmental * High speed SPI (4-wire, up to 50MHz) interface to access all internal registers * MII Management (MIIM, MDC/MDIO 2-wire) Interface to access all PHY registers per Clause 22.2.4.5 of the IEEE 802.3 specification * I/O pin strapping facility to set certain register bits from I/O pins during reset time * Control registers configurable on-the-fly * Commercial Temperature Range: 0C to +70C * Industrial Temperature Range: -40C to +85C * Small package available in an 64-pin lead free (ROHS) QFN form factor * 0.065m CMOS technology for lower power consumption Target Applications * Industrial Ethernet applications that employ IEEE 802.3 compliant MACs. (Ethernet/IP, Profinet, MODBUS TCP, etc) * VoIP Phone * Set-top/Game Box * Automotive * Industrial Control * IPTV POF * SOHO Residential Gateway with full wire speed of four LAN Ports * Broadband Gateway/Firewall/VPN * Integrated DSL/Cable Modem * Wireless LAN access point + gateway * Standalone 10/100 switch * Networked Measurement and Control Systems Power and Power Management * Full-chip software power down (All registers value are not saved and strap-in value will re-strap after release the power down.) * Per port software power down * Energy Detect Power Down (EDPD), which disables the PHY transceiver when cables are removed * Supports IEEE P802.3az energy-efficient Ethernet (EEE) to reduce power consumption in transceivers in LPI state even though cables are not removed * Dynamic clock tree control to reduce clocking in areas not in use * Very low power consumption (less than 0.5W) without extra power consumption on transformers * Voltages: Using external LDO power supplies - Analog VDDAT 3.3V - VDDIO support 3.3V, 2.5V and 1.8V - Low 1.2V voltage for analog and digital core power * Wake on LAN support with configurable packet control Additional Features * Single 25MHz +50ppm reference clock requirement * Comprehensive programmable two LED indicator support for link, activity, full/half duplex and 10/100 speed July 24, 2014 3 Revision 1.0 Micrel, Inc. KSZ8794CNX Ordering Information Part Number Temperature Range Package Lead Finish/Grade KSZ8794CNXCC 0C to 70C 64-Pin QFN Pb-Free/Commercial KSZ8794CNXIC -40C to +85C 64-Pin QFN Pb-Free/Industrial KSZ8794CNX-EVAL Evaluation Board Revision History Revision Date Description 1.0 06/03/14 Initial document created 1.0 07/18/14 MarCom formatting/reflow of initial submission datasheet. D.Tanabe July 24, 2014 4 Revision 1.0 Micrel, Inc. KSZ8794CNX Contents General Description ................................................................................................................................................................ 1 Functional Diagram ................................................................................................................................................................. 1 Highlights and Features .......................................................................................................................................................... 2 Management Capabilities ................................................................................................................................................... 2 Robust PHY Ports ............................................................................................................................................................... 2 MAC and GMAC Ports........................................................................................................................................................ 2 Advanced Switch Capabilities............................................................................................................................................. 2 Configuration Registers Access ......................................................................................................................................... 3 Power and Power Management ......................................................................................................................................... 3 Additional Features ............................................................................................................................................................. 3 Packaging and Environmental ............................................................................................................................................ 3 Target Applications ............................................................................................................................................................. 3 Ordering Information ............................................................................................................................................................... 4 Revision History ...................................................................................................................................................................... 4 Contents .................................................................................................................................................................................. 5 List of Figures ........................................................................................................................................................................ 13 List of Tables ......................................................................................................................................................................... 14 Pin Configuration ................................................................................................................................................................... 15 Pin Description ...................................................................................................................................................................... 16 Strap-in Options .................................................................................................................................................................... 21 Introduction............................................................................................................................................................................ 22 Functional Overview: Physical Layer (PHY) ......................................................................................................................... 22 100BASE-TX Transmit ..................................................................................................................................................... 22 100BASE-TX Receive ...................................................................................................................................................... 22 PLL Clock Synthesizer...................................................................................................................................................... 22 Scrambler/Descrambler (100BASE-TX only) ................................................................................................................... 22 Straight Cable ............................................................................................................................................................... 24 Crossover Cable ........................................................................................................................................................... 24 Auto-Negotiation ................................................................................................................................................................... 25 LinkMD(R) Cable Diagnostics .................................................................................................................................................. 27 Access .......................................................................................................................................................................... 27 Usage ........................................................................................................................................................................... 27 A LinkMD example ....................................................................................................................................................... 28 On-chip Termination and Internal Biasing ........................................................................................................................ 28 Functional Overview: Media Access Controller (MAC) ......................................................................................................... 29 Media Access Controller (MAC) Operation ...................................................................................................................... 29 Inter-Packet Gap (IPG) ................................................................................................................................................. 29 Back-off Algorithm ........................................................................................................................................................ 29 Late Collision ................................................................................................................................................................ 29 Illegal Frames ............................................................................................................................................................... 29 Flow Control.................................................................................................................................................................. 29 Half-Duplex Back Pressure .......................................................................................................................................... 29 Broadcast Storm Protection.......................................................................................................................................... 30 Functional Overview: Switch Core ........................................................................................................................................ 31 Address Look-Up .............................................................................................................................................................. 31 Learning ............................................................................................................................................................................ 31 Migration ........................................................................................................................................................................... 31 July 24, 2014 5 Revision 1.0 Micrel, Inc. KSZ8794CNX Aging ................................................................................................................................................................................. 31 Forwarding ........................................................................................................................................................................ 31 Switching Engine .............................................................................................................................................................. 32 Functional Overview: Power ................................................................................................................................................. 33 Functional Overview: Power Management ........................................................................................................................... 33 Normal Operation Mode ................................................................................................................................................... 33 Energy Detect Mode ......................................................................................................................................................... 33 Soft Power-Down Mode .................................................................................................................................................... 34 Port-based Power-Down Mode ........................................................................................................................................ 34 Energy Efficient Ethernet (EEE) ....................................................................................................................................... 34 LPI Signaling................................................................................................................................................................. 35 LPI Assertion ................................................................................................................................................................ 35 LPI Detection ................................................................................................................................................................ 36 PHY LPI Transmit Operation ........................................................................................................................................ 36 PHY LPI Receive Operation ......................................................................................................................................... 37 Negotiation with EEE Capability ................................................................................................................................... 37 Wake on LAN (WoL) ............................................................................................................................................................. 38 Direction of Energy ....................................................................................................................................................... 38 Direction of Link-up ....................................................................................................................................................... 38 Magic PacketTM ............................................................................................................................................................ 38 Interrupt (INT_N/PME_N)...................................................................................................................................................... 39 Functional Overview: Interfaces ............................................................................................................................................ 40 Configuration Interface ..................................................................................................................................................... 40 SPI Slave Serial Bus Configuration .............................................................................................................................. 40 MII Management Interface (MIIM) ................................................................................................................................ 43 Standard Media Independent Interface [MII] ................................................................................................................ 44 Reduced Media Independent Interface [RMII].............................................................................................................. 44 Reduced Gigabit Media Independent Interface [RGMII] .............................................................................................. 44 Port 4 GMAC4 SW4-RGMII Interface ........................................................................................................................... 45 Functional Overview: Advanced Functionality ...................................................................................................................... 48 QoS Priority Support ......................................................................................................................................................... 48 Port-based Priority ........................................................................................................................................................ 48 802.1p-based Priority ................................................................................................................................................... 48 DiffServ-Based Priority ................................................................................................................................................. 49 Spanning Tree Support..................................................................................................................................................... 50 Rapid Spanning Tree Support .......................................................................................................................................... 51 Tail Tagging Mode ............................................................................................................................................................ 52 IGMP Support ................................................................................................................................................................... 53 IGMP Snooping ............................................................................................................................................................ 53 IGMP Send Back to the Subscribed Port ..................................................................................................................... 53 IPv6 MLD Snooping .......................................................................................................................................................... 53 Port Mirroring Support ...................................................................................................................................................... 53 "Receive Only" mirror on a Port .................................................................................................................................... 53 "Transmit Only" mirror on a Port ................................................................................................................................... 53 "Receive and Transmit" mirror on two Ports................................................................................................................. 53 VLAN Support ................................................................................................................................................................... 54 Ingress Rate Limit ......................................................................................................................................................... 56 July 24, 2014 6 Revision 1.0 Micrel, Inc. KSZ8794CNX Egress Rate Limit ......................................................................................................................................................... 56 Transmit Queue Ratio Programming ............................................................................................................................ 56 802.1X Port-Based Security ............................................................................................................................................. 57 Authentication Register and Programming Model ........................................................................................................ 58 ACL Filtering ..................................................................................................................................................................... 58 Access Control Lists ..................................................................................................................................................... 58 Matching Field .............................................................................................................................................................. 60 Action Field ................................................................................................................................................................... 61 Processing Field ........................................................................................................................................................... 61 DOS Attack Prevention via ACL ................................................................................................................................... 62 Device Registers Mapping .................................................................................................................................................... 63 Direct Register Description ................................................................................................................................................... 64 Global Registers .................................................................................................................................................................... 66 Register 0 (0x00): Chip ID0 .......................................................................................................................................... 66 Register 1 (0x01): Chip ID1 / Start Switch.................................................................................................................... 66 Register 2 (0x02): Global Control 0 .............................................................................................................................. 66 Register 3 (0x03): Global Control 1 .............................................................................................................................. 67 Register 4 (0x04): Global Control 2 .............................................................................................................................. 68 Register 6 (0x06): Global Control 4 .............................................................................................................................. 69 Register 7 (0x07): Global Control 5 .............................................................................................................................. 69 Register 8 (0x08): Global Control 6 MIB Control .......................................................................................................... 70 Register 9 (0x09): Global Control 7 .............................................................................................................................. 70 Register 10 (0x0A): Global Control 8 ........................................................................................................................... 70 Register 11 (0x0B): Global Control 9 ........................................................................................................................... 71 Register 12 (0x0C): Global Control 10 ......................................................................................................................... 72 Register 13 (0x0D): Global Control 11 ......................................................................................................................... 72 Register 14 (0x0E): Power Down Management Control 1 ........................................................................................... 72 Register 15 (0x0F): Power Down Management Control 2 ........................................................................................... 72 Port Registers........................................................................................................................................................................ 73 Register 16 (0x10): Port 1 Control 0 ............................................................................................................................. 73 Register 32 (0x20): Port 2 Control 0 ............................................................................................................................. 73 Register 48 (0x30): Port 3 Control 0 ............................................................................................................................. 73 Register 64 (0x40): Reserved....................................................................................................................................... 73 Register 80 (0x50): Port 4 Control 0 ............................................................................................................................. 73 Register 17 (0x11): Port 1 Control 1 ............................................................................................................................. 74 Register 33 (0x21): Port 2 Control 1 ............................................................................................................................. 74 Register 49 (0x31): Port 3 Control 1 ............................................................................................................................. 74 Register 65 (0x41): Reserved....................................................................................................................................... 74 Register 81 (0x51): Port 4 Control 1 ............................................................................................................................. 74 Register 18 (0x12): Port 1 Control 2 ............................................................................................................................. 75 Register 34 (0x22): Port 2 Control 2 ............................................................................................................................. 75 Register 50 (0x32): Port 3 Control 2 ............................................................................................................................. 75 Register 66 (0x42): Reserved....................................................................................................................................... 75 Register 82 (0x52): Port 4 Control 2 ............................................................................................................................. 75 Register 19 (0x13): Port 1 Control 3 ............................................................................................................................. 75 Register 35 (0x23): Port 2 Control 3 ............................................................................................................................. 75 July 24, 2014 7 Revision 1.0 Micrel, Inc. KSZ8794CNX Register 51 (0x33): Port 3 Control 3 ............................................................................................................................. 75 Register 67 (0x43): Reserved....................................................................................................................................... 75 Register 83 (0x53): Port 4 Control 3 ............................................................................................................................. 75 Register 20 (0x14): Port 1 Control 4 ............................................................................................................................. 76 Register 36 (0x24): Port 2 Control 4 ............................................................................................................................. 76 Register 52 (0x34): Port 3 Control 4 ............................................................................................................................. 76 Register 68 (0x44): Reserved....................................................................................................................................... 76 Register 84 (0x54): Port 4 Control 4 ............................................................................................................................. 76 Register 21 (0x15): Port 1 Control 5 ............................................................................................................................. 76 Register 37 (0x25): Port 2 Control 5 ............................................................................................................................. 76 Register 53 (0x35): Port 3 Control 5 ............................................................................................................................. 76 Register 69 (0x45): Reserved....................................................................................................................................... 76 Register 85 (0x55): Port 4 Control 5 ............................................................................................................................. 76 Register 22 (0x16): Reserved....................................................................................................................................... 76 Register 38 (0x26): Reserved....................................................................................................................................... 76 Register 54 (0x36): Reserved....................................................................................................................................... 76 Register 70 (0x46): Reserved....................................................................................................................................... 76 Register 86 (0x56): Port 4 Interface Control 6.............................................................................................................. 77 Register 23 (0x17): Port 1 Control 7 ............................................................................................................................. 78 Register 39 (0x27): Port 2 Control 7 ............................................................................................................................. 78 Register 55 (0x37): Port 3 Control 7 ............................................................................................................................. 78 Register 71 (0x47): Reserved....................................................................................................................................... 78 Register 87 (0x57): Reserved....................................................................................................................................... 78 Register 24 (0x18): Port 1 Status 0 .............................................................................................................................. 79 Register 40 (0x28): Port 2 Status 0 .............................................................................................................................. 79 Register 56 (0x38): Port 3 Status 0 .............................................................................................................................. 79 Register 72 (0x48): Reserved....................................................................................................................................... 79 Register 87 (0x57): Reserved....................................................................................................................................... 79 Register 25 (0x19): Port 1 Status 1 .............................................................................................................................. 80 Register 41 (0x29): Port 2 Status 1 .............................................................................................................................. 80 Register 57 (0x39): Port 3 Status 1 .............................................................................................................................. 80 Register 73 (0x49): Reserved....................................................................................................................................... 80 Register 89 (0x59): Reserved....................................................................................................................................... 80 Register 26 (0x1A): Port 1 PHY Control 8 .................................................................................................................... 81 Register 42 (0x2A): Port 2 PHY Control 8 .................................................................................................................... 81 Register 58 (0x3A): Port 3 PHY Control 8 .................................................................................................................... 81 Register 74 (0x4A): Reserved ...................................................................................................................................... 81 Register 90 (0x5A): Reserved ...................................................................................................................................... 81 Register 27 (0x1B): Port 1 LinkMD result ..................................................................................................................... 82 Register 43 (0x2B): Port 2 LinkMD result ..................................................................................................................... 82 Register 59 (0x3B): Port 3 LinkMD result ..................................................................................................................... 82 Register 75 (0x4B): Reserved ...................................................................................................................................... 82 Register 91 (0x5B): Reserved ...................................................................................................................................... 82 Register 28 (0x1C): Port 1 Control 9 ............................................................................................................................ 82 Register 44 (0x2C): Port 2 Control 9 ............................................................................................................................ 82 July 24, 2014 8 Revision 1.0 Micrel, Inc. KSZ8794CNX Register 60 (0x3C): Port 3 Control 9 ............................................................................................................................ 82 Register 76 (0x4C): Reserved ...................................................................................................................................... 82 Register 92 (0x5C): Reserved ...................................................................................................................................... 82 Register 29 (0x1D): Port 1 Control 10 .......................................................................................................................... 83 Register 45 (0x2D): Port 2 Control 10 .......................................................................................................................... 83 Register 61 (0x3D): Port 3 Control 10 .......................................................................................................................... 83 Register 77 (0x4D): Reserved ...................................................................................................................................... 83 Register 93 (0x5D): Reserved ...................................................................................................................................... 83 Register 30 (0x1E): Port 1 Status 2 .............................................................................................................................. 84 Register 46 (0x2E): Port 2 Status 2 .............................................................................................................................. 84 Register 62 (0x3E): Port 3 Status 2 .............................................................................................................................. 84 Register 78 (0x4E): Reserved ...................................................................................................................................... 84 Register 94 (0x5E): Reserved ...................................................................................................................................... 84 Register 31 (0x1F): Port 1 Control 11 and Status 3 ..................................................................................................... 84 Register 47 (0x2F): Port 2 Control 11 and Status 3 ..................................................................................................... 84 Register 63 (0x3F): Port 3 Control 11 and Status 3 ..................................................................................................... 84 Register 79 (0x4F): Reserved ...................................................................................................................................... 84 Register 95 (0x5F): Reserved ...................................................................................................................................... 84 Advanced Control Registers ................................................................................................................................................. 86 Register 104 (0x68): MAC Address Register 0 ............................................................................................................ 86 Register 105 (0x69): MAC Address Register 1 ............................................................................................................ 86 Register 106 (0x6A): MAC Address Register 2 ............................................................................................................ 86 Register 107 (0x6B): MAC Address Register 3 ............................................................................................................ 86 Register 108 (0x6C): MAC Address Register 4............................................................................................................ 86 Register 110 (0x6E): Indirect Access Control 0 ........................................................................................................... 87 Register 111 (0x6F): Indirect Access Control 1............................................................................................................ 87 Register 112 (0x70): Indirect Data Register 8 .............................................................................................................. 88 Register 113 (0x71): Indirect Data Register 7 .............................................................................................................. 88 Register 114 (0x72): Indirect Data Register 6 .............................................................................................................. 88 Register 115 (0x73): Indirect Data Register 5 .............................................................................................................. 88 Register 116 (0x74): Indirect Data Register 4 .............................................................................................................. 88 Register 117 (0x75): Indirect Data Register 3 .............................................................................................................. 88 Register 118 (0x76): Indirect Data Register 2 .............................................................................................................. 88 Register 119 (0x77): Indirect Data Register 1 .............................................................................................................. 88 Register 120 (0x78): Indirect Data Register 0 .............................................................................................................. 88 Register 160 (0XA0): Indirect Byte Register (It is for PME, EEE and ACL Registers)................................................. 88 Register 124 (0x7C): Interrupt Status Register ............................................................................................................ 89 Register 125 (0x7D): Interrupt Mask Register .............................................................................................................. 89 Register 126 (0x7E): ACL Interrupt Status Register .................................................................................................... 89 Register 127 (0x7F): ACL Interrupt Control Register ................................................................................................... 89 Register 128 (0x80): Global Control 12 ........................................................................................................................ 90 Register 129 (0x81): Global Control 13 ........................................................................................................................ 90 Register 130 (0x82): Global Control 14 ........................................................................................................................ 90 Register 131 (0x83): Global Control 15 ........................................................................................................................ 91 Register 132 (0x84): Global Control 16 ........................................................................................................................ 91 Register 134 (0x86): Global Control 18 ........................................................................................................................ 92 July 24, 2014 9 Revision 1.0 Micrel, Inc. KSZ8794CNX Register 135 (0x87): Global Control 19 ........................................................................................................................ 92 Register 144 (0x90): TOS Priority Control Register 0 .................................................................................................. 93 Register 145 (0x91): TOS Priority Control Register 1 .................................................................................................. 93 Register 146 (0x92): TOS Priority Control Register 2 .................................................................................................. 93 Register 147 (0x93): TOS Priority Control Register 3 .................................................................................................. 93 Register 148 (0x94): TOS Priority Control Register 4 .................................................................................................. 93 Register 149 (0x95): TOS Priority Control Register 5 .................................................................................................. 94 Register 150 (0x96): TOS Priority Control Register 6 .................................................................................................. 94 Register 151 (0x97): TOS Priority Control Register 7 .................................................................................................. 94 Register 152 (0x98): TOS Priority Control Register 8 .................................................................................................. 94 Register 153 (0x99): TOS Priority Control Register 9 .................................................................................................. 94 Register 154 (0x9A): TOS Priority Control Register 10 ................................................................................................ 94 Register 155 (0x9B): TOS Priority Control Register 11 ................................................................................................ 94 Register 156 (0x9C): TOS Priority Control Register 12 ............................................................................................... 95 Register 157 (0x9D): TOS Priority Control Register 13 ............................................................................................... 95 Register 158 (0x9E): TOS Priority Control Register 14 ................................................................................................ 95 Register 159 (0x9F): TOS Priority Control Register 15 ................................................................................................ 95 Register 163 (0XA3): Global Control 20 ....................................................................................................................... 96 Register 164 (0XA4): Global Control 21 ....................................................................................................................... 96 Register 176 (0xB0): Port 1 Control 12 ........................................................................................................................ 97 Register 192 (0xC0): Port 2 Control 12 ........................................................................................................................ 97 Register 208 (0xD0): Port 3 Control 12 ........................................................................................................................ 97 Register 224 (0xE0): Reserved .................................................................................................................................... 97 Register 240 (0xF0): Port 4 Control 12 ........................................................................................................................ 97 Register 177 (0xB1): Port 1 Control 13 ........................................................................................................................ 98 Register 193 (0xC1): Port 2 Control 13 ........................................................................................................................ 98 Register 209 (0xD1): Port 3 Control 13 ........................................................................................................................ 98 Register 225 (0xE1): Reserved .................................................................................................................................... 98 Register 241 (0xF1): Port 4 Control 13 ........................................................................................................................ 98 Register 178 (0xB2): Port 1 Control 14 ........................................................................................................................ 98 Register 194 (0xC2): Port 2 Control 14 ........................................................................................................................ 98 Register 210 (0xD2): Port 3 Control 14 ........................................................................................................................ 98 Register 226 (0xE2): Reserved .................................................................................................................................... 98 Register 242 (0xF2): Port 4 Control 14 ........................................................................................................................ 98 Register 179 (0xB3): Port 1 Control 15 ........................................................................................................................ 99 Register 195 (0xC3): Port 2 Control 15 ........................................................................................................................ 99 Register 211 (0xD3): Port 3 Control 15 ........................................................................................................................ 99 Register 227 (0xE3): Reserved .................................................................................................................................... 99 Register 243 (0xF3): Port 4 Control 15 ........................................................................................................................ 99 Register 180 (0xB4): Port 1 Control 16 ........................................................................................................................ 99 Register 196 (0xC4): Port 2 Control 16 ........................................................................................................................ 99 Register 212 (0xD4): Port 3 Control 16 ........................................................................................................................ 99 Register 228 (0xE4): Reserved .................................................................................................................................... 99 Register 244 (0xF4): Port 4 Control 16 ........................................................................................................................ 99 Register 181 (0xB5): Port 1 Control 17 ........................................................................................................................ 99 July 24, 2014 10 Revision 1.0 Micrel, Inc. KSZ8794CNX Register 197 (0xC5): Port 2 Control 17 ........................................................................................................................ 99 Register 213 (0xD5): Port 3 Control 17 ........................................................................................................................ 99 Register 229 (0xE5): Reserved .................................................................................................................................... 99 Register 245 (0xF5): Port 4 Control 17 ........................................................................................................................ 99 Register 182 (0xB6): Port 1 Rate Limit Control .......................................................................................................... 100 Register 198 (0xC6): Port 2 Rate Limit Control .......................................................................................................... 100 Register 214 (0xD6): Port 3 Rate Limit Control .......................................................................................................... 100 Register 230 (0xE6): Reserved .................................................................................................................................. 100 Register 246 (0xF6): Port 4 Rate Limit Control .......................................................................................................... 100 Register 183 (0xB7): Port 1 Priority 0 Ingress Limit Control 1(4)................................................................................. 100 Register 199 (0xC7): Port 2 Priority 0 Ingress Limit Control 1 ................................................................................... 100 Register 215 (0xD7): Port 3 Priority 0 Ingress Limit Control 1 ................................................................................... 100 Register 231 (0xE7): Reserved .................................................................................................................................. 100 Register 247 (0xF7): Port 4 Priority 0 Ingress Limit Control 1.................................................................................... 100 Register 184 (0xB8): Port 1 Priority 1 Ingress Limit Control 2(4)................................................................................. 101 Register 200 (0xC8): Port 2 Priority 1 Ingress Limit Control 2 ................................................................................... 101 Register 216 (0xD8): Port 3 Priority 1 Ingress Limit Control 2 ................................................................................... 101 Register 232 (0xE8): Reserved .................................................................................................................................. 101 Register 248 (0xF8): Port 4 Priority 1 Ingress Limit Control 2.................................................................................... 101 Register 185 (0xB9): Port 1 Priority 2 Ingress Limit Control 3(4)................................................................................. 101 Register 201 (0xC9): Port 2 Priority 2 Ingress Limit Control 3 ................................................................................... 101 Register 217 (0xD9): Port 3 Priority 2 Ingress Limit Control 3 ................................................................................... 101 Register 233 (0xE9): Reserved .................................................................................................................................. 101 Register 249 (0xF9): Port 4 Priority 2 Ingress Limit Control 3.................................................................................... 101 Register 186 (0xBA): Port 1 Priority 3 Ingress Limit Control 4(4) ................................................................................ 102 Register 202 (0xCA): Port 2 Priority 3 Ingress Limit Control 4 ................................................................................... 102 Register 218 (0xDA): Port 3 Priority 3 Ingress Limit Control 4 ................................................................................... 102 Register 234 (0xEA): Reserved .................................................................................................................................. 102 Register 250 (0xFA): Port 4 Priority 3 Ingress Limit Control 4 ................................................................................... 102 Register 187 (0xBB): Port 1 Queue 0 Egress Limit Control 1(5) ................................................................................. 103 Register 203 (0xCB): Port 2 Queue 0 Egress Limit Control 1 .................................................................................... 103 Register 219 (0xDB): Port 3 Queue 0 Egress Limit Control 1 .................................................................................... 103 Register 235 (0xEB): Reserved .................................................................................................................................. 103 Register 251 (0xFB): Port 4 Queue 0 Egress Limit Control 1 .................................................................................... 103 Register 188 (0xBC) : Port 1 Queue 1 Egress Limit Control 2(5) ................................................................................ 103 Register 204 (0xCC) : Port 2 Queue 1 Egress Limit Control 2................................................................................... 103 Register 220 (0xDC) : Port 3 Queue 1 Egress Limit Control 2................................................................................... 103 Register 236 (0xEC) : Reserved................................................................................................................................. 103 Register 252 (0xFC) : Port 4 Queue 1 Egress Limit Control 2 ................................................................................... 103 Register 189 (0xBD): Port 1 Queue 2 Egress Limit Control 3(5) ................................................................................. 103 Register 205 (0xCD): Port 2 Queue 2 Egress Limit Control 3.................................................................................... 103 Register 221 (0xDD): Port 3 Queue 2 Egress Limit Control 3.................................................................................... 103 Register 237 (0xED): Reserved.................................................................................................................................. 103 Register 253 (0xFD): Port 4 Queue 2 Egress Limit Control 3 .................................................................................... 103 Register 190 (0xBE) : Port 1 Queue 3 Egress Limit Control 4(5) ................................................................................ 103 July 24, 2014 11 Revision 1.0 Micrel, Inc. KSZ8794CNX Register 206 (0xCE) : Port 2 Queue 3 Egress Limit Control 4 ................................................................................... 103 Register 222 (0xDE) : Port 3 Queue 3 Egress Limit Control 4 ................................................................................... 103 Register 238 (0xEE): Reserved .................................................................................................................................. 103 Register 254 (0xFE): Port 4 Queue 3 Egress Limit Control 4 .................................................................................... 103 Register 191(0xBF): Testing Register ........................................................................................................................ 104 Register 207(0xCF): Reserved Control Register....................................................................................................... 104 Register 223(0xDF): Test Register 2 .......................................................................................................................... 104 Register 239(0xEF): Test Register 3 .......................................................................................................................... 104 Register 255(0xFF): Test Register 4 .......................................................................................................................... 104 Indirect Register Description ............................................................................................................................................... 105 Static MAC Address Table .................................................................................................................................................. 106 VLAN Table ......................................................................................................................................................................... 108 Dynamic MAC Address Table ............................................................................................................................................. 110 PME Indirect Registers ....................................................................................................................................................... 112 Programming Examples: ..................................................................................................................................................... 113 Read Operation .......................................................................................................................................................... 113 Write Operation .......................................................................................................................................................... 113 ACL Rule Table and ACL Indirect Registers....................................................................................................................... 114 ACL Register and Programming Model...................................................................................................................... 114 ACL Indirect Registers................................................................................................................................................ 115 EEE Indirect Registers ........................................................................................................................................................ 124 EEE Global Registers ..................................................................................................................................................... 124 Management Information Base (MIB) Counters ................................................................................................................. 133 MIIM Registers .................................................................................................................................................................... 137 Absolute Maximum Ratings(6) ............................................................................................................................................. 141 Operating Ratings(7) ............................................................................................................................................................ 141 Electrical Characteristics(9,10) ............................................................................................................................................... 141 Timing Diagrams ................................................................................................................................................................. 143 RGMII Timing .................................................................................................................................................................. 143 MII Timing ....................................................................................................................................................................... 144 RMII Timing..................................................................................................................................................................... 146 SPI Timing ...................................................................................................................................................................... 147 Auto-Negotiation Timing ................................................................................................................................................. 148 MDC/MDIO Timing ......................................................................................................................................................... 149 Power-down/Power-up and Reset Timing ...................................................................................................................... 150 Reset Circuit Diagram ......................................................................................................................................................... 151 Selection of Reference Crystal............................................................................................................................................ 152 MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA ..................................................................... 154 Template Revision History .................................................................................................................................................. 155 July 24, 2014 12 Revision 1.0 Micrel, Inc. KSZ8794CNX List of Figures Figure 1. Typical Straight Cable Connection ....................................................................................................................... 24 Figure 2. Typical Crossover Cable Connection ................................................................................................................... 24 Figure 3. Auto-Negotiation and Parallel Operation .............................................................................................................. 26 Figure 4. Destination Address Lookup and Resolution Flow Chart ..................................................................................... 32 Figure 5. EEE Transmit and Receive Signaling Paths ........................................................................................................ 35 Figure 6. Traffic Activity and EEE LPI Operations ............................................................................................................... 37 Figure 7. SPI Access Timing ................................................................................................................................................ 41 Figure 8. SPI Multiple Access Timing .................................................................................................................................. 42 Figure 9. 802.1p Priority Field Format ................................................................................................................................. 48 Figure 10. Tail Tag Frame Format ....................................................................................................................................... 52 Figure 11. ACL Format......................................................................................................................................................... 59 Figure 12. Interface and Register Mapping.......................................................................................................................... 63 Figure 13. ACL Table Access ............................................................................................................................................ 114 Figure 14. RGMII v2.0 Specification (Figure3-Multiplexing and Timing Diagram)............................................................. 143 Figure 15. MAC Mode MII Timing - Data Received from MII ............................................................................................ 144 Figure 16. MAC Mode MII Timing - Data Transmitted from MII ........................................................................................ 144 Figure 17. PHY Mode MII Timing - Data Received from MII............................................................................................. 145 Figure 18. PHY Mode MII Timing - Data Transmitted from MII......................................................................................... 145 Figure 19. RMII Timing - Data Received from RMII .......................................................................................................... 146 Figure 20. RMII Timing - Data Transmitted to RMII .......................................................................................................... 146 Figure 21. SPI Input Timing ............................................................................................................................................... 147 Figure 22. Auto-Negotiation Timing ................................................................................................................................... 148 Figure 23. MDC/MDIO Timing............................................................................................................................................ 149 Figure 27. Reset Timing ..................................................................................................................................................... 150 Figure 28. Recommended Reset Circuit ............................................................................................................................ 151 Figure 29. Recommended Circuit for Interfacing with CPU/FPGA Reset .......................................................................... 151 Figure 30. 64-Pin (8mm x 8mm) QFN Package................................................................................................................. 153 July 24, 2014 13 Revision 1.0 Micrel, Inc. KSZ8794CNX List of Tables Table 1. MDI/MDI-X Pin Definitions ...................................................................................................................................... 23 Table 2. Internal Function Block Status ................................................................................................................................ 33 Table 3. Available Interfaces ................................................................................................................................................ 40 Table 4. SPI Connections .................................................................................................................................................... 40 Table 5. MII Management Interface Frame Format .............................................................................................................. 43 Table 6. Signals of RGMII/MII/RMII ...................................................................................................................................... 44 Table 7. Port 4 SW4-RGMII Connection .............................................................................................................................. 45 Table 8. Port 4 SW4-RGMII Clock Delay Configuration hwit Connection Partner.= ........................................................... 45 Table 9. Port 4 SW4-MII Connection ................................................................................................................................... 46 Table 10. Port 4 SW4-RMII Connection ................................................................................................................................ 47 Table 11. Tail Tag Rules ....................................................................................................................................................... 52 Table 12. FID+DA Look-Up in the VLAN Mode ................................................................................................................... 54 Table 13. FID+SA Look-Up in the VLAN Mode ................................................................................................................... 54 Table 14. 10/100/1000Mbps Rate Selection for the Rate limit ............................................................................................ 55 Table 15. Mapping of Functional Areas within the Address Space ..................................................................................... 63 Table 16. Static MAC Address Table ................................................................................................................................. 106 Table 17. VLAN Table ........................................................................................................................................................ 108 Table 18. VLAN ID and Indirect Registers .......................................................................................................................... 109 Table 19. Dynamic MAC Address Table ............................................................................................................................ 110 Table 20. PME Indirect Registers ...................................................................................................................................... 112 Table 21. ACL Indirect Registers for 14 Bytes ACL Rules ................................................................................................. 115 Table 22. Temporal storage for 14 Bytes ACL Rules ......................................................................................................... 120 Table 23. ACL Read and Write Control .............................................................................................................................. 121 Table 24. Port 1 MIB Counter Indirect Memory Offerts ...................................................................................................... 133 Table 25. Format of "Per Port" MIB Counter ....................................................................................................................... 134 Table 26. All Port Dropped Packet MIB Counters............................................................................................................... 134 Table 27. Format of Per Port RX/TX Total Bytes MIB Counter .......................................................................................... 135 Table 28. Format of "All Dropped Packet" MIB Counter ..................................................................................................... 135 Table 29. RGMII v2.0 Specification (Timing Specifics from Table 2) ................................................................................. 143 Table 30. MAC Mode MII Timing Parameters..................................................................................................................... 144 Table 31. PHY Mode MII Timing Parameters ..................................................................................................................... 145 Table 32. RMII Timing Parameters ..................................................................................................................................... 146 Table 33. SPI Input Timing Parameters .............................................................................................................................. 147 Table 34. Auto-Negotiation Timing Parameters .................................................................................................................. 148 Table 35. MDC/MDIO Typical Timing Parameters.............................................................................................................. 149 Table 36. Reset Timing Parameters ................................................................................................................................... 150 Table 37. Transformer Selection Criteria ............................................................................................................................ 152 Table 38. Qualified Magnetic Vendors ................................................................................................................................ 152 Table 39. Typical Reference Crystal Characteristics .......................................................................................................... 152 July 24, 2014 14 Revision 1.0 Micrel, Inc. KSZ8794CNX Pin Configuration 64-Pin QFN Pin Configuration July 24, 2014 15 Revision 1.0 Micrel, Inc. KSZ8794CNX Pin Description Pin Number Pin Name Type(1) 1 VDD12A P 1.2V Core Power 2 VDDAT P 3.3V Analog Power 3 GNDA GND 4 RXP1 I 1 Port 1 Physical receive signal + (differential) 5 RXM1 I 1 Port 1 Physical receive signal - (differential) 6 TXP1 O 1 Port 1 Physical transmit signal + (differential) 7 TXM1 O 1 Port 1 Physical transmit signal - (differential) 8 RXP2 I 2 Port 2 Physical receive signal + (differential) 9 RXM2 I 2 Port 2 Physical receive signal - (differential) 10 TXP2 O 2 Port 2 Physical transmit signal + (differential) 11 TXM2 O 2 Port 2 Physical transmit signal - (differential) 12 VDDAT P 13 RXP3 I 3 Port 3 Physical receive signal + (differential) 14 RXM3 I 3 Port 3 Physical receive signal - (differential) 15 TXP3 O 3 Port 3 Physical transmit signal + (differential) 16 TXM3 O 3 Port 3 Physical transmit signal - (differential) 17 GNDA GND Analog Ground. 18 INTR_N Opu Interrupt: Active low This pin is Open-Drain output pin. Port Pin Function Analog Ground 3.3V Analog Power 19 LED3_1 Ipu/O 3 Port 3 LED Indicator 1 See global Register 11 bits [5:4] for details. Strap Option: Switch Port 4 GMAC4 Interface Mode Select by LED3[1:0] 00 = MII for SW4-MII 01 = RMII for SW4-RMII 10 = Reserved 11 = RGMII for SW4-RGMII (Default) 20 LED3_0 Ipu/O 3 Port 3 LED Indicator 0 See global Register 11 bits [5:4] for details. Strap Option: see LED3_1 21 VDD12D P 22 GNDD GND 1.2V Core Power. Digital Ground. Notes: 1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. GND = Ground. Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. OTRI = Output tristated. PU = Strap pin pull-up. PD = Strap pull-down. NC = No connect or tie to ground for this product only. July 24, 2014 16 Revision 1.0 Micrel, Inc. KSZ8794CNX Pin Description (Continued) Pin Number Pin Name Type(1) Port Pin Function 23 TXEN4/TXD4_CTL Ipd 4 MII/RMII: Port 4 Switch transmit enable. RGMII: Transmit data control. 24 TXD4_0 Ipd 4 RGMII/MII/RMII: Port 4 Switch transmit bit [0]. 25 TXD4_1 Ipd 4 RGMII/MII/RMII: Port 4 Switch transmit bit [1]. 26 GNDD GND 27 VDDIO P 28 29 TXD4_2 TXD4_3 Ipd Ipd 30 TXER4 Ipd 31 NC NC 32 GNDD GND 33 VDD12D P 34 TXC4/REFCLKI4 /GTXC4 I/O Digital Ground. 3.3V, 2.5V or 1.8V digital VDD for digital I/O circuitry. 4 RGMII/MII: Port 4 Switch transmit bit [2]. RMII: No connection. 4 RGMII/MII: Port 4 Switch transmit bit [3]. RMII: No connection. 4 MII: Port 4 Switch transmit error. RGMII/RMII: No connection. No Connect Digital Ground 1.2V Core Power 4 Port 4 Switch GMAC4 Clock Pin MII: 2.5/25MHz clock, PHY mode is output, MAC mode is input. RMII: Input for receiving 50MHz clock in normal mode RGMII: Input 125MHz clock with falling and rising edge to latch data for the transmit. 35 RXC4/GRXC4 I/O 4 Port 4 Switch GMAC4 Clock Pin MII: 2.5/25MHz clock, PHY mode is output, MAC mode is input. RMII: Output 50MHz reference clock for the receiving/transmit in the clock mode. RGMII: Output 125MHz clock with falling and rising edge to latch data for the receiving. 36 RXD4_0 Ipd/O 4 RGMII/MII/RMII: Port 4 Switch receive bit [0]. 37 RXD4_1 Ipd/O 4 RGMII/MII/RMII: Port 4 Switch receive bit [1]. 38 GNDD GND 39 VDDIO P 40 July 24, 2014 RXD4_2 Ipd/O Digital Ground. 3.3V, 2.5V or 1.8V digital VDD for digital I/O circuitry. 4 RGMII/MII: Port 4 Switch receive bit [2]. RMII: No connection. 17 Revision 1.0 Micrel, Inc. KSZ8794CNX Pin Description (Continued) Pin Number 41 42 43 44 45 46 47 48 Pin Name RXD4_3 RXDV4/CRSDV4 /RXD4_CTL RXER4 CRS4 COL4 REFCLKO PME_N LED2_1 Type(1) Ipd/O Ipd/O Ipd/O Ipd/O Ipd/O Port 4 RGMII/MII: Port 4 Switch receive bit [3]. RMII: No connection. 4 MII: RXDV4 is for Port 4 Switch GMII/MII receive data valid. RMII: CRSDV4 is for Port 4 RMII carrier sense/receive data valid output. RGMII: RXD4_CTL is for Port 4 RGMII receive data control 4 MII: Port 4 Switch receives error. RGMII/RMII: No connection. 4 MII: Port 4 Switch MII modes carrier sense. RGMII/RMII: No connection. 4 MII: Port 4 Switch MII collision detects. RGMII/RMII: No connection. 25MHz Clock Output (Option) Controlled by the strap pin LED2_0. Default is enabled, it is better to disabled it if not be used. Ipu/O Power Management Event This output signal indicates that a Wake On LAN event has been detected as a result of a Wake-Up frame being detected. The KSZ8794CNX is requesting the system to wake up from low power mode. Its assertion polarity is programmable with the default polarity to be active low. I/O Ipu/O Pin Function 2 Port 2 LED Indicator 1 See global register 11 bits [5:4] for details. Strap Option: Port 4 MII and RMII Modes Select When Port 4 is MII mode: PU = MAC mode. PD = PHY mode. When Port 4 is RMII mode: PU = Clock mode in RMII, using 25MHz OSC clock and provide 50MHz RMII clock from pin RXC4. PD = Normal mode in RMII, the TXC4/REFCLKI4 pin on the Port 4 RMII will receive an external 50MHz clock. Note: Port 4 also can use either an internal or external clock in RMII mode based on this strap pin or the setting of the Register 86 (0x56) bit [7]. July 24, 2014 18 Revision 1.0 Micrel, Inc. KSZ8794CNX Pin Description (Continued) Pin Number 49 Pin Name LED2_0 Type(1) Ipu/O Port 2 Pin Function Port 2 LED Indicator 0 See global register 11 bits [5:4] for details. Strap Option: REFCLKO Enable PU = REFCLK_O (25MHz) is enabled. (Default) PD = REFCLK_O is disabled Note: It is better to disable this 25MHz clock if do not provide an extra 25MHz clock for system. 50 LED1_1 Ipu/O 1 Port 1 LED Indicator 1. See global Register 11 bits [5:4] for details. Strap Option: PLL Clock Source Select PU = Still use 25MHz clock from XI/XO pin even though it is in Port 4 RMII normal mode. PD = Use external clock from TXC4 in Port 4 RMII normal mode. Note: If received clock in Port 4 RMII normal mode has bigger clock jitter, still can select to use the 25MHz crystal/Oscillator as switch's clock source. 51 LED1_0 Ipu/O 1 Port 1 LED Indicator 0 See global Register 11 bits [5:4] for details. Strap Option: Speed Select in RGMII PU = 1Gbps in RGMII. (Default) PD = 10/100Mbps in RGMII. Note: Programmable through internal registers also. 52 SPIQ Ipd/O All SPI Serial Data Output in SPI Slave Mode Strap Option: Serial Bus Configuration PD = SPI slave mode. PU = MDC/MDIO mode. Note: An external pull-up or pull-down resistor is required. 53 SCL_MDC Ipu All Clock for SPI or MDC/MDIO Interfaces Input clock up to 50MHz in SPI slave mode. Input clock up to 25MHz in MDC/MDIO for MIIM access. 54 SDA_MDIO Ipu/O All Data Line for SPI or MDC/MDIO Interfaces Serial data input in SPI slave mode. MDC/MDIO interface input/output data line. All SPI Interface Chip Select When SPIS_N is high, the KSZ8794CNX is deselected and SPIQ is held in the high impedance state. A high-to-low transition initiates the SPI data transfer. This pin is active low. 55 SPIS_N Ipu 56 VDDIO P 57 GNDD GND 58 RST_N Ipu 59 VDD12D P 1.2V Core Power. 60 VDDAT P 3.3V Analog Power. July 24, 2014 3.3V, 2.5V or 1.8V digital VDD for digital I/O circuitry. Digital Ground. Reset This active low signal resets the hardware in the device. See the timing requirements in the Timing Diagram Section. 19 Revision 1.0 Micrel, Inc. KSZ8794CNX Pin Description (Continued) Pin Number Pin Name 61 ISET 62 GNDA Type(1) Port Pin Function Transmit Output Current Set This pin configures the physical transmit output current. It should be connected to GND thru a 12.4k 1% resistor. GND Analog Ground. 63 XI I Crystal Clock Input/Oscillator Input When using a 25MHz crystal, this input is connected to one end of the crystal circuit. When using a 3.3V oscillator, this is the input from the oscillator. The crystal or oscillator should have a tolerance of 50ppm. 64 XO O Crystal Clock Output. When using a 25MHz crystal, this output is connected to one end of the crystal circuit. July 24, 2014 20 Revision 1.0 Micrel, Inc. KSZ8794CNX Strap-in Options The KSZ8794CNX can function as a managed switch and utilizes strap-in pins to configure the device for different modes. The strap-in option pins are configured by using external pull-up/down resistors to create a high or low state on the pins which are sampled after power down reset or warm reset. The functions are described in the table below. Pin # 49 Pin Name LED2_0 (2) PU/PD Ipu/O Description REFCLKO Enable Strap Option: PU = REFCLK_O (25MHz) is enabled. (Default) PD = REFCLK_O is disabled Port 4 MII and RMII Modes Select Strap Option: When Port 4 is MII mode: PU = MAC mode. PD = PHY mode. 63 LED2_1 Ipu/O When Port 4 is RMII mode: PU = Clock mode in RMII, using 25MHz OSC clock and provide 50MHz RMII clock from pin RXC4. PD = Normal mode in RMII, the TXC4/REFCLKI4 pin on the Port 4 RMII will receive an external 50MHz clock Note: Port 4 also can use either an internal or external clock in RMII mode based on this strap pin or the setting of the Register 86 (0x56) bit [7]. 19,20 51 LED3[1,0] LED1_0 Ipu/O Ipu/O Switch Port 4 GMAC4 Interface Mode Select Strap Option: 00 = MII for SW4-MII 01 = RMII for SW4-RMII 10 = Reserved 11 = RGMII for SW4-RGMII (Default) Port 4 Gigabit Select Strap Option: PU = 1 Gbps in RGMII. (Default) PD = 10/100Mbps in RGMII. Note: Also programmable through internal register. 50 LED1_1 Ipu/O PLL Clock Source Select Strap Option: PU = Still use 25MHz clock from XI/XO pin even though it is in Port 4 RMII normal mode. PD = Use external clock from TXC4 in Port 4 RMII normal mode. Note: If received clock in Port 4 RMII normal mode has bigger clock jitter, still can select to use the 25MHz crystal/Oscillator as switch's clock source. 52 SPIQ Ipd/O Serial Bus Configuration Strap Option: PD = SPI slave mode. (Default) PU = MDC/MDIO mode. Note: An external pull-up or pull-down resistor is requested. Notes: 2. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. July 24, 2014 21 Revision 1.0 Micrel, Inc. KSZ8794CNX Introduction The KSZ8794CNX contains three 10/100 physical layer transceivers, three media access control (MAC) units and one Gigabit media access control (GMAC) units with an integrated Layer 2 managed switch. The device runs in two modes. The first mode is as a three-port stand-alone switch. The second is as four-port switch with a fourth port that is provided through a Gigabit media independent interface that supports RGMII, MII and RMII. This is useful for implementing an integrated broadband router. The KSZ8794CNX has the flexibility to reside in a managed mode. In a managed mode, a host processor has complete control of the KSZ8794CNX via the SPI bus, or the MDC/MDIO interface. On the media side, the KSZ8794CNX supports IEEE 802.3 10BASE-T, 100BASE-TX on all copper ports with AutoMDI/MDIX. The KSZ8794CNX can be used as a fully managed four-port switch or hooked up to a microprocessor via its RGMII/MII/RMII interfaces to allow for integrating into a variety of environments. Physical signal transmission and reception are enhanced through the use of patented analog circuitry and DSP technology that makes the design more efficient and allows for reduced power consumption and smaller die size. Major enhancements from the KSZ8864RMN to the KSZ8794CNX include high speed host interface options such as the RGMII interfaces, power saving features such as IEEE 802.1az energy efficient Ethernet (EEE), MLD snooping, Wake On LAN (WoL), port-based ACL filtering and the port security, programmable QoS priority and flexible rate limiting. Functional Overview: Physical Layer (PHY) 100BASE-TX Transmit The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion, MLT3 encoding and transmission. The circuit starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is set by an external 1% 12.4k resistor for the 1:1 transformer ratio. It has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX transmitter. 100BASE-TX Receive The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and clock recovery, NRZI-to-NRZ conversion, descrambling, 4B/5B decoding, and serial-to-parallel conversion. The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust its characteristics to optimize the performance. In this design, the variable equalizer will make an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. This is an ongoing process and can self-adjust against environmental changes such as temperature variations. The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate for the effect of baseline wander and improve the dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive. The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by the 4B/5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC. PLL Clock Synthesizer The KSZ8794CNX generates 125MHz, 83MHz, 41MHz, 25MHz and 10MHz clocks for system timing. Internal clocks are generated from an external 25MHz crystal or oscillator. Scrambler/Descrambler (100BASE-TX only) The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander. The data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). This can generate a 2047bit non-repetitive sequence. The receiver will then descramble the incoming data stream with the same sequence at the transmitter. July 24, 2014 22 Revision 1.0 Micrel, Inc. KSZ8794CNX 10BASE-T Transmit The 10BASE-T output driver is incorporated into the 100BASE-T driver to allow transmission with the same magnetics. They are internally wave-shaped and pre-emphasized into outputs with a typical 2.3V amplitude. The harmonic contents are at least 27dB below the fundamental when driven by an all-ones Manchester-encoded signal. 10BASE-T Receive On the receive side, input buffers and level detecting squelch circuits are employed. A differential input receiver circuit and a PLL perform the decoding function. The Manchester-encoded data stream is separated into a clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400mV or with short pulsewidths in order to prevent noises at the RXP or RXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KSZ8794CNX decodes a data frame. The receiver clock is maintained active during idle periods in between data reception. MDI/MDI-X Auto Crossover To eliminate the need for crossover cables between similar devices, the KSZ8794CNX supports HP Auto-MDI/MDI-X and IEEE 802.3u standard MDI/MDI-X auto crossover. HP Auto-MDI/MDI-X is the default. The auto-sense function detects remote transmit and receive pairs and correctly assigns transmit and receive pairs for the KSZ8794CNX device. This feature is extremely useful when end users are unaware of cable types, and also, saves on an additional uplink configuration connection. The auto-crossover feature can be disabled through the Port control registers, or MIIM PHY registers. The IEEE 802.3u standard MDI and MDI-X definitions are: Table 1. MDI/MDI-X Pin Definitions MDI MDI-X RJ-45 Pins Signals RJ-45 Pins Signals 1 TD+ 1 RD+ 2 TD- 2 RD- 3 RD+ 3 TD+ 6 RD- 6 TD- July 24, 2014 23 Revision 1.0 Micrel, Inc. KSZ8794CNX Straight Cable A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. The following diagram depicts a typical straight cable connection between a NIC Card (MDI) and a switch, or hub (MDI-X). Figure 1. Typical Straight Cable Connection Crossover Cable A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device. The following diagram shows a typical crossover cable connection between two switches or hubs (two MDI-X devices). Figure 2. Typical Crossover Cable Connection July 24, 2014 24 Revision 1.0 Micrel, Inc. KSZ8794CNX Auto-Negotiation The KSZ8794CNX conforms to the auto-negotiation protocol as described by the 802.3 committee. Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation. Link partners advertise their capabilities to each other, and then compare their own capabilities with those they received from their link partners. The highest speed and duplex setting that is common to the two link partners is selected as the mode of operation. Auto-negotiation is supported for the copper ports only. The following list shows the speed and duplex operation mode (highest to lowest): * 100Base-TX, full-duplex * 100Base-TX, half-duplex * 10Base-T, full-duplex * 10Base-T, half-duplex If auto-negotiation is not supported or the KSZ8794CNX link partner is forced to bypass auto-negotiation, the KSZ8794CNX sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and allows the KSZ8794CNX to establish link by listening for a fixed signal protocol in the absence of auto-negotiation advertisement protocol. The auto-negotiation link up process is shown in the following flow chart. July 24, 2014 25 Revision 1.0 Micrel, Inc. KSZ8794CNX Figure 3. Auto-Negotiation and Parallel Operation July 24, 2014 26 Revision 1.0 Micrel, Inc. KSZ8794CNX LinkMD(R) Cable Diagnostics The LinkMD feature utilizes time domain reflectometry (TDR) to analyze the cabling plant for common cabling problems such as open circuits, short circuits and impedance mismatches. LinkMD works by sending a pulse of known amplitude and duration down the MDI and MDI-X pairs and then analyzes the shape of the reflected signal. Timing the pulse duration gives an indication of the distance to the cabling fault with maximum distance of 200m and accuracy of 2m. Internal circuitry displays the TDR information in a user-readable digital format. Note: Cable diagnostics are only valid for copper connections only. Access LinkMD is initiated by accessing the PHY special control/status Registers {26, 42, 58} and the LinkMD result Registers {27, 43, 59} for Ports 1, 2 and 3 respectively; and in conjunction with the Port Registers control 10 for Ports 1, 2 and 3 respectively to disable Auto MDI/MDIX. Alternatively, the MIIM PHY Registers 0 and 1d can be used for LinkMD access also. Usage The following is a sample procedure for using LinkMD with Registers {26, 27, 29} on Port 1: 1. Disable auto MDI/MDI-X by writing a `1' to Register 29, bit [2] to enable manual control over the differential pair used to transmit the LinkMD pulse. 2. Start cable diagnostic test by writing a `1' to Register 26, bit [4]. This enable bit is self-clearing. 3. Wait (poll) for Register 26, bit [4] to return a `0', and indicating cable diagnostic test is completed. 4. Read cable diagnostic test results in Register 26, bits [6:5]. The results are as follows: 00 = normal condition (valid test) 01 = open condition detected in cable (valid test) 10 = short condition detected in cable (valid test) 11 = cable diagnostic test failed (invalid test) The `11' case, invalid test, occurs when the KSZ8794CNX is unable to shut down the link partner. In this instance, the test is not run, since it would be impossible for the KSZ8794CNX to determine if the detected signal is a reflection of the signal generated or a signal from another source. 5. Get distance to fault by concatenating Register 26, bit [0] and Register 27, bits [7:0]; and multiplying the result by a constant of 0.4. The distance to the cable fault can be determined by the following formula: D (distance to cable fault) = 0.4 x (Register 26, bit [0], Register 27, bits [7:0]) D (distance to cable fault) is expressed in meters. Concatenated value of Registers 26 bit [0] and 27 bits [7:0] should be converted to decimal before decrease 26 and multiplying by 0.4. The constant (0.4) may be calibrated for different cabling conditions, including cables with a velocity of propagation that varies significantly from the norm. For Port 2, 3 and using the MIIM PHY Registers, LinkMD usage is similar. July 24, 2014 27 Revision 1.0 Micrel, Inc. KSZ8794CNX A LinkMD example The following is a sample procedure for using LinkMD on port 1, port 2 and port 3. //Disable Auto-MDI/MDI-X and Force to MDI-X mode //'w' is WRITE the register. `r' is READ register below w 1d 04 w 2d 04 w 3d 04 //Set Internal registers temporary by indirect registers, adjust for LinkMD w 6e a0 w 6f 4d w a0 08 //Enable LinkMD Testing with Fault Cable for port 1, port 2 and port 3 by Port Register Control 8 bit [4] w 1a 10 w 2a 10 w 3a 10 //Wait until Port Register Control 8 bit [4] returns a `0' (Self Clear) //Diagnosis results r 1a r 1b r 2a r 2b r 3a r 3b //For example on port 1, the result analysis based on the values of the register 0x1a and 0x1b //The register 0x1a bits [6-5] are for the open or the short detection. //The register 0x1a bit [0] + the register 0x1b bits [7-0] = CDT_Fault_Count [8-0] //The distance to fault is about 0.4 x (CDT_Fault_Count [8-0]) On-chip Termination and Internal Biasing The KSZ8794CNX reduces the board cost and simplifies the board layout by using on-chip termination resistors for all ports and RX/TX differential pairs without the external termination resistors. The combination of the on-chip termination and the internal biasing will save more PCB space and power consumption in system, compared with using external biasing and termination resistors for multiple ports' switches because the transformers do not consume power anymore. The center taps of the transformer should not need to be tied to the analog power. July 24, 2014 28 Revision 1.0 Micrel, Inc. KSZ8794CNX Functional Overview: Media Access Controller (MAC) Media Access Controller (MAC) Operation The KSZ8794CNX strictly abides by IEEE 802.3 standards to maximize compatibility. Inter-Packet Gap (IPG) If a frame is successfully transmitted, the 96-bit time IPG is measured between the two consecutive MTXEN. If the current packet is experiencing collision, the 96-bit time IPG is measured from MCRS and the next MTXEN. Back-off Algorithm The KSZ8794CNX implements the IEEE Standard 802.3 binary exponential back-off algorithm, and optional "aggressive mode" back-off. After 16 collisions, the packet may be optionally dropped depending on Register 3's chip configuration. Late Collision If a transmit packet experiences collisions after 512-bit times of the transmission, the packet will be dropped. Illegal Frames The KSZ8794CNX discards frames less than 64 bytes and can be programmed to accept frames up to 1536 bytes in Register 4. For special applications, the KSZ8794CNX can also be programmed to accept frames up to 2K bytes in Register 3 bit [6]. Since the KSZ8794CNX supports VLAN tags, the maximum sizing is adjusted when these tags are present. Flow Control The KSZ8794CNX supports standard 802.3x flow control frames on both transmit and receive sides. On the receive side, if the KSZ8794CNX receives a pause control frame, the KSZ8794CNX will not transmit the next normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received before the current timer expires, the timer will be updated with the new value in the second pause frame. During this flow controlled period, only flow control packets from the KSZ8794CNX will be transmitted. On the transmit side, the KSZ8794CNX has intelligent and efficient ways to determine when to invoke flow control. The flow control is based on availability of the system resources, including available buffers, available transmit queues and available receive queues. The KSZ8794CNX flow controls the port that receives a packet if the destination port resource is busy. The KSZ8794CNX issues a flow control frame (XOFF), containing the maximum pause time defined in IEEE standard 802.3x. Once the resource is freed up, the KSZ8794CNX sends out the other flow control frame (XON) with zero pause time to turn off the flow control, which turns on transmission to the port. A hysteresis feature is also provided to prevent over-activation and deactivation of the flow control mechanism. The KSZ8794CNX flow controls all ports if the receive queue becomes full. Half-Duplex Back Pressure The KSZ8794CNX also provides a half-duplex back pressure option. Note that this is not in IEEE 802.3 standards. The activation and deactivation conditions are the same as the ones given for full-duplex mode. If back pressure is required, the KSZ8794CNX sends preambles to defer the other station's transmission (carrier sense deference). To avoid jabber and excessive deference as defined in IEEE 802.3 standards, after a certain period of time, the KSZ8794CNX discontinues carrier sense but raises it quickly after it drops packets to inhibit other transmissions. This short silent time (no carrier sense) is to prevent other stations from sending out packets and keeps other stations in a carrier sensedeferred state. If the port has packets to send during a back pressure situation, the carrier sense-type back pressure is interrupted and those packets are transmitted instead. If there are no more packets to send, carrier sense-type back pressure becomes active again until switch resources are free. If a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is generated immediately, reducing the chance of further colliding and maintaining carrier sense to prevent reception of packets. To ensure no packet loss in 10BASE-T or 100BASE-TX half-duplex modes, the user must enable the following: * Aggressive back-off (Register 3, bit [0]) * No excessive collision drop (Register 4, bit [3]) * Back pressure (Register 4, bit [5]) These bits are not set as the default because this is not the IEEE standard. July 24, 2014 29 Revision 1.0 Micrel, Inc. KSZ8794CNX Broadcast Storm Protection The KSZ8794CNX has an intelligent option to protect the switch system from receiving too many broadcast packets. Broadcast packets are normally forwarded to all Ports except the source Port and thus use too many switch resources (bandwidth and available space in transmit queues). The KSZ8794CNX has the option to include "multicast packets" for storm control. The broadcast storm rate parameters are programmed globally and can be enabled or disabled on a per port basis. The rate is based on a 50ms (0.05s) interval for 100BT and a 500ms (0.5s) interval for 10BT. At the beginning of each interval, the counter is cleared to zero and the rate limit mechanism starts to count the number of bytes during the interval. The rate definition is described in Registers 6 and 7. The default setting for Registers 6 and 7 is 0x4A (74 decimal). This is equal to a rate of 1%, calculated as follows: 148,80 frames/sec X 50ms (0.05s)/interval X 1% = 74 frames/interval (approx.) = 0x4A July 24, 2014 30 Revision 1.0 Micrel, Inc. KSZ8794CNX Functional Overview: Switch Core Address Look-Up The internal look-up table stores MAC addresses and their associated information. It contains a 1K unicast address table plus switching information. The KSZ8794CNX is guaranteed to learn 1K addresses and distinguishes itself from a hashbased look-up table, which, depending on the operating environment and probabilities, may not guarantee the absolute number of addresses it can learn. Learning The internal look-up engine updates its table with a new entry if the following conditions are met: * The received packet's source address (SA) does not exist in the look-up table. * The received packet is good; the packet has no receiving errors and is of legal length. The look-up engine inserts the qualified SA into the table, along with the Port number and time stamp. If the table is full, the last entry of the table is deleted first to make room for the new entry. Migration The internal look-up engine also monitors whether a station is moved. If this occurs, it updates the table accordingly. Migration happens when the following conditions are met: * The received packet's SA is in the table but the associated source Port information is different. * The received packet is good; the packet has no receiving errors and is of legal length. The look-up engine will update the existing record in the table with the new source Port information. Aging The look-up engine will update the time stamp information of a record whenever the corresponding SA appears. The time stamp is used in the aging process. If a record is not updated for a period of time, the look-up engine will remove the record from the table. The look-up engine constantly performs the aging process and will continuously remove aging records. The aging period is 300 +/- 75 seconds. This feature can be enabled or disabled through Register 3 bit [2]. Forwarding The KSZ8794CNX will forward packets using an algorithm that is depicted in the following flowcharts. Figure 4 shows stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table for the destination address, and comes up with "Port to forward 1" (PTF1). PTF1 is then further modified by the spanning tree, IGMP snooping, port mirroring, and port VLAN processes and authentication to come up with "Port to forward 2" (PTF2). The authentication and ACL have highest priority in the forwarding process, ACL result will overwrite the result of the forwarding process. This is where the packets will be sent. The KSZ8794CNX will not forward the following packets: 1. Error packets These include framing errors, Frame Check Sequence (FCS) errors, alignment errors, and illegal size packet errors. 2. IEEE802.3x PAUSE frames KSZ8794CNX intercepts these packets and performs full duplex flow control accordingly. 3. "Local" packets Based on destination address (DA) lookup, if the destination port from the lookup table matches the port from which the packet originated, the packet is defined as "local." July 24, 2014 31 Revision 1.0 Micrel, Inc. KSZ8794CNX Figure 4. Destination Address Lookup and Resolution Flow Chart Switching Engine The KSZ8794CNX features a high-performance switching engine to move data to and from the MAC's packet buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency. The KSZ8794CNX has a 64kB internal frame buffer. This resource is shared between all five Ports. There are a total of 512 buffers available. Each buffer is sized at 128Byte. July 24, 2014 32 Revision 1.0 Micrel, Inc. KSZ8794CNX Functional Overview: Power The KSZ8794CNX device requires 3.3V analog power. An external 1.2V LDO provides the necessary 1.2V to power the analog and digital logic cores. The various I/O's can be operated at 1.8V, 2.5V, and 3.3V. Table below illustrates the various voltage options and requirements of the device. Power Signal Name Device Pin Requirement VDDAT 2,12, 60 VDDIO 27, 39, 56 VDD12A 1 VDD12D 21, 33, 59 1.2V core power. Filtered 1.2V input voltage. These pins feed 1.2V to power the internal analog and digital cores. GNDA 3, 17, 62 Analog Ground. GNDD 22, 26, 32, 38,57 Digital Ground. 3.3V input power to the analog blocks of transceiver in the device. Choice of 1.8V or 2.5V or 3.3V for the I/O circuits. These input power pins power the I/O circuitry of the device. Functional Overview: Power Management The KSZ8794CNX supports enhanced power management in a low power state, with energy detection to ensure low power dissipation during device idle periods. There are three operation modes under the power management function which are controlled by the Register 14 bits [4:3] and the Port Control 10 Register bit [3] as shown below: Register 14 bits [4:3] = 00 Normal Operation Mode Register 14 bits [4:3] = 01 Energy Detect Mode Register 14 bits [4:3] = 10 Soft Power Down Mode Register 14 bits [4:3] = 11 Reserved The Port Control 10 Register 29, 45, 61 bit [3] = 1 are for the Port Based Power-Down Mode. Table 2 indicates all internal function blocks' status under four different power management operation modes. Table 2. Internal Function Block Status KSZ8794CNX Function Blocks Power Management Operation Modes Normal Mode Energy Detect Mode Soft Power Down Mode Internal PLL Clock Enabled Disabled Disabled Tx/Rx PHY Enabled Energy detect at Rx Disabled MAC Enabled Disabled Disabled Host Interface Enabled Disabled Disabled Normal Operation Mode This is the default setting bits [4:3] = 00 in Register 14 after chip power-up or hardware reset. When KSZ8794CNX is in normal operation mode, all PLL clocks are running, PHY and MAC are on, and the host interface is ready for CPU read or writes. During normal operation mode, the host CPU can set the bits [4:3] in Register 14 to change the current normal operation mode to any one of the other three power management operation modes. Energy Detect Mode Energy detect mode provides a mechanism to save more power than in the normal operation mode when the KSZ8794CNX Port is not connected to an active link partner. In this mode, the device will save more power when the cables are unplugged. If the cable is not plugged in, the device can automatically enter a low power state--the energy detect mode. In this mode, the device will keep transmitting 120ns width pulses at a 1-pulse rate. Once activity resumes July 24, 2014 33 Revision 1.0 Micrel, Inc. KSZ8794CNX due to plugging a cable in or attempting by the far end to establish link, the device can automatically power up to normal power state in energy detect mode. The energy detect mode consists of two states, normal power state and low power state. While in low-power state, the device reduces power consumption by disabling all circuitry except the energy detect circuit of the receiver. The energy detect mode is entered by setting bits [4:3] = 01 in Register 14. When the KSZ8794CNX is in this mode, it will monitor the cable energy. If there is no energy on the cable for a time longer than the pre-configured value at bits [7:0] the go-sleep time in Register 15, KSZ8794CNX will go into low power state. When KSZ8794CNX is in low power state, it will keep monitoring the cable energy. Once the energy is detected from the cable, the device will enter normal power state. When the device is at normal power state, it is able to transmit or receive packet from the cable. Soft Power-Down Mode The soft power-down mode is entered by setting bits [4:3] = 10 in Register 14. When KSZ8794CNX is in this mode, all PLL clocks are disabled, also all of PHYs and the MACs are off. Any dummy host access will wake-up this device from current soft power down mode to normal operation mode and internal reset will be issued to make all internal Registers go to the default values. Port-based Power-Down Mode In addition, the KSZ8794CNX features a per-port power down mode. To save power, a PHY port that is not in use can be powered down via the Port Control 10 Register bit [3], or MIIM PHY Register 0 bit [11]. Energy Efficient Ethernet (EEE) Along with the supports of different type of power saving modes (H/W power down, S/W power down and Energy Detect mode), the KSZ8794CNX extends the green function capability by supporting EEE (Energy Efficient Ethernet) features defined in IEEE P802.3azTM/D2.3, March 2010. Both 10Base-T and 100Base-TX EEE functions are supported in KSZ8794CNX. In 100Base-TX the EEE operation is asymmetric on the same link, which means one direction could be at Low Power Idle (LPI) state while another direction could exist on packet transfer activity. Differing from other types of power saving modes, the EEE is able to maintain the link while power saving is achieved. Based on EEE specification, the energy saving from EEE is done at the PHY level. KSZ8794CNX reduces the power consumption not only at PHY level but also at MAC and switch level by shutting down the unused clocks as much as possible when the device is in a LPI phase. July 24, 2014 34 Revision 1.0 Micrel, Inc. KSZ8794CNX Figure 5. EEE Transmit and Receive Signaling Paths The KSZ8794CNX supports the IEEE 802.3az EEE standard for both 10 and 100Mbps interfaces. The EEE capability combines switch, MAC with PHY to support operation in the LPI mode. When the LPI mode is enabled, systems on both sides of the link can save power during periods of low link utilization. EEE implementation provides a protocol to coordinate transitions to or from lower power consumption without changing the link status and without dropping or corrupting frames. The transition time into and out of the lower power consumption is kept small enough to be transparent to upper layer protocols and applications. EEE specifies means to exchange capabilities between link partners to determine whether EEE is supported and to select the best set of parameters common to both sides. Besides supporting the 100BASE-TX PHY EEE, KSZ8794CNX also supports 10BASE-T with reduced transmit amplitude requirements for 10Mbps mode to allow a reduction in power consumption. LPI Signaling Low Power Idle LPI signaling allows switch to indicate to the PHY, and to the link partner, that a break in the data stream is expected, and switch can use this information to enter power-saving modes that require additional time to resume normal operation. LPI signaling also informs the switch when the link partner has sent such an indication. The definition of LPI signaling uses the MAC for simplified full-duplex operation (with carrier sense deferral). This provides full-duplex operation but uses the carrier sense signal to defer transmission when the PHY is in the LPI mode. The decision on when to signal LPI (LPI request) to the link partner is made by the switch and communicated to the PHY through MAC MII interface. The switch is also informed when the link partner is signaling LPI, indication of LPI activation (LPI indication) on the MAC interface. The conditions under which switch decides to send LPI, and what actions are taken by switch when it receives LPI from the link partner, are specified in implementation section. LPI Assertion Without LPI assertion, the normal traffic transition continues on the MII interface. As soon as an LPI request is asserted, the LPI assert function starts to transmit the "Assert LPI" encoding on the MII and stop the MAC from transmitting normal July 24, 2014 35 Revision 1.0 Micrel, Inc. KSZ8794CNX traffic. Once the LPI request is de-asserted, the LPI assert function starts to transmit the normal inter-frame encoding on the MII again. After a delay, the MAC is allowed to start transmitting again. This delay is provided to allow the link partner to prepare for normal operation. The following figure illustrates the EEE LPI between two active data idles. LPI Detection In the absence of "Assert LPI" encoding on the receive MII, the LPI detect function maps the receive MII signals as normal conditions. At the start of LPI, indicated by the transition from normal inter-frame encoding to the "Assert LPI" encoding on the receive MII, the LPI detect function continues to indicate idle on interface, and asserts LP_IDLE indication. At the end of LPI, indicated by the transition from the "Assert LPI" encoding to any other encoding on the receive MII, LP_IDLE indication is de-asserted and the normal decoding operation resumes. PHY LPI Transmit Operation When the PHY detects the start of "Assert LPI" encoding on the MII, the PHY signals sleep to its link partner to indicate the local transmitter is entering LPI mode. The EEE capability requires the PHY transmitter to go quiet after sleep is signaled. LPI requests are passed from one end of the link to the other and system energy savings can be achieved even if the PHY link does not go into a low power mode. The transmit function of the local PHY is enabled periodically to transmit refresh signals that are used by the link partner to update adaptive filters and timing circuits in order to maintain link integrity. This quiet-refresh cycle continues until the reception of the normal inter-frame encoding on the MII. The transmit function in the PHY communicates this to the link partner by sending a wake signal for a predefined period of time. The PHY then enters the normal operating state. No data frames are lost or corrupted during the transition to or from the LPI mode. In 100BT/Full duplex EEE operation, Refresh transmission are used to maintain link and the Quiet periods are used for the power saving. Approximately, every 20-22ms a Refresh of 200-220us is sent to the link partner. The Refresh transmission and Quiet periods are shown in Figure 6. July 24, 2014 36 Revision 1.0 Micrel, Inc. KSZ8794CNX Figure 6. Traffic Activity and EEE LPI Operations PHY LPI Receive Operation On receive, entering the LPI mode is triggered by the reception of a sleep signal from the link partner, which indicates that the link partner is about to enter the LPI mode. After sending the sleep signal, the link partner ceases transmission. When the receiver detects the sleep signal, the local PHY indicates "Assert LPI" on the MII and the local receiver can disable some functionality to reduce power consumption. The link partner periodically transmits refresh signals that are used by the local PHY. This quiet-refresh cycle continues until the link partner initiates transition back to normal mode by transmitting the wake signal for a predetermined period of time controlled by the LPI assert function. This allows the local receiver to prepare for normal operation and transition from the "Assert LPI" encoding to the normal inter-frame encoding on the MII. After a system specified recovery time, the link supports the nominal operational data rate. Negotiation with EEE Capability The EEE capability shall be advertised during the auto-negotiation stage. Auto-negotiation provides a linked device with the capability to detect the abilities supported by the device at the other end of the link, determine common abilities, and configure for joint operation. Auto-negotiation is performed at power up or reset, on command from management, due to link failure, or due to user intervention. During auto-negotiation, both link partners indicate their EEE capabilities. EEE is supported only if during Auto-negotiation both the local device and link partner advertise the EEE capability for the resolved PHY type. If EEE is not supported, all EEE functionality is disabled and the LPI client does not assert LPI. If EEE is supported by both link partners for the negotiated PHY type, then the EEE function can be used independently in either direction. July 24, 2014 37 Revision 1.0 Micrel, Inc. KSZ8794CNX Wake on LAN (WoL) Wake on LAN allows a computer to be turned on or woken up by a network message. The message is usually sent by a program executed on another computer on the same local area network. Wake-up frame events are used to wake the system whenever meaningful data is presented to the system over the network. Examples of meaningful data include the reception of a Magic Packet, a management request from a remote administrator, or simply network traffic directly targeted to the local system. The KSZ8794CNX can be programmed to notify the host of the Wake-Up frame detection with the assertion of the interrupt signal (INTR_N) or assertion of the power management event signal (PME). The PME control is by PME indirect Registers. KSZ8794CNX MAC supports the detection of the following Wake-Up events: * Detection of energy signal over a pre-configured value: Port PME Control Status Register bit [0] in PME indirect registers. * Detection of a linkup in the network link state: Port PME Control Status Register bit [1] in the PME indirect registers. * Receipt of a Magic Packet: Port PME Control Status Register bit [2] in the PME indirect registers. There are also other types of Wake-Up events that are not listed here as manufacturers may choose to implement these in their own way. Direction of Energy The energy is detected from the cable and is continuously presented for a time longer than pre-configured value, especially when this energy change may impact the level at which the system should re-enter to the normal power state. Direction of Link-up Link status wake events are useful to indicate a linkup in the network's connectivity status. Magic PacketTM The Magic Packet is a broadcast frame containing anywhere within its payload 6 bytes of all 1s (FF FF FF FF FF FF) followed by sixteen repetitions of the target computer's 48-bit DA MAC address. Since the magic packet is only scanned for the above string, and not actually parsed by a full protocol stack, it may be sent as any network- and transport-layer protocol. Magic Packet technology is used to remotely wake up a sleeping or powered off PC on a LAN. This is accomplished by sending a specific packet of information, called a Magic Packet frame, to a node on the network. When a PC capable of receiving the specific frame goes to sleep, it enables the Magic Packet RX mode in the LAN controller. When the LAN controller receives a Magic Packet frame, it will alert the system to wake up. Once the KSZ8794CNX has been enabled for Magic Packet Detection in Port PME Control Mask Register bit [2] in the PME indirect register, it scans all incoming frames addressed to the node for a specific data sequence, which indicates to the controller this is a Magic Packet frame. A Magic Packet frame must also meet the basic requirements for the LAN technology chosen, such as Source Address (SA), Destination Address (DA), which may be the receiving station's IEEE MAC address, or a multicast or broadcast address and CRC. The specific sequence consists of 16 duplications of the MAC address of this node, with no breaks or interruptions. This sequence can be located anywhere within the packet, but must be preceded by a synchronization stream. The synchronization stream is defined as 6 bytes of 0xFF. The device will also accept a broadcast frame, as long as the 16 duplications of the IEEE address match the address of the machine to be awakened. Example of Magic Packet: If the IEEE address for a particular node on a network is 11h 22h, 33h, 44h, 55h, 66h, the LAN controller would be scanning for the data sequence (assuming an Ethernet frame): DA - SA - TYPE - FF FF FF FF FF FF - 11 22 33 44 55 66 -11 22 33 44 55 66-11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 11 22 33 44 55 66 - 11 22 33 44 55 66 -11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 11 22 3344 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 -MISC-CRC. There are no further restrictions on a Magic Packet frame. For instance, the sequence could be in a TCP/IP packet or an IPX packet. The frame may be bridged or routed across the network without affecting its ability to wake-up a node at the frame's destination. If the scans do not find the specific sequence shown above, it discards the frame and takes no further action. If the KSZ8794CNX detects the data sequence, however, it then alerts the PC's power management circuitry (assert the PME pin) to wake up the system. July 24, 2014 38 Revision 1.0 Micrel, Inc. KSZ8794CNX Interrupt (INT_N/PME_N) INT_N is an interrupt signal that is used to inform the external controller that there has been a status update in the KSZ8794CNX interrupt status register. Bits [3:0] of Register 125 are the interrupt mask control bits to enable and disable the conditions for asserting the INT_N signal. Bits [3:0] of Register 124 are the interrupt status bits to indicate which interrupt conditions have occurred. The interrupt status bits are cleared after reading those bits in Register 124. PME_N is an optional PME interrupt signal that is used to inform the external controller that there has been a status update in the KSZ8794CNX interrupt status register. Bits [4] of Register 125 are the PME mask control bits to enable and disable the conditions for asserting the PME_N signal. Bits [4] of Register 124 are the PME interrupt status bits to indicate which PME interrupt conditions have occurred. The PME interrupt status bit [4] is cleared after reading this bit of Register 124. Additionally, the interrupt pins of INT_N and PME_N eliminate the need for the processor to poll the switch for status change. July 24, 2014 39 Revision 1.0 Micrel, Inc. KSZ8794CNX Functional Overview: Interfaces The KSZ8794CNX device incorporates a number of interfaces to enable it to be designed into a standard network environment as well as a vendor unique environment. The available interfaces are summarized in Table 3. The detail of each usage in this table is provided in the following sections. Table 3. Available Interfaces Registers Accessed Interface Type Usage SPI Configuration and Register Access [As Slave Serial Bus] - External CPU or controller can R/W all internal registers thru this interface. MIIM Configuration and Register Access MDC/MDIO capable CPU or controllers can R/W 3 PHYs registers. PHYs Only RMII Data Flow Interface to the Port 4 GMAC using the faster reduced RMII timing. n/a MII Data Flow Interface to the Port 4 GMAC using the standard MII timing. n/a RGMII Data Flow Interface to the Port 4 GMAC using the faster reduced RGMII timing. n/a All Configuration Interface SPI Slave Serial Bus Configuration The KSZ8794CNX can also act as an SPI slave device. Through the SPI, the entire feature set can be enabled, including "VLAN," "IGMP snooping," "MIB counters," etc. The external master device can access any register from Register 0 to Register 127 randomly. The system should configure all the desired settings before enabling the switch in the KSZ8794CNX. To enable the switch, write a "1" to Register 1 bit [0]. Two standard SPI commands are supported (00000011 for "READ DATA," and 00000010 for "WRITE DATA"). To speed configuration time, the KSZ8794CNX also supports multiple reads or writes. After a byte is written to or read from the KSZ8794CNX, the internal address counter automatically increments if the SPI Slave Select Signal (SPIS_N) continues to be driven low. If SPIS_N is kept low after the first byte is read, the next byte at the next address will be shifted out on SPIQ. If SPIS_N is kept low after the first byte is written, bits on the Master Out Slave Input (SPID) line will be written to the next address. Asserting SPIS_N high terminates a read or write operation. This means that the SPIS_N signal must be asserted high and then low again before issuing another command and address. The address counter wraps back to zero once it reaches the highest address. Therefore the entire register set can be written to or read from by issuing a single command and address. The KSZ8794CNX is able to support a SPI bus up to 50MHz. A high performance SPI master is recommended to prevent internal counter overflow. To use the KSZ8794CNX SPI: 1. At the board level, connect KSZ8794CNX pins as follows: Table 4. SPI Connections KSZ8794CNX Signal Name Microprocessor Signal Description SPIS_N (S_CS) SPI Slave Select. SCL (S_CLK) SPI Clock. SDA (S_DI) Master Output. Slave Input. SPIQ (S_DO) Master Input. Slave Output. 2. Configure the serial communication to SPI slave mode by pulling down pin SPIQ with a pull-down resistor. 3. Write configuration data to registers using a typical SPI write data cycle as shown in Figure 7 or SPI multiple write as shown in Figure 8. Note that data input on SDA is registered on the rising edge of SCL clock. 4. Registers can be read and the configuration can be verified with a typical SPI read data cycle as shown in Figure 7 or a multiple read as shown in Figure 8. Note that read data is registered out of SPIQ on the falling edge of SCL clock. July 24, 2014 40 Revision 1.0 Micrel, Inc. KSZ8794CNX Figure 7. SPI Access Timing July 24, 2014 41 Revision 1.0 Micrel, Inc. KSZ8794CNX Figure 8. SPI Multiple Access Timing July 24, 2014 42 Revision 1.0 Micrel, Inc. KSZ8794CNX MII Management Interface (MIIM) The KSZ8794CNX supports the standard IEEE 802.3 MII Management Interface, also known as the Management Data Input/output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the states of the KSZ8794CNX. An external device with MDC/MDIO capability is used to read the PHY status or configure the PHY settings. Further details on the MIIM interface are found in Clause 22.2.4.5 of the IEEE 802.3u Specification. The MIIM interface consists of the following: * A physical connection that incorporates the data line MDIO and the clock line MDC. * A specific protocol that operates across the aforementioned physical connection that allows an external controller to communicate with the KSZ8794CNX device. * Access to a set of eight 16-bit registers, consisting of 8 standard MIIM Registers [0:5h], 1d and 1f MIIM registers per port. The MIIM Interface can operate up to a maximum clock speed of 25MHz MDC clock. The following table depicts the MII Management Interface frame format. Table 5. MII Management Interface Frame Format Preamble Start of Frame Read/Write OP Code PHY Address Bits[4:0] REG Address Bits[4:0] TA Data Bits[15:0] Idle Read 32 1's 01 10 AAAAA RRRRR Z0 DDDDDDDD_DDDDDDDD Z Write 32 1's 01 01 AAAAA RRRRR 10 DDDDDDDD_DDDDDDDD Z The MIIM interface does not have access to all the configuration registers in the KSZ8794CNX. It can only access the standard MIIM registers. See "MIIM Registers". The SPI interface, on the other hand, can be used to access all registers with the entire KSZ8794CNX feature set. July 24, 2014 43 Revision 1.0 Micrel, Inc. KSZ8794CNX Switch Port 4 GMAC Interface The KSZ8794CNX GMAC4 interface supports MII/RGMII/RMII four interfaces protocols and shares one set of input/output signals. The purpose of this interface is to provide a simple, inexpensive, and easy-to implement interconnection between the GMAC/MAC sub layer and a GPHY/PHY. Data on these interfaces are framed using the IEEE Ethernet standard. As such it consists of a preamble, start of frame delimiter, Ethernet headers, protocol specific data and a cyclic redundancy check (CRC) checksum. Transmit and Receive signals for MII/RGMII/RMII interfaces shown in Table 6. Table 6. Signals of RGMII/MII/RMII Direction Type RGMII MII RMII Input (Output) GTXC TXC REFCLKI Input Input TXER TXD_CTL TXEN Input (Output) COL Input TXD[3:0] Input (Output) GRXC TXD[3:0] Output Output RXD_CTL Input (Output) Output TXEN TXD[1:0] RXC RXC RXER RXER RXDV CRS_DV CRS RXD[3:0] RXD[3:0] RXD[1:0] Standard Media Independent Interface [MII] The MII interface is capable of supporting 10/100Mbps. Data and delimiters are synchronous to clock references. It provides independent four transmit and receive data paths and uses signal levels, two media status signals are provided. The CRS indicates the presence of carrier, and the COL indicates the occurrence of a collision. Both half and full duplex operations are provided by MII interface. The MII transfers data using 4-bit words (nibble) in each direction. Clocked at 2.5/25MHz to achieve 10/100Mbps speed. Reduced Media Independent Interface [RMII] The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). The KSZ8794CNX supports the RMII interface on the Port 4 GMAC4 and provides the following key characteristics: * Supports 10Mbps and 100Mbps data rates. * Uses a single 50MHz clock reference (provided internally or externally): in internal mode, the chip provides a reference clock from the RXC pin to the opposite clock input pin for RMII interface. In external mode, the chip receives 50MHz reference clock from an external oscillator or opposite RMII interface. * Provides independent 2-bit wide (bi-bit) transmit and receive data paths. Reduced Gigabit Media Independent Interface [RGMII] It is intended to be an alternative to the IEEE802.3u MII and the IEEE802.3z RGMII. The principle objective is to reduce the number of pins required to interconnect the GMAC and the GPHY in a cost effective and technology independent manner. In order to accomplish this objective, the data paths and all associated control signals will be reduced and control signals will be multiplexed together and both edges of the clock will be used. For gigabit operation, the clocks will operate at 125MHz with using rising edge and falling edge to latch data. July 24, 2014 44 Revision 1.0 Micrel, Inc. KSZ8794CNX Port 4 GMAC4 SW4-RGMII Interface Table 7 shows the RGMII reduced connections when connecting to an external GMAC or GPHY: Table 7. Port 4 SW4-RGMII Connection KSZ8794CNX SW4-RGMII Connection External GMAC/GPHY KSZ8794CNX SW4-RGMII Signals Type Description MRX_CTL TXD4_CTL Input Transmit control MRXD[3:0] TXD4[3:0] Input Transmit data bit [3:0] MRX_CLK GTX4_CLK Input Transmit clock MTX_CTL RXD4_CTL Output Receive control MTXD[3:0] RXD4[3:0] Output Receive data bit [3:0] MGTX_CLK GRXC4 Output Receive clock The RGMII interface operates at up to a 1000Mbps speed rate. Additional transmit and receive signals control the different direction of the data transfer. This RGMII interface supports RGMII Rev 2.0 with adjustble ingress clock and egress clock delay by the Register 86 (0x56). For RGMII correct configuration with the connection partner, the Register 86 (0x56) bits [4:3] need to setup correctly, a configuration table as below. Table 8. Port 4 SW4-RGMII Clock Delay Configuration with Connection Partner.= KSZ8794 Register 86 Bits [4:3] Configuration Bit [4:3]=11 Mode Bit [4:3]=10 Mode Bit [4:3]=01 Mode Bit [4:3]=00 Mode RGMII Clock Mode (Receive and Transmit) KSZ8794 Register 86 (0x56) KSZ8794 RGMII Clock Delay/Slew Configuration Connection Partner RGMII Clock Configuration (A processor, an external GPHY or back to back connection) Ingress Clock Input Bit [4] = 1 Delay No Delay Egress Clock Output Bit [3] = 1 Delay No Delay Ingress Clock Input Bit [4] = 1 Delay No Delay Egress Clock Output Bit [3] = 0 No Delay Delay Ingress Clock Input Bit [4] = 0 (default) No Delay Delay Egress Clock Output Bit [3] = 1 (default) Delay No Delay Ingress Clock Input Bit [4] = 0 No Delay Delay Egress Clock Output Bit [3] = 0 No Delay Delay For example, two KSZ8795 devices are the back to back connection, if one device set bit [4:3] ='11', another one should set bit [4:3] = `00'. If one device set bit [4:3] ='01', another one should set bit [4:3] = `01' too. The RGMII mode is configured by the strap-in pin LED3 [1:0] ='11' (default) or Register 86 (0x56) bits [1:0] = `11' (default). The speed choice is by the strap-in pin LED1_0 or Register 86 (0x56) bit [6], the default speed is 1Gbps with bit [6] = 1', set bit [6] = `0' is for 10/100Mbps speed in RGMII mode. KSZ8795CLX provides Register 86 Bits [4:3] with the adjustable clock delay and Register 164 Bits [6:4] with the adjustable drive strength for best RGMII timing on board level in 1Gbps mode. July 24, 2014 45 Revision 1.0 Micrel, Inc. KSZ8794CNX Port 4 GMAC4 SW4-MII Interface Table 9 shows two connection methods below: 1. The first is an external MAC connecting in SW4-MII PHY mode. 2. The second is an external PHY connecting in SW4-MII MAC mode. 3. The MAC mode or PHY mode setting is determined by the strap pin LED2_1. Table 9. Port 4 SW4-MII Connection MAC to MAC Connection KSZ8794CNX SW4-MII PHY Mode MAC to PHY Connection KSZ8794CNX SW4-MII MAC Mode External MAC KSZ8794CNX SW4-MII Signals Type Description External PHY KSZ8794CNX SW4-MII Signals Type MTXEN TXEN4 Input Transmit enable MTXEN RXDV4 Output MTXER TXER4 Input Transmit error MTXER RXER4 Output MTXD[3:0] RXD4[3:0] Output MTXD[3:0] TXD4[3:0] Input Transmit data bit [3:0] MTXC TXC4 Output Transmit clock MTXC RXC4 Input MCOL COL4 Output Collision detection MCOL COL4 Input MCRS CRS4 Output Carrier sense MCRS CRS4 Input MRXDV RXDV4 Output Receive data valid MRXDV TXEN4 Input MRXER RXER4 Output Receive error MRXER TXER4 Input MRXD[3:0] RXD4[3:0] Output Receive data bit [3:0] MRXD[3:0] TXD4[3:0] Input MRXC RXC4 Output Receive clock MRXC TXC4 Input The MII interface operates in either MAC mode or PHY mode. These interfaces are nibble-wide data interfaces, so they run at one-quarter the network bit rate (not encoded). Additional signals on the transmit side indicate when data is valid or when an error occurs during transmission. Likewise, the receive side has indicators that convey when the data is valid and without physical layer errors. For half-duplex operation, there is a COL signal that indicates a collision has occurred during transmission. Note: Normally MRXER would indicate a receive error coming from the physical layer device. MTXER would indicate a transmit error from the MAC device. These signals are not appropriate for this configuration. For PHY mode operation with an external MAC, if the device interfacing with the KSZ8794CNX has an MRXER pin, it can be tied low. For MAC mode operation with an external PHY, if the device interfacing with the KSZ8794CNX has an MTXER pin, it can be tied low. Port 4 GMAC4 SW4-RMII Interface The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). The KSZ8794CNX supports RMII interface on Port 4 and provides the following key characteristics: * Supports 10Mbps and 100Mbps data rates. * Uses a single 50MHz clock reference (provided internally or externally): In internal mode, the chip provides a reference clock from the RXC4 pin to the opposite clock input pin for RMII interface when Port 4 RMII is set to clock mode. * In external mode, the chip receives 50MHz reference clock on the TXC4/REFCLKI4 pin from an external oscillator or opposite RMII interface when the device is set to normal mode. * Provides independent 2-bit wide (bi-bit) transmit and receive data paths. * For the details of SW4-RMII (Port 4 GMAC4 RMII) signal connection, see the table below: When the device is strapped to normal mode, the reference clock comes from the TXC4/REFCLKI4 pin and will be used as the device's clock source. Set the strap pin LED1_1 can select the device's clock source either from the TXC4/REFCLKI4 pin or from an external 25MHz crystal/oscillator clock on the XI/XO pin. July 24, 2014 46 Revision 1.0 Micrel, Inc. KSZ8794CNX In internal mode, when using an internal 50MHz clock as SW4-RMII reference clock, the KSZ8794CNX Port 4 should be set to clock mode by the strap pin LED2_1 or the port Register 86 bit [7]. The clock mode of the KSZ8794CNX device will provide the 50MHz reference clock to the Port 4 RMII interface. In external mode, when using an external 50MHz clock source as SW4-RMII reference clock, the KSZ8794CNX Port 4 should be set to normal mode by the strap pin LED2_1 or the port Register 86 bit [7]. The normal mode of the KSZ8794CNX device will start to work when it receives the 50MHz reference clock on the TXC4/REFCLKI4 pin from an external 50MHz clock source. Table 10. Port 4 SW4-RMII Connection SW4-RMII MAC to MAC Connection (`PHY mode') SW4-RMII MAC to PHY Connection (`MAC mode') External MAC KSZ8794CNX SW4-RMII KSZ8794CNX SW Signal Type Description External PHY KSZ8794CNX SW4-RMII KSZ8794CNX SW Signal Type REF_CLKI RXC4 Output 50MHz in Clock mode Reference Clock 50MHz REFCLKI4 Input 50MHz in Normal Mode CRS_DV RXDV4 /CRSDV4 Output Carrier Sense/Receive data valid CRS_DV TXEN4 Input Receive error RXER TXER4 Input RXD[1:0] RXD4[1:0] Output Receive data bit [1:0] RXD[1:0] TXD4[1:0] Input TX_EN TXEN4 Input Transmit data enable TX_EN RXDV4 /CRSDV4 Output TXD[1:0] TXD4[1:0] Input Transmit data bit [1:0] TXD[1:0] RXD4[1:0] Output 50MHz REFCLKI4 Input 50MHz in Normal Mode Reference Clock REF_CLKI RXC4 Output 50MHz in Clock mode Note: MAC/PHY mode in RMII is different than MAC/PHY mode in MII. There is no strap pin and register configuration request in RMI. Follow the signals connection in the table. July 24, 2014 47 Revision 1.0 Micrel, Inc. KSZ8794CNX Functional Overview: Advanced Functionality QoS Priority Support The KSZ8794CNX provides Quality of Service (QoS) for applications such as VoIP and video conferencing. The KSZ8794CNX offers one, two, or four priority queues per port by setting the Port Control 13 Register bit [1] and the Port Control 0 Register bit [0], the 1/2/4 queues split as follows: [Port Control 9 bit [1], Control 0 Register bit [0]] = 00 Single output queue as default. [Port Control 9 bit [1], Control 0 Register bit [0]] = 01 Egress Port can be split into two priority transmit queues. [Port Control 9 bit [1], Control 0 Register bit [0]] = 10 Egress Port can be split into four priority transmit queues. The four priority transmit queue is a new feature in the KSZ8794CNX. Queue 3 is the highest priority queue and queue 0 is the lowest priority queue. The Port Control 9 Register bit [1] and the Port Control 0 Register bit [0] are used to enable split transmit queues for Ports 1, 2, 3 and 4, respectively. If a Port's transmit queue is not split, high priority and low priority packets have equal priority in the transmit queue. There is an additional option to either always deliver high priority packets first or to use programmable weighted fair queuing for the four priority queue scale by the Port Control 14, 15, 16 and 17 Registers (default values are 8, 4, 2, 1 by their bits [6:0]. Register 130 bit [7:6] Prio_2Q[1:0] is used when the 2 Queue configuration is selected. These bits are used to map the 2bit result of IEEE 802.1p from the registers 128, 129 or TOS/DiffServ mapping from Registers 144-159 (for 4 Queues) into two-queue mode with priority high or low. Please see the descriptions of Register 130 bits [7:6] for detail. Port-based Priority With port-based priority, each ingress Port is individually classified as a priority 0-3 receiving Port. All packets received at the priority 3 receiving Port are marked as high priority and are sent to the high-priority transmit queue if the corresponding transmit queue is split. The Port Control 0 Register bits [4:3] is used to enable Port-based priority for Ports 1, 2, 3 and 4, respectively. 802.1p-based Priority For 802.1p-based priority, the KSZ8794CNX examines the ingress (incoming) packets to determine whether they are tagged. If tagged, the 3-bit priority field in the VLAN tag is retrieved and compared against the "priority mapping" value, as specified by the registers 128 and 129, both register 128/129 can map 3-bit priority field of 0-7 value to 2-bit result of 0-3 priority levels. The "priority mapping" value is programmable. Figure 9 illustrates how the 802.1p priority field is embedded in the 802.1Q VLAN tag. Figure 9. 802.1p Priority Field Format July 24, 2014 48 Revision 1.0 Micrel, Inc. KSZ8794CNX 802.1p-based priority is enabled by bit [5] of the Port Control 0 Registers for ports 1, 2, 3 and 4, respectively. The KSZ8794CNX provides the option to insert or remove the priority tagged frame's header at each individual egress port. This header, consisting of the two-byte VLAN Protocol ID (VPID) and the two-byte tag control Information field (TCI), is also referred to as the IEEE 802.1Q VLAN tag. Tag Insertion is enabled by bit[2] of the Port control 0 Register and the Port Control 8 Register to select which source port (ingress port) PVID can be inserted on the egress port for Ports 1, 2, 3 and 4, respectively. At the egress port, untagged packets are tagged with the ingress port's default tag. The default tags are programmed in the Port Control 3 and control 4 register for ports 1, 2, 3 and 4, respectively. The KSZ8794CNX will not add tags to already tagged packets. Tag Removal is enabled by bit [1] of the port registers control 0 for Ports 1, 2, 3 and 4, respectively. At the egress port, tagged packets will have their 802.1Q VLAN tags removed. The KSZ8794CNX will not modify untagged packets. The CRC is recalculated for both tag insertion and tag removal. 802.1p Priority Field Re-mapping is a QoS feature that allows the KSZ8794CNX to set the "User Priority Ceiling" at any ingress port by the Port Control 2 Register bit [7]. If the ingress packet's priority field has a higher priority value than the default tag's priority field of the ingress port, the packet's priority field is replaced with the default tag's priority field. DiffServ-Based Priority DiffServ-based priority uses the ToS registers (Registers 144 to 159) in the Advanced Control Registers section. The ToS priority control registers implement a fully decoded, 128-bit differentiated services code point (DSCP) register to determine packet priority from the 6-bit ToS field in the IP header. When the most significant six bits of the ToS field are fully decoded, 64 code points for DSCP result. These are compared with the corresponding bits in the DSCP register to determine priority. July 24, 2014 49 Revision 1.0 Micrel, Inc. KSZ8794CNX Spanning Tree Support Port 4 is the designated port for spanning tree support. The other ports (Port 1 - Port 3) can be configured in one of the five spanning tree states via "transmit enable," "receive enable," and "learning disable" register settings in Registers 18, 34 and 50 for Ports 1, 2 and 3, respectively. The following description shows the port setting and software actions taken for each of the five spanning tree states. The KSZ8794CNX supports common spanning tree (CST). To support spanning tree, the host port (Port 4) is the designated port for the processor. The other ports can be configured in one of the five spanning tree states via "transmit enable", "receive enable" and "learning disable" register settings in Port Control 2 Registers. The following table shows the port setting and software actions taken for each of the five spanning tree states. Disable State Port Setting Software Action The port should not forward or receive any packets. Learning is disabled. "Transmit enable = 0, Receive enable = 0, Learning disable = 1." The processor should not send any packets to the port. The switch may still send specific packets to the processor (packets that match some entries in the static table with "overriding bit" set) and the processor should discard those packets. Blocking State Port Setting Only packets to the processor are forwarded. Learning is disabled. "Transmit enable = 0, Receive enable = 0, Learning disable = 1" Listening State Port Setting Software Action Only packets to and from the processor are forwarded. Learning is disabled. "Transmit enable = 0, Receive enable = 0, Learning disable = 1. The processor should program the static MAC table with the entries that it needs to receive (e.g. BPDU packets). The "overriding" bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state, see "Tail Tagging Mode" section for details. Address learning is disabled on the port in this state. Learning State Port Setting Software Action Only packets to and from the processor are forwarded. Learning is enabled. "Transmit enable = 0, Receive enable = 0, Learning disable = 0." Forwarding State Port Setting Packets are forwarded and received normally. Learning is enabled. "Transmit enable = 1, Receive enable = 1, Learning disable = 0." July 24, 2014 Note: Processor is connected to Port 4 via MII interface. Address learning is disabled on the port in this state. Software Action The processor should not send any packets to the port(s) in this state. The processor should program the "Static MAC table" with the entries that it needs to receive (e.g., BPDU packets). The "overriding" bit should also be set so that the switch will forward those specific packets to the processor. Address learning is disabled on the Port in this state. The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU packets). The "overriding" bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state, see "Tail Tagging Mode" section for details. Address learning is enabled on the port in this state. Software Action The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU packets). The "overriding" bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state, see "Tail Tagging Mode" section for details. Address learning is enabled on the port in this state. 50 Revision 1.0 Micrel, Inc. KSZ8794CNX Rapid Spanning Tree Support There are three operational states of the discarding, learning, and forwarding assigned to each port for RSTP. Discarding ports do not participate in the active topology and do not learn MAC addresses. Ports in the Learning states learn MAC addresses, but do not forward user traffic. Ports in the Forwarding states fully participate in both data forwarding and MAC learning. RSTP uses only one type of BPDU called RSTP BPDUs. They are similar to STP Configuration BPDUs with the exception of a type field set to "version 2" for RSTP and "version 0" for STP, and flag field carrying additional information. Disable State Port Setting The state includes three states of the disable, blocking and listening of STP. "Transmit enable = 0, Receive enable = 0, Learning disable = 1." Learning State Port Setting Only packets to and from the processor are forwarded. Learning is enabled. "Transmit enable = 0, Receive enable = 0, Learning disable = 0." Forwarding State Port Setting Packets are forwarded and received normally. Learning is enabled. "Transmit enable = 1, Receive enable = 1, Learning disable = 0." July 24, 2014 Software Action The processor should not send any packets to the port. The switch may still send specific packets to the processor (packets that match some entries in the static table with "overriding bit" set) and the processor should discard those packets. When disable the port's learning capability (learning disable = '1'), set the Register 2 bit [5] and bit [4] will flush rapidly with the port related entries in the dynamic MAC table and static MAC table. Note: processor is connected to Port 4 via MII interface. Address learning is disabled on the port in this state. Software Action The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU packets). The "overriding" bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state, see "Tail Tagging Mode" section for details. Address learning is enabled on the port in this state. Software Action The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU packets). The "overriding" bit should be set so that the switch will forward those specific packets to the processor. The processor may send packets to the port(s) in this state, see "Tail Tagging Mode" section for details. Address learning is enabled on the port in this state. 51 Revision 1.0 Micrel, Inc. KSZ8794CNX Tail Tagging Mode The tail tag is only seen and used by the Port 4 interface, which should be connected to a processor by the SW4- RGMII, MII or RMII interfaces. One byte tail tagging is used to indicate the source/destination port on port 4. Only bits [3:0] are used for the destination in the tail tagging byte. Other bits are not used. The tail tag feature is enabled by setting Register 12 bit [1]. Figure 10. Tail Tag Frame Format Table 11. Tail Tag Rules Ingress to Port 4 (Host --> KSZ8794CNX) Bits [3:0] Destination 0,0,0,0 Reserved 0,0,0,1 Port 1 (Direct forward to Port 1) 0,0,1,0 Port 2 (Direct forward to Port 2) 0,1,0,0 Port 3 (Direct forward to Port 3) 1,0,0,0 Reserved x,1,1,1 Port 1, 2 and 3 (direct forward to Port 1, 2, 3) Bits [7:4] 0,0,0,0 Queue 0 is used at destination Port 0,0,0,1 Queue 1 is used at destination Port 0,0,1,0 Queue 2 is used at destination Port 0,0,1,1 Queue 3 is used at destination Port 0, 1,x,x Anyhow send packets to specified Port in bits [3:0] 1, x,x,x Bits [6:0] will be ignored as normal (Address look-up) Egress from Port 4 (KSZ8794CNX --> Host) Bits [1:0] Source 0,0 Port 1 (Packets from Port 1) 0,1 Port 2 (Packets from Port 2) 1,0 Port 3 (Packets from Port 3) 1,1 Reserved July 24, 2014 52 Revision 1.0 Micrel, Inc. KSZ8794CNX IGMP Support There are two components involved with the support of the internet group management protocol (IGMP) in layer 2. The first part is IGMP snooping, the second part is this IGMP packet which is sent back to the subscribed port. Those components are described below. IGMP Snooping The KSZ8794CNX traps IGMP packets and forwards them only to the processor (port 4 SW4-RGMII/MII/RMII). The IGMP packets are identified as IP packets (either Ethernet IP packets, or IEEE 802.3 SNAP IP packets) with IP version = 0x4 and protocol version number = 0x2. Set Register 5 bit [6] to `1' to enable IGMP snooping. IGMP Send Back to the Subscribed Port Once the host responds to the received IGMP packet, the host should know the original IGMP ingress port and send back the IGMP packet to this port only, to avoid this IGMP packet being broadcast to all ports which will downgrade the performance. With the tail tag mode enabled, the host will know the port which IGMP packet has been received from tail tag bits [1:0] and can send back the response IGMP packet to this subscribed port by setting bits [3:0] in the tail tag. Enable "Tail Tag Mode" by setting register 12 bit[1]. IPv6 MLD Snooping The KSZ8794CNX traps IPv6 multicast listener discovery (MLD) packets and forwards them only to the processor (Port 4). MLD snooping is controlled by Register 164 bit [2] (MLD snooping enable) and Register 164 bit [3] (MLD option). With MLD snooping enabled, the KSZ8794CNX traps packets that meet all of the following conditions: * IPv6 multicast packets * Hop count limit = 1 * IPv6 next header = 1 or 58 (or = 0 with hop-by-hop next header = 1 or 58) If the MLD option bit is set to "1", the KSZ8794CNX traps packets with the following additional condition: * IPv6 next header = 43, 44, 50, 51, or 60 (or = 0 with hop-by-hop next header = 43, 44, 50, 51, or 60) * For MLD snooping, tail tag mode also needs to be enabled, so that the processor knows which port the MLD packet was received on. This is achieved by setting register 12 bit [1]. Port Mirroring Support The KSZ8794CNX supports "port mirror" as described below: "Receive Only" Mirror on a Port All the packets received on the port will be mirrored on the sniffer sort. For example, Port 1 is programmed to be "rx sniff," and Port 4 is programmed to be the "sniffer port." A packet, received on Port 1, is destined to Port 3 after the internal lookup. The KSZ8794CNX will forward the packet to both Port 3 and Port 4. KSZ8794CNX can optionally forward even "bad" received packets to Port 3. "Transmit Only" Mirror on a Port All the packets transmitted on the port will be mirrored on the sniffer port. For example, Port 1 is programmed to be "tx sniff," and Port 4 is programmed to be the "sniffer port." A packet, received on any of the ports, is destined to Port 1 after the internal look-up. The KSZ8794CNX will forward the packet to both Ports 1 and 4. "Receive and Transmit" Mirror on two Ports All the packets received on Port A AND transmitted on Port B will be mirrored on the sniffer port. To turn on the "AND" feature, set Register 5 bit 0 to 1. For example, Port 1 is programmed to be "rx sniff," Port 2 is programmed to be "tx sniff," and Port 4 is programmed to be the "Sniffer Port." A packet, received on Port 1, is destined to Port 3 after the internal look-up. The KSZ8794CNX will forward the packet to Port 4 only, since it does not meet the "AND" condition. A packet, received on Port 1, is destined to Port 2 after the internal look-up. The KSZ8794CNX will forward the packet to both Port 2 and Port 4, since it does meet the "AND" condition. Multiple ports can be selected to be "rx sniffed" or "tx sniffed." Any port can be selected to be the "sniffer port." All these per port features can be selected through the Port Control 1 Register. July 24, 2014 53 Revision 1.0 Micrel, Inc. KSZ8794CNX VLAN Support The KSZ8794CNX supports 128 active VLANs and 4096 possible VIDs specified in IEEE 802.1q. KSZ8794CNX provides a 128-entry VLAN table, which correspond to 4096 possible VIDs and converts to FID (7 bits) for address look-up max 128 active VLANs. If a non-tagged or null-VID-tagged packet is received, then the ingress port VID is used for look-up when 802.1q is enabled by the global register 5 control 3 bit [7]. In the VLAN mode, the look-up process starts from VLAN table look-up to determine whether the VID is valid. If the VID is not valid, the packet will then be dropped and its address will not be learned. If the VID is valid, FID is retrieved for further look-up by the static MAC table or dynamic MAC table. FID+DA is used to determine the destination port. The following table describes the different actions in different situations of DA and FID+DA in the static MAC table and dynamic MAC table after the VLAN table finish a look-up action. FID+SA is used for learning purposes. The following table also describes learning in the dynamic MAC table when the VLAN table has done a look-up in the static MAC table without a valid entry. Table 12. FID+DA Look-Up in the VLAN Mode DA found in Static MAC table USE FID Flag? FID Match? DA+FID found in Dynamic MAC table No Don't care Don't care No Broadcast to the membership ports defined in the VLAN table bits [11:7]. No Don't care Don't care Yes Send to the destination port defined in the dynamic MAC table bits [58:56]. Yes 0 Don't care Don't care Send to the destination port(s) defined in the static MAC table bits [52:48]. Yes 1 No No Broadcast to the membership ports defined in the VLAN table bits [11:7]. Yes 1 No Yes Send to the destination port defined in the dynamic MAC table bits [58:56]. Yes 1 Yes Don't care Send to the destination port(s) defined in the static MAC table bits [52:48]. Action Table 13. FID+SA Look-Up in the VLAN Mode SA+FID found in Dynamic MAC table Action No The SA+FID will be learned into the dynamic table. Yes Time stamp will be updated. Advanced VLAN features are also supported in KSZ8794CNX, such as "VLAN ingress filtering" and "discard non PVID" defined in bits [6:5] of the Port Control 2 Register. These features can be controlled on a port basis. July 24, 2014 54 Revision 1.0 Micrel, Inc. KSZ8794CNX Rate Limiting Support The KSZ8794CNX provides a fine resolution hardware rate limiting based on both bit per second (bps) and packet per second (pps). For bps, the rate step is 64kbps when the rate limit is less than 1Mbps rate for 100BT or 10BT, and 640kbps for 1000. The rate step is 1Mbps when the rate limit is more than 1Mbps rate for 100BT or 10BT, 10Mbps for 1000. For pps, the rate step is 128pps (besides the 1st one which is 64pps) when the rate limit is less than 1Mbps rate for 100BT or 10BT, and 1280pps (except the 1st one of 640pps) for 1000. The rate step is 1Mbps when the rate limit is more than 1.92Kpps rate for 100BT or 10BT, 19.2kpps for 1000. Refer to the table below. Note: the pps limiting is bounded by bps rate for each pps setting, the mapping is shown in the 2nd column of the table. Table 14. 10/100/1000Mbps Rate Selection for the Rate limit Item Bps bound of pps (egress only) Code Code PPS BPS PPS BPS PPS BPS 7'd0 7'd0 19.2Kpps 10Mbps 192Kpps 100Mbps 1.92Mpps 1000Mbps 7d'1 - 7d'10 7d'3,6, (8x)10 1.92Kpps * code 1Mbps * code 1.92Kpps * code 1Mbps * code 19.2Kpps * code 10Mbps * code 7d'11 - 7d'100 7d'11 - 7d'100 10Mbps 1.92Kpps * code 1Mbps * code 19.2Kpps * code 10Mbps * code 7d'101 7d'102 64pps 64Kbps 64pps 64Kbps 640pps 640Kbps 7d'102 7d'104 128pps 128Kbps 128pps 128Kbps 1280pps 1280Kbps 7d'103 7d'108 256pps 192Kbps 256pps 192Kbps 2560pps 1920Kbps 7d'104 7d'112 384pps 256Kbps 384pps 256Kbps 3840pps 2560Kbps 7d'105 7d'001 512pps 320Kbps 512pps 320Kbps 5120pps 3200Kbps 7d'106 7d'001 640pps 384Kbps 640pps 384Kbps 6400pps 3840Kbps 7d'107 7d'001 768pps 448Kbps 768pps 448Kbps 7680pps 4480Kbps 7d'108 7d'002 896pps 512Kbps 896pps 512Kbps 8960pps 5120Kbps 7d'109 7d'002 1024pps 576Kbps 1024pps 576Kbps 10240pps 5760Kbps 7d'110 7d'002 1152pps 640Kbps 1152pps 640Kbps 11520pps 6400Kbps 7d'111 7d'002 1280pps 704Kbps 1280pps 704Kbps 12800pps 7040Kbps 7d'112 7d'002 1408pps 768Kbps 1408pps 768Kbps 14080pps 7680Kbps 7d'113 7d'003 1536pps 832Kbps 1536pps 832Kbps 15360pps 8320Kbps 7d'114 7d'003 1664pps 896Kbps 1664pps 896Kbps 16640pps 8960Kbps 7d'115 7d'003 1792pps 969Kbps 1792pps 969Kbps 17920pps 9690Kbps 10Mbps 100Mbps 1000Mbps The rate limit is independently on the "receiving side" and on the "transmitting side" on a per port basis. For 10BASE-T, a rate setting above 10Mbps means the rate is not limited. On the receive side, the data receive rate for each priority at each port can be limited by setting up ingress rate control registers. On the transmit side, the data transmit rate for each queue at each port can be limited by setting up Egress Rate Control registers. For bps mode, the size of each frame has options to include minimum IFG (Inter Frame Gap) or preamble byte, in addition to the data field (from packet DA to FCS). July 24, 2014 55 Revision 1.0 Micrel, Inc. KSZ8794CNX Ingress Rate Limit For ingress rate limiting, KSZ8794CNX provides options to selectively choose frames from all types; multicast, broadcast, and flooded unicast frames via bits [3:2] of the Port Rate Limit Control Register. The KSZ8794CNX counts the data rate from those selected type of frames. Packets are dropped at the ingress port when the data rate exceeds the specified rate limit or the flow control takes effect without packet dropped when the ingress rate limit flow control is enabled by the Port Rate Limit Control Register bit [4]. The ingress rate limiting supports the port-based, 802.1p and DiffServ-based priorities, the Port-based priority is fixed priority 0-3 selection by bits [4:3] of the port Control 0 Register. The 802.1p and DiffServ-based priority can be mapped to priority 0-3 by default of the Register 128 and 129. In the ingress rate limit, set Register 135 Global Control 19 bit [3] to enable queue-based rate limit if using two-queue or four-queue mode. All related ingress ports and egress port should be split to two-queue or four-queue mode by the Port Control 9 and Control 0 Registers. The four-queue mode will use Q0-Q3 for priority 0-3 by bits [6:0] of the Port Register Ingress Limit Control 1-4. The two-queue mode will use Q0-Q1 for priority 0-1 by bits [6:0] of the port ingress limit control 1-2 Registers. The priority levels in the packets of the 802.1p and DiffServ can be programmed to priority 0-3 via the Register 128 and 129 for a remapping. Egress Rate Limit For egress rate limiting, the leaky bucket algorithm is applied to each output priority queue for shaping output traffic. Interframe gap is stretched on a per frame base to generate smooth, non-burst egress traffic. The throughput of each output priority queue is limited by the egress rate specified by the data rate selection table followed the egress rate limit control registers. If any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in the output queue and packet memory. After the memory of the queue or the port is used up, packet dropping or flow control will be triggered. As a result of congestion, the actual egress rate may be dominated by flow control/dropping at the ingress end, and may be therefore slightly less than the specified egress rate. The egress rate limiting supports the portbased, 802.1p and DiffServ-based priorities, the port-based priority is fixed priority 0-3 selection by bits [4:3] of the port Control 0 Register. The 802.1p and DiffServ-based priority can be mapped to priority 0-3 by default of the Register 128 and 129. In the egress rate limit, set Register 135 Global Control 19 bit [3] for queue-based rate limit to be enabled if using two-queue or four-queue mode. All related ingress ports and egress port should be split to two-queue or four-queue mode by the Port Control 9 and Control 0 Registers. The four-queue mode will use Q0-Q3 for priority 0-3 by bits [6:0] of the port Egress Limit Control 1-4 Register. The two-queue mode will use Q0-Q1 for priority 0-1 by bits [6:0] of the Port Egress Rate Limit Control 1-2 Register. The priority levels in the packets of the 802.1p and DiffServ can be programmed to priority 0-3 by Register 128 and 129 for a re-mapping. When the egress rate is limited, just use one queue per port for the egress port rate limit. The priority packets will be based upon the data rate selection table (see Tables 13 above). If the egress rate limit uses more than one queue per port for the egress port rate limit, then the highest priority packets will be based upon the data rate selection table for the rate limit exact number. Other lower priority packet rates will be limited based upon 8:4:2:1 (default) priority ratio, which is based on the highest priority rate. The transmit queue priority ratio is programmable. To reduce congestion, it is good practice to make sure the egress bandwidth exceeds the ingress bandwidth. Transmit Queue Ratio Programming In transmit queues 0-3 of the egress port, the default priority ratio is 8:4:2:1. The priority ratio can be programmed by the port control 10, 11, 12 and 13 registers. When the transmit rate exceeds the ratio limit in the transmit queue, the transmit rate will be limited by the transmit queue 0-3 ratio of the port control 10, 11, 12 and 13 registers. The highest priority queue will not be limited. Other lower priority queues will be limited based on the transmit queue ratio. July 24, 2014 56 Revision 1.0 Micrel, Inc. KSZ8794CNX VLAN and Address Filtering To prevent certain kinds of packets that could degrade the quality of the switch in applications such as voice over Internet protocol (VoIP), the switch provides the mechanism to filter and map the packets with the following MAC addresses and VLAN IDs. * Self-address packets * Unknown unicast packets * Unknown multicast packets * Unknown VID packets * Unknown IP multicast packets The packets sourced from switch itself can be filtered out by enabling self-address filtering via the Global Control 18 Register bit [6]. The self-address filtering will filter packets on the egress Port, self MAC address is assigned in the Register 104-109 MAC Address Registers 0-5. The unknown unicast packet filtering can be enabled by the Global Control Register 15 bit [5] and bits [4:0] specify the port map for forwarding. The unknown multicast packet filtering can be enabled by the Global Control Register 16 bit [5] and forwarding port map is specified in bits [4:0]. The unknown VID packet filtering can be enabled by Global Control Register 17 bit [5] with forwarding port map specified in bits [4:0]. The unknown IP multicast packet filtering can be enable by Global Control Register 18 bit [5] with forwarding port map specified in bits [4:0]. Those filtering above are global based. 802.1X Port-Based Security IEEE 802.1x is a port-based authentication protocol. EAPOL is the protocol normally used by the authentication process as uncontrolled port. By receiving and extracting special EAPOL frames, the microprocessor (CPU) can control whether the ingress and egress ports should forward packets or not. If a user port wants service from another port (authenticator), it must get approved by the authenticator. The KSZ8794 detect EAPOL frames by checking the destination address of the frame. The destination addresses should be either a multicast address as defined in IEEE 802.1x (01-80-C2-00-00-03) or an address used in the programmable reserved multicast address domain with offset -00-03. Once EAPOL frames are detected, the frames are forwarded to the CPU so it can send the frames to the authenticator server. Eventually, the CPU determines whether the requestor is qualified or not based on its MAC_Source addresses, and frames are either accepted or dropped. When the KSZ8794CNX is configured as an authenticator, the Ports of the switch must then be configured for authorization. In an authenticator-initiated port authorization, a client is powered up or plugs into the port, and the authenticator port sends an Extensible Authentication Protocol (EAP) PDU to the supplicant requesting the identification of the supplicant. At this point in the process, the port on the switch is connected from a physical standpoint; however, the 802.1X process has not authorized the port and no frames are passed from the port on the supplicant into the switching fabric. If the PC attached to the switch did not understand the EAP PDU that it was receiving from the switch, it would not be able to send an ID and the port would remain unauthorized. In this state, the port would never pass any user traffic and would be as good as disabled. If the client PC is running the 802.1X EAP, it would respond to the request with its configured ID. (This could be a user name/password combination or a certificate.) After the switch, the authenticator receives the ID from the PC (the supplicant). The KSZ8794CNX then passes the ID information to an authentication server (RADIUS server) that can verify the identification information. The RADIUS server responds to the switch with either a success or failure message. If the response is a success, the port will be authorized and user traffic will be allowed to pass through the port like any switch port connected to an access device. If the response is a failure, the port will remain unauthorized and, therefore, unused. If there is no response from the server, then the port will also remain unauthorized and will not pass any traffic. July 24, 2014 57 Revision 1.0 Micrel, Inc. KSZ8794CNX Authentication Register and Programming Model The Port Authentication Control Registers define the control of port based authentication. The per-port authentication can be programmed in these registers. KSZ8794CNX provides three modes for implementing the IEEE 802.1x feature. Each mode can be selected by setting the appropriate bits in the Port Authentication Registers. When mode control bits AUTHENCIATION_MODE = 00 (pass mode), forced-authorization is enabled and a port is always authorized and does not require any messages from either the supplicant or the authentication server. This is typically the case when connecting to another switch, a router, or a server, and also when connecting to clients that do not support 802.1X. When ACL is enabled, all the packets are passed if they miss ACL rules, otherwise, ACL actions apply. The Block mode (when AUTHENCIATION_MODE = 01) is the standard port based authentication mode. A port in this mode sends EAP packets to the supplicant and will not become authorized unless it receives a positive response from the authentication server. Traffic is blocked before authentication to all of the incoming packets, upon authentication, software will switch to pass mode to allow all the incoming packets. In this mode, the source address of incoming packets is not checked. Including the EAP address, the forwarding map of all reserved multicast addresses need to be configured to be allowed to be forwarded before and after authentication in lookup table. When ACL is enabled, packets except ACL hit are blocked. The third mode is called Trap mode (when AUTHENTICATION_MODE = 11'b). In this mode, all the packets are sent to CPU port. If ACL is enabled, the missed packets would be forwarded to the CPU rather than dropped. All these per port features can be selected through the Port Control 5 Register, bit [2] is used to enable ACL, bits [1:0] are for the modes selected. ACL Filtering ACL (Access Control List) can be created to perform the protocol-independent layer 2 MAC, layer 3 IP or layer 4 TCP/UDP ACL filtering that filters incoming Ethernet packets based on the ACL rule table. The feature allows the switch to filter customer traffic based on the source MAC address in the Ethernet header, the IP address in the IP header, and the port number and protocol in the TCP header. This function can be performed through MAC table and ACL Rule table. Besides multicast filtering handled using entries in the static table, ACL can be configured for all routed network protocols to filter the packets of those protocols as the packets pass through the switch. Access lists can prevent certain traffic from entering or exiting a network. Access Control Lists KSZ8794CNX offers a rule-based access control list (ACL Rule table). ACL Rule table is an ordered list of access control entries. Each entry specifies certain rules (a set of matching conditions and action rules) to permit or deny the packet access to the switch fabric. The meaning of `permit' or `deny' depends on the context in which the ACL is used. When a packet is received on an interface, the switch compares the fields in the packet against any applied ACLs to verify that the packet has the permissions required to be forwarded, based on the conditions specified in the lists. The filter tests the packets against the ACL entries one-by-one. Usually the first match determines whether the router accepts or rejects packets. However, it is allowed to cascade the rules to form more robust and/or stringent requirements for incoming packets. ACLs allow switch filter ingress traffic based on the source, Layer 2 header destination MAC address and Ethernet type, source, destination IP address in Layer 3 header, port number, and protocol in the Layer 4 header of a packet. Each list consists of 3 parts: the Matching, the Action, and the Processing field. The Matching field specifies the rules that each packet matches against and the Action field specifies the action taken if the test succeeds against the rules. The figure below shows the format of ACL and a description of the individual fields. July 24, 2014 58 Revision 1.0 Micrel, Inc. KSZ8794CNX Figure 11. ACL Format July 24, 2014 59 Revision 1.0 Micrel, Inc. KSZ8794CNX Matching Field MD [1:0]: MODE- there are three modes of operation defined in ACL. MD = 00 disables the current rule list. No action will be taken. MD = 01 is qualification rules for Layer 2 MAC header filtering. MD = 10 is used for Layer 3 IP address filtering. MD = 11 performs Layer 4 TCP port number/protocol filtering. ENB [1:0]: ENABLE - Enables different rules in the current list. When MD = 01, If ENB = 00, the 11 bits of the aggregated bit field from PM, P, RPE, RP, MM in the action field specify a count value for packets matching the MAC address and type in the matching fields. The count unit is defined in MSB of the forward bit field; while = 0, sec will be used and while = 1, msec will be used. The second MSB of the forwarded bit determines the algorithm used to generate an interrupt when the counter terminates. When = 0, an 11-bit counter is loaded with the count value from the ACL and starts counting down every unit of time. An interrupt is generated when it expires (i.e., the next qualified packet has not been received within the period specified by the value). When = 1, the counter is incremented on every matched packet received and an interrupt is generated when the terminal count reaches the count value in the ACL. The count resets thereafter. If ENB = 01, the MAC address bit field is used for testing; If ENB = 10, the MAC type bit field is used for testing; If ENB = 11, both the MAC address and type are tested against these bit fields in the list. When MD = 10, If ENB = 01, the IP address and mask or IP protocol is enabled to be tested accordingly. If ENB = 10, the source and destination addresses are compared. The drop/forward decision is based on the EQ bit setting. When MD = 11, If ENB = 00, protocol comparison is enabled. If ENB = 01, TCP address comparison is selected. If ENB = 10, UDP address comparison is selected. If ENB = 11, the sequence number of the TCP is compared. S/D: Source or destination selection S/D = 0, the destination address/port is compared; S/D = 1, the source is chosen. E/Q: comparison algorithm: E/Q = 0, match if they are not equal; E/Q = 1, match if they are equal. MAC Address [47:0]: MAC source or destination address TYPE [15:0]: MAC Ether Type IP Address [31:0]: IP source or destination address IP Mask [31:0]: IP address mask for group address filtering MAX Port [15:0], MIN Port [15:0] (Sequence Number [31:0]): The range of TCP Port number or sequence number matching. July 24, 2014 60 Revision 1.0 Micrel, Inc. KSZ8794CNX PC [1:0]: Port Comparison PC = 00, the comparison is disabled. PC = 01, matches either one of MAX or MIN. PC = 10, match if the Port number is in the range of MAX to MIN. PC = 11, match if the Port number is out of the range. PRO [7:0]: IP Protocol to be matched FME: Flag Match Enable FME = 0, disable TCP FLAG matching. FME = 1, enable TCP FLAG matching FLAG [5:0]: TCP Flag to be matched. Action Field PM [1:0]: Priority Mode PM = 00, no priority is selected, the priority is determined by the QoS/Classification is used. PM = 01, the priority in P bit field is used if it is greater than QoS result. PM = 10, the priority in P bit field is used if it is smaller than QoS result. PM = 11, the P bit field will replace the priority determined by QoS. P [2:0]: Priority. RPE: Remark Priority Enable RPE = 0, no remarking is necessary. RPE = 1, the VLAN priority bits in the tagged packets are replaced by RP bit field in the list. RP [2:0]: Remarked Priority. MM [1:0]: Map Mode MM = 00, no forwarding remapping is necessary. MM = 01, the forwarding map in FORWORD is OR'ed with the Forwarding map from the look-up table. MM = 10, the forwarding map in FORWORD is AND'ed with the Forwarding map from the look-up table. MM = 11, the forwarding map in FORWORD replaces the Forwarding map from the look-up table. FORWARD Bits [4:0]: Forwarding Port(s) - Each bit indicates the forwarding decision of one Port. Processing Field FRN Bits [3:0]: First Rule Number - Assign which entry with its Action Field in 16 entries is used in the rule set. For the rule set, see description below. RULESET Bits [15:0]: Rule Set - Group of rules to be qualified, there are 16 entries rule can be assigned to a rule set per port by the two rule-set registers. The Rule table allows the rules to be cascaded. There are 16 entries in the RTB. Each entry can be a rule on its own, or can be cascaded with other entries to form a rule set. The test result of incoming packets against rule set will be the AND'ed result of all the test result of incoming packets against the rules included in this rule set. The action of the rule set will be the action of the first rule specified in FRN field. The rule with higher priority will have lower index number. Or rule 0 is the highest priority rule and rule 15 is the lowest priority. ACL rule table entry is disabled when mode bits are set to 2'b00. A rule set (RULESET) is used to select the match results of different rules against incoming packets. These selected match results will be AND'ed to determine whether the frame matches or not. The conditions of different rule sets having the same action will be OR'ed for comparison with frame fields, and the CPU will program the same action to those rule sets that are to be OR'ed together. For matched rule sets, different rule sets having different actions will be arbitrated or July 24, 2014 61 Revision 1.0 Micrel, Inc. KSZ8794CNX chosen based upon the first rule number (FRN) of each rule set. The rule table will be set up with the high priority rule at the top of the table or with the smaller index. Regardless whether the matched rule sets have the same or different action, the hardware will always compare the first rule number of different rule sets to determine the final rule set and action. DOS Attack Prevention via ACL The ACL can provide certain detection/protection of the following DoS (Denial of Service) attack types based on rule setting, which can be programmed to drop or not to drop each type of DoS packet respectively. Example 1: When MD = `10', ENABLE = `10', setting EQ bit to `1' can determine the drop or forward packets with identical source and destination IP addresses in IPv4/IPv6. Example 2: When MD = `11', ENABLE = `01/10', setting EQ bit to `1' can determine the drop or forward packets with identical source and destination TCP/UDP Ports in IPv4/IPv6. Example 3: When MD = `11', ENABLE = `11', Sequence Number = `0', FME = `1', FMSK = `00101001', FLAG = `xx1x1xx1', Setting the EQ bit to `1' will drop/forward the all packets with a TCP sequence number equal to `0', and flag bit URG = `1', PSH = `1' and FIN = `1'. Example 4: When MD = `11', ENABLE = `01', MAX Port = `1024', MIN Port = `0', FME = `1', FMSK = `00010010', FLAG = `xxx0xx1x', Setting the EQ bit to `1' will drop/forward the all packets with a TCP Port number 1024, and flag bit URB = `0', SYN = `1'. ACL related registers are Register 110 (0x6E), Register 111 (0x6F), and the ACL rule tables. July 24, 2014 62 Revision 1.0 Micrel, Inc. KSZ8794CNX Device Registers Mapping The KSZ8794CLX device has a rich set of registers available to manage the functionality of the device. Access to these registers is via the MIIM or SPI interfaces. The Figure below provides a global picture of accessibility via the various interfaces and addressing ranges from the perspective of each interface. Figure 12. Interface and Register Mapping The registers within the linear 0x00-0xFF address space are all accessible via the SPI interface by a CPU attached to that bus. The mapping of the various functions within that linear address space is summarized in table below. Table 15. Mapping of Functional Areas within the Address Space Register Locations 0x00 - 0xFF 0x6E - 0x6F 0x70 - 0x78 0xA0 0x17 - 0x4F July 24, 2014 Device Area Description Switch Control and Configuration Registers which control the overall functionality of the Switch, MAC, and PHYs Indirect Control Registers Registers used to indirectly address and access distinct areas within the device. - MIB (Management Information Base) Counters - Static MAC Address Table - Dynamic MAC Address Table - VLAN Table - PME Indirect Register - ACL Indirect Register - EEE Indirect Register Indirect Access Registers Registers used to indirectly address and access four distinct areas within the device. - MIB (Management Information Base) Counters - Static MAC Address Table - Dynamic MAC Address Table - VLAN Table Indirect Byte Access Registers This indirect byte register is used to access: - PME Indirect Registers - ACL Indirect Registers - EEE Indirect Registers PHY1 to PHY4 MIIM registers mapping to those port registers address range The same PHY registers as specified in IEEE 802.3 specification. 63 Revision 1.0 Micrel, Inc. KSZ8794CNX Direct Register Description Address Contents 0x00-0x01 Family ID, Chip ID, Revision ID, and start switch Registers 0x02-0x0D Global Control Registers 0 - 11 0x0E-0x0F Global Power Down Management Control Registers 0x10-0x14 Port 1 Control Registers 0 - 4 0x15 Port 1 Authentication Control Register 0x16-0x18 Port 1 Reserved (Factory Test Registers) 0x19-0x1F Port 1 Control/Status Registers 0x20-0x24 Port 2 Control Registers 0 - 4 0x25 Port 2 Authentication Control Register 0x26-0x28 Port 2 Reserved (Factory Test Registers) 0x29-0x2F Port 2 Control/Status Registers 0x30-0x34 Port 3 Control Registers 0 - 4 0x35 Port 3 Authentication Control Register 0x36-0x38 Port 3 Reserved (Factory Test Registers) 0x39-0x3F Port 3 Control/Status Registers 0x40-0x44 Port 4 Control Registers 0 - 4 0x45 Port 4 Authentication Control Register 0x46-0x48 Port 4 Reserved (Factory Test Registers) 0x49-0x4F Port 4 Control/Status Registers 0x50-0x54 Port 4 Control Registers 0 - 4 0x56-0x58 Port 4 Reserved (Factory Test Registers) 0x59-0x5F Port 4 Control/Status Registers 0x60-0x67 Reserved (Factory Testing Registers) 0x68-0x6D MAC Address Registers 0x6E-0x6F Indirect Access Control Registers 0x70-0x78 Indirect Data Registers 0x79-0x7B Reserved (Factory Testing Registers) 0x7C-0x7D Global Interrupt and Mask Registers 0x7E-0x7F Reserved (Factory Testing Registers) 0x80-0x87 Global Control Registers 12 - 19 0x88 Switch Self Test Control Register 0x89-0x8F QM Global Control Registers 0x90-0x9F Global TOS Priority Control Registers 0 - 15 0xA0 Global Indirect Byte Register 0xA0-0xAF Reserved (Factory Testing Registers) 0xB0-0xBE Port 1 Control Registers 0xBF Reserved (Factory Testing Register): Transmit Queue Remap Base Register 0xC0-0xCE Port 2 Control Registers July 24, 2014 64 Revision 1.0 Micrel, Inc. KSZ8794CNX Address Contents 0xCF Reserved (Factory Testing Register) 0xD0-0xDE Port 3 Control Registers 0xDF Reserved (Factory Testing Register) 0xE0-0xEE Port 4 Control Registers 0xEF Reserved (Factory Testing Register) 0xF0-0xFE Port 4 Control Registers 0xFF Reserved (Factory Testing Register) July 24, 2014 65 Revision 1.0 Micrel, Inc. KSZ8794CNX Global Registers Address Name Description Mode Default Chip family. RO 0x87 RO 0x6 RO 0x0 Register 0 (0x00): Chip ID0 7-0 Family ID Register 1 (0x01): Chip ID1 / Start Switch 7-4 Chip ID 3-1 Revision ID 0 Start Switch 0x6 = 8794 1 = Start the switch function of the chip 0 = Stop the switch function of the chip R/W 1 Register 2 (0x02): Global Control 0 7 6 New back off enable Global soft reset enable New Back-off algorithm designed for UNH 1 = Enable 0 = Disable Global Software Reset 1 = Enable to reset all FSM and data path (not configuration) 0 = Disable reset R/W 0 RO 0 R/W (SC) 0 R/W (SC) 0 Note: This reset will stop to receive packets if it is being in the traffic. All registers keep their configuration values. 5 Flush dynamic MAC table Flush the entire dynamic MAC table for RSTP. This bit is self-clear (SC). 1 = Trigger the flush dynamic MAC table operation. 0 = Normal operation Note: All the entries associated with a Port that has its learning capability being turned off (Learning Disable) will be flushed. If you want to flush the entire Table, all Ports learning capability must be turned off. Flush the matched entries in static MAC table for RSTP 1 = Trigger the flush static MAC table operation. 0 = Normal operation 4 Flush static MAC table Note: The matched entry is defined as the entry whose Forwarding Ports field contains a single Port and MAC address with unicast. This Port, in turn, has its learning capability being turned off (Learning Disable). Per Port, multiple entries can be qualified as matched entries. 3 Reserved N/A Don't change. RO 1 2 Reserved N/A Don't change. RO 1 UNH Mode 1 = The switch will drop packets with 0x8808 in the T/L filed, or DA = 01-80-C2-00-00-01. 0 = The switch will drop packets qualified as "flow control" packets. R/W 0 R/W 0 1 0 Link Change Age 1 = Link change from "link" to "no link" will cause fast aging (<800s) to age address table faster. After an age cycle is complete, the age logic will return to normal (300 75 seconds). Note: If any port is unplugged, all addresses will be automatically aged out. July 24, 2014 66 Revision 1.0 Micrel, Inc. KSZ8794CNX Global Registers (Continued) Address Name Description Mode Default Register 3 (0x03): Global Control 1 7 Reserved N/A Don't change. RO 0 6 2K Byte packet support 1 = Enable 2K Byte packet support. 0 = Disable 2K Byte packet support. R/W 0 5 IEEE 802.3x Transmit Flow Control Disable 0 = Enables transmit flow control based on AN result. 1 = Will not enable transmit flow control regardless of the AN result. R/W 4 IEEE 802.3x Receive Flow Control Disable 0 = Enables receive flow control based on AN result. 1 = Will not enable receive flow control regardless of the AN result. 0 R/W 0 Note: Bit [5] and bit [4] default values are controlled by the same pin, but they can be programmed independently. 3 Frame Length Field Check 1 = Check frame length field in the IEEE packets. If the actual length does not match, the packet will be dropped (for L/T <1500) . R/W 2 Aging Enable 1 = Enable Aging function in the chip. 0 = Disable Aging function. R/W 1 Fast age Enable 1 = Turn on Fast Aging (800s). R/W 0 Aggressive Back Off Enable 1 = Enable more aggressive back-off algorithm in half duplex mode to enhance performance. This is not in the IEEE standard. R/W July 24, 2014 67 0 1 0 0 Revision 1.0 Micrel, Inc. KSZ8794CNX Global Registers (Continued) Address Name Description Mode Default R/W 1 R/W 1 Register 4 (0x04): Global Control 2 This feature is used for port VLAN (described in Port Control 1 Register). 7 Unicast Port-VLAN Mismatch Discard 1 = All packets cannot cross VLAN boundary. 0 = Unicast packets (excluding unknown/ multicast/broadcast) can cross VLAN boundary. Note: When mirroring is enabled, the single-destination packets will be dropped if it's mirrored to another port. 6 Multicast Storm Protection Disable 1 = "Broadcast Storm Protection" does not include multicast packets. Only DA = FFFFFFFFFFFF packets will be regulated. 0 = "Broadcast Storm Protection" includes DA = FFFFFFFFFFFF and DA[40] = 1 packet. 5 Back Pressure Mode 1 = Carrier sense based backpressure is selected. 0 = Collision based backpressure is selected. R/W 1 4 Flow Control and Back Pressure fair Mode 1 = Fair mode is selected. In this mode, if a flow control port and a non-flow control port talk to the same destination port, then packets from the non-flow control port may be dropped. This is to prevent the flow control port from being flow controlled for an extended period of time. 0 = In this mode, if a flow control port and a non-flow control port talk to the same destination port, the flow control port will be flow controlled. This may not be "fair" to the flow control port. R/W 1 3 No Excessive Collision Drop 1 = The switch will not drop packets when 16 or more collisions occur. 0 = The switch will drop packets when 16 or more collisions occur. R/W 2 Reserved N/A Don't change. RO 1 Legal Maximum Packet Size Check Disable 1 = Enables acceptance of packet sizes up to 1536 bytes (inclusive). 0 = 1522 bytes for tagged packets (not including packets with STPID from CPU to Ports 1-4), 1518 bytes for untagged packets. Any packets larger than the specified value will be dropped. R/W 0 Reserved N/A RO July 24, 2014 68 0 0 0 0 Revision 1.0 Micrel, Inc. KSZ8794CNX Global Registers (Continued) Address Name Description Mode Default Register 5 (0x05): Global Control 3 7 802.1q VLAN Enable 1 = 802.1q VLAN mode is turned on. VLAN table needs to be set up before the operation. 0 = 802.1q VLAN is disabled. R/W 0 6 IGMP Snoop Enable on Switch Port 4 SW4RGMII/MII/RMII Interface 1 = IGMP Snoop enabled. All the IGMP packets will be forwarded to the Switch Port 4 RGMII/MII/RMII I/F. 0 = IGMP Snoop disabled. R/W 0 Reserved N/A Don't change. RO 00000 R/W 0 0 5-1 0 Sniff Mode Select 1 = Enables Rx AND Tx sniff (both source port and destination port need to match). 0 = Enables Rx OR Tx sniff (Either source port or destination port need to match). Note: Default is used to implement Rx only sniff. Register 6 (0x06): Global Control 4 7 Switch SW4-MII/RMII Back Pressure Enable 1 = Enable half-duplex back pressure on the switch MII/RMII interface. 0 = Disable back pressure on the switch MII interface. R/W 6 Switch SW4-MII/RMII Half-Duplex Mode 1 = Enable MII/RMII interface half-duplex mode. 0 = Enable MII/RMII interface full-duplex mode. R/W 5 Switch SW4-MII/RMII Flow Control Enable 1 = Enable full-duplex flow control on the switch MII/RMII interface. 0 = Disable full-duplex flow control on the switch MII/RMII interface. R/W 4 Switch SW4-MII/RMII Speed 1 = The switch SW4-MII/RMII is in 10Mbps mode. 0 = The switch SW4-MII/RMII is in 100Mbps mode. R/W 3 Null VID Replacement 1 = Replace null VID with Port VID (12 bits). 0 = No replacement for null VID. R/W 0 Broadcast Storm Protection Rate Bit[10:8] This register, along with the next register, determines how many "64 byte blocks" of packet data are allowed on an input Port in a preset period. The period is 50ms for 100BT or 500ms for 10BT. The default is 1%. R/W 000 This register, along with the previous register, determines how many "64-byte blocks" of packet data are allowed on an input Port in a preset period. The period is 50ms for 100BT or 500ms for 10BT. The default is 1%. R/W 0x4A(3) 2-0 0 0 0 Register 7 (0x07): Global Control 5 7-0 Broadcast Storm Protection Rate Bits [7:0] Note: 3. 148,800 frames/sec x 50ms/interval x 1% = 74 frames/interval (approx.) = 0x4A. July 24, 2014 69 Revision 1.0 Micrel, Inc. KSZ8794CNX Global Registers (Continued) Address Name Description Mode Default R/W (SC) 0 Register 8 (0x08): Global Control 6 MIB Control 7 Flush Counter 1 = All the MIB counter of enabled Port(s) will be reset to 0. This bit is self-cleared after the operation finishes. 0 = No reset of the MIB counter. 6 Freeze Counter 1 = Enabled Port(s) will stop counting. 0 = Enabled Port(s) will not stop counted. R/W 0 5 Reserved N/A Don't change. RO 0 Control Enable 1 = Enable flush and freeze for each Port. Bit [4] is for Port 4 Flush + Freeze. Bit [3] is reserved. Bit [2] is for Port 3 Flush + Freeze. Bit [1] is for Port 2 Flush + Freeze. Bit [0] is for Port 1 Flush + Freeze. 0 = Disable flush and freeze. R/W 0 N/A Don't change. RO 0x40 RO 0x00 4-0 Register 9 (0x09): Global Control 7 7-0 Factory Testing Register 10 (0x0A): Global Control 8 7-0 Factory Testing July 24, 2014 N/A Don't change. 70 Revision 1.0 Micrel, Inc. KSZ8794CNX Global Registers (Continued) Address Name Description Mode Default RO 0 R/W 0 R/W 00 Register 11 (0x0B): Global Control 9 7 6 Reversed Port 4 SW4- RMII Reference Clock Edge Select N/A Don't change. Select the data sampling edge of the SW4- RMII reference clock: 1 = Data sampling on the negative edge of REFCLK. 0 = Data sampling on the positive edge of REFCLK (default). Programmable LED output to indicate Port's activity/status using 2 bits of the control register. LED is ON (active) when the output is LOW; the LED is OFF (inactive) when the output is HIGH. 5-4 LED Mode Control Bits [5:4] 00 01 10 11 LEDx_1 Speed ACT Duplex Duplex LEDx_0 Link/ACT Link Link/ACT Link LINK = LED ON; ACT = LED Blink; LINK/ACT = LED On/Blink. Speed = LED ON (100BT); LED OFF (10BT); LED Blink (1000BT reserved). Duplex = LED ON (Full duplex); LED OFF (Half duplex). 3 Reserved N/A Don't change. RO 0 2 Reserved N/A Don't change. RO 0 R/W 0 R/W 0 1 = Enable REFCLKO pin clock output 0 = Disable REFCLKO pin clock output. 1 REFCLKO Enable Strap-in option: LED2_0 PU = REFCLK_O (25MHz) is enabled. (Default) PD = REFCLK_O is disabled Note: This is an additional clock. This clock can save an oscillator if system need this clock source. If the system doesn't need this 25MHz clock source that should be disabled. 0 SPI Read Sampling Clock Edge Select July 24, 2014 Select the SPI clock edge for sampling SPI read data. 1 = Trigger on the rising edge of SPI clock (for higher speed SPI) 0 = Trigger on the falling edge of SPI clock. 71 Revision 1.0 Micrel, Inc. KSZ8794CNX Global Registers (Continued) Address Name Description Mode Default Register 12 (0x0C): Global Control 10 7-6 Reserved Reserved RO 0 5-2 Reserved N/A Don't change. RO 0001 1 Tail Tag Enable Tail Tag feature is applied for Port 4 only. 1 = Insert 1 Byte of data right before FCS. 0 = Do not insert. R/W 0 0 Pass Flow Control Packet 1 = Switch will not filter 802.1x "flow control" packets. 0 = Switch will filter 802.1x "flow control" packets. R/W 0 RO 00000000 Register 13 (0x0D): Global Control 11 7-0 Factory Testing N/A Don't change. Register 14 (0x0E): Power Down Management Control 1 7-6 5 Reserved N/A Don't change. RO 00 PLL Power Down Pll Power Down Enable: 1 = Enable 0 = Disable R/W 0 Power Management Mode Select Power Management Mode : 00 = Normal mode (D0) 01 = Energy Detection mode (D2) 10 = Soft Power Down mode (D3) 11 = Reserved R/W 00 Reserved N/A Don't change. RO 000 R/W 01010000 Note: It occurs in the Energy Detect mode (EDPD mode) 4-3 2-0 Register 15 (0x0F): Power Down Management Control 2 7-0 Go_Sleep_Time [7:0] July 24, 2014 When the Energy Detect mode is on, this value is used to control the minimum period that the no energy event has to be detected consecutively before the device enters the low power state. The unit is 20ms. The default of go_sleep time is 1.6 seconds (80Dec x 20ms). 72 Revision 1.0 Micrel, Inc. KSZ8794CNX Port Registers The following registers are used to enable features that are assigned on a per port basis. The register bit assignments are the same for all Ports, but the address for each Port is different, as indicated. Register 16 (0x10): Port 1 Control 0 Register 32 (0x20): Port 2 Control 0 Register 48 (0x30): Port 3 Control 0 Register 64 (0x40): Reserved Register 80 (0x50): Port 4 Control 0 Address Name Description 7 Broadcast Storm Protection Enable 6 5 4-3 Mode Default 1 = Enable broadcast storm protection for ingress packets on the Port. 0 = Disable broadcast storm protection. R/W 0 DiffServ Priority Classification Enable 1 = Enable DiffServ priority classification for ingress packets on Port. 0 = Disable DiffServ function. R/W 0 802.1p Priority Classification Enable 1 = Enable 802.1p priority classification for ingress packets on Port. 0 = Disable 802.1p priority classification for ingress packets on Port. R/W 0 R/W 00 Tag insertion 1 = When packets are output on the Port, the switch will add 802.1q tags to packets without 802.1q tags when received. The switch will not add tags to packets already tagged. The tag inserted is the ingress Port's "Port VID." 0 = Disable tag insertion. R/W 0 Tag Removal 1 = When packets are output on the Port, the switch will remove 802.1q tags from packets with 802.1q tags when received. The switch will not modify packets received without tags. 0 = Disable tag removal. R/W 0 Port-Based Priority Classification Enable 00 = Ingress packets on Port will be classified as priority 0 queue if "Diffserv" or "802.1p" classification is not enabled or fails to classify. 01 = Ingress packets on Port will be classified as priority 1 queue if "Diffserv" or "802.1p" classification is not enabled or fails to classify. 10 = Ingress packets on Port will be classified as priority 2 queue if "Diffserv" or "802.1p" classification is not enabled or fails to classify. 11 = Ingress packets on Port will be classified as priority 3 queue if "Diffserv" or "802.1p" classification is not enabled or fails to classify. Note: "DiffServ", "802.1p" and Port priority can be enabled at the same time. The OR'ed result of 802.1p and DSCP overwrites the Port priority. 2 1 July 24, 2014 73 Revision 1.0 Micrel, Inc. KSZ8794CNX Port Registers (Continued) Address Name Description Mode Default R/W 0 Mode Default This bit [0] in Registers16/32/48/64/80 should be in combination with Registers177/193/209/225/241 bit [1] for Port 1-5. This will select the split of 1, 2 and 4 queues: 0 Two Queues Split Enable For Port 1, Register 177 bit [1], Register 16 bit [0]: 11 = Reserved 10 = The Port output queue is split into four priority queues or if map 802.1p to priority 0-3 mode. 01 = The Port output queue is split into two priority queues or if map 802.1p to priority 0-3 mode. 00 = Single output queue on the Port. There is no priority differentiation even though packets are classified into high or low priority. Register 17 (0x11): Port 1 Control 1 Register 33 (0x21): Port 2 Control 1 Register 49 (0x31): Port 3 Control 1 Register 65 (0x41): Reserved Register 81 (0x51): Port 4 Control 1 Address Name Description 7 Sniffer Port 1 = Port is designated as Sniffer port and will transmit packets that are monitored. 0 = Port is a normal port. R/W 0 6 Receive Sniff 1 = All the packets received on the port will be marked as "monitored packets" and forwarded to the designated "Sniffer port." 0 = No receive monitoring. R/W 0 Transmit Sniff 1 = All the packets transmitted on the port will be marked as "monitored packets" and forwarded to the designated "Sniffer port." 0 = No transmit monitoring. R/W 0 Port VLAN Membership Defines the port's Port VLAN membership. Bit [4] stands for Port 4, Bit [3] Reserved, Bit [2] stands for Port 3, Bit [1] stands for Port 2, Bit [0] stands for Port 1. The Port can only communicate within the membership. A `1' includes a port in the membership, a `0' excludes a port in the membership. R/W 0x1f 5 4-0 July 24, 2014 74 Revision 1.0 Micrel, Inc. KSZ8794CNX Port Registers (Continued) Register 18 (0x12): Port 1 Control 2 Register 34 (0x22): Port 2 Control 2 Register 50 (0x32): Port 3 Control 2 Register 66 (0x42): Reserved Register 82 (0x52): Port 4 Control 2 Address Name Description Mode Default User Priority Ceiling 1 = If packet `s "user priority field" is greater than the "user priority field" in the port default tag register, replace the packet's "user priority field" with the "user priority field" in the port default tag Register Control 3. 0 = No replace packet's priority filed with Port default tag priority filed of the Port Control 3 Register bits [7:5]. 7 R/W 0 6 Ingress VLAN Filtering. 1 = The switch will discard packets whose VID port membership in VLAN table bits[11:7] does not include the ingress port. 0 = No ingress VLAN filtering. R/W 0 5 Discard Non-PVID packets 1 = The switch will discard packets whose VID does not match ingress port default VID. 0 = No packets will be discarded. R/W 0 4 Force Flow Control 1 = Enables Rx and Tx flow control on the port, regardless of the AN result. 0 = Flow control is enabled based on the AN result (Default) R/W 3 Back Pressure Enable 1 = Enable port half-duplex back pressure. 0 = Disable port half-duplex back pressure. R/W 0 2 Transmit Enable 1 = Enable packet transmission on the port. 0 = Disable packet transmission on the port. R/W 1 1 Receive Enable 1 = Enable packet reception on the port. 0 = Disable packet reception on the port. R/W 1 0 Learning Disable 1 = Disable switch address learning capability. 0 = Enable switch address learning. R/W 0 Mode Default R/W 0 0 Note: Bits [2:0] are used for spanning tree support. See "Spanning Tree Support" section. Register 19 (0x13): Port 1 Control 3 Register 35 (0x23): Port 2 Control 3 Register 51 (0x33): Port 3 Control 3 Register 67 (0x43): Reserved Register 83 (0x53): Port 4 Control 3 Address 7-0 Name Description Default Tag [15:8] Port's default tag, containing: 7-5: User priority bits 4: CFI bit 3-0: VID[11:8] July 24, 2014 75 Revision 1.0 Micrel, Inc. KSZ8794CNX Port Registers (Continued) Register 20 (0x14): Port 1 Control 4 Register 36 (0x24): Port 2 Control 4 Register 52 (0x34): Port 3 Control 4 Register 68 (0x44): Reserved Register 84 (0x54): Port 4 Control 4 Address 7-0 Name Description Default Tag [7:0] Default Port 1's tag, containing: 7-0: VID[7:0] Mode Default R/W 1 Note: Registers 19 and 20 (and those corresponding to other Ports) serve two purposes: (1) Associated with the ingress untagged packets, and used for egress tagging; (2) Default VID for the ingress untagged or null-VID-tagged packets, and used for address look up. Register 21 (0x15): Port 1 Control 5 Register 37 (0x25): Port 2 Control 5 Register 53 (0x35): Port 3 Control 5 Register 69 (0x45): Reserved Register 85 (0x55): Port 4 Control 5 Address 7-3 2 Name Description Mode Default Reserved N/A Don't change. RO 00000 ACL Enable 1 = Enable ACL 0 = Disable ACL R/W 0 R/W 00 These bits control port-based authentication: 1-0 AUTHENTICATION_MODE 00, 10 = Authentication disable, all traffic is allowed (forced-authorized), if ACL is enabled, pass all traffic if ACL missed 01 = Authentication enabled, all traffic is blocked, if ACL is enabled, traffic is blocked if ACL missed 11 = Authentication enabled, all traffic is trapped to CPU Port, if ACL is enabled, traffic is trapped to port 5 CPU Port only if ACL missed. Register 22 (0x16): Reserved Register 38 (0x26): Reserved Register 54 (0x36): Reserved Register 70 (0x46): Reserved July 24, 2014 76 Revision 1.0 Micrel, Inc. KSZ8794CNX Port Registers (Continued) Register 86 (0x56): Port 4 Interface Control 6 Address Name Description Mode Default R/W 1 R/W 1 RO 1 R/W 0 R/W 1 Port 4 SW4-RMII Mode Select 1 = RMII uses internal clock (clock mode) 0 = RMII uses external clock (normal mode) 7 RMII_CLK_SEL Strap-in option for Port 4: LED2_1 PU = SW4-RMII is in the clock mode (Default) PD = SW4-RMII is in the normal mode. Note: This pin has an internal pull-up 1 = 1Gbps is chosen for Port 4 in RGMII mode. 0 = 10/100Mbps is chosen for Port 4 in RGMII mode. Strap-in option: LED1_0 6 Is_1Gbps PU = 1Gbps in SW4- RGMII mode (Default) PD = 10/100Mbps in SW4-RGMII mode Note: This pin has an internal pull-up. Use bit [4] of the Register 6, Global Control 4 to set for 10 or 100 speed in 10/100Mbps mode. 5 Reserved N/A Don't change. Enable Ingress RGMII-ID Mode 4 RGMII Internal Delay (ID) Ingress Enable 1 = Ingress RGMII-ID enabled. Min. 1.5ns delay is added to ingress clock input 0 = No delay is added, only clock to data skew applied. Note: The egress delay of the connection partner should be set to opposite value to match this ingress delay or no delay. Enable Egress RGMII-ID Mode 3 RGMII Internal Delay (ID) Egress Enable 1 = Egress RGMII-ID enabled. Min. 1.5 ns delay is added to egress clock output 0 = No delay is added, only clock to data skew applied. Note: The ingress delay of the connection partner should be set to opposite value to match this egress delay or no delay. July 24, 2014 77 Revision 1.0 Micrel, Inc. KSZ8794CNX Port Registers (Continued) Address Name Description Mode Default R/W 1 R/W 11 Port 4 SW4-MII Mode Select 1 = MII is in MAC mode. (Default) 0 = MII is in PHY mode. 2 MII Mode Select Strap-in option: LED2_1 PU = MII is in MAC mode. (Default) PD = MII is in PHY mode. Note: When set SW4-MII to PHY mode, the CRS, COL, RXC and TXC pins will change from the input to output. 1-0 Interface Mode Select These bits select the interface type and mode for Switch Port 4 (SW4). Port 4 Mode Select: 00 = MII 01 = RMII 10 = Reserved 11 = RGMII. Strap-in option: LED3[1:0] 00 = MII 01 = RMII 10 = Reserved 11 = RGMII (Default) Note: These pins have internal pull-ups. Register 23 (0x17): Port 1 Control 7 Register 39 (0x27): Port 2 Control 7 Register 55 (0x37): Port 3 Control 7 Register 71 (0x47): Reserved Register 87 (0x57): Reserved July 24, 2014 78 Revision 1.0 Micrel, Inc. KSZ8794CNX Port Registers (Continued) Address 7-6 Name Description Reserved N/A Don't Change. Mode Default RO 0000 R/W 11 These bits indicate that the KSZ8794CNX has implemented both the optional MAC control sublayer and the PAUSE function as specified in IEEE Clause 31 and Annex 31B for full duplex operation independent of rate and medium. 5-4 Advertised_Flow_Control _Capability 00 = No pause 01 = Symmetric PAUSE 10 = Asymmetric PAUSE toward link partner toward link partner 11 = Both Symmetric PAUSE and Asymmetric PAUSE toward local devices Bit [5] indicates that asymmetric PAUSE is supported. The value of bit [4] when bit [5] is set indicates the direction of the PAUSE frames that are supported for flow across the link. Asymmetric PAUSE configuration results in independent enabling of the PAUSE receive and PAUSE transmit functions as defined by IEEE Annex 31B. 3 Advertised 100BT FullDuplex Capability 1 = Advertise 100BT full-duplex capability. 0 = Suppress 100BT full-duplex capability from transmission to link partner. R/W 1 2 Advertised 100BT HalfDuplex Capability 1 = Advertise 100BT half-duplex capability. 0 = Suppress 100BT half-duplex capability from transmission to link partner. R/W 1 1 Advertised 10BT FullDuplex Capability 1 = Advertise 10BT full-duplex capability. 0 = Suppress 10BT full-duplex capability from transmission to link partner. R/W 1 0 Advertised 10BT HalfDuplex Capability 1 = Advertise 10BT half-duplex capability. 0 = Suppress 10BT half-duplex capability from transmission to link partner. R/W 1 Register 24 (0x18): Port 1 Status 0 Register 40 (0x28): Port 2 Status 0 Register 56 (0x38): Port 3 Status 0 Register 72 (0x48): Reserved Register 87 (0x57): Reserved July 24, 2014 79 Revision 1.0 Micrel, Inc. KSZ8794CNX Port Registers (Continued) Address 7-6 Name Description Reserved N/A Don't Change. Mode Default RO 0000 RO 00 These bits indicate the partner capability for both the optional MAC control sub-layer and the PAUSE function as specified in IEEE Clause 31 and Annex 31B for full duplex operation independent to rate and medium. Partner_Flow_Control _Capable 00 = No pause 01 = Symmetric PAUSE 10 = Asymmetric PAUSE toward link partner toward link partner 11 = Both Symmetric PAUSE and Asymmetric PAUSE toward local devices 3 Partner 100BT FullDuplex Capability 1 = Link partner 100BT full-duplex capable. 0 = Link partner not 100BT full-duplex capable. RO 0 2 Partner 100BT HalfDuplex Capability 1 = Link partner 100BT half-duplex capable. 0 = Link partner not 100BT half-duplex capable. RO 0 1 Partner 10BT Full-Duplex Capability 1 = Link partner 10BT full-duplex capable. 0 = Link partner not 10BT full-duplex capable. RO 0 0 Partner 10BT Half-Duplex Capability 1 = Link partner 10BT half-duplex capable. 0 = Link partner not 10BT half-duplex capable. RO 0 Mode Default 5-4 Register 25 (0x19): Port 1 Status 1 Register 41 (0x29): Port 2 Status 1 Register 57 (0x39): Port 3 Status 1 Register 73 (0x49): Reserved Register 89 (0x59): Reserved Address Name Description 7 Hp_Mdix 1 = HP Auto MDI/MDI-X Mode 0 = Micrel Auto MDI/MDI-X Mode R/W 1 6 Factory Testing N/A Don't Change. RO 0 5 Polrvs 1 = Polarity is reversed 0 = Polarity is not reversed RO 0 4 Transmit Flow Control Enable 1 = Transmit flow control feature is active 0 = Transmit flow control feature is inactive RO 0 3 Receive Flow Control Enable 1 = Receive flow control feature is active 0 = Receive flow control feature is inactive RO 0 2 Operation Speed 1 = Link speed is 100Mbps 0 = Link speed is 10Mbps RO 0 1 Operation Duplex 1 = Link duplex is full 0 = Link duplex is half RO 0 0 Reserved N/A Don't Change. RO 0 July 24, 2014 80 Revision 1.0 Micrel, Inc. KSZ8794CNX Port Registers (Continued) Register 26 (0x1A): Port 1 PHY Control 8 Register 42 (0x2A): Port 2 PHY Control 8 Register 58 (0x3A): Port 3 PHY Control 8 Register 74 (0x4A): Reserved Register 90 (0x5A): Reserved Address Name Description Mode Default 1 = Less than 10 meter short RO 0 CDT_Result 00 = Normal condition 01 = Open condition detected in cable 10 = Short condition detected in cable 11 = Cable diagnostic test has failed RO 00 4 CDT_Enable 1 = Enable cable diagnostic test. After CDT test has completed, this bit will be self-cleared. 0 = Indicates that the cable diagnostic test (if enabled) has Indicate cable diagnostic test. R/W (SC) 0 3 Force_Link 1 = Force link pass 0 = Normal Operation R/W 0 2 Pwrsave 1 = Enable power saving 0 = Disable power saving R/W 0 Remote Loopback 1 = Perform Remote loopback, loopback on Port 1 as follows: Port 1 (Reg. 26, bit [1] = `1') Start : RXP1/RXM1 (Port 1) Loopback: PMD/PMA of Port 1's PHY End: TXP1/TXM1 (Port 1) Setting Reg. 42, 58, 74 bit [1] = `1' will perform remote loopback on Port 2, 3, 4. 0 = Normal Operation. R/W 0 RO 0 CDT 10M Short 7 6-5 1 Note: CDT means Cable Diagnostic Test Bit[8] of CDT Fault Count 0 CDT_Fault_Count[8] July 24, 2014 Distance to the fault. It's approximately 0.4*CDT_Fault_Count[8:0]. 81 Revision 1.0 Micrel, Inc. KSZ8794CNX Port Registers (Continued) Register 27 (0x1B): Port 1 LinkMD result Register 43 (0x2B): Port 2 LinkMD result Register 59 (0x3B): Port 3 LinkMD result Register 75 (0x4B): Reserved Register 91 (0x5B): Reserved Address Name Description Mode Default RO 0 Mode Default R/W 0 Forced Speed 1 = Forced 100BT if Auto-Negotiation (AN) is disabled (bit [7]). 0 = Forced 10BT if Auto-Negotiation (AN) is disabled (bit [7]). R/W 1 Forced Duplex 1 = Forced full-duplex if (1) AN is disabled or (2) AN is enabled but failed. 0 = Forced half-duplex if (1) AN is disabled or (2) AN is enabled but failed (Default). R/W 0 Reserved N/A Don't Change. RO 0 Bits[7:0] of CDT Fault Count 7-0 CDT_Fault_Count[7:0] Distance to the fault. It's approximately 0.4m*CDT_Fault_Count[8:0] Register 28 (0x1C): Port 1 Control 9 Register 44 (0x2C): Port 2 Control 9 Register 60 (0x3C): Port 3 Control 9 Register 76 (0x4C): Reserved Register 92 (0x5C): Reserved Address 7 Name Disable Auto-Negotiation Description 1 = Disable Auto-Negotiation. Speed and duplex are decided by bits [6:5] of the same register. 0 = Auto-Negotiation is on. Note: The register bit value is the INVERT of the strap value at the pin. 6 5 4-0 July 24, 2014 82 Revision 1.0 Micrel, Inc. KSZ8794CNX Port Registers (Continued) Register 29 (0x1D): Port 1 Control 10 Register 45 (0x2D): Port 2 Control 10 Register 61 (0x3D): Port 3 Control 10 Register 77 (0x4D): Reserved Register 93 (0x5D): Reserved Address Name Description Mode Default 7 LED Off 1 = Turn off all Port's LEDs (LEDx_2, LEDx_1, LEDx_0 Pins, where "x" is the Port number). These pins will be driven high if this bit is set to one. 0 = Normal operation. R/W 0 6 Txids 1 = Disable Port's transmitter. 0 = Normal operation. R/W 0 5 Restart AN 1 = Restart Auto-Negotiation. 0 = Normal operation. R/W (SC) 0 4 Reserved N/A Don't Change RO 0 3 Power Down 1 = Power down. 0 = Normal operation. R/W 0 2 Disable Auto MDI/MDI-X 1 = Disable Auto-MDI/MDIX function. 0 = Enable Auto-MDI/MDIX function. R/W 0 1 Forced MDI 1 = If Auto-MDI/MDIX is disabled, force PHY into MDI mode. 0 = MDI-X mode. R/W 0 MAC Loopback 1 = Perform MAC loopback. Loop back path is as follows: E.g. set Port 1 MAC Loopback (Reg. 29, bit [0] = `1'), use Port 2 as monitor Port. The packets will transfer. Start: Port 2 receiving (also can start to receive packets from Port 3, 4, 5). Loop-back: Port 1's MAC. End: Port 2 transmitting (also can end at Port 3, 4, 5 respectively). Setting Reg. 45, 61, 93, bit [0] = `1' will perform MAC loopback on Port 2, 3, 4, 5 respectively. 0 = Normal Operation. R/W 0 0 July 24, 2014 83 Revision 1.0 Micrel, Inc. KSZ8794CNX Port Registers (Continued) Register 30 (0x1E): Port 1 Status 2 Register 46 (0x2E): Port 2 Status 2 Register 62 (0x3E): Port 3 Status 2 Register 78 (0x4E): Reserved Register 94 (0x5E): Reserved Name Description 7 MDIX Status 6 Address Mode Default 1 = MDI. 0 = MDI-X. RO 0 Auto-Negotiation Done 1 = Auto-Negotiation done. 0 = Auto-Negotiation not done. RO 0 5 Link Good 1 = Link good. 0 = Link not good. RO 0 4-0 Reserved N/A Don't Change. RO 00000 Mode Default Register 31 (0x1F): Port 1 Control 11 and Status 3 Register 47 (0x2F): Port 2 Control 11 and Status 3 Register 63 (0x3F): Port 3 Control 11 and Status 3 Register 79 (0x4F): Reserved Register 95 (0x5F): Reserved Address Name Description 7 PHY Loopback 1 = Perform PHY loopback. Loop back path is as follows: Example, Set Port 1 PHY Loopback (Reg. 31, bit [7] = `1') Use the Port 2 as monitor Port. The packets will transfer. Start: Port 2 receiving (also can start from Port 3, 4, 5). Loopback: PMD/PMA of Port 1's PHY End: Port 2 transmitting (also can end at Port 3, 4, 5 respectively). Setting Reg. 47, 63, 95, bit [7] = `1' will perform PHY loopback on Port 2, 3, 4, 5 respectively. 0 = Normal Operation. R/W 0 6 Reserved N/A Don't Change RO 0 5 PHY Isolate 1 = Electrical isolation of PHY from MII/RMII and TX+/TX-. 0 = Normal operation. R/W 0 4 Soft Reset 1 = PHY soft reset. This bit is self-clearing. 0 = Normal operation. R/W (SC) 0 3 Force Link 1 = Force link in the PHY. 0 = Normal operation R/W 0 July 24, 2014 84 Revision 1.0 Micrel, Inc. KSZ8794CNX Port Registers (Continued) Address 2-0 Name Description Port Operation Mode Indication Indicate the current state of Port operation mode: 000 = Reserved 001 = Still in Auto-Negotiation 010 = 10BASE-T half duplex 011 = 100BASE-TX half duplex 100 = Reserved 101 = 10BASE-T full duplex 110 = 100BASE-TX full duplex 111 = Reserved Mode Default RO 001 Note: Port Control 7-11 and Port Status 1-3 contents can be accessed by MDC/MDIO interface via the standard MIIM registers. July 24, 2014 85 Revision 1.0 Micrel, Inc. KSZ8794CNX Advanced Control Registers Registers 104 to 109 define the switching engine's MAC address. This 48-bit address is used as the source address in MAC pause control frames. Address Name Description Mode Default R/W 0x00 R/W 0x10 R/W 0xA1 R/W 0xff R/W 0xff Register 104 (0x68): MAC Address Register 0 7-0 MACA[47:40] Register 105 (0x69): MAC Address Register 1 7-0 MACA[39:32] Register 106 (0x6A): MAC Address Register 2 7-0 MACA[31:24] Register 107 (0x6B): MAC Address Register 3 7-0 MACA[23:16] Register 108 (0x6C): MAC Address Register 4 7-0 MACA[15:8] July 24, 2014 86 Revision 1.0 Micrel, Inc. KSZ8794CNX Advanced Control Registers (Continued) Use Registers 110 and 111 to read or write data to the static MAC address table, VLAN table, dynamic address table, PME registers, ACL tables, EEE registers and the MIB counters. Address Name Description Mode Default EEE/ACL/PME Indirect Register Function Select 000 = Indirect mode is used for table select in bits [3:2] While these bits are not equal 000, bits [3:2] are used for 2 additional MSB address bits. 001 = Global and Port base EEE registers are selected, Port count is specified in 4 MSB indirect address bits and 8 bits register pointer is specified in 8 LSB indirect address bits. 010 = Port base ACL registers are selected, Port count is specified in 4 MSB indirect address bits and register pointer is specified in 8 LSB indirect address bits. 011 = Reserved 100 = PME control registers are selected. 101 = LinkMD cable diagnosis used. (See example in LinkMD section). R/W 000 Read High Write Low 1 = Read cycle. 0 = Write cycle. R/W 0 R/W 0 R/W 00 R/W 00000000 Register 110 (0x6E): Indirect Access Control 0 7-5 4 If bits [6:5] = 00, then 00 = Static MAC Address Table selected. 01 = VLAN table selected. 10 = Dynamic Address Table selected. 11 = MIB Counter selected. If bits [6:5] not equal 00, then These are indirect address [11:10] that is MSB of indirect address, bits [11:8] of the indirect address may be served as Port address, and bits [7:0] as register address. 3-2 Table Select or Indirect Address [11:10] Note: The Register 110 bits[3:0] are used for the indirect address bits [11:8] 4 MSB bits, the 4 bits are used for the port indirect registers as well. 0000 = Global indirect registers 0001 = Port 1 indirect registers 0010 = Port 2 indirect registers 0011 = Port 3 indirect registers 0100 = Reserved 0101= Port 4 indirect registers Note: The Register 111 bits[7:0] are used for the indirect address bits of 8 LSB for indirect register address spacing. 1-0 Indirect Address [9:8] Bits [9:8] of indirect address. Register 111 (0x6F): Indirect Access Control 1 7-0 Indirect Address [7:0] Bits [7:0] of indirect address. Note: Write to Register 111 will actually trigger a command. Read or write access will be decided by bit [4] of Register 110. July 24, 2014 87 Revision 1.0 Micrel, Inc. KSZ8794CNX Advanced Control Registers (Continued) The following Indirect Data Registers 112-120 are used for table of static, VLAN, dynamic table, PME, EEE, ACL and MIB counter. Address Name Description Mode Default R/W 00000000 R/W 00000000 R/W 00000000 R/W 00000000 R/W 00000000 R/W 00000000 R/W 00000000 R/W 00000000 R/W 00000000 Register 112 (0x70): Indirect Data Register 8 7-0 Indirect Data [68:64] Bits [71:64] of indirect data. Register 113 (0x71): Indirect Data Register 7 7-0 Indirect Data [63:56] Bits [63:56] of indirect data. Register 114 (0x72): Indirect Data Register 6 7-0 Indirect Data [55:48] Bits [55:48] of indirect data. Register 115 (0x73): Indirect Data Register 5 47-40 Indirect Data [47:40] Bits [47:40] of indirect data. Register 116 (0x74): Indirect Data Register 4 7-0 Indirect Data [39:32] Bits [39:32] of indirect data. Register 117 (0x75): Indirect Data Register 3 7-0 Indirect Data [31:24] Bits [31:24] of indirect data Register 118 (0x76): Indirect Data Register 2 7-0 Indirect Data [23:6] Bits [23:16] of indirect data. Register 119 (0x77): Indirect Data Register 1 7-0 Indirect Data [15:8] Bits [15:8] of indirect data. Register 120 (0x78): Indirect Data Register 0 7-0 Indirect Data [7:0] Bits [7:0] of indirect data. The named indirect byte registers is a direct register which is used for PME/ACL/EEE Indirect Register access only. The Indirect Byte Register 160 (0XA0) is used for read/write to all PME, EEE and ACL indirect registers. Address Name Description Mode Default R/W 00000000 Register 160 (0XA0): Indirect Byte Register (It is for PME, EEE and ACL Registers) 7-0 Indirect Byte [7:0] July 24, 2014 Byte data of indirect access. 88 Revision 1.0 Micrel, Inc. KSZ8794CNX Advanced Control Registers (Continued) Address Name Description Mode Default RO 000 RO 0 RO 0 R/WC 0 R/WC 0 R/WC 0 Register 124 (0x7C): Interrupt Status Register 7-5 Reserved N/A Don't Change 1 = PME interrupt request 0 = Normal 4 PME Interrupt Status Note: This bit reflects PME control registers, write to PME Control Register to clear. This bit is set when PME is asserted. Write a "1" to clear this bit (WC) 3 2 Reserved N/A Don't Change Port 3 Interrupt Status 1 = Port 3 interrupt request 0 = Normal Note: This bit is set by a link change on Port 3. Write a "1" to clear this bit (WC) 1 Port 2 Interrupt Status 1 = Port 2 interrupt request 0 = Normal Note: This bit is set by a link change on Port 2. Write a "1" to clear this bit (WC) 0 Port 1 Interrupt Status 1 = Port 1 interrupt request 0 = Normal Note: This bit is set by link change on Port 1. Write a "1" to clear this bit (WC) Register 125 (0x7D): Interrupt Mask Register 7-5 Reserved Don't Change. RO 000 4 PME Interrupt Mask 1 = Enable PME interrupt. 0 = Normal R/W 0 3 Reserved N/A Don't Change RO 0 2 Port 3 Interrupt Mask 1 = Enable Port 3 interrupt. 0 = Normal R/W 0 1 Port 2 Interrupt Mask 1 = Enable Port 2 interrupt. 0 = Normal R/W 0 0 Port 1 Interrupt Mask 1 = Enable Port 1 interrupt. 0 = Normal R/W 0 Register 126 (0x7E): ACL Interrupt Status Register 7-5 4-0 Reserved Don't Change. RO 000 ACL_INT_STATUS ACL Interrupt Status, one bit per port 1 = ACL interrupt detected. 0 = No ACL interrupt detected. RO 00000 Register 127 (0x7F): ACL Interrupt Control Register 7-5 4-0 Reserved Don't Change. RO 000 ACL_INT_ENABLE ACL Interrupt Enable, one bit per port 1 = ACL interrupt enabled. 0 = ACL interrupt disabled. R/W 0 July 24, 2014 89 Revision 1.0 Micrel, Inc. KSZ8794CNX Advanced Control Registers (Continued) The Registers 128, 129 can be used to map from 802.1p priority field 0-7 to the switch's four priority queues 0-3. 0x3 is the highest priority queues as priority 3 and 0x0 is the lowest priority queues as priority 0. Address Name Description Mode Default Register 128 (0x80): Global Control 12 7-6 Tag_0x3 IEEE 802.1p mapping. The value in this field is used as the frame's priority when its IEEE 802.1p tag has a value of 0x3. R/W 0x1 5-4 Tag_0x2 IEEE 802.1p mapping. The value in this field is used as the frame's priority when its IEEE 802.1p tag has a value of 0x2. R/W 0x1 3-2 Tag_0x1 IEEE 802.1p mapping. The value in this field is used as the frame's priority when its IEEE 802.1p tag has a value of 0x1. R/W 0x0 1-0 Tag_0x0 IEEE 802.1p mapping. The value in this field is used as the frame's priority when its IEEE 802.1p tag has a value of 0x0. R/W 0x0 Register 129 (0x81): Global Control 13 7-6 Tag_0x7 IEEE 802.1p mapping. The value in this field is used as the frame's priority when its IEEE 802.1p tag has a value of 0x7. R/W 0x3 5-4 Tag_0x6 IEEE 802.1p mapping. The value in this field is used as the frame's priority when its IEEE 802.1p tag has a value of 0x6. R/W 0x3 3-2 Tag_0x5 IEEE 802.1p mapping. The value in this field is used as the frame's priority when its IEEE 802.1p tag has a value of 0x5. R/W 0x2 1-0 Tag_0x4 IEEE 802.1p mapping. The value in this field is used as the frame's priority when its IEEE 802.1p tag has a value of 0x4. R/W 0x2 R/W 10 RO 001000 Register 130 (0x82): Global Control 14 When the 2 Queues configuration is selected, these Pri_2Q[1:0] bits are used to map the 2-bit result of IEEE 802.1p from Register 128/129 or TOS/DiffServ from Register 144-159 mapping (for 4 Queues) into two queues low/high priorities. Pri_2Q[1:0] 7-6 2-bit result of IEEE 802.1p or TOS/DiffServ 00 (0) = Map to Low priority queue 01 (1) = Prio_2Q[0] map to Low/High priority queue 10 (2) = Prio_2Q[1] map to Low/High priority queue 11 (3) = Map to High priority queue Pri_2Q[1:0] : 00 = Result 0,1, 2 are low priority. 3 is high priority. 01 = Not supported and should be avoided 10 = Result 0,1 are low priority. 2, 3 are high priority (default). 11 = Result 0 is low priority. 1, 2, 3 are high priority. 5-0 Reserved July 24, 2014 N/A Don't Change 90 Revision 1.0 Micrel, Inc. KSZ8794CNX Advanced Control Registers (Continued) Address Name Description Mode Default Register 131 (0x83): Global Control 15 7-6 5 4-0 Reserved N/A Don't Change RO 10 Unknown Unicast Packet Forward 1 = Enable supporting unknown unicast packet forward 0 = Disable R/W 0 R/W 00000 Unknown Unicast Packet Forward Port Pap 00000 = Filter unknown unicast packet 00001 = Forward unknown unicast packet to Port 1 00011 = Forward unknown unicast packet to Port 1, Port 2 00111 = Forward unknown unicast packet to Port 1, Port 2 and Port 3 11111 = Broadcast unknown unicast packet to all Ports Note: Bit 3 is reserved Register 132 (0x84): Global Control 16 7-6 5 4-0 Reserved N/A Don't Change RO 01 Unknown Multicast Packet Forward (not including IP multicast packet) 1 = Enable supporting unknown multicast packet forward 0 = Disable R/W 0 R/W 00000 Unknown Multicast Packet Forward Port Map 00000 = Filter unknown multicast packet 00001 = Forward unknown multicast packet to Port 1 00011 = Forward unknown multicast packet to Port 1, Port 2 00111 = Forward unknown multicast packet to Port 1, Port 2 and Port 3 11111 = Broadcast unknown multicast packet to all Ports Note: Bit 3 is reserved Register 133(0x85): Global Control 17 7-6 5 4-0 Reserved N/A Don't Change RO 00 Unknown VID Packet Forward 1 = Enable supporting unknown VID packet forward 0 = Disable R/W 0 R/W 00000 Unknown VID Packet Forward Port Map 00000 = Filter unknown VID packet 00001 = Forward unknown VID packet to Port 1 00011 = Forward unknown VID packet to Port 1, Port 2 00111 = Forward unknown VID packet to Port 1, Port 2 and Port 3 11111 = Broadcast unknown VID packet to all Ports Note: Bit 3 is reserved July 24, 2014 91 Revision 1.0 Micrel, Inc. KSZ8794CNX Advanced Control Registers (Continued) Address Name Description Mode Default Register 134 (0x86): Global Control 18 7 6 Reserved N/A Don't Change RO 0 Self-Address Filter Enable 1 = Enable filtering of self-address unicast and multicast packet 0 = Do not filter self-address packet R/W 0 R/W 0 R/W 00000 Note: The self-address filtering will filter packets on the egress port , self MAC address is assigned in the Register 104-109. 5 4-0 Unknown IP Multicast Packet Forward Unknown IP Multicast Packet Forward Port Map 1 = Enable supporting unknown IP multicast packet forward 0 = Disable supporting unknown IP multicast packet forward 00000 = Filter unknown IP multicast packet 00001 = Forward unknown IP multicast packet to Port 1 00011 = Forward unknown IP multicast packet to Port 1, Port 2 00111 = Forward unknown IP multicast packet to Port 1, Port 2 and Port 3 11111 = Broadcast unknown IP multicast packet to all Ports Note: Bit 3 is reserved Register 135 (0x87): Global Control 19 7-6 5-4 3 2 1-0 Reserved N/A Don't Change RO 00 Ingress Rate Limit Period The unit period for calculating Ingress Rate Limit 00 = 16ms 01 = 64ms 1x = 256ms R/W 01 Queue-based Egress Rate Limit Enabled Enable Queue-based Egress Rate Limit 0 = Port-base Egress Rate Limit (default) 1 = Queue-based Egress Rate Limit R/W 0 Insertion Source Port PVID Tag Selection Enable 1 = Enable source Port PVID tag insertion or noninsertion option on the egress Port for each source Port PVID based on the Ports control 8 Registers. 0 = Disable, all packets from any ingress Port will be inserted PVID based on Port Control 0 Register bit [2]. R/W 0 Reserved N/A Don't Change RO 00 July 24, 2014 92 Revision 1.0 Micrel, Inc. KSZ8794CNX Advanced Control Registers (Continued) Address Name Description Mode Default Register 144 (0x90): TOS Priority Control Register 0 The Ipv4/Ipv6 TOS priority control registers implement a fully decoded 64-bit differentiated services code point (DSCP) register used to determine priority from the 6-bit TOS field in the IP header. The most significant 6 bits of the TOS field are fully decoded into 64 possibilities, and the singular code that results is mapped to the value in the corresponding bit in the DSCP register. 7-6 DSCP[7:6] 5-4 DSCP[5:4] 3-2 DSCP[3:2] 1-0 DSCP[1:0] Ipv4 and Ipv6 mapping The value in this field is used as the frame's priority when bits [7:2] of the frame's IP OS/DiffServ/Traffic Class value is 0x03. Ipv4 and Ipv6 mapping The value in this field is used as the frame's priority when bits [7:2] of the frame's IP OS/DiffServ/Traffic Class value is 0x02. Ipv4 and Ipv6 mapping The value in this field is used as the frame's priority when bits [7:2] of the frame's IP OS/DiffServ/Traffic Class value is 0x01. Ipv4 and Ipv6 mapping The value in this field is used as the frame's priority when bits [7:2] of the frame's IP OS/DiffServ/Traffic Class value is 0x00. R/W 00 R/W 00 R/W 00 R/W 00 Register 145 (0x91): TOS Priority Control Register 1 7-6 DSCP[15:14] Ipv4 and Ipv6 mapping _ for value 0x07 R/W 00 5-4 DSCP[13:12] Ipv4 and Ipv6 mapping _ for value 0x06 R/W 00 3-2 DSCP[11:10] Ipv4 and Ipv6 mapping _ for value 0x05 R/W 00 1-0 DSCP[9:8] Ipv4 and Ipv6 mapping _ for value 0x04 R/W 00 Register 146 (0x92): TOS Priority Control Register 2 7-6 DSCP[23:22] Ipv4 and Ipv6 mapping _ for value 0x0B R/W 00 5-4 DSCP[21:20] Ipv4 and Ipv6 mapping _ for value 0x0A R/W 00 3-2 DSCP[19:18] Ipv4 and Ipv6 mapping _ for value 0x09 R/W 00 1-0 DSCP[17:16] Ipv4 and Ipv6 mapping _ for value 0x08 R/W 00 Register 147 (0x93): TOS Priority Control Register 3 7-6 DSCP[31:30] Ipv4 and Ipv6 mapping _ for value 0x0F R/W 00 5-4 DSCP[29:28] Ipv4 and Ipv6 mapping _ for value 0x0E R/W 00 3-2 DSCP[27:26] Ipv4 and Ipv6 mapping _ for value 0x0D R/W 00 1-0 DSCP[25:24] Ipv4 and Ipv6 mapping _ for value 0x0C R/W 00 Register 148 (0x94): TOS Priority Control Register 4 7-6 DSCP[39:38] Ipv4 and Ipv6 mapping _ for value 0x13 R/W 00 5-4 DSCP[37:36] Ipv4 and Ipv6 mapping _ for value 0x12 R/W 00 3-2 DSCP[35:34] Ipv4 and Ipv6 mapping _ for value 0x11 R/W 00 1-0 DSCP[33:32] Ipv4 and Ipv6 mapping _ for value 0x10 R/W 00 July 24, 2014 93 Revision 1.0 Micrel, Inc. KSZ8794CNX Advanced Control Registers (Continued) Address Name Description Mode Default Register 149 (0x95): TOS Priority Control Register 5 7-6 DSCP[47:46] Ipv4 and Ipv6 mapping _ for value 0x17 R/W 00 5-4 DSCP[45:44] Ipv4 and Ipv6 mapping _ for value 0x16 R/W 00 3-2 DSCP[43:42] Ipv4 and Ipv6 mapping _ for value 0x15 R/W 00 1-0 DSCP[41:40] Ipv4 and Ipv6 mapping _ for value 0x14 R/W 00 Register 150 (0x96): TOS Priority Control Register 6 7-6 DSCP[55:54] Ipv4 and Ipv6 mapping _ for value 0x1B R/W 00 5-4 DSCP[53:52] Ipv4 and Ipv6 mapping _ for value 0x1A R/W 00 3-2 DSCP[51:50] Ipv4 and Ipv6 mapping _ for value 0x19 R/W 00 1-0 DSCP[49:48] Ipv4 and Ipv6 mapping _ for value 0x18 R/W 00 Register 151 (0x97): TOS Priority Control Register 7 7-6 DSCP[63:62] Ipv4 and Ipv6 mapping _ for value 0x1F R/W 00 5-4 DSCP[61:60] Ipv4 and Ipv6 mapping _ for value 0x1E R/W 00 3-2 DSCP[59:58] Ipv4 and Ipv6 mapping _ for value 0x1D R/W 00 1-0 DSCP[57:56] Ipv4 and Ipv6 mapping _ for value 0x1C R/W 00 Register 152 (0x98): TOS Priority Control Register 8 7-6 DSCP[71:70] Ipv4 and Ipv6 mapping _ for value 0x23 R/W 00 5-4 DSCP[69:68] Ipv4 and Ipv6 mapping _ for value 0x22 R/W 00 3-2 DSCP[67:66] Ipv4 and Ipv6 mapping _ for value 0x21 R/W 00 1-0 DSCP[65:64] Ipv4 and Ipv6 mapping _ for value 0x20 R/W 00 Register 153 (0x99): TOS Priority Control Register 9 7-6 DSCP[79:78] Ipv4 and Ipv6 mapping _ for value 0x27 R/W 00 5-4 DSCP[77:76] Ipv4 and Ipv6 mapping _ for value 0x26 R/W 00 3-2 DSCP[75:74] Ipv4 and Ipv6 mapping _ for value 0x25 R/W 00 1-0 DSCP[73:72] Ipv4 and Ipv6 mapping _ for value 0x24 R/W 00 Register 154 (0x9A): TOS Priority Control Register 10 7-6 DSCP[87:86] Ipv4 and Ipv6 mapping _ for value 0x2B R/W 00 5-4 DSCP[85:84] Ipv4 and Ipv6 mapping _ for value 0x2A R/W 00 3-2 DSCP[83:82] Ipv4 and Ipv6 mapping _ for value 0x29 R/W 00 1-0 DSCP[81:80] Ipv4 and Ipv6 mapping _ for value 0x28 R/W 00 Register 155 (0x9B): TOS Priority Control Register 11 7-6 DSCP[95:94] Ipv4 and Ipv6 mapping _ for value 0x2F R/W 00 5-4 DSCP[93:92] Ipv4 and Ipv6 mapping _ for value 0x2E R/W 00 3-2 DSCP[91:90] Ipv4 and Ipv6 mapping _ for value 0x2D R/W 00 1-0 DSCP[89:88] Ipv4 and Ipv6 mapping _ for value 0x2C R/W 00 July 24, 2014 94 Revision 1.0 Micrel, Inc. KSZ8794CNX Advanced Control Registers (Continued) Address Name Description Mode Default Register 156 (0x9C): TOS Priority Control Register 12 7-6 DSCP[103:102] Ipv4 and Ipv6 mapping _ for value 0x33 R/W 00 5-4 DSCP[101:100] Ipv4 and Ipv6 mapping _ for value 0x32 R/W 00 3-2 DSCP[99:98] Ipv4 and Ipv6 mapping _ for value 0x31 R/W 00 1-0 DSCP[97:96] Ipv4 and Ipv6 mapping _ for value 0x30 R/W 00 Register 157 (0x9D): TOS Priority Control Register 13 7-6 DSCP[111:110] Ipv4 and Ipv6 mapping _ for value 0x37 R/W 00 5-4 DSCP[109:108] Ipv4 and Ipv6 mapping _ for value 0x36 R/W 00 3-2 DSCP[107:106] Ipv4 and Ipv6 mapping _ for value 0x35 R/W 00 1-0 DSCP[105:104] Ipv4 and Ipv6 mapping _ for value 0x34 R/W 00 Register 158 (0x9E): TOS Priority Control Register 14 7-6 DSCP[119:118] Ipv4 and Ipv6 mapping _ for value 0x3B R/W 00 5-4 DSCP[117:116] Ipv4 and Ipv6 mapping _ for value 0x3A R/W 00 3-2 DSCP[115:114] Ipv4 and Ipv6 mapping _ for value 0x39 R/W 00 1-0 DSCP[113:112] Ipv4 and Ipv6 mapping _ for value 0x38 R/W 00 Register 159 (0x9F): TOS Priority Control Register 15 7-6 DSCP[127:126] Ipv4 and Ipv6 mapping _ for value 0x3F R/W 00 5-4 DSCP[125:124] Ipv4 and Ipv6 mapping _ for value 0x3E R/W 00 3-2 DSCP[123:122] Ipv4 and Ipv6 mapping _ for value 0x3D R/W 00 1-0 DSCP[121:120] Ipv4 and Ipv6 mapping _ for value 0x3C R/W 00 July 24, 2014 95 Revision 1.0 Micrel, Inc. KSZ8794CNX Advanced Control Registers (Continued) Address Name Description Mode Default RO 0 R/W 110 RO 0 R/W 010 RO 0x2 R/W 0 R/W 0 RO 10 Register 163 (0XA3): Global Control 20 7 Reserved N/A Don't Change High Speed Interfaces Drive Strength for GMII & RGMI 6-4 3 GMII/RGMI High Speed Drive Strength Reserved 000 = 2mA 001 = 4mA 010 = 8mA 011 = 12mA 100 = 16mA 101 = 20mA 110 = 24mA (default) 111 = 28mA N/A Don't Change High Speed Interfaces Drive Strength for MII & RMII 2-0 MII/RMII Low Speed Drive Strength 000 = 2mA 001 = 4mA 010 = 8mA (default) 011 = 12mA 100 = 16mA 101 = 20mA 110 = 24mA 111 = 28mA Register 164 (0XA4): Global Control 21 7-4 Reserved N/A Don't Change IPv6 MLD Snooping Option 3 IPv6 MLD Snooping Option 1 = Enable 0 = Disable IPv6 MLD Snooping Enable 2 1-0 IPv6 MLD Snooping Enable Reserved July 24, 2014 1 = Enable 0 = Disable N/A Don't Change 96 Revision 1.0 Micrel, Inc. KSZ8794CNX Advanced Control Registers (Continued) Address Name Description Mode Default RO 1 R/W 0 RO 0000 R/W 0 R/W 0 R/W 0 R/W 0 Register 176 (0xB0): Port 1 Control 12 Register 192 (0xC0): Port 2 Control 12 Register 208 (0xD0): Port 3 Control 12 Register 224 (0xE0): Reserved Register 240 (0xF0): Port 4 Control 12 7 6 Reserved Pass All Frames Port based enable to pass all frames 1 = Enable 0 = Disable Note: This is used in the port mirroring with RX sniff only. 5-4 3 Reserved Insert Source Port PVID for Untagged Packet Destination to Highest Egress Port Reserved Register 176: Insert source Port 1 PVID for untagged frame at egress Port 4 Register 192: Insert source Port 2 PVID for untagged frame at egress Port 4 Register 208: Insert source Port 3 PVID for untagged frame at egress Port 4 Register 224: Reserved Register 240: Reserved Note: Enabled by the Register 135 bit [2]. 2 Insert Source Port PVID for Untagged Packet Destination to Second Highest Egress Port Register 176: Reserved Register 192: Reserved Register 208: Reserved Register 224: Reserved Register 240: Insert source Port 4 PVID for untagged frame at egress Port 3 Note: Enabled by the Register 135 bit [2]. 1 Insert Source Port PVID for Untagged Packet Destination to Second Lowest Egress Port Register 176: Insert source Port 1 PVID for untagged frame at egress Port 3 Register 192: Insert source Port 2 PVID for untagged frame at egress Port 3 Register 208: Insert source Port 3 PVID for untagged frame at egress Port 2 Register 224: Reserved Register 240: Insert source Port 4 PVID for untagged frame at egress Port 2 Note: Enabled by the Register 135 bit [2]. 0 Insert Source Port PVID for Untagged Packet Destination to Lowest Egress Port Register 176: Insert source Port 1 PVID for untagged frame at egress Port 2 Register 192: Insert source Port 2 PVID for untagged frame at egress Port 1 Register 208: Insert source Port 3 PVID for untagged frame at egress Port 1 Register 224: Reserved Register 240: Insert source Port 4 PVID for untagged frame at egress Port 1 Note: Enabled by the Register 135 bit [2]. July 24, 2014 97 Revision 1.0 Micrel, Inc. KSZ8794CNX Advanced Control Registers (Continued) Address Name Description Mode Default RO 0000000 R/W 0 0 = Disable tagged packets drop 1 = Enable tagged packets drop R/W 0 Enable Port Transmit Queue 3 Ratio 0 = Strict priority. Will transmit all the packets from this priority queue 3 before transmit lower priority queue. 1 = Bits [6:0] reflect the packet number allow to transmit from this priority queue 3 within a certain time. R/W 1 Port Transmit Queue 3 Ratio[6:0] Packet number for Transmit Queue 3 for highest priority packets in four queues mode. R/W 0001000 Register 177 (0xB1): Port 1 Control 13 Register 193 (0xC1): Port 2 Control 13 Register 209 (0xD1): Port 3 Control 13 Register 225 (0xE1): Reserved Register 241 (0xF1): Port 4 Control 13 7-2 Reserved This bit, in combination with Register16/32/48/64/80 bit [0], will select the split of 1, 2 and 4 queues: {Register 177 bit [1], Register 16 bit [0] = }: 1 4 Queue Split Enable 0 Enable Dropping Tag 11 = Reserved. 10 = The port output queue is split into four priority queues or if map 802.1p to priority 0-3 mode. 01 = The port output queue is split into two priority queues or if map 802.1p to priority 0-3 mode. 00 = Single output queue on the port. There is no priority differentiation even though packets are classified into high and low priority. Register 178 (0xB2): Port 1 Control 14 Register 194 (0xC2): Port 2 Control 14 Register 210 (0xD2): Port 3 Control 14 Register 226 (0xE2): Reserved Register 242 (0xF2): Port 4 Control 14 7 6-0 July 24, 2014 98 Revision 1.0 Micrel, Inc. KSZ8794CNX Advanced Control Registers (Continued) Address Name Description Mode Default Enable Port Transmit Queue 2 Ratio 0 = Strict priority. Will transmit all the packets from this priority queue 2 before transmit lower priority queue. 1 = Bits [6:0] reflect the packet number allow to transmit from this priority queue 1 within a certain time. R/W 1 Port Transmit Queue 2 Ratio[6:0] Packet number for Transmit Queue 2 for high/low priority packets in high/low priority packets in four queues mode. R/W 0000100 Enable Port Transmit Queue 1 Rate 0 = Strict priority. Will transmit all the packets from this priority queue 1 before transmit lower priority queue. 1 = Bits [6:0] reflect the packet number allow to transmit from this priority queue 1 within a certain time. R/W 1 Port Transmit Queue 1 Ratio[6:0] Packet number for Transmit Queue 1 for low/high priority packets in four queues mode and high priority packets in two queues mode. R/W 0000010 Enable Port Transmit Queue 0 Rate 0 = Strict priority. Will transmit all the packets from this priority queue 0 before transmit lower priority queue. 1 = Bits [6:0] reflect the packet number allow to transmit from this priority queue 0 within a certain time. R/W 1 Port Transmit Queue 0 Ratio[6:0] Packet number for Transmit Queue 0 for lowest priority packets in four queues mode and low priority packets in two queues mode. R/W 0000001 Register 179 (0xB3): Port 1 Control 15 Register 195 (0xC3): Port 2 Control 15 Register 211 (0xD3): Port 3 Control 15 Register 227 (0xE3): Reserved Register 243 (0xF3): Port 4 Control 15 7 6-0 Register 180 (0xB4): Port 1 Control 16 Register 196 (0xC4): Port 2 Control 16 Register 212 (0xD4): Port 3 Control 16 Register 228 (0xE4): Reserved Register 244 (0xF4): Port 4 Control 16 7 6-0 Register 181 (0xB5): Port 1 Control 17 Register 197 (0xC5): Port 2 Control 17 Register 213 (0xD5): Port 3 Control 17 Register 229 (0xE5): Reserved Register 245 (0xF5): Port 4 Control 17 7 6-0 July 24, 2014 99 Revision 1.0 Micrel, Inc. KSZ8794CNX Advanced Control Registers (Continued) Address Name Description Mode Default RO 0 Register 182 (0xB6): Port 1 Rate Limit Control Register 198 (0xC6): Port 2 Rate Limit Control Register 214 (0xD6): Port 3 Rate Limit Control Register 230 (0xE6): Reserved Register 246 (0xF6): Port 4 Rate Limit Control 7 Reserved 6 Ingress Limit Port/Priority Based Select 1 = Ingress rate limit is Port based 0 = Ingress rate limit is priority based R/W 0 5 Ingress Limit Bit/Packets Mode Select 1 = Rate limit is counted based on number of packet. 0 = rate limit is counted based on number of bit. R/W 0 4 Ingress Rate Limit Flow Control Enable 1 = Flow Control is asserted if the Port's receive rate is exceeded. 0 = Flow Control is not asserted if the Port's receive rate is exceeded. R/W 0 Limit Mode Ingress Limit Mode These bits determine what type of frames are limited and counted against ingress rate limiting. 00 = Limit and count all frames. 01 = Limit and count Broadcast, Multicast, and flooded unicast frames. 10 = Limit and count Broadcast and Multicast frames only. 11 = Limit and count Broadcast frames only. R/W 00 Count IFG Count IFG Bytes 1 = Each frame's minimum inter-frame gap. (IFG) bytes (12 per frame) are included in Ingress and Egress rate limiting calculations. 0 = IFG bytes are not counted. R/W 0 Count Pre Count Preamble Bytes 1 = Each frame's preamble bytes (8 per frame) are included in Ingress and Egress rate limiting calculations. 0 = Preamble bytes are not counted. R/W 0 3-2 1 0 Register 183 (0xB7): Port 1 Priority 0 Ingress Limit Control 1(4) Register 199 (0xC7): Port 2 Priority 0 Ingress Limit Control 1 Register 215 (0xD7): Port 3 Priority 0 Ingress Limit Control 1 Register 231 (0xE7): Reserved Register 247 (0xF7): Port 4 Priority 0 Ingress Limit Control 1 July 24, 2014 100 Revision 1.0 Micrel, Inc. KSZ8794CNX Advanced Control Registers (Continued) Address 7 6-0 Name Description Reserved Port Based Priority 0 Ingress Limit Ingress Data Rate Limit For Priority 0 Frames Ingress traffic from this Port is shaped according to the Rate Selection Table in Rate Limit Support section. Mode Default RO 0 R/W 0000000 RO 0 R/W 0000000 Register 184 (0xB8): Port 1 Priority 1 Ingress Limit Control 2(4) Register 200 (0xC8): Port 2 Priority 1 Ingress Limit Control 2 Register 216 (0xD8): Port 3 Priority 1 Ingress Limit Control 2 Register 232 (0xE8): Reserved Register 248 (0xF8): Port 4 Priority 1 Ingress Limit Control 2 7 6-0 Reserved Port Based Priority 1 Ingress Limit Ingress Data Rate Limit For Priority 1 Frames Ingress traffic from this Port is shaped according to the Rate Selection Table in Rate Limit Support section. Register 185 (0xB9): Port 1 Priority 2 Ingress Limit Control 3(4) Register 201 (0xC9): Port 2 Priority 2 Ingress Limit Control 3 Register 217 (0xD9): Port 3 Priority 2 Ingress Limit Control 3 Register 233 (0xE9): Reserved Register 249 (0xF9): Port 4 Priority 2 Ingress Limit Control 3 July 24, 2014 101 Revision 1.0 Micrel, Inc. KSZ8794CNX Advanced Control Registers (Continued) Address 7 6-0 Name Description Reserved Port Based Priority 2 Ingress Limit Ingress Data Rate Limit For Priority 2 Frames Ingress traffic from this Port is shaped according to the Rate Selection Table in Rate Limit Support section. Mode Default RO 0 R/W 0000000 R/W 0 R/W 0000000 Register 186 (0xBA): Port 1 Priority 3 Ingress Limit Control 4(4) Register 202 (0xCA): Port 2 Priority 3 Ingress Limit Control 4 Register 218 (0xDA): Port 3 Priority 3 Ingress Limit Control 4 Register 234 (0xEA): Reserved Register 250 (0xFA): Port 4 Priority 3 Ingress Limit Control 4 7 Port Based Ingress Rate Limit Enable 6-0 Port Based Priority 3 Ingress Limit Ingress Data Rate Limit For Priorities Setting Valid Trigger port ingress rate limit engine to take effect for all the priority queues according to priority ingress limit control. Note: Any write to this register will trigger port ingress rate limit engine to take effect for all the priority queues according to priority ingress limit control. For the port priority 0-3 ingress rate limit control to take effect, bit [7] of in Register 186, 202, 218, 234 and 250 for Ports 1, 2, 3, 4 and 5, respectively will need to set last after configured bits [6:0] of Port Ingress Limit Control 1-4 registers. Ingress Data Rate Limit For Priority 3 Frames Ingress traffic from this Port is shaped according to the Rate Selection Table in Rate Limit Support section. Note: 4. In the port priority 0-3 ingress rate limit mode, will need to set all related egress ports to two queues or four queues mode. July 24, 2014 102 Revision 1.0 Micrel, Inc. KSZ8794CNX Advanced Control Registers (Continued) Address Name Description Mode Default Register 187 (0xBB): Port 1 Queue 0 Egress Limit Control 1(5) Register 203 (0xCB): Port 2 Queue 0 Egress Limit Control 1 Register 219 (0xDB): Port 3 Queue 0 Egress Limit Control 1 Register 235 (0xEB): Reserved Register 251 (0xFB): Port 4 Queue 0 Egress Limit Control 1 7 7 7 7 7 6-0 6-0 6-0 6-0 6-0 RO 0 R/W 0000000 RO 0 R/W 0000000 Register 188 (0xBC) : Port 1 Queue 1 Egress Limit Control 2(5) Register 204 (0xCC) : Port 2 Queue 1 Egress Limit Control 2 Register 220 (0xDC) : Port 3 Queue 1 Egress Limit Control 2 Register 236 (0xEC) : Reserved Register 252 (0xFC) : Port 4 Queue 1 Egress Limit Control 2 7 6-0 Reserved Port Queue 1 Egress Limit Egress Data Rate Limit For Priority 1 Frames Egress traffic from this priority queue is shaped according to the Rate Selection Table in Rate Limit Support section. In four queues mode, it is low/high priority. In two queues mode, it is high priority. Register 189 (0xBD): Port 1 Queue 2 Egress Limit Control 3(5) Register 205 (0xCD): Port 2 Queue 2 Egress Limit Control 3 Register 221 (0xDD): Port 3 Queue 2 Egress Limit Control 3 Register 237 (0xED): Reserved Register 253 (0xFD): Port 4 Queue 2 Egress Limit Control 3 7 6-0 Reserved Port Queue 2 Egress Limit Egress Data Rate Limit For Priority 2 Frames Egress traffic from this priority queue is shaped according to the Rate Selection Table in Rate Limit Support section. In four queues mode, it is high/low priority. Register 190 (0xBE) : Port 1 Queue 3 Egress Limit Control 4(5) Register 206 (0xCE) : Port 2 Queue 3 Egress Limit Control 4 Register 222 (0xDE) : Port 3 Queue 3 Egress Limit Control 4 Register 238 (0xEE): Reserved Register 254 (0xFE): Port 4 Queue 3 Egress Limit Control 4 July 24, 2014 103 Revision 1.0 Micrel, Inc. KSZ8794CNX Advanced Control Registers (Continued) Address 7 6-0 Name Description Mode Default RO 0 Egress Data Rate Limit For Priority 3 Frames Egress traffic from this priority queue is shaped according to the Rate Selection Table in Rate Limit Support section. In four queues mode, it is highest priority. R/W 0000000 N/A Don't Change. RO 0x80 N/A Don't Change. RO 0x15 N/A Don't Change. RO 0x0C N/A Don't Change. RO 0x32 N/A Don't Change. RO 0x00 Reserved Port Queue 3 Egress Limit Register 191(0xBF): Testing Register 7-0 Reserved Register 207(0xCF): Reserved Control Register 7-0 Reserved Register 223(0xDF): Test Register 2 7-0 Reserved Register 239(0xEF): Test Register 3 7-0 Reserved Register 255(0xFF): Test Register 4 7-0 Reserved Note: 5. In the port queue 0-3 egress rate limit mode, the highest priority get exact rate limit based on the rate select table, other priorities packets rate are based upon the ratio of the Port Control 14/15/16/17 Registers when use more than one egress queue per port. July 24, 2014 104 Revision 1.0 Micrel, Inc. KSZ8794CNX Indirect Register Description Control Indirect Address Contents Direct Address 0x6E, Function Select bits [7-5] = 000 Table_select bits [3-2] = 00 0x000 - 0x01F Static MAC address table entry 0 - 31 Direct Address 0x6E, Function Select bits [7-5] = 000 Table_select bits [3-2] = 01 0x000 - 0x1FF VLAN table bucket 0 - 1023 (4 entry per bucket) Direct Address 0x6E, Function Select bits [7-5] = 000 Table_select bits [3-2] = 10 0x000 - 0x1FF Dynamic MAC address table enty 0 - 1023 Direct Address 0x6E, Function Select bits [7-5] = 000 Table_select bits [3-2] = 11 0x000 - 0x08F, 0x100 - 0x109 0x000 - 0x01F Port 1 MIB Counters 0x020 - 0x03F Port 2 MIB Counters 0x040 - 0x05F Port 3 MIB Counters 0x060 - 0x07F Reserved 0x080 - 0x09F Port 4 MIB Counters 0x100 - 0x113 Total Byte and Dropped MIB Counter Direct Address 0x6E, Function Select bits [7-5] = 001, bits [3-0] = Indirect Address bits [11-8] = MSB Indirect Address = Port indirect register address 0xn {0xn, 6h00} - {0xn, 6h05} Port-based 16-bit EEE Control Registers 0 - 5 n - Port number Use Indirect Byte Register (0xA0) Direct Address 0x6E, Function Select bits [7-5] = 010, bits [3-0] = Indirect Address bits [11-8] = MSB Indirect Address = Port indirect register address 0xn {0xn, 6h00} - {0xn, 6h1F} ACL entry 0 - 15, 6h00 and 6h01 for entry 0, etc. n = Port number Use Indirect Byte Register(0xA0) Direct Address 0x6E, Function Select bits [7-5] = 011, bits [3-0] = Indirect Address bits [11-8] = MSB Indirect Address = Port indirect register address 0xn {0xn, 8h00} - {0xn, 8h4FF} Reserved for the factory Direct Address 0x6E, Function Select bits [7-5] = 100, bits [3-0] = Indirect Address bits [11-8] = MSB Indirect Address = Port indirect register address 0xn {0xn, 8h00} - {0xn, 8h4FF} Configuration Registers, PME etc. n = 0 - Global n = 1 - 3 Port number Use Indirect Byte Register(0xA0) Direct Address 0x6E, Function Select bits [7-5] = 101, bits [3-0] = Indirect Address bits [11-8] = MSB Indirect Address = Port indirect register address 0xn {0xn, 8h00} - {0xn, 8h4FF} Reserved for the factory July 24, 2014 105 Revision 1.0 Micrel, Inc. KSZ8794CNX Static MAC Address Table The KSZ8794CNX incorporates a static and a dynamic address table. When a DA look-up is requested, both tables will be searched to make a packet forwarding decision. When an SA look-up is requested, only the dynamic table is searched for aging, migration, and learning purposes. The static DA look-up result will have precedence over the dynamic DA lookup result. If there are DA matches in both tables, the result from the static table will be used. The static table can only be accessed and controlled by an external SPI master (usually a processor). The entries in the static table will not be aged out by KSZ8794CNX. An external device does all addition, modification and deletion. Note: Register bit assignments are different for static MAC table reads and static MAC table write, as shown in the two tables below. Table 16. Static MAC Address Table Address Name Description Mode Default Format of Static MAC Table for Reads (32 entries) FID Filter VLAN ID, representing one of the 128 active VLANs. RO 0000000 56 Use FID 1 = Use (FID+MAC) to look-up in static table. 0 = Use MAC only to look-up in static table. RO 0 55 Reserved Reserved. RO N/A 54 Override 1 = Override spanning tree "transmit enable = 0" or "receive enable = 0* setting. This bit is used for spanning tree implementation. 0 = No override. RO 0 53 Valid 1 = This entry is valid, the look-up result will be used. 0 = This entry is not valid. RO 0 52-48 Forwarding Ports These 5 bits control the forward Ports. For example, 00001 = Forward to Port 1 00010 = Forward to Port 2 00100 = Forward to Port 3 01000 = Reserved 10000 = Forward to Port 4 00110 = Forward to Port 2 and Port 3 11111 = Broadcasting (excluding the ingress port) RO 00000 47-0 MAC Address (DA) 48-bit MAC address. RO 0x0 63-57 July 24, 2014 106 Revision 1.0 Micrel, Inc. KSZ8794CNX Table 16. Static MAC Address Table (continued) Address Name Description Mode Default Format of Static MAC Table for Writes (32 entries) 62-56 FID Filter VLAN ID, representing one of the 128 active VLANs. W 0000000 Use FID 1 = Use (FID+MAC) to look-up in static table. 0 = Use MAC only to look-up in static table. W 0 54 Override 1 = Override spanning tree "transmit enable = 0" or "receive enable = 0" setting. This bit is used for spanning tree implementation. 0 = No override. W 0 53 Valid 1 = This entry is valid, the look-up result will be used. 0 = This entry is not valid. W 0 52-48 Forwarding Ports These 5 bits control the forward ports. For example, 00001 = Forward to Port 1 00010 = Forward to Port 2 00100 = Forward to Port 3 01000 = Reserved 10000 = Forward to Port 4 00110 = Forward to Port 2 and Port 3 11111 = Broadcasting (excluding the ingress port) W 00000 47-0 MAC Address (DA) 48-bit MAC address. W 0x0 55 Examples: (1) Static Address Table Read (read the 2nd entry) Write to Register 110 with 0x10 (read static table selected) Write to Register 111 with 0x1 (trigger the read operation) Then Read Register 113 (63:56) Read Register 114 (55:48) Read Register 115 (47:40) Read Register 116 (39:32) Read Register 117 (31:24) Read Register 118 (23:16) Read Register 119 (15:8) Read Register 120 (7:0) (2) Static Address Table Write (write the 8th entry) Write Register 113 (62:56) Write Register 114 (55:48) Write Register 115 (47:40) Write Register 116 (39:32) Write Register 117 (31:24) Write Register 118 (23:16) Write Register 119 (15:8) Write Register 120 (7:0) Write to Register 110 with 0x00 (write static table selected) Write to Register 111 with 0x7 (trigger the write operation) July 24, 2014 107 Revision 1.0 Micrel, Inc. KSZ8794CNX VLAN Table The VLAN table is used for VLAN table look-up. If 802.1q VLAN mode is enabled (Register 5 bit [7] = 1), this table is used to retrieve VLAN information that is associated with the ingress packet. There are three fields for FID (filter ID), Valid, and VLAN membership in the VLAN table. The three fields must be initialized before the table is used. There is no VID field because 4096 VIDs are used as a dedicated memory address index into a 1024x52-bit memory space. Each entry has four VLANs. Each VLAN has 13 bits. Four VLANs need 52 bits. There are a total of 1024 entries to support a total of 4096 VLAN IDs by using dedicated memory address and data bits. Refer to Table 17 for details. FID has 7 bits to support 128 active VLANs. Table 17. VLAN Table Address Name Description Mode Initial Value suggestion Format of Static VLAN Table (Support Max 4096 VLAN ID entries and 128 Active VLANs) 12 11-7 6-0 Valid 1 = The entry is valid. 0 = Entry is invalid. R/W 0 Membership Specifies which Ports are members of the VLAN. If a DA look-up fails (no match in both static and dynamic tables), the packet associated with this VLAN will be forwarded to Ports specified in this field. E.g., 1x001 means Ports 4 and 1 are in this VLAN, x is bit 10 which is reserved in the KSZ8794CNX. R/W 11111 FID Filter ID. The KSZ8794CNX supports 128 active VLANs represented by these seven bit fields. FID is the mapped ID. If 802.1q VLAN is enabled, the look-up will be based on FID+DA and FID+SA. R/W 0 If 802.1q VLAN mode is enabled, the KSZ8794CNX assigns a VID to every ingress packet when the packet is untagged or tagged with a null VID, the packet is assigned with the default Port VID of the ingress Port. If the packet is tagged with non-null VID, the VID in the tag is used. The look-up process starts from the VLAN table look-up based on VID number with its dedicated memory address and data bits. If the entry is not valid in the VLAN table, the packet is dropped and no address learning occurs. If the entry is valid, the FID is retrieved. The FID+DA and FID+SA lookups in MAC tables are performed. The FID+DA look-up determines the forwarding Ports. If FID+DA fails for look-up in the MAC table, the packet is broadcast to all the members or specified members (excluding the ingress Port) based on the VLAN table. If FID+SA fails, the FID+SA is learned. To communicate between different active VLANs, set the same FID; otherwise set a different FID. The VLAN table configuration is organized as 1024 VLAN sets, each VLAN set consists of four VLAN entries, to support up to 4096 VLAN entries. Each VLAN set has total 60 bits and 3 reversed bits are inserted between entries, actually 52 bits are used for VLAN set which should be read or written at the same time specified by the indirect address. The VLAN entries in the VLAN set are mapped to indirect data registers as follow: * Entry0[12:0] maps to the VLAN set bits [12:0] {Register 119[4:0], Register 120[7:0]} * Entry1[12:0] maps to the VLAN set bits[28:16] {Register 117[4:0], Register 118[7:0]} * Entry2[12:0] maps to the VLAN set bits[44:32] {Register 115[4:0], Register 116[7:0]} * Entry3[12:0] maps to the VLAN set bits[60:48] {Register 113[4:0], Register 114[7:0]} In order to read one VLAN entry, the VLAN set is read first and the specific VLAN entry information can be extracted. To update any VLAN entry, the VLAN set is read first then only the desired VLAN entry is updated and the whole VLAN set is written back. The FID in the VLAN table is 7 bits, so the VLAN table supports unique 128 flow VLAN groups. Each VLAN set address is 10 bits long (Maximum is 1024) in the Indirect Address Register 110 and 111, the bits [9:8] of VLAN set address is at bits [1:0] of Register 110, and the bits [7:0] of VLAN set address is at bits [7:0] of Register 111. Each Write and Read can access up to four consecutive VLAN entries. July 24, 2014 108 Revision 1.0 Micrel, Inc. KSZ8794CNX Examples: 1. VLAN Table Read (read the VID = 2 entry) Write the indirect control and address registers first Write to Register 110 (0x6E) with 0x14 (read VLAN table selected) Write to Register 111 (0x6F) with 0x0 (trigger the read operation for VID = 0, 1, 2, 3 entries) Then read the Indirect Data Registers bits [38:26] for VID = 2 entry Read Register 115 (0x73), (Register 115 [4:0] are bits [12:8] of VLAN VID = 2 entry) Read Register 116 (0x74), (Register 116 [7:0] are bits [7:0] of VLAN VID = 2 entry) 2. VLAN Table Write (write the VID = 10 entry) Read the VLAN set that contains VID = 8, 9, 10, 11. Write to Register 110 (0x6E) with 0x14 (read VLAN table selected) Write to Register 111 (0x6F) with 0x02 (trigger the read operation and VID = 8, 9, 10, 11 indirect address) Read the VLAN set first by the Indirect Data Registers 113, 114, 115, 116, 117, 118, 119, 120. Modify the Indirect Data Registers bits [44:32] by the Register 115 bit[4-0] and Register 116 bits [7:0] as follows: Write to Register 115 (0x73), (Register115 [4:0] are bits [12:8} of VLAN VID = 10 entry) Write to Register 116 (0x74), (Register116 [7:0] are bits [7:0] of VLAN VID = 10 entry) Then write the indirect control and address Registers Write to Register 110 (0x6E) with 0x04 (write VLAN table selected) Write to Register 111 (0x6F) with 0x02 (trigger the write operation and VID = 8, 9, 10, 11 indirect address) The following table shows the relationship of the indirect address/data registers and VLAN ID. Table 18. VLAN ID and Indirect Registers Indirect Address high/low bit[9-0] for VLAN sets Indirect Data Registers Bits for each VLAN entry VID Numbers VID bit[12-2] in VLAN Tag VID bit[1-0] in VLAN Tag 0 Bits [12:0] 0 0 0 0 Bits [28:16] 1 0 1 0 Bits [44:32] 2 0 2 0 Bits [60:48] 3 0 3 1 Bits [12:0] 4 1 0 1 Bits [28:16] 5 1 1 1 Bits [44:32] 6 1 2 1 Bits [60:48] 7 1 3 2 Bits [12:0] 8 2 0 2 Bits [28:16] 9 2 1 2 Bits [44:32] 10 2 2 2 Bits [60:48] 11 2 3 : : : : : : : : : : : : : : : 1023 Bits [12:0] 4092 1023 0 1023 Bits [28:16] 4093 1023 1 1023 Bits [44:32] 4094 1023 2 1023 Bits [60:48] 4095 1023 3 July 24, 2014 109 Revision 1.0 Micrel, Inc. KSZ8794CNX Dynamic MAC Address Table This table is read only. Table 19. Dynamic MAC Address Table Address Name Description Mode Default Format of Dynamic MAC Address Table (1K entries) MAC Empty 1 = There is no valid entry in the table. 0 = There are valid entries in the table. RO 1 70-61 No of Valid Entries Indicates how many valid entries in the table. 0x3ff means 1K entries 0x1 and bit [71] = 0: means 2 entries 0x0 and bit [71]= 0: means 1 entry 0x0 and bit [71] = 1: means 0 entry RO 0 60-59 Time Stamp 2-bit counters for internal aging RO 58-56 Source Port The source Port where FID+MAC is learned. 000 = Port 1 001 = Port 2 010 = Port 3 011 = Reserved 100 = Port 4 RO 55 Data Ready 1 = The entry is not ready, retry until this bit is set to 0. 0 = The entry is ready. RO 54-48 FID Filter ID. RO 0x0 47-0 MAC Address 48-bit MAC address. RO 0x0 71 July 24, 2014 110 0x0 Revision 1.0 Micrel, Inc. KSZ8794CNX Examples: (1) Dynamic MAC Address Table Read (read the 1st entry), and retrieve the MAC table size Write to Register 110 with 0x18 (read dynamic table selected) Write to Register 111 with 0x0 (trigger the read operation) and then Read Register 112 (71:64) Read Register 113 (63:56); // the above two registers show # of entries Read Register 114 (55:48) // if bit [55] is 1, restart (reread) from this register Read Register 115 (47:40) Read Register 116 (39:32) Read Register 117 (31:24) Read Register 118 (23:16) Read Register 119 (15:8) Read Register 120 (7:0) th (2) Dynamic MAC Address Table Read (read the 257 entry), without retrieving # of entries information Write to Register 110 with 0x19 (read dynamic table selected) Write to Register 111 with 0x1 (trigger the read operation) and then Read Register 112 (71:64) Read Register 113 (63:56) Read Register 114 (55:48) // if bit [55] is 1, restart (reread) from this register Read Register 115 (47:40) Read Register 116 (39:32) Read Register 117 (31:24) Read Register 118 (23:16) Read Register 119 (15:8) Read Register 120 (7:0) July 24, 2014 111 Revision 1.0 Micrel, Inc. KSZ8794CNX PME Indirect Registers The EEE registers are provided on global and per port basis. These registers are read/write using indirect memory access as below: Table 20. PME Indirect Registers Address Name Description Mode Default RO All `0' Global PME Control Register Reg. 110 (0x6E) bits [7:5]=100 for PME, Reg.110 bits [3:0]=0x0 for the indirect global register, Reg. 111 (0x6F) bits [7:0]= Offset to access the Indirect Byte Register 0xA0. Offset: 0x00 (bits [31:24]), 0x01 (bits [23:16]), 0x02 (bit [15:8]), 0x03 (bits [7:0]). Location: (100 PME) -> {0x0, offset} ->0xA0 holds the data. 31-2 Reserved 1 PME Output Enable 1= PME output pin is enabled. 0= PME output pin is disabled. R/W 0 0 PME Output Polarity 1= PME output pin is active high. 0= PME output pin is active low. R/W 0 Port PME Control Status Register Reg. 110 (0x6E) bits [7:5]=100 for PME, Reg. 110 bits [3:0]=0xn for the Indirect Port Register (n=1, 2 and 3). Reg. 111 (0x6F) bits [7:0]= Offset to access the Indirect Byte Register 0xA0. Offset: 0x00 (bits [31:24]), 0x01 (bits [23:16]), 0x02 (bits [5:8]), 0x03 (bits [7:0]). Location: (100 PME) -> {0xn, offset} ->0xA0 holds the data. 31-3 Reserved RO All `0' 2 Magic Packet Detect 1 = Magic packet is detected at any port (write 1 to clear). 0 = No magic packet is detected. R/W W1C 0 1 Link Up Detect 1 = Link up is detected at any port (write 1 to clear). 0 = No link-up is detected. R/W W1C 0 0 Energy Detect 1 = Energy is detected at any port (write 1 to clear). 0 = No energy is detected. R/W W1C 0 RO All `0' Port PME Control Mask Register Reg. 110 (0x6E) bits [7:5]=100 for PME, Reg. 110 bits [3:0]=0xn for port (n=1, 2 and 3). Reg. 111 (0x6F) bits [7:0]= Offset to access the Indirect Byte Register 0xA0. Offset: 0x04 (bits [31:24]), 0x05 (bits [23:16]), 0x06 (bits [15:8]), 0x07 (bits [7:0]). Location: (100 PME) -> {0xn, offset} ->0xA0 holds the data. 31-3 2 1 0 Reserved Magic Packet Detect Enable 1 = The PME pin will be asserted when a magic packet is detected at host QMU. 0 = The PME pin will not be asserted by the magic packet detection. R/W 0 Link Up Detect Enable 1 = The PME pin will be asserted when a linkup is detected at any port. 0 = The PME pin will not be asserted by the linkup detection. R/W 0 Energy Detect Enable 1 = The PME pin will be asserted when energy on line is detected at any port. 0 = The PME pin will not be asserted by the energy detection. R/W 0 July 24, 2014 112 Revision 1.0 Micrel, Inc. KSZ8794CNX Programming Examples: Read Operation 1. Use the Indirect Access Control Register to select register to be read, to read Global PME Control Register. Write 0x90 to the Register 110 (0x6E) // PME selected and read operation, and 4 MSBs of Port number (Register 110 bits [3:0]) = 0 for the Global PME Register. 2. Write 0x03 to the Register 111 (0x6F) // trigger the read operation for bits [7:0] of the Global PME Control Register. 3. Read the Indirect Byte Register 160 (0xA0) // Get the value of the Global PME Control Register. Write Operation 1. Write 0x80 to the Register 110 (0x6E) //PME selected and write operation, and 4 MSBs of Port number = 0 for the Global PME Register. 2. Write 0x03 to the Register 111 (0x6F) // select write the bits [7:0] of the Global PME Control Address Register. 3. Write new value to the Indirect Byte Register 160 bits [7:0] (0xA0) //Write value to the Global PME Control Register of the Indirect PME Data Register by the assigned the indirect data register address. July 24, 2014 113 Revision 1.0 Micrel, Inc. KSZ8794CNX ACL Rule Table and ACL Indirect Registers ACL Register and Programming Model The ACL registers are accessible by the microcontroller through a serial interface. The per-port register set is accessed through indirect addressing mechanism. The ACL entries are stored in the format shown in the following figure. Each ACL rule list table can input up to 16 entries per port, total 4 ACL rule list tables can be set for 4 ports. Figure 13. ACL Table Access To update any port-based ACL registers, it is suggested to execute a read modify write sequence for each 128-bit (112 are used) entry addressed by the Indirect Address Register to ensure the integrity of control content. Minimum two indirect control writes and two indirect control reads are needed for each ACL entry read access (indirect data read shall follow), and minimum one indirect control read and three indirect control writes are required for each ACL entry write access. Each 112-bit Port-based ACL word entry (ACL Word) is accomplished through a sequence of the Indirect Access Control 0 Registers 110 (0x6E) accesses by specifying the bits[3:0] 4-bit Port number (Indirect address [11:8]) and 8-bit indirect register address (indirect address[7:0]) in the Indirect Access Control 1 Register 111 (0x6F). The address numbers 0x000x0d are used to specify the byte location of each entry (see above figure), address 0x00 indicates the byte 15 (MSB) of each 128-bit entry, address 0x01 indicates the byte 14 etc., bytes at address 0x0E and 0x0F are reserved for the future. Address 0x10 & 0x11 hold bit-wise Byte Enable for each entry. Address 0x12 is used as control and status register. The format of these registers is defined in the following section. July 24, 2014 114 Revision 1.0 Micrel, Inc. KSZ8794CNX ACL Indirect Registers This table is used to implement ACL mode selection and filtering per port. Table 21. ACL Indirect Registers for 14 Bytes ACL Rules Address Name Description Mode Default RO 0x0 R/W 0000 RO 00 R/W 00 Port_ACL_0 ACL Port Register 0 (0x00) Reg. 110 (0x6E) bits [7:5] = 010 for ACL, Reg. 110 bits [3:0] = 0xn for Port 1, 2, 3 and 4. Reg. 111 (0x6F) bits [7:0] = Offset 0x00 to access the Indirect Byte Register 0xA0. Location: (010 ACL) -> {0xn, offset} ->0xA0 holds the data. Processing Field 7-4 3-0 Reserved FRN[3:0] First Rule Number This is for the first rule number of the Rule Set. There are total 16 entries per port in ACL rule table. Each single rule can be set with other rule for a rule set by the ACL port Register 12 (0x0c) and Register 13 (0x0d). Regardless single rule or rule set, have to assign an entry for using which Action Field by FRN[3:0]. Port_ACL_1 ACL Port Register 1 (0x01) Reg. 110 (0x6E) bits [7:5] = 010 for ACL, Reg. 110 bits [3:0] = 0xn for Port 1, 2, 3 and 4. Reg. 111(0x6F) bits [7:0] = Offset 0x01 to access the Indirect Byte Register 0xA0. Location: (010 ACL) -> {0xn, offset} ->0xA0 holds the data. Matching Fields 7-6 5-4 Reserved MD[1:0] July 24, 2014 MODE 00 = Disable the current rule list, no action taken 01 = Qualify rules for layer 2 MAC header filtering 10 = Is used for layer 3 IP address filtering 11 = Performs layer 4 TCP port number/protocol filtering 115 Revision 1.0 Micrel, Inc. KSZ8794CNX Table 21. ACL Indirect Registers for 14 Bytes ACL Rules (continued Address Mode Default ENB[1:0] ENABLE When MD=01: 00 = The 11 bits from PM, P, REP, MM in action field specify a count value for packets matching MAC Address and TYPE in Matching Field. The count unit is defined in FORWARD field bit [4]; Bit [4] = 0, usec will be used. Bit [4] = 1, msec will apply. The FORWAED field bit [3] determines the algorithm used to generate interrupt when counter terminated. Bit [3] = 0, an 11-bit counter will be loaded with the count value from the list and start counting down every unit time. An interrupt will be generated when expires, i.e., next qualified packet has not been received within the period specified by the value. Bit [3] = 1, the counter is incremented every matched packet received and the interrupt is generated while terminal count reached, the count resets thereafter. 01 = MAC address bit field is participating in test. 10 = MAC TYPE bit field is used for test. 11 = Both MAC address and TYPE are tested against these bit fields in the list. When MD=10: 00 = Reserved. 01 = IP address and mask or IP protocol is enabled to be tested accordingly. 10 = SA and DA are compared; the drop/forward decision is based on the E/Q bit setting. 11 = Reserved When MD=11: 00 = Protocol comparison is enabled. 01 = TCP/UDP address comparison is selected. 10 = It is same with `01' 11 = The sequence number of TCP is compared. R/W 00 1 S_D Source/Destination Address 0 = DA is used to compare. 1 = SA is used to compare R/W 0 0 EQ Compare Equal 0 = Match if they are not equal. 1 = Match if they are equal. R/W 0 3-2 Name Description Port_ACL_2 ACL Port Register 2 (0x02) Reg. 110 (0x6E) bits [7:5] = 010 for ACL, Reg. 110 bits[3:0 ] = 0xn for Port 1, 2, 3 and 4. Reg. 111 (0x6F) bits [7:0] = Offset 0x02 to access the Indirect Byte Register 0xA0. Location: (010 ACL) -> {0xn, offset} ->0xA0 holds the data. Matching Fields for Layer 2 July 24, 2014 116 Revision 1.0 Micrel, Inc. KSZ8794CNX Table 21. ACL Indirect Registers for 14 Bytes ACL Rules (continued) Address 7-0 Name MAC_ADDR[47:40] Description MAC Address Mode Default R/W 00000000 R/W 00000000 R/W 00000000 R/W 00000000 R/W 00000000 R/W 00000000 R/W 00000000 Port_ACL_3 ACL Port Register 3 (0x03) Reg. 110 (0x6E) bits [7:5] = 010 for ACL, Reg. 110 bits [3:0] = 0xn for Port 1, 2, 3 and 4. Reg. 111 (0x6F) bits [7:0] = Offset 0x03 to access the Indirect Byte Register 0xA0. Location: (010 ACL) -> {0xn, offset} ->0xA0 holds the data. Matching Fields for Layer 2 7-0 MAC_ADDR[39:32] MAC Address Port_ACL_4 ACL Port Register 4 (0x04) Reg. 110 (0x6E) bits [7:5] = 010 for ACL, Reg. 110 bits [3:0] = 0xn for Port 1, 2, 3 and 4. Reg. 111 (0x6F) bits [7:0] = Offset 0x04 to access the Indirect Byte Register 0xA0. Location: (010 ACL) -> {0xn, offset} ->0xA0 holds the data. Matching Fields for Layer 2 7-0 MAC_ADDR[31:24] MAC Address ACL Port Register 5 (0x05) Reg. 110 (0x6E) bits [7:5] = 010 for ACL, Reg. 110 bits [3:0] = 0xn for Port 1, 2, 3 and 4. Reg. 111 (0x6F) bits [7:0] = Offset 0x05 to access the Indirect Byte Register 0xA0. Location: (010 ACL) -> {0xn, offset} ->0xA0 holds the data. Matching Fields for Layer 2 7-0 MAC_ADDR[23:16] MAC Address Port_ACL_6 ACL Port Register 6 (0x06) Reg. 110 (0x6E) bits [7:5] = 010 for ACL, Reg. 110 bits [3:0] = 0xn for Port 1, 2, 3 and 4. Reg. 111 (0x6F) bits [7:0] = Offset 0x06 to access the Indirect Byte Register 0xA0. Location: (010 ACL) -> {0xn, offset} ->0xA0 holds the data. Matching Fields for Layer 2 7-0 MAC_ADDR[15:8] MAC Address Port_ACL_7 ACL Port Register 7 (0x07) Reg. 110 (0x6E) bits [7:5] = 010 for ACL, Reg. 110 bits [3:0] = 0xn for Port 1, 2, 3 and 4. Reg. 111 (0x6F) bits [7:0] = Offset 0x07 to access the Indirect Byte Register 0xA0. Location: (010 ACL) -> {0xn, offset} ->0xA0 holds the data. Matching Fields for Layer 4 7-0 MAC_ADDR[7:0] MAC Address Port_ACL_8 ACL Port Register 8 (0x08) Reg. 110 (0x6E) bits [7:5] = 010 for ACL, Reg. 110 bits [3:0] = 0xn for Port 1, 2, 3 and 4. Reg. 111 (0x6F) bits [7:0] = Offset 0x08 to access the Indirect Byte Register 0xA0. Location: (010 ACL) -> {0xn, offset} ->0xA0 holds the data. 7-0 TYPE[15:8] July 24, 2014 Ether Type 117 Revision 1.0 Micrel, Inc. KSZ8794CNX Table 21. ACL Indirect Registers for 14 Bytes ACL Rules (continued) Address Name Description Mode Default R/W 00000000 Port_ACL_9 ACL Port Register 9 (0x09) Reg. 110 (0x6E) bits [7:5] = 010 for ACL, Reg. 110 bits [3:0] = 0xn for Port 1, 2, 3 and 4. Reg. 111 (0x6F) bits [7:0] = Offset 0x09 to access the Indirect Byte Register 0xA0. Location: (010 ACL) -> {0xn, offset} ->0xA0 holds the data. 7-0 FLAG[7:0] TCP FLAG Note: Layer 2, layer 3 and layer 4 in matching field should be in different entries. Same layer should be in same entry. See ACL Format figure for the detail. Port_ACL_A ACL Port Register 10 (0x0A) Reg. 110 (0x6E) bits [7:5] = 010 for ACL, Reg. 110 bits [3:0] = 0xn for Port 1, 2, 3 and 4. Reg. 111 (0x6F) bits [7:0] = Offset 0x0A to access the Indirect Byte Register 0xA0. Location: (010 ACL) -> {0xn, offset} ->0xA0 holds the data. Action Field 7-6 PM[1:0] 5-3 P[2:0] Priority Mode 00 = No priority is selected; the priority determined by QoS/Classification is used in the tagged packets. 01 = Priority in P [2:0] bits field is used if it is greater than QoS result in the 3-bit priority field of the tagged packets received. 10 = Priority in P [2:0] bits field is used if it is smaller than QoS result in the 3-bit priority field of the tagged packets received. 11 = P [2:0] bits field will replace the 3-bit priority field of the tagged packets received. R/W 00 R/W 000 RPE Remark Priority Enable 0 = No remarking is necessary. 1 = VLAN priority bits in the packets are replaced by RP [2:1] bits field below in the list. R/W 0 RP[2:1] Remark Priority 00 = Priority 0 01 = Priority 1 10 = Priority 2 11 = Priority 3 R/W 00 Priority 2 1-0 Note: The 3-bit priority value to be used depends on PM [1:0] setting in bits [7:6]. Port_ACL_B ACL Port Register 11 (0x0B) Reg. 110 (0x6E) bits [7:5] = 010 for ACL, Reg. 110 bits [3:0] = 0xn for Port 1, 2, 3 and 4. Reg. 111 (0x6F) bits [7:0] = Offset 0x0B to access the Indirect Byte Register 0xA0. Location: (010 ACL) -> {0xn, offset} ->0xA0 holds the data. Action Field July 24, 2014 118 Revision 1.0 Micrel, Inc. KSZ8794CNX Table 21. ACL Indirect Registers for 14 Bytes ACL Rules (continued) Address 7 6-5 4-0 Name Description RP[0] MM[1:0] FORWARD[4:0] Mode Default Remark Priority R/W 0 Map Mode 00 = No forwarding remapping is necessary. Don't use the forwarding map in FORWARD field, use the forwarding map from the look-up table only. 01 = The forwarding map in FORWARD field is OR'ed with the forwarding map from the look-up table. 10 = The forwarding map in FORWARD field is AND'ed with the forwarding map from the look-up table. 11 = The forwarding map in FORWARD field replaces the forwarding map from the look-up table. R/W 00 Port Map Each bit indicates forwarding decision of one port. Bit [0] = Port 1 Bit [1] = Port 2 Bit [2] = Port 3 Bit [3] = Reserved Bit [4] = Port 4 When MD=01 and ENB=00, Bit [4] is used as count unit. 0 = us. 1 = ms. Bit [3] is used to select count modes: 0 = count down in the 11-bit counter from an assigned. value in the Action field PM, P, RPE, RP and MM, an interrupt will be generated when expired. 1= count up in the 11-bit counter for every matched packet received up to reach an assigned value in the Action field PM, P, RPE, RP and MM, and then an interrupt will be generated. R/W Note: See ENB field description for detail. Port_ACL_C ACL Port Register 12 (0x0C) Reg. 110 (0x6E) bits [7:5] = 010 for ACL, Reg. 110 bits [3:0] = 0xn for Port 1, 2, 3 and 4. Reg. 111 (0x6F) bits [7:0] = Offset 0x0C to access the Indirect Byte Register 0xA0. Location: (010 ACL) -> {0xn, offset} ->0xA0 holds the data. Processing Field 7-0 RULESET[15:8] July 24, 2014 Rule Set Each bit indicates this entry in bits 0-15 16 entries of the rule list to be assigned for the rule set to be used in the rules cascade per port. 119 R/W 00000000 Revision 1.0 Micrel, Inc. KSZ8794CNX Table 21. ACL Indirect Registers for 14 Bytes ACL Rules (continued) Address Name Description Mode Default R/W 00000000 Port_ACL_D ACL Port Register 13 (0x0D) Reg. 110 (0x6E) bits [7:5] = 010 for ACL, Reg. 110 bits [3:0] = 0xn for Port 1, 2, 3 and 4. Reg. 111 (0x6F) bits [7:0] = Offset 0x0D to access the Indirect Byte Register 0xA0. Location: (010 ACL) -> {0xn, offset} ->0xA0 holds the data. Processing Field 7-0 RULESET[7:0] Rule Set Each bit indicates this entry in bits 0 to 15, total 16 entries of the rule list can be assigned for the rule set to be used in the rules cascade per port. Table 22. Temporal storage for 14 Bytes ACL Rules Address Name Description Mode Default RO 00 R/W 0 R/W 0x00 Port_ACL_BYTE_ENB_MSB ACL Port Register 14 (0x10) Reg. 110 (0x6E) bits [7:5] = 010 for ACL, Reg. 110 bits [3:0] = 0xn for Port 1, 2 ,3 and 4. Reg. 111 (0x6F) bits [7:0] = Offset 0x10 to access the Indirect Byte Register 0xA0. Location: (010 ACL) -> {0xn, offset} ->0xA0 holds the data. 7-6 5-0 Reserved BYTE_ENB[13:8] Byte Enable in ACL table; 14-Byte per entry 1 = Byte is selected for read/write 0 = Byte is not selected Bit [0] of BYTE_ENB[13:0] is for byte address 0x0D in ACL table entry, Bit [1] of BYTE_ENB[13:0] is for byte address 0x0C in ACL table entry, etc. Bit [13] of BYTE_ENB[13:0] is for byte address 0x00 in ACL table entry. Port_ACL_ BYTE_ENB_LSB ACL Port Register 15 (0x11) Reg. 110 (0x6E) bits [7:5] = 010 for ACL, Reg. 110 bits [3:0] = 0xn for Port 1, 2, 3 and 4. Reg. 111 (0x6F) bits [7:0] = Offset 0x11 to access the Indirect Byte Register 0xA0. Location: (010 ACL) -> {0xn, offset} ->0xA0 holds the data. 7-0 BYTE_ENB[7:0] July 24, 2014 Byte Enable in ACL table; 14-Byte per entry 1 = Byte is selected for read/write 0 = Byte is not selected Bit [0] of BYTE_ENB[13:0] is for byte address 0x0D in ACL table entry, Bit [1] of BYTE_ENB[13:0] is for byte address 0x0C in ACL table entry, etc. Bit [13] of BYTE_ENB[13:0] is for byte address 0x00 in ACL table entry. 120 Revision 1.0 Micrel, Inc. KSZ8794CNX Table 23. ACL Read and Write Control Address Name Description Mode Default Port_ACL_ACCESS_CONTROL1 ACL Port Register 16 (0x12) Reg. 110 (0x6E) bits [7:5] = 010 for ACL, Reg. 110 bits [3:0] = 0xn for Port 1, 2, 3 and 4. Reg. 111 (0x6F) bits [7:0] = Offset 0x12 to access the Indirect Byte Register 0xA0. Location: (010 ACL) -> {0xn, offset} ->0xA0 holds the data. 7 Reserved N/A Don't Change RO 0 6 WRITE_STATUS Write Operation Status 1 = Write completed 0 = Write is in progress RO 1 5 READ_STATUS Read Operation Status 1 = Read completed 0 = Read is in progress RO 1 4 WRITE_READ Request Type 1 = Write 0 = Read R/W 0 ACL_ENTRY_ADDRESS ACL Entry Address 0000= entry 0. 0001= entry 1. ..... 1111= entry 15. R/W 0000 RO 0000000 R/W 0 3-0 Port_ACL_ ACCESS_CONTROL2 ACL Port Register 17 (0x13) Reg. 110 (0x6E) bits [7:5] = 010 for ACL, Reg. 110 bits [3:0] = 0xn for Port 1, 2, 3 and 4. Reg. 111 (0x6F) bits [7:0] = Offset 0x13 to access the Indirect Byte Register 0xA0. Location: (010 ACL) -> {0xn, offset} ->0xA0 holds the data. 7-1 0 Reserved Force DLR Miss N/A Don't Change 1 = DLR filtering uses single ACL entry. DLR packet matching the ACL entry will be considered as MISS. 0 = DLR filtering uses multiple ACL entries. DLR packet matching the rule set for DLR packet will be considered as HIT. Note: DLR means Device Level Redundancy. July 24, 2014 121 Revision 1.0 Micrel, Inc. KSZ8794CNX The ACL registers can be programmed using the read/write examples below. Read Operation Use the Indirect Access Control Register to select register to be read. To read Entry0 that is 1st entry of Port 1: Write 0x41 to Register 110 (0x6E) // select ACL and write to Port 1 (Port 2, 3 and 4 are 0x42, 0x43 and 0x45) Write 0x10 to Register 111 (0x6F) // trigger the write operation for Port 1 in the ACL Port Register 14 (Byte Enable MSB register) address. Write 0x3F into the Indirect Byte Register 160 (0xA0) for MSB of Byte Enable word. Write 0x41 to Register 110 (0x6E) // select write to Port 1. Write 0x11 to Register 111 (0x6F) // trigger the write operation for Port 1 in the ACL Port Register 15 (Byte Enable LSB Register) address. (The above 2 may be part of burst). Write 0xFF into the Indirect Byte Register 160 (0xA0) for LSB of Byte Enable word. (The above steps set Byte Enable Register to select all bytes in ACL word from 0x00-0x0d in ACL table entry) Write 0x41 to Register 110 (0x6E) //select ACL and write operations to Port 1. Write 0x12 to Register 111 (0x6F) //Write ACL read/write control register address 0x12 to the indirect address in Register 111 to trigger the read operation for Port 1 in the ACL Port Register 16 (ACL Access Control Register) to read entry 0. Write 0x00 into the Indirect Byte Register 160 (0xA0)//ACL Port Register 16 (0x12) bit [4] = 0 to read ACL and bits [3:0] = 0x0 for entry 0.(The above steps set ACL control register to read ACL entry word 0). Write 0x51 to Register 110 (0x6E) //select ACL and read to Port 1 (Port 2, 3 and 4 are 0x52, 0x53 and 0x55). Write 0x12 to Register 111 (0x6F) //trigger the read operation for Port 1 in the ACL Port Register16 (ACL Access Control 1). Read the Indirect Byte Register 160 (0xA0) to get data (If bit [5] is set, the read completes in the ACL port Register 16 (0x12) and go to next step. Otherwise, repeat the above polling step). Write 0x51 to Register 110 (0x6E) // select read to Port 1. Write 0x00 to Register 111 (0x6F) // trigger the read/burst read operation(s) based on the Byte Enable Register setting by the Port 1 ACL access Register 0 (0x00).Read/Burst read the Indirect Byte Register 160 (0xA0) // to get data of ACL entry word 0, write 0x00 to 0x0D indirect address and read Register 160 (0xA0) after each byte address write to Register 111 (0x6F). Write Operation Use the Indirect Access Control Register to select register to be written. To write even byte number of 15th entry of Port 4: Write 0x55 to Register 110 (0x6E) // select ACL and read to Port 4. Write 0x12 to Register 111 (0x6F) // trigger the read operation for Port 4 ACL Access Control Register read. Read the Indirect Byte Register 160 (0xA0) to get data (If bit [6] is set, the previous write completes and go to next step. Otherwise, repeat the above polling step). Write 0x45 to Register 110 (0x6E) // select ACL and write to Port 4. Write 0x00 to Register 111 (0x6F) //set offset address for Port 4 ACL Port Register 0. Write/Burst write the Indirect Byte Register 160 (0xA0) for ACL Port Register 0, 1, 2, ...,13 from 0x00 to 0x0D) (Write or Burst write even bytes of Port 4 ACL access Registers 0, 1, ..., 13 to holding buffer). Write 0x45 to Register 110 (0x6E) // select ACL and write to Port 4. Write 0x10 to Register 111 (0x6F) // trigger the write operation for Port 4 in the ACL Port Register 14 (Byte Enable MSB register). Write 0x15 into the Indirect Byte Register 160 (0xA0) for MSB of Byte Enable word to enable odd bytes address 0x01, 0x03 and 0x05. Write 0x45 to Register 110 (0x6E) // select write to Port 4. July 24, 2014 122 Revision 1.0 Micrel, Inc. KSZ8794CNX Write 0x11 to Register 111 (0x6F) // trigger the write operation for Port 4 in the ACL Port Register 15 (Byte Enable LSB register). Write 0x55 into the Indirect Byte Register 160 (0xA0) for LSB of Byte Enable word to enable odd bytes address 0x07, 0x09, 0x0B and 0x0D.(The above steps set Byte Enable Register to select odd address bytes in ACL word.) Write 0x45 to Register 110 (0x6E) // select write to Port 4. Write 0x12 to Register 111 (0x6F) // write the port ACL access control register address (0x12) to the Indirect Address Register 111 for setting the write operation to Port 4 in the ACL Port Register 16 to write entry 15 bytes 1, 3, 5...,13. Write 0x1F into the Indirect Byte Register 160 (0xA0) // for the write operation to 15th entry in the ACL Port Register 16 (0x12) bit4=1 to write ACL, bits [3:0] = 0xF to write entry 15. (The above steps set ACL Control Register to write ACL entry word 15 from holding buffer.) The bit arrangement of above example assumes layer 2 rule of MODE = 01 in ACL Port Register 1 (0x01), refer to ACL format for MODE = 10 and 11. July 24, 2014 123 Revision 1.0 Micrel, Inc. KSZ8794CNX EEE Indirect Registers The EEE function is for the copper ports only. The EEE registers are provided on global and per port basis. These registers are read/write using indirect memory access as below: LPI means Low Power Idle. EEE Global Registers Address Name Description Mode Default EEE Global Register 0 Global EEE QM Buffer Control Register Reg. 110 (0x6E) bits [7:5] = 001 for EEE, Reg. 110 bits [3:0] = 0x0 for the indirect global register. Reg. 111 (0x6F) bits [7:0] = Offset to access the Indirect Byte Register 0xA0. Offset: 0x30 (bits [15:8]), 0x31 (bits [7:0]). Location: (001 EEE) -> {0x0, offset} ->0xA0 holds the data. 15-8 7 6-0 Reserved N/A Don't Change RO 0x40 LPI Terminated By Input Traffic Enable 1 = LPI request will be stopped if input traffic is detected. 0 = LPI request won't be stopped by input traffic. R/W 0 Reserved N/A Don't Change RO 0x10 R/W 0x10 EEE Global Register 1 Global Empty TXQ to LPI wait time control Register Reg. 110 (0x6E) bits [7:5] = 001 for EEE, Reg. 110 bits [3:0] = 0x0 for the indirect global register, Reg. 111 (0x6F) bits [7:0] = Offset to access the Indirect Byte Register 0xA0. Offset: 0x32 (bits [15:8]), 0x33 (bits [7:0]) Location: (001 EEE) -> {0x0, offset} ->0xA0 holds the data. 15-0 Empty TXQ to LPI Wait Time This register specifies the time that the LPI request will be generated after a TXQ has been empty exceeds this configured time. This is only valid when EEE 100BT is enabled. This setting will apply to all the Ports. The unit is 1.3ms. The default value is 1.3 sec. (range from 1.3ms to 86 second) EEE Global Register 2 Global EEE PCS DIAGNOSTIC Register Reg. 110 (0x6E) bits [7:5] = 001 for EEE, Reg. 110 bits [3:0] = 0x0 for the indirect global register. Reg. 111 (0x6F) bits [7:0] = Offset to access the Indirect Byte Register 0xA0. Offset: 0x34(bits [15:8]), 0x35 (bits [7:0]). Location: (001 EEE) -> {0x0, offset} ->0xA0 holds the data. 15-12 Reserved N/A Don't Change RO 0x6 11-8 Reserved N/A Don't Change RO 0x8 7-4 Reserved N/A Don't Change RO 0x0 R/W 1 R/W 1 R/W 1 R/W 1 3 Port 4 Next Page Enable 2 Port 3 Next Page Enable 1 Port 2 Next Page Enable 0 Port 1 Next Page Enable July 24, 2014 1 = Enable next page exchange during AutoNegotiation. 0 = Skip next page exchange during Auto-Negotiation. 1 = Enable next page exchange during AutoNegotiation. 0 = Skip next page exchange during Auto-Negotiation. 1 = Enable next page exchange during AutoNegotiation. 0 = Skip next page exchange during Auto-Negotiation. 1 = Enable next page exchange during Auto Negotiation. 0 = Skip next page exchange during Auto-Negotiation. 124 Revision 1.0 Micrel, Inc. KSZ8794CNX EEE Global Registers (Continued) Address Name Description Mode Default RO 0x0000 RO 0x0201 RO 0x0001 EEE Global Register 3 Global EEE Minimum LPI cycles before back to Idle Control Register Reg. 110 (0x6E) bits [7:5] = 001 for EEE, Reg. 110 bits [3:0] = 0x0 for the indirect global register, Reg. 111 (0x6F) bits [7:0] = Offset to access the Indirect Byte Register 0xA0. Offset: 0x36 (bits [15:8], 0x37 (bits [7:0]). Location: (001 EEE) -> {0x0, offset} ->0xA0 holds the data. 15-0 Reserved N/A Don't Change EEE Global Register 4 Global EEE Wakeup Error Threshold Control Register Reg. 110 (0x6E) bits [7:5] = 001 for EEE, Reg. 110 bits [3:0] = 0x0 for the indirect global register, Reg. 111 (0x6F) bits [7:0] = Offset to access the Indirect Byte Register 0xA0. Offset: 0x38 (bits [15:8]), 0x39 (bits [7:0]). Location: (001 EEE) -> {0x0, offset} ->0xA0 holds the data. 15-0 EEE Wakeup Threshold This value specifies the maximum time allowed for PHY to wake up. If wakeup time is longer than this, EEE wakeup error count will be incremented. Note: This is EEE standard, don't change. EEE Global Register 5 Global EEE PCS Diagnostic Control Register Reg. 110 (0x6E) bits [7:5] = 001 for EEE, Reg. 110 bits [3:0] = 0x0 for the indirect global register, Reg. 111 (0x6F) bits [7:0] = Offset to access the Indirect Byte Register 0xA0. Offset: 0x3A (bits [15:8]), 0x3B (bits [7:0]). Location: (001 EEE) -> {0x0, offset} ->0xA0 holds the data. 15-0 Reserved July 24, 2014 N/A Don't Change. 125 Revision 1.0 Micrel, Inc. KSZ8794CNX EEE Port Registers (Continued) Address Name Description Mode Default EEE Port Register 0 Port Auto-Negotiation Expansion Status Register Reg. 110 (0x6E) bits [7:5] = 001 for EEE, Reg. 110 bits [3:0] = 0xn, n=1-3 for the Indirect Port Register , Reg. 111 (0x6F) bits [7:0] = Offset to access the Indirect Byte Register 0xA0. Offset: 0x0C (bits [15:8]), 0x0D (bits [7:0]). Location: (001 EEE) -> {0xn, offset} ->0xA0 holds the data. 15-7 Reserved N/A Don't Change RO 9h000 6 Receive Next Page Location Able 1 = Received Next Page storage location is specified by bits [6:5]. 0 = Received Next Page storage location is not specified by bits [6:5]. RO 1 5 Received Next Page Storage Location 1 = Link Partner Next Pages are stored in MIIM Register 8h (Additional next page). 0 = Link Partner Next Pages are stored in MIIM Register 5h RO 1 4 Parallel Detection Fault 1 = A fault has been detected via the Parallel Detection function. 0 = A fault has not been detected via the Parallel Detection function. This bit is cleared after reading. R/LH 0 3 Link Partner Next Page Able 1 = Link Partner is Next Page abled 0 = Link Partner is not Next Page abled RO 0 2 Next Page Able 1 = Local Device is Next Page abled 0 = Local Device is not Next Page abled RO 1 1 Page Received 1 = A New Page has been received 0 = A New Page has not been received R/LH 0 0 Link Partner AutoNegotiation Able 1 = Link Partner is Auto-Negotiation abled 0 = Link Partner is not Auto-Negotiation abled RO 0 July 24, 2014 126 Revision 1.0 Micrel, Inc. KSZ8794CNX EEE Port Registers (Continued) Address Name Description Mode Default EEE Port Register 1 Port Auto-Negotiation Next Page Transmit Register Reg. 110 (0x6E) bits [7:5] = 001 for EEE, Reg. 110 bits [3:0] = 0xn, n=1-3 for the Indirect Port Register , Reg. 111 (0x6F) bits [7:0] = Offset to access the Indirect Byte Register 0xA0. Offset: 0x0E (bits [15:8]), 0x0F (bits [7 :0]). Location: (001 EEE) -> {0xn, offset} ->0xA0 holds the data. This register doesn't need to be set if EEE Port Register 5 bit[7]=1 default for Automatically perform EEE capability 15 Next Page Next Page (NP) is used by the Next Page function to indicate whether or not this is the last Next Page to be transmitted. NP shall be set as follows: 1 = Additional Next Page(s) will follow. 0 = Last page. 14 Reserved Reserved RO 0 Message Page Message Page (MP) is used by the Next Page function to differentiate a Message Page from an Unformatted Page. MP shall be set as follows: 1 = Message Page. 0 = Unformatted Page. R/W 1 Acknowledge 2 Acknowledge 2 (Ack2) is used by the Next Page function to indicate that a device has the ability to comply with the message. Ack2 shall be set as follows: 1 = Will comply with message. 0 = Cannot comply with message. R/W 0 Toggle Toggle (T) is used by the Arbitration function to ensure synchronization with the Link Partner during Next Page exchange. This bit shall always take the opposite value of the Toggle bit in the previously exchanged Link Codeword. The initial value of the Toggle bit in the first Next Page transmitted is the inverse of bit [11] in the base Link Codeword and, therefore, may assume a value of logic one or zero. The Toggle bit shall be set as follows: 1 = Previous value of the transmitted Link Codeword equal to logic zero. 0 = Previous value of the transmitted Link Codeword equal to logic one. RO 0 Message/Unformatted Code field Message/Unformatted Code field bits [10:0] R/W 1 13 12 11 10-0 July 24, 2014 127 R/W 0 Revision 1.0 Micrel, Inc. KSZ8794CNX EEE Port Registers (Continued) Address Name Description Mode Default EEE Port Register 2 Port Auto-Negotiation Link Partner Next Page Receive Register Reg. 110 (0x6E) bits [7:5] = 001 for EEE, Reg. 110 bits [3:0] = 0xn, n=1-3 for the indirect port register. Reg. 111 (0x6F) bits [7:0] = Offset to access the Indirect Byte Register 0xA0. Offset: 0x10 (bits [15:8]), 0x11 (bits [7:0]. Location: (001 EEE) -> {0xn, offset} ->0xA0 holds the data. 15 14 13 12 11 10-0 Next page Next Page (NP) is used by the Next Page function to indicate whether or not this is the last Next Page to be transmitted. NP shall be set as follows: 1 = Additional Next Page(s) will follow. 0 = Last page. RO 0 Acknowledge Acknowledge (Ack) is used by the Auto-Negotiation function to indicate that a device has successfully received its Link Partner's Link Codeword. The Acknowledge Bit is encoded in bit D14 regardless of the value of the Selector Field or Link Codeword encoding. If no Next Page information is to be sent, this bit shall be set to logic one in the Link Codeword after the reception of at least three consecutive and consistent FLP Bursts (ignoring the Acknowledge bit value). RO 0 Message Page Message Page (MP) is used by the Next Page function to differentiate a Message Page from an Unformatted Page. MP shall be set as follows: 1 = Message Page 0 = Unformatted Page RO 0 Acknowledge 2 Acknowledge 2 (Ack2) is used by the Next Page function to indicate that a device has the ability to comply with the message. Ack2 shall be set as follows: 1 = Will comply with message. 0 = Cannot comply with message. RO 0 Toggle Toggle (T) is used by the Arbitration function to ensure synchronization with the Link Partner during Next Page exchange. This bit shall always take the opposite value of the Toggle bit in the previously exchanged Link Codeword. The initial value of the Toggle bit in the first Next Page transmitted is the inverse of bit [11] In the base Link Codeword and, therefore, may assume a value of logic one or zero. The Toggle bit shall be set as follows: 1 = Previous value of the transmitted Link Codeword equal to logic zero. 0 = Previous value of the transmitted Link Codeword equal to logic one. RO 0 Message/Unformatted Code field Message/Unformatted Code field bits [10:0] RO 0 July 24, 2014 128 Revision 1.0 Micrel, Inc. KSZ8794CNX EEE Port Registers (Continued) Address Name Description Mode Default EEE Port Register 3 Link Partner EEE Capability Status and Local Device EEE Capability Advisement Register Reg. 110 (0x6E) bits [7:5] = 001 for EEE, Reg. 110 bits [3:0] = 0xn, n=1-3 for the Indirect Port Register. Reg. 111 (0x6F) bits [7:0] = Offset to access the Indirect Byte Register 0xA0. Offset: 0x28 (bits [15:8]), 0x29 (bits [7:0]). Location: (001 EEE) -> {0xn, offset} ->0xA0 holds the data. 15 14 Reserved N/A Don't Change RO 0 LP 10GBASE-KR EEE 1 = EEE is supported for 10GBASE-KR 0 = EEE is not supported for 10GBASE-KR RO 0 Note: LP is Link Partner Note: LP is Link Partner 13 LP 10GBASE-KX4 EEE 1 = EEE is supported for 10GBASE-KX4 0 = EEE is not supported for 10GBASE-KX4 RO 0 12 LP 1000BASE-KX EEE 1 = EEE is supported for 1000BASE-KX 0 = EEE is not supported for 1000BASE-KX RO 0 11 LP 10GBASE-T EEE 1 = EEE is supported for 10GBASE-T 0 = EEE is not supported for 10GBASE-T RO 0 10 LP 1000BASE-T EEE 1 = EEE is supported for 1000BASE-T 0 = EEE is not supported for 1000BASE-T RO 0 9 LP 100BASE-TX EEE 1 = EEE is supported for 100BASE-TX 0 = EEE is not supported for 100BASE-TX RO 0 Reserved Reserved RO 7h'0 Local 100BASE-TX EEE 1 = EEE is supported for 100BASE-TX 0 = EEE is not supported for 100BASE-TX R/W 1 N/A Don't Change RO 0 RO 0x0000 8-2 1 Note: This is for local port to support EEE capability 0 Reserved EEE Port Register 4 Port EEE Wake Up Error Count Register Reg. 110 (0x6E) bits [7:5] = 001 for EEE, Reg. 110 bits [3:0] = 0xn, n=1-3 for the Indirect Port Register. Reg. 111 (0x6F) bits [7:0] = Offset to access the Indirect Byte Register 0xA0. Offset: 0x2A (bits [15:8]), 0x2B (bits [7:0]). Location: (001 EEE) -> {0xn, offset} ->0xA0 holds the data. 15-0 EEE Wakeup Error Counter July 24, 2014 This count is incremented by one whenever a wakeup from LPI to Idle state is longer than the Wake-Up error threshold time specified in EEE Global Register 4. The default of Wake-Up error threshold time is 20.5s. This register is read-cleared 129 Revision 1.0 Micrel, Inc. KSZ8794CNX EEE Port Registers (Continued) Address Name Description Mode Default EEE Port Register 5 Port EEE Control Register Reg. 110 (0x6E) bits [7:5]=001 for EEE, Reg. 110 bits [3:0] = 0xn, n=1-3 for the Indirect Port Register. Reg. 111 (0x6F) bits [7:0] = Offset to access the Indirect Byte Register 0xA0. Offset: 0x2C (bits [15:8]), 0x2D (bits [7:0]). Location: (001 EEE) -> {0xn, offset} ->0xA0 holds the data. 15 10BT EEE Disable 1 = 10BT EEE mode is disabled 0 = 10BT EEE mode is enabled R/W 1 Note: 10BT EEE mode save power by reducing signal amplitude only. 14-8 Reserved N/A Don't Change RO 7h'0 7 H/W Based EEE NP Auto-Negotiation Enable 1 = H/W will automatically perform EEE capability exchange with Link Partner through next page exchange. EEE 100BT enable (bit [0] of this register). Will be set by h/w if EEE capability is matched. 0 = H/W based EEE capability exchange is off. EEE capability exchange is done by software. R/W 1 6 H/W 100BT EEE Enable Status 1 = 100BT EEE is enabled by H/W based np exchange 0 = 100BT EEE is disabled R 0 TX LPI Received 1 = Indicates that the transmit PCS has received low power idle signaling one or more times since the register was last read. 0 = Indicates that the PCS has not received low power idle signaling. This bit is cleared after reading. R/RC 0 TX LPI Indication 1 = Indicates that the transmit PCS is currently receiving low power idle signals. 0 = Indicates that the PCS is not currently receiving low power idle signals. R 0 RX LPI Received 1 = Indicates that the receive PCS has received low power idle signaling one or more times since the register was last read. 0 = Indicates that the PCS has not received low power idle signaling. This bit is cleared after reading. R/RC 0 2 RX LPI Indication 1 = Indicates that the receive PCS is currently receiving low power idle signals. 0 = Indicates that the PCS is not currently receiving low power idle signals. R 0 1 EEE SW Mode Enable 1 = EEE is enabled through S/W setting bit [0] of this register. 0 = EEE is enabled through H/W Auto-Negotiation R/W 0 R/W 0 5 4 3 0 EEE SW 100BT Enable 1 = EEE 100BT is enabled 0 = EEE 100BT is disabled Note: This bit could be set by S/W or H/W if H/W based EEE Next Page Auto-Negotiation enable is on. July 24, 2014 130 Revision 1.0 Micrel, Inc. KSZ8794CNX EEE Port Registers (Continued) Address Name Description Mode Default EEE Port Register 6 Port EEE LPI Recovery Time Register Reg. 110 (0x6E) bits [7:5] = 001 for EEE, Reg. 110bits [3:0] = 0xn, n=1-3 for the Indirect Port Register. Reg. 111 (0x6F) bits [7:0] = Offset to access the Indirect Byte Register 0xA0. Offset: 0x2E (bits [15:8]), 0x2F (bits [7:0]). Location: (001 EEE) -> {0xn, offset} ->0xA0 holds the data. 15-8 7-0 Reserved Reserved RO 1 LPI Recovery Counter This register specifies the time that the MAC device has to wait before it can start to send out packets. This value should be the maximum of the LPI recovery time between local device and remote device. The unit is 640ns. The default is about 25us = 39 (0x27) X 640ns Note: This value can be adjust if PHY recovery time is less than the standard 20.5us for the packets to be sent out quickly from EEE LPI mode. R/W 0x27 July 24, 2014 131 Revision 1.0 Micrel, Inc. KSZ8794CNX Programming Examples: Read Operation 1. Use the Indirect Access Control Register to select register to be read, to read the EEE Global Register 0 (Global EEE QM Buffer Control Register). 2. Write 0x30 to the Register 110 (0x6E) // EEE selected and read operation, and 4 MSBs of Port number = 0 for the global register. 3. Write 0x30 to the indirect Register 111 (0x6F) // trigger the read operation and ready to read the EEE Global Register 0 bits [15:8]. 4. Read the Indirect Byte Register 160 (0xA0) //Get the bits [15:8] value of the EEE Global Register 0. Write Operation 1. Write 0x20 to Register 110 (0x6E) // EEE selected and write operation, 4 MSBs of Port number = 0 is for global register. 2. Write 0x31 to Register 111 (0x6F) // select the offset address, ready to write the EEE Global Register 0 bits [7:0]. 3. Write new value to the Indirect Byte Register 160 (0xA0) bits [7:0]. July 24, 2014 132 Revision 1.0 Micrel, Inc. KSZ8794CNX Management Information Base (MIB) Counters The MIB counters are provided on per port basis. These counters are read using indirect memory access as below: Table 24. Port 1 MIB Counter Indirect Memory Offerts Offset Counter Name Description 0x0 RxHiPriorityByte Rx hi-priority octet count including bad packets. 0x1 RxUndersizePkt Rx undersize packets w/good CRC. 0x2 RxFragments Rx fragment packets w/bad CRC, symbol errors or alignment errors. 0x3 RxOversize Rx oversize packets w/good CRC (max: 1536 or 1522 bytes). 0x4 RxJabbers Rx packets longer than 1522 bytes w/either CRC errors, alignment errors, or symbol errors (depends on max packet size setting) or Rx packets longer than 1916 bytes only. 0x5 RxSymbolError Rx packets w/ invalid data symbol and legal preamble, packet size. 0x6 RxCRCerror Rx packets within (64,1522) bytes w/an integral number of bytes and a bad CRC (upper limit depends on max packet size setting). 0x7 RxAlignmentError Rx packets within (64,1522) bytes w/a non-integral number of bytes and a bad CRC (upper limit depends on max packet size setting). 0x8 RxControl8808Pkts The number of MAC control frames received by a Port with 88-08h in EtherType field. 0x9 RxPausePkts The number of PAUSE frames received by a Port. PAUSE frame is qualified with EtherType (88-08h), DA, control opcode (00-01), data length (64 byte min), and a valid CRC. 0xA RxBroadcast Rx good broadcast packets (not including errored broadcast packets or valid multicast packets). 0xB RxMulticast Rx good multicast packets (not including MAC control frames, errored multicast packets or valid broadcast packets). 0xC RxUnicast Rx good unicast packets. 0xD Rx64Octets Total Rx packets (bad packets included) that were 64 octets in length. 0xE Rx65to127Octets Total Rx packets (bad packets included) that are between 65 and 127 octets in length. 0xF Rx128to255Octets Total Rx packets (bad packets included) that are between 128 and 255 octets in length. 0x10 Rx256to511Octets Total Rx packets (bad packets included) that are between 256 and 511 octets in length. 0x11 Rx512to1023Octets Total Rx packets (bad packets included) that are between 512 and 1023 octets in length. 0x12 Rx1024to1522Octets Total Rx packets (bad packets included) that are between 1024 and 1522 octets in length. 0x13 Rx1523to2000Octets Total Rx packets (bad packets included) that are between 1523 and 2000 octets in length. 0x14 Rx2001toMax1Octets Total Rx packets (bad packets included) that are between 2001 and Max-1 octets in length (upper limit depends on max packet size -1). 0x15 TxHiPriorityByte Tx hi-priority good octet count, including PAUSE packets. 0x16 TxLateCollision The number of times a collision is detected later than 512 bit-times into the Tx of a packet. 0x17 TxPausePkts The number of PAUSE frames transmitted by a Port. 0x18 TxBroadcastPkts Tx good broadcast packets (not including errored broadcast or valid multicast packets). 0x19 TxMulticastPkts Tx good multicast packets (not including errored multicast packets or valid broadcast packets). 0x1A TxUnicastPkts Tx good unicast packets. 0x1B TxDeferred Tx packets by a Port for which the 1st Tx attempt is delayed due to the busy medium. 0x1C TxTotalCollision Tx total collision, half-duplex only. 0x1D TxExcessiveCollision A count of frames for which Tx fails due to excessive collisions. 0x1E TxSingleCollision Successfully Tx frames on a Port for which Tx is inhibited by exactly one collision. 0x1F TxMultipleCollision Successfully Tx frames on a Port for which Tx is inhibited by more than one collision. July 24, 2014 133 Revision 1.0 Micrel, Inc. KSZ8794CNX For Port 2, the base is 0x20, same offset definition (0x20-0x3f) For Port 3, the base is 0x40, same offset definition (0x40-0x5f) Reserved, the base is 0x60, same offset definition (0x60-0x7f) For Port 4, the base is 0x80, same offset definition (0x80-0x9f) Table 25. Format of "Per Port" MIB Counter Address Name Description Mode Default Format of Per Port MIB Counters 38 Overflow 1 = Counter overflow. 0 = No Counter overflow. RO 0 37 Count Valid 1 = Counter value is valid. 0 = Counter value is not valid. RO 0 36-30 Reserved N/A No Change RO All `0' 29-0 Counter Values Counter value. RO 0 Table 26. All Port Dropped Packet MIB Counters Offset Counter Name 0x100 Port1 Rx Total Bytes Port 1 Rx total octet count, including bad packets. 0x101 Port1 Tx Total Bytes Port 1 Tx total good octet count, including PAUSE packets. 0x102 Port1 Rx Drop Packets Port 1 Rx packets dropped due to lack of resources. 0x103 Port1 Tx Drop Packets Port 1 Tx packets dropped due to lack of resources. 0x104 Port2 Rx Total Bytes Port 2 Rx total octet count, including bad packets. 0x105 Port2 Tx Total Bytes Port 2 Tx total good octet count, including PAUSE packets. 0x106 Port2 Rx Drop Packets Port 2 Rx packets dropped due to lack of resources. 0x107 Port2 Tx Drop Packets Port 2 Tx packets dropped due to lack of resources. 0x108 Port3 Rx Total Bytes Port 3 Rx total octet count, including bad packets. 0x109 Port3 Tx Total Bytes Port 3 Tx total good octet count, including PAUSE packets. 0x10A Port3 Rx Drop Packets Port 3 Rx packets dropped due to lack of resources. 0x10B Port3 Tx Drop Packets Port 3 Tx packets dropped due to lack of resources. 0x10C Port4 Rx Total Bytes Port 4 Rx total octet count, including bad packets. 0x10D Port4 Tx Total Bytes Port 4 Tx total good octet count, including PAUSE packets. 0x10E Port4 Rx Drop Packets Port 4 Rx packets dropped due to lack of resources. 0x10F Port4 Tx Drop Packets Port 4 Tx packets dropped due to lack of resources. 0x110 Port5 Rx Total Bytes Port 4 Rx total octet count, including bad packets. 0x111 Port5 Tx Total Bytes Port 4 Tx total good octet count, including PAUSE packets. 0x112 Port5 Rx Drop Packets Port 4 Rx packets dropped due to lack of resources. 0x113 Port5 Tx Drop Packets Port 4 Tx packets dropped due to lack of resources. July 24, 2014 Description 134 Revision 1.0 Micrel, Inc. KSZ8794CNX Table 27. Format of Per Port RX/TX Total Bytes MIB Counter Address Name Description Mode Default Format of Per Port Total Byte MIB Counters 38 Overflow 1 = Counter overflow. 0 = No Counter overflow. RO 0 37 Count Valid 1 = Counter value is valid. 0 = Counter value is not valid. RO 0 36 Reserved N/A No Change RO 0 35-0 Counter Values Counter value. RO 0 Mode Default Table 28. Format of "All Dropped Packet" MIB Counter Address Name Description Format of All Port Dropped Packet MIB Counters 38 Overflow 1 = Counter overflow. 0 = No Counter overflow. RO 0 37 Count Valid 1 = Counter value is valid. 0 = Counter value is not valid. RO 0 36-16 Reserved N/A No Change RO All `0' 15-0 Counter Values Counter value. RO 0 Note: All MIB counter per port are read clear. July 24, 2014 135 Revision 1.0 Micrel, Inc. KSZ8794CNX The KSZ8794CNX provides a total of 36 MIB counters per port. These counters are used to monitor the port activity for network management and maintenance. These MIB counters are read using indirect memory access, per the following examples. Programming Examples: (1) MIB counter read (read Port 1 Rx64Octets counter) Write to Register 110 with 0x1c (read MIB counters selected) Write to Register 111 with 0xd (trigger the read operation) Then Read Register 116 (counter value [39:32]) // If bit [38] = 1, there was a counter overflow Read Register 117 (counter value [31:24]) Read Register 118 (counter value [23:16]) Read Register 119 (counter value [15:8]) Read Register 120 (counter value [7:0]) (2) MIB counter read (read Port 2 Rx64Octets counter) Write to Register 110 with 0x1c (read MIB counter selected) Write to Register 111 with 0x2d (trigger the read operation) Then Read Register 116 (counter value [39:32]) // If bit [38] = 1, there was a counter overflow Read Register 117 (counter value [31:24]) Read Register 118 (counter value [23:16]) Read Register 119 (counter value [15:8]) Read Register 120 (counter value [7:0]) (3) MIB counter read (read Port 1 TX drop packets) Write to Register 110 with 0x1d Write to Register 111 with 0x03 Then Read Register 116 (counter value [39:32]) // If bit [38] = 1, there was a counter overflow Read Register 119 (counter value [15:8]) Read Register 120 (counter value [7:0]) Note: To read out all the counters, the best performance over the SPI bus is (160+3) x 8 x 20 = 26us, where there are 160 registers, 3 overhead, 8 clocks per access, at 50MHz. In the heaviest condition, the byte counter will overflow in 2 minutes. It is recommended that the software read all the counters at least every 30 seconds. The all Port MIB counters are designed as "read clear." July 24, 2014 136 Revision 1.0 Micrel, Inc. KSZ8794CNX MIIM Registers All the registers defined in this section can be also accessed via the SPI interface. Note: different mapping mechanisms are used for MIIM and SPI. The "PHYAD" defined in IEEE is assigned as "0x1" for Port 1, "0x2" for Port 2 and "0x3" for Port 3. The "REGAD" supported are 0x0-0x5 (0h-5h), 0x1D (1dh) and 0x1F (1fh). Address Name Description Mode Default Register 0h: Basic Control Soft Reset 1 = PHY soft reset. 0 = Normal operation. R/W (SC) 0 14 Loop Back 1 = Perform MAC loopback, loop back path as follows: Assume the loop-back is at Port 1 MAC, Port 2 is the monitor port. Port 1 MAC Loopback (Port 1 Reg. 0, bit [14] = 1') Start: RXP2/RXM2 (Port 2). Can also start from Ports 3, 4. Loopback: MAC/PHY interface of Port 1's MAC End: TXP2/TXM2 (Port 2). Can also end at Ports 3, 4 respectively. Setting address 0x3, 4 Reg. 0, bit [14] = `1' will perform MAC loopback on Ports 3, 4, respectively. 0 = Normal Operation. R/W 0 13 Force 100 1 = 100Mbps. 0 = 10Mbps. R/W 1 12 AN Enable 1 = Auto-Negotiation enabled. 0 = Auto-Negotiation disabled. R/W 1 11 Power Down 1 = Power down. 0 = Normal operation. R/W 0 10 PHY Isolate 1 = Electrical PHY isolation of PHY from Tx+/Tx-. 0 = Normal operation. R/W 0 9 Restart AN 1 = Restart Auto-Negotiation. 0 = Normal operation. R/W 0 8 Force Full Duplex 1 = Full duplex. 0 = Half duplex. R/W 1 7 Reserved Reserved RO 0 6 Reserved Reserved RO 0 5 Hp_mdix 1 = HP Auto-MDI/MDIX mode 0 = Micrel Auto-MDI/MDIX mode R/W 1 4 Force MDI 1 = MDI mode when disable Auto-MDI/MDIX. 0 = MDIX mode when disable Auto-MDI/MDIX. R/W 0 3 Disable Auto MDI/MDI-X 1 = Disable Auto-MDI/MDIX. 0 = Enable Auto-MDI/MDIX. R/W 0 2 Disable far End fault 1 = Disable far end fault detection. 0 = Normal operation. R/W 0 1 Disable Transmit 1 = Disable transmit. 0 = Normal operation. R/W 0 0 Disable LED 1 = Disable LED. 0 = Normal operation. R/W 0 15 July 24, 2014 137 Revision 1.0 Micrel, Inc. KSZ8794CNX MIIM Registers (Continued) Address Name Description Mode Default Register 1h: Basic Status 15 T4 Capable 0 = Not 100 BASET4 capable. RO 0 14 100 Full Capable 1 = 100BASE-TX full-duplex capable. 0 = Not capable of 100BASE-TX full-duplex. RO 1 13 100 Half Capable 1 = 100BASE-TX half-duplex capable. 0 = Not 100BASE-TX half-duplex capable. RO 1 12 10 Full Capable 1 = 10BASE-T full-duplex capable. 0 = Not 10BASE-T full-duplex capable. RO 1 11 10 Half Capable 1 = 10BASE-T half-duplex capable. 0 = 10BASE-T half-duplex capable. RO 1 10-7 Reserved Reserved RO 0 6 Reserved Reserved RO 0 5 AN Complete 1 = Auto-Negotiation complete. 0 = Auto-Negotiation not completed. RO 0 4 Far End fault 1 = far end fault detected. 0 = No far end fault detected. RO 0 3 AN Capable 1 = Auto-Negotiation capable. 0 = Not Auto-Negotiation capable. RO 1 2 Link Status 1 = Link is up. 0 = Link is down. RO 0 1 Reserved Reserved RO 0 0 Extended Capable 0 = Not extended register capable. RO 0 High order PHYID bits. RO 0x0022 Low order PHYID bits. RO 0x1550 Register 2h: PHYID HIGH 15-0 Phyid High Register 3h: PHYID LOW 15-0 Phyid Low Register 4h: Advertisement Ability 15 Reserved Reserved RO 0 14 Reserved Reserved RO 0 13 Reserved Reserved RO 0 12 Reserved Reserved RO 0 11 Reserved Reserved RO 1 10 Pause 1 = Advertise pause ability. 0 = Do not advertise pause ability. R/W 1 9 Reserved Reserved R/W 0 8 Adv 100 Full 1 = Advertise 100 full-duplex ability. 0 = Do not advertise 100 full-duplex ability. R/W 1 7 Adv 100 Half 1 = Advertise 100 half-duplex ability. 0 = Do not advertise 100 half-duplex ability. R/W 1 July 24, 2014 138 Revision 1.0 Micrel, Inc. KSZ8794CNX MIIM Registers (Continued) Address Name Description 6 Adv 10 Full 5 4-0 Mode Default 1 = Advertise 10 full-duplex ability. 0 = Do not advertise 10 full-duplex ability. R/W 1 Adv 10 Half 1 = Advertise 10 half-duplex ability. 0 = Do not advertise 10 half-duplex ability. R/W 1 Selector Field 802.3 RO 00001 Register 5h: Link Partner Ability 15 Reserved Reserved RO 0 14 Reserved Reserved RO 0 13 Reserved Reserved RO 0 12-11 Reserved Reserved RO 0 10 Pause 1 = Link partner flow control capable. 0 = Link partner not flow control capable. RO 0 9 Reserved Reserved RO 0 8 Adv 100 Full 1 = Link partner 100BT full-duplex capable. 0 = Link partner not 100BT full-duplex capable. RO 0 7 Adv 100 Half 1 = Link partner 100BT half-duplex capable. 0 = Link partner not 100BT half-duplex capable. RO 0 6 Adv 10 Full 1 = Link partner 10BT full-duplex capable. 0 = Link partner not 10BT full-duplex capable. RO 0 5 Adv 10 Half 1 = Link partner 10BT half-duplex capable. 0 = Link partner not 10BT half-duplex capable. RO 0 Reserved Reserved RO 00001 1 = Enable cable diagnostic. After CDT test has completed, this bit will be self-cleared. 0 = Indicates cable diagnostic test (if enabled) has completed and the status information is valid for reading. R/W (SC) 0 CDT_Result 00 = Normal condition 01 = Open condition detected in cable 10 = Short condition detected in cable 11 = Cable diagnostic test has failed RO 00 CDT 10M Short 1 = Less than 10 meter short RO 0 11-9 Reserved Reserved RO 0 8-0 CDT_Fault_Count Distance to the fault. It's approximately 0.4m*CDT_Fault_Count[8:0] RO 000000000 4-0 Register 1dh: LinkMD Control/Status CDT_Enable 15 14-13 12 Note: CDT means Cable Diagnostic Test July 24, 2014 139 Revision 1.0 Micrel, Inc. KSZ8794CNX MIIM Registers (Continued) Address Name Description Mode Default RO 0000000000 RO 001 Register 1fh: PHY Special Control/Status 15-11 Reserved 10-8 Port Operation Mode Indication Indicate the current state of port operation mode: 000 = Reserved 001 = still in auto-negotiation 010 = 10BASE-T half duplex 011 = 100BASE-TX half duplex 100 = Reserved 101 = 10BASE-T full duplex 110 = 100BASE-TX full duplex 111 = PHY/MII isolate 7-6 Reserved N/A, don't change R/W 00 5 Polrvs 1 = Polarity is reversed 0 = Polarity is not reversed RO 0 4 MDI-X status 1 = MDI 0 = MDI-X RO 0 3 Force_lnk 1 = Force link pass 0 = Normal operation R/W 0 2 Pwrsave 1 = Enable power save 0 = Disable power save R/W 0 1 Remote Loopback 1 = Perform Remote loopback, loop back path as follows: Port 1 (PHY ID address 0x1 Reg. 1fh, bit [1] = `1') Start: RXP1/RXM1 (Port 1) Loopback: PMD/PMA of Port 1's PHY End: TXP1/TXM1 (Port 1) Setting PHY ID address 0x2, 3, 4 Reg. 1fh bit [1] = `1', will perform remote loopback on Port 2, 3, 4. 0 = Normal Operation. R/W 0 0 Reserved Reserved RO 0 July 24, 2014 140 Revision 1.0 Micrel, Inc. KSZ8794CNX Absolute Maximum Ratings(6) Operating Ratings(7) Supply Voltage (VDD12A, VDD12D) ...................................... -0.5V to +1.8V (VDDAT, VDDIO) ......................................... -0.5V to +4.0V Input Voltage ................................................ -0.5V to +4.0V Output Voltage ............................................. -0.5V to +4.0V Lead Temperature (soldering, 10 sec.) ...................... 260C Storage Temperature (TS) ......................... -55C to +150C Max Junction Temperature (TJ).................................. 125C HBM ESD Rating .......................................................... 5KV Supply Voltage (VDD12A, VDD12D) .................................. 1.140V to 1.260V (VDDAT)................................................ 3.135V to 3.465V (VDDIO @ 3.3V) ................................... 3.135V to 3.465V (VDDIO @ 2.5V) ................................... 2.375V to 2.625V (VDDIO @ 1.8V) ................................... 1.710V to 1.890V Ambient Temperature (TA) Commercial............................................. -0C to +70C Industrial ............................................... -40C to +85C Package Thermal Resistance(8) Thermal Resistance (JA) ............................. 31.96C/W Thermal Resistance (JC) ............................ 13.54C/W Electrical Characteristics(9,10) VIN = 1.2V/3.3V; TA = 25C. Symbol Parameter Condition Min Typ Max Units 100BASE-TX Operation--All Ports 100% Utilization IDX 100BASE-TX (Transmitter) 3.3V Analog VDDAT 107 mA ID12 100BASE-TX 1.2V VDD12A + VDD12D 35 mA IDDIO 100BASE-TX (Digital IO) 3.3V Digital VDDIO 11 mA 10BASE-T Operation --All Ports 100% Utilization IDX 10BASE-T (Transmitter) 3.3V Analog VDDAT 110 mA ID12 10BASE-T 1.2V VDD12A + VDD12D 29 mA IDDIO 10BASE-T (Digital IO) 3.3V Digital VDDIO 11 mA Auto-Negotiation Mode IDX 3.3V Analog VDDAT 51 mA ID12 1.2V Analog/Digital VDD12A + VDD12D 34 mA IDDIO 3.3V Digital VDDIO 11 mA Power Management Mode ISPDM1 Soft Power Down Mode 3.3V VDDAT + VDDIO 0.23 mA ISPDM2 Soft Power Down Mode 1.2V VDD12A + VDD12D 0.17 mA IEDM1 Energy Detect Mode (EDPD) 3.3V VDDAT + VDDIO 20 mA IEDM2 Energy Detect Mode (EDPD) 1.2V VDD12A + VDD12D 27 mA IEEE1 100BT EEE Mode at Idle 3.3V VDDAT + VDDIO 20 mA IEEE2 100BT EEE Mode at Idle 1.2V VDD12A + VDD12D 27 mA CMOS Inputs VIH VIL IIN Input High Voltage Input Low Voltage Input Current (Excluding Pull-up/Pull-down) July 24, 2014 VDDIO=3.3V 2.0 V VDDIO=2.5V 1.8 V VDDIO=1.8V 1.3 V VDDIO=3.3V 0.8 V VDDIO=2.5V 0.7 V VDDIO=1.8V 0.5 V VIN = GND ~ VDDIO 10 A 141 Revision 1.0 Micrel, Inc. KSZ8794CNX Electrical Characteristics (Continued) VIN = 1.2V/3.3V; TA = 25C. Symbol Parameter Condition Min Typ Max Units VDDIO=3.3V 2.4 V VDDIO=2.5V 2.0 V VDDIO=1.8V 1.5 V CMOS Outputs VOH VOL IOZ Output High Voltage Output Low Voltage Output Tri-State Leakage VDDIO=3.3V 0.4 V VDDIO=2.5V 0.4 V VDDIO=1.8V 0.3 V VIN = GND ~ VDDIO 10 A 1.05 V 2 % 3 5 ns 0 0.5 ns 0.5 ns 5 % 100BASE-TX Transmit (measured differentially after 1:1 transformer) 100 termination on the VO Peak Differential Output Voltage differential output 100 termination on the VIMB Output Voltage Imbalance differential output Rise/fall Time tr tt Rise/fall Time Imbalance 0.95 Duty Cycle Distortion Overshoot Output Jitters Peak-to-peak 0 0.75 1.4 ns 300 400 585 mV 2.2 2.5 2.8 V 1.4 3.5 ns 28 30 ns 10BASE-T Receive VSQ Squelch Threshold 5MHz square wave 10BASE-T Transmit (measured differentially after 1:1 transformer) VDDAT = 3.3V 100 termination on the VP Peak Differential Output Voltage differential output Output Jitters Peak-to-peak Rise/fall Times I/O Pin Internal Pull-Up and Pull-Down Resistance R1.8PU I/O Pin Effective Pull-Up Resistance VDDIO = 1.8V 75 95 135 k R1.8PD I/O Pin Effective Pull-Down Resistance VDDIO = 1.8V 53 68 120 k R2.5PU I/O Pin Effective Pull-Up Resistance VDDIO = 2.5V 46 60 93 k R2.5PD I/O Pin Effective Pull-Down Resistance VDDIO = 2.5V 46 59 103 k R3.3PU I/O Pin Effective Pull-Up Resistance VDDIO = 3.3V 35 45 65 k R3.3PD I/O Pin Effective Pull-Down Resistance VDDIO = 3.3V 37 46 74 k Notes: 6. Exceeding the absolute maximum rating may damage the device. 7. The device is not guaranteed to function outside its operating rating. Unused inputs must always be tied to an appropriate logic voltage level (ground or VDD). 8. No heat spreader in package. The thermal junction to ambient (JA) and the thermal junction to case (JC) are under air velocity 0m/s. 9. Specification for packaged product only. There is no an additional transformer consumption due to use on chip termination technology with internal biasing for 10Base-T and 100Base-TX. The test condition is in port 4 RGMII mode (default). 10. Measurements were taken with operating ratings. July 24, 2014 142 Revision 1.0 Micrel, Inc. KSZ8794CNX Timing Diagrams RGMII Timing The RGMII timing conforms to the timing requirements in the RGMII Version 2.0 Specification. Figure 14. RGMII v2.0 Specification (Figure3-Multiplexing and Timing Diagram) Table 29. RGMII v2.0 Specification (Timing Specifics from Table 2) Symbol Parameter Min Typ Max Units TskewT Data to clock output skew (at transmitter) *NOTE 11 -500 0 500 ps TskewR Data to clock input skew (at receiver) *NOTE 11 1 2.6 ns Tcyc Clock Cycle Duration *NOTE 12 7.2 8 8.8 ns Duty_G Duty Cycle for Gigabit 45 50 55 % Duty_T Duty Cycle for 10/100T 40 50 60 % Tr / Tf Rise / Fall Time (20-80%) 0.75 ns Note: 11. RGMII V2.0 add internal delay (RGMII-ID) option to match the clocks timing for the transmit and the receiving. 12. For 10Mbps and 100Mbps, Tcyc will scale to 400ns+/-40ns and 40ns+/-4ns. July 24, 2014 143 Revision 1.0 Micrel, Inc. KSZ8794CNX MII Timing Figure 15. MAC Mode MII Timing - Data Received from MII Figure 16. MAC Mode MII Timing - Data Transmitted from MII Table 30. MAC Mode MII Timing Parameters 10Base-T/100Base-TX Symbol Parameter Min Typ Max tCYC3 Clock Cycle tS3 Set-Up Time 2 ns tH3 Hold Time 2 ns Output Valid 3 tOV3 July 24, 2014 400/40 Units 144 8 ns 10 ns Revision 1.0 Micrel, Inc. KSZ8794CNX Figure 17. PHY Mode MII Timing - Data Received from MII Figure 18. PHY Mode MII Timing - Data Transmitted from MII Table 31. PHY Mode MII Timing Parameters 10BaseT/100BaseT Symbol Parameter tCYC4 Clock Cycle tS4 Set-Up Time 10 ns tH4 Hold Time 0 ns tOV4 Output Valid 16 July 24, 2014 Min Typ Max 400/40 20 145 Units ns 25 ns Revision 1.0 Micrel, Inc. KSZ8794CNX RMII Timing Figure 19. RMII Timing - Data Received from RMII Figure 20. RMII Timing - Data Transmitted to RMII Table 32. RMII Timing Parameters Timing Parameter Description tcyc Clock cycle t1 Setup time 4 ns t2 Hold time 2 ns tod Output delay 3 July 24, 2014 Min Typ Max 20 146 Unit ns 10 ns Revision 1.0 Micrel, Inc. KSZ8794CNX SPI Timing Figure 21. SPI Input Timing Table 33. SPI Input Timing Parameters Symbol fC Parameter Min Clock Frequency Typ Max Units 50 MHz tCHSL SPIS_N Inactive Hold Time 2 ns tSLCH SPIS_N Active Set-Up Time 4 ns tCHSH SPIS_N Active Hold Time 2 ns tSHCH SPIS_N Inactive Set-Up Time 4 ns tSHSL SPIS_N Deselect Time 10 ns tDVCH Data Input Set-Up Time 4 ns tCHDX Data Input Hold Time 2 ns tCLCH Clock Rise Time 1 us tCHCL Clock fall Time 1 us tDLDH Data Input Rise Time 1 us tDHDL Data Input fall Time 1 us July 24, 2014 147 Revision 1.0 Micrel, Inc. KSZ8794CNX Auto-Negotiation Timing Figure 22. Auto-Negotiation Timing Table 34. Auto-Negotiation Timing Parameters Symbols Parameters tBTB FLP burst to FLP burst tFLPW FLP burst width tPW Clock/Data pulse width tCTD Clock pulse to Data pulse 55.5 64 69.5 s tCTC Clock pulse to Clock pulse 111 128 139 s Number of Clock/Data pulse per burst 17 July 24, 2014 148 Min Typ Max Units 8 16 24 ms 2 ms 100 ns 33 Revision 1.0 Micrel, Inc. KSZ8794CNX MDC/MDIO Timing Figure 23. MDC/MDIO Timing Table 35. MDC/MDIO Typical Timing Parameters Timing Parameter Description fC Typ Max Unit Clock Frequency 2.5 25 MHz tP MDC period 400 t1MD1 MDIO (PHY input) setup to rising edge of MDC 10 ns tMD2 MDIO (PHY input) hold from rising edge of MDC 4 ns tMD3 MDIO (PHY output) delay from rising edge of MDC 5 ns July 24, 2014 Min 149 ns Revision 1.0 Micrel, Inc. KSZ8794CNX Power-down/Power-up and Reset Timing Figure 24. Reset Timing Table 36. Reset Timing Parameters Symbol Parameter tSR Stable Supply Voltages to Reset High 10 ms tCS Configuration Set-Up Time 5 ns tCH Configuration Hold Time 5 ns tRC Reset to Strap-In Pin Output 6 ns tvr 3.3V rise time 200 us July 24, 2014 Min 150 Typ Max Units Revision 1.0 Micrel, Inc. KSZ8794CNX Reset Circuit Diagram Micrel recommends the following discrete reset circuit as shown in Figure 28 when powering up the KS8795 device. For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), we recommend the reset circuit as shown in Figure 29. VC D1: 1N4148 R 10k D1 KS8794 RST C 10F Figure 25. Recommended Reset Circuit VC R 10k D1 KS8794 CPU/FPGA RST RST_OUT_n D2 C 10F D1, D2: 1N4148 Figure 26. Recommended Circuit for Interfacing with CPU/FPGA Reset At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the Micrel device. The reset out RST_OUT_n from CPU/FPGA provides the warm reset after power up. July 24, 2014 151 Revision 1.0 Micrel, Inc. KSZ8794CNX Selection of Isolation Transformer(13) One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated commonmode choke is recommended for exceeding FCC requirements at line side. Request to separate the center taps of RX/TX at chip side. The following table gives recommended transformer characteristics. Table 37. Transformer Selection Criteria Characteristics Name Value Test Condition Turns Ratio 1 CT : 1 CT Open-Circuit Inductance (min.) 350H 100mV, 100kHz, 8mA Insertion Loss (max.) 1.1dB 0.1MHz to 100MHz HIPOT (min.) 1500Vrms Note: 13. The IEEE 802.3u standard for 100BASE-TX assumes a transformer loss of 0.5dB. For the transmit line transformer, insertion loss of up to 1.3dB can be compensated by increasing the line drive current by means of reducing the ISET resistor value. 14. The center taps of RX and TX should be isolated for the low power consumption. The following transformer vendors provide compatible magnetic parts for Micrel's device: Table 38. Qualified Magnetic Vendors Vendors and Parts Auto MDIX Number of Ports Vendors and Parts Auto MDIX Number of Ports Pulse H1164NL Yes 4 Pulse H1102 Yes 1 YCL PH406082 Yes 4 Bel Fuse S558-5999-U7 Yes 1 TDK TLA-6T718A Yes 1 YCL PT163020 Yes 1 LanKom LF-H41S Yes 1 Transpower HB726 Yes 1 Datatronic NT79075 Yes 1 Delta LF8505 Yes 1 Selection of Reference Crystal Table 39. Typical Reference Crystal Characteristics Characteristics Value Units Frequency 25.00000 MHz Frequency tolerance (max) <= 50 ppm 27 pF 40 Load capacitance (max) Note: Typical value varies per specific crystal spec. Series resistance (max ESR) July 24, 2014 152 Revision 1.0 Micrel, Inc. KSZ8794CNX Package Information Figure 27. 64-Pin (8mm x 8mm) QFN Package July 24, 2014 153 Revision 1.0 Micrel, Inc. KSZ8794CNX MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Micrel's terms and conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2014 Micrel, Incorporated. July 24, 2014 154 Revision 1.0