KSZ8794CNXCC - MICREL SEMICONDUCTOR

KSZ8794CNX

Integrated 4-Port 10/100 Managed Ethernet

Switch with Gigabit RGMII/MII/RMII Interface

Revision 1.0

General Descr i ption

The KSZ8794CNX is a highly integrated, Layer 2

managed, four-port switch with numerous features

designed to reduce system cost. It is intended for cost-

sensitive applications requiring three 10/100Mbps copper

ports and one 10/100/1000Mbps Gigabit uplink port. The

KSZ8794CNX incorporates a small package outline,

lowest power consumption with internal biasing, and on-

chip termination. Its extensive features set includes

enhanced power management, programmable rate limiting

and priority ratio, tagged and port-based VLAN, port-based

security and ACL rule-based packet filtering technology,

QoS priority with four queues, management interfaces,

enhanced MIB counters, high-performance memory

bandwidth, and a shared memory-based switch fabric with

non-blocking support. The KSZ8794CNX provides support

for multiple CPU data interfaces to effectively address both

current and emerging fast Ethernet and Gigabit Ethernet

applications where the GMAC interface can be configured

to any of RGMII, MI I and RMI I modes.

The KSZ8794CNX is built on Micrel’s latest industry-

leading Ethernet analog and digital technology, with

features designed to offload host processing and

streamline your overall design:

• Three integrated 10/100Base-T/TX MAC/PHYs.

• One integrated 10/100/1000Base-T/TX GMAC with

selectable RGMII, MII or RMII interfaces.

• Small 64-pin QFN package.

A robust assortment of power management features

including Energy Efficient Ethernet (EEE), PME and WoL

have been designed in to satisfy energy efficient

environments.

All registers in the MAC and PHY units can be managed

through the SPI interface. MIIM PHY registers can be

accessed through the MDC/MDIO interface.

Datasheets and support documentation are available on

Micrel’s web site at: www.micrel.com.

Functional Diagram

KSZ8794CNX Functional B lo ck D iagram

LinkMD® is a registered trademark of Micrel, Inc.

Auto MDI/MDI-X™ is a trademark of Hewlett-Pacard Company, L.P

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

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KSZ8794CNX

Highlights and Features

Management Capabilities

• The KSZ8794CNX includes all the functi ons of a

10/100Base-T/ T X switch system which combines a

switch engine, frame buffer management, address look-

up table, queue management, MIB counters, media

access controllers (MAC) and PHY transcei vers

• Non-blocking store-and-for war d switch fabric assures

fast packet delivery by utilizing 1024 entries forwarding

table

• Port mirroring/monitoring/snif f i ng: ingress and/or egress

traffic to any port

• MIB counters for f ul l y compliant statistic s gat hering 36

counters per port

• Support hardware for port-based flush and freeze

command in MIB counter.

• Multiple loopback of remote, PHY and MAC modes

support for the diagnostics

• Rapid Spanning Tree Support (RSTP) for topol ogy

management and rin g/linear recovery

Robust PHY Ports

• Four Integrated IEEE 802.3 / 802.3u co m pl i ant E thernet

transceivers support ing 10Base-T and 1 00Base-TX

• IEEE 802.1az EEE supported

• On-Chip terminat i on resistors and intern al bi asing for

differential pairs to reduce power

• HP Auto MDI/MDI-X™ crossover support eliminating the

need to differentiat e between straight or crossover

cables in applications

MAC and GMAC Ports

• Four internal media access control (MAC 1 to MAC3)

units and one internal gi gabit media acc ess control

(GMAC4) unit

• RGMII, MII or RMII interfaces support for the port 4

GMAC4 with uplink

• 2KByte Jumbo packet support

• Tail tagging mode (one byte added befo re FCS) support

on port 4 to inform the processor which ingress port

receives the packet and its priority

• Supports Reduce d M edia Independent Interface (RMII)

with 50 MHz reference clock output

• Supports Media I ndependent Interface (MI I) in either

PHY mode or MAC m ode on port 4

• Micrel LinkMD® cable diagnostic capabilities for

determining cabl e opens, shorts, and l ength

Advanced Switch Capabilities

• Non-blocking store-and-for war d switch fabric assures

fast packet delivery by utilizing 1024 entry forwarding

table

• 64kb frame buffer RAM

• IEEE 802.1q VLAN support for up to 128 active VLA N

groups (full-range 4096 of VLAN IDs)

• IEEE 802.1p/Q t ag i nsertion or removal on a per port

basis (egress)

• VLAN ID tag/un-tag options on per port basis

• Fully compliant with IEEE 802.3/802.3u stand ards

• IEEE 802.3x full-duplex with force mode option and half-

duplex back-press ure collision flow cont rol

• IEEE 802.1w rapid spanning tree protocol support

• IGMP v1/v2/v3 snooping for multicast packet filtering

• QoS/CoS packets prioritization support: 802.1p,

DiffServ-based and re-mapping of 802.1p priority field

per port basis on four priority levels

• IPv4/IPv6 QoS support

• IPV6 multicast listener discovery (MLD) snooping

• Programmable rat e li m i t i ng at the ingress and egress

ports on a per port basis

• Jitter-free per packet based rat e l i m iting support

• Tail tag mode (1 byte added before FCS) support on

Port 4 to inform t he processor which ingres s port

receives the packet

• Broadcast storm protection with percentage control

(global and per port basis)

• 1K entry forwarding table with 64K Byte frame buffer

• 4 priority queues with dynamic packet mappi ng for IEEE

802.1P, IPv4 TOS (DIFFSERV), IPv6 Traffic Class, etc.

• Supports Wake on LAN (WoL) using AM D’s Magic

Packet

• VLAN and Address Filtering

• Support 802.1x port-based securit y, authentication and

MAC-based authentication v ia access control lists (ACL)

• Provide port-based and rule-based ACLs to support

layer 2 MAC SA/ DA address, layer 3 IP address an d IP

mask, layer 4 TCP/UDP port number, IP protocol, TCP

flag and their combination for the port security f i ltering

• Ingress and egress rat e l imit based on bit per second

(bps) and packet-based rate limiting (pps)

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KSZ8794CNX

Configuration Registers Access

• High speed SPI (4-wi re, up to 50MHz) interface to

access all internal registers

• MII Management (MIIM, MDC/MDIO 2-wire) Interface to

access all PHY registers per Clause 22.2. 4. 5 of the

IEEE 802.3 specifi cat i on

• I/O pin strapping facilit y to set certain re gi st er bits from

I/O pins during reset time

• Control registers conf i gurable on-the-fly

Power and Power Management

• Full-chip software powe r down (All regist ers val ue are

not saved and strap-in value will re-strap after release

the power down.)

• Per port software power down

• Energy Detect P ower D own (EDPD), which disables the

PHY transceiver whe n cables are removed

• Supports IEEE P802.3az energy-efficient Ethernet

(EEE) to reduce powe r consumption in tr ansceivers in

LPI state even though cables are not removed

• Dynamic clock tree control to reduce clo cking in areas

not in use

• Very low power consum ption (less than 0.5W) without

extra power consum ption on transformers

• Voltages: Using external LDO power supplies

− Analog VDDAT 3. 3V

− VDDIO support 3.3V, 2.5V and 1.8V

− Low 1.2V voltage for anal og and digital core po wer

• Wake on LAN support with configurable packet control

Additional Features

• Single 25MHz +50ppm referen ce clock requirem ent

• Comprehensiv e programmable two LED i ndicat or

support for link, activity, full/half duplex and 10/100

speed

Packaging and Environmental

• Commercial Temperature Range: 0°C to +70°C

• Industrial Temperature Ra nge: -40°C to +85°C

• Small package available in an 64-pin lead free (ROHS)

QFN form factor

• 0.065µm CMOS technology for lower power

consumption

Target Applications

• Industrial Ethernet applications that emp l oy IEEE 802.3

compliant MACs. (Ethernet/IP, Profinet, MODBUS TCP,

etc)

• VoIP Phone

• Set-top/Game Box

• Automotive

• Industrial Control

• IPTV POF

• SOHO Residential Gatewa y with f ul l wire speed of four

LAN Ports

• Broadband Gateway/Firewall/VPN

• Integrated DSL/Cable Modem

• Wireless LAN acc ess point + gateway

• Standalone 10/100 switch

• Networked Measure m ent and Control Systems

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KSZ8794CNX

Ordering I nfor m ati on

Part Number

Temperatur e Range

Package

Lead Finish/Grade

KSZ8794CNXCC 0°C to 70°C 64-Pin QFN Pb-Free/Commercial

KSZ8794CNXIC -40°C to +85°C 64-Pin QFN Pb-Free/Industrial

KSZ8794CNX-EVAL Evaluation B oard

Revision Hi stor y

Revision Date Description

1.0 06/03/14 Initial document created

1.0 07/18/14 MarCom formatting/reflow of initial submissio n datasheet. D.Tanabe

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Contents

General Descripti on ................................................................................................................................................................ 1

Functional Diagram ................................................................................................................................................................. 1

Highlights and Features .......................................................................................................................................................... 2

Management Capabi l ities ................................................................................................................................................... 2

Robust PHY Ports ............................................................................................................................................................... 2

MAC and GMAC Ports ........................................................................................................................................................ 2

Advanced Switch Capabilities............................................................................................................................................. 2

Configuration Registers Access ......................................................................................................................................... 3

Power and Power Management ......................................................................................................................................... 3

Additional Features ............................................................................................................................................................. 3

Packaging and Environmental ............................................................................................................................................ 3

Target Applications ............................................................................................................................................................. 3

Ordering Information ............................................................................................................................................................... 4

Revision History ...................................................................................................................................................................... 4

Contents .................................................................................................................................................................................. 5

List of Figures ........................................................................................................................................................................ 13

List of Tables ......................................................................................................................................................................... 14

Pin Configuration ................................................................................................................................................................... 15

Pin Description ...................................................................................................................................................................... 16

Strap-in Options .................................................................................................................................................................... 21

Introduction ............................................................................................................................................................................ 22

Functional Overv i ew: Physical Layer (PHY) ......................................................................................................................... 22

100BASE-TX Transmit ..................................................................................................................................................... 22

100BASE-TX Receive ...................................................................................................................................................... 22

PLL Clock Synthesizer ...................................................................................................................................................... 22

Scrambler/Descrambler (100BASE-TX only) ................................................................................................................... 22

Straight Cable ............................................................................................................................................................... 24

Crossover Cable ........................................................................................................................................................... 24

Auto-Negotiation ................................................................................................................................................................... 25

LinkMD® Cable Diagnostics .................................................................................................................................................. 27

Access .......................................................................................................................................................................... 27

Usage ........................................................................................................................................................................... 27

A LinkMD example ....................................................................................................................................................... 28

On-chip Termination and Internal Biasing ........................................................................................................................ 28

Functional Overv i ew: M edia Access Controlle r (MAC) ......................................................................................................... 29

Media Access Cont roll er (MAC) Operation ...................................................................................................................... 29

Inter-Packet Gap (IPG) ................................................................................................................................................. 29

Back-off Algorithm ........................................................................................................................................................ 29

Late Collision ................................................................................................................................................................ 29

Illegal Frames ............................................................................................................................................................... 29

Flow Control .................................................................................................................................................................. 29

Half-Duplex Back P re ssu r e .......................................................................................................................................... 29

Broadcast Storm Protection .......................................................................................................................................... 30

Functional Overv i ew: S witch Core ........................................................................................................................................ 31

Address Look-Up .............................................................................................................................................................. 31

Learning ............................................................................................................................................................................ 31

Migration ........................................................................................................................................................................... 31

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Aging ................................................................................................................................................................................. 31

Forwarding ........................................................................................................................................................................ 31

Switching Engine .............................................................................................................................................................. 32

Functional Overv i ew: P ower ................................................................................................................................................. 33

Functional Overv i ew: Power Management ........................................................................................................................... 33

Normal Operation M ode ................................................................................................................................................... 33

Energy Detect Mode ......................................................................................................................................................... 33

Soft Power-Down Mode .................................................................................................................................................... 34

Port-based Power-Down Mode ........................................................................................................................................ 34

Energy Efficient Ethernet (EEE) ....................................................................................................................................... 34

LPI Signaling................................................................................................................................................................. 35

LPI Assertion ................................................................................................................................................................ 35

LPI Detection ................................................................................................................................................................ 36

PHY LPI Transmi t Operation ........................................................................................................................................ 36

PHY LPI Receive Oper ation ......................................................................................................................................... 37

Negotiation with E EE Capability ................................................................................................................................... 37

Wake on LAN (WoL) ............................................................................................................................................................. 38

Direction of Energ y ....................................................................................................................................................... 38

Direction of Link-up ....................................................................................................................................................... 38

Magic Packet™ ............................................................................................................................................................ 38

Interrupt (INT_N/PME_N) ...................................................................................................................................................... 39

Functional Overv i ew: Interfaces ............................................................................................................................................ 40

Configuration Interface ..................................................................................................................................................... 40

SPI Slave Serial Bus Configuration .............................................................................................................................. 40

MII Management I nterface (MIIM) ................................................................................................................................ 43

Standard Media I ndependent Interface [ M II] ................................................................................................................ 44

Reduced Media Independent Interface [RMII] .............................................................................................................. 44

Reduced Gigabit Medi a Independent Interface [RGMII] .............................................................................................. 44

Port 4 GMAC4 SW4-RGMII Interface ........................................................................................................................... 45

Functional Overv i ew: A dvanced Functionality ...................................................................................................................... 48

QoS Priority Suppo rt ......................................................................................................................................................... 48

Port-based Priority ........................................................................................................................................................ 48

802.1p-based Priority ................................................................................................................................................... 48

DiffServ-Based Priority ................................................................................................................................................. 49

Spanning Tree Support ..................................................................................................................................................... 50

Rapid Spanning Tre e Support .......................................................................................................................................... 51

Tail Tagging Mode ............................................................................................................................................................ 52

IGMP Support ................................................................................................................................................................... 53

IGMP Snooping ............................................................................................................................................................ 53

IGMP Send Back to the Subscribed Port ..................................................................................................................... 53

IPv6 MLD Snooping .......................................................................................................................................................... 53

Port Mirroring S upport ...................................................................................................................................................... 53

“Receive Only” mirror on a Port .................................................................................................................................... 53

“Transmit Only” mirror on a Port ................................................................................................................................... 53

“Receive and Tran smit” mirror on two Port s ................................................................................................................. 53

VLAN Support ................................................................................................................................................................... 54

Ingress Rate Limit ......................................................................................................................................................... 56

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Egress Rate Limit ......................................................................................................................................................... 56

Transmit Queue Ratio Programming ............................................................................................................................ 56

802.1X Port-Based Security ............................................................................................................................................. 57

Authentication Register and Program ming Model ........................................................................................................ 58

ACL Filtering ..................................................................................................................................................................... 58

Access Control Li sts ..................................................................................................................................................... 58

Matching Field .............................................................................................................................................................. 60

Action Field ................................................................................................................................................................... 61

Processing Field ........................................................................................................................................................... 61

DOS Attack Prevention via ACL ................................................................................................................................... 62

Device Registers Mapping .................................................................................................................................................... 63

Direct Regi ster Description ................................................................................................................................................... 64

Global Registers .................................................................................................................................................................... 66

Register 0 (0x00): Chip ID0 .......................................................................................................................................... 66

Register 1 (0x01): Chip ID1 / Start Switch .................................................................................................................... 66

Register 2 (0x02): Gl obal Control 0 .............................................................................................................................. 66

Register 3 (0x03): Gl obal Control 1 .............................................................................................................................. 67

Register 4 (0x04): Gl obal Control 2 .............................................................................................................................. 68

Register 6 (0x06): Global Control 4 .............................................................................................................................. 69

Register 7 (0x07): Gl obal Control 5 .............................................................................................................................. 69

Register 8 (0x08): Gl obal Control 6 MIB Control .......................................................................................................... 70

Register 9 (0x09): Gl obal Control 7 .............................................................................................................................. 70

Register 10 (0x0A ): Gl obal Control 8 ........................................................................................................................... 70

Register 11 (0x0B ): Gl obal Control 9 ........................................................................................................................... 71

Register 12 (0x0C): Gl obal Control 10 ......................................................................................................................... 72

Register 13 (0x0D): Gl obal Control 11 ......................................................................................................................... 72

Register 14 (0x0E ): Power Down Management Control 1 ........................................................................................... 72

Register 15 (0x0F): Power Down Management Control 2 ........................................................................................... 72

Port Registers........................................................................................................................................................................ 73

Register 16 (0x10): P ort 1 Control 0 ............................................................................................................................. 73

Register 32 (0x20): P ort 2 Control 0 ............................................................................................................................. 73

Register 48 (0x30): P ort 3 Control 0 ............................................................................................................................. 73

Register 64 (0x40): Reserved ....................................................................................................................................... 73

Register 80 (0x50): P ort 4 Control 0 ............................................................................................................................. 73

Register 17 (0x11): Port 1 Control 1 ............................................................................................................................. 74

Register 33 (0x21): P ort 2 Control 1 ............................................................................................................................. 74

Register 49 (0x31): P ort 3 Control 1 ............................................................................................................................. 74

Register 65 (0x41): Reserved ....................................................................................................................................... 74

Register 81 (0x51): P ort 4 Control 1 ............................................................................................................................. 74

Register 18 (0x12): P ort 1 Control 2 ............................................................................................................................. 75

Register 34 (0x22): P ort 2 Control 2 ............................................................................................................................. 75

Register 50 (0x32): P ort 3 Control 2 ............................................................................................................................. 75

Register 66 (0x42): Reserved ....................................................................................................................................... 75

Register 82 (0x52): P ort 4 Control 2 ............................................................................................................................. 75

Register 19 (0x13): P ort 1 Control 3 ............................................................................................................................. 75

Register 35 (0x23): P ort 2 Control 3 ............................................................................................................................. 75

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Register 51 (0x33): P ort 3 Control 3 ............................................................................................................................. 75

Register 67 (0x43): Reserved ....................................................................................................................................... 75

Register 83 (0x53): P ort 4 Control 3 ............................................................................................................................. 75

Register 20 (0x14): P ort 1 Control 4 ............................................................................................................................. 76

Register 36 (0x24): P ort 2 Control 4 ............................................................................................................................. 76

Register 52 (0x34): P ort 3 Control 4 ............................................................................................................................. 76

Register 68 (0x44): Reserved ....................................................................................................................................... 76

Register 84 (0x54): P ort 4 Control 4 ............................................................................................................................. 76

Register 21 (0x15): Port 1 Contr ol 5 ............................................................................................................................. 76

Register 37 (0x25): Port 2 Contr ol 5 ............................................................................................................................. 76

Register 53 (0x35): Port 3 Contr ol 5 ............................................................................................................................. 76

Register 69 (0x45): Reserved ....................................................................................................................................... 76

Register 85 (0x55): Port 4 Contr ol 5 ............................................................................................................................. 76

Register 22 (0x16): Reserved ....................................................................................................................................... 76

Register 38 (0x26): Reserved ....................................................................................................................................... 76

Register 54 (0x36): Reserved ....................................................................................................................................... 76

Register 70 (0x46): Reserved ....................................................................................................................................... 76

Register 86 (0x56): Port 4 Interface Control 6 .............................................................................................................. 77

Register 23 (0x17): P ort 1 Control 7 ............................................................................................................................. 78

Register 39 (0x27): Port 2 Contr ol 7 ............................................................................................................................. 78

Register 55 (0x37): Port 3 Contr ol 7 ............................................................................................................................. 78

Register 71 (0x47): Reserved ....................................................................................................................................... 78

Register 87 (0x57): Reserved ....................................................................................................................................... 78

Register 24 (0x18): Port 1 Status 0 .............................................................................................................................. 79

Register 40 (0x28): Port 2 Status 0 .............................................................................................................................. 79

Register 56 (0x38): Port 3 Status 0 .............................................................................................................................. 79

Register 72 (0x48): Reserved ....................................................................................................................................... 79

Register 87 (0x57): Reserved ....................................................................................................................................... 79

Register 25 (0x19): P ort 1 Status 1 .............................................................................................................................. 80

Register 41 (0x29): P ort 2 Status 1 .............................................................................................................................. 80

Register 57 (0x39): P ort 3 Status 1 .............................................................................................................................. 80

Register 73 (0x49): Reserved ....................................................................................................................................... 80

Register 89 (0x59): Reserved ....................................................................................................................................... 80

Register 26 (0x1A ): Port 1 PHY Control 8 .................................................................................................................... 81

Register 42 (0x2A ): Port 2 PHY Control 8 .................................................................................................................... 81

Register 58 (0x3A ): Port 3 PHY Control 8 .................................................................................................................... 81

Register 74 (0x4A ): Reserved ...................................................................................................................................... 81

Register 90 (0x5A): Reserved ...................................................................................................................................... 81

Register 27 (0x1B ): Port 1 LinkMD result ..................................................................................................................... 82

Register 43 (0x2B ): Port 2 LinkMD result ..................................................................................................................... 82

Register 59 (0x3B): Port 3 LinkMD result ..................................................................................................................... 82

Register 75 (0x4B ): Reserved ...................................................................................................................................... 82

Register 91 (0x5B ): Reserved ...................................................................................................................................... 82

Register 28 (0x1C): P ort 1 Control 9 ............................................................................................................................ 82

Register 44 (0x2C): P ort 2 Control 9 ............................................................................................................................ 82

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Register 60 (0x3C): P ort 3 Control 9 ............................................................................................................................ 82

Register 76 (0x4C): Reserved ...................................................................................................................................... 82

Register 92 (0x5C): Reserved ...................................................................................................................................... 82

Register 29 (0x1D): P ort 1 Control 10 .......................................................................................................................... 83

Register 45 (0x2D): P ort 2 Control 10 .......................................................................................................................... 83

Register 61 (0x3D): Port 3 Control 10 .......................................................................................................................... 83

Register 77 (0x4D): Reserved ...................................................................................................................................... 83

Register 93 (0x5D): Reserved ...................................................................................................................................... 83

Register 30 (0x1E ): Port 1 Status 2 .............................................................................................................................. 84

Register 46 (0x2E ): Port 2 Status 2 .............................................................................................................................. 84

Register 62 (0x3E ): Port 3 Status 2 .............................................................................................................................. 84

Register 78 (0x4E ): Reserved ...................................................................................................................................... 84

Register 94 (0x5E ): Reserved ...................................................................................................................................... 84

Register 31 (0x1F): Port 1 Control 11 and S t atus 3 ..................................................................................................... 84

Register 47 (0x2F): Port 2 Control 11 and S t atus 3 ..................................................................................................... 84

Register 63 (0x3F): Port 3 Control 11 and S t atus 3 ..................................................................................................... 84

Register 79 (0x4F): Reserved ...................................................................................................................................... 84

Register 95 (0x5F): Reserved ...................................................................................................................................... 84

Advanced Control Re gist ers ................................................................................................................................................. 86

Register 104 (0x68): MAC Address Register 0 ............................................................................................................ 86

Register 105 (0x69): MAC Address Register 1 ............................................................................................................ 86

Register 106 (0x6A ): M AC Address Regi st er 2 ............................................................................................................ 86

Register 107 (0x6B ): M AC Address Regi st er 3 ............................................................................................................ 86

Register 108 (0x6C ): M A C Address Register 4 ............................................................................................................ 86

Register 110 (0x6E ): Indirect Access C ontrol 0 ........................................................................................................... 87

Register 111 (0x6F): Indirect Access C ontrol 1 ............................................................................................................ 87

Register 112 (0x70): Indirect Data Register 8 .............................................................................................................. 88

Register 113 (0x71): Indirect Data Register 7 .............................................................................................................. 88

Register 114 (0x72): Indirect Data Register 6 .............................................................................................................. 88

Register 115 (0x73): Indirect Data Register 5 .............................................................................................................. 88

Register 116 (0x74): Indirect Data Register 4 .............................................................................................................. 88

Register 117 (0x75): Indirect Data Register 3 .............................................................................................................. 88

Register 118 (0x76): Indirect Data Register 2 .............................................................................................................. 88

Register 119 (0x77): Indirect Data Register 1 .............................................................................................................. 88

Register 120 (0x78): Indirect Data Register 0 .............................................................................................................. 88

Register 160 (0XA0): Indirect Byte Register (It is for PME, EEE and ACL Registers) ................................................. 88

Register 124 (0x7C ): Interrupt Status Regi ster ............................................................................................................ 89

Register 125 (0x7D ): Interrupt Mask Register .............................................................................................................. 89

Register 126 (0x7E): ACL Interrupt Status Register .................................................................................................... 89

Register 127 (0x7F): ACL Interrupt Control Register ................................................................................................... 89

Register 128 (0x80): Global Control 12 ........................................................................................................................ 90

Register 129 (0x81): Global Control 13 ........................................................................................................................ 90

Register 130 (0x82): Global Control 14 ........................................................................................................................ 90

Register 131 (0x83): Global Control 15 ........................................................................................................................ 91

Register 132 (0x84): Global Control 16 ........................................................................................................................ 91

Register 134 (0x86): Global Control 18 ........................................................................................................................ 92

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Register 135 (0x87): Global Control 19 ........................................................................................................................ 92

Register 144 (0x90): TOS Priority Control Register 0 .................................................................................................. 93

Register 145 (0x91): TOS Priority Control Register 1 .................................................................................................. 93

Register 146 (0x92): TOS Priority Control Register 2 .................................................................................................. 93

Register 147 (0x93): TOS P riori t y Control Register 3 .................................................................................................. 93

Register 148 (0x94): TOS Priority Control Register 4 .................................................................................................. 93

Register 149 (0x95): TOS Priority Control Register 5 .................................................................................................. 94

Register 150 (0x96): TOS Priority Control Register 6 .................................................................................................. 94

Register 151 (0x97): TOS Priority Control Register 7 .................................................................................................. 94

Register 152 (0x98): TOS Priority Control Register 8 .................................................................................................. 94

Register 153 (0x99): TOS Priority Control Register 9 .................................................................................................. 94

Register 154 (0x9A): TOS P riority Cont r ol Register 10 ................................................................................................ 94

Register 155 (0x9B ): T OS Priority Control Register 11 ................................................................................................ 94

Register 156 (0x9C ): TO S P riority Control Regist er 12 ............................................................................................... 95

Register 157 (0x9D ): TO S P riority Control Regist er 13 ............................................................................................... 95

Register 158 (0x9E ): T OS Priority Control Register 14 ................................................................................................ 95

Register 159 (0x9F): TOS Priority Cont rol Register 15 ................................................................................................ 95

Register 163 (0XA3): Gl obal Control 20 ....................................................................................................................... 96

Register 164 (0XA4): Gl obal Control 21 ....................................................................................................................... 96

Register 176 (0xB 0): Port 1 Control 12 ........................................................................................................................ 97

Register 192 (0xC0 ): P ort 2 Control 12 ........................................................................................................................ 97

Register 208 (0xD0 ): P ort 3 Control 12 ........................................................................................................................ 97

Register 224 (0xE0): Reserved .................................................................................................................................... 97

Register 240 (0xF0): Port 4 Control 12 ........................................................................................................................ 97

Register 177 (0xB 1): Port 1 Control 13 ........................................................................................................................ 98

Register 193 (0xC1 ): P ort 2 Control 13 ........................................................................................................................ 98

Register 209 (0xD1 ): P ort 3 Control 13 ........................................................................................................................ 98

Register 225 (0xE1): Reserved .................................................................................................................................... 98

Register 241 (0xF1): Port 4 Control 13 ........................................................................................................................ 98

Register 178 (0xB 2): Port 1 Control 14 ........................................................................................................................ 98

Register 194 (0xC2 ): P ort 2 Control 14 ........................................................................................................................ 98

Register 210 (0xD2 ): P ort 3 Control 14 ........................................................................................................................ 98

Register 226 (0xE2): Reserved .................................................................................................................................... 98

Register 242 (0xF2): Port 4 Control 14 ........................................................................................................................ 98

Register 179 (0xB 3): Port 1 Control 15 ........................................................................................................................ 99

Register 195 (0xC3 ): P ort 2 Control 15 ........................................................................................................................ 99

Register 211 (0xD3 ): P ort 3 Control 15 ........................................................................................................................ 99

Register 227 (0xE3): Reserved .................................................................................................................................... 99

Register 243 (0xF3): Port 4 Control 15 ........................................................................................................................ 99

Register 180 (0xB4): Port 1 Control 16 ........................................................................................................................ 99

Register 196 (0xC4 ): P ort 2 Control 16 ........................................................................................................................ 99

Register 212 (0xD4 ): P ort 3 Control 16 ........................................................................................................................ 99

Register 228 (0xE4): Reserved .................................................................................................................................... 99

Register 244 (0xF4): Port 4 Control 16 ........................................................................................................................ 99

Register 181 (0xB 5): Port 1 Control 17 ........................................................................................................................ 99

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KSZ8794CNX

Register 197 (0xC5 ): P ort 2 Control 17 ........................................................................................................................ 99

Register 213 (0xD5 ): P ort 3 Control 17 ........................................................................................................................ 99

Register 229 (0xE5): Reserved .................................................................................................................................... 99

Register 245 (0xF5): Port 4 Control 17 ........................................................................................................................ 99

Register 182 (0xB 6): Port 1 Rate Limit Contr ol .......................................................................................................... 100

Register 198 (0xC6 ): P ort 2 Rate Limit Control .......................................................................................................... 100

Register 214 (0xD6 ): P ort 3 Rate Limit Control .......................................................................................................... 100

Register 230 (0xE6): Reserved .................................................................................................................................. 100

Register 246 (0xF6): Port 4 Rate Limit Cont rol .......................................................................................................... 100

Register 183 (0xB7): Port 1 Priority 0 Ingress Limit C ontrol 1(4) ................................................................................. 100

Register 199 (0xC7 ): P ort 2 Priority 0 Ingress Limit Control 1 ................................................................................... 100

Register 215 (0xD7 ): P ort 3 Priority 0 Ingress Limit Control 1 ................................................................................... 100

Register 231 (0xE7): Reserved .................................................................................................................................. 100

Register 247 (0xF7): Port 4 Priority 0 Ingress Limit Co nt rol 1 .................................................................................... 100

Register 184 (0xB8): Port 1 Priority 1 Ingress Limit C ontrol 2(4) ................................................................................. 101

Register 200 (0xC8 ): P ort 2 Priority 1 Ingress Limit Control 2 ................................................................................... 101

Register 216 (0xD8 ): P ort 3 Priority 1 Ingress Limit Control 2 ................................................................................... 101

Register 232 (0xE8): Reserved .................................................................................................................................. 101

Register 248 (0xF8): Port 4 Priority 1 Ingress Limit Co nt rol 2 .................................................................................... 101

Register 185 (0xB9): Port 1 Priority 2 Ingress Limit C ontrol 3(4) ................................................................................. 101

Register 201 (0xC9 ): P ort 2 Priority 2 Ingress Limit Control 3 ................................................................................... 101

Register 217 (0xD9 ): P ort 3 Priority 2 Ingress Limit Control 3 ................................................................................... 101

Register 233 (0xE9): Reserved .................................................................................................................................. 101

Register 249 (0xF9): Port 4 Priority 2 Ingress Limit Control 3 .................................................................................... 101

Register 186 (0xBA): Port 1 Priority 3 Ingress Limit C ont rol 4(4) ................................................................................ 102

Register 202 (0xCA): Port 2 Priority 3 Ingress Limit Control 4 ................................................................................... 102

Register 218 (0xDA): Port 3 Priority 3 Ingress Limit Control 4 ................................................................................... 102

Register 234 (0xEA): Reserved .................................................................................................................................. 102

Register 250 (0xFA ): P ort 4 Priority 3 Ingress Limit Control 4 ................................................................................... 102

Register 187 (0xBB): Port 1 Queue 0 Egre ss Limit Control 1(5) ................................................................................. 103

Register 203 (0xCB): Port 2 Queue 0 Egress Limit Control 1 .................................................................................... 103

Register 219 (0xDB): Port 3 Queue 0 Egre ss Limit Control 1 .................................................................................... 103

Register 235 (0xEB): Reserved .................................................................................................................................. 103

Register 251 (0xFB ): P ort 4 Queue 0 Egress Limit Control 1 .................................................................................... 103

Register 188 (0xBC) : Port 1 Queue 1 Egress Limit Control 2(5) ................................................................................ 103

Register 204 (0xCC) : Port 2 Queue 1 Egress Limit Control 2 ................................................................................... 103

Register 220 (0xDC) : Port 3 Queue 1 Egress Lim i t Control 2 ................................................................................... 103

Register 236 (0xEC) : Reserved................................................................................................................................. 103

Register 252 (0xFC) : Port 4 Queue 1 E gress Limit Control 2 ................................................................................... 103

Register 189 (0xB D): Port 1 Queue 2 Egress Limit Control 3(5) ................................................................................. 103

Register 205 (0xC D): Port 2 Queue 2 Egress Limit Control 3 .................................................................................... 103

Register 221 (0xD D): Port 3 Queue 2 Egress Limit Control 3 .................................................................................... 103

Register 237 (0xED): Reserve d .................................................................................................................................. 103

Register 253 (0xFD): Port 4 Queue 2 Egress Limit Control 3 .................................................................................... 103

Register 190 (0xBE) : P ort 1 Queue 3 Egress Limit Control 4(5) ................................................................................ 103

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KSZ8794CNX

Register 206 (0xCE) : Port 2 Queue 3 Egre ss Limit Control 4 ................................................................................... 103

Register 222 (0xDE) : Port 3 Queue 3 Egress Limit Control 4 ................................................................................... 103

Register 238 (0xEE): Reserved .................................................................................................................................. 103

Register 254 (0xFE ): P ort 4 Queue 3 Egress Limit Control 4 .................................................................................... 103

Register 191(0xB F): Testing Regist er ........................................................................................................................ 104

Register 207(0xCF): Reserved Control Register ....................................................................................................... 104

Register 223(0xDF): Test Register 2 .......................................................................................................................... 104

Register 239(0xE F): Test Register 3 .......................................................................................................................... 104

Register 255(0xFF): Test Register 4 .......................................................................................................................... 104

Indirect Register Description ............................................................................................................................................... 105

Static MAC Address Table .................................................................................................................................................. 106

VLAN Table ......................................................................................................................................................................... 108

Dynamic MAC Addres s Table ............................................................................................................................................. 110

PME Indirect Registers ....................................................................................................................................................... 112

Programming Examples: ..................................................................................................................................................... 113

Read Operation .......................................................................................................................................................... 113

Write Operation .......................................................................................................................................................... 113

ACL Rule Table and AC L I ndi rect Registers ....................................................................................................................... 114

ACL Register and P rogramming Model ...................................................................................................................... 114

ACL Indirect Registers ................................................................................................................................................ 115

EEE Indirect Registers ........................................................................................................................................................ 124

EEE Global Register s ..................................................................................................................................................... 124

Management Inf orm at i on Base (MIB) Counters ................................................................................................................. 133

MIIM Registers .................................................................................................................................................................... 137

Absolute Maximum Ratings(6) ............................................................................................................................................. 141

Operating Rat ings(7) ............................................................................................................................................................ 141

Electrical Characteristics(9,10) ............................................................................................................................................... 141

Timing Diagrams ................................................................................................................................................................. 143

RGMII Timing .................................................................................................................................................................. 143

MII Timing ....................................................................................................................................................................... 144

RMII Timing..................................................................................................................................................................... 146

SPI Timing ...................................................................................................................................................................... 147

Auto-Negotiation Timing ................................................................................................................................................. 148

MDC/MDIO Timing ......................................................................................................................................................... 149

Power-down/Power-up and Reset Timing ...................................................................................................................... 150

Reset Circuit Diagram ......................................................................................................................................................... 151

Selection of Refer ence Crystal ............................................................................................................................................ 152

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA ..................................................................... 154

Template Revision History .................................................................................................................................................. 155

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KSZ8794CNX

List of Figures

Figure 1. Typical St raight Cable Connection ....................................................................................................................... 24

Figure 2. Typical Cro ssover Cable Connect i on ................................................................................................................... 24

Figure 3. Auto-Negotiation and Parallel Oper ation .............................................................................................................. 26

Figure 4. Destination A ddress Lookup and Resolution Flow Chart ..................................................................................... 32

Figure 5. EEE Transmit and Receive Si gnali ng Paths ........................................................................................................ 35

Figure 6. Traffic Activity and EEE LPI Operations ............................................................................................................... 37

Figure 7. SPI Access Timing ................................................................................................................................................ 41

Figure 8. SPI Multiple Access Timing .................................................................................................................................. 42

Figure 9. 802.1p Priorit y Field Format ................................................................................................................................. 48

Figure 10. Tail Tag Frame Format ....................................................................................................................................... 52

Figure 11. ACL Format ......................................................................................................................................................... 59

Figure 12. Interf ace and Register Mapping .......................................................................................................................... 63

Figure 13. ACL Table Access ............................................................................................................................................ 114

Figure 14. RGMI I v2.0 Specification (Fi gure3-Multiplex i ng and T iming Diagram) ............................................................. 143

Figure 15. MAC Mode MII Timing – Data Receiv ed from MII ............................................................................................ 144

Figure 16. MAC Mode MII Timing – Data Transmitted from MII ........................................................................................ 144

Figure 17. PHY Mode MII Timing – Data Received from M II ............................................................................................. 145

Figure 18. PHY Mode MII Timing – Data Transmitted from MII ......................................................................................... 145

Figure 19. RMII Timing – Data Rec ei ved from RMII .......................................................................................................... 146

Figure 20. RMII Timing – Data Transmitted to RMII .......................................................................................................... 146

Figure 21. SPI Input Timing ............................................................................................................................................... 147

Figure 22. Auto-Negotiation Timing ................................................................................................................................... 148

Figure 23. MDC/MDIO Timing ............................................................................................................................................ 149

Figure 27. Reset Timi ng ..................................................................................................................................................... 150

Figure 28. Recomm ended Reset Circuit ............................................................................................................................ 151

Figure 29. Recomm ended Circuit for Interfacing with CPU/FP G A Reset .......................................................................... 151

Figure 30. 64-Pin (8mm x 8mm) QFN Package ................................................................................................................. 153

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KSZ8794CNX

List of Tables

Table 1. MDI/MDI -X Pin Definitions ...................................................................................................................................... 23

Table 2. Internal Function Block Status ................................................................................................................................ 33

Table 3. Available Interfaces ................................................................................................................................................ 40

Table 4. SPI Connections .................................................................................................................................................... 40

Table 5. MII Manag ement Interface Frame Format .............................................................................................................. 43

Table 6. Signals of RGMII/MII/RMII ...................................................................................................................................... 44

Table 7. Port 4 SW4-RGMII Connection .............................................................................................................................. 45

Table 8. Port 4 SW4-RGMII Clock Dela y Configuration hwit Connection Partner.= ........................................................... 45

Table 9. Port 4 SW4-MII Connection ................................................................................................................................... 46

Table 10. Port 4 SW4-RMII Connection ................................................................................................................................ 47

Table 11. Tail Tag Rule s ....................................................................................................................................................... 52

Table 12. FID+DA Look-Up in the VLAN Mode ................................................................................................................... 54

Table 13. FID+SA Look-Up in the VLAN Mode ................................................................................................................... 54

Table 14. 10/100/1000Mbps Rate Selection for the Rate limit ............................................................................................ 55

Table 15. Mapping of Functional Areas within the Address Sp ace ..................................................................................... 63

Table 16. Static MAC Address Table ................................................................................................................................. 106

Table 17. VLAN Table ........................................................................................................................................................ 108

Table 18. VLAN ID and Indirect Registers .......................................................................................................................... 109

Table 19. Dynamic MAC Address Table ............................................................................................................................ 110

Table 20. PME Indirect Registers ...................................................................................................................................... 112

Table 21. ACL Indire ct Registers for 14 Byt es A CL Rules ................................................................................................. 115

Table 22. Temporal st orage for 14 Bytes ACL Rules ......................................................................................................... 120

Table 23. ACL Read and Write Control .............................................................................................................................. 121

Table 24. Port 1 MI B Counter Indirect Memory O f ferts ...................................................................................................... 133

Table 25. Format of “Per Port” MIB Counter ....................................................................................................................... 134

Table 26. All Port Dropped Packet MIB Counters ............................................................................................................... 134

Table 27. Format of Per Port RX/TX Total Bytes MIB Counter .......................................................................................... 135

Table 28. Format of “All Dropped Packet” MIB Counter ..................................................................................................... 135

Table 29. RGMII v2.0 Specification (Timing Specifics from Table 2) ................................................................................. 143

Table 30. MAC Mode MII Timing Parameters ..................................................................................................................... 144

Table 31. PHY Mode MII Timing Parameters ..................................................................................................................... 145

Table 32. RMII Timing Parameters ..................................................................................................................................... 146

Table 33. SPI Input Timing Parameters .............................................................................................................................. 147

Table 34. Auto-Negotiation Timing Parameters .................................................................................................................. 148

Table 35. MDC/MDIO Typical Timing Parameters .............................................................................................................. 149

Table 36. Reset Timing Parameters ................................................................................................................................... 150

Table 37. Transfor mer Select ion Crite ri a ............................................................................................................................ 152

Table 38. Qualified Magnetic Vendors ................................................................................................................................ 152

Table 39. Typical R ef erence Crystal Characteristics .......................................................................................................... 152

July 24, 2014 14 Revision 1.0

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KSZ8794CNX

Pin Configuration

64-Pin QFN Pin Configuration

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KSZ8794CNX

Pin Description

Pin Number

Pin Name

Type

(1)

Port

Pin Function

1 VDD12A P 1.2V Core Power

2 VDDAT P 3.3V Analog P ower

3 GNDA GND Analog Ground

4 RXP1 I 1 Port 1 Physical receive signal + (differential)

5 RXM1 I 1 Port 1 Physical receive signal - (differential)

6 TXP1 O 1 Port 1 Physical transmit signal + (differential)

7 TXM1 O 1 Port 1 Physical transmit signal - (differential)

8 RXP2 I 2 Port 2 Physical receive signa l + (differential)

9 RXM2 I 2 Port 2 Physical receive signal - (differential)

10 TXP2 O 2 Port 2 Ph ysic al transmit signal + (differential)

11 TXM2 O 2 Port 2 Physical transmit signal - (differential)

12 VDDAT P 3.3V Analog Power

13 RXP3 I 3 Port 3 Physical receive signal + (differential )

14 RXM3 I 3 Port 3 Physical receiv e s ignal - (differential)

15 TXP3 O 3 Port 3 Physical transmit signal + (differential)

16 TXM3 O 3 Port 3 Physical transmit signal – (differential)

17 GNDA GND Analog Ground.

18 INTR_N Opu Interrupt: Active low

This pin is Open-Drain output pin.

19 LED3_1 Ipu/O 3

Port 3 LED Indicator 1

See global Register 11 bits [5:4] for details.

Strap Option: Switch Port 4 GMAC4 Interface Mode Select by

LED3[1:0]

00 = MII for SW 4-MII

01 = RMII for SW4-RMII

10 = Reserved

11 = RGMII for SW4-RGMII (Default)

20 LED3_0 Ipu/O 3 Port 3 LED Indicator 0

See global Register 11 bits [5:4] for details.

Strap Option: see LED3_1

21 VDD12D P 1.2V Core Power.

22 GNDD GND Digital Gr ound.

Notes:

1. P = Power supply.

I = Input.

O = Output.

I/O = Bidirectional.

GND = Ground.

Ipu = Input w/internal pull-up.

Ipd = Input w/internal pull-down.

Ipd/O = Input w/internal pull-down during reset, output pin otherwise.

Ipu/O = Input w/internal pull-up during reset, output pin otherwise.

OTRI = Output tristated.

PU = Strap pin pull-up.

PD = Strap pull-down.

NC = No connect or tie to ground for this product only.

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KSZ8794CNX

Pin Description (Continued)

Pin Number

Pin Name

Type

(1)

Port

Pin Function

23 TXEN4/TXD4_CTL Ipd 4

MII/RMII:

Port 4 Switch tr ansmit enable .

RGMII:

Transmit data control.

24 TXD4_0 Ipd 4 RGMII/MII/RMII:

Port 4 Switch transmit bit [0].

25 TXD4_1 Ipd 4 RGMII/MII/RMII:

Port 4 Switch transmit bit [1].

26 GNDD GND Digital Ground.

27 VDDIO P 3.3V, 2.5V or 1.8V digital VDD for digital I/O circuitry.

28 TXD4_2 Ipd 4

RGMII/MII:

Port 4 Switch transmit bit [2].

RMII:

No connection.

29 TXD4_3 Ipd 4

RGMII/MII:

Port 4 Switch transmit bit [3].

RMII:

No connection.

30 TXER4 Ipd 4

MII:

Port 4 Switch transmit error.

RGMII/RMII:

No connection.

31 NC NC No Connect

32 GNDD GND Digital Ground

33 VDD12D P 1.2V Core Power

34 TXC4/REFCLKI4

/GTXC4 I/O 4

Port 4 Switch GMAC4 Clock Pin

MII: 2.5/25MHz clock, PHY mode is output, MAC mode is input.

RMII: Input for receiving 5 0MHz clock in n ormal mode

RGMII: Input 125MHz clock with falling and rising edge to latch data for

the transmit.

35 RXC4/GRXC4 I/O 4

Port 4 Switch GMAC4 Clock Pin

MII: 2.5/25MHz clock, PHY mode is output, MAC mode is input.

RMII: Output 50MHz reference clock for the receiving/transmit in the

clock mode.

RGMII: Output 125MHz clock with falling and rising edge to latch data

for the receiving.

36 RXD4_0 Ipd/O 4 RGMII/MII/RMII:

Port 4 Switch receiv e bi t [0].

37 RXD4_1 Ipd/O 4 RGMII/MII/RMII:

Port 4 Switch receiv e bi t [1].

38 GNDD GND Digital Ground.

39 VDDIO P 3.3V, 2.5V or 1.8V digital VDD for digital I/O circuitry.

40 RXD4_2 Ipd/O 4

RGMII/MII:

Port 4 Switch receiv e bi t [2].

RMII:

No connection.

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Micrel, Inc.

KSZ8794CNX

Pin Description (Continued)

Pin Number

Pin Name

Type

(1)

Port

Pin Function

41 RXD4_3 Ipd/O 4

RGMII/MII:

Port 4 Switch receiv e bi t [3].

RMII:

No connection.

42 RXDV4/CRSDV4

/RXD4_CTL Ipd/O 4

MII:

RXDV4 is for Port 4 Switch GMII/MII receive dat a valid.

RMII:

CRSDV4 is for Port 4 RMII carrier sense/receive data valid output.

RGMII:

RXD4_CTL is for Port 4 RGMII receiv e data control

43 RXER4 Ipd/O 4

MII:

Port 4 Switch receives error.

RGMII/RMII:

No connection.

44 CRS4 Ipd/O 4

MII:

Port 4 Switch MII m odes carrier sense.

RGMII/RMII:

No connection.

45 COL4 Ipd/O 4

MII:

Port 4 Switch MII collision detects.

RGMII/RMII:

No connection.

46 REFCLKO Ipu/O 25MHz Clock Output (Option)

Controlled by the strap pin LED 2_0.

Default is enab l ed, it is better to di s abled it if not be used.

47 PME_N I/O

Power Man agement Event

This output s i gnal indicates that a Wake On LAN event has been

detected as a res ul t of a Wake-Up frame being detected. The

KSZ8794CNX is requesting the system to wake up from low power

mode. Its assertion polarit y is programmab le with the default polarity

to be active low.

48 LED2_1 Ipu/O 2

Port 2 LED Indicator 1

See global reg ister 11 bits [5:4] for details.

Strap Option: Port 4 MII and RMII Modes Select

When Port 4 is MII mode:

PU = MAC mode.

PD = PHY mode.

When Port 4 is R M II mode:

PU = Clock mode in RMI I, using 25MHz OSC clock and provide

50MHz RMII clock from pin RXC4.

PD = Normal mode in RMII, the TXC4/RE FCLKI4 pin on the Port 4

RMII will receive an external 50MHz clock.

Note: Port 4 also can use either an internal or external clock in RMII mode

based on this strap pin or the setting of the Register 86 (0x56) bit [7].

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KSZ8794CNX

Pin Description (Continued)

Pin Number

Pin Name

Type

(1)

Port

Pin Function

49 LED2_0 Ipu/O 2

Port 2 LED Indicator 0

See global reg ister 11 bits [5:4] for details.

Strap Option: REFCLKO Enable

PU = REFCLK_O (25MHz) is enabled. (Default)

PD = REFCLK_O is disabled

Note: It is better to disable this 25MHz clock if do not provide an extra 25MHz

clock for system.

50 LED1_1 Ipu/O 1

Port 1 LED Indicator 1.

See global Register 11 bits [5:4] for details.

Strap Option: P LL C lock Source Select

PU = Still use 25MHz clock from XI/XO pin even though it is in Port 4

RMII normal mode.

PD = Use external cl ock from TXC4 in Por t 4 RMII norm al mode.

Note: If received clock in Port 4 RMII normal mode has bigger clock jitter, still

can select to use the 25MHz crystal/Oscillator as switch’s clock source.

51 LED1_0 Ipu/O 1

Port 1 LED Indicator 0

See global Register 11 bits [5:4] for details.

Strap Option: S peed Select in RGM II

PU = 1Gbps in RGMII. (Default)

PD = 10/100Mbps in RGMII.

Note: Programmable through internal registers also.

52 SPIQ Ipd/O All

SPI Serial Data Output in SPI Slave Mode

Strap Option: Serial Bus Configuration

PD = SPI slave mode.

PU = MDC/MDIO mode.

Note: An external pull-up or pull-down resistor is required.

53 SCL_MDC Ipu All Clock fo r S P I or MDC/MDIO Interfaces

Input clock up to 50MHz in SPI s lave mode.

Input clock up to 25MHz in MDC/MDIO for MIIM access.

54 SDA_MDIO Ipu/O All Data Line for SPI or MDC/MDIO Interfaces

Serial data input in SPI slave m ode.

MDC/MDIO interface input/ output data line.

55 SPIS_N Ipu All

SPI Interface Chip Select

When SPIS_N is high, the KSZ8794CNX is desel ec ted and SPIQ i s

held in the high impedance stat e. A high-to-low transition initiates the

SPI data transfer. This pin is a ctive low.

56 VDDIO P 3.3V, 2.5V or 1.8V digital VDD for digital I/O circuitry.

57 GNDD GND Digital Ground.

58 RST_N Ipu Reset

This activ e low signal resets the hardware in the device. See the timing

requirements in the Timing Diagram Section.

59 VDD12D P 1.2V Core Power.

60 VDDAT P 3.3V Analog Power.

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KSZ8794CNX

Pin Description (Continued)

Pin Number

Pin Name

Type

(1)

Port

Pin Function

61 ISET Transmit Output Current Set

This pin configures the physical transmit output current.

It should be connected to GND thru a 12.4kΩ 1% resistor.

62 GNDA GND Analog Ground.

63 XI I

Crystal Clock Input/Oscillator Input

When using a 25MHz crystal, this input is connected to one end of t he

crystal circ ui t. When using a 3.3V oscillator, this is the input from t he

oscillator.

The crystal or oscillator should have a tolerance of ±50ppm.

64 XO O Crystal Clock Output.

When using a 25MHz crystal, this output is connected to one end of

the crystal circuit.

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KSZ8794CNX

Strap-in Options

The KSZ8794CNX can func tion as a managed switch and utilizes strap-in pins to configure the device for different modes.

The strap-in option pins are configured by using external pull-up/down resistors to create a high or low state on the pins

which are sampled after power down reset or warm reset. The fun ct i ons are described in t he table below.

Pin # Pin Name PU/PD(

) Description

49 LED2_0 Ipu/O

REFCLKO Enable

Strap Option:

PU = REFCLK_O (25MHz) is enabled. (Default)

PD = REFCLK_O is disabled

63 LED2_1 Ipu/O

Port 4 MII and RMII Modes Select

Strap Option:

When Port 4 is MII mode:

PU = MAC mode.

PD = PHY mode.

When Port 4 is R M II mode:

PU = Clock mode in RMI I, using 25MHz OSC clock and provide 50MHz RM II clock

from pin RXC4.

PD = Normal mode in RMII, the TXC4/RE FCLKI4 pin on the Port 4 RMII wi ll receive

an external 50MHz clock

Note: Port 4 also can use either an internal or external clock in RMII mode based on this strap

pin or the setting of the Register 86 (0x56) bit [7].

19,20 LED3[1,0] Ipu/O

Switch Port 4 GMAC4 Interface Mode Select

Strap Option:

00 = MII for SW 4-MII

01 = RMII for SW 4-RMII

10 = Reserved

11 = RGMII for SW4-RGMII (Default)

51 LED1_0 Ipu/O

Port 4 Gigabit Select

Strap Option:

PU = 1 Gbps in RGMII. (Default)

PD = 10/100Mbps in RGMII.

Note: Also programmable through internal register.

50 LED1_1 Ipu/O

PLL Clock Source Select

Strap Option:

PU = Still use 25MHz clock from XI/XO pin even though it is in Port 4 RMII normal

mode.

PD = Use external cl ock from TXC4 in Por t 4 RMII normal mode.

Note: If received clock in Port 4 RMII normal mode has bigger clock jitter, still can select to

use the 25MHz crystal/Oscillator as switch’s clock source.

52 SPIQ Ipd/O

Serial Bus Configuration

Strap Option:

PD = SPI slave mode. (Default)

PU = MDC/MDIO mode.

Note: An external pull-up or pull-down resistor is requested.

Notes:

2. Ipd/O = Input w/internal pull-down during reset, output pin otherwise.

Ipu/O = Input w/internal pull-up during reset, output pin otherwise.

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KSZ8794CNX

Introduction

The KSZ8794CNX contains three 10/100 physical layer transceivers, three media access control (MAC) units and one

Gigabit media access control (GMAC) units with an integrated Layer 2 managed switch. The device runs in two modes.

The first mode is as a three-port stand-alone switc h. The second is as four-port switch with a fourth port that is provided

through a Gigabit media independent interface that supports RGMII, MII and RMII. This is useful for implementing an

integrated broadband router.

The KSZ8794CNX has the flexibility to reside in a managed mode. In a managed mode, a host processor has complete

control of the KSZ8794CNX via the SPI bus, or the MDC/MDIO int erface.

On the media side, the KSZ8794CNX supports IEEE 802.3 10BASE-T, 100BASE-TX on all copper ports with Auto-

MDI/MDIX. The KSZ8794CNX can be used as a fully managed four-port switch or hooked up to a microprocessor via its

RGMII/MII/RMII interfaces to all ow f or integrating into a variety of environment s.

Physical signal transmission and reception are enhanced through the use of patented analog circuitry and DSP

technology th at makes the design more efficient and all ows for reduced power consumption and small er die size.

Major enhancements from the KSZ8864RMN to the KSZ8794CNX include high speed host interface options such as the

RGMII interfaces, power saving features such as IEEE 802.1az energy efficient Ethernet (EEE), MLD snooping, Wake

On LAN (WoL), port-based ACL filt ering and the port securit y, programmable QoS priority and flexible rate limiting.

Functional Overview: Physical Layer (PHY)

100BASE-TX Transmit

The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI

conversion, MLT3 encoding and transmission. The circuit starts with a parallel-to-serial conversion, which converts the MII

data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding

followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3

current output. The output current is set by an external 1% 12.4kΩ resistor for the 1:1 transformer ratio. It has a typical

rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot, and timing

jitter. The wave-shaped 10BAS E-T output is also incorpo rat ed i nto the 100BASE-TX transmitter.

100BASE-TX Receive

The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and

clock recovery, NRZI-to-NRZ conversion, descrambling, 4B/5B decoding, and serial-to-parallel conversion. The receiving

side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Since

the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust its

characteristics to optimize the performance. In this design, the variable equalizer will make an initial estimation based on

comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. This

is an ongoing process and can self-adjust against environmental changes such as temperature variati ons.

The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to

compensate for the effect of baseline wander and improve the dynamic range. The differential data conversion circuit

converts the MLT3 f ormat back to NRZI. The slicing threshold is also adaptive.

The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used

to convert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by the 4B/5B

decoder. Finally, the NRZ serial data is c onverted to the MII format and provided as t he input data to the MAC.

PLL Clock Synthesizer

The KSZ8794CNX generates 125MHz, 83MHz, 41MHz, 25MHz and 10MHz clocks for system timing. Internal clocks are

generated from an external 25MHz crystal or oscillator.

Scrambler/Descrambler (100BASE-TX only)

The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander.

The data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). This can generate a 2047-

bit non-repetitive sequence. The receiver will then descramble the incoming data stream with the same sequence at the

transmitter.

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10BASE-T Transmit

The 10BASE-T output driver is incorporated into the 100BASE-T driver to allow transmission with the same magnetics.

They are internally wave-shaped and pre-emphasized into outputs with a typical 2.3V amplitude. The harmonic contents

are at least 27dB below the fundamental when driven by an all-ones Manchester-encoded signal.

10BASE-T Receiv e

On the receive side, input buf fers and level detecting squelch circuits are employed. A differential input receiver circuit and

a PLL perform the decoding function. The Manchester-encoded data stream is separated into a clock signal and NRZ

data. A squelch circuit rejects signals with levels less than 400mV or with short pulsewidths in order to prevent noises at

the RXP or RXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto

the incoming signal and the KSZ8794CNX decodes a data frame. The receiver clock is maintained active during idle

periods in between dat a reception.

MDI/MDI-X Auto Crossover

To eliminate the need for crossover cables between similar devices, the KSZ8794CNX supports HP Auto-MDI/MDI-X and

IEEE 802.3u stand ard MDI/MDI-X auto crossover. HP Auto-MDI/MDI-X is the default.

The auto-sense function detects remote transmit and receive pairs and correctly assigns transmit and receive pairs for the

KSZ8794CNX device. This feature is extremely useful when end users are unaware of cable types, and also, saves on an

additional uplink configuration connection. The auto-crossover feature can be disabled through the Port control registers,

or MIIM PHY registers. The IEEE 802.3u standard MDI and M DI -X defi nition s are:

Table 1. MDI/MDI-X Pin Definitions

MDI MDI-X

RJ-45 Pins

Signals

RJ-45 Pins

Signals

1 TD+ 1 RD+

2 TD- 2 RD-

3 RD+ 3 TD+

6 RD- 6 TD-

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Straight Cable

A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. The following diagram

depicts a typical straight cable connecti on between a NIC Card (MDI) and a switch, or hub (MDI-X).

Figure 1. Typical Straight Cable Connection

Crossover Cable

A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device. The

following diagram s hows a typical crossover cable connection between two switches or hubs (two MDI-X devices).

Figure 2. Typical Crossove r Cable Connection

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Auto-Negotiation

The KSZ8794CNX conforms to the auto-negotiation protocol as described by the 802.3 committee. Auto-negotiation

allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation. Link partners

advertise their capabilities to each other, and then compare their own capabilities with those they received from their link

partners. The highest speed and duplex setting that is common to the two link partners is selected as the mode of

operation. Aut o-negotiation is supported for the copper ports only.

The following list shows the speed and duplex operation mode (highest to lowest):

• 100Base-TX, full-duplex

• 100Base-TX, half-duplex

• 10Base-T, full-duplex

• 10Base-T, half-duplex

If auto-negotiation is not supported or the KSZ8794CNX link partner is forced to bypass auto-negotiation, the

KSZ8794CNX sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and

allows the KSZ8794CNX to establish link by listening for a fixed signal protocol in the absence of auto-negotiation

advertisemen t protocol. The auto-negoti ation link up process is shown in t he f ol lowing flow chart.

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Figure 3. Auto-Negotiation and Parallel Operation

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LinkMD® Cable Diagnostics

The LinkMD feature utilizes time domain reflectometry (TDR) to analyze the cabling plant for common cabling problems

such as open circuits, short circuits and impedance mismatches.

LinkMD works by sending a pulse of known amplitude and duration down the MDI and MDI-X pairs and then analyzes the

shape of the reflected signal. Timing the pulse duration gives an indication of the distance to the cabling fault with

maximum distance of 200m and accuracy of ±2m. Internal circuitry displays the TDR information in a user-readable digital

format.

Note: Cable diagnostics are only valid for copper connections only.

Access

LinkMD is initiated by accessing the PHY special control/status Registers {26, 42, 58} and the LinkMD result Registers {27,

43, 59} for Ports 1, 2 and 3 respectively; and in conjunction with the Port Registers control 10 for Ports 1, 2 and 3

respectively to disable Auto MDI/MDIX.

Alternatively, the MIIM PHY Registers 0 and 1d can be used for Li nkMD access also.

Usage

The following is a sample procedure for using LinkMD with Regist ers {26, 27, 29} on Port 1:

1. Disable auto MDI/MDI-X by writing a ‘1’ to Register 29, bit [2] to enable manual control over the differential pair used

to transmit the LinkMD pulse.

2. Start cable diagnostic test by writing a ‘1’ to Register 26, bit [ 4]. This enable bit is self-clearing.

3. Wait (poll) for Register 26, bit [4] to return a ‘0’, and indicati ng cable diagnostic t est is completed.

4. Read cable diagnostic test results in R egister 26, bits [6:5]. The results are as follows:

00 = normal condition (valid test)

01 = open condition det ected in cable (valid test)

10 = short condition det ected in cable (valid test)

11 = cable diagnostic test failed (invalid test)

The ‘11’ case, invalid test, occurs when the KSZ8794CNX is unable to shut down the link partner. In this instance, the

test is not run, since it would be impossible for the KSZ8794CNX to determine if the detected signal is a reflection of

the signal generate d or a signal from anot her source.

5. Get distance to fault by concatenating Register 26, bit [0] and Register 27, bits [7:0]; and multiplying the result by a

constant of 0.4. The di st ance to the cable fault can be determined by the following formula:

D (distance to cabl e fault) = 0.4 x (Register 26, bit [0], Reg ister 27, bits [7:0])

D (distance to cable f ault) is expressed in meters.

Concatenated value of Registers 26 bit [0] and 27 bits [7:0] should be converted to decimal before decrease 26

and multiplying by 0.4.

The constant (0.4) may be calibrated for different cabling conditions, including cables with a velocity of propagation

that varies significa ntly from the norm.

For Port 2, 3 and using the MIIM PHY Registers, LinkMD usage is similar.

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A LinkMD example

The following is a sample procedure for using LinkMD on port 1, port 2 and port 3.

//Disable Auto-MDI/MDI-X and Fo rce to MDI-X mode

//’w’ is WRITE the register. ‘r’ is READ register below

w 1d 04

w 2d 04

w 3d 04

//Set Internal registers temporary by i ndirect registers, adjust for LinkMD

w 6e a0

w 6f 4d

w a0 08

//Enable LinkMD Te st i ng with Fault Cable for port 1, port 2 and port 3 by Port Register Control 8 bit [4]

w 1a 10

w 2a 10

w 3a 10

//Wait until Port Register Control 8 bit [4] returns a ‘0’ (Self Clear)

//Diagnosis results

r 1a

r 1b

r 2a

r 2b

r 3a

r 3b

//For example on port 1, t he r esult analysis based on the values of the register 0x1a and 0x1b

//The register 0x 1a bi ts [6-5] are for the open or the short detect i on.

//The register 0x 1a bi t [0] + the register 0x 1b bits [7-0] = CDT_Fault_Count [8-0]

//The distance t o fault is about 0.4 x (CDT_Fault_Count [8-0])

On-chip Termination and Internal Biasing

The KSZ8794CNX reduces the board cost and simplifies the board layout by using on-chip termination resistors for all

ports and RX/TX differential pairs without the external termination resistors. The combination of the on-chip termination

and the internal biasing will save more PCB space and power consumption in system, compared with using external

biasing and termination resistors for multiple ports’ switches because the transformers do not consume power anymore.

The center taps of the transformer should not need to be tied to the analog power.

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Functional Overview: Medi a A ccess Controller (MAC)

Media Access Controller (MAC) Operation

The KSZ8794CNX strictly abides by I E EE 802.3 standards to maximize compatibility.

Inter-Packet Gap (IPG)

If a frame is successfully transmitted, the 96-bit time IPG is measured between the two consecutive MTXEN. If the current

packet is experiencing collision, the 96-bit time IPG is measur ed from MCRS and t he next MTXEN.

Back-off Algorithm

The KSZ8794CNX implements the IEEE Standard 802.3 binary exponential back-off algorithm, and optional “aggressive

mode” back-off. After 16 collisions, the packet may be optional ly dropped dependi ng on Register 3’s chip c onfiguration.

Late Collision

If a transmit packet ex periences collisions after 512-bit times of the transmission, the packet will be dropped.

Illegal Frames

The KSZ8794CNX discards frames less than 64 bytes and can be programmed to accept frames up to 1536 bytes in

present.

Flow Control

The KSZ8794CNX sup ports standard 802.3x flow control frames on both transmit and rec ei ve sides.

On the receive side, if the KSZ8794CNX receives a pause control frame, the KSZ8794CNX will not transmit the next

normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received before the

current timer expires, the timer will be updated with the new value in the second pause frame. During this flow controlled

period, only flow control packets from the KSZ8794CNX will be transmitted.

On the transmit side, the KSZ8794CNX has intelligent and efficient ways to determine when to invoke flow control. The

flow control is based on availability of the system resources, including available buffers, available transmit queues and

available receive queues.

The KSZ8794CNX flow controls the port that receives a packet if the destination port resource is busy. The KSZ8794CNX

issues a flow control frame (XOFF), containing the maximum pause time defined in IEEE standard 802.3x. Once the

resource is freed up, the KSZ8794CNX sends out the other flow control frame (XON) with zero pause time to turn off the

flow control, which turns on transmission to the port. A hysteresis feature is also provided to prevent over-activation and

deactivation of t he f l ow control mechanism.

The KSZ8794CNX f l ow co ntrols all ports if the rec ei ve queue becomes full.

Half-Duplex Back Pressure

The KSZ8794CNX also provides a half-duplex back pressure option. Note that this is not in IEEE 802.3 standards. The

activation and deactivation conditions are the same as the ones given for full-duplex mode. If back pressure is required,

the KSZ8794CNX sends preambles to defer the other station's transmission (carrier sense deference). To avoid jabber

and excessive deference as defined in IEEE 802.3 standards, after a certain period of time, the KSZ8794CNX

discontinues carrier sense but raises it quickly after it drops packets to inhibit other transmissions. This short silent time

(no carrier sense) is to prevent other stations from sending out packets and keeps other stations in a carrier sense-

deferred state. If the port has packets to send during a back pressure situation, the carrier sense-type back pressure is

interrupted and those packets are transmitted instead. If there are no more packets to send, carrier sense-type back

pressure becomes active again until switch resources are free. If a collision occurs, the binary exponential back-off

algorithm is skipped and carrier sense is generated immediately, reduc ing the chance of further colliding and maintaining

carrier sense to prevent reception of packets. To ensure no packet loss in 10BASE-T or 100BASE-TX half-duplex modes,

the user must enable the following:

• Aggressive bac k-off (Register 3, bit [0])

• No excessive collision drop (Register 4, bit [3])

• Back pressure (Register 4, bit [5] )

These bits are not set as the default because this is not the IEEE standard.

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Broadcast Storm Protection

The KSZ8794CNX has an intelligent option to protect the switch system from receiving too many broadcast packets.

Broadcast packets are normally forwarded to all Ports except the source Port and thus use too many switch resources

(bandwidth and available space in transmit queues). The KSZ8794CNX has the option to include “multicast packets” for

storm control. The broadcast storm rate parameters are programmed globally and can be enabled or disabled on a per

port basis. The rate is based on a 50ms (0.05s) interval for 100BT and a 500ms (0.5s) interval for 10BT. At the beginning

of each interval, the counter is cleared to zero and the rate limit mechanism starts to count the number of bytes during the

interval. The rate definition is described in Registers 6 and 7. The default setting for Registers 6 and 7 is 0x4A (74

decimal). This is equal to a rate of 1%, calculated as follows:

148,80 frames/se c X 50ms (0.05s)/interval X 1% = 74 frames/ interval (approx.) = 0x4A

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Functional Overview: Switch Core

Address Look-Up

The internal look-up table stores MAC addresses and their associated information. It contains a 1K unicast address table

plus switching information. The KSZ8794CNX is guaranteed to learn 1K addresses and distinguishes itself from a hash-

based look-up table, which, depending on the operating environment and probabilities, may not guarantee the absolute

number of addresses it can learn.

Learning

The internal look -up engine updates its table with a new entry if the following condit i ons are met:

• The received packet’s source address (SA) does not exist in t he l ook-up table.

• The received packet is good; the packet has n o receiving errors and i s of l egal l ength.

The look-up engine inserts the qualified SA into the table, along with the Port number and time stamp. If the table is full,

the last entry of t he t abl e i s deleted first to make room for the new entry.

Migration

The internal look-up engine also monitors whether a station is moved. If this occurs, it updates the table accordingly.

Migration happen s wh en the following conditions are met:

• The received packet’s SA is in the table but the associated source Port information is different.

• The received packet is good; the packet has n o receiving errors and i s of l egal l ength.

The look-up engine wil l update the existing record in the table with t he new source Port information.

Aging

The look-up engine will update the time stamp information of a record whenever the corresponding SA appears. The time

stamp is used in the aging process. If a record is not updated for a period of time, the look-up engine will remove the

record from the table. The look-up engine constantly performs the aging process and will continuously remove aging

records. The aging p eriod is 300 +/- 75 seconds. This feature can be enabled or disabled t hrough Register 3 bit [2].

Forwarding

The KSZ8794CNX will forward packets using an algorithm that is depicted in the following flowcharts. Figure 4 shows

stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table for

the destination address, and comes up with “Port to forward 1” (PTF1). PTF1 is then further modified by the spanning

tree, IGMP snooping, port mirroring, and port VLAN processes and authentication to come up with “Port to forward 2”

(PTF2). The authentication and ACL have highest priority in the forwarding process, ACL result will overwrite the result of

the forwarding process. This is where the packets will be sent.

The KSZ8794CNX will not forward the fol lowing packets:

1. Error packets

These include framing errors, Frame Check Sequence (FCS) errors, alignment errors, and illegal size packet errors.

2. IEEE802.3x PAUSE frames

KSZ8794CNX i ntercepts these packets and performs full duplex f l ow control accordingly.

3. "Local" packets

Based on destination address (DA) lookup, if the destination port from the lookup table matches the port from which

the packet originated, t he packet is defined as "local."

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Figure 4. Destination Address Lookup and Resolution Flow Chart

Switching Engine

The KSZ8794CNX features a high-performance switching engine to move data to and from the MAC’s packet buffers. It

operates in store and forward mode, while the efficient switching mechanism reduces overall latency. The KSZ8794CNX

has a 64kB internal frame buffer. This res ource is shared between all five Ports. There are a total of 512 buffers available.

Each buffer is sized at 128Byte.

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Functional Overview: Power

The KSZ8794CNX device requires 3.3V analog power. An external 1.2V LDO provides the necessary 1.2V to power the

analog and digital logic cores. The various I/O’s can be operated at 1.8V, 2.5V, and 3.3V. Table below illustrates the

various voltage options and requirements of the device.

Power Signal Name Device Pin Requirement

VDDAT 2,12, 60 3.3V input po wer t o the analog blocks of tran sceiver in the device.

VDDIO 27, 39, 56 C hoice of 1.8V or 2.5V or 3.3V for the I/O circuits. These input po wer pins power the

I/O circuitry of the device.

VDD12A 1 1.2V core power. Filtered 1.2V input voltage. These pins feed 1.2V to power the

internal analog and digital cores.

VDD12D 21, 33, 59

GNDA 3, 17, 62 Analog Ground.

GNDD 22, 26, 32, 38,57 Digital Ground.

Functional Overview: Power Management

The KSZ8794CNX supports enhanced power management in a low power state, with energy detection to ensure low

power dissipation during device idle periods. There are three operation modes under the power management function

which are controlled by the Register 14 bi ts [4:3] and the Port Control 10 Register bit [3] as show n bel ow:

The Port Control 10 Register 29, 45, 61 bit [3] = 1 are for the Port Based Power-Down Mode.

Table 2 indicates all i nternal function bl ocks’ status under four dif ferent power manag em ent operation modes.

Table 2. Internal Function Block Status

KSZ8794CNX Function Blocks Power Man agement Operati on Modes

Normal Mode Energy Detect Mo de Soft Power Down Mode

Internal PLL Clock Enabled Disabled Disabled

Tx/Rx PHY Enabled Energy detect at Rx Disabled

MAC Enabled Disabled Disabled

Host Interface Enabled Disabled Disabled

Normal Operation Mode

This is the default setting bits [4:3] = 00 in Register 14 after chip power-up or hardware reset. When KSZ8794CNX is in

normal operation mode, all PLL clocks are running, PHY and MAC are on, and the host interface is ready for CPU read or

writes.

During normal operation mode, the host CPU can set the bits [4:3] in Register 14 to change the current nor mal operation

mode to any one of the other three power mana gem ent operation modes.

Energy Detect Mode

Energy detect mode provides a mechanism to save more power than in the normal operation mode when the

KSZ8794CNX Port is not connected to an active link partner. In this mode, the device will save more power when the

cables are unplugged. If the cable is not plugged in, the device can automatically enter a low power state—the energy

detect mode. In this mode, the device will keep transmitting 120ns width pulses at a 1-pulse rate. Once activity resumes

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due to plugging a cable in or attempting by the far end to establish link, the device can automatically power up to normal

power state in energy detect mode.

The energy detect mode consists of two states, normal power state and low power state. While in low-power state, the

device reduces power consumption by disabling all circuitry except the energy detect circuit of the receiver. The energy

detect mode is entered by setting bits [4:3] = 01 in Register 14. When the KSZ8794CNX is in this mode, it will monitor the

cable energy. If there is no energy on the cable for a time longer than the pre-configured value at bits [7:0]  the go-sleep

time in Register 15, KSZ8794CNX will go into low power state. When KSZ8794CNX is in low power state, it will keep

monitoring the cable energy. Once the energy is detected from the cable, the device will enter normal power state. When

the device is at normal p ower state, it i s able to transmit or receive packet from the cable.

Soft Power-Down Mode

The soft power-down mode is entered by setting bits [4:3] = 10 in Register 14. When KSZ8794CNX is in this mode, all

PLL clocks are disabled, also all of PHYs and the MACs are off. Any dummy host access will wake-up this device from

current soft power down mode to normal operation mode and internal reset will be issued to make all internal Registers go

to the default values.

Port-based Power-Down Mode

In addition, the KSZ8794CNX features a per-port power down mode. To save power, a PHY port that is not in use can be

powered down vi a the Port Control 10 Register bit [3], or MIIM PHY Register 0 bit [11].

Energy Efficient Ethernet (EEE)

Along with the supports of different type of power saving modes (H/W power down, S/W power down and Energy Detect

mode), the KSZ8794CNX extends the green function capability by supporting EEE (Energy Efficient Ethernet) features

defined in IEEE P802.3az™/D2.3, March 2010. Both 10Base-T and 100Base-TX EEE functions are supported in

KSZ8794CNX. In 100Base-TX the EEE operation is asymmetric on the same link, which means one direction could be at

Low Power Idle (LPI) state while another direction could exist on packet transfer activity. Differing from other types of

power saving modes, the EEE is able to maintain the link while power saving is achieved. Based on EEE specificati on, the

energy saving from EEE is done at the PHY level. KSZ8794CNX reduces the power consumption not only at PHY level

but also at MAC and switch level by shutting down the unused clocks as much as possible when the device is in a LPI

phase.

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Figure 5. EEE Transmit and Receive Signalin g Paths

The KSZ8794CNX supports the IEEE 802.3az EEE standard for both 10 and 100Mbps interfaces. The EEE capability

combines switch, MAC with PHY to support operation in the LPI mode. When the LPI mode is enabled, systems on both

sides of the link can sav e power during periods of low link utilization.

EEE implementation provides a protocol to coordinate transitions to or from lower power consumption without changing

the link status and without dropping or corrupting frames. The transition time into and out of the lower pow er consumption

is kept small enough to be transparent to upper layer protocols and applications. EEE specifies means to exchange

capabilities between link partners to determine whether EEE is supported and to select the best set of parameters

common to both sides.

Besides supporting the 100BASE-TX PHY EEE, KSZ8794CNX also supports 10BASE-T with reduced transmit amplitude

requirements for 10M bps mode to allow a reduct i on i n power consumpti on.

LPI Signaling

Low Power Idle LPI signaling allows switch to indicate to the PHY, and to the link partner, that a break in the data stream

is expected, and switch can use this information to enter power-saving modes that require additional time to resume

normal operation. LPI signaling also informs the switch when the link partner has sent such an indication. The definition

of LPI signaling uses the MAC for simplified full-duplex operation (with carrier sense deferral). This provides full-duplex

operation but uses t he carrier sense signal to defer transmission when the PHY is i n the LPI mode.

The decision on when to signal LPI (LPI request) to the link partner is made by the switch and communicated to the PHY

through MAC MII interface. The switch is also informed when the link partner is signaling LPI, indication of LPI activation

(LPI indication) on the MAC interface. The conditions under which switch decides to send LPI, and what actions are taken

by switch when it receives LPI from the link partner, are specifie d i n i m plem entation section.

LPI Assertion

Without LPI assertion, the normal traffic transition continues on the MII interface. As soon as an LPI request is asserted,

the LPI assert function starts to transmit the “Assert LPI” encoding on the MII and stop the MAC from transmitting normal

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traffic. Once the LPI request is de-asserted, the LPI assert function starts to transmit the normal inter-frame encoding on

the MII again. After a delay, the MAC is allowed to start transmitting again. This delay is provided to allow the link partner

to prepare for normal o peration. The following f i gure i llustrates the EEE LPI between two active data idles.

LPI Detection

In the absence of “Assert LPI” encoding on the receive MII, the LPI detect function maps the receive MII signals as normal

conditions. At the start of LPI, indicated by the transition from normal inter-frame encoding to the “Assert LPI” encoding on

the receive MII, the LPI detect function continues to indicate idle on interface, and asserts LP_IDLE indication. At the end

of LPI, indicated by the transition from the “Assert LPI” encoding to any other encoding on the receive MII, LP_IDLE

indication is de-ass erted and the normal decoding operation res um es.

PHY LPI Transmit Operation

When the PHY detects the start of “Assert LPI” encoding on the MII, the PHY signals sleep to its link partner to indicate

the local transmitter is entering LPI mode. The EEE capability requires the PHY transmitter to go quiet after sleep is

signaled. LPI requests are passed from one end of the link to the other and system energy savings can be achieved even

if the PHY link does not go into a low power mode.

The transmit function of the local PHY is enabled periodically to transmit refresh signals that are used by the link partner

to update adaptive filters and timing circuits in order to maintain link integrity. This quiet-refresh cycle continues until the

reception of the normal inter-frame encoding on the MII. The transmit function in the PHY communicates this to the link

partner by sending a wake signal for a predefined period of time. The PHY then enters the normal operating state. No

data frames are lost or corrupted during t he transition to or from the LPI mode.

In 100BT/Full duplex EEE operation, Refresh transmission are used to maintain link and the Quiet periods are used for

the power saving. Approximately, every 20-22ms a Refresh of 200-220us is sent to the link partner. The Refresh

transmission and Quiet periods are shown in Figure 6.

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Figure 6. Traffic Activity and EEE LPI Operations

PHY LPI Receive Operation

On receive, entering the LPI mode is triggered by the reception of a sleep signal from the link partner, which indicates that

the link partner is about to enter the LPI mode. After sending the sleep signal, the link partner ceases transmission. When

the receiver detects the sleep signal, the local PHY indicates “Assert LPI” on the MII and the local receiver can disable

some functionality to reduce power consumption. The link partner periodically transmits refresh signals that are used by

the local PHY. This quiet-refresh cycle continues until the link partner initiates transition back to normal mode by

transmitting the wake signal for a predetermined period of time controlled by the LPI assert function. This allows the local

receiver to prepare for normal operation and transition from the “Assert LPI” encoding to the normal inter-frame encoding

on the MII. After a syst em specified recovery time, the link supports the nominal operational data rate.

Negotiation with EEE Capability

The EEE capability shall be advertised during the auto-negotiation stage. Auto-negotiation provides a linked device with

the capability to detect the abilities supported by the device at the other end of the link, determine common abilities, and

configure for joint operation. Auto-negotiation is performed at power up or reset, on command from management, due to

link failure, or due t o user intervention.

During auto-negotiation, both link partners indicate their EEE capabilities. EEE is supported only if during Auto-negotiation

both the local device and link partner advertise the EEE capability for the resolved PHY type. If EEE is not supported, all

EEE functionality is disabled and the LPI client does not assert LPI. If EEE is supported by both link partners for the

negotiated PHY type, then the EEE f unct i on can be used independ ently in either direction.

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Wake on LAN (WoL)

Wake on LAN allows a computer to be turned on or woken up by a network message. The message is usually sent by a

program executed on another computer on the same local area network. Wake-up frame events are used to wake the

system whenever meaningful data is presented to the system over the network. Examples of meaningful data include the

reception of a Magic Packet, a management request from a remote administrator, or simply network traffic directly

targeted to the local system. The KSZ8794CNX can be programmed to notify the host of the Wake-Up frame detection

with the assertion of the interrupt signal (INTR_N) or assertion of the power management event signal (PME). The PME

control is by PME indirect Registers.

KSZ8794CNX MAC supports the detection of t he f ol l owing Wake-Up events:

• Detection of energy signal over a pre-configured value: Port PME Control Status Register bit [0] in PME indirect

registers.

• Detection of a linkup i n the network link state: Port PME Control Status Register bit [1] in the PME indirect registers.

• Receipt of a Magic Packet: Port PME Control Status Register bit [2] in the PME indi rect registers.

There are also other types of Wake-Up events that are not listed here as manufacturers may choose to implement these

in their own way.

Direction of Energy

The energy is detected from the cable and is continuously presented for a time longer than pre-configured value,

especially when t hi s energy change may im pact the level at which the syst em shoul d re-ent er to the normal power state.

Direction of Link-up

Link status wake events are useful to indicat e a l i nkup in the network’s c onnectivity status.

Magic Packet™

The Magic Packet is a broadcast frame containing anywhere within its payload 6 bytes of all 1s (FF FF FF FF FF FF)

followed by sixteen repetitions of the target computer's 48-bit DA MAC address. Since the magic packet is only scanned

for the above string, and not actually parsed by a full protocol stack, it may be sent as any network- and transport-layer

protocol.

Magic Packet technology is used to remotely wake up a sleeping or powered off PC on a LAN. This is accomplished by

sending a specific packet of information, called a Magic Packet frame, to a node on the network. When a PC capable of

receiving the specific frame goes to sleep, it enables the Magic Packet RX mode in the LAN controller. When the LAN

controller receives a Magic Packet frame, it will alert the system to wake up. Once the KSZ8794CNX has been enabled

for Magic Packet Detection in Port PME Control Mask Register bit [2] in the PME indirect register, it scans all incoming

frames addressed t o the node for a specific dat a sequence, which indicates to the controller this is a Magic P acket f rame.

A Magic Packet frame must also meet the basic requirements for the LAN technology chosen, such as Source Address

(SA), Destination Address (DA), which may be the receiving station’s IEEE MAC address, or a multicast or broadcast

address and CRC. The specific sequence consists of 16 duplications of the MAC address of this node, with no breaks or

interruptions. This sequence can be located anywhere within the packet, but must be preceded by a synchronization

stream. The synchronization stream is defined as 6 bytes of 0xFF. The device will also accept a broadcast frame, as long

as the 16 duplications of the IEEE address match the address of t he m achine to be awakened .

Example of Magic Pa ck et:

If the IEEE address for a particular node on a network is 11h 22h, 33h, 44h, 55h, 66h, the LAN controller would be

scanning for the data sequence (assuming an Ethernet frame): DA - SA - TYPE - FF FF FF FF FF FF - 11 22 33 44 55 66

-11 22 33 44 55 66-11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 2 2 33 44 55 66 -

11 22 33 44 55 66 - 11 22 33 44 55 66 -11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 -

11 22 3344 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 -MISC-CRC.

There are no further restrictions on a Magic Packet frame. For instance, the sequence could be in a TCP/IP packet or an

IPX packet. The frame may be bridged or routed across the network without affecting its ability to wake-up a node at the

frame’s destination. If the scans do not find the specific sequence shown above, it discards the frame and takes no further

action. If the KSZ8794CNX detects the data sequence, however, it then alerts the PC’s power management circuitry

(assert the PME pin) t o wake up the system.

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KSZ8794CNX

Interrupt (INT_N/PME_N)

INT_N is an interrupt signal that is used to inform the external controller that there has been a status update in the

KSZ8794CNX interrupt status register. Bits [3:0] of Register 125 are the interrupt mask control bits to enable and disable

the conditions for asserting the INT_N signal. Bits [3:0] of Register 124 are the interrupt status bits to indicate which

interrupt conditions have occurred. The interrupt status bits a re cleared after reading t hose bits in Register 124.

PME_N is an optional PME interrupt signal that is used to inform the external controller that there has been a status

update in the KSZ8794CNX interrupt status register. Bits [4] of Register 125 are the PME mask c ontrol bits to enable and

disable the conditions for asserting the PME_N signal. Bits [4] of Register 124 are the PME interrupt status bits to indicate

which PME interrupt conditions have occurred. The PME interrupt status bit [4] is cleared after reading this bit of Register

124.

Additionally, the interrupt pins of INT_N and PME_N eliminate the need for the processor to poll the switch for status

change.

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KSZ8794CNX

Functional Overview: Interfaces

The KSZ8794CNX device incorporates a number of interfaces to enable it to be designed into a standard network

environment as well as a vendor unique environment. The available interfaces are summarized in Table 3. The detail of

each usage in this tabl e i s provided in the following sections.

Table 3. Available Interfaces

Interface Type Usage Registers

Accessed

SPI Configuration and

thru this interface. All

MIIM Configuration and

RMII Data Flow Interface to the Port 4 GMAC using the fas ter reduced RMII timing. n/a

MII Data Flow Interface to the Port 4 GMAC using the st andard MII timi ng. n/a

RGMII Data Flo w Interface to the Port 4 GMAC using the faste r reduced RGMII timing. n/a

Configuration Interface

SPI Slave Serial Bus Configuration

The KSZ8794CNX can also act as an SPI slave device. Through the SPI, the entire feature set can be enabled, including

“VLAN,” “IGMP snooping,” “MIB counters,” etc. The external master device can access any register from Register 0 to

KSZ8794CNX. T o enabl e the switch, wri te a "1" to Register 1 bit [0].

Two standard SPI commands are supported (00000011 for “READ DATA,” and 00000010 for “WRITE DATA”). To speed

configuration time, the KSZ8794CNX also supports multiple reads or writes. After a byte is written to or read from the

KSZ8794CNX, the internal address counter automatically increments if the SPI Slave Select Signal (SPIS_N) continues to

be driven low. If SPIS_N is kept low after the first byte is read, the next byte at the next address will be shifted out on

SPIQ. If SPIS_N is kept low after the first byte is written, bits on the Master Out Slave Input (SPID) line will be written to

the next address. Asserting SPIS_N high terminates a read or write operation. This means that the SPIS_N signal must

be asserted high and then low again before issuing another command and address. The address counter wraps back to

zero once it reaches the highest address. Therefore the entire register set can be written to or read from by issuing a

single command and address.

The KSZ8794CNX is able to support a SPI bus up to 50MHz. A high performance SPI master is recommended to prevent

internal counter overflow.

To use the KSZ8794CNX SPI:

1. At the board lev el , connect KSZ8794CNX pins as follows:

Table 4. SPI Connections

KSZ8794CNX Signal Name Microprocessor Signal Description

SPIS_N (S_CS) SPI Slave Select.

SCL (S_CLK) SPI Clock.

SDA (S_DI) Master Output. Slave Input.

SPIQ (S_DO) Master Input. Slave Output .

2. Configure the serial communication to S PI slave mode by pulling down pin SPIQ with a pull-down resistor.

3. Write configuration data to registers using a typical SPI write data cycle as shown in Figure 7 or SPI multiple write as

shown in Figure 8. Note that data input on SDA is registered on the rising edge of SCL clock.

4. Registers can be read and the configuration can be verified with a typical SPI read data cycle as shown in Figure 7 or

a multiple read as shown in Figure 8. Not e t hat read data is registered out of SPIQ on the fal li ng edge of SCL clock.

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Figure 7. SPI Access Timing

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Figure 8. SPI Multiple Access Timing

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KSZ8794CNX

MII Management Interface (MIIM)

The KSZ8794CNX supports the standard IEEE 802.3 MII Management Interface, also known as the Management Data

Input/output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the states of the

KSZ8794CNX. An external device with MDC/MDIO capability is used to read the PHY status or configure the PHY

settings. Further details on the MII M i nt erface a re f ound in Clause 22.2.4.5 of the IEEE 802. 3u Specification.

The MIIM interface consists of the fol l owing:

• A physical connect ion t hat incorporates the dat a l ine MDIO and the clock line MDC.

• A specific protocol that operates across the aforementioned physical connection that allows an external controller to

communicate wit h t he K SZ8794CNX device.

• Access to a set of eight 16-bit registers, consisting of 8 standard MIIM Registers [0:5h], 1d and 1f MIIM registers per

port.

The MIIM Interfac e can operate up to a max i m um clock speed of 25MHz MDC clock.

The following tabl e depicts the MII Managem ent Interface frame format.

Table 5. MII Management Interface Frame Format

Preamble Start of

Frame Read/Write

OP Code

PHY

Address

Bits[4:0]

REG

Address

Bits[4:0] TA Data Bits[15:0 ] Idle

Read 32 1’s 01 10 AAAAA RRRRR Z0 DDDDDDDD_DDDDDDDD Z

Write 32 1’s 01 01 AAAAA RRRRR 10 DDDDDDDD_DDDDDDDD Z

The MIIM interface does not have access to all the configuration registers in the KSZ8794CNX. It can only access the

standard MIIM regis ters. See “MIIM Registers”. The SPI interface, on the other hand, can be used to access all registers

with the entire KS Z8794CNX feature set.

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KSZ8794CNX

Switch Port 4 GMAC Interface

The KSZ8794CNX GMAC4 interface supports MII/RGMII/RMII four interfaces protocols and shares one set of input/output

signals. The purpose of this interface is to provide a simple, inexpensive, and easy-to implement interconnection between

the GMAC/MAC sub layer and a GPHY/PHY. Data on these interfaces are framed using the IEEE Ethernet standard. As

such it consists of a preamble, start of frame delimiter, Ethernet headers, protocol specific data and a cyclic redundancy

check (CRC) checksum.

Transmit and Receive signals for MII/RGMII/RMII interfaces shown in Table 6.

Table 6. Signals of RGMII/MII/RMII

Direction Type

RGMII

MII

RMII

Input (Output)

GTXC

TXC

REFCLKI

Input

TXER

Input

TXD_CTL

TXEN

Input (Output)

COL

Input

TXD[3:0]

TXD[1:0]

Input (Output)

GRXC

RXC

Output

RXER

Output

RXD_CTL

RXDV

CRS_DV

Input (Output)

CRS

Output

RXD[3:0]

RXD[1:0]

Standard Media Independent Interf ace [MII]

The MII interface is capable of supporting 10/100Mbps. Data and delimiters are synchronous to clock references. It

provides independent four transmit and receive data paths and uses signal levels, two media status signals are provided.

The CRS indicates the presence of carrier, and the COL indicates the occurrence of a collision. Both half and full duplex

operations are provided by MII interface.

The MII transfers data using 4-bit words (nibble) in each directio n. Clocked at 2.5/25MH z t o achieve 10/100Mbps speed.

Reduced Media I nd ependent Interface [RMII]

The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). The

KSZ8794CNX supports the RMII interface on the Port 4 GMAC4 a nd prov i des the following k ey characteristics:

• Supports 10Mbps and 100Mbps data rates.

• Uses a single 50MHz clock reference (provided internally or externally): in internal mode, the chip provides a

reference clock f rom the RXC pin to the opposite clock input pin for RMII interface. In external mode, the chip receives

50MHz reference clock from an external oscillator or opposite RMI I interface.

• Provides independ ent 2-bit wide (bi-bit) transmit and receive data paths.

Reduced Gigabit Media Independent Interface [RGMII]

It is intended to be an alternative to the IEEE802.3u MII and the IEEE802.3z RGMII. The principle objective is to reduce

the number of pins required to interconnect the GMAC and the GPHY in a cost effective and technology independent

manner. In order to accomplish this objective, the data paths and all associated control signals will be reduced and control

signals will be multiplexed together and both edges of the clock will be used. For gigabit operation, the clocks will operate

at 125MHz with using rising edge and f alling edge to latch data.

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KSZ8794CNX

Port 4 GMAC4 SW 4-RGMII Inte r face

Table 7 shows the RGMII reduced connections when connecting to an external GMAC o r GP HY :

Table 7. Port 4 SW4-RGMII Connection

KSZ8794CNX SW4-RGMII Connection

External GMAC/GPHY KSZ8794CNX SW4-RGMII

Signals Type Description

MRX_CTL TXD4_CTL Input Transmit control

MRXD[3:0] TXD4[3:0] Input Transmit data bit [3:0]

MRX_CLK GTX4_CLK Input Transmit clock

MTX_CTL RXD4_CTL Output Receive control

MTXD[3:0] RXD4[3:0] Output Receive data bit [3:0]

MGTX_CLK GRXC4 Output Receive clock

The RGMII interface operates at up to a 1000Mbps speed rate. Additional transmit and receive signals control the

different direction of the data transfer. This RGMII interface supports RGMII Rev 2.0 with adjustble ingress clock and

egress clock delay by the Register 86 (0x56).

For RGMII correct configuration with the connection partner, the Register 86 (0x56) bits [4:3] need to setup correctly, a

configuration table as below.

Table 8. Port 4 SW4-RGMII Clock Delay Configuration with Connection Partner.=

KSZ8794

Bits [4:3]

Configuration

RGMII Clock Mode

(Recei ve and

Transmit)

KSZ8794

KSZ8794 RGMII

Clock

Delay/Slew

Configuration

Connection Partner RGMII Clock

Configuration

(A pro ce ssor, an external GPHY or

back to back connection)

Bit [4:3]=11

Mode Ingress Clock Input Bit [4] = 1 Delay No Dela y

Egress Clock Output Bit [3] = 1 Delay No Delay

Bit [4:3]=10

Mode Ingress Clock Input Bit [4] = 1 Delay No Delay

Egress Clock Output Bit [3] = 0 No Delay Delay

Bit [4:3]=01

Mode Ingress Clock Input Bit [4] = 0 (default) No Delay Delay

Egress Clock Output Bit [3] = 1 (default) Delay No Delay

Bit [4:3]=00

Mode Ingress Clock Input Bit [4] = 0 No Delay Delay

Egress Clock Output Bit [3] = 0 No Delay Delay

For example, two KSZ8795 devices are the back to back connection, if one device set bit [4:3] =’11’, another one should

set bit [4:3] = ‘00’. If one device set bit [4:3] =’01’, another one should set bit [4:3] = ‘01’ too.

The RGMII mode is configured by the strap-in pin LED3 [1:0] =’11’ (default) or Register 86 (0x56) bits [1:0] = ‘11’ (default).

The speed choice is by the strap-in pin LED1_0 or Register 86 (0x56) bit [6], the default speed is 1Gbps with bit [6] = 1’,

set bit [6] = ‘0’ is for 10/100Mbps speed in RGMII mode. KSZ8795CLX provides Register 86 Bits [4:3] with the adjustable

clock delay and Register 164 Bits [6:4] with the adjustable drive strength for best RGMII timing on board level in 1Gbps

mode.

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KSZ8794CNX

Port 4 GMAC4 SW 4-MII Interface

Table 9 shows two c onnection methods belo w:

1. The first is an external MAC connecting in SW4-MII PHY mode.

2. The second is an ex t ernal PHY connecting in SW4-MII MAC mode.

3. The MAC mode or PHY mode setting is determined by t he st rap pin LED2_1.

Table 9. Port 4 SW4-MII Connection

MAC to MAC Connection

KSZ8794CNX SW4-MII PHY Mode MAC to PHY Connection

KSZ8794CNX SW4-MII MAC Mode

External MAC KSZ8794CNX SW4-MII

Signals Type Description External

PHY KSZ8794CNX

SW4-MII Signals Type

MTXEN TXEN4 Input Transmit enable MTXEN RXDV4 Output

MTXER TXER4 Input Transmit error MTXER RXER4 Output

MTXD[3:0] TXD4[3:0] Input

Transmit data bit

[3:0]

MTXD[3:0] RXD4[3:0] Output

MTXC TXC4 Output Transmit clock MTXC RXC4 Input

MCOL COL4 Output

Collision detection MCOL COL4 Input

MCRS CRS4 Output

Carrier sense MCRS CRS4 Input

MRXDV RXDV4 Output Receive data valid MRXDV TXEN4 Input

MRXER RXER4 Output Receive error MRXER TXER4 Input

MRXD[3:0] RXD4[3:0] Output

Receive data bit

[3:0]

MRXD[3:0] TXD4[3:0] Input

MRXC RXC4 Output Receive clock MRXC TXC4 Input

The MII interface operates in either MAC mode or PHY mode. These interfaces are nibble-wide data interfaces, so they

run at one-quarter the network bit rate (not encoded). Additional signals on the transmit side indicate when data is valid or

when an error occurs du ring transmission. Likewise, the receive side has indicators that conv ey when the data is valid and

without physical layer errors. For half-duplex operation, there is a COL signal that indicates a collision has occurred during

transmission.

Note: Normally MRXER would indicate a receive error coming from the physical layer device. MTXER would indicate a transmit error from the MAC

device. These signals are not appropriate for this configuration. For PHY mode operation with an external MAC, if the device interfacing with the

KSZ8794CNX has an MRXER pin, it can be tied low. For MAC mode operation with an external PHY, if the device interfacing with the KSZ8794CNX has

an MTXER pin, it can be tied low.

Port 4 GMAC4 SW 4-RMII Interface

The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). The

KSZ8794CNX supports RMII interface on Port 4 and provides the followin g key characteristics:

• Supports 10Mbps and 100Mbps data rates.

• Uses a single 50MHz clock reference (provided internally or externally): In internal mode, the chip provides a

reference clock from the RXC4 pin to the opposite clock input pin for RMII interface when Port 4 RMII is set to

clock mod e .

• In external mode, the chip receives 50MHz reference cl ock on the TXC 4 /R EFCLKI4 p in from an external oscillator

or opposite RMII interface when the device is set to normal mode.

• Provides independ ent 2-bit wide (bi-bit) transmit and receive data paths.

• For the details of SW4-RMII (Port 4 GMAC4 RMII) signal connecti on, see t he table below:

When the device is strapped to normal mode, the reference clock comes from the TXC4/REFCLKI4 pin and will be used

as the device’s clock source. Set the strap pin LED1_1 can select the device’s clock source either from the

TXC4/REFCLKI4 pin or from an external 25M Hz crystal/oscillator clock on the XI/XO pin.

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KSZ8794CNX

In internal mode, when using an internal 50MHz clock as SW4-RMII reference clock, the KSZ8794CNX Port 4 should be

set to clock mode by the strap pin LED2_1 or the port Register 86 bit [7]. The clock mode of the KSZ8794CNX device will

provide the 50MHz reference clock to the Port 4 RMII interface.

In external mode, when using an external 50MHz clock source as SW4-RMII reference clock, the KSZ8794CNX Port 4

should be set to normal mode by the strap pin LED2_1 or the port Register 86 bit [7]. The normal mode of the

KSZ8794CNX device will start to work when it receives the 50MHz reference clock on the TXC4/REFCLKI4 pin from an

external 50M Hz cl o ck sou r ce.

Table 10. Port 4 SW4-RMII Connection

SW4-RMII MAC to MAC Connection

(‘PHY mode’) SW4-RMII MAC to PHY Connection

(‘MAC mode’)

External

MAC KSZ8794CNX

SW4-RMII KSZ8794CNX

SW Signal Type Description External

PHY KSZ8794CNX

SW4-RMII KSZ8794CNX SW

Signal Type

REF_CLKI RXC4 Output 50MHz i n

Clock mode Reference Clock 50MHz REFCLKI4

Input 50MHz in

Normal Mode

CRS_DV RXDV4

/CRSDV4 Output Carrier

Sense/Receiv e data

valid CRS_DV TXEN4 Input

Receive error RXER TXER4 Input

RXD[1:0] RXD4[1:0] Output Receive data bit

[1:0] RXD[1:0] TXD4[1:0] Input

TX_EN TXEN4 Input Transmit data

enable TX_EN RXDV4

/CRSDV4 Output

TXD[1:0] TXD4[1:0] Input Transmit data bit

[1:0] TXD[1:0] RXD4[1:0] Output

50MHz REFCLKI4 I nput 50MHz in

Normal Mode R eference Clo c k REF_CLKI RXC4 Output 50MHz i n

Clock mode

Note: MAC/PHY mode in RMII is different than MAC/PHY mode in MII. There is no strap pin and register configuration request in RMI. Follow the

signals connection in the table.

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KSZ8794CNX

Functional Overview: Advanced Functionality

QoS Priority Support

The KSZ8794CNX provides Quality of Service (QoS) for applications such as VoIP and video conferencing. The

KSZ8794CNX offers one, two, or four priority queues per port by setting the Port Control 13 Register bit [1] and the Port

Control 0 Register bit [ 0], the 1/2/4 queues split as follows:

[Port Control 9 bit [1], Control 0 Register bit [0]] = 00 Single output queue as default .

[Port Control 9 bit [1], Control 0 Register bit [0]] = 01 Egress Port can be split i nto two priority transmi t queues.

[Port Control 9 bit [1], Control 0 Register bit [0]] = 10 Egress Port can be split into four priority transmit queues.

The four priority transmit queue is a new feature in the KSZ8794CNX. Queue 3 is the highest priority queue and queue 0

is the lowest priority queue. The Port Control 9 Register bit [1] and the Port Control 0 Register bit [0] are used to enable

split transmit queues for Ports 1, 2, 3 and 4, respectively. If a Port's transmit queue is not split, high priority and l ow priority

packets have equal priority in the transmit queue.

There is an additional option to either always deliver high priority packets first or to use programmable weighted fair

queuing for the four priority queue scale by the Port Control 14, 15, 16 and 17 Registers (default values are 8, 4, 2, 1 by

their bits [6:0].

Register 130 bit [7:6] Prio_2Q[1:0] is used when the 2 Queue configuration is selected. These bits are used to map the 2-

bit result of IEEE 802.1p from the registers 128, 129 or TOS/DiffServ mapping from Registers 144-159 (for 4 Queues) into

two-queue mode wit h priority high or low.

Please see the descri ptions of Register 130 bits [7:6] for detail.

Port-based Priority

With port-based priority, each ingress Port is individually classified as a priority 0-3 receiving Port. All packets received at

the priority 3 receiving Port are marked as high priority and are sent to the high-priority transmit queue if the

corresponding transmit queue is split. The Port Control 0 Register bits [4:3] is used to enable Port-based priority for Ports

1, 2, 3 and 4, respectively.

802.1p-based Priori ty

For 802.1p-based priority, the KSZ8794CNX examines the ingress (incoming) packets to determine whether they are

tagged. If tagged, the 3-bit priority field in the VLAN tag is retrieved and compared against the “priority mapping” value, as

specified by the registers 128 and 129, both register 128/129 can map 3-bit priority field of 0-7 value to 2-bit result of 0-3

priority levels. The “priority mapping” value is programmable.

Figure 9 illustrat es how the 802.1p priority field is embedded in the 802.1Q VLAN tag.

Figure 9. 802.1p Priority Field Format

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KSZ8794CNX

802.1p-based pri orit y is enabled by bit [5] of the Port Control 0 Regist ers for ports 1, 2, 3 and 4, respectively.

The KSZ8794CNX provides the option to insert or remove the priority tagged frame's header at each individual egress

port. This header, consisting of the two-byte VLAN Protocol ID (VPID) and the tw o-byte tag control Information field (TCI),

is also referred to as t he IEEE 802.1Q VLAN tag.

Tag Insertion is enabled by bit[2] of the Port control 0 Register and the Port Control 8 Register to select which source

port (ingress port) PVID can be inserted on the egress port for Ports 1, 2, 3 and 4, respectively. At the egress port,

untagged packets are tagged with the ingress port’s default tag. The default tags are programmed in the Port Control 3

and control 4 register for ports 1, 2, 3 and 4, respecti vely. The KSZ8794CNX will not add tags to already tagged packets.

Tag Removal is enabled by bit [1] of the port registers control 0 for Ports 1, 2, 3 and 4, respectively. At the egress port,

tagged packets will have their 802.1Q VLAN tags removed. The K S Z 8794CNX will not modify untagged packets.

The CRC is recalcul at ed f or both tag insertion and tag removal.

802.1p Priority Field Re-mapping is a QoS feature that allows the KSZ8794CNX to set the “User Prior ity Ceiling” at any

ingress port by the Port Control 2 Register bit [7]. If the ingress packet’s priority field has a higher priority value than the

default tag’s prio rit y field of the ingress port , the packet’s priorit y field is replaced with the default tag’s priority field.

DiffServ-Based Priority

DiffServ-based priority uses the ToS registers (Registers 144 to 159) in the Advanced Control Registers section. The ToS

priority control registers implement a full y decoded, 128-bit differen tiated services code point (DSCP) register to det ermine

packet priority from the 6-bit ToS field in the IP header. When the most significant six bits of the ToS field are fully

decoded, 64 code points for DSCP result. These are compared with the corresponding bits in the DSCP register to

determine priority .

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KSZ8794CNX

Spanning Tree Support

Port 4 is the designate d port for spanning tree support.

The other ports (Port 1 - Port 3) can be configured in one of the five spanning tree states via “transmit enable,” “receive

enable,” and “learning disable” register settings in Registers 18, 34 and 50 for Ports 1, 2 and 3, respectively. The following

description shows the port setting and software actions taken for each of the five spanni ng tree states.

The KSZ8794CNX supports common spanning tree (CST). To support spanning tree, the host port (Port 4) is the

designated port for the processor. The other ports can be configured in one of the five spanning tree states via “transmit

enable”, “receive enabl e” and “learning disable” register settings in Port Control 2 Registers. T he following table shows the

port setting and softw are actions taken for ea ch of the five spanning t ree st at es.

Disable State Port Setting Software Action

The port should not

forward or rec eive any

packets. Lear ning is

disabled.

"Transmit enable = 0,

Receive enable = 0,

Learning disable = 1."

The processor should not sen d any packets to t he port. The switch m ay still

send specific packets to the processor (pac kets that match some entries i n the

static table with “overriding bit” set) and the processor should discard those

packets.

Note: Processor is connected to Port 4 via MII interface. Address learning is disabled on

the port in this state.

Blocking S tate Port Setting Software Action

Only packets t o the

processor are

forwarded. Learning is

disabled.

"Transmit enab l e = 0,

Receive enable = 0,

Learning disable = 1"

The processor should not sen d any packets to t he port(s) in this state. The

processor should program the “Static MAC table” with the e ntries that it ne eds

to receive (e.g., BPDU packets). The “over r i ding” bit shoul d also be set so t hat

the switch will forward those specific pack ets to the proces sor. Address

learning is disabled on the Port in this state.

Listening State Port Setting Software Action

Only packets t o and

from the processor are

forwarded. Learning is

disabled.

"Transmit enable = 0,

Receive enable = 0,

Learning disable = 1.

The processor should program the static MAC table with the entries that it

needs to receive (e.g. BPDU p ac kets). The “over riding” bit should be set so that

the switch will forward those specific pack ets to the processor. The processor

may send pack ets to the port(s) in this state, see “Tail Taggi ng Mode” section

for details. Address lear ning is disabled on the port in this state.

Learning State Port Setting Software Ac tion

Only packets t o and

from the processor are

forwarded. Learning is

enabled.

“Transmit enable = 0,

Receive enable = 0,

Learning disable = 0.”

The processor should program the static MAC table with the entries that it

needs to receive (e.g., BPDU pac kets). The “over riding” bit should be set so

that the switc h wi ll forward thos e specific packets to the process or. The

processor may send packets to the port(s) i n this state, s ee “Tail Tagging

Mode” section for details. Address lear ning is enable d on the port in this state.

Forwarding State

Port Setting

Software Action

Packets are forwarded

and received normally.

Learning is en abled.

“Transmit enable = 1,

Receive enable = 1,

Learning disable = 0.”

The processor should program the static MAC table with the entries that it

needs to receive (e.g., BPDU pac kets). The “over riding” bit should be set so

that the switc h wi ll forward thos e specific packets to the proces sor. The

processor may send packets to the port(s) in this state, s ee “Tail Tagging

Mode” section for details. Address lear ning is enable d on the port in this state.

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Rapid Spanning Tree Support

There are three operational states of the discarding, learning, and forwarding assigned to each port for RSTP. Discarding

ports do not participate in the active topology and do not learn MAC addresses. Ports in the Learning states learn MAC

addresses, but do not forward user traffic. Ports in the Forwarding states fully participate in both data forwarding and MAC

learning. RSTP uses only one type of BPDU called RSTP BPDUs. They are similar to STP C onfiguration BPDUs with the

exception of a ty pe field set to “version 2” for RSTP and “version 0” f or S TP, and flag field carrying additional informati on.

Disable State

Port Setting

Software Actio n

The state inc l udes

three states of the

disable, bloc k ing and

listening of STP.

"Transmit enable = 0,

Receive enable = 0,

Learning disable = 1."

The processor should not sen d any packets to t he port. The switch m ay still

send specific packets to the processor (pac kets that match some entries i n the

static table with “overriding bit” set) and the processor should discard those

packets. When disable the port’s learning c apability (learning disa bl e = ’1’), set

the Register 2 bit [5] and bit [4] will flush rapidly with the port relat ed entries in

the dynamic MA C table and stat ic MAC table. Not e: processor is c onnected to

Port 4 via MII interface. Address learning is dis abled on the port in this state.

Learning State

Port Setting

Software Action

Only packets t o and

from the processor

are forwarded.

Learning is en abled.

“Transmit enable = 0,

Receive enable = 0,

Learning disable = 0.”

The processor should program the static MAC table with the entries that it

needs to receive (e.g., BPDU pac kets). The “over riding” bit should be set so

that the switc h wi ll forward thos e specific packets to the process or. The

processor may send packets to the port(s) in this stat e, see “Tail Tagging

Mode” section for details. Address learning is enabled on the port in t his state.

Forwarding State

Port Setting

Software Actio n

Packets are

forwarded and

received normally.

Learning is en abled.

“Transmit enable = 1,

Receive enable = 1,

Learning disable = 0.”

The processor should program the static MAC table with the entries that it

needs to receive (e.g., BPDU pac k ets). The “overriding” bit should be set so

that the switc h wi ll forward thos e specific packets to the process or. The

processor may send packets to the port(s) in this state, s ee “Tail Tagging

Mode” section for details. Address learning is enabled on the port in t his state.

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Tail Tagging Mode

The tail tag is only seen and used by the Port 4 interface, which should be connected to a processor by the SW4- RGMII,

MII or RMII interfaces. One byte tail tagging is used to indicate the source/destination port on port 4. Only bits [3:0] are

used for the destination in the tail tagging byte. Other bits are not used. The tail tag feature is enabled by setting Register

12 bit [1].

Figure 10. Tail Tag Frame Format

Table 11. Tail Tag Rules

Ingress to Port 4 (Host --> KSZ8794CNX)

Bits [3:0] Destination

0,0,0,0 Reserved

0,0,0,1 Por t 1 (Direct forward to Port 1)

0,0,1,0 Por t 2 (Direct forward to Port 2)

0,1,0,0 Por t 3 (Direct forward to Port 3)

1,0,0,0 Reserved

x,1,1,1 Port 1, 2 and 3 (direct forward to Port 1, 2, 3)

Bits [7:4]

0,0,0,0 Q ueue 0 is used at desti nation Port

0,0,0,1 Q ueue 1 is used at desti nation Port

0,0,1,0 Q ueue 2 is used at desti nation Port

0,0,1,1 Q ueue 3 is used at desti nation Port

0, 1,x,x Anyhow send pack ets to specif i ed P ort in bits [3:0]

1, x,x,x Bits [6:0] will be ignored as normal (Address look-up)

Egress from P ort 4 (KSZ8794CNX --> Host)

Bits [1:0]

Source

0,0 Port 1 (Packets from Port 1)

0,1 Port 2 (Packets from Port 2)

1,0 Port 3 (Packets from Por t 3)

1,1 Reserved

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IGMP Support

There are two components involved with the support of the internet group management protocol (IGMP) in layer 2. The

first part is IGMP snooping, the second part is this IGMP packet which is sent back to the subscribed port. Those

components are de scribed below.

IGMP Snooping

The KSZ8794CNX traps IGMP packets and forwards them only to the processor (port 4 SW4-RGMII/MII/RMII). The IGMP

packets are identified as IP packets (either Ethernet IP packets, or IEEE 802.3 SNAP IP packets) with IP version = 0x4

and protocol version number = 0x2. Set Register 5 bit [6] to ‘1’ to enable IGMP s nooping.

IGMP Send Back to the Subscribed Port

Once the host responds to the received IGMP packet, the host should know the original IGMP ingress port and send back

the IGMP packet to this port only, to avoid this IGMP packet being broadcast to all ports which will downgrade the

performance.

With the tail tag mode enabled, the host will know the port which IGMP packet has been received from tail tag bits [1:0]

and can send back the response IGMP packet to this subscribed port by setting bits [3:0] in the tail tag. Enable “Tail Tag

Mode” by setting register 12 bit[1].

IPv6 MLD Snooping

The KSZ8794CNX traps IPv6 multicast listener discovery (MLD) packets and forwards them only to the processor (Port

4). MLD snooping is controlled by Register 164 bit [2] (MLD snooping enable) and Register 164 bit [3] (MLD option).

With MLD snooping enabled, the KSZ8794CNX traps packets t hat meet all of the following conditions:

• IPv6 multicast pack ets

• Hop count limit = 1

• IPv6 next header = 1 or 58 (or = 0 with hop-by-hop next header = 1 or 58) If the MLD option bit is set to “1”, the

KSZ8794CNX traps packets with the following additional condit ion:

• IPv6 next header = 43, 44, 50, 51, or 60 (or = 0 with hop-by-hop next header = 43, 44, 50, 51, or 60)

• For MLD snooping, tail tag mode also needs to be enabled, so that the processor knows which port the MLD packet

was received on. This is achieved by set t i ng register 12 bit [1].

Port Mirroring Support

The KSZ8794CNX sup ports “port mirror” as described below:

“Receive Only” Mirror on a Port

All the packets received on the port will be mirrored on the sniffer sort. For example, Port 1 is programmed to be “rx sniff,”

and Port 4 is programmed to be the “sniffer port.” A packet, received on Port 1, is destined to Port 3 after the internal look-

up. The KSZ8794CNX will forward the packet to both Port 3 and Port 4. KSZ8794CNX can optionally forward even “bad”

received packets to Port 3.

“Transmit Only” Mirror on a Port

All the packets transmitted on the port will be mirrored on the sniffer port. For example, Port 1 is programmed to be “tx

sniff,” and Port 4 is programmed to be the “sniffer port.” A packet, received on any of the ports, is destined to Port 1 after

the internal look-up. T he KSZ8794CNX will forward the packet to both Ports 1 and 4.

“Receive and Transmit” Mi rror on two Ports

All the packets received on Port A AND transmitted on Port B will be mirrored on the sniffer port. To turn on the “AND”

feature, set Register 5 bit 0 to 1. For example, Port 1 is programmed to be “rx sniff,” Port 2 is programmed to be “tx sniff,”

and Port 4 is programmed to be the “Sniffer Port.” A packet, received on Port 1, is destined to Port 3 after the internal

look-up. The KSZ8794CNX will forward the packet to Port 4 only, since it does not meet the “AND” condition. A packet,

received on Port 1, is destined to Port 2 after the internal look-up. The KSZ8794CNX will forward the packet to both Port 2

and Port 4, since it doe s meet the “AND” condition.

Multiple ports can be selected to be “rx sniffed” or “tx sniffed.” Any port can be selected to be the “sniffer port.” All these

per port features can be selected through the Port Control 1 Register.

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KSZ8794CNX

VLAN Support

The KSZ8794CNX supports 128 active VLANs and 4096 possible VIDs specified in IEEE 802.1q. KSZ8794CNX provides

a 128-entry VLAN table, which correspond to 4096 possible VIDs and converts to FID (7 bits) for address look-up max

128 active VLANs. If a non-tagged or null-VID-tagged packet is received, then the ingress port VID is used for look-up

when 802.1q is enabled by the global register 5 control 3 bit [7]. In the VLAN mode, the look-up process starts from VLAN

table look-up to determine whether the VID is valid. If the VID is not valid, the packet will then be dropped and its address

will not be learned. If the VID is valid, FID is retrieved for further look-up by the static MAC table or dynamic MAC table.

FID+DA is used to determine the destination port. The following table describes the different actions in different situations

of DA and FID+DA in the static MAC table and dynamic MAC table after the VLAN table finish a look-up action. FID+SA is

used for learning purposes. The following table also describes learning in the dynamic MAC table when the VLAN table

has done a look-up in the static MAC table wit hout a valid entry.

Table 12. FID+DA Look-Up in the VLAN Mode

DA found in

Static MAC table USE FID

Flag? FID Match? DA+FID found in

Dynamic M AC table Action

No Don’t care Don’t care No Broadcast to the membership ports defined in the

VLAN table bits [11:7].

No Don’t care Don’t care Yes Send to the destination port defined in the d y namic

MAC table bits [58:56].

Yes 0 D on’t care Don’t c are Send to the destination port(s) def ined in the stat ic

MAC table bits [52:48].

Yes 1 No No Broadcast to the membership ports defined in the

VLAN table bits [11:7].

Yes 1 No Yes Send to the destinatio n port defined in t he dynamic

MAC table bits [58:56].

Yes 1 Yes Don’t care S end to the desti nation port(s) defined in the s tatic

MAC table bits [52:48].

Table 13. FID+SA Look-Up in the VLAN Mode

SA+FID found in

Dynamic M AC table

Action

No The SA+FID will be learned into the dynamic table.

Yes Time stamp will be updated.

Advanced VLAN features are also supported in KSZ8794CNX, such as “VLAN ingress filtering” and “discard non PVID”

defined in bits [6:5] of the Port Control 2 Regi st er. These features can be controlled on a por t basis.

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Rate Limiting Support

The KSZ8794CNX provides a fine resolution hardware rate limiting based on both bit per second (bps) and packet per

second (pps).

For bps, the rate step is 64kbps when the rate lim it is less than 1Mbps rate for 10 0BT or 10BT, and 640kbps for 1000. The

rate step is 1Mbps when the rate limit is more than 1Mbps rate for 100B T or 10BT, 10Mbps for 1000.

For pps, the rate step is 128pps (besides the 1st one which is 64pps) when the rate limit is less than 1Mbps rate for

100BT or 10BT, and 1280pps (except the 1st one of 640pps) for 1000. The rate step is 1Mbps when the rate limit is more

than 1.92Kpps rate for 100BT or 10BT, 19.2kpps for 1000.

Refer to the table below. Note: the pps limiting is bounded by bps rate for each pps setting, the mapping is shown in the

2nd column of the t abl e.

Table 14. 10/100/ 1000Mbps Rate Selection for the Rate limit

Item Bps bound of pps

(egress only) 10Mbps 100Mbps 1000Mbps

Code Code PPS BPS PPS BPS PPS BPS

7’d0 7’d0 19.2Kpps 10Mbps 192Kpps 100Mbps 1.92Mpps 1000Mbps

7d’1 – 7d’10 7d’3,6, (8x)10 1.92Kpps

* code 1Mbps

* code 1.92Kpps *

code 1Mbps *

code 19.2Kpps *

code 10Mbps *

code

7d’11 – 7d’100 7d’11 – 7d’100 10Mbps 1.92Kpps *

code 1Mbps *

code 19.2Kpps *

code 10Mbps *

code

7d’101 7d’102 64pps 64Kbps 64pps 64Kbps 640pps 640Kbps

7d’102 7d’104 128pps 128Kbps 128pps 128Kbps 1280pps 1280Kbps

7d’103 7d’108 256pps 192Kbps 256pps 192Kbps 2560pps 1920Kbps

7d’104 7d’112 384pps 256Kbps 384pps 256Kbps 3840pps 2560Kbps

7d’105 7d’001 512pps 320Kbps 512pps 320Kbps 5120pps 3200Kbps

7d’106 7d’001 640pps 384Kbps 640pps 384Kbps 6400pps 3840Kbps

7d’107 7d’001 768pps 448Kbps 768pps 448Kbps 7680pps 4480Kbps

7d’108 7d’002 896pps 512Kbps 896pps 512Kbps 8960pps 5120Kbps

7d’109 7d’002 1024pps 576Kbps 1024pps 576Kbps 10240pps 5760Kbps

7d’110 7d’002 1152pps 640Kbps 1152pps 640Kbps 11520pps 6400Kbps

7d’111 7d’002 1280pps 704Kbps 1280pps 704Kbps 12800pps 7040Kbps

7d’112 7d’002 1408pps 768Kbps 1408pps 768Kbps 14080pps 7680Kbps

7d’113 7d’003 1536pps 832Kbps 1536pps 832Kbps 15360pps 8320Kbps

7d’114 7d’003 1664pps 896Kbps 1664pps 896Kbps 16640pps 8960Kbps

7d’115 7d’003 1792pps 969Kbps 1792pps 969Kbps 17920pps 9690Kbps

The rate limit is independently on the “receiving side” and on the “transmitting side” on a per port basis . For 10 BASE-T, a

rate setting above 10Mbps means the rate is not li m i ted.

On the receive side, the data receive rate for each priority at each port can be limited by setting up ingress rate control

registers. On the transmit side, the data transmit rate for each queue at each port can be limited by setting up Egress

Rate Control registers. For bps mode, the size of each frame has options to include minimum IFG (Inter Frame Gap) or

preamble byte, i n addi tion to the data fiel d (f rom packet DA to FCS).

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Ingress Rate Limit

For ingress rate limiting, KSZ8794CNX provides options to selectively choose frames from all types; multicast, br oadcast,

and flooded unicast frames via bits [3:2] of the Port Rate Limit Control Register. The KSZ8794CNX counts the data rate

from those selected type of frames. Packets are dropped at the ingress port when the data rate exceeds the specified

rate limit or the flow control takes effect without packet dropped when the ingress rate limit flow control is enabled by the

Port Rate Limit Control Register bit [4]. The ingress rate limiting supports the port-based, 802.1p and DiffServ-based

priorities, the Port-based priority is fixed priority 0-3 selection by bits [4:3] of the port Control 0 Register. The 802.1p and

DiffServ-based priority can be mapped to priority 0-3 by default of the Register 128 and 129. In the ingress rate limit, set

Register 135 Global Control 19 bit [3] to enable queue-based rate limit if u sing two-queue or four-queue mode. All related

ingress ports and egress port should be split to two-queue or four-queue mode by the Port Control 9 and Control 0

Registers. The four-queue mode will use Q0-Q3 for priority 0-3 by bi ts [6:0] of the Port Register Ingress Limit Control 1-4.

The two-queue mode w ill use Q0-Q1 for priority 0-1 by bits [6:0] of the port ingress limit control 1-2 Registers. The priority

levels in the packets of the 802.1p and DiffServ can be programmed to priority 0-3 via the Register 128 and 129 for a re-

mapping.

Egress Rate Limit

For egress rate limiting, the leaky bucket algorithm is applied to each output priority queue for shaping output traffic. Inter-

frame gap is stretched on a per frame base to generate smooth, non-burst egress traffic. The throughput of each output

priority queue is limited by the egress rate specified by the data rate selection table followed the egress rate limit control

registers.

If any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in the

output queue and packet memory. After the memory of the queue or the port is used up, packet dropping or flow control

will be triggered. As a result of congestion, the actual egress rate may be dominated by flow control/dropping at the

ingress end, and may be therefore slightly less than the specified egress rate. The egress rate limiting suppor ts the port-

based, 802.1p and DiffServ-based priorities, the port-based priority is fixed priority 0-3 selection by bits [4:3] of the port

Control 0 Register. The 802.1p and DiffServ-based priority can be mapped to priority 0-3 by default of the Register 128

and 129. In the egress rate limit, set Register 135 Global Control 19 bit [3] for queue-based rate limit to be enabled if

using two-queue or four-queue mode. All related ingress ports and egress port should be split to two-queue or four-queue

mode by the Port Control 9 and Control 0 Registers. The four-queue mode will use Q0-Q3 for priority 0-3 by bits [6:0] of

the port Egress Limit Control 1-4 Register. The two-queue mode will use Q0-Q1 for priority 0-1 by bits [6:0] of the Port

Egress Rate Limit Control 1-2 Register. The priority levels in the packets of the 802.1p and DiffServ can be programmed

to priority 0-3 by Regi st er 128 and 129 for a re-mapping.

When the egress rate is limited, just use one queue per port for the egress port rate limit. The priority packets will be

based upon the data rate selection table (see Tables 13 above). If the egress rate limit uses more than one queue per

port for the egress port rate limit, then the highest priority packets will be based upon the data rate selection table for the

rate limit exact number. Other lower priority packet rates will be limited based upon 8:4:2:1 (default) priority ratio, which is

based on the highest pri ority rate. The t ransmit queue priority ratio is programmable.

To reduce congestion, it is good practice to make sure the egress bandwidth exceeds the ingr ess bandwidth.

Transmit Queue Ratio Programmi ng

In transmit queues 0-3 of the egress port, the default priority ratio is 8:4:2:1. The priority ratio can be programmed by the

port control 10, 11, 12 and 13 registers. When the transmit rate exceeds the ratio limit in the transmit queue, the transmit

rate will be limited by the transmit queue 0-3 ratio of the port control 10, 11, 12 and 13 registers. The highest priority

queue will not be lim ited. Other lower priority queues will be limited based on the transmit queue ratio.

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KSZ8794CNX

VLAN and Address Filtering

To prevent certain kinds of packets that could degrade the quality of the switch in applications such as voice over Internet

protocol (VoIP), the switch provides the mechanism to filter and map the packets with the following MAC addresses and

VLAN IDs.

• Self-address packets

• Unknown unicast pac kets

• Unknown multicast packets

• Unknown VID packet s

• Unknown IP multicast packets

The packets sourced from switch itself can be filtered out by enabling self-address filtering via the Global Control 18

The unknown unicast packet filtering can be enabled by the Global Control Register 15 bit [5] and bits [4:0] specify the

port map for forwar ding.

The unknown multi cast packet filtering can be enabled by the Global Control Register 16 bit [5] and forwarding port map is

specified in bits [4:0].

The unknown VID packet filtering can be enabled by Global Control Register 17 bit [5] with forwarding por t map specified

in bits [4:0].

The unknown IP multicast packet filtering can be enable by Global Control Register 18 bit [5] with forwarding

port map specified in bits [4:0].

Those filtering abov e are global based.

802.1X Port-Bas ed Security

IEEE 802.1x is a port-based authentication protocol. EAPOL is the protocol normally used by the authentication process

as uncontrolled port. By receiving and extracting special EAPOL frames, the microprocessor (CPU) can control whether

the ingress and egress ports should forward packets or not. If a user port wants service from another port (authenticator),

it must get approved by the authenticator. The KSZ8794 detect EAPOL frames by checking the destination address of the

frame. The destination addresses should be either a multicast address as defined in IEEE 802.1x (01-80-C2-00-00-03) or

an address used in the programmable reserved multicast address domain with offset -00-03. Once EAPOL frames are

detected, the frames are forwarded to the CPU so it can send the frames to the authenticator server. Eventually, the CPU

determines whether the requestor is qualified or not based on its MAC_Source addresses, and frames are either accepted

or dropped.

When the KSZ8794CNX is configured as an authenticator, the Ports of the switch must then be configured for

authorization. In an authenticator-initiated port authorization, a client is powered up or plugs into the port, and the

authenticator port sends an Extensible Authentication Protocol (EAP) PDU to the supplicant requesting the identification

of the supplicant. At this point in the process, the port on the switch is connected from a physical standpoint; however, the

802.1X process has not authorized the port and no frames are passed from the port on the supplicant into the switching

fabric. If the PC attached to the switch did not understand the EAP PDU that it was receiving from the switch, it would not

be able to send an ID and the port would remain unauthorized. In this state, the port would never pass any user traffic and

would be as good as disabled. If the client PC is running the 802.1X EAP, it would respond to the request with its

configured ID. (Thi s c oul d be a user name/password combinat i on or a certificate.)

After the switch, the authenticator receives the ID from the PC (the supplicant). The KSZ8794CNX then passes the ID

information to an authentication server (RADIUS server) that can verify the identification information. The RADIUS server

responds to the switch with either a success or failure message. If the response is a success, the port will be authorized

and user traffic will be allowed to pass through the port like any switch port connected to an access device. If the

response is a failure, the port will remain unauthorized and, therefore, unused. If there is no response from the server,

then the port will also remain unauthoriz ed and will not pass any t raffic.

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Authentication Register and Progra mming Model

The Port Authentication Control Registers define the control of port based authentication. The per-port authentication can

be programmed in these registers. KSZ8794CNX provides three modes for implementing the IEEE 802.1x feature. Each

mode can be selected by setting the appropriate bits in the Port Authentication Registers.

When mode control bits AUTHENCIATION_MODE = 00 (pass mode), forced-authorization is enabled and a port is always

authorized and does not require any messages from either the supplicant or the authentication server. This is typically the

case when connecting to another switch, a router, or a server, and also when connecting to clients that do not support

802.1X. When ACL is en abled, all the packets are passed if they m i ss ACL rules, otherwise , ACL actions apply.

The Block mode (when AUTHENCIATION_MODE = 01) is the standard port based authentication mode. A port in this

mode sends EAP packets to the supplicant and will not become authorized unless it receives a positive response from the

authentication server. Traffic is blocked before authentication to all of the incoming packets, upon authentication, software

will switch to pass mode to allow all the incoming packets. In this mode, the source address of incoming packets is not

checked. Including the EAP address, the forwarding map of all reserved multicast addresses need to be c onfigured to be

allowed to be forwarded before and after authentication in lookup table. When ACL is enabled, packets except ACL hit are

blocked.

The third mode is called Trap mode (when AUTHENTICATION_MODE = 11'b). In this mode, all the packets are sent to

CPU port. If ACL is enabled, the missed packets would be forwarded to the CPU rather than dropped. All these per port

features can be selected through the Port Control 5 Register, bit [2] is used to enable ACL, bits [1:0] are for the modes

selected.

ACL Filtering

ACL (Access Control List) can be created to perform the protocol-independent layer 2 MAC, layer 3 IP or layer 4

TCP/UDP ACL filtering that filters incoming Ethernet packets based on the ACL rule table. The feature allows the switch

to filter customer traffic based on the source MAC address in the Ethernet header, the IP address in the IP header, and

the port number and protocol in the TCP header. This function can be performed through MAC table and ACL Rule table.

Besides multicast filtering handled using entries in the static table, ACL can be configured for all routed network protocols

to filter the packets of those protocols as the packets pass through the switch. Access lists can prevent certain traffic from

entering or exiti ng a net work.

Access Control Lists

KSZ8794CNX offers a rule-based access control list (ACL Rule table). ACL Rule table is an ordered list of access control

entries. Each entry specifies certain rules (a set of matching conditions and action rules) to permit or deny the packet

access to the switch fabric. The meaning of ‘permit’ or ‘deny’ depends on the context in which the ACL is used. When a

packet is received on an interface, the switch compares the fields in the packet against any applied ACLs to verify that the

packet has the permissions required to be forwarded, based on t he conditions specified in the lists.

The filter tests the packets against the ACL entries one-by-one. Usually the first match determines whether the router

accepts or rejects packets. However, it is allowed to cascade the rules to form more robust and/or stringent requirements

for incoming packets. ACLs allow switch filter ingress traffic based on the source, Layer 2 header destination MAC

address and Ethernet type, source, destination IP address in Layer 3 header, port number, and protocol in the Layer 4

header of a packet.

Each list consists of 3 parts: the Matching, the Action, and the Processing field. The Matching field specifies the rules that

each packet matches against and the Action field specifies the action taken if the test succeeds against the rules. The

figure below sho ws the format of ACL and a description of the individual fields.

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Figure 11. ACL Format

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Matching Field

MD [1:0]: MODE- there are three m odes of operation defi ned i n ACL.

MD = 00 disables t he current rule list. No action will be taken.

MD = 01 is qualification rules for Layer 2 MAC head er filtering.

MD = 10 is used for Layer 3 IP address filtering.

MD = 11 performs Layer 4 TCP port number/protocol fil t ering.

ENB [1:0]: ENABLE – Enabl es different rules in the cur rent list.

When MD = 01,

If ENB = 00, the 11 bits of the aggregated bit field from PM, P, RPE, RP, MM in the action field specify a count value for

packets matching the M A C address and type in the matching fields.

The count unit is def ined in MSB of the forward bit field; while = 0, µsec will be used and whi le = 1, msec will be use d.

The second MSB of the forwarded bit determines the algorithm used to generate an interrupt when the counter

terminates. When = 0, an 11-bit counter is loaded w ith the count value from the ACL and starts counting dow n every unit

of time. An interrupt is generated when it expires (i.e., the next qualified packet has not been received within the period

specified by the value). When = 1, the counter is incremented on every matched packet received and an interrupt is

generated when the terminal count reac hes t he count value in the ACL. The count resets t hereafter.

If ENB = 01, the MAC addr ess bit field is used for t est ing;

If ENB = 10, the MAC type bit field is used for testing;

If ENB = 11, both the MAC address and type are tested against these bit fields in the list.

When MD = 10,

If ENB = 01, the IP addre ss and mask or IP protocol is enabled to be tested accordingly.

If ENB = 10, the source and destination addresses are compared. The drop/forward decision is based on the EQ bit

setting.

When MD = 11,

If ENB = 00, protocol comparison is enabled.

If ENB = 01, TCP address comparison is selected.

If ENB = 10, UDP addres s comparison is selected.

If ENB = 11, the sequence number of the TCP is compared.

S/D: Source or destination selection

S/D = 0, the destination a ddress/port is compa red;

S/D = 1, the source is chosen.

E/Q: comparison algorithm:

E/Q = 0, match if they are not equal;

E/Q = 1, match if they are equal.

MAC Address [47 :0] : MAC source or destinati on address

TYPE [15:0]: MAC Ether Type

IP Address [31:0]: IP so urce or destination address

IP Mask [31:0]: IP address mask for gr oup address filtering

MAX Port [15:0], MIN Port [15:0] (Sequence Number [31:0]): The range of TCP Port number or sequence number

matching.

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PC [1:0]: Port Comparison

PC = 00, the compariso n is disabled.

PC = 01, matches eithe r one of MAX or MIN.

PC = 10, match if the Port num ber is in the range of MAX to MIN.

PC = 11, match if the Port num ber is out of the range.

PRO [7:0]: IP Protocol to be matche d

FME: Flag Match Enable

FME = 0, disable TCP FLAG m at ching.

FME = 1, enable TCP FLA G m atching

FLAG [5:0]: TCP Flag to be matched.

Action Field

PM [1:0]: Pri ority Mode

PM = 00, no priority is sele ct ed, t he priority is determi ned by the QoS/Classification is used.

PM = 01, the priority in P bit f i el d i s used i f it is greater than QoS re sult.

PM = 10, the priority in P bit f i el d i s used i f it is smaller than QoS result.

PM = 11, the P bit field will repla ce t he priority determi ned by QoS.

P [2:0]: Priority.

RPE: Remark Priority Ena bl e -

RPE = 0, no remarking is n ecessary.

RPE = 1, the VLAN priority bi ts in the tagged packets are replaced by RP bit field in the list.

RP [2:0]: Remarked Priori ty.

MM [1:0]: Map Mode

MM = 00, no forwarding remapping is neces sary.

MM = 01, the forwarding map in FORWORD is O R’ed with the Forwarding map from the look-up table.

MM = 10, the forwarding map in FORWORD is AND’ed with the Forwarding map from the loo k-up table.

MM = 11, the forwarding map in FORWORD repl aces the Forwarding m ap from the look-up table.

FORWARD Bits [4:0 ]: Forwarding Port(s) - Each bi t indicates the forwa rding decision of one P ort .

Processing Field

FRN Bits [3:0]: First Rule Number – Assign which entry with i ts Action Field in 16 entries is used in the rule set.

For the rule set, see description below.

RULESET Bits [15:0]: Rule Set - Group of rules to be qualified, there are 16 entries rule can be assigne d t o a rule set per

port by the two rule-set registers. The Rule table allows the rules to be cascaded. There are 16 entries in the RTB. Each

entry can be a rule on its own, or can be cascaded with other entries to form a rule set. The test result of incoming

packets against rule set will be the AND’ed result of all the test result of i ncoming packets against the rules included in this

rule set. The action of the rule set will be the action of the first rule specified in FR N field. The rule with higher priority will

have lower index number. Or rule 0 is the highest priority rule and rule 15 is the lowest priority. ACL rule table entry is

disabled when mode bits are set to 2’ b00.

A rule set (RULESET) is used to select the match results of different rules against incoming packets. These selected

match results will be AND’ed to determine whether the frame matches or not. The conditions of different rule sets having

the same action will be OR’ed for comparison with frame fields, and the CPU will program the same action to those rule

sets that are to be OR’ed together. For matched rule sets, different rule sets having different actions will be arbitrated or

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chosen based upon the first rule number (FRN) of each rule set. The rule table will be set up with the high priority rule at

the top of the table or with the smaller index. Regardless whether the matched rule sets have the same or different action,

the hardware will always compare the f i rs t rule number of diff erent rule sets to determine t he final rule set and act ion.

DOS Attack Prevention via ACL

The ACL can provide certain detection/protection of the following DoS (Denial of Service) attack types based on rule

setting, which can be p rogrammed to drop or not t o drop each type of DoS packet respectively.

Example 1:

When MD = ‘10’, ENABLE = ‘10’, setting EQ bit to ‘1’ can determine the drop or forward packets with identical source and

destination IP addresses in IPv4/IPv6.

Example 2: When MD = ‘11’, ENABLE = ‘01/10’, setting EQ bit to ‘1’ can determine the drop or forward packets with

identical source an d destination TCP/ UDP Ports in IPv4/IPv6.

Example 3:

When MD = ‘11’, ENABLE = ‘11’, Sequence Number = ‘0’, FME = ‘1’, FMSK = ‘00101001’, FLAG = ‘xx1x1xx1’, Setting the

EQ bit to ‘1’ will drop/forward the all packets with a TCP sequence number equal to ‘0’, and flag bit URG = ‘1’, PSH = ‘1’

and FIN = ‘1’.

Example 4:

When MD = ‘11’, ENABLE = ‘01’, MAX Port = ‘1024’, MIN Port = ‘0’, FME = ‘1’, FMSK = ‘00010010’, FLAG = ‘xxx0xx1x’,

Setting the EQ bit to ‘1’ will drop/forward the all packets with a TCP Port number ≤ 1024, and flag bi t URB = ‘0’, SYN = ‘1’.

ACL related registers are Register 110 (0x6E), Register 111 (0x6F), and the ACL rule tables.

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Device R egisters Mapping

The KSZ8794CLX device has a rich set of registers available to manage the functionality of the device. Access to these

registers is via the MIIM or SPI interfaces. The Figure below provides a global picture of accessibility via the various

interfaces and addressing ranges from t he perspective of each int erface.

Figure 12. Interface and Reg ister Mapping

The registers within the linear 0x00-0xFF address space are all accessible via the SPI interface by a CPU attached to that

bus. The mapping of the various function s wit hi n that linear add ress space is summari zed in table below.

Table 15. Mapping of Functional Areas within the Address Space

0x00 – 0xFF Switch Control and Configuration Registers which control the overall funct ionality of the

Switch, MAC, and PHYs

0x6E – 0x6F Indirect Control Registers

Registers used to indirectly address and access

distinct are as within the devic e.

- MIB (Management Information Base) Counters

- Static MAC Address Table

- Dynamic MAC Address Table

- VLAN Table

- PME Indirect Regi s ter

- ACL Indirect Register

- EEE Indirect R egister

0x70 – 0x78 Indirect Access Registers

Registers used to indirectly address and acc ess four

distinct are as within the devic e.

- MIB (Management Information Base)

Counters

- Static MAC Address Table

- Dynamic MAC Address Table

- VLAN Table

0xA0 Indirect Byte Access Registers

This indirect byt e register is u s ed to access:

- PME Indirect Registers

- ACL Indirect Registers

- EEE Indirect Registers

0x17 – 0x4F PHY1 to PHY4 MIIM registers mapping to those

port registers address rang e The same PHY registers as specified in IEE E 802.3

specification.

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Direct Register Description

Address Contents

0x00-0x01 Family ID, Chip ID, Revision ID, and start switch Regi s ters

0x02-0x0D Global Contro l R egisters 0 – 11

0x0E-0x0F G l obal Power Down Management Contr ol Registers

0x10-0x14 Port 1 C ontrol Registers 0 – 4

0x15 Port 1 Authentication Control Regist er

0x16-0x18 Port 1 R es erved (Factory Test Registers )

0x19-0x1F Port 1 Control/Status Registers

0x20-0x24 Port 2 C ontrol Registers 0 – 4

0x25 Port 2 Authentication Control Regist er

0x26-0x28 Port 2 R es erved (Factory Test Registers )

0x29-0x2F Port 2 Control/Status Registers

0x30-0x34 Port 3 C ontrol Registers 0 – 4

0x35 Port 3 Authentication Control Regist er

0x36-0x38 Port 3 R es erved (Factory Test Registers )

0x39-0x3F Port 3 Control/Status Regist ers

0x40-0x44 Port 4 C ontrol Registers 0 – 4

0x45 Port 4 Authentication Control Regist er

0x46-0x48 Port 4 Reserved ( Factory Test Regi s ters)

0x49-0x4F Port 4 Control/Status Registers

0x50-0x54 Port 4 Control Regis t ers 0 – 4

0x56-0x58 Port 4 Reserved (Factory Tes t Registers)

0x59-0x5F Port 4 Control/Stat us Registers

0x60-0x67 Reserved (Factory Testing Registers)

0x68-0x6D MAC Address Registers

0x6E-0x6F I ndi r ect Access Control Register s

0x70-0x78 Indirec t Data Registers

0x79-0x7B Reserved (Factory Testing Registers)

0x7C-0x7D Global Inter rupt and Mask Re gisters

0x7E-0x7F Res er ved (Fact ory Testing Registers)

0x80-0x87 Globa l Control Regist er s 12 – 19

0x88 Switch Self Test Control Register

0x89-0x8F QM Global Control Registers

0x90-0x9F Global TO S Priority Control Registers 0 - 15

0xA0 Global Indirect Byte Register

0xA0-0xAF Reserved (Fac tory Testing Re gi s ters)

0xB0-0xBE Port 1 Cont rol Registers

0xBF Reserved (Factory Testing Register): Transmit Queue Rem ap Base Register

0xC0-0xCE Port 2 Control Registers

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Address Contents

0xCF Reserv ed (Factor y T es ting Register)

0xD0-0xDE Port 3 Control Registers

0xDF Reserv ed (Factor y T es ting Register)

0xE0-0xEE Port 4 Cont rol Registers

0xEF Reserved (Factory Testing Register)

0xF0-0xFE Port 4 Control Registers

0xFF Reserved (Factory Testing Register)

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Global Registers

Address Name Description Mode Default

7-0 Family ID Chip family. RO 0x87

7-4 Chip ID 0x6 = 8794 RO 0x6

3-1 Revision ID RO 0x0

0 Start Switch 1 = Start the switc h function of the c hi p

0 = Stop the switch function of t he chip

R/W

7 New back off enable New Back-off algorithm design ed for UNH

1 = Enable

0 = Disable R/W 0

6 Global soft reset enable

Global Software Reset

1 = Enable to reset all FSM and data path (not

configuration)

0 = Disable reset

Note: This reset will stop to receive packets if it is being in the

traffic. All registers keep their configuration values.

RO 0

5 Flush dynamic MAC table

Flush the entire dynamic MAC tabl e for RSTP. This bit is

self-clear (SC).

1 = Trigger the f l us h dynamic MA C table operation.

0 = Normal operat i on

Note: All the entries associated with a Port that has its learning

capability being turned off (Learning Disable) will be flushed. If

you want to flush the entire Table, all Ports learning capability

must be turned off.

R/W

(SC) 0

4 Flush static MAC table

Flush the matched entries in static MAC table for RSTP

1 = Trigger the f l us h static MAC table operation.

0 = Normal operat i on

Note: The matched entry is defined as the entry whose

Forwarding Ports field contains a single Port and MAC address

with unicast. This Port, in turn, has its learning capability being

turned off (Learning Disable). Per Port, multiple entries can be

qualified as matched entries.

R/W

(SC) 0

3 Reserved N/A Don’t change. RO 1

2 Reserved N/A Don’t change. RO 1

1 UNH Mode

1 = The switch will drop packet s with 0x8808 in the T/L

filed, or DA = 01-80-C2-00-00-01.

0 = The switch will drop packet s qualified as “flow

control” packets.

R/W 0

0 Link Change A ge

1 = Link change from “link” to “no link” will cause fast

aging (<800µs) to age addres s table faster. A fter an age

cycle is compl ete, the age logic will return to normal (300

±75 seconds).

Note: If any port is unplugged, all addresses will be

automatically aged out.

R/W 0

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Global Registers (Continued)

Address Name Description Mode Default

7 Reserved N/A Don’t change. RO 0

6 2K Byte packet support 1 = E nable 2K Byte packet support.

0 = Disable 2K Byte packet support. R/W 0

5 IEEE 802.3x Transmit

Flow Control Disable

0 = Enables trans m i t flow control based on AN

result.

1 = Will not enable transmit f low control regar dless of

the AN result.

R/W 0

4 IEEE 802.3x R eceive

Flow Control Disable

0 = Enables receive flow control based on AN result.

1 = Will not enable receive flow control regardless of

the AN result.

Note: Bit [5] and bit [4] default values are controlled by the

same pin, but they can be programmed independently.

R/W 0

3 Frame Length F i eld

Check

1 = Check frame len gth field in the IEEE packets.

If the actual length does not match, the packet will

be dropped (for L/T <1500) . R/W 0

2 Aging Enable 1 = Enable Aging f unction in the chip.

0 = Disable Aging function. R/W 1

1 Fast age Enable 1 = Turn on Fast Aging (800µs). R/W 0

0 Aggressive Back Off

Enable

1 = Enable more aggressive back-off algorithm in half

duplex mode to enhanc e performance. This is not

in the IEEE standard. R/W 0

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Global Registers (Continued)

Address Name Description Mode Default

7 Unicast Port-VLAN

Mismatch Discard

This featur e i s used for port V LA N ( described in Port

Control 1 Register).

1 = All packets c annot cross VLAN boundary.

0 = Unicast pac kets (excluding unknown/

multicast/broadcast) can cross VLAN boundary.

Note: When mirroring is enabled, the single-destination

packets will be dropped if it’s mirrored to another port.

R/W 1

6 Multicast Storm

Protection Di s able

1 = “Broadcast S torm Protection” does not include

multicast packets . Only DA = FFFFFFFFFFFF

packets will be regul ated.

0 = “Broadcast Storm Protection” includes

DA = FFFFFFFFFFFF and DA[40] = 1 packet.

R/W 1

5 Back Pressure Mode 1 = Carrier sense bas ed backpressure is selected.

0 = Collision based backpressure is select ed. R/W 1

4 Flow Control and Back

Pressure fair Mode

1 = Fair mode is selected. In this mode, if a flow control

port and a non-flo w control port talk t o the same

destination port, then packets from the non-flow

control port ma y be dropped. This i s to prevent the

flow control port from being flow controlled for an

extended period of time.

0 = In this mode, if a flow control port and a non-flow

control port talk to the same destination port, the

flow control port will be flow contr olled. This may

not be “fair” to the f l ow control port.

R/W 1

3 No Excessive Collision

Drop

1 = The switch will not drop packets when 16 or more

collisions occur.

0 = The switch will drop pac k ets when 16 or mor e

collisions occur.

R/W 0

2 Reserved N/A Don’t change. RO 0

1 Legal Maximum Packet

Size Check Disable

1 = Enables acceptance of packet sizes up to 1536

bytes (inclusive).

0 = 1522 bytes f or tagged packets (not including

packets with STPID from CPU to Ports 1-4), 1518

bytes for untagged pac k ets. Any packets larger

than the specified value will be dropped.

R/W 0

0 Reserved N/A RO 0

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Global Registers (Continued)

Address Name Description Mode Default

7 802.1q VLAN Enable 1 = 802.1q VLAN mode i s turned on. VLA N table needs

to be set up before the operation.

0 = 802.1q VLAN is disabled. R/W 0

6 IGMP Snoop Enable on

Switch Port 4 SW4-

RGMII/MII/RMII Interface

1 = IGMP Snoop enabled. All the IGMP packets will be

forwarded to the Switch Port 4 RGMII/MII/RMII I/F.

0 = IGMP Snoop disabled. R/W 0

5-1 Reserved N/A Don’t c hange. RO 00000

0 Sniff Mode Select

1 = Enables Rx AN D Tx sniff (both source port and

destination port need to match).

0 = Enables Rx OR Tx sniff (Either source port or

destination port need to match).

Note:

Default is used to implement Rx only sniff.

R/W 0

7 Switch SW4-MII/RMII

Back Pressure Enable

1 = Enable half-duplex back pres sure on the switch

MII/RMII interface.

0 = Disable bac k pressure on the switch MII inter fa ce . R/W 0

6 Switch SW4-MII/RMII

Half-Duplex Mode 1 = Enable MII/RMII interface half-duplex mo de.

0 = Enable MII/RMII interface f ull -duplex mode. R/W 0

5 Switch SW4-MII/RMII

Flow Control Enable

1 = Enable full-duplex flow control on the switch

MII/RMII interface.

0 = Disable full-duplex flow control on the switch

MII/RMII interface.

R/W 0

4 Switch SW4-MII/RMII

Speed 1 = The switch SW4-MII/RMII is in 10Mbps mode.

0 = The switch SW4-MII/RMII is in 100Mbps mode. R/W 0

3 Null VID Replacement 1 = Replace null VID with Port VI D (12 bits).

0 = No replace m ent for null VID. R/W 0

2-0 Broadcast Storm

Protection Rate Bit[10:8]

This register, along with the next register, determines

how many “64 byte blocks” of pac ket data are allowed

on an input Port in a preset period. The period is 50ms

for 100BT or 500ms for 10BT. The default is 1%.

R/W 000

7-0 Broadcast Storm

Protection Rate Bits [7:0]

This register, along with the previous regis ter,

determines ho w many “64-byte block s” of packet dat a

are allowed on an i nput Port in a preset period. The

period is 50ms for 100BT or 500ms for 10BT. T he

default is 1%.

R/W 0x4A(3)

Note:

3. 148,800 frames/sec × 50ms/interval × 1% = 74 frames/interval (approx.) = 0x4A.

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Global Registers (Continued)

Address Name Description Mode Default

7 Flush Counter

1 = All the MIB counter of enabled P ort(s) will be reset

to 0. This bit is self-cleared after the operation

finishes.

0 = No reset of the M IB counter.

R/W

(SC) 0

6 Freeze Counter 1 = Enabled Port(s) will stop counting.

0 = Enabled Port(s) will not stop counted. R/W 0

5 Reserved N/A Don’t cha nge. RO 0

4 - 0 Control Enable

1 = Enable flush and f reeze for each P ort.

Bit [4] is for Port 4 Flush + Freeze.

Bit [3] is reserved.

Bit [2] is for Port 3 Flush + Freeze.

Bit [1] is for Port 2 Flush + Freeze.

Bit [0] is for Port 1 Flush + Freeze.

0 = Disable flu sh and freeze.

R/W 0

7-0 Fact ory Testing N/A Don’t change. RO 0x40

7-0 Fact ory Testing N/A Don’t change. RO 0x00

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Global Registers (Continued)

Address Name Description Mode Default

7 Reversed N/A Don’t change. RO 0

6 Port 4 SW4- RMII

Reference Cl ock Edge

Select

Select the dat a sampling edge of the SW4- RMII

reference cloc k:

1 = Data sampling on the negative edge of REFCLK.

0 = Data sampling on the positi v e edge of REFCLK

(default).

R/W 0

5-4 LED Mod e

Programmable LED output to indicate Port’s activity/status

using 2 bits of the control register. LED is ON (active)

when the output is LOW; the LED is OFF (inac tive) when

the output is HIGH.

Control

Bits [5:4] 00 01 10 11

LEDx_1 Speed ACT Duplex Duplex

LEDx_0 Link/ACT Link Link/ACT Link

LINK = LED ON; ACT = LE D Blink;

LINK/ACT = LED On/Blink.

Speed = LED ON (100BT); LED OFF (10BT); LED Blink

(1000BT reserved).

Duplex = LED ON (Full duplex); LE D OFF (Half duplex).

R/W 00

3 Reserved N/A Don’t change. RO 0

2 Reserved N/A Don’t change. RO 0

1 REFCLKO Enable

1 = Enable REFCLK O pin clock output

0 = Disable RE FCLKO pin clock output.

Strap-in option: LED2_0

PU = REFCLK_O (25MHz) is enabled. (Default)

PD = REFCLK_O is disabled

Note: This is an additional clock. This clock can save an

oscillator if system need this clock source. If the system doesn’t

need this 25MHz clock source that should be disabled.

R/W 0

0 SPI Read Sampling

Clock Edge Select

Select the SPI clock edge for sampl ing SPI read data.

1 = Trigger on the rising ed ge of SPI clock (for higher

speed SPI)

0 = Trigger on the falling edge of SPI clock .

R/W 0

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Global Registers (Continued)

Address Name Description Mode Default

7-6 Reserved Reserved RO 0

5-2 Reserved N/A Don’t change. RO 0001

1 Tail Tag Enable Tail Tag featur e i s applied for Port 4 only.

1 = Insert 1 Byte of data right befor e FCS.

0 = Do not insert. R/W 0

0 Pass Flow Control Packet 1 = Switch will not filter 802.1x “fl ow control” packet s.

0 = Switch will filter 802.1x “flow control” packets. R/W 0

7 – 0 Factory Tes ting N/A Don’t change. RO 00000000

7-6 Reserved N/A Don’t change. RO 00

5 PLL Power Down

Pll Power Down Enable:

1 = Enable

0 = Disable

Note: It occurs in the Energy Detect mode (EDPD mode)

R/W 0

4 – 3 Power Management

Mode Select

Power Management Mode :

00 = Normal mode ( D0)

01 = Energy Detection mode (D2)

10 = Soft Power Do wn mode (D3)

11 = Reserved

R/W 00

2-0 Reserved N/A Don’t change. RO 000

7 – 0 Go_Sleep_Time [7:0]

When the Energy Detect mode is on, this value is

used to control the minimum per iod that the no energy

event has to be det ec ted consecut ively before t he

device enters the low power state. The unit is 20ms.

The default of go_sleep time i s 1.6 seconds (80Dec x

20ms).

R/W 01010000

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Port Registers

The following registers are used to enable features that are assigned on a per port basis . The register bit assignments are

the same for all Ports, but the address for each Port is different, as indicated.

Address

Name

Description

Mode

Default

7 Broadcast Storm

Protection En able

1 = Enable broadc ast storm pr otection for ingr es s

packets on the Port.

0 = Disable bro adc ast storm pr otection. R/W 0

6 DiffServ Priority

Classificat i on Enable

1 = Enable Diff S erv priority cl as sification for i ngress

packets on Port.

0 = Disable DiffServ function. R/W 0

5 802.1p P riority

Classificat i on Enable

1 = Enable 802. 1p pr i ority classification for i ngress

packets on Port.

0 = Disable 802.1p priority classification for ingress

packets on Port.

R/W 0

4 – 3 Port-Based Priority

Classificat i on Enable

00 = Ingress packets on Port will be classified as

priority 0 queue if “Diffserv ” or “802.1p” classificatio n is

not enabled or fails to classify.

01 = Ingress packets on Port will be classified as priority

1 queue if “Diff s erv” or “802.1p” classificati on is not

enabled or fails to classify.

10 = Ingress packet s on Port will be classified as priority

2 queue if “Diff s erv” or “802.1p” classificati on is not

enabled or fails to classify.

11 = Ingress packets on Port will be classified as priority

3 queue if “Diff s erv” or “802.1p” classificati on is not

enabled or fails to classify.

Note: “DiffServ”, “802.1p” and Port priority can be enabled at

the same time. The OR’ed result of 802.1p and DSCP

overwrites the Port priority.

R/W 00

2 Tag insertion

1 = When packet s are output on the Por t, the switch

will add 802.1q tags t o packets without 802.1q tags

when received. T he switch will not add tags to

packets already tagged. The tag ins er ted is the

ingress Port’s “Port VID.”

0 = Disable tag insertion.

R/W 0

1 Tag Removal

1 = When packet s are output on the Por t, the switch

will remove 802.1q tags from packets with 802.1q

tags when received. The switch will not modify

packets received without tags.

0 = Disable tag removal.

R/W 0

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Port Registers (Co ntinued)

Address Name Description Mode Default

0 Two Queues Split Enable

This bit [ 0] in Registers16/32/48/64/80 should be in

combination with Registers177/193/209/2 25/241 bit [1]

for Port 1-5. This will select the split of 1, 2 and 4

queues:

For Port 1, Register 177 bit [1], Regi s ter 16 bit [0]:

11 = Reserved

10 = The Port output queu e is split into four priority

queues or if map 802.1p to priority 0-3 mode.

01 = The Port output queue is split int o two priority

queues or if map 802.1p to priority 0-3 mode.

00 = Single output que ue on the Port. There is no

priority different i ation even thou gh packets are

classified into high or low priority.

R/W 0

Address Name Description Mode Default

7 Sniffer Port 1 = Port is desi gnated as Sniff er port and will t ransmit

packets that are monitored.

0 = Port is a normal port. R/W 0

6 Receive Sniff

1 = All the pack ets received on the port will be m arked

as “monitored packets” and forwarded to the

designated “Snif fer port.”

0 = No receive moni toring.

R/W 0

5 Transmit Sniff

1 = All the pack ets transmitted on the port will be

marked as “monitor ed packets” and forwarded to

the designated “Sniffer port.”

0 = No transmit monitoring.

R/W 0

4-0 Port VLAN Membership

Defines the port’s Port VLAN membership.

Bit [4] stands for Port 4,

Bit [3] Reserved,

Bit [2] stands for Port 3,

Bit [1] stands for Por t 2,

Bit [0] stands for Port 1.

The Port can only communicate within the member ship.

A ‘1’ includes a port in the mem bership, a ‘0’ exc l udes a

port in the membership.

R/W 0x1f

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Port Registers (Co ntinued)

Address

Name

Description

Mode

Default

7 User Priority Ceili ng

1 = If packet ‘s “user priorit y fi el d” is greater than the

“user priority field” in the port default tag register,

replace the packet’s “user priority field” with the

“user priority field” in the port default tag Register

Control 3.

0 = No replace packet’s priority filed with Port def aul t

tag priority filed of the Port Control 3 Register bits

[7:5].

R/W 0

6 Ingress VLAN Filtering.

1 = The switch will discard packets whose VID port

membership in VLAN table bits[11:7] does not

include the ingress port.

0 = No ingress VLA N filtering.

R/W 0

5 Discard Non-PVID

packets

1 = The switch will discard pac k ets whose VID does

not match ingress port default VI D .

0 = No packets will be discarded. R/W 0

4 Force Flow Control

1 = Enables Rx and Tx flow control on t he port,

regardless of the AN result.

0 = Flow control is enabled based on the AN result

(Default)

R/W 0

3 Back Pressure Enable 1 = Enable port hal f-duplex back pressure.

0 = Disable por t half-duplex bac k pressure. R/W 0

2 Transmit Enable 1 = Enable packet transmiss i on on the port.

0 = Disable pac k et transmissi on on the port. R/W 1

1 Receive Enable 1 = Enable pack et reception on the port.

0 = Disable pac k et reception on the port. R/W 1

0 Learning Dis able 1 = Disable switch address learning capability.

0 = Enable switc h address lear ni ng. R/W 0

Note: Bits [2:0] are used for spanning tree support. See “Spanning Tree Support” section.

Address

Name

Description

Mode

Default

7-0 Default Tag [15:8]

Port’s defaul t tag, containing:

7-5: User priority bits

4: CFI bit

3-0: VID[11:8]

R/W 0

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Port Registers (Co ntinued)

Address

Name

Description

Mode

Default

7-0 Default Tag [7:0] Defaul t Port 1’s tag, containing:

7-0: VID[7:0] R/W 1

Note:

Registers 19 and 20 (and those corresponding to other Ports) serve two purposes: (1) Associated with the ingress untagged packets, and used for

egress tagging; (2) Default VID for the ingress untagged or null-VID-tagged packets, and used for address look up.

Address Name Description Mode Default

7-3 Reserved N/A Don’t change. RO 00000

2 ACL Ena ble 1 = Enable AC L

0 = Disable ACL R/W 0

1-0 AUTHENTICATION_MODE

These bits control port-based aut he ntic ati on:

00, 10 = Authentication disable, all traffic is all owed

(forced-authorized), if ACL is enabled, pass all

traffic if ACL missed

01 = Authentic ation enabled, all traffic is blo cked, if

ACL is enabled, traffic is blocked if A CL missed

11 = Authenticat i on enabled, all t raffic is trapped to

CPU Port, if ACL is enabled, traffic is trapped to

port 5 CPU Port only if ACL missed.

R/W 00

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Port Registers (Co ntinued)

Address

Name

Description

Mode

Default

7 RMII_CLK_SEL

Port 4 SW4-RMII Mode Select

1 = RMII uses inter nal clock (clock mode)

0 = RMII uses external clock ( normal mode)

Strap-in option for Port 4: LED2_1

PU = SW4-RMII is in the cl oc k mode (Default)

PD = SW4-RMII is in the nor m al m ode.

Note: This pin has an internal pull-up

R/W 1

6 Is_1Gbps

1 = 1Gbps is chosen f or Port 4 in RGMII mode.

0 = 10/100Mbps is chosen for Port 4 in RGMII mode.

Strap-in option: LED1_0

PU = 1Gbps in SW4- RGMII mode (Default)

PD = 10/100Mbps in SW4-RGMII mode

Note: This pin has an internal pull-up.

Use bit [4] of the Register 6, Global Control 4 to set for 10 or

100 speed in 10/100Mbps mode.

R/W 1

5 Reserved N/A Don’t change. RO 1

4 RGMII Internal Delay (ID)

Ingress Enable

Enable Ingres s RGMII-ID Mode

1 = Ingress RGMII-ID enabled. Min. 1.5ns

delay is added to ingress clock input

0 = No delay is adde d, only clock to dat a

skew applied.

Note: The egress delay of the connection partner should be

set to opposite value to match this ingress delay or no delay

R/W 0

3 RGMII Internal Delay (ID)

Egress Enable

Enable Egress R GMII-ID Mode

1 = Egress RGMII-ID enabled. Min. 1.5

ns delay is added to egress clock

output

0 = No delay is adde d, only clock to dat a

skew applied.

Note: The ingress delay of the connection partner should be

set to opposite value to match this egress delay or no delay.

R/W 1

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Port Registers (Co ntinued)

Address Name Description Mode Default

2 MII Mode Select

Port 4 SW4-MII Mode Select

1 = MII is in MAC mode. (Default)

0 = MII is in PHY mode.

Strap-in option: LED2_1

PU = MII is in MAC mode. (Default)

PD = MII is in PHY mode.

Note: When set SW4-MII to PHY mode, the CRS, COL, RXC

and TXC pins will change from the input to output

R/W

1-0 Interface Mode Select

These bits sel ect the interf ac e type and mod e for

Switch Port 4 (SW4).

Port 4 Mode Select:

00 = MII

01 = RMII

10 = Reserved

11 = RGMII.

Strap-in option: LED3[1:0]

00 = MII

01 = RMII

10 = Reserved

11 = RGMII (Default)

Note: These pins have internal pull-ups.

R/W 11

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Port Registers (Continued)

Address Name Description Mode Default

7 - 6 Reserved N/A Don’t Change. RO 0000

5-4 Advertised_Flow_Control

_Capability

These bits indicate that the KS Z8794CNX has

implemented both the optional MAC control sublayer and

the PAUSE fun c tion as specified in IEEE Clause 31 and

Annex 31B for f ul l duplex operat ion independent of rate

and medium.

00 = No pause

01 = Symmetric PAUSE

10 = Asymmetric PAUSE toward link partner toward

link partner

11 = Both Symmetric PAUSE and Asymmetric PAUSE

toward local devices

Bit [5] indicates that asymmetric PAUSE is supported.

The value of bit [4] when bit [5] is set indicates the

direction of the PAUSE frames that are supported for

flow across the link. Asymmetric PAUSE configuration

results in independent enabling of the PAUSE receive

and PAUSE transmit functions as defined by IEE E Annex

31B.

R/W 11

3 Advertised 100BT Ful l -

Duplex Capabi lity

1 = Advertise 100BT full-duplex capability.

0 = Suppress 100BT full-duplex capability f rom

transmission to link partner. R/W 1

2 Advertised 100BT Half-

Duplex Capabi lity

1 = Advertise 100BT half-dup lex capability.

0 = Suppress 100BT half-duplex capability from

transmission to link partner. R/W 1

1 Advertised 10BT Full-

Duplex Capabi lity

1 = Advertise 10BT full-duplex capability.

0 = Suppress 10BT full-duplex c apability from

transmission to link partner. R/W 1

0 Advertised 10BT Half-

Duplex Capabi lity

1 = Advertise 10BT half-dupl ex capability.

0 = Suppress 10BT half-duplex capability f r om

transmission to link partner. R/W 1

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Port Registers (Co ntinued)

Address Name Description Mode Default

7 - 6 Reserved N/A Don’t Change. RO 0000

5-4 Partner_Flow_Control

_Capable

These bits indicate the partn er capability for both the

optional MAC control sub-layer and the PAUS E function

as specified in IEEE Clause 31 and Annex 31B for ful l

duplex operation independent to rate and m edium.

00 = No pause

01 = Symmetric PAUSE

10 = Asymmetric PAUSE toward link partner toward

link partner

11 = Both Symmetric PAUSE and Asymmetric PAUSE

toward local devices

RO 00

3 Partner 100BT Full-

Duplex Capabi lity 1 = Link partner 100BT f ull-duplex capabl e.

0 = Link partner not 100BT full-duplex capabl e. RO 0

2 Partner 100BT Half-

Duplex Capabi lity 1 = Link partner 100BT half-duplex capabl e.

0 = Link partner not 100BT half-duplex capable. RO 0

1 Partner 10BT Full-Duplex

Capability 1 = Link partner 10B T full-duplex c apable.

0 = Link partner not 10BT full-duplex capable. RO 0

0 Partner 10BT Half-Duplex

Capability 1 = Link partner 10B T half-duplex ca pable.

0 = Link partner not 10BT half-duplex capabl e. RO 0

Address Name Description Mode Default

7 Hp_Mdix 1 = HP Auto MDI/MDI-X Mode

0 = Micrel Auto MDI/MDI-X Mode R/W 1

6 Factory Testing N/A Don’t Change. RO 0

5 Polrvs 1 = Polarity is reversed

0 = Polarity is not reversed RO 0

4 Transm it Flow Control

Enable 1 = T ransmit flow contro l feature is active

0 = Transmit flow control featur e is inactive RO 0

3 Receive Fl ow Control

Enable 1 = Recei v e flow control feature is active

0 = Receive flow control featur e is inactive RO 0

2 Operatio n S peed 1 = Link speed is 100Mbps

0 = Link speed is 10Mbps RO 0

1 Operatio n Duplex 1 = Link duplex is full

0 = Link duplex i s hal f RO 0

0 Reserved N/A Don’t Change. RO 0

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Port Registers (Co ntinued)

Address

Name

Description

Mode

Default

CDT 10M Short

Note: CDT m eans Cable

Diagnostic Test

1 = Less than 10 meter s hort RO 0

6 - 5 CDT_Result

00 = Normal condition

01 = Open condition detected in cable

10 = Short condition detecte d in cable

11 = Cable dia gnostic test has failed

RO 00

4 CDT_Enable

1 = Enable cable diagnostic test. After CDT test has

completed, this bit will be self-cleared.

0 = Indicates that the cable diagnostic test (if enabled)

has Indicate c able diagnosti c test.

R/W

(SC) 0

3 Force_Link 1 = Force link pas s

0 = Normal Oper ation R/W 0

2 Pwrsave 1 = Enable power saving

0 = Disable power saving R/W 0

1 Remote Loopback

1 = Perform Rem ote loopback, loopback on Port 1 as

follows:

Port 1 (Reg. 26, bit [1] = ‘1’)

Start : RXP1/R XM1 (Port 1)

Loo pback: PMD/PMA of Port 1’s PHY

End: TXP1/TXM1 (Port 1)

Setting Reg. 42, 58, 74 bit [1] = ‘1’ will perform

remote loopback on Port 2, 3, 4.

0 = Normal Oper ation.

R/W 0

0 CDT_Fault_Count[8]

Bit[8] of CDT Fault Count

Distance to t he fault.

It’s approximately 0.4*CDT_Fault_Count[8:0].

RO 0

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Port Registers (Co ntinued)

Address

Name

Description

Mode

Default

7-0 CDT_Fault_Count[7:0]

Bits[7:0] of CDT Fault Count

Distance to t he fault.

It’s approximately 0.4m*CDT_Fault_Count[8:0]

RO 0

Address Name Description Mode Default

7 Disable Auto-Negotiation

1 = Disable Auto-Negotiation. Speed and duplex are

decided by bits [6:5] of the same regist er .

0 = Auto-Negotiation is on.

Note: The register bit value is the INVERT of t he s trap

value at the pin .

R/W 0

6 Forced Speed

1 = Forced 100BT if Auto-Negotiation (AN) is dis abled

(bit

[7]).

0 = Forced 10BT if Auto-Negotiation (AN) is dis abled (bit

[7]).

R/W 1

5 Forced Duplex

1 = Forced full-duplex if (1) AN is disabled or (2) AN is

enabled but failed.

0 = Forced half-duplex if (1) AN is disabled or (2) AN

is enabled but failed (Default).

R/W 0

4-0 Reserved N/A Don’t Change. RO 0

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Port Registers (Co ntinued)

Address

Name

Description

Mode

Default

7 LED Off

1 = Turn off all P ort’s LEDs (LED x _2, LEDx_1,

LEDx_0 Pins, where “x” is the Port number). These

pins will be driven h i gh if this bit is set to one.

0 = Normal operat i on.

R/W 0

6 Txids 1 = Disable Port’s transmitter.

0 = Normal operat i on. R/W 0

5 Restart AN 1 = Restart Auto-Negotiation.

0 = Normal operat i on. R/W

(SC) 0

4 Reserved N/A Don’t Change RO 0

3 Power Down 1 = Power down.

0 = Normal operat i on. R/W 0

2 Disable Auto MDI/MDI-X 1 = Disable Auto-MDI/MDIX function.

0 = Enable Auto-MDI/MDIX function. R/W 0

1 Forced MDI 1 = If Auto-MDI/MDIX is disabled, force P HY into

MDI mode.

0 = MDI-X mode. R/W 0

0 MAC Loopback

1 = Perform MAC loopback. Loop back pat h is as

follows:

E.g. set Port 1 MAC Loopback (Reg. 29, bit [0] =

‘1’), use Port 2 as monitor Port. The packets will

transfer.

Start: Port 2 receiving (also can st art to receive

packets from Port 3, 4, 5).

Loop-back: Port 1’s MAC.

End: Port 2 transmitting (also can e nd at Port 3, 4,

5 respectively).

Setting Reg. 45, 61, 93, bit [0] = ‘1’ will perform

MAC loopback on Port 2, 3, 4, 5 respectively.

0 = Normal Oper ation.

R/W 0

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Port Registers (Co ntinued)

Address

Name Description

Mode

Default

7 MDIX Status 1 = MDI.

0 = MDI-X. RO 0

6 Auto-Negotiation Done 1 = Auto-Negotiation done.

0 = Auto-Negotiation not done. RO 0

5 Link Good 1 = Link good.

0 = Link not good. RO 0

4-0 Reserved N/ A Don’t Change. RO 00000

Address Name Description Mode Default

7 PHY Loopback

1 = Perform PHY loopback. Loop back path is as

follows: Example,

Set Port 1 PHY Loopback (Reg. 31, bit [7] = ‘1’)

Use the Port 2 as monitor P ort. The packets will

transfer.

Start: Port 2 receiving (also can start from Port 3, 4,

5).

Loopback: PMD/PMA of Port 1’s PHY

End: Port 2 transmit ting (also can end at Port 3, 4,

5 respectively).

Setting Reg. 47, 63, 95, bit [7] = ‘1’ will perform

PHY loopback on Port 2, 3, 4, 5 respectively.

0 = Normal Oper ation.

R/W 0

6 Reserved N/A Don’t Change RO 0

5 PHY Isolate 1 = Electric al i solation of PHY from MII/RMII and

TX+/TX-.

0 = Normal operation. R/W 0

4 Soft Reset 1 = PHY soft reset. This bit is self-clearing.

0 = Normal operation. R/W

(SC) 0

3 Force Link 1 = Force link i n the PHY.

0 = Normal operation R/W 0

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Port Registers (Co ntinued)

Address Name Description Mode Default

2-0 Port Operation Mode

Indication

Indicate the c urrent state of Port operation mode:

000 = Reserved

001 = Still in Auto-Negotiation

010 = 10BASE-T half duplex

011 = 100BASE-TX half duplex

100 = Reserved

101 = 10BASE-T full duplex

110 = 100BASE-TX full duplex

111 = Reserved

RO 001

Note: Port Control 7-11 and Port Status 1-3 contents can be accessed by MDC/MDIO interface via the standard MIIM registers.

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Advance d Control Registers

Registers 104 to 109 define t he switching engin e’ s MAC address. This 48-bit address is used as the source address i n MAC pause

control frames.

Address Name Description Mode Default

7-0 MACA[47:40] R/W 0x00

7-0 MACA[39:32] R/W 0x10

7-0 MACA[31:24] R/W 0xA1

7-0 MACA[23:16] R/W 0xff

7-0 MACA[15:8] R/W 0xff

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Advance d Control Registers (Continued)

Use Registers 110 and 111 to read or write data to the static MAC address table, VLAN table, dynamic address table,

PME registers, ACL tables, EEE registers and the MIB counters.

Address Name Description Mode Default

7-5 EEE/ACL/PME Indirect

000 = Indirect mode is used for table se lect in bits [3:2]

While these bits are no t equal 000, bits [3:2] are

used for 2 additional MSB address bits.

001 = Global a nd Port base EEE registers are selected,

Port count is specified in 4 MSB i ndirect address

bits and 8 bits register pointer is specified in 8

LSB indirect address bi ts.

010 = Port base ACL registers are s elected, Port count

is specified in 4 MSB indirec t address bit s and

address bits.

011 = Reserved

100 = PME control registers are selected.

101 = LinkMD cable diagnosis us ed. (See example in

LinkMD section).

R/W 000

4 R ead High Write Low 1 = Read cycle.

0 = Write cycle. R/W 0

3-2 Table Select or

Indirect Address [11:10]

If bits [6:5] = 00, then

00 = Static MAC Address Table selected.

01 = VLAN table sel ec ted.

10 = Dynamic Address Table selected.

11 = MIB Counter selected.

If bits [6:5] not equal 00, then These are indirect

address [11:10 ] that is MSB of indirect address, bi ts

[11:8] of the indirect address may be served as Port

address, and b its [7:0] as register address.

Note: The Register 110 bits[3:0] are used for the indirect

address bits [11:8] 4 MSB bits, the 4 bits are used for the port

indirect registers as well.

0000 = Global indi rect registers

0001 = Port 1 indirect registers

0010 = Port 2 indirect registers

0011 = Port 3 indirect registers

0100 = Reserv ed

0101= Port 4 indirect registers

Note: The Register 111 bits[7:0] are used for the indirect

address bits of 8 LSB for indirect register address spacing.

R/W 0

1-0 Indirect Address [9:8] Bits [9:8] of indirect address. R/W 00

7-0 Indirect Addr ess [7:0] Bits [7:0] of indir ect address. R/W 00000000

Note: Write to Register 111 will actually trigger a command. Read or write access will be decided by bit [4] of Register 110.

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Advance d Control Registers (Continued)

The following Indirect Data Registers 112-120 are used for table of static, VLAN, dynamic table, PME, EEE, ACL and MIB

counter.

Address Name Description Mode Default

7-0 Indir ect Data [68:64] Bits [71:64] of indirect data. R/W 00000000

7-0 Indir ect Data [63:56] Bits [63:56] of indirect data. R/W 00000000

7-0 Indir ect Data [55:48] Bits [55:48] of indirect data. R/W 00000000

47-40 Indirect Data [47:40] Bits [47:40] of i ndirect data. R/W 00000000

7-0 Indir ect Data [39:32] Bits [39:32] of indirect data. R/W 00000000

7-0 Indir ect Data [31:24] Bits [31:24] of indirect data R/W 00000000

7-0 Indir ect Data [23:6] Bits [23:16] of indirec t data. R/W 00000000

7-0 Indir ect Data [15:8] Bits [15:8] of indirect data. R/W 00000000

7-0 Indir ect Data [7:0] Bits [7:0] of indirect data. R/W 00000000

The named indirect byte registers is a direct register which is used for PME/ACL/EEE Indirect Register access only. The Indirect Byte

Address

Name

Description

Mode

Default

7-0 Indirect Byte [7:0] Byte data of indirect access. R/W 00000000

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Advance d Control Registers (Continued)

Address Name Description Mode Default

7 – 5 Reserved N/A Don’t Change RO 000

4 PME Interrupt Status

1 = PME interrupt request

0 = Normal

Note: This bit reflects PME control registers, write to

PME Control Register to clear.

This bit is set when PME is asserted. Write a

“1” to clear this bit (WC)

RO 0

3 Reserved N/A Don’t Change RO 0

2 Port 3 Int er rupt Status

1 = Port 3 interrupt request

0 = Normal

Note: This bit is set by a link change on Port 3.

Write a “1” to clear this bit (WC)

R/WC 0

1 Port 2 Int er rupt Status

1 = Port 2 interrupt request

0 = Normal

Note: This bit is set by a link change on Port 2.

Write a “1” to clear this bit (WC)

R/WC 0

0 Port 1 Int er rupt Status

1 = Port 1 interrupt request

0 = Normal

Note: This bit is set by link change on Port 1. Write

a “1” to clear this bit (WC)

R/WC 0

7 – 5 Reserved Don’t Change. RO 000

4 PME Interrupt Mask 1 = Enable PME interrupt.

0 = Normal R/W 0

3 Reserved N/A Don’t Change RO 0

2 Port 3 Int er rupt Mask 1 = Enable Port 3 interrupt.

0 = Normal R/W 0

1 Port 2 Int er rupt Mask 1 = Enable Port 2 interrupt.

0 = Normal R/W 0

0 Port 1 Int er rupt Mask 1 = Enable Port 1 interrupt.

0 = Normal R/W 0

7 – 5 Reserved Don’t Change. RO 000

4-0 ACL_INT_STATUS ACL Interrupt Status, one bit per port

1 = ACL interrupt detected.

0 = No ACL interr upt detected. RO 00000

7 – 5 Reserved Don’t Change. RO 000

4-0 ACL_INT_ENABLE ACL Interrupt Enable, one bit per port

1 = ACL interrupt enabled.

0 = ACL interrupt disabled. R/W 0

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Advance d Control Registers (Continued)

The Registers 128, 129 can be used t o map from 802.1p priority field 0-7 to the switch’s four priority queues 0-3. 0x3 is the highest

priority queues as priority 3 and 0x0 is the lowes t priority queues as priority 0.

Address

Name

Description

Mode

Default

7 – 6 Tag_0x3 I E E E 802.1p mapping. The value in this field is

used as the fram e’ s priority when its IEEE 802.1p

tag has a value of 0x3. R/W 0x1

5 – 4 Tag_0x2 I E E E 802.1p mapping. The value in this field is

used as the fram e’ s priority when its IEEE 802.1p

tag has a value of 0x2. R/W 0x1

3 – 2 Tag_0x1 I E E E 802.1p mapping. The value in this field is

used as the fram e’ s priority when its IEEE 802.1p

tag has a value of 0x1. R/W 0x0

1 – 0 Tag_0x0 I E E E 802.1p mapping. The value in this field is

used as the fram e’ s priority when its IEEE 802.1p

tag has a value of 0x0. R/W 0x0

7 – 6 Tag_0x7 I E E E 802.1p mapping. The value in this field is

used as the fram e’ s priority when its IEEE 802.1p

tag has a value of 0x7. R/W 0x3

5 – 4 Tag_0x6 I E E E 802.1p mapping. The value in this field is

used as the fram e’ s priority when its IEEE 802.1p

tag has a value of 0x6. R/W 0x3

3 – 2 Tag_0x5 I E E E 802.1p mapping. The value in this field is

used as the fram e’ s priority when its IEEE 802.1p

tag has a value of 0x5. R/W 0x2

1 – 0 Tag_0x4 I E E E 802.1p mapping. The value in this field is

used as the fram e’ s priority when its IEEE 802.1p

tag has a value of 0x4. R/W 0x2

7 – 6 Pri_2Q[1:0]

When the 2 Queues configura tion is selected, these

Pri_2Q[1:0] bits are used to map the 2-bit result of

IEEE 802.1p from Register 128/129 or

TOS/DiffServ from Register 144-159 map ping (for 4

Queues) into t wo queues low/high priorities.

2-bit result of IE E E 802.1p or TOS/ DiffServ

00 (0) = Map to Low priority queue

01 (1) = Prio_2Q[0] map to Low/High priority queue

10 (2) = Prio_2Q[1] map to Low/High priority queue

11 (3) = Map to High priority queue

Pri_2Q[1:0] :

00 = Result 0,1, 2 are low priority. 3 is high priority.

01 = Not supported and should be av oided

10 = Result 0,1 are l ow priority. 2, 3 are high

priority (default).

11 = Result 0 is low priority. 1, 2, 3 are high priority.

R/W 10

5-0 Reserved N/A Don’t Change RO 001000

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Advance d Control Registers (Continued)

Address Name Description Mode Default

7-6 Reserved N/A Don’t Change RO 10

5 Unknown Unicast Packet

Forward

1 = Enable supporting unknown unicast packet

forward

0 = Disable R/W 0

4 – 0 Unknown Unicast Packet

Forward Port Pap

00000 = Filter unknown unicast packet

00001 = For wa r d unk nown unicast packet to Port 1

00011 = For wa r d unk nown unicast packet to Port 1,

Port 2

00111 = Forward unk nown unicast pac ket to Port 1,

Port 2 and Port 3

11111 = Broadcast unknown unicast packet to all

Ports

Note: Bit 3 is reserved

R/W 00000

7-6 Reserved N/A Don’t Change RO 01

5 Unknown Multicast Packet

Forward (not including IP

multicast packet)

1 = Enable supporting unknown multicast packet

forward

0 = Disable R/W 0

4 – 0 Unknown Multicast Packet

Forward Port Map

00000 = Filter unknown multicast packet

00001 = Forward unknown multicast packet to

Port 1

00011 = Forward unknown multicast packet to

Port 1, Port 2

00111 = Forward unk nown multicast packet to

Port 1, Port 2 and Port 3

11111 = Broadcast unknown multicast packet to all

Ports

Note: Bit 3 is reserved

R/W 00000

7 – 6 Reserved N/A Don’t Change RO 00

5 Unknown VID Packet Forward 1 = Enable supporting unknown VID pac ket forward

0 = Disable R/W 0

4 – 0 Unknown VID Packet Forward

Port Map

00000 = Filter unknown VID packet

00001 = Forward unknown VID pac ket to Port 1

00011 = Forward unknown VID pac ket to Port 1,

Port 2

00111 = Forward unknown VID packet to Port 1,

Port 2 and Port 3

11111 = Broadcast unknown VID packet to all

Ports

Note:

Bit 3 is reserved

R/W 00000

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Advanced Control Registers (Continued)

Address Name Description Mode Default

7 Reserved N/A Don’t Change RO 0

6 Self-Addr es s Filter Enable

1 = Enable filte r i ng of self-address unicast and

multicast packet

0 = Do not filter self-address p acket

Note: The self-address filtering will filter packets on

the egress port , self MAC address is

assigned in the Register 104-109.

R/W 0

5 Unknown IP Multicast Packet

Forward

1 = Enable supporting unknown IP multicast packet

forward

0 = Disable supporting unknown IP multicast packet

forward

R/W 0

4 – 0 Unknown IP Multicast Packet

Forward Port Map

00000 = Filter unknown IP multicas t packet

00001 = For wa r d unk nown IP multi c ast packet to

Port 1

00011 = For wa r d unk nown IP multi c ast packet to

Port 1, Port 2

00111 = Forward unkn own IP multicast packet to

Port 1, Port 2 and Port 3

11111 = Broadcast unknown I P multicast pack et to

all Ports

Note: Bit 3 is reserved

R/W 00000

7-6 Reserved N/A Don’t Change RO 00

5 – 4 Ingress Rate Li mit Period

The unit perio d for calculating Ingress Rate Limit

00 = 16ms

01 = 64ms

1x = 256ms

R/W 01

3 Queue-based Egress Rate

Limit Enabled

Enable Queue-based Egress Rate Limit

0 = Port-base Egress Rate Limit (default)

1 = Queue-based Egres s Rate Limit R/W 0

2 Insertion Source Port PVID

Tag Selection Enable

1 = Enable source Port PVID tag insertion or non-

insertion option on the egress Port for each

source Port PVID based on the Ports control 8

Registers.

0 = Disable, all packets from any ingress Port will

be inserted PVID based on Port Control 0

R/W 0

1 – 0 Reserved N/A Don’t Change RO 00

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Advance d Control Registers (Continued)

Address Name Description Mode Default

The Ipv4/Ipv6 TOS priority control registers implement a fully decoded 64-bit differentiated services code point ( DSCP) register used to

determine priority from the 6-bit TOS field in the IP header. The most signifi c ant 6 bits of the TOS field are fully decoded into 64

possibilit ies, and the singular code that results is mappe d to the value in the corresponding bit in the DSCP register.

7 – 6 DSCP[7:6]

Ipv4 and Ipv6 mapping

The value in thi s field is used as t he frame’s priority

when bits [7:2] of the frame’s IP OS/DiffServ/Traffic

Class value is 0x03.

R/W 00

5 – 4 DSCP[5:4]

Ipv4 and Ipv6 mapping

The value in thi s field is used as t he frame’s priority

when bits [7:2] of the frame’s IP OS/DiffServ/Traffic

Class value is 0x02.

R/W 00

3 – 2 DSCP[3:2]

Ipv4 and Ipv6 mapping

The value in thi s field is used as t he frame’s priority

when bits [7:2] of the frame’s IP OS/DiffServ/Traffic

Class value is 0x01.

R/W 00

1 – 0 DSCP[1:0]

Ipv4 and Ipv6 mapping

The value in thi s field is used as t he frame’s priority

when bits [7:2] of the frame’s IP OS/DiffServ/Traffic

Class value is 0x00.

R/W 00

7 – 6 DSCP[15:14]

Ipv4 and Ipv6 mapping

_ for value 0x07 R/W 00

5 – 4 DSCP[13:12] Ipv4 and Ipv6 mapping _ for value 0x06 R/W 00

3 – 2 DSCP[11:10]

Ipv4 and Ipv6 mapping

_ for value 0x05 R/W 00

1 – 0 DSCP[9:8] Ipv4 and Ipv6 mapping _ for value 0x04 R/W 00

7 – 6 DSCP[23:22]

Ipv4 and Ipv6 mapping

_ for value 0x0B R/W 00

5 – 4 DSCP[21:20] Ipv4 and Ipv6 mapping _ for value 0x0A R/W 00

3 – 2 DSCP[19:18] Ipv4 and Ipv6 mapping _ for value 0x09 R/W 00

1 – 0 DSCP[17:16]

Ipv4 and Ipv6 mapping

_ for value 0x08 R/W 00

7 – 6 DSCP[31:30]

Ipv4 and Ipv6 mapping

_ for value 0x0F R/W 00

5 – 4 DSCP[29:28] Ipv4 and Ipv6 mapping _ for value 0x0E R/W 00

3 – 2 DSCP[27:26] Ipv4 and Ipv6 mapping _ for value 0x0D R/W 00

1 – 0 DSCP[25:24]

Ipv4 and Ipv6 mapping

_ for value 0x0C R/W 00

7 – 6 DSCP[39:38]

Ipv4 and Ipv6 mapping

_ for value 0x13 R/W 00

5 – 4 DSCP[37:36] Ipv4 and Ipv6 mapping _ for value 0x12 R/W 00

3 – 2 DSCP[35:34] Ipv4 and Ipv6 mapping _ for value 0x11 R/W 00

1 – 0 DSCP[33:32]

Ipv4 and Ipv6 mapping

_ for value 0x10 R/W 00

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Advance d Control Registers (Continued)

Address Name Description Mode Default

7 – 6 DSCP[47:46] Ipv4 and Ipv6 mapping _ for value 0x17 R/W 00

5 – 4 DSCP[45:44] Ipv4 and Ipv6 mapping _ for value 0x16 R/W 00

3 – 2 DSCP[43:42]

Ipv4 and Ipv6 mapping

_ for value 0x15 R/W 00

1 – 0 DSCP[41:40] Ipv4 and Ipv6 mapping _ for value 0x14 R/W 00

7 – 6 DSCP[55:54] Ipv4 and Ipv6 mapping _ for value 0x1B R/W 00

5 – 4 DSCP[53:52] Ipv4 and Ipv6 mapping _ for value 0x1A R/W 00

3 – 2 DSCP[51:50]

Ipv4 and Ipv6 mapping

_ for value 0x19 R/W 00

1 – 0 DSCP[49:48] Ipv4 and Ipv6 mapping _ for value 0x18 R/W 00

7 – 6 DSCP[63:62]

Ipv4 and Ipv6 mapping

_ for value 0x1F R/W 00

5 – 4 DSCP[61:60] Ipv4 and Ipv6 mapping _ for value 0x1E R/W 00

3 – 2 DSCP[59:58] Ipv4 and Ipv6 mapping _ for value 0x1D R/W 00

1 – 0 DSCP[57:56]

Ipv4 and Ipv6 mapping

_ for value 0x1C R/W 00

7 – 6 DSCP[71:70]

Ipv4 and Ipv6 mapping

_ for value 0x23 R/W 00

5 – 4 DSCP[69:68] Ipv4 and Ipv6 mapping _ for value 0x22 R/W 00

3 – 2 DSCP[67:66] Ipv4 and Ipv6 mapping _ for value 0x21 R/W 00

1 – 0 DSCP[65:64]

Ipv4 and Ipv6 mapping

_ for value 0x20 R/W 00

7 – 6 DSCP[79:78]

Ipv4 and Ipv6 mapping

_ for value 0x27 R/W 00

5 – 4 DSCP[77:76] Ipv4 and Ipv6 mapping _ for value 0x26 R/W 00

3 – 2 DSCP[75:74] Ipv4 and Ipv6 mapping _ for value 0x25 R/W 00

1 – 0 DSCP[73:72]

Ipv4 and Ipv6 mapping

_ for value 0x24 R/W 00

7 – 6 DSCP[87:86] Ipv4 and Ipv6 mapping _ for value 0x2B R/W 00

5 – 4 DSCP[85:84]

Ipv4 and Ipv6 mapping

_ for value 0x2A R/W 00

3 – 2 DSCP[83:82] Ipv4 and Ipv6 mapping _ for value 0x29 R/W 00

1 – 0 DSCP[81:80]

Ipv4 and Ipv6 mapping

_ for value 0x28 R/W 00

7 – 6 DSCP[95:94] Ipv4 and Ipv6 mapping _ for value 0x2F R/W 00

5 – 4 DSCP[93:92]

Ipv4 and Ipv6 mapping

_ for value 0x2E R/W 00

3 – 2 DSCP[91:90] Ipv4 and Ipv6 mapping _ for value 0x2D R/W 00

1 – 0 DSCP[89:88] Ipv4 and Ipv6 mapping _ for value 0x2C R/W 00

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Advance d Control Registers (Continued)

Address Name Description Mode Default

7 – 6 DSCP[103:102] Ipv4 and Ipv6 mapping _ for value 0x33 R/W 00

5 – 4 DSCP[101:100] Ipv4 and Ipv6 mapping _ for value 0x32 R/W 00

3 – 2 DSCP[99:98]

Ipv4 and Ipv6 mapping

_ for value 0x31 R/W 00

1 – 0 DSCP[97:96] Ipv4 and Ipv6 mapping _ for value 0x30 R/W 00

7 – 6 DSCP[111:110] Ipv4 and Ipv6 mapping _ for value 0x37 R/W 00

5 – 4 DSCP[109:108] Ipv4 and Ipv6 mapping _ for value 0x36 R/W 00

3 – 2 DSCP[107:106]

Ipv4 and Ipv6 mapping

_ for value 0x35 R/W 00

1 – 0 DSCP[105:104] Ipv4 and Ipv6 mapping _ for value 0x34 R/W 00

7 – 6 DSCP[119:118]

Ipv4 and Ipv6 mapping

_ for value 0x3B R/W 00

5 – 4 DSCP[117:116] Ipv4 and Ipv6 mapping _ for value 0x3A R/W 00

3 – 2 DSCP[115:114] Ipv4 and Ipv6 mapping _ for value 0x39 R/W 00

1 – 0 DSCP[113:112]

Ipv4 and Ipv6 mapping

_ for value 0x38 R/W 00

7 – 6 DSCP[127:126]

Ipv4 and Ipv6 mapping

_ for value 0x3F R/W 00

5 – 4 DSCP[125:124] Ipv4 and Ipv6 mapping _ for value 0x3E R/W 00

3 – 2 DSCP[123:122] Ipv4 and Ipv6 mapping _ for value 0x3D R/W 00

1 – 0 DSCP[121:120]

Ipv4 and Ipv6 mapping

_ for value 0x3C R/W 00

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Advance d Control Registers (Continued)

Address Name Description Mode Default

7 Reserved N/A Don’t Change RO 0

6 – 4 GMII/RGMI

High Speed Drive Strength

High Speed Interfaces Drive Strength for GMII &

RGMI

000 = 2mA

001 = 4mA

010 = 8mA

011 = 12mA

100 = 16mA

101 = 20mA

110 = 24mA (default)

111 = 28mA

R/W 110

3 Reserved N/A Don’t Change RO 0

2 – 0 MII/RMII

Low Speed Drive Strength

High Speed Interfaces Drive Strength for MII & RMII

000 = 2mA

001 = 4mA

010 = 8mA (default)

011 = 12mA

100 = 16mA

101 = 20mA

110 = 24mA

111 = 28mA

R/W 010

7 – 4 Reserved N/A Don’t Change RO 0x2

3 IPv6 MLD Snooping Opt i on

IPv6 MLD Snooping Option

1 = Enable

0 = Disable

R/W 0

2 IPv6 MLD Snooping Enable

IPv6 MLD Snooping Enable

1 = Enable

0 = Disable

R/W 0

1 – 0 Reserved N/A Don’t Change RO 10

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Advance d Control Registers (Continued)

Address Name Description Mode Default

7 Reserved RO 1

6 Pass All Frames

Port based ena ble to pass all fr ames

1 = Enable

0 = Disable

Note: This is used in the port mirroring with RX sniff only.

R/W 0

5 – 4 Reserved Reserved RO 0000

3 Insert Source Port PVID for

Untagged Packet Destination

to Highest Egress Port

untagged frame at egress Port 4

Note: Enabled by the Register 135 bit [2].

R/W 0

Insert Source Port PVID for

Untagged Packet Destination

to Second Highes t Egress

Port

untagged frame at egress Port 3

Note: Enabled by the Register 135 bit [2].

R/W 0

1 Insert Source Port PVID for

Untagged Packet Destination

to Second Lowest Egress Port

untagged frame at egress Port 3

untagged frame at egress Port 2

Note: Enabled by the Register 135 bit [2].

R/W 0

0 Insert Source Port PVID for

Untagged Packet Destination

to Lowest Egress Port

untagged frame at egress Port 2

untagged frame at egress Port 1

Note: Enabled by the Register 135 bit [2].

R/W 0

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Advanced Control Registe rs (Continued)

Address Name Description Mode Default

7 – 2 Reserved RO 0000000

1 4 Queue Split Enable

This bit, in combination with Register16/32/48/64/80

bit [0], will select the split of 1, 2 and 4 queues:

{Register 177 bit [1], Register 16 bit [0] = }:

11 = Reserved.

10 = The port output queue i s split into four priority

queues or if map 802.1p to priority 0-3 mode.

01 = The port output queue is s pl it into two priori ty

queues or if map 802.1p to priority 0-3 mode.

00 = Single out put queue on the port. There is no

priority different i ation even thou gh packets are

classified into high and low priorit y.

R/W 0

0 Enab le D r opping T ag 0 = Disable tagged packets drop

1 = Enable tagged packets drop R/W 0

7 Enable Port Transmit Queu e 3

Ratio

0 = Strict priority. Will transmit al l the packets from

this priority queue 3 before transmit lower

priority queue.

1 = Bits [6:0] reflect the packet number allo w to

transmit from this pr i ority queue 3 within a

certain time.

R/W 1

6 – 0 Port Transmit Queue 3

Ratio[6:0] Packet number for Transmit Queue 3 for highest

priority packets in four que ues mode. R/W 0001000

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Advance d Control Registers (Continued)

Address Name Description Mode Default

7 Enable Port Transmit Queue 2

Ratio

0 = Strict priority. Will transmit all the packets from

this priority queue 2 before transmit lower

priority queue.

1 = Bits [6:0] r eflect the packet num ber allow to

transmit from this pr i ority queue 1 within a

certain time.

R/W 1

6 – 0 Port Transmit Queue 2

Ratio[6:0]

Packet number for Transmit Queue 2 for high/low

priority packets in high/low priority packet s in four

queues mode. R/W 0000100

7 Enable Port Transmit Queue 1

Rate

0 = Strict priority. Will transmit al l the packets from

this priority queue 1 before transmit lower

priority queue.

1 = Bits [6:0] reflect the packet number allow to

transmit from this pr i ority queue 1 within a

certain time.

R/W 1

6 – 0 Port Transmit Queue 1

Ratio[6:0]

Packet number for Transmit Queue 1 for low/high

priority packets in four que ues mode and hig h

priority packets in two queues mode. R/W 0000010

7 Enable Port Transmit Queu e 0

Rate

0 = Strict priority. Will transmit al l the packets from

this priority queue 0 before transmit lower

priority queue.

1 = Bits [6:0] r eflec t the packet number allow to

transmit from this pr i ority queue 0 within a

certain time.

R/W 1

6 – 0 Port Transmit Queue 0

Ratio[6:0]

Packet number for Transmit Queue 0 for lowest

priority packets in four que ues mode and lo w

priority packets in two queues mode. R/W 0000001

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Advance d Control Registers (Continued)

Address Name Description Mode Default

7 Reserved RO 0

6 Ingress Limit Port/Priority

Based Select 1 = Ingress rate limit is Port based

0 = Ingress rat e li mit is priorit y b ased R/W 0

5 Ingress Limit Bit/Packets

Mode Select

1 = Rate limit is counted based on number of

packet.

0 = rate limit is counted based on

number of bit.

R/W 0

4 Ingress Rate Limit Flow

Control Enabl e

1 = Flow Contr ol i s asserted if the Port’s receive

rate is exceeded.

0 = Flow Contr ol i s not asserted if the Port’s receive

rate is exceeded.

R/W 0

3 – 2 Limit Mode

Ingress Limit M ode

These bits det ermine what type of frames are

limited and count ed against ingr es s rate limiting.

00 = Limit and count all frames.

01 = Limit and count Broadcast, Multicast, and

flooded unicast frames .

10 = Limit and count Broadcast and Multicast

frames only.

11 = Limit and count Broadcast frames only.

R/W 00

1 Count IFG

Count IFG Bytes

1 = Each frame’s minimum inter-frame gap.

(IFG) bytes (12 per fr ame) are included in

Ingress and Egress rat e limiting calculations.

0 = IFG bytes are not counted.

R/W 0

0 Count Pre

Count Preamble Bytes

1 = Each frame’s preamble bytes ( 8 per

frame) are included in Ingress and Egress rate

limiting calculations.

0 = Preamble bytes are not counted.

R/W 0

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Advance d Control Registers (Continued)

Address Name Description Mode Default

7 Reserved RO 0

6 – 0 Port Based Priority 0 Ingress

Limit

Ingress Data R ate Limit Fo r Pri ority 0 Frames

Ingress traffic from this Port is shaped according to

the Rate Selection Table in Rate Limit Support

section.

R/W 0000000

7 Reserved RO 0

6 – 0 Port Based Priority 1 Ingress

Limit

Ingress Data R ate Limit Fo r Pri ority 1 Frames

Ingress traffic from this Port is shaped according to

the Rate Selection Table in R ate Limit Support

section.

R/W 0000000

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Advance d Control Registers (Continued)

Address Name Description Mode Default

7 Reserved RO 0

6 – 0 Port Based Priority 2 Ingress

Limit

Ingress Data R ate Limit Fo r Pri ority 2 Frames

Ingress traffic from this Port is shaped according to

the Rate Selection Table in R ate Limit Support

section.

R/W 0000000

7 Port Based Ing ress Rate Limit

Enable

Ingress Data R ate Limit Fo r Pri orities Setti ng

Valid

Trigger port ingress rate limit engine to take effect

for all the priority queues acc ording to priority

ingress limit c ontrol.

Note: Any write to this register will trigger port ingress rate

limit engine to take effect for all the priority queues

according to priority ingress limit control. For the port

priority 0-3 ingress rate limit control to take effect, bit [7] of

in Register 186, 202, 218, 234 and 250 for Ports 1, 2, 3, 4

and 5, respectively will need to set last after configured

bits [6:0] of Port Ingress Limit Control 1-4 registers.

R/W 0

6 – 0 Port Based Priority 3 Ingress

Limit

Ingress Data R ate Limit Fo r Pri ority 3 Frames

Ingress traffic from this Port is shaped according to

the Rate Selection Table in R ate Limit Support

section.

R/W 0000000

Note:

4. In the port priority 0-3 ingress rate limit mode, will need to set all related egress ports to two queues or four queues mode.

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Advance d Control Registers (Continued)

Address Name Description Mode Default

7 7 7 7 7

6 – 0 6 – 0 6 – 0 6 – 0 6 – 0

7 Reserved RO 0

6 – 0 Port Queue 1 Egr es s Limit

Egress Data Rat e Limit For Priority 1 Frames

Egress traffic from this priority queue is s haped

according to the Rate Selection Table in Rate Limit

Support sect i on.

In four queues mode, it is low/high priority.

In two queues m ode, it is high pr i or i ty.

R/W 0000000

7 Reserved RO 0

6 – 0 Port Queue 2 Egr es s Limit

Egress Data Rate Limit Fo r Pri ority 2 Frames

Egress traffic from this priority queue is s haped

according to the Rate Selection Table in Rate Limit

Support sect i on.

In four queues mode, it is high/low priority.

R/W 0000000

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Advanced Control Registers ( Continued)

Address Name Description Mode Default

7 Reserved RO 0

6 – 0 Port Queue 3 Egr es s Limit

Egress Data Rate Limit Fo r Pri ority 3 Frames

Egress traffic from this priority queue is shaped

according to the Rate Selection Table in Rate Limit

Support sect i on.

In four queues mode, it is highest priorit y.

R/W 0000000

7 - 0 Reserved N/A Don’t Change. RO 0x80

7 - 0 Reserved N/A Don’t Cha nge. RO 0x15

7 - 0 Reserved N/A Don’t Change. RO 0x0C

7 - 0 Reserved N/A Don’t Cha nge. RO 0x32

7-0 Reserved N/A Don’t Change. RO 0x00

Note:

5. In the port queue 0-3 egress rate limit mode, the highest priority get exact rate limit based on the rate select table, other priorities packets rate are

based upon the ratio of the Port Control 14/15/16/17 Registers when use more than one egress queue per port.

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Indirect Register Description

Control

Indirect Address

Contents

Direct Addres s 0x6E,

Function Select bits [7-5] = 000

Table_select bits [3-2] = 00 0x000 – 0x01F Static MAC addr ess table entry 0 – 31

Direct Addres s 0x6E,

Function Select bits [7-5] = 000

Table_select bits [3-2] = 01 0x000 – 0x1FF VLAN table bucket 0 – 1023 ( 4 entry per

bucket)

Direct Addres s 0x6E,

Function Select bits [7-5] = 000

Table_select bits [3-2] = 10 0x000 – 0x1FF Dynamic MAC address table enty 0 – 1023

Direct Addres s 0x6E,

Function Select bits [7-5] = 000

Table_select bits [3-2] = 11

0x000 – 0x08F,

0x100 – 0x109

0x000 – 0x01F Port 1 MIB Counters

0x020 – 0x03F Port 2 MIB Counters

0x040 – 0x05F Port 3 MIB Counters

0x060 – 0x07F Reserved

0x080 – 0x09F Port 4 MIB Counters

0x100 – 0x113 Total Byte and Dropped MIB

Counter

Direct Addres s 0x6E,

Function Select bits [7-5] = 001,

bits [3-0] = Indirect Address bits [11-8] =

MSB Indirect Address

= Port indirect register address 0xn

{0xn, 6h00} –

{0xn, 6h05}

Port-based 16-bit EEE Cont rol Registers 0 –

n – Port number

Use Indirect Byte Register (0xA0)

Direct Addres s 0x6E,

Function Select bits [7-5] = 010,

bits [3-0] = Indirect A ddress bits [11-8] =

MSB Indirect Address

= Port indirect register address 0xn

{0xn, 6h00} –

{0xn, 6h1F}

ACL entry 0 – 15, 6h00 and 6h01 for ent ry 0,

etc.

n = Port number

Use Indirect Byte Register(0xA0)

Direct Addres s 0x6E,

Function Select bits [7-5] = 011,

bits [3-0] = Indirect A ddress bits [11-8] =

MSB Indirect Address

= Port indirect register address 0xn

{0xn, 8h00} –

{0xn, 8h4FF } Reserved for t he factory

Direct Addres s 0x6E,

Function Select bits [7-5] = 100,

bits [3-0] = Indirect A ddress bits [11-8] =

MSB Indirect Address

= Port indirect register address 0xn

{0xn, 8h00} –

{0xn, 8h4FF }

Configuration Registers, PME etc.

n = 0 - Global

n = 1 – 3 Port number

Use Indirect Byte Register(0xA0)

Direct Address 0x6E,

Function Select bits [7-5] = 101,

bits [3-0] = Indirect A ddress bits [11-8] =

MSB Indirect Address

= Port indirect register address 0xn

{0xn, 8h00} –

{0xn, 8h4FF } Reserved for t he factory

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Static MAC Address Table

The KSZ8794CNX incorporates a static and a dynamic address table. When a DA look-up is requested, both tables will

be searched to make a packet forwarding decision. When an SA look-up is requested, only the dynamic table is searched

for aging, migration, and learning purpos es. The static DA look-up result will have precedence over the dynamic DA look-

up result. If there are DA matches in both tables, the result from the static table will be used. The static table can only be

accessed and controlled by an external SPI master (usually a processor). The entries in the static table will not be aged

out by KSZ8794CNX. An external device does all addition, modification and deletion.

Note:

below.

Table 16. Static MAC Address Tab le

Address Name Description Mode Default

Format of Static MAC Table fo r Reads (32 entries)

63-57 FID Filter VLAN ID, representing one of the 128 active

VLANs. RO 0000000

56 Use FID 1 = Use (FID+MAC) to l ook-up in static t able.

0 = Use MAC only to look-up in static table. RO 0

55 Reserved Reserved. RO N/A

54 Override

1 = Override spanning tree “transmit enable = 0” or

“receive enable = 0* s etting. This bit is used for

spanning tree implem entation.

0 = No override.

RO 0

53 Valid 1 = This entry is val id, the look-up r esult will be used.

0 = This entry is not valid. RO 0

52-48 Forwarding Ports

These 5 bits cont rol the forward Ports.

For example,

00001 = For ward to Port 1

00010 = For ward to Port 2

00100 = Forward to Port 3

01000 = Reserved

10000 = For ward to Port 4

00110 = For ward to Port 2 and Port 3

11111 = Broadc as ting (excluding the ingress port)

RO 00000

47-0 MAC Address (DA) 48-bit MAC address. RO 0x0

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Table 16. Static MAC Address T able (continued)

Address Name Description Mode Default

Format of Static MAC Table fo r Writes (32 entries)

62-56 FID Filter VLAN ID, representi ng one of the 128 active VLANs. W 0000000

55 Use FID 1 = Use ( FID+MAC) to look-up in static table.

0 = Use MAC only to look-up in static t abl e. W 0

54 Override

1 = Override spanning tree “transmit enable = 0” or

“receive enable = 0” setting. This bi t is used for

spanning tree implem entation.

0 = No override.

W 0

53 Valid 1 = This entry is valid, the look-up result will be use d.

0 = This entry is not valid. W 0

52-48 Forwarding Ports

These 5 bits cont rol the forward ports.

For example,

00001 = For ward to Port 1

00010 = For ward to Port 2

00100 = Forward to Port 3

01000 = Reserved

10000 = For ward to Port 4

00110 = For ward to Port 2 and Port 3

11111 = Broad c asting (exclud ing the ingress port)

W 00000

47-0 MAC Address (DA) 48-bit MAC address. W 0x0

Examples:

(1) Static Addres s Table Read (read the 2 nd entry)

Write to Register 11 0 with 0x10 (read stat ic table selected)

Write to Register 11 1 with 0x1 (trigger the read operation)

Then

Read Register 113 ( 63:56)

Read Register 114 (55: 48)

Read Register 115 (47: 40)

Read Register 116 (39: 32)

Read Register 117 (31: 24)

Read Register 118 (23: 16)

Read Register 119 (15: 8)

Read Register 120 (7: 0)

(2) Static Addres s Table Write (write the 8th entry)

Write Register 113 (62:56)

Write Register 114 (55:48)

Write Register 115 (47:40)

Write Register 116 (39:32)

Write Register 117 (31:24)

Write Register 118 (23:16)

Write Register 119 (15:8)

Write Register 120 (7:0)

Write to Register 11 0 with 0x00 (write st atic table selected)

Write to Register 11 1 with 0x7 (trigger the write operation)

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VLAN Table

The VLAN table is used for VLAN table look-up. If 802.1q VLAN mode is enabled (Register 5 bit [7] = 1), this table is used

to retrieve VLAN information that is associated with the ingress packet. There are three fields for FID (filter ID), Va lid, and

VLAN membership in the VLAN table. The three fields must be initialized before the table is used. There is no VID field

because 4096 VIDs are used as a dedicated memory address index into a 1024x52-bit memory space. Each entry has

four VLANs. Each VLAN has 13 bits. Four VLANs need 52 bits. There are a total of 1024 entries to support a total of

4096 VLAN IDs by using dedicated memory address and data bits. Refer to Table 17 for details. FID has 7 bits to support

128 active VLANs.

Table 17. VLAN Table

Address Name Description Mode Initial Value

suggestion

Format of Static VL AN Table (Support Max 4096 VLAN ID entries and 128 Active VLANs)

12 Valid 1 = The entry is valid.

0 = Entry is inval id. R/W 0

11-7 Membership

Specifies which Ports are members of the VLAN.

If a DA look-up fails (no match in both static and dynamic

tables), the p acket associat ed with this VLA N will be

forwarded to P or ts specified in this field.

E.g., 1x001 means Ports 4 and 1 are in this VLAN, x is bit

10 which is res erved in the KSZ8794CNX.

R/W 11111

6-0 FID

Filter ID. The KSZ8794CNX supports 128 ac tive VLANs

represente d by these seven bit fields. FID is the mapped

ID. If 802.1q V LA N is enabled, the look-up will be based

on FID+DA and FID+SA.

R/W 0

If 802.1q VLAN mode is enabled, the KSZ8794CNX assigns a VID to every ingress packet when the packet is untagged

or tagged with a null VID, the packet is assigned with the default Port VID of the ingress Port. If the packet is tagged with

non-null VID, the VID in the tag is used. The look-up process starts from the VLAN table look-up based on VID number

with its dedicated memory address and data bits. If the entry is not valid in the VLAN table, the packet is dropped and no

address learning occurs. If the entry is valid, the FID is retrieved. The FID+DA and FID+SA lookups in MAC tables are

performed. The FID+DA look-up determines the forwarding Ports. If FID+DA fails for look-up in the MAC ta ble, the packet

is broadcast to all the members or specified members (excluding the ingress Port) based on the VLAN table. If FID+SA

fails, the FID+SA is learned. To communicate between different active VLANs, set the same FID; otherwise set a different

FID.

The VLAN table configuration is organized as 1024 VLAN sets, each VLAN set consists of four VLAN entries, to support

up to 4096 VLAN entries. Each VLAN set has total 60 bits and 3 reversed bits are inserted between entries, actually 52

bits are used for VLAN s et which should be read or written at the same ti m e specified by the indire ct address.

The VLAN entries in the V LAN set are mapped to indirect data registers as follow:

• Entry0[12:0] maps to the VLAN set bits [12:0] {Register 119[4:0], Register 120[7:0]}

• Entry1[12:0] maps to t he VLAN set bits[28:16] {Register 117[4:0], Register 118[7:0]}

• Entry2[12:0] maps to the VLAN set bits[44:32] {Register 115[4:0], Register 116[7:0]}

• Entry3[12:0] maps to t he VLAN set bits[60:48] {Register 113[4:0], Register 114[7:0]}

In order to read one VLAN entry, the VLAN set is read first and the specific VLAN entry information can be extracted. To

update any VLAN entry, the VLAN set is read first then only the desired VLAN entry is updated and the whole VLAN set is

written back. The FID in the VLAN table is 7 bits, so the VLAN table supports unique 128 flow VLAN groups. Each VLAN

set address is 10 bits long (Maximum is 1024) in the Indirect Address Register 110 and 111, the bits [9:8] of VLAN set

address is at bits [1:0] of Register 110, and the bits [7:0] of VL AN set address is at bits [7:0] of Register 111. Each Write

and Read can access up to f our consecutive VLAN entries.

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Examples:

1. VLAN Table Read (read the VID = 2 ent ry )

Write the indirect control and address registers first

Write to Register 11 0 (0x6E) with 0x14 (read VLAN table selected)

Write to Register 11 1 (0x6F) with 0x0 (trigger the read operation for VID = 0, 1, 2, 3 entries)

Then read the Indirect Data Registers bits [38:26] for VID = 2 entry

Read Register 115 (0x73), (Register 115 [4:0] are bits [12:8] of VLAN VID = 2 entry)

Read Register 116 (0x74), (Register 116 [7:0] are bits [7:0] of VLAN VID = 2 entry)

2. VLAN Table Write ( write the VID = 10 entry)

Read the VLAN set that contains VID = 8, 9, 10, 11.

Write to Register 110 (0x6E) with 0x14 (read VLAN table selected)

Write to Register 111 (0x6F) with 0x02 (trigger the read operation and V I D = 8, 9, 10, 11 indirect address)

Read the VLAN set first by the Indirect Data Registers 113, 114, 115, 116, 117, 118, 119, 120.

Modify the Indirect Data Regi st ers bits [44:32] by the Register 115 bit[4-0] and Register 116 bits [7:0] as follows:

Write to Register 115 (0x73), (Register115 [4:0] are bits [12:8} of VLAN VID = 10 entry)

Write to Register 116 (0x74), (Register116 [7:0] are bits [7:0] of VLAN VID = 10 entry)

Then write the indi rect control and address Registers

Write to Register 11 0 (0x6E) with 0x04 (write VLAN table selected)

Write to Register 11 1 (0x6F) with 0x02 (trigger the writ e operat ion and VID = 8, 9, 10, 11 indirect address)

The following t abl e shows the relationship of the indirect address/data registers and VLAN ID.

Table 18. VLAN ID and Indi rect Registers

Indirect Address

high/low bit[9-0] for

VLAN sets

Indirect Dat a

Registers Bits f or

each VLAN entry

VID

Numbers VID bit[12-2] in VLAN

Tag VID bit[1-0] in VLAN

Tag

0 Bits [12:0] 0 0 0

0 Bits [28:16] 1 0 1

0 Bits [44:32] 2 0 2

0 Bits [60:48] 3 0 3

1 Bits [12:0] 4 1 0

1 Bits [28:16] 5 1 1

1 Bits [44:32] 6 1 2

1 Bits [60:48] 7 1 3

2 Bits [12:0] 8 2 0

2 Bits [28:16] 9 2 1

2 Bits [44:32] 10 2 2

2 Bits [60:48] 11 2 3

: : : : :

1023 Bits [12:0] 4092 1023 0

1023 Bits [28:16] 4093 1023 1

1023 Bits [44:32] 4094 1023 2

1023 Bits [60:48] 4095 1023 3

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Dynamic MA C Add ress Table

This table is read only.

Table 19. Dynamic MAC Address T able

Address Name Description Mode Default

Format of Dynamic MAC Add ress Table (1K entries)

71 MAC Empty 1 = There is no vali d entry in the table.

0 = There are valid entries in the table. RO 1

70-61 No of Valid Entries

Indicates how many valid entries in the table.

0x3ff means 1K entries

0x1 and bit [71] = 0: means 2 entries

0x0 and bit [71]= 0: means 1 entry

0x0 and bit [71] = 1: means 0 entry

RO 0

60-59 Time St amp 2-bit counters for intern al aging RO

58-56 Source Port

The source Port where FID+MAC is learned.

000 = Port 1

001 = Port 2

010 = Port 3

011 = Reserved

100 = Port 4

RO 0x0

55 Data Read y 1 = The entry is not ready, retr y unti l this bit is set to 0.

0 = The entry is r eady. RO

54-48 FID Filter ID. RO 0x0

47-0 MAC Address 48-bit MAC address. RO 0x0

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Examples:

(1) Dynamic MAC Addr ess Table Read (read t he 1 st entry), and retrieve the M AC table size

Write to Register 11 0 with 0x18 (read dynam i c t able selected)

Write to Register 11 1 with 0x0 (trigger the read operation) and t hen

Read Register 112 (71:64)

Read Register 113 (63: 56); // the above two re gist ers show # of entries

Read Register 114 (55: 48) // if bit [55] is 1, restart (reread) from t his register

Read Register 115 (47: 40)

Read Register 116 (39: 32)

Read Register 117 (31: 24)

Read Register 118 (23: 16)

Read Register 119 (15: 8)

Read Register 120 (7: 0)

(2) Dynamic MAC Addr ess Table Read (read t he 257 th entry), without r etrieving # of entries information

Write to Register 11 0 with 0x19 (read dynam i c t able selected)

Write to Register 11 1 with 0x1 (trigger the read operation) and t hen

Read Register 112 (71:64)

Read Register 113 (63:56)

Read Register 114 (55: 48) // if bit [55] i s 1, resta rt (reread) from this regist er

Read Register 115 (47: 40)

Read Register 116 (39: 32)

Read Register 117 (31: 24)

Read Register 118 (23: 16)

Read Register 119 (15: 8)

Read Register 120 (7: 0)

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PME Indirect Registers

The EEE registers are provided on global and per port basis. These registers are read/w rite using indirect memory access

as below:

Table 20. PME Indirect Register s

Address Name Description Mode Default

Global PME Control Register

Reg. 110 (0x6E ) bits [7:5]= 100 for PME, Reg.110 b i ts [3:0]=0x0 for the indirect global regist er,

Reg. 111 (0x6F) bits [7:0]= Offset to access the I ndi r ect Byte Register 0xA0.

Offset: 0x00 ( bits [31:24]) , 0x01 (bits [23:16]), 0x02 (bit [15:8]), 0x03 (bits [7:0]).

Location: (100 PME) -> {0x0, offset} ->0xA0 holds the data.

31-2 Reserved RO All ‘0’

1 PME Output Enable 1= PME output pin is enabled.

0= PME output pin i s disabled. R/W 0

0 PME Output Polarity 1= PME output pin is activ e high.

0= PME output pin i s active low. R/W 0

Port PME Control Status Register

Reg. 110 (0x6E ) bits [7:5]= 100 for PME, Reg. 110 bit s [3:0]=0xn for the Indirect Port Register (n=1, 2 and 3).

Reg. 111 (0x6F) bits [7:0]= Offset to access the I ndi r ect Byte Register 0xA0.

Offset: 0x00 ( bits [31:24]) , 0x01 (bits [23:16]), 0x02 (bits [5:8]), 0x03 (bits [7:0]).

Location: (100 PME) -> {0xn, offset} ->0xA0 holds the data.

31-3 Reserved RO All ‘0’

2 Magic Packet D etect 1 = Magic packet is detected at any port (write 1 to

clear).

0 = No magic packet is detected.

R/W

W1C 0

1 Link Up Detect 1 = Link up is detected at any port (write 1 to clear).

0 = No link-up is detected. R/W

W1C 0

0 Energy Detect 1 = Energy is detected at any port (write 1 to clear).

0 = No energy is det ected. R/W

W1C 0

Port PME Control Mask Register

Reg. 110 (0x6E ) bits [7:5]= 100 for PME, Reg. 110 bit s [3:0]=0xn for port (n=1, 2 and 3).

Reg. 111 (0x6F) bits [7:0]= Of fset to access the I ndirect Byte Regis ter 0xA0.

Offset: 0x04 (bits [31:24]), 0x05 (bi ts [23:16]), 0x 06 (bits [15:8] ), 0x07 (bits [7: 0]).

Location: (100 PME) -> {0xn, offset} ->0xA0 holds the data.

31-3 Reserved RO All ‘0’

2 Magic Packet D etect

Enable

1 = The PME pin will be asserted when a magic packet

is detected at host QMU.

0 = The PME pin will not be asserted by the magic

packet detecti on.

R/W 0

1 Link Up Detect Enable

1 = The PME pin will be asserted when a linkup is

detected at any port.

0 = The PME pin will not be asserted by the linkup

detection.

R/W 0

0 Energy Detect Enable

1 = The PME pin will be asserted when energy on line

is detected at any port.

0 = The PME pin will not be asserted by the energy

detection.

R/W 0

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Programming Examples:

Read Operation

1. Use the Indirect Access Control Register to select register to be read, to read Global PME Control Register. Write

0x90 to the Register 110 (0x6E) // PME selected and read operation, and 4 MSBs of Port number (Register 110 bits

[3:0]) = 0 for the Global PME Regist er.

2. Write 0x03 to the Register 111 (0x6F) // trigger t he read operation for bit s [ 7:0] of the Global PME Cont rol Register.

3. Read the Indirect Byte Register 160 (0xA0) // Get the value of the Global PM E Control Regist er.

Write Operation

1. Write 0x80 to the Register 110 (0x6E) //PME selected and write operation, and 4 MSBs of Port number = 0 for the

Global PME Register.

2. Write 0x03 to the Register 111 (0x6F) // select write the bits [ 7:0] of the Global PME Control Address Register.

3. Write new value to the Indirect Byte Register 160 bits [7:0] (0xA0) //Write value to the Global PME Control Register of

the Indirect PME Dat a Register by the assi gned the indirect data register address.

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ACL Rule Table and ACL Indirect Registers

ACL Register and Programming Model

The ACL registers are accessible by the microcontroller through a serial interface. The per-port register set is accessed

through indirect addressing mechanism. The ACL entries are stored in the format shown in the following figur e. Each ACL

rule list table can input up to 16 entries per port , total 4 ACL rule list tables can be set for 4 ports.

Figure 13. ACL Table Access

To update any port-based ACL registers, it is suggested to execute a read modify write sequence for each 128-bit (112

are used) entry addressed by the Indirect Addres s Register to ensure the integrity of control content. Minimum two indirect

control writes and two indirect control reads are needed for each ACL entry read access (indirect data read shall follow),

and minimum one indirect control read and three indirect control writes are required for each ACL entry write access.

Each 112-bit Port-based ACL word entry (ACL Word) is accomplished through a sequence of the Indirect Access Control

0 Registers 110 (0x6E) accesses by specifying the bits[3:0] 4-bit Port number (Indirect address [11:8]) and 8-bit indirect

0x0d are used to specify the byte location of each entry (see above figure), address 0x00 indicates the byte 15 (MSB) of

each 128-bit entry, address 0x01 indicates the byte 14 etc., bytes at address 0x0E and 0x0F are reserved for the future.

Address 0x10 & 0x11 hold bit-wise Byte Enable for each entry. Address 0x12 is used as control and status register. The

format of these registers is defined in the following secti on.

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ACL Indirect Registers

This table is used to impl ement ACL mode selection and filtering p er port.

Table 21. ACL Indirect Regist ers for 14 Bytes ACL Rules

Address Name Description Mode Default

Port_ACL_0

ACL Port Register 0 (0x00)

Reg. 110 (0x6E ) bits [7:5] = 010 for A C L, Reg. 110 bits [3:0] = 0xn for Port 1, 2, 3 and 4.

Reg. 111 (0x6F) bits [7:0] = Offset 0x00 to access t he Indirect Byte Register 0xA0.

Location: (010 ACL) -> {0xn, offset} ->0xA0 holds the data.

Processing Field

7-4 Reserved RO 0x0

3-0 FRN[3:0]

First Rule Number

This is for the f i rst rule number of the Rule Set. There

are total 16 entries per port in ACL rule table. E ac h

single rule can be set with other rule for a rule set by

the ACL port Regis ter 12 (0x0c) and Register 13

(0x0d).

Regardless s ingle rule or rul e s et, have to assign an

entry for using which Action Field by FRN[3:0].

R/W 0000

Port_ACL_1

ACL Port Register 1 (0x01)

Reg. 110 (0x6E ) bits [7:5] = 010 for A C L, Reg. 110 bits [3:0] = 0xn for Port 1, 2, 3 and 4.

Reg. 111(0x6F) bits [7:0] = Offset 0x01 to ac c ess the Indirect Byte Register 0xA0.

Location: (010 ACL) -> {0xn, offset} ->0xA0 holds the data.

Matching Fields

7-6 Reserved RO 00

5-4 MD[1:0]

MODE

00 = Disable the current rule list, no action taken

01 = Qualify rules for layer 2 M A C header filteri ng

10 = Is used for layer 3 IP address f i ltering

11 = Performs layer 4 TCP port num ber/protocol

filtering

R/W 00

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Table 21. ACL Indirect Regist ers for 14 Bytes ACL Rules (continued

Address Name Description Mode Default

3-2 ENB[1:0]

ENABLE

When MD=01:

00 = The 11 bits from PM, P, REP, MM i n ac tion field

specify a count value for pack ets matching MA C

Address and TYP E in Matching Field.

The count unit is defined in FO R WARD field bit [4];

Bit [4] = 0, usec will be used.

Bit [4] = 1, msec will apply.

The FORWAED field bit [3] determines the algorithm

used to generate interrupt when counter terminated.

Bit [3] = 0, an 11-bit counter will be loaded with t he

count value from the list and start counting down every

unit time. An interrupt will be generated when expires,

i.e., next qualified packet has not been received withi n

the period specified by the v alue.

Bit [3] = 1, the counter is incremented every matched

packet receiv ed and the interrupt is generated while

terminal count reached, the count resets thereafter.

01 = MAC address bit field is participating in test.

10 = MAC TYPE bit field is used for test.

11 = Both MAC address and TYPE are tested against

these bit fields in the list.

When MD=10:

00 = Reserved.

01 = IP address and mask or IP protocol is enabled to

be tested accordingly.

10 = SA and DA are compared; the dr op/forward

decision is based on the E/Q bit s etting.

11 = Reserved

When MD=11:

00 = Protocol comparison is enabled.

01 = TCP/UDP address comparis on is selected.

10 = It is same with ‘01’

11 = The sequence number of TCP is compared.

R/W 00

1 S_D Source/Destination Address

0 = DA is used to com par e.

1 = SA is used to com pare R/W 0

0 EQ Compare Equal

0 = Match if t hey are not equal.

1 = Match if t hey are equal. R/W 0

Port_ACL_2

ACL Port Register 2 (0x02)

Reg. 110 (0x6E ) bits [7:5] = 010 for A C L, Reg. 110 bits[3:0 ] = 0xn for Port 1, 2, 3 and 4.

Reg. 111 (0x6F) bits [7:0] = Offset 0x02 to access t he Indirect Byte Register 0xA0.

Location: (010 ACL) -> {0xn, offset} ->0xA0 holds the data.

Matching Fields for Layer 2

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Table 21. ACL Indirect Regist ers for 14 Bytes ACL Rules (continued )

Address Name Description Mode Default

7-0 MAC_ADDR[47:40] MAC Address R/W 00000000

Port_ACL_3

ACL Port Register 3 (0x03)

Reg. 110 (0x6E ) bits [7:5] = 010 for A C L, Reg. 110 bits [3:0] = 0xn for Port 1, 2, 3 and 4.

Reg. 111 (0x6F) bits [7:0] = Offset 0x03 to access t he Indirect Byte Register 0xA0.

Location: (010 ACL) -> {0xn, offset} ->0xA0 holds the data.

Matching Fields for Layer 2

7-0 MAC_ADDR[39:32] MAC Address R/W 00000000

Port_ACL_4

ACL Port Register 4 (0x04)

Reg. 110 (0x6E ) bits [7:5] = 010 for ACL, Reg. 110 bits [3:0] = 0xn for P ort 1, 2, 3 and 4.

Reg. 111 (0x6F) bits [7:0] = Offset 0x04 to access t he Indirect Byte Register 0xA0.

Location: (010 ACL) -> {0xn, offset} ->0xA0 holds the data.

Matching Fields for Layer 2

7-0 MAC_ADDR[31:24] MAC Address R/W 00000000

ACL Port Register 5 (0x05)

Reg. 110 (0x6E ) bits [7:5] = 010 for ACL, Reg. 110 bits [3:0] = 0xn for P ort 1, 2, 3 and 4.

Reg. 111 (0x6F) bits [7:0] = Offset 0x05 to access t he Indirect Byte Register 0xA0.

Location: (010 ACL) -> {0xn, offset} ->0xA0 holds the data.

Matching Fields for Layer 2

7-0 MAC_ADDR[23:16] MAC Address R/W 00000000

Port_ACL_6

ACL Port Register 6 (0x06)

Reg. 110 (0x6E ) bits [7:5] = 010 for A C L, Reg. 110 bits [3:0] = 0xn for Port 1, 2, 3 and 4.

Reg. 111 (0x6F) bits [7:0] = Of fset 0x06 to access the Indirect Byte Register 0xA0.

Location: (010 ACL) -> {0xn, offset} ->0xA0 holds the data.

Matching Fields for Layer 2

7-0 MAC_ADDR[15:8] MAC Address R/W 00000000

Port_ACL_7

ACL Port Register 7 (0x07)

Reg. 110 (0x6E ) bits [7:5] = 010 for A C L, Reg. 110 bits [3:0] = 0xn for Port 1, 2, 3 and 4.

Reg. 111 (0x6F) bits [7:0] = Offset 0x07 to access t he Indirect Byte Register 0xA0.

Location: (010 ACL) -> {0xn, offset} ->0xA0 holds the data.

Matching Fields for Layer 4

7-0 MAC_ADDR[7:0] MAC Address R/W 00000000

Port_ACL_8

ACL Port Register 8 (0x08)

Reg. 110 (0x6E ) bits [7:5] = 010 for A C L, Reg. 110 bits [3:0] = 0xn for Port 1, 2, 3 and 4.

Reg. 111 (0x6F) bits [7:0] = Offset 0x08 to access t he Indirect Byte Register 0xA0.

Location: (010 ACL) -> {0xn, offset} ->0xA0 holds the data.

7-0 TYPE[15:8] Ether Type R/W 00000000

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Table 21. ACL Indirect Regist ers for 14 Bytes ACL Rules (continued )

Address Name Description Mode Default

Port_ACL_9

ACL Port Register 9 (0x09)

Reg. 110 (0x6E ) bits [7:5] = 010 for ACL, R eg. 110 bits [3:0] = 0xn for Port 1, 2, 3 and 4.

Reg. 111 (0x6F) bits [7:0] = Off set 0x09 to access the Indirect B yte Register 0xA0.

Location: (010 ACL) -> {0xn, offset} ->0xA0 holds t he data.

7-0 FLAG[7:0] TCP FLAG R/W 00000000

Note: Layer 2, layer 3 and layer 4 in matching field should b e in different entr ies. Same layer should be in same entry.

See ACL Format figure for the detail.

Port_ACL_A

ACL Port Register 10 (0x0A)

Reg. 110 (0x6E) bits [7:5] = 010 for ACL, Reg. 110 bits [3:0] = 0xn for Port 1, 2, 3 and 4.

Reg. 111 (0x6F) bits [7:0] = Offset 0x0A to access t he Indirect Byte Register 0xA0.

Location: (010 ACL) -> {0xn, off s et} ->0xA0 holds the data.

Action Field

7-6 PM[1:0]

Priority Mode

00 = No priority is selected; the priority determined by

QoS/Classification is used in the tagged packets.

01 = Priorit y in P [2:0] bits field is used if it is greater

than QoS result in the 3-bit pri or i ty field of the

tagged packets received.

10 = Priorit y in P [2:0] bits field is used if it is sm aller

than QoS result in the 3-bit pri or i ty field of the

tagged packets received.

11 = P [2:0] bits field will repla ce the 3-bit priority field

of the tagged packets received.

R/W 00

5-3 P[2:0] Priority

Note: The 3-bit priority value to be used depends on PM [1:0]

setting in bits [7:6].

R/W 000

2 RPE

Remark Priority Enable

0 = No remarking i s necessary.

1 = VLAN priority bits in the pac kets are replaced by

RP [2:1] bits field be low in the list.

R/W 0

1-0 RP[2:1]

Remark Priority

00 = Priorit y 0

01 = Priorit y 1

10 = Priorit y 2

11 = Priorit y 3

R/W 00

Port_ACL_B

ACL Port Register 11 (0x0B)

Reg. 110 (0x6E ) bits [7:5] = 010 for ACL, R eg. 110 bits [3:0] = 0xn for Port 1, 2, 3 and 4.

Reg. 111 (0x6F) bits [7:0] = Off s et 0x0B to access the Indirect B yte Register 0xA0.

Location: (010 ACL) -> {0xn, off s et} ->0xA0 holds the data.

Action Field

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Table 21. ACL Indirect Regist ers for 14 Bytes ACL Rules (continued)

Address Name Description Mode Default

7 RP[0] Remark Priority R/W 0

6-5 MM[1:0]

Map Mode

00 = No for warding remappin g is necessary. Don’t use

the forwarding map in FORWARD field, use the

forwarding map from the look-up table only.

01 = The forwarding map in FO RWARD field is OR’ed

with the forwarding map from the look-up table.

10 = The forwarding map in FO RWARD field is AND’ed

with the forwarding map from the look-up table.

11 = The forwarding map in FO RWARD field replaces

the forwarding map from the look-up table.

R/W 00

4-0 FORWARD[4:0]

Port Map

Each bit indicates forwarding decision of o ne port.

Bit [0] = Port 1

Bit [1] = Port 2

Bit [2] = Port 3

Bit [3] = Reserved

Bit [4] = Port 4

When MD=01 and ENB =00,

Bit [4] is used as c ount unit.

0 = us.

1 = ms.

Bit [3] is used to select count m odes:

0 = count down in the 11-bit counter from an assigned.

value in the Action fiel d PM, P, RPE, RP and MM,

an interrupt will be generated when expired.

1= count up in the 11-bit counter for every matched

packet received up to r each an assigned value in

the Action field PM, P , RPE, RP and MM, and then

an interrupt will b e generated.

Note: See ENB field description for detail.

R/W

Port_ACL_C

ACL Port Register 12 (0x0C)

Reg. 110 (0x6E) bits [7:5] = 010 for ACL, Reg. 110 bits [3:0] = 0xn for P ort 1, 2, 3 and 4.

Reg. 111 (0x6F) bits [7:0] = Off s et 0x0C to access the Indirect Byte Register 0xA0.

Location: (010 ACL) -> {0xn, off s et} ->0xA0 holds the d ata.

Processing Field

7-0 RULESET[15:8]

Rule Set

Each bit indicates this entry in bits 0-15 16 entries of

the rule list to be assigned for the rule set to be used in

the rules casc ade per port.

R/W 00000000

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Table 21. ACL Indirect Regist ers for 14 Bytes ACL Rules (continued )

Table 22. T emporal storage f or 14 Bytes ACL R ules

Address Name Description Mode Default

Port_ACL_BYTE_ENB_MSB

ACL Port Register 14 (0x10)

Reg. 110 (0x6E) bits [7:5] = 010 for ACL, Reg. 110 bits [3:0] = 0xn for P ort 1, 2 ,3 and 4.

Reg. 111 (0x6F) bits [7:0] = Off s et 0x10 to access the Indirect Byte Re gi ster 0xA0.

Location: (010 ACL) -> {0xn, off s et} ->0xA0 holds the data.

7-6 Reserved RO 00

5-0 BYTE_ENB[13:8]

Byte Enable in A C L table; 14-Byte per entry

1 = Byte is selected for r ead/write

0 = Byte is not selected

Bit [0] of BYTE_ENB[13:0] is for byte address 0x0D in

ACL table entry,

Bit [1] of BYTE_ENB[13: 0] is for byte address 0x0C in

ACL table entry, etc.

Bit [13] of BYTE_ENB[13:0] i s for byte address 0x00 in

ACL table entry.

R/W 0

Port_ACL_ BYTE_ENB_LSB

ACL Port Register 15 (0x11)

Reg. 110 (0x6E) bits [7:5] = 010 for ACL, R eg. 110 bits [3:0] = 0xn for Port 1, 2, 3 and 4.

Reg. 111 (0x6F) bits [7:0] = Offset 0x11 to access the Indirect Byte Register 0xA0.

Location: (010 ACL) -> {0xn, off s et} ->0xA0 holds the data.

7-0 BYTE_ENB[7:0]

Byte Enable in A C L table; 14-Byte per entry

1 = Byte is select ed for read/writ e

0 = Byte is not selected

Bit [0] of BYTE_ENB[13:0] is for byte address 0x0D in

ACL table entry,

Bit [1] of BYTE_ENB[13: 0] is for byte address 0x0C in

ACL table entry, etc.

Bit [13] of BYTE_ENB[13:0] i s for byte address 0x00 in

ACL table entry.

R/W 0x00

Address Name Description Mode Default

Port_ACL_D

ACL Port Register 13 (0x0D)

Reg. 110 (0x6E) bits [7:5] = 010 for ACL, Reg. 110 bits [3:0] = 0xn for Port 1, 2, 3 and 4.

Reg. 111 (0x6F) bits [7:0] = Off set 0x0D to access the Indirect Byte Register 0xA0.

Location: (010 ACL) -> {0xn, off s et} ->0xA0 holds the data.

Processing Field

7-0 RULESET[7:0]

Rule Set

Each bit indicates this entry in bits 0 to 15, total 16

entries of the rule list can be assigned for t he rule set to

be used in the rules cascade per port.

R/W 00000000

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Table 23. ACL Read and Write Control

Address Name Description Mode Default

Port_ACL_ACCESS_CONTROL1

ACL Port Register 16 (0x12)

Reg. 110 (0x6E) bits [7:5] = 010 for ACL, Reg. 110 bits [3:0] = 0xn for Port 1, 2, 3 and 4.

Reg. 111 (0x6F) bits [7:0] = Offset 0x12 to access the Indirect Byte Register 0xA0.

Location: (010 ACL) -> {0xn, off s et} ->0xA0 holds the data.

7 Reserved N/A Don’t Change RO 0

6 WRITE_STATUS Write Operation Status

1 = Write compl eted

0 = Write is in progress RO 1

5 READ_STATUS Read Operation Status

1 = Read completed

0 = Read is in progress RO 1

4 WRITE_READ Request Type

1 = Write

0 = Read R/W 0

3-0 ACL_ENTRY_ADDRESS

ACL Entry Address

0000= entry 0.

0001= entry 1.

…..

1111= entry 15.

R/W 0000

Port_ACL_ ACCESS_CONT ROL2

ACL Port Register 17 (0x13)

Reg. 110 (0x6E) bits [7:5] = 010 for ACL, Reg. 110 bits [3:0] = 0xn for Port 1, 2, 3 and 4.

Reg. 111 (0x6F) bits [7:0] = Offset 0x13 to access the Indirect B yte Register 0xA0.

Location: (010 ACL) -> {0xn, offset} ->0xA0 holds the data.

7-1 Reserved N/A Don’t Change RO 0000000

0 Force DLR Miss

1 = DLR filtering uses single ACL entry. DLR packet

matching the ACL entry will be considered as MISS.

0 = DLR filtering uses multiple ACL entries. DLR packet

matching the rul e s et for DLR packet will be considered

as HIT.

Note: DLR means Device Level Redundancy.

R/W 0

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The ACL registers c an be programmed usin g the read/write examples below.

Read Operation

Use the Indirect Access Control Register to select re gi st er t o be read. To read Entry0 that is 1st entry of Port 1:

Write 0x41 to Register 110 (0x6E) // select ACL and write to Port 1 (Port 2, 3 and 4 are 0x42, 0x43 and 0x45)

Write 0x10 to Register 111 (0x6F) // trigger the write operation for Port 1 in the ACL Port Register 14 (Byte Enable MSB

Write 0x3F into the I ndi rect Byte Register 160 (0xA0) for MSB of Byte Enable word.

Write 0x41 to Register 110 (0x6E) // select write to Port 1.

Write 0x11 to Register 111 (0x6F) // trigger the write operation for Port 1 in the ACL Port Register 15 (Byte Enable LSB

Write 0xFF into the Indirect Byte Register 160 (0xA0) for LSB of Byte Enable word. (The above steps set Byte Enable

Write 0x41 to Register 110 (0x6E) //select ACL and write operations to Port 1.

Write 0x12 to Register 111 (0x6F) //Write ACL read/write control register address 0x12 to the indirect address in Register

111 to trigger the read operation for Po rt 1 in t he A CL Port Register 16 (ACL Access Control Register) to read entry 0.

Write 0x00 into the Indirect Byte Register 160 (0xA0)//ACL Port Register 16 (0x12) bit [4] = 0 to read ACL and bits [3:0] =

0x0 for entry 0.(The above steps set ACL control register to read ACL entry wor d 0).

Write 0x51 to Register 110 (0x6E) //select ACL and read to Port 1 (Port 2, 3 and 4 are 0x52, 0x53 and 0x55 ).

Write 0x12 to Register 111 (0x6F) //trigger the read operation for Port 1 in the ACL Port Register16 (ACL Access Control

1).

Read the Indirect Byte Register 160 (0xA0) to get data (If bit [5] is set, the read completes in the ACL port Register 16

(0x12) and go to nex t step. Otherwise, repeat the above polling step).

Write 0x51 to Register 110 (0x6E) // select read to P ort 1.

Write 0x00 to Register 111 (0x6F) // trigger the read/burst read operation(s) based on the Byte Enable Register setting by

the Port 1 ACL access Register 0 (0x00).Read/Burst read the Indirect Byte Register 160 (0xA0) // to get data of ACL entry

word 0, write 0x00 to 0x0D indirect address and read Register 160 (0xA0) after each byte address write to Register 111

(0x6F).

Write Operation

Use the Indirect Access Control Register to select re gi st er t o be written. To write even byte number of 15th entry of Port 4:

Write 0x55 to Register 110 (0x6E) // select ACL and read to Port 4.

Write 0x12 to Register 111 (0x6F) // trigger the read operation for Port 4 ACL Access Cont rol Register read.

Read the Indirect Byte Register 160 (0xA0) to get data (If bit [6] is set, the previous write completes and go to next step.

Otherwise, repeat the above polling step).

Write 0x45 to Register 110 (0x6E) // select ACL an d write to Port 4.

Write 0x00 to Register 111 (0x6F) //set off set address for Port 4 ACL Port Register 0.

Write/Burst write the Indirect Byte Register 160 (0xA0) for ACL Port Register 0, 1, 2, …,13 from 0x00 to 0x0D) (Write or

Burst write even bytes of Port 4 ACL acces s Registers 0, 1, …, 13 to holdi ng buffer).

Write 0x45 to Register 110 (0x6E) // select ACL and write to Port 4.

Write 0x10 to Register 111 (0x6F) // trigger the write operation for Port 4 in the ACL Port Register 14 (Byte Enable MSB

Write 0x15 into the Indirect Byte Register 160 (0xA0) for MSB of Byte Enable word to enable odd bytes address 0x01,

0x03 and 0x05.

Write 0x45 to Register 110 (0x6E) // select write to Port 4.

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Write 0x11 to Register 111 (0x6F) // trigger the write operation for Port 4 in the ACL Port Register 15 (Byte Enable LSB

Write 0x55 into the Indirect Byte Register 160 (0xA0) for LSB of Byte Enable word to enable odd bytes address 0x07,

0x09, 0x0B and 0x0D.(The above steps set Byte Enable Register to select odd address bytes in ACL word.)

Write 0x45 to Register 110 (0x6E) // select write to Port 4.

Write 0x12 to Register 111 (0x6F) // write the port ACL access control register address (0x12) to the Indirect Address

Write 0x1F into the Indirect Byte Register 160 (0xA0) // for the write operation to 15th entry in the ACL Port Register 16

(0x12) bit4=1 to write ACL, bits [3:0] = 0xF to write entry 15.

(The above steps set A CL Control Register to write ACL entry word 15 from holding buff er.)

The bit arrangement of above example assumes layer 2 rule of MODE = 01 in ACL Port Register 1 (0x01), refer to ACL

format for MODE = 1 0 and 11.

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EEE Indirect Registers

The EEE function is for the copper ports only. The EEE registers are provided on global and per port basis. These

registers are read/writ e using indirect mem ory access as below: LPI means Low Power Idle.

EEE Global Registers

Address Name Description Mode Default

EEE Global Register 0

Global EEE QM Buffer Control Register

Reg. 110 (0x6E) bits [7:5] = 001 for EEE, Reg. 110 bits [3:0] = 0x0 for t he indirect global register.

Reg. 111 (0x6F) bits [7:0] = Offset to access the Indir ec t Byte Register 0xA0.

Offset: 0x30 (bits [15:8]), 0x31 (bits [7:0]).

Location: (001 EEE) -> {0x0, offset} ->0xA0 hol ds the data.

15-8 Reserved N/A Don’t Change RO 0x40

7 LPI Terminated By Input

Traffic Enable

1 = LPI request will be s topped if input traffic is

detected.

0 = LPI request won’t be stopped b y input traffic. R/W 0

6-0 Reserved N/A Don’t Change RO 0x10

EEE Global Register 1

Global Empty TXQ to LPI wait time control Register

Reg. 110 (0x6E ) bits [7:5] = 001 for EEE, Reg. 110 bits [3:0] = 0x0 for the indirect global register,

Reg. 111 (0x6F) bits [7:0] = Offset to access the Indir ec t Byte Register 0xA0.

Offset: 0x32 (bits [15:8]), 0x33 (bits [7:0])

Location: (001 EEE) -> {0x0, offset} ->0xA0 hol ds the data.

15-0 Empty TXQ to LPI Wait

Time

This regist er specifies the t ime that the LPI request will

be generated a fter a TXQ has been em pty exceeds this

configured time. This is onl y valid when EEE 100B T is

enabled. This setting will ap ply to all the Ports. The unit

is 1.3ms. The default value is 1.3 sec. (range from

1.3ms to 86 sec ond)

R/W 0x10

EEE Global Register 2

Global EEE PCS DIAGNOSTIC Register

Reg. 110 (0x6E) bits [7:5] = 001 for EEE, Reg. 110 bits [3:0] = 0x0 for t he indirect global register.

Reg. 111 (0x6F) bits [7:0] = Offset to access the Indirect Byte Register 0xA0.

Offset: 0x34(bits [15:8]), 0x35 (bits [7:0]).

Location: (001 EEE) -> {0x0, offset} ->0xA0 hol ds the data.

15-12 Reserved N/A Don’t Change RO 0x6

11-8 Reserved N/A Don’t Change RO 0x8

7-4 Reserved N/A Don’t Change RO 0x0

3 Port 4 Next Page

Enable

1 = Enable next page exchange during Auto-

Negotiation.

0 = Skip next page e xchange during Auto-Negotiation.

R/W 1

2 Port 3 Next Page

Enable

1 = Enable next page exchange dur i ng Auto-

Negotiation.

0 = Skip next page exchange during Auto-Negotiation.

R/W 1

1 Port 2 Next Page

Enable

1 = Enable next page exchange dur i ng Auto-

Negotiation.

0 = Skip next page e xchange during Auto-Negotiation.

R/W 1

0 Port 1 Next Page

Enable

1 = Enable next page exchange dur i ng Auto

Negotiation.

0 = Skip next page e xchange during Auto-Negotiation.

R/W 1

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EEE Global Registers (Continued)

Address Name Description Mode Default

EEE Global Register 3

Global EEE Minimum LPI cycles before back to Idle Control Reg ister

Reg. 110 (0x6E) bits [7:5] = 001 for EEE, Reg. 110 bits [3:0] = 0x0 for the indirect global register,

Reg. 111 (0x6F) bits [7:0] = Offset to access the Indir ect Byte Register 0xA0.

Offset: 0x36 (bits [15:8], 0x37 (bits [7:0]).

Location: (001 EEE) -> {0x0, offset} ->0xA0 hol ds the data.

15-0 Reserved N/A Don’t Change RO 0x0000

EEE Global Register 4

Global EEE Wakeup Error Threshold Control Register

Reg. 110 (0x6E) bits [7:5] = 001 for EEE, Reg. 110 bits [3:0] = 0x0 for the indirect gl obal register,

Reg. 111 (0x6F) bits [7:0] = Offset to access the Indir ec t Byte Register 0xA0.

Offset: 0x38 (bits [15:8]), 0x39 (bits [7:0]).

Location: (001 EEE) -> {0x0, offset} ->0xA0 hol ds the data.

15-0 EEE Wakeup Threshold

This value specifies the maximum time allowed for PHY

to wake up.

If wakeup time is longer than this, EEE wakeup error

count will be incremented.

Note: This is EEE standard, don’t change.

RO 0x0201

EEE Global Register 5

Global EEE PCS Diagnostic Control Register

Reg. 110 (0x6E) bits [7:5] = 001 for EEE, Reg. 110 bits [3:0] = 0x0 for t he indirect global register,

Reg. 111 (0x6F) bits [7:0] = Offset to access the Indi r ect Byte Register 0xA0.

Offset: 0x3A (bits [15:8]), 0x3B (bits [7:0]).

Location: (001 EEE) -> {0x0, offset} ->0xA0 holds the data.

15-0 Reserved N/A Don’t Change. RO 0x0001

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EEE Port Registers (Continued)

Address Name Description Mode Default

EEE Port Register 0

Port Auto-Negotiatio n E xpansion Status Register

Reg. 110 (0x6E ) bits [7:5] = 001 for EEE, Reg. 110 bits [3:0] = 0xn, n=1-3 for the Indir ect Port Register ,

Reg. 111 (0x6F) bits [7:0] = Offset to access the Indi r ect Byte Register 0xA0.

Offset: 0x0C (bits [15:8]), 0x0D (bits [7:0]).

Location: (001 EEE) -> {0xn, offset} ->0xA0 holds the data.

15-7 Reserved N/A Don’t Change RO 9h000

6 Receive Next Page

Location Able

1 = Received Ne xt P age s torage location is specified

by bits [6:5].

0 = Received Ne xt P age s torage location is not

specified by bits [6:5].

RO 1

5 Received Ne xt P age

Storage Location

1 = Link Partne r N ext Pages are stored in MIIM

0 = Link Partner Next Pages are stored in MIIM

RO 1

4 Parallel Det ec tion Fault

1 = A fault has bee n detected via the Parallel Det ec tion

function.

0 = A fault has not been detected via the Parallel

Detection function.

This bit is c l ear ed after reading.

R/LH 0

3 Link Partner Next Page

Able 1 = Link Partner is Next Page abled

0 = Link Partner is not Next Page abled RO 0

2 Next Page Abl e 1 = Local Device is Next Page abled

0 = Local Devi c e i s not Next Page abled RO 1

1 Page Received 1 = A New Page has be en received

0 = A New Page has not been received R/LH 0

0 Link Partner Auto-

Negotiation Able 1 = Link Partner is A uto-Negotiation abled

0 = Link Partner is not Auto-Negot iation abled RO 0

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EEE Port Registers (Continued)

Address Name Description Mode Default

EEE Port Register 1

Port Auto-Negotiatio n Next Page Transmit Register

Reg. 110 (0x6E ) bits [7:5] = 001 for EEE, Reg. 110 bits [3:0] = 0xn, n=1-3 for the Indir ect Port Register ,

Reg. 111 (0x6F) bits [7:0] = Offset to access the Indi r ect Byte Register 0xA0.

Offset: 0x0E (bits [15:8]), 0x0F (bits [7 :0]).

Location: (001 EEE) -> {0xn, offset} ->0xA0 hol ds the data.

This regist er doesn’t need to be set if EEE Port Regist er 5 bit[7]=1 defaul t for Automatic ally perform EEE capabilit y

15 Next Page

Next Page (NP) i s used by the Next Page function to

indicate whether or not this is the last Next Page to be

transmitted. NP shall be set as follows:

1 = Additional Next Page(s) wi l l follow.

0 = Last page.

R/W 0

14 Reserved Reserved RO 0

13 Message Page

Message Page (MP) is used by t he Next Page func tion

to differentiate a Message Page from an Unformatted

Page. MP shall be set as follows:

1 = Message Page.

0 = Unformatt ed P age.

R/W 1

12 Ackno wled ge 2

Acknowledge 2 (Ack2) is used by the Next Page

function to indicate that a device has the ability to

comply with the message. Ack2 shall be s et as follows:

1 = Will compl y with message.

0 = Cannot comply with message.

R/W 0

11 Toggle

Toggle (T ) is used by the Arbitration function to ensure

synchronizat ion with the Li nk Partner dur i ng Next

Page exchang e. This bit shall always take the opposite

value of the Toggle bit in the prev iously exchang ed

Link Codeword. The initial value of the Toggle bit in the

first Next Page transmitted is the inverse of bit [11]

in the base Link Codeword an d, therefore, may assume

a value of logic one or zero. The Toggle bit shall be

set as follows:

1 = Previous v al ue of the trans mitted Link Codeword

equal to logic zero.

0 = Previous v al ue of the trans mitted Link Codeword

equal to logic one.

RO 0

10-0 Message/Unformatted

Code field Mes sage/Unform atted Code field bi ts [10:0] R/W 1

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EEE Port Registers (Continued)

Address Name Description Mode Default

EEE Port Register 2

Port Auto-Negotiatio n Link Partner Next Page Recei ve Register

Reg. 110 (0x6E ) bits [7:5] = 001 for EEE, Reg. 110 bits [3:0] = 0xn, n=1-3 for the indirect port register.

Reg. 111 (0x6F) bits [7:0] = Offset to access the I ndirect Byte Register 0xA0.

Offset: 0x10 (bits [15:8]), 0x11 (bits [7:0].

Location: (001 EEE) -> {0xn, offset} ->0xA0 hol ds the data.

15 Next page

Next Page (NP) i s used by the Next Page function to

indicate whether or not this is the last Next Page to be

transmitted. NP shall be set as follows:

1 = Additional Next Page(s) wi l l follow.

0 = Last page.

RO 0

14 Acknowledge

Acknowledge (Ack) is used by the Auto-Negotiation

function to indicate that a device has successfully

received its Link Partner’s Link Codeword. The

Acknowledge Bit is encoded i n bi t D14 regardless of

the value of the S elector Fiel d or Li nk Codeword

encoding. I f no Next Page information is to be sent , this

bit shall be set to logic one in the Link Codeword after

the reception of at least three c onsecutive and

consistent FLP Bursts (ignoring the Acknowledge bit

value).

RO 0

13 Message Page

Message Page (MP) is used by t he Next Page func tion

to differentiate a Message Page from an Unformatted

Page. MP shall be set as follows:

1 = Message Page

0 = Unformatt ed P age

RO 0

12 Ackno wled ge 2

Acknowledge 2 (Ack2) is used by the Next Page

function to indicate that a device has the ability to

comply with the message. Ack2 shall be s et as follows:

1 = Will comply with message.

0 = Cannot comply with message.

RO 0

11 Toggle

Toggle (T ) is used by the Arbitration function to ensure

synchronizat ion with the Li nk Partner dur i ng Next

Page exchang e. This bit shall always take the opposite

value of the Toggle bit in the prev iously exchang ed

Link Codeword. The initial value of the Toggle bit in the

first Next Pag e transmitt ed is the inverse of bit [11]

In the base Link Codeword and, therefore, may

assume a value of logic one or zer o. The Toggle bit

shall be

set as follows:

1 = Previous v al ue of the trans mitted Link Codeword

equal to logic zero.

0 = Previous v al ue of the trans mitted Link Codeword

equal to logic one.

RO 0

10-0 Message/Unformatted

Code field Mes sage/Unform atted Code field bi ts [10:0] RO 0

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EEE Port Registers (Continued)

Address Name Description Mode Default

EEE Port Register 3

Link Partn er EEE Capabil i ty Status and L ocal Device EEE C apability Advisement Register

Reg. 110 (0x6E) bits [7:5] = 001 for EEE, Reg. 110 bits [3:0] = 0xn, n=1-3 for the Indir ec t Port Register.

Reg. 111 (0x6F) bits [7:0] = Offset to access the Indi r ect Byte Register 0xA0.

Offset: 0x28 (bits [15:8]), 0x29 (bits [7:0]).

Location: (001 EEE) -> {0xn, offset} ->0xA0 hol ds the data.

15 Reserved N/A Don’t Change RO 0

14 LP 10GBASE-KR EEE

Note: LP is Link Partner

1 = EEE is supported for 10GBASE-KR

0 = EEE is not supported for 10GBASE-KR

Note: LP is Link Partner

RO 0

13 LP 10GBASE-KX4 EEE 1 = EEE is supported for 10G B ASE-KX4

0 = EEE is not supported for 10GB ASE-KX4 RO 0

12 LP 1000BASE -KX EEE 1 = EEE is supported for 1000B A S E-KX

0 = EEE is not supported for 1000BAS E-KX RO 0

11 LP 10GBASE-T EEE 1 = EEE is supported for 10GB ASE-T

0 = EEE is not supported for 10GB ASE-T RO 0

10 LP 1000BASE -T EEE 1 = EEE is supported for 1000BASE-T

0 = EEE is not supported for 1000BAS E-T RO 0

9 LP 100BASE-TX EEE 1 = EEE is supported for 100BA S E-TX

0 = EEE is not supported for 100BAS E-TX RO 0

8-2 Reserved Reserved RO 7h’0

1 Local 100BASE-TX EEE

Note: This is for local port to

support EEE capability

1 = EEE is supported for 100BASE-TX

0 = EEE is not supported for 100BAS E-TX R/W 1

0 Reserved N/A Don’t Change RO 0

EEE Port Register 4

Port EEE Wake Up Error Count Register

Reg. 110 (0x6E ) bits [7:5] = 001 for EEE, Reg. 110 bits [3:0] = 0xn, n=1-3 f or the Indirect P ort Register.

Reg. 111 (0x6F) bits [7:0] = Offset to access the Indir ec t Byte Register 0xA0.

Offset: 0x2A (bits [15:8]), 0x2B (bits [7:0]).

Location: (001 EEE) -> {0xn, offset} ->0xA0 hol ds the data.

15-0 EEE Wakeup Error

Counter

This count is incremented by one whenever a wakeup

from LPI to I dl e s tate is longer than the Wake-Up error

threshold tim e specified in EEE Global Register 4. The

default of Wake-Up er ror threshold time is 20.5µs. This

RO 0x0000

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EEE Port Registers (Continued)

Address Name Description Mode Default

EEE Port Register 5

Port EEE Control Register

Reg. 110 (0x6E ) bits [7:5]=001 f or EEE, Reg. 110 bits [3:0] = 0xn, n=1-3 for the Indirec t Port Register.

Reg. 111 (0x6F) bits [7:0] = Offset to access the Indirect Byte Register 0xA0.

Offset: 0x2C (bits [15:8]), 0x2D (bits [7:0]).

Location: (001 EEE) -> {0xn, offset} ->0xA0 hol ds the data.

15 10BT EEE Disable

1 = 10BT EEE mode is d i s abled

0 = 10BT EEE mode is e nabled

Note: 10BT EEE mode save power by reducing signal

amplitude only.

R/W 1

14-8 Reserved N/A Don’t Change RO 7h’0

7 H/W Based EEE NP

Auto-Negoti ation Enable

1 = H/W will automatically perform EEE capabi li ty

exchange with Link Partner through next page

exchange. E E E 100BT enable (bit [0] of this

matched.

0 = H/W based EEE c apability exchange is off. E EE

capability exchange is do ne by software.

R/W 1

6 H/W 100BT EEE Enable

Status 1 = 100BT EEE is enabled by H/ W based np exchange

0 = 100BT EEE is disabled R 0

5 TX LPI Received

1 = Indicates t hat the transmit PCS has received low

power idle signaling one or more times sinc e the

0 = Indicates t hat the PCS has not r ec ei v ed low power

idle signali ng.

This bit is c l ear ed after reading.

R/RC 0

4 TX LPI Indication

1 = Indicates t hat the transmit PC S i s currently

receiving low power idle signals.

0 = Indicates t hat the PCS is not cur r ently receiving

low power idle s i gnals.

R 0

3 RX LPI Received

1 = Indicates t hat the receive PCS has received l ow

power idle signaling one or more times sinc e the

0 = Indicates t hat the PCS has not r ec ei v ed low power

idle signali ng.

This bit is c l ear ed after reading.

R/RC 0

2 RX LPI Indicati on

1 = Indicates t hat the receive PCS is currently

receiving low power idle signals.

0 = Indicates t hat the PCS is not cur r ently receiving

low power idle signal s.

R 0

1 EEE SW Mode Enable 1 = EEE is enabled through S/W set ting bit [0] of this

0 = EEE is enabled through H/W Auto-Negotiation R/W 0

0 EEE SW 100BT Enable

1 = EEE 100BT is enabled

0 = EEE 100BT is disabled

Note: This bit could be set by S/W or H/W if H/W based EEE

Next Page Auto-Negotiation enable is on.

R/W 0

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EEE Port Registers (Continued)

Address Name Description Mode Default

EEE Port Register 6

Port EEE LPI Recovery Time Register

Reg. 110 (0x6E) bits [7:5] = 001 for EEE, Reg. 110bits [3:0] = 0xn, n=1-3 for the Indirect Port Register.

Reg. 111 (0x6F) bits [7:0] = Offset to access the Indi r ect Byte Register 0xA0.

Offset: 0x2E (bits [15:8]), 0x2F (bits [7:0]).

Location: (001 EEE) -> {0xn, offset} ->0xA0 holds the data.

15-8 Reserved Reserved RO 1

7-0 LPI Recovery Counter

This regist er specifies the t ime that the MAC device

has to wait before it can start t o s end out packets . This

value should b e the maximum of the LPI recovery time

between local device and remote device.

The unit is 640ns.

The default is about 25us = 39 (0x 27) X 640ns

Note: This value can be adjust if PHY recovery tim e i s

less than the standard 20.5us for the packets to be

sent out quickly from EEE LP I mode.

R/W 0x27

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Programming Examples:

Read Operation

1. Use the Indirect Access Control Register to select register to be read, to read the EEE Global Register 0 (Global EEE

QM Buffer Control Register).

2. Write 0x30 to the Register 110 (0x6E) // EEE selected and read operation, and 4 MSBs of Port number = 0 for the

global register.

3. Write 0x30 to the indirect Register 111 (0x6F) // trigger the read operation and ready to read the EEE Global Register

0 bits [15:8].

4. Read the Indirect B yte Register 160 (0x A0) //Get the bits [15:8] value of the EEE Global Register 0.

Write Operation

1. Write 0x20 to Register 110 (0x6E) // EEE selected and write operation, 4 MSBs of Port number = 0 is for global

2. Write 0x31 to Register 11 1 (0x6F) // select the offset address, ready to write the EEE Global Register 0 bits [7:0].

3. Write new value to the Indirect Byte Register 160 (0xA0) bits [7:0].

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Management Information Base (MIB) Counters

The MIB counters are provided on per port basis. These counters are read using indirect memory access as below:

Table 24. Port 1 MIB Counter Indirect Memory Offerts

Offset Counter Name Description

0x0 RxHiPriorityByte Rx hi-pri ority octet count including bad packets.

0x1 RxUndersizePkt Rx undersize p ackets w/good CR C.

0x2 RxFragments Rx fragment packets w/bad CRC, symbol errors or alignment errors.

0x3 RxOversize Rx oversize packets w/good CRC (m ax: 1536 or 1522 bytes).

0x4 RxJabbers Rx packets longer than 1522 b yt es w/either CRC errors, alignment errors, or symbol errors

(depends on max packet size s etting) or Rx pack ets longer than 1916 bytes onl y.

0x5 RxSymbolError Rx packets w/ invalid data symbol and legal preamble, p ac ket size.

0x6 RxCRCerror Rx pack ets within (6 4,1522) bytes w/an integral number of bytes and a bad CRC (upper limit

depends on max packet size setting).

0x7 RxAlignmentError Rx packets within (64,1522) bytes w/a non-integral num ber of bytes and a bad CRC (upper lim i t

depends on max packet size setting).

0x8 RxControl8808Pkts The number of MAC control frames recei v ed by a Port with 88-08h in EtherType field.

0x9 RxPausePkts The number of PAUSE frames r eceived by a Port. P A U S E frame is qualifi ed with EtherType

(88-08h), DA, control opcode (00-01), data lengt h (64 byte min) , and a valid CRC.

0xA RxBroadcast Rx good broad c ast packets (not including errored broadcas t packets or valid multicast packets).

0xB RxMulticast Rx g ood multicast packets (not inc l uding MAC control frames, errored multicas t packets or vali d

broadcast packets).

0xC RxUnicast Rx goo d unicast packets.

0xD Rx64Octets Total Rx packet s (bad packets included) that were 64 octets in length.

0xE Rx65to127Octets T otal Rx packets (bad packets included) that are between 65 and 127 octets in length.

0xF Rx128to255Octets T otal Rx packets (bad packets included) that are between 128 and 255 octets in length.

0x10 Rx256to511Octets Total Rx packets (bad packets i nc l uded) that are between 256 and 511 octets in length.

0x11 Rx512to1023Octets Total Rx packets (bad packets i nc l uded) that are between 512 and 1023 octets in length.

0x12 Rx1024to1522Octets Total Rx packets (bad packets included) that are between 1024 and 1522 octets in length.

0x13 Rx1523to2000Octets Total Rx packets (bad pac kets included) that are between 1523 and 2000 octets in length.

0x14 Rx2001toMax-

1Octets Total Rx packets ( bad packets inclu ded) that are between 2001 and Max-1 octets in length (upper

limit depends on max packet s ize -1).

0x15 TxHiPriorityByte Tx hi-priorit y good octet coun t, including PA U S E packets.

0x16 TxLateCollision The number of times a collis ion is detected later than 512 bit-times int o the Tx of a packet.

0x17 TxPausePkts The number of PAUSE fr ames transmit ted by a Port.

0x18 TxBroadcastPkts Tx good broadcast packets (not including errored broadcas t or valid multic ast packets).

0x19 TxMulticastPkts Tx good multic as t packets (not i nc l uding errored m ul ticast packet s or valid broadcas t packets).

0x1A TxUnicastPkts Tx good unicast packets.

0x1B TxDeferred Tx pack ets by a Port for which the 1st Tx attem pt is delayed due to the busy medium .

0x1C TxTotalCollision Tx total collis ion, half-du plex only.

0x1D TxExcessiveCollision A count of frames for which Tx fails due to excessive collisions.

0x1E TxSingleCollision Successf ully Tx frames o n a Port for which Tx is inhibited by exactly one collision.

0x1F TxMultipleCollision Succes sfully Tx fram es on a Port for which Tx is inhibited by more than one collision.

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For Port 2, the base is 0x20, same offset definition (0x20-0x3f)

For Port 3, the base is 0x40, same offset definition (0x40-0x5f)

Reserved, the base i s 0x60, same offset de fi n ition (0x60-0x7f)

For Port 4, the base is 0x80, same offset definition (0x80-0x9f)

Table 25. Format of “Per Port” MIB Counter

Address Name Description Mode Default

Format of Per Port M IB Counters

38 Overflow 1 = Counter over flow.

0 = No Counter over flow. RO 0

37 Count Valid 1 = Counter value is val id.

0 = Counter value is not valid. RO 0

36-30 Reserved N/ A No Change RO All ‘0’

29-0 Counter Values Counter value. RO 0

Table 26. All Port Dropped Packet MIB Counters

Offset

Counter Name

Description

0x100 Port1 Rx Total Bytes Port 1 Rx total oc tet count, inc luding bad packets.

0x101 Port1 Tx T otal Bytes Port 1 Tx total good octet c ount, including PAUSE packets.

0x102 Port 1 R x Drop Packets Port 1 Rx packets dropped due to lac k of resources.

0x103 Port1 Tx Drop Packets Port 1 Tx packets dropped due to lack of resources.

0x104 Port2 Rx Total Bytes Port 2 Rx total octet count, including bad packets.

0x105 Port2 Tx Total Bytes Port 2 Tx total good octet count , including PAUSE packets.

0x106 Port2 Rx Drop Packets Port 2 Rx packets dr opped due to lack of resources.

0x107 Port2 Tx Drop Packets Port 2 Tx packets dropped due to lack of resources.

0x108 Port3 Rx Total Bytes Port 3 Rx total octet count, including bad packets.

0x109 Port3 Tx Total Bytes Port 3 Tx total good octet count , including PAUSE packets.

0x10A Port3 Rx Drop Packets Port 3 Rx packets dropped due to lack of resour ces.

0x10B Port3 Tx Drop Packets Port 3 Tx packets dropped due to lack of resources.

0x10C Port4 Rx Total Bytes Port 4 Rx total octet c ount, including bad packets.

0x10D Port4 Tx Total Bytes Port 4 Tx total good octet c ount, including PAUSE packets.

0x10E Port4 Rx Drop Packets Port 4 Rx packets dropped due to lack of resour ces.

0x10F Port4 Tx Drop Packets Port 4 Tx packets dropped due to lack of r esources.

0x110 Port5 Rx Total Bytes Port 4 Rx total octet count, including bad packets.

0x111 Port5 Tx Total Bytes Port 4 Tx total good oct et count, including PAUSE packets.

0x112 Port5 Rx Drop Packets Port 4 Rx packets dropped due to lack of resources.

0x113 Port5 Tx Drop Packets Port 4 Tx packets dropped du e to lack of resources.

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Table 27. Format of Per Port RX/TX Total Bytes MIB Counter

Address Name Description Mode Default

Format of Per Port Total Byte MIB Counters

38 Overflow 1 = Counter over flow.

0 = No Counter over flow. RO 0

37 Count Valid 1 = Counter value is val id.

0 = Counter value is not valid. RO 0

36 Reserved N/A No Change RO 0

35-0 Counter V alues Counter value. RO 0

Table 28. Format of “All Dropped Packet” MIB Counter

Address Name Description Mode Default

Format of All Port Dropped P acket MIB Counters

38 Overflow 1 = Counter over flow.

0 = No Counter over flow. RO 0

37 Count Valid 1 = Counter value is val id.

0 = Counter value is not valid. RO 0

36-16 Reserved N/ A No Change RO All ‘0’

15-0 Counter V alues Counter value. RO 0

Note: All MIB counter per port are read clear.

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The KSZ8794CNX provides a total of 36 MIB counters per port. These counters are used to monitor the port activity for

network manageme nt and maintenance. These MIB counters are read using indirect memory access, per the following

examples.

Programming Examples:

(1) MIB counter read (read Port 1 Rx64Octets counter)

Write to Register 11 0 with 0x1c (read MIB counters selected)

Write to Register 11 1 with 0xd (trigger the read operation)

Then

Read Register 116 ( counter value [39:32])

// If bit [38] = 1, there was a counter overf low

Read Register 117 ( counter value [31:24])

Read Register 118 (counter value [23:16 ])

Read Register 119 (counter value [15:8])

Read Register 120 (counter value [7:0])

(2) MIB counter read (read Port 2 Rx64Octets counter)

Write to Register 11 0 with 0x1c (read MIB counter selected)

Write to Register 11 1 with 0x2d (trigger the read operation)

Then

Read Register 116 ( counter value [39:32])

// If bit [38] = 1, there was a counter overf low

Read Register 117 (counter value [31:24 ])

Read Register 118 (counter value [23:16 ])

Read Register 119 (counter value [15:8])

Read Register 120 (counter value [7:0])

(3) MIB counter read (read Port 1 TX drop packets)

Write to Register 11 0 with 0x1d

Write to Register 11 1 with 0x03

Then

Read Register 116 ( counter value [39:32])

// If bit [38] = 1, there was a counter overf low

Read Register 119 (counter value [15:8])

Read Register 120 (counter value [7:0])

Note:

To read out all the counters, the best performance over the SPI bus is (160+3) × 8 × 20 = 26us, where there are 160 registers, 3 overhead, 8 clocks per

access, at 50MHz. In the heaviest condition, the byte counter will overflow in 2 minutes. It is recommended that the software read all the counters at

least every 30 seconds. The all Port MIB counters are designed as “read clear.”

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MIIM Registers

All the registers defined in this section can be also accessed via the SPI interface. Note: different mapping mechanisms

are used for MIIM and SPI. The “PHYAD” defined in IEEE is assigned as “0x1” for Port 1, “0x2” for Port 2 and “0x3” for

Port 3. The “REGAD” sup port ed are 0x0-0x5 (0h-5h), 0x 1D (1dh) and 0x1F (1fh).

Address

Name

Description

Mode

Default

15 Soft Reset 1 = PHY soft reset.

0 = Normal operat i on. R/W

(SC) 0

14 Loop Back

1 = Perform MAC loopback, loop bac k path as follows:

Assume the loop-back is at Port 1 MAC, Port 2 is the monitor

port.

Port 1 MAC Loopback (Port 1 Reg. 0, bit [14] = 1’)

Start: RXP2/RXM2 (Port 2). Can also start from Ports 3, 4.

Loopback: M A C /PHY interfac e of Port 1’s MAC

End: TXP2/TXM2 (Port 2). Can also end at Ports 3, 4

respectively.

Setting address 0x3, 4 Reg. 0, bit [14] = ‘1’ will perform MAC

loopback on Ports 3, 4, respectively.

0 = Normal Oper ation.

R/W 0

13 Force 100 1 = 100Mbps.

0 = 10Mbps. R/W 1

12 AN Enable 1 = Auto-Negotiati on enabled.

0 = Auto-Negotiation disabled. R/W 1

11 Power Down 1 = Power down.

0 = Normal operat i on. R/W 0

10 PHY Isolate 1 = Electrical PHY isolation of PHY from Tx+/Tx-.

0 = Normal operat i on. R/W 0

9 Restart AN 1 = Restart Auto-Negotiation.

0 = Normal operat i on. R/W 0

8 Force F ul l D uplex 1 = Full duplex.

0 = Half duplex. R/W 1

7 Reserved Reserved RO 0

6 Reserved Reserved RO 0

5 Hp_mdix 1 = HP Auto-MDI/MDIX mode

0 = Micrel Auto-MDI/MDIX mode R/W 1

4 Force MDI 1 = MDI mode wh en disable Auto-MDI/MDIX.

0 = MDIX mode when di sable Auto-MDI/MDIX. R/W 0

3 Disable Auto MDI/MDI-X 1 = Disable Auto-MDI/MDIX.

0 = Enable Auto-MDI/MDIX. R/W 0

2 Disable far End fault 1 = D isable far end fault detection.

0 = Normal operat i on. R/W 0

1 Disable Transmit 1 = Di s able transmit.

0 = Normal operat i on. R/W 0

0 Disable LED 1 = Disable LED.

0 = Normal operat i on. R/W 0

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MIIM Registers (Continued)

Address

Name Description Mode Default

15 T4 Capable 0 = Not 100 BASET4 capable. RO 0

14 100 Full Cap able 1 = 100BASE-TX full -dup le x capa ble.

0 = Not capable of 100BASE-TX full-duplex. RO 1

13 100 Half Ca pable 1 = 100BASE-TX half-duple x capable.

0 = Not 100BASE-TX half-duple x capable. RO 1

12 10 Full Capa ble 1 = 10BASE-T full-d uplex capable.

0 = Not 10BASE-T full-duplex capable. RO 1

11 10 Half Cap able 1 = 10BASE-T half-duplex capable.

0 = 10BASE-T half-duplex capable. RO 1

10-7 Reserved Reserved RO 0

6 Reserved Reserved RO 0

5 AN Compl ete 1 = Auto-Negotiation compl ete.

0 = Auto-Negotiation not completed. RO 0

4 Far End f ault 1 = far end fault detected.

0 = No far end fault detected. RO 0

3 AN Capable 1 = Auto-Negotiation capable.

0 = Not Auto-Negotiation capable. RO 1

2 Link Stat us 1 = Link is up.

0 = Link is down. RO 0

1 Reserved Reserved RO 0

0 Extended Capable 0 = Not extended register capable. RO 0

15-0 Phyid High High order PHYID bits. RO 0x0022

15-0 Phyid Low Low order PHYI D bi ts. RO 0x1550

15 Reserved Reserved RO 0

14 Reserved Reserved RO 0

13 Reserved Reserved RO 0

12 Reserved Reserved RO 0

11 Reserved Reserved RO 1

10 Pause 1 = Advertise pause ability.

0 = Do not advert i s e pause ability. R/W 1

9 Reserved Reserved R/W 0

8 Adv 100 Full 1 = Advertise 100 full-duplex ability.

0 = Do not advert i s e 100 full-duplex ability. R/W 1

7 Adv 100 Half 1 = Advertise 100 half-duple x ability.

0 = Do not advert i s e 100 half-duple x a bility. R/W 1

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MIIM Registers (Co ntinued)

Address Name Description Mode Default

6 Adv 10 Full 1 = Advertise 10 full-duplex ability.

0 = Do not advertise 10 full-duplex ability. R/W 1

5 Adv 10 Half 1 = Advertise 10 half-duple x ability.

0 = Do not advertise 10 half-duplex ability. R/W 1

4-0 Selector Fi eld 802.3 RO 00001

15 Reserved Reserved RO 0

14 Reserved Reserved RO 0

13 Reserved Reserved RO 0

12-11 Reserved Reserved RO 0

10 Pause 1 = Li nk partner flow control capable.

0 = Link partner not flow control c apable. RO 0

9 Reserved Reserved RO 0

8 Adv 100 Full 1 = Link partner 100BT full-dupl ex capable.

0 = Link partner not 100BT full-duplex capabl e. RO 0

7 Adv 100 Half 1 = Link partner 100B T half-duplex capable.

0 = Link partner not 100BT half-duplex capable. RO 0

6 Adv 10 Full 1 = Link partner 10BT full-duplex capable.

0 = Link partner not 10BT full-duplex capable. RO 0

5 Adv 10 Half 1 = Link partner 10B T half-duplex capable.

0 = Link partner not 10BT half-duplex capabl e. RO 0

4-0 Reserved Reserved RO 00001

15 CDT_Enable

Note: CDT means Cable

Diagnostic Test

1 = Enable cable diagnostic. After CDT test has completed, this

bit will be self-cleared.

0 = Indicates cable diagnostic test (if enabled) has completed

and the status i nformation is vali d for reading.

R/W

(SC) 0

14-13 CDT_Result

00 = Normal condition

01 = Open condition detected in cable

10 = Short condition detecte d in cable

11 = Cable dia gnostic test has failed

RO 00

12 CDT 10M Short 1 = Less than 10 meter short RO 0

11-9 Reserved Reserved RO 0

8-0 CDT_Fault_Count Dist ance to the fault.

It’s approximately 0.4m*CDT_Fault_Count[8:0] RO 000000000

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MIIM Registers (Co ntinued)

Address Name Description Mode Default

15-11 Reserved RO 0000000000

10-8 Port Operation Mode

Indication

Indicate the c urrent state of port operati on mode:

000 = Reserved

001 = still in auto-negotiation

010 = 10BASE-T half duple x

011 = 100BASE-TX half duplex

100 = Reserved

101 = 10BASE-T full duplex

110 = 100BASE-TX full duple x

111 = PHY/MII isolate

RO 001

7-6 Reserved N/A , don’t change R/W 00

5 Polrvs 1 = Polarity is reversed

0 = Polarity is not reversed RO 0

4 MDI-X status 1 = MDI

0 = MDI-X RO 0

3 Force_lnk 1 = Force link pass

0 = Normal operat i on R/W 0

2 Pwrsave 1 = Enable power save

0 = Disable power save R/W 0

1 Remote Loopback

1 = Perform Rem ote loopback, loop back path as follows:

Port 1 (PHY ID address 0x1 Reg. 1fh, bit [1] = ‘1’)

Start: RXP1/RXM1 (Port 1)

Loopback: PMD/PMA of Port 1’s PHY

End: TXP1/TXM1 (Port 1)

Setting PHY I D address 0x2, 3, 4 Reg. 1fh

bit [1] = ‘1’, will perform rem ote loopback on Port 2, 3,

0 = Normal Oper ation.

R/W 0

0 Reserved Reserved RO 0

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Absolute Ma xi mu m Ratings(6)

Supply Voltage

(VDD12A, VDD12D) ...................................... –0.5V to +1.8V

(VDDAT, VDDIO) ......................................... –0.5V to +4.0V

Input Voltage ................................................ –0.5V to +4.0V

Output Voltage ............................................. –0.5V to +4.0V

Lead Temperature (soldering, 10 sec.) ...................... 260°C

Storage Temperature (TS) ......................... –55°C to +150°C

Max Junction Temperatur e (TJ) .................................. 125°C

HBM ESD Rating .......................................................... 5KV

Operating Ratings(7)

Supply Voltage

(VDD12A, VDD12D) .................................. 1.140V to 1.260V

(VDDAT) ................................................ 3.135V to 3.465V

(VDDIO @ 3.3V) ................................... 3.135V to 3.465V

(VDDIO @ 2.5V) ................................... 2.375V to 2.625V

(VDDIO @ 1.8V) ................................... 1.710V to 1.890V

Ambient Temperature (TA)

Commercial ............................................. –0°C to +70°C

Industrial ............................................... –40°C to +85°C

Package Thermal R esistance(8)

Thermal Resistance (θJA) ............................. 31.96°C/W

Thermal Resistance (θJC) ............................ 13.54°C/W

Electric al Characteristics(9,10)

VIN = 1.2V/3.3V; TA = 25°C.

Symbol Parameter Condition Min Typ Max Units

100BASE-TX Operation—Al l Po rts 100% Utilization

IDX 100BASE-TX (Transmitter) 3.3V Analog VDDAT 107 mA

ID12 100BASE-TX 1.2V VDD12A + VDD12D 35 mA

IDDIO 100BASE-TX (Digital IO) 3.3V Digital VDDIO 11 mA

10BASE-T Operation —All Ports 100% Utilization

IDX 10BASE-T (Transmitter) 3.3V Analog VDDAT 110 mA

ID12 10BASE-T 1.2V VDD12A + VDD12D 29 mA

IDDIO 10BASE-T (Digital IO) 3.3V Digital VDDIO 11 mA

Auto-Negotiation Mode

IDX 3.3V Analog VDDAT 51 mA

ID12 1.2V Analog/Digit al VDD12A + VDD12D 34 mA

IDDIO 3.3V D igital VDDIO 11 mA

Power Man agement Mode

ISPDM1 Soft Power Do wn Mode 3.3V VDDAT + VDDIO 0.23 mA

ISPDM2 Soft Power Do wn Mode 1.2V VDD12A + VDD12D 0.17 mA

IEDM1 Energy Detect Mode (EDPD) 3.3V VDDAT + VDDIO 20 mA

IEDM2 Energy Detect Mode (EDPD) 1.2V VDD12A + VDD12D 27 mA

IEEE1 100BT EE E Mode at Idle 3.3V VDDAT + VDDIO 20 mA

IEEE2 100BT EE E Mode at Idle 1.2V VDD12A + VDD12D 27 mA

CMOS Inputs

VIH Input High Voltage

VDDIO=3.3V 2.0 V

VDDIO=2.5V 1.8 V

VDDIO=1.8V 1.3 V

VIL Input Low Voltage

VDDIO=3.3V 0.8 V

VDDIO=2.5V 0.7 V

VDDIO=1.8V 0.5 V

IIN Input Current (Excluding Pull-up/Pull-down) VIN = GND ~ VDDIO 10 µA

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Electric al Characteristics (Continued)

VIN = 1.2V/3.3V; TA = 25°C.

Symbol Parameter Condition Min Typ Max Units

CMOS Outputs

VOH Output High Voltage

VDDIO=3.3V 2.4 V

VDDIO=2.5V 2.0 V

VDDIO=1.8V 1.5 V

VOL Output Low Voltage

VDDIO=3.3V 0.4 V

VDDIO=2.5V 0.4 V

VDDIO=1.8V 0.3 V

IOZ Output Tri-S tate Leakage VIN = GND ~ VDDIO 10 µA

100BASE-TX T ransmit (measured differentially after 1:1 transformer)

VO Peak Differential Output Vol tage

100Ω termination on the

differential output

0.95 1.05 V

VIMB Output Voltage Imbalance

100Ω termination on the

differential output

2 %

tr tt Rise/fall Time 3 5 ns

Rise/fall T i m e Imbalance 0 0.5 ns

Duty Cycle Dis tortion ±0.5 ns

Overshoot 5 %

Output Jitters Peak-to-peak 0 0.75 1.4 ns

10BASE-T Re ceive

VSQ Squelch Thr es hold 5MHz square wave 300 400 585 mV

10BASE-T Transmit (measured differentially after 1:1 transformer)

VDDAT = 3.3V

VP Peak Differe ntial Output Vol tage

100Ω termination on the

differential output

2.2 2.5 2.8 V

Output Jitters Peak-to-peak 1.4 3.5 ns

Rise/fall Times 28 30 ns

I/O Pin Internal Pull-Up and Pull-Down Resistance

R1.8PU I/O Pin Effective Pull-Up Resistance VDDIO = 1.8V 75 95 135 kΩ

R1.8PD I/O Pin Effective Pull-Down Resistanc e VDDIO = 1.8V 53 68 120 kΩ

R2.5PU I/O Pin Effective Pull-Up Resistance VDDIO = 2.5V 46 60 93 kΩ

R2.5PD I/O Pin Effective Pull-Down Resistanc e VDDIO = 2.5V 46 59 103 kΩ

R3.3PU I/O Pin Effecti ve Pull -Up Resist anc e VDDIO = 3.3V 35 45 65 kΩ

R3.3PD I/O Pin Effective Pull-Down Resistanc e VDDIO = 3.3V 37 46 74 kΩ

Notes:

6. Exceeding the absolute maximum rating may damage the device.

7. The device is not guaranteed to function outside its operating rating. Unused inputs must always be tied to an appropriate logic voltage level (ground

or VDD).

8. No heat spreader in package. The thermal junction to ambient (θJA) and the thermal junction to case (θJC) are under air velocity 0m/s.

9. Specification for packaged product only. There is no an additional transformer consumption due to use on chip termination technology with internal

biasing for 10Base-T and 100Base-TX. The test condition is in port 4 RGMII mode (default).

10. Measurements were taken with operating ratings.

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Timing Diagrams

RGMII Timing

The RGMII timing conf orms to the timing requi rements in the RGMII Version 2.0 Specificat ion.

Figure 14. RGMII v2.0 Specification (Figure3-Multiplexing and Tim i ng Diagram )

Table 29. RGMII v2.0 Specification (Timing Specifics from Table 2)

Symbol Parameter Min Typ Max Units

TskewT Data to clock output skew (at transmitter) *NOTE 11 -500 0 500 ps

TskewR Data to clock input skew (at receiv er )

*NOTE 11

1 2.6 ns

Tcyc Clock Cycle Duration *NOTE 12 7.2 8 8.8 ns

Duty_G Duty Cycle for Gigabit 45 50 55 %

Duty_T Duty Cycle for 10/100T 40 50 60 %

Tr / Tf Rise / Fall Time (20-80%) 0.75 ns

Note:

11. RGMII V2.0 add internal delay (RGMII-ID) option to match the clocks timing for the transmit and the receiving.

12. For 10Mbps and 100Mbps, Tcyc will scale to 400ns+/-40ns and 40ns+/-4ns.

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MII Timing

Figure 15. MAC Mode MII Timing – Data Received from MII

Figure 16. MAC Mode MII Timing – Data Transmitted from MI I

Table 30. MAC Mode MII Timing Parameters

10Base-T/100Base-TX

Symbol Parameter Min Typ Max Units

tCYC3 Clock Cycle 400/40 ns

tS3 Set-Up Time 2 ns

tH3 Hold Time 2 ns

tOV3 Output Valid 3 8 10 ns

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Figure 17. PHY Mode MII Timing – Data Recei ved fro m MII

Figure 18. PHY Mode MII Timing – Data Transmitted from MII

Table 31. PHY Mode MII Timing Parameters

10BaseT/100BaseT

Symbol Parameter Min Typ Max Units

tCYC4 Clock Cycle 400/40 ns

tS4 Set-Up Time 10 ns

tH4 Hold Time 0 ns

tOV4 Output Valid 16 20 25 ns

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RMII Timing

Figure 19. RMII Timing – Data Received from RMII

Figure 20. RMII Timing – Data Transmitted to RMII

Table 32. RMII T iming Parameters

Timing Parameter Description Min Typ Max Unit

tcyc Clock cycle 20 ns

t1 Setup time 4 ns

t2 Hold time 2 ns

tod Output delay 3 10 ns

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SPI Timing

Figure 21. SPI Input Timing

Table 33. SPI Input Timing Parameters

Symbol Parameter Min Typ Max Units

fC Clock Frequency 50 MHz

tCHSL SPIS_N Inacti ve Hold Tim e 2 ns

tSLCH SPIS_N Active Set-Up Time 4 ns

tCHSH SPIS_N Active Hold Time 2 ns

tSHCH SPIS_N Inactive Set-Up Time 4 ns

tSHSL SPIS_N Deselect Time 10 ns

tDVCH Data Input Set-Up Time 4 ns

tCHDX Data Input Hold Time 2 ns

tCLCH Clock Rise Time 1 us

tCHCL Clock fall Time 1 us

tDLDH Dat a Input Rise T ime 1 us

tDHDL Data Input fall Time 1 us

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Auto-Negotiation Timing

Figure 22. Auto-Negotiation Timing

Table 34. Auto-Negotiation Timi ng Parameters

Symbols Parameters Min Typ Max Units

tBTB FLP burst to FLP burst 8 16 24 ms

tFLPW FLP burst width 2 ms

tPW Clock/Data pulse width 100 ns

tCTD Clock pulse to Data pulse 55.5 64 69.5 µs

tCTC Clock pulse to Clock pulse 111 128 139 µs

Number of Clo ck/Data pulse per bur st 17 33

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MDC/MDIO Timing

Figure 23. MDC/MDIO Timing

Table 35. MDC/MDIO Typical Timing Parameters

Timing Parameter Description Min Typ Max Unit

fC Clock Frequenc y 2.5 25 MHz

tP MDC period 400 ns

t1MD1 MDIO (PHY i nput) setup to rising edge of MDC 10 ns

tMD2 MDIO (PHY i nput) hold from ris i ng edge of MDC 4 ns

tMD3 MDIO (PHY output) delay fro m rising edge of M DC 5 ns

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Power-down/Power-up and Reset Timing

Figure 24. Reset Timing

Table 36. Reset Timing Parameters

Symbol Parameter Min Typ Max Units

tSR S table Supply Volt ages to Reset Hi gh 10 ms

tCS Configuration Set-Up Time 5 ns

tCH Configuration Hol d Time 5 ns

tRC Res et to Strap-In Pin O utput 6 ns

tvr 3.3V rise time 200 us

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Reset Circuit Diagram

Micrel recommends the following discrete reset circuit as shown in Figure 28 when powering up the KS8795 device.

For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), we recommend

the reset circuit as shown in Figure 29.

Figure 25. Recommended Reset Circuit

Figure 26. Recommended Circuit for Interfacing with CPU/FPGA Reset

At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the Micrel device. The reset out

RST_OUT_n from CPU/FPGA provides the warm reset after power up.

10k

10µF

KS8794

RST

D1: 1N4148

10k

10µF

CPU/FPGA

RST_OUT_n

KS8794

RST

D1, D2: 1N4148

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Selection of Isolation Transformer(13)

One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common-

mode choke is recommended for exceeding FCC requirements at line side. Request to separate the center taps of

RX/TX at chip side. The following table gives recommended transformer characteristics.

Table 37. Transformer Selection Criteria

Characteristics Name Value Test Condition

Turns Ratio 1 CT : 1 CT

Open-Circuit Inductance (min.) 350µH 100mV, 100kH z, 8mA

Insertion Loss (max.) 1.1dB 0.1MHz to 100MHz

HIPOT (min.) 1500Vrms

Note:

13. The IEEE 802.3u standard for 100BASE-TX assumes a transformer loss of 0.5dB. For the transmit line transformer, insertion loss of up to

1.3dB can be compensated by increasing the line drive current by means of reducing the ISET resistor value.

14. The center taps of RX and TX should be isolated for the low power consumption.

The following transformer vendors prov ide compatible magnetic parts for Mi crel’s device:

Table 38. Qualified Magnetic Vendors

Vendors and Parts Auto

MDIX Number

of Ports Vendors and Parts Auto

MDIX Number of

Ports

Pulse H1164NL Yes 4 Pulse H1102 Yes 1

YCL PH406082 Yes 4 Bel Fuse S558-5999-U7 Yes 1

TDK TLA-6T718A Yes 1 YCL PT163020 Yes 1

LanKom LF-H41S Yes 1 Transpower HB726 Yes 1

Datatronic NT79075 Yes 1 Delta LF8505 Yes 1

Selection of Refer ence Crystal

Table 39. T ypical Reference C rystal Charact eristics

Characteristics Value Units

Frequency 25.00000 MHz

Frequency tol erance (max) <= ±50 ppm

Load capacitance (max)

Note: Typical value varies per specific crystal spec.

27 pF

Series resistance (max ESR) 40 Ω

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Package I nformation

Figure 27. 64-Pin (8mm x 8mm) QFN Package

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MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com

Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This

information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,

specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability

whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties

relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product

can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical

implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a

significant injury to the user. A

Purchaser’s use or sale of Micrel Products for use in life support appliances,

devices or systems is a Purchaser’s own risk and Purchaser agrees to fully

indemnify Micrel for any damages resulting from such use or sale.

July 24, 2014 154 Revision 1.0