SCBS703I − AUGUST 1997 − REVISED OCT OBER 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DSupport Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC)
DSupport Unregulated Battery Operation
Down to 2.7 V
DTypical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
DIoff and Power-Up 3-State Support Hot
Insertion
DBus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
DLatch-Up Performance Exceeds 500 mA Per
JESD 17
DESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
SN54LVTH125 ...J OR W PACKAGE
SN74LVTH125 . . . D, DB, DGV, NS,
OR PW PACKAGE
(TOP VIEW)
SN54LVTH125 . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OE
1A
1Y
2OE
2A
2Y
GND
VCC
4OE
4A
4Y
3OE
3A
3Y
3212019
910111213
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3OE
1Y
NC
2OE
NC
2A
1A
1OE
NC
3Y
3A V
4OE
2Y
GND
NC CC
NC − No internal connection
SN74LVTH125 . . . RGY PACKAGE
(TOP VIEW)
114
78
2
3
4
5
6
13
12
11
10
9
4OE
4A
4Y
3OE
3A
1A
1Y
2OE
2A
2Y
1OE
3Y V
GND
CC
description/ordering information
These bus buffers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to
provide a TTL interface to a 5-V system environment.
The ’LVTH125 devices feature independent line drivers with 3-state outputs. Each output is in the
high-impedance state when the associated output-enable (OE) input is high.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
QFN − RGY Tape and reel SN74LVTH125RGYR LXH125
SOIC − D
Tube SN74LVTH125D
LVTH125
SOIC − D Tape and reel SN74LVTH125DR LVTH125
−40°C to 85°C
SOP − NS Tape and reel SN74LVTH125NSR LVTH125
−40°C to 85°CSSOP − DB Tape and reel SN74LVTH125DBR LXH125
TSSOP − PW
Tube SN74LVTH125PW
LXH125
TSSOP − PW Tape and reel SN74LVTH125PWR LXH125
TVSOP − DGV Tape and reel SN74LVTH125DGVR LXH125
CDIP − J Tube SNJ54LVTH125J SNJ54LVTH125J
−55°C to 125°CCFP − W Tube SNJ54LVTH125W SNJ54LVTH125W
−55 C to 125 C
LCCC − FK Tube SNJ54LVTH125FK SNJ54LVTH125FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright 2003, Texas Instruments Incorporated
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCBS703I − AUGUST 1997 − REVISED OCT OBER 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
When V CC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
OE A
OUTPUT
Y
L H H
LLL
H X Z
logic diagram (positive logic)
1
1OE
2
1A 1Y
3
4
2OE
5
2A 2Y
6
10
3OE
9
3A 3Y
8
13
4OE
12
4A 4Y
11
Pin numbers shown are for the D, DB, DGV, J, NS, PW, RGY, and W packages.
SCBS703I − AUGUST 1997 − REVISED OCT OBER 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state, VO (see Note 1) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . .
Current into any output in the low state, IO: SN54LVTH125 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74LVTH125 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the high state, IO (see Note 2): SN54LVTH125 48 mA. . . . . . . . . . . . . . . . . . . . . . .
SN74LVTH125 64 mA. . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA(see Note 3): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): DGV package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 4): RGY package 47°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 5)
SN54LVTH125 SN74LVTH125
UNIT
MIN MAX MIN MAX
UNIT
VCC Supply voltage 2.7 3.6 2.7 3.6 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIInput voltage 5.5 5.5 V
IOH High-level output current −24 −32 mA
IOL Low-level output current 48 64 mA
∆t/∆vInput transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆VCC Power-up ramp rate 200 200 µs/V
TAOperating free-air temperature −55 125 −40 85 °C
NOTE 5: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SCBS703I − AUGUST 1997 − REVISED OCT OBER 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54LVTH125 SN74LVTH125
UNIT
PARAMETER
TEST CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
VIK VCC = 2.7 V, II = −18 mA −1.2 −1.2 V
VCC = 2.7 V to 3.6 V, IOH = −100 µA VCC−0.2 VCC−0.2
VOH
VCC = 2.7 V, IOH = −8 mA 2.4 2.4
V
VOH
VCC = 3 V
IOH = −24 mA 2V
VCC = 3 V IOH = −32 mA 2
VCC = 2.7 V
IOL = 100 µA 0.2 0.2
VCC = 2.7 V IOL = 24 mA 0.5 0.5
VOL
IOL = 16 mA 0.4 0.4
V
VOL
VCC = 3 V
IOL = 32 mA 0.5 0.5 V
VCC = 3 V IOL = 48 mA 0.55
IOL = 64 mA 0.55
VCC = 0 or 3.6 V, VI = 5.5 V 10 10
II
Control
inputs VCC = 3.6 V, VI = VCC or GND ±1±1
µA
II
Data inputs
VCC = 3.6 V
VI = VCC 1 1
µA
Data inputs VCC = 3.6 V VI = 0 −5 −5
Ioff VCC = 0, VI or VO = 0 to 4.5 V ±100 µA
VCC = 3 V
VI = 0.8 V 75 75
I
I(hold)
Data inputs VCC = 3 V VI = 2 V −75 −75 µA
II(hold)
Data inputs
VCC = 3.6 V‡, VI = 0 to 3.6 V ±500
µA
IOZH VCC = 3.6 V, VO = 3 V 5 5 µA
IOZL VCC = 3.6 V, VO = 0.5 V −5 −5 µA
IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
OE = don’t care ±50∗±50 µA
IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
OE = don’t care ±50∗±50 µA
VCC = 3.6 V,
Outputs high 0.12 0.19 0.12 0.19
I
CC
VCC = 3.6 V,
I
O
= 0,
V = V or GND
Outputs low 4.5 7 4.5 7 mA
ICC
IO = 0,
VI = VCC or GND Outputs disabled 0.12 0.19 0.12 0.19
mA
∆ICC§VCC = 3 V to 3.6 V, One input at VCC − 0.6 V,
Other inputs at VCC or GND 0.3 0.2 mA
CiVI = 3 V or 0 4 4 pF
CoVO = 3 V or 0 6.5 6.5 pF
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
†All typical values are at VCC = 3.3 V, TA = 25°C.
‡This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
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SCBS703I − AUGUST 1997 − REVISED OCT OBER 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN54LVTH125 SN74LVTH125
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC = 3.3 V
± 0.3 V VCC = 2.7 V VCC = 3.3 V
± 0.3 V VCC = 2.7 V UNIT
(INPUT)
(OUTPUT)
MIN MAX MIN MAX MIN TYP†MAX MIN MAX
tPLH
A
Y
1 4.2 4.7 1 2 3.5 4.5
ns
tPHL A Y 1 4.1 5.1 1 2.1 3.9 4.9 ns
tPZH
OE
Y
1 4.9 5.6 1 2 4 5.5
ns
tPZL OE Y1.1 4.9 5.6 1.1 2.1 4 5.4 ns
tPHZ
OE
Y
1.5 5.3 5.9 1.5 2.3 4.5 5.7
ns
tPLZ OE Y1.3 4.7 4.2 1.3 2.8 4.5 4 ns
†All typical values are at VCC = 3.3 V, TA = 25°C.
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SCBS703I − AUGUST 1997 − REVISED OCT OBER 2003
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
6 V
Open
GND
500 Ω
500 Ω
Data Input
Timing Input 2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
2.7 V
0 V
Input Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
3 V
0 V
VOL + 0.3 V
VOH − 0.3 V
≈0 V
2.7 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6 V
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns
.
D. The outputs are measured one at a time with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN74LVTH125D ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH125DBR ACTIVE SSOP DB 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH125DBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH125DBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH125DE4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH125DG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH125DGVR ACTIVE TVSOP DGV 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH125DGVRE4 ACTIVE TVSOP DGV 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH125DGVRG4 ACTIVE TVSOP DGV 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH125DR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH125DRE4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH125DRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH125NSR ACTIVE SO NS 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH125NSRE4 ACTIVE SO NS 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH125NSRG4 ACTIVE SO NS 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH125PW ACTIVE TSSOP PW 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH125PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH125PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH125PWR ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH125PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH125PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH125RGYR ACTIVE VQFN RGY 14 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN74LVTH125RGYRG4 ACTIVE VQFN RGY 14 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
PACKAGE OPTION ADDENDUM
www.ti.com 21-Dec-2009
Addendum-Page 1
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVTH125 :
•Enhanced Product: SN74LVTH125-EP
NOTE: Qualified Version Definitions:
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
PACKAGE OPTION ADDENDUM
www.ti.com 21-Dec-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVTH125DBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
SN74LVTH125DGVR TVSOP DGV 14 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1
SN74LVTH125DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVTH125DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVTH125NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74LVTH125PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVTH125RGYR VQFN RGY 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVTH125DBR SSOP DB 14 2000 367.0 367.0 38.0
SN74LVTH125DGVR TVSOP DGV 14 2000 367.0 367.0 35.0
SN74LVTH125DR SOIC D 14 2500 333.2 345.9 28.6
SN74LVTH125DR SOIC D 14 2500 367.0 367.0 38.0
SN74LVTH125NSR SO NS 14 2000 367.0 367.0 38.0
SN74LVTH125PWR TSSOP PW 14 2000 367.0 367.0 35.0
SN74LVTH125RGYR VQFN RGY 14 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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