SBFS019A – JANUARY 1988 — REVISED OCTOBER 2003
www.ti.com
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1998-2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
MPC508A
MPC509A
FUNCTIONAL DIAGRAMS
Single-Ended 8-Channel/Differential 4-Channel
CMOS ANALOG MULTIPLEXERS
FEATURES
●ANALOG OVERVOLTAGE PROTECTION: 70VPP
●NO CHANNEL INTERACTION DURING
OVERVOLTAGE
●BREAK-BEFORE-MAKE SWITCHING
●ANALOG SIGNAL RANGE: ±15V
●STANDBY POWER: 7.5mW typ
●TRUE SECOND SOURCE
Level
Shift
1kΩ
1kΩ
1kΩ
Overvoltage
Clamp and
Signal
Isolation
5V
Ref
Decoder/
Driver
NOTE: (1) Digital
Input Protection.
In 1A
In 1B
In 4B
MPC509A A
0
A
1
EN
Out A
1kΩ
In 4A
Out B
(1) (1) (1)
Level
Shift
1kΩ
1kΩ
1kΩ
Overvoltage
Clamp and
Signal
Isolation
5V
Ref
Decoder/
Driver
NOTE: (1) Digital
Input Protection.
In 1
In 2
In 8
MPC508A A0A1A2EN
(1)
Out
(1) (1) (1)
DESCRIPTION
The MPC508A is an 8-channel single-ended analog
multiplexer and the MPC509A is a 4-channel differential
multiplexer.
The MPC508A and MPC509A multiplexers have input
overvoltage protection. Analog input voltages may exceed
either power supply voltage without damaging the device or
disturbing the signal path of other channels. The protection
circuitry assures that signal fidelity is maintained even under
fault conditions that would destroy other multiplexers. Analog
inputs can withstand 70VPP signal levels and standard ESD
tests. Signal sources are protected from short circuits should
multiplexer power loss occur; each input presents a 1kΩ
resistance under this condition. Digital inputs can also sustain
continuous faults up to 4V greater than either supply voltage.
These features make the MPC508A and MPC509A ideal for
use in systems where the analog signals originate from
external equipment or separately powered sources.
The MPC508A and MPC509A are fabricated with Burr-
Brown’s dielectrically isolated CMOS technology. The
multiplexers are available in plastic DIP and plastic SOIC
packages. Temperature range is –40°C to +85°C.
MPC508
MPC509
MPC508A, MPC509A
2SBFS019A
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ELECTRICAL CHARACTERISTICS
Supplies = +15V, –15V; VAH (Logic Level High) = +4.0V, VAL (Logic Level Low) = +0.8V, unless otherwise specified.
MPC508A/509A
PARAMETER TEMP MIN TYP MAX UNITS
ANALOG CHANNEL CHARACTERISTICS
VS, Analog Signal Range Full –15 +15 V
RON, On Resistance(1) +25°C 1.3 1.5 kΩ
Full 1.5 1.8 kΩ
IS (OFF), Off Input Leakage Current +25°C 0.5 nA
Full 10 nA
ID (OFF), Off Output Leakage Current +25°C 0.2 nA
MPC508A Full 5 nA
MPC509A Full 5 nA
ID (OFF) with Input Overvoltage Applied(2) +25°C 2.0 µA
ID (ON), On Channel Leakage Current +25°C2nA
MPC508A Full 10 nA
MPC509A Full 10 nA
IDIFF Differential Off Output Leakage Current
(MPC509A Only) Full 10 nA
DIGITAL INPUT CHARACTERISTICS
VAL, Input Low Threshold Drive Full 0.8 V
VAH, Input High Threshold(3) Full 4.0 V
IA, Input Leakage Current (High or Low)(4) Full 1.0 µA
SWITCHING CHARACTERISTICS
tA, Access Time +25°C 0.5 µs
Full 0.6 µs
tOPEN, Break-Before-Make Delay +25°C2580 ns
tON (EN), Enable Delay (ON) +25°C 200 ns
Full 500 ns
tOFF (EN), Enable Delay (OFF) +25°C 250 ns
Full 500 ns
Settling Time (0.1%) +25°C 1.2 µs
(0.01%) +25°C 3.5 µs
"OFF Isolation"(5) +25°C5068 dB
CS (OFF), Channel Input Capacitance +25°C5pF
CD (OFF), Channel Output Capacitance: MPC508A +25°C25pF
MPC509A +25°C12pF
CA, Digital Input Capacitance 25°C5pF
CDS (OFF), Input to Output Capacitance +25°C 0.1 pF
POWER REQUIREMENTS
PD, Power Dissipation Full 7.5 mW
I+, Current Pin 1(6) Full 0.7 1.5 mA
I–, Current Pin 27(6) Full 5 20 µA
NOTES: (1) VOUT = ±10V, IOUT = –100µA. (2) Analog overvoltage = ±33V. (3) To drive from DTL/TTL circuits. 1kΩ pull-up resistors to +5.0V supply are recommended.
(4) Digital input leakage is primarily due to the clamp diodes. Typical leakage is less than 1nA at 25°C. (5) VEN = 0.8V, RL = 1kΩ, CL = 15pF, VS = 7Vrms, f = 100kHz.
Worst-case isolation occurs on channel 4 due to proximity of the output pins. (6) VEN, VA = 0V or 4.0V.
MPC508A, MPC509A 3
SBFS019A www.ti.com
PIN CONFIGURATIONS
TRUTH TABLES
"ON"
A2A1A0EN CHANNEL
X X X L None
LLLH1
LLHH2
LHLH3
LHHH4
HLLH5
HLHH6
HHLH7
HHHH8
MPC508A MPC509A
"ON"
CHANNEL
A1A0EN PAIR
X X L None
LLH1
LHH 2
HLH 3
HHH 4
Voltage between supply pins ............................................................... 44V
V+ to ground ........................................................................................ 22V
V– to ground ........................................................................................ 25V
Digital input overvoltage VEN, VA:
VSUPPLY (+) ................................................... +4V
VSUPPLY (–) ................................................... –4V
or 20mA, whichever occurs first.
Analog input overvoltage VS:
VSUPPLY (+) ................................................ +20V
VSUPPLY (–) ................................................ –20V
Continuous current, S or D ............................................................... 20mA
Peak current, S or D
(pulsed at 1ms, 10% duty cycle max) ............................................ 40mA
Power dissipation(2) .......................................................................... 1.28W
Operating temperature range ........................................... –40°C to +85°C
Storage temperature range............................................. –65°C to +150°C
NOTE: (1) Absolute maximum ratings are limiting values, applied individu-
ally, beyond which the serviceability of the circuit may be impaired. Func-
tional operation under any of these conditions is not necessarily implied.
(2) Derate 1.28mW/°C above TA = +70°C.
ABSOLUTE MAXIMUM RATINGS(1)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A
0
En
–V
SUPPLY
In 1
In 2
In 3
In 4
Out
A
1
A
2
Ground
+V
SUPPLY
In 5
In 6
In 7
In 8
Top View
MPC508A (Plastic)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A
0
En
–V
SUPPLY
In 1A
In 2A
In 3A
In 4A
Out A
A
1
Ground
+V
SUPPLY
In 1B
In 2B
In 3B
In 4B
Out B
Top View
MPC509 A (Plastic)
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see
the Package Option Addendum located at the end of this
data sheet.
MPC508A, MPC509A
4SBFS019A
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COMBINED CMR vs
FREQUENCY MPC509A AND INA110
120
100
80
60
40
20
01 10 100 1k 10k
Fre
q
uenc
y
(
Hz
)
Common-Mode Rejection (dB)
G = 500
G = 100
G = 10
CROSSTALK vs SIGNAL FREQUENCY
1
0.1
0.01
0.001
0.0001 110
100 1k 10k
Si
g
nal Frequency (Hz)
Crosstalk (% of Off Channel Signal)
Rs = 100kΩ
Rs = 1kΩRs = 100Ω
Rs = 10kΩ
SETTLING TIME vs
SOURCE RESISTANCE FOR 20V STEP CHANGE
1k
100
10
1
0.10.01 0.1 110 100
Source Resistance (kΩ)
Settling Time (µs)
To ±0.01%
To ±0.1%
TYPICAL PERFORMANCE CURVES
Typical at +25°C unless otherwise noted.
MPC508A, MPC509A 5
SBFS019A www.ti.com
Differential Multiplexer Static Accuracy
Static accuracy errors in a differential multiplexer are diffi-
cult to control, especially when it is used for multiplexing
low-level signals with full-scale ranges of 10mV to 100mV.
The matching properties of the multiplexer, source and
output load play a very important part in determining the
transfer accuracy of the multiplexer. The source impedance
unbalance, common-mode impedance, load bias current mis-
match, load differential impedance mismatch, and common-
mode impedance of the load all contribute errors to the
multiplexer. The multiplexer ON resistance mismatch, leak-
age current mismatch and ON resistance also contribute to
differential errors.
The effects of these errors can be minimized by following the
general guidelines described in this section, especially for
low-level multiplexing applications. Refer to Figure 2.
Load (Output Device) Characteristics
•Use devices with very low bias current. Generally, FET
input amplifiers should be used for low-level signals less
than 50mV FSR. Low bias current bipolar input amplifi-
ers are acceptable for signal ranges higher than 50mV
FSR. Bias current matching will determine the input
offset.
• The system dc common-mode rejection (CMR) can never
be better than the combined CMR of the multiplexer and
driven load. System CMR will be less than the device
which has the lower CMR figure.
• Load impedances, differential and common-mode, should
be 1010Ω or higher.
DISCUSSION OF
PERFORMANCE
DC CHARACTERISTICS
The static or dc transfer accuracy of transmitting the multi-
plexer input voltage to the output depends on the channel ON
resistance (RON), the load impedance, the source impedance,
the load bias current and the multiplexer leakage current.
Single-Ended Multiplexer Static Accuracy
The major contributors to static transfer accuracy for single-
ended multiplexers are:
Source resistance loading error;
Multiplexer ON resistance error;
and, dc offset error caused by both load bias current and
multiplexer leakage current.
Resistive Loading Errors
The source and load impedances will determine the input
resistive loading errors. To minimize these errors:
•Keep loading impedance as high as possible. This mini-
mizes the resistive loading effects of the source resis-
tance and multiplexer ON resistance. As a guideline, load
impedances of 108Ω, or greater, will keep resistive load-
ing errors to 0.002% or less for 1000Ω source imped-
ances. A 106Ω load impedance will increase source
loading error to 0.2% or more.
•Use sources with impedances as low as possible. 1000Ω
source resistance will present less than 0.001% loading
error and 10kΩ source resistance will increase source
loading error to 0.01% with a 108 load impedance.
Input resistive loading errors are determined by the follow-
ing relationship (see Figure 1).
Source and Multiplexer Resistive Loading Error
∈+ = +
++
×() %RR RR
RR R
SON SON
SONL
100
where RS = source resistance
RL = load resistance
RON = multiplexer ON resistance
Input Offset Voltage
Bias current generates an input OFFSET voltage as a result
of the IR drop across the multiplexer ON resistance and
source resistance. A load bias current of 10nA will generate
an offset voltage of 20µV if a 1kΩ source is used. In general,
for the MPC508A, the OFFSET voltage at the output is
determined by:
VOFFSET = (IB + IL) (RON + RS)
where IB = Bias current of device multiplexer is driving
IL = Multiplexer leakage current
RON = Multiplexer ON resistance
RS = source resistance
Z
L
R
S4A
R
S48
R
OFF4A
R
OFF4B
C
CM
R
S1
R
S1B
R
ON1A
R
ON1B
I
L
Cd/2
Cd/2
R
CM
Rd/2
Rd/2
I
BIAS A
I
BIAS B
R
CM4
R
CM1
V
S1
V
S8
I
LB
FIGURE 2. MPC509A DC Accuracy Equivalent Circuit.
RS1
RS8
RON
ROFF
VS1
VS8 ZL
Measured
Voltage
IL
VM
IBIAS
FIGURE 1. MPC508A DC Accuracy Equivalent Circuit.
MPC508A, MPC509A
6SBFS019A
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Source
Node A
CSB
RSA
ZCM
CdA
CdB
CSA
RSB
RCMS
CCMS
Node B
MPC509A
Channel
RdA
RdB
Load
Load
Source Node A
C
S
R
S
R
L
C
L
MPC508A Channel
Source Characteristics
•The source impedance unbalance will produce offset,
common-mode and channel-to-channel gain-scatter er-
rors. Use sources which do not have large impedance
unbalances if at all possible.
•Keep source impedances as low as possible to minimize
resistive loading errors.
•Minimize ground loops. If signal lines are shielded,
ground all shields to a common point at the system
analog common.
If the MPC509A is used for multiplexing high-level signals
of ±1V to ±10V full-scale ranges, the foregoing precautions
should still be taken, but the parameters are not as critical as
for low-level signal applications.
DYNAMIC CHARACTERISTICS
Settling Time
The gate-to-source and gate-to-drain capacitance of the CMOS
FET switches, the RC time constants of the source and the
load determine the settling time of the multiplexer.
Governed by the charge transfer relation i = C (dV/dt), the
charge currents transferred to both load and source by the
analog switches are determined by the amplitude and rise
time of the signal driving the CMOS FET switches and the
gate-to-drain and gate-to-source junction capacitances as
shown in Figures 3 and 4. Using this relationship, one can see
that the amplitude of the switching transients, seen at the
source and load, decrease proportionally as the capacitance
of the load and source increase. The trade-off for reduced
switching transient amplitude is increased settling time. In
effect, the amplitude of the transients seen at the source and
load are:
dVL = (i/C) dt
where i = C (dV/dt) of the CMOS FET switches
C = load or source capacitance
The source must then redistribute this charge, and the effect
of source resistance on settling time is shown in the Typical
Performance Curves. This graph shows the settling time for
a 20V step change on the input. The settling time for smaller
step changes on the input will be less than that shown in the
curve.
Switching Time
This is the time required for the CMOS FET to turn ON after
a new digital code has been applied to the Channel Address
inputs. It is measured from the 50 percent point of the address
input signal to the 90 percent point of the analog signal seen
at the output for a 10V signal change between channels.
Crosstalk
Crosstalk is the amount of signal feedthrough from the three
(MPC509A) or seven (MPC508A) OFF channels appearing
at the multiplexer output. Crosstalk is caused by the voltage
divider effect of the OFF channel, OFF resistance and junc-
tion capacitances in series with the RON and RS impedances
of the ON channel. Crosstalk is measured with a 20Vp-p
1kHz sine wave applied to all OFF channels. The crosstalk
for these multiplexers is shown in the Typical Performance
Curves.
Common-Mode Rejection (MPC509A Only)
The matching properties of the load, multiplexer and source
affect the common-mode rejection (CMR) capability of a
differentially multiplexed system. CMR is the ability of the
multiplexer and input amplifier to reject signals that are
common to both inputs, and to pass on only the signal
difference to the output. For the MPC509A, protection is
provided for common-mode signals of ±20V above the
power supply voltages with no damage to the analog switches.
The CMR of the MPC509A and Burr-Brown’s INA110
instrumentation amplifier is 110dB at DC to 10Hz (G = 100)
with a 6dB/octave roll off to 70dB at 1000Hz. This measure-
ment of CMR is shown in the Typical Performance Curves
and is made with a Burr-Brown model INA110 instrumenta-
tion amplifier connected for gains of 10, 100, and 500.
FIGURE 3. Settling Time Effects—MPC508A
FIGURE 4. Settling and Common-Mode-Effects—
MPC509A
MPC508A, MPC509A 7
SBFS019A www.ti.com
SWITCHING WAVEFORMS
Typical at +25°C, unless otherwise noted.
100ns/Div
1 On
V
A
Input
2V/Div
Output
0.5V/Div
V
AM
4.0V
Address Drive
(V
A
)
Output
50% 50%
t
OPEN
0V
MPC508A
(1)
GND
In 2 Thru In 7
In 1
In 8
Out
A
2
A
1
A
0
En
1kΩ
50Ω
+5V
+4.0V 12.5pF
V
A
V
OUT
NOTE: (1) Similar connection for MPC509A.
BREAK-BEFORE-MAKE DELAY (t
OPEN
)
ENABLE DELAY (tON (EN), tOFF (EN))
100ns/Div
Output
2V/Div
MPC508A(1)
GND
In 2 Thru In 8
In 1
Out
A2
A1
A0
En
1kΩ
+10V
12.5pF
NOTE:
(
1
)
Similar connection for MPC509A.
50Ω
VA
Enable Drive
VAM 4.0V
50%
90%
90%
0V
Output
tON(EN) tOFF(EN)
Enable Drive
2V/Div
Factors which will degrade multiplexer and system DC CMR
are:
• Amplifier bias current and differential impedance mis-
match
• Load impedance mismatch
• Multiplexer impedance and leakage current mismatch
• Load and source common-mode impedance
AC CMR roll off is determined by the amount of common-
mode capacitances (absolute and mismatch) from each signal
line to ground. Larger capacitances will limit CMR at higher
frequencies; thus, if good CMR is desired at higher frequen-
cies, the common-mode capacitances and unbalance of sig-
nal lines and multiplexer-to-amplifier wiring must be mini-
mized. Use twisted-shielded-pair signal lines wherever pos-
sible.
MPC508A, MPC509A
8SBFS019A
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8
6
4
2
0100 1k 10k 100k 1M 10M
Toggle Frequency (Hz)
Supply Current (mA)
V
S
= ±10V
MPC508A
(1)
GND
In 2 Thru In 7
En
In 8
Out
A
2
A
1
A
0
En
10MΩ
+4V 14pF
NOTE:
(
1
)
Similar connection for MPC509A.
A
A
–I
SUPPLY
–15V/–10V
±10V/±5V
–V
+I
SUPPLY
+15V/+10V
50Ω
V
A
SUPPLY CURRENT vs TOGGLE FREQUENCY
V
S
= ±15V
±10V/±5V
±10V/±5V
PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS
Unless otherwise specified: TA = +25, VS = ±15V, VAM = +4V, VAL = 0.8V.
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6–10 –8–6–4–20246810
On Resistance (kΩ)
ON RESISTANCE vs
ANALOG INPUT VOLTAGE NORMALIZED ON RESISTANCE
vs SUPPLY VOLTAGE
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8 ±5 ±6 ±7 ±8 ±9 ±10 ±11 ±12 ±13 ±14 ±15
Supply Volta
g
e (V)
Normalized On Resistance
(Referred to Value at ±15V)
±125°C > T
A
> –55°C
V
IN
= +5V
ON RESISTANCE vs ANALOG INPUT SIGNAL,
SUPPLY VOLTAGE 100µA
V
2
R
ON
= V
2
/100µA
In Out
V
IN
Analo
g
Input
(
V
)
T
A
= +125°C
T
A
= +25°C
T
A
= –55°C
MPC508A, MPC509A 9
SBFS019A www.ti.com
Out
±10V
A
En +0.8V
I
D
(Off)
10V
Out
±10V
AI
D
(On)
En
A
0
A
1
100nA
10nA
1nA
100pA
10pA25 50 75 100 125
Temperature (°C)
Leakage Current
LEAKAGE CURRENT vs TEMPERATURE
NOTE: (1) Two measurements per channel: +10V/–10V and –10V/+10V.
(Two measurements per device for I
D
(Off): +10V/–10V and –10V/+10V).
+4.0V
±
10V
±
Out
10V
I
S
(Off)
±10V
A
En +0.8V
±
Off Output
Current
I
D
(Off)
Off Input
Leakage Current
I
S
(Off)
On Leakage
Current I
D
(On)
Analog Input Overvoltage (V)
+12 +15 +18 +21 +24 +27 +30 +33 +36
7
6
5
4
3
2
1
0
Analog Input Current (mA)
Output Off Leakage Current (nA)
Analog Input
Current (I
IN
)
Output Off
Leakage Current
I
O
(Off)
I
IN
I
O
(Off)
A
+V
IN
ANALOG INPUT OVERVOLTAGE CHARACTERISTICS
21
18
12
9
6
3
0
15
A
Analog Input Overvoltage (V)
−12 −15 −18 −21 −24 −27 −30 −33 −36
4
2
0
Analog Input Current (mA)
Output Off Leakage Current (µA)
Analog Input
Current (I
IN
)
Output Off
Leakage Current
I
O
(Off)
I
IN
I
O
(Off)
A
−V
IN
21
18
12
9
6
3
0
15
A
Positive Input Overvoltage
Negative Input Overvoltage
PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS (CONT)
MPC508A, MPC509A
10 SBFS019A
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PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS (CONT)
A
±V
IN
V
IN
–Voltage Across Switch (V)
0 ±2 ±4 ±6 ±8 ±10 ±12 ±14 ±16
±14
±12
±10
±8
±6
±4
±2
0
Switch Current (mA)
ON-CHANNEL CURRENT vs VOLTAGE
–55°C+25°C
+125°C
ACCESS TIME WAVEFORM
VA Input
2V/Div
Output A
5V/Div
200ns/Div
VAM 4.0V
0V
10V
tA
50%
10V
90%
Address
Drive (VA)
Output A
MPC
508A(1)
GND
In 2 Thru
In 7
In 1
In 8
Out
A2
A1
A0
En
10MΩ
50Ω
+4V 14pF
VA
NOTE: (1) Similar connection for MPC509A.
–10V
1000
900
800
700
600
500
400
300 3456789101112131415
Lo
g
ic Level Hi
g
h
(
V
)
Access Time (ns)
ACCESS TIME vs LOGIC LEVEL (High)
Probe
+10V
+15V
VREF +V
–15V
–V
MPC508A, MPC509A 11
SBFS019A www.ti.com
Direct
Multiplexer
Output
Buffered
OPA602
1/4 OPA404
MPC508A
Out
Out
In 1
In 2
In 3
In 8
A
0
A
1
A
2
2
8
A
0
A
1
A
2
MPC508A
8
2
6-Bit Channel
Address Generator
A
0
A
1
A
2
In 1
In 2
In 3
In 8
In 1
In 8
MPC508A
En
En
Out
En
+V
+V
+V
4LSBs 4MSBs
8 Analog Inputs (CH57 to 64) 8 Analog Inputs (CH1 to 8)
Settling Time to
±0.01% is 20µs
with R
S
= 100Ω
INSTALLATION AND
OPERATING INSTRUCTIONS
The ENABLE input, pin 2, is included for expansion of the
number of channels on a single node as illustrated in Figure
5. With ENABLE line at a logic 1, the channel is selected by
the 2-bit (MPC509A) or 3-bit (MPC508A) Channel Select
Address (shown in the Truth Tables). If ENABLE is at logic
0, all channels are turned OFF, even if the Channel Address
Lines are active. If the ENABLE line is not to be used, simply
tie it to +VSUPPLY.
If the +15V and/or –15V supply voltage is absent or shorted
to ground, the MPC509A and MPC508A multiplexers will
not be damaged; however, some signal feedthrough to the
output will occur. Total package power dissipation must not
be exceeded.
For best settling speed, the input wiring and interconnections
between multiplexer output and driven devices should be
kept as short as possible. When driving the digital inputs
from TTL, open collector output with pull-up resistors are
recommended
To preserve common-mode rejection of the MPC509A, use
twisted-shielded pair wire for signal lines and inter-tier
connections and/or multiplexer output lines. This will help
common-mode capacitance balance and reduce stray signal
pickup. If shields are used, all shields should be connected as
close as possible to system analog common or to the com-
mon-mode guard driver.
CHANNEL EXPANSION
Single-Ended Multiplexer (MPC508A)
Up to 32 channels (four multiplexers) can be connected to a
single node, or up to 64 channels using nine MPC508A
multiplexers on a two-tiered structure as shown in Figures 5
and 6.
FIGURE 5. 32-Channel, Single-Tier Expansion.
FIGURE 6. Channel Expansion Up to 64 Channels Using
8 x 8 Two-Tiered Expansion.
Differential Multiplexer (MPC509A)
Single or multitiered configurations can be used to expand
multiplexer channel capacity up to 32 channels using a
32 x 1 or 16 channels using a 4 x 4 configuration.
Single-Node Expansion
The 32 x 1 configuration is simply eight (MPC509A) units
tied to a single node. Programming is accomplished with a
5-bit counter, using the 2LSBs of the counter to control
Channel Address inputs A0 and A1 and the 3MSBs of the
counter to drive a 1-of-8 decoder. The 1-of-8 decoder then is
used to drive the ENABLE inputs (pin 2) of the MPC509A
multiplexers.
Two-Tier Expansion
Using a 4 x 4 two-tier structure for expansion to 16 channels,
the programming is simplified. A 4-bit counter output does
not require a 1-of-8 decoder. The 2LSBs of the counter drive
the A0 and A1 inputs of the four first-tier multiplexers and the
2MSBs of the counter are applied to the A0 and A1 inputs of
the second-tier multiplexer.
Single vs Multitiered Channel Expansion
In addition to reducing programming complexity, two-tier
configuration offers the added advantages over single-node
expansion of reduced OFF channel current leakage (reduced
OFFSET), better CMR, and a more reliable configuration if
a channel should fail in the ON condition (short). Should a
channel fail ON in the single-node configuration, data cannot
be taken from any channel, whereas only one channel group
is failed (4 or 8) in the multitiered configuration.
MPC
508A
8 Analog Inputs8 Analog Inputs
Out
Group 1
Group 4
Out
Enable
Enable
20
21
22
23
24
Settling Time to 0.01% for RS < 100Ω
—Two MPC508A units in parallels: 10µs
—Four MPC509 A units in parallels: 12
µ
s
Direct
Multiplexer
Output
Buffered
OPA602
1/4 OPA404
5-Bit
Binary
Counter
To
Group
2
To
Group
3
1 of 4
Decoder
In 1
In 2
In 3
In 8 A2A1A0
2
8
A2A1A0
MPC
508A
Group 1
Ch1-8
2
8
In 1
In 2
In 3
In 8Group 4
Ch25-42
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
MPC508AP ACTIVE PDIP N 16 25 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
MPC508APG4 ACTIVE PDIP N 16 25 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
MPC508AU ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MPC508AU/1K ACTIVE SOIC DW 16 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MPC508AU/1KG4 ACTIVE SOIC DW 16 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MPC508AUG4 ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MPC509AP ACTIVE PDIP N 16 25 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
MPC509APG4 ACTIVE PDIP N 16 25 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
MPC509AU ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MPC509AU/1K ACTIVE SOIC DW 16 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MPC509AU/1KG4 ACTIVE SOIC DW 16 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
MPC509AUG4 ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Feb-2009
Addendum-Page 1
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Feb-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
MPC508AU/1K SOIC DW 16 1000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
MPC509AU/1K SOIC DW 16 1000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
MPC508AU/1K SOIC DW 16 1000 367.0 367.0 38.0
MPC509AU/1K SOIC DW 16 1000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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