Document Number: MPC5554 Rev. 2.0, 10/2007 Freescale Semiconductor Data Sheet: Technical Data MPC5554 Microcontroller Data Sheet by: Microcontroller Division This document provides electrical specifications, pin assignments, and package diagrams for the MPC5554 microcontroller device. For functional characteristics, refer to the MPC5553/MPC5554 Microcontroller Reference Manual. 1 Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.2 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . 5 3.3 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.4 EMI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.5 ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 9 3.6 VRC and POR Electrical Specifications . . . . . . . . . 9 3.7 Power-Up/Down Sequencing . . . . . . . . . . . . . . . . 10 3.8 DC Electrical Specifications. . . . . . . . . . . . . . . . . . 13 3.9 Oscillator and FMPLL Electrical Characteristics . . 20 3.10 eQADC Electrical Characteristics . . . . . . . . . . . . . 22 3.11 H7Fa Flash Memory Electrical Characteristics . . . 23 3.12 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.13 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4 Mechanicals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.1 MPC5554 416 PBGA Pinouts . . . . . . . . . . . . . . . . 45 4.2 MPC5554 Package Dimensions . . . . . . . . . . . . . . 48 5 Revision History for the MPC5554 Data Sheet . . . . . . . 50 Overview The MPC5554 microcontroller (MCU) is a member of the MPC5500 family of microcontrollers built on the Power ArchitectureTM embedded technology. This family of parts contains many new features coupled with high performance CMOS technology to provide substantial reduction of cost per feature and significant performance improvement over the MPC500 family. The host processor core of this device complies with the Power Architecture embedded category that is 100% user-mode compatible (with floating point library) with the original Power PCTM user instruction set architecture (UISA). The embedded architecture has enhancements that improve the performance in embedded applications. The core also has additional instructions, including digital signal processing (DSP) instructions, beyond the original Power PC instruction set. (c) Freescale Semiconductor, Inc., 2007. All rights reserved. Overview The MPC5500 family of parts contains many new features coupled with high performance CMOS technology to provide significant performance improvement over the MPC565. The MPC5554 of the MPC5500 family has two levels of memory hierarchy. The fastest accesses are to the 32-kilobytes (KB) unified cache. The next level in the hierarchy contains the 64-KB on-chip internal SRAM and 2-megabytes (MB) internal flash memory. The internal SRAM and flash memory can hold instructions and data. The external bus interface has been designed to support most of the standard memories used with the MPC5xx family. The complex input/output timer functions of the MPC5500 family are performed by two enhanced time processor unit (eTPU) engines. Each eTPU engine controls hardware channels, providing a total of 64 hardware channels. The eTPU has been enhanced over the TPU by providing 24-bit timers, double-action hardware channels, variable number of parameters per channel, angle clock hardware, and additional control and arithmetic instructions. The eTPU can be programmed using a high-level programming language. The less complex timer functions of the MPC5500 family are performed by the enhanced modular input/output system (eMIOS). The eMIOS' 24 hardware channels are capable of single-action, double-action, pulse-width modulation (PWM), and modulus-counter operations. Motor control capabilities include edge-aligned and center-aligned PWM. Off-chip communication is performed by a suite of serial protocols including controller area networks (FlexCANs), enhanced deserial/serial peripheral interfaces (DSPIs), and enhanced serial communications interfaces (eSCIs). The DSPIs support pin reduction through hardware serialization and deserialization of timer channels and general-purpose input/output (GPIOs) signals. The MCU of the MPC5554 has an on-chip 40-channel enhanced queued dual analog-to-digital converter (eQADC). The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset control are also determined by the SIU. The internal multiplexer submodule (SIU_DISR) provides multiplexing of eQADC trigger sources, daisy chaining the DSPIs, and external interrupt signal multiplexing. MPC5554 Microcontroller Data Sheet, Rev. 2.0 2 Freescale Semiconductor Ordering Information 2 Ordering Information M PC 5554 M ZP 80 R 2 Qualification status Core code Device number Temperature range Package identifier Operating frequency (MHz) Tape and reel status Temperature Range M = -40 C to 125 C A = -55 C to 125 C Package Identifier ZP = 416PBGA SnPb VR = 416PBGA Pb-free Operating Frequency 80 = 80 MHz 112 = 112 MHz 132 = 132 MHz Tape and Reel Status R2 = Tape and reel (blank) = Trays Qualification Status P = Pre qualification M = Fully spec. qualified Note: Not all options are available on all devices. Refer to Table 1. Figure 1. MPC5500 Family Part Number Example Unless noted in this data sheet, all specifications apply from TL to TH. Table 1. Orderable Part Numbers Speed (MHz) Freescale Part Number1 Package Description Nominal Max3 (fMAX) 132 132 112 114 80 82 MPC5554AVR132 132 132 MPC5554MZP132 132 132 112 114 80 82 132 132 MPC5554MVR132 MPC5554MVR112 MPC5554MVR80 MPC5554MZP112 MPC5554MZP80 MPC5554AZP132 Operating Temperature2 MPC5554 Lead-free 416 package MPC5554 Lead 416 package Min (TL) Max (TH) -40 C 125 C -55 C 125 C -40 C 125 C -55 C 125 C 1 All devices are PPC5554, rather than MPC5554, until product qualifications are complete. Not all configurations are available in the PPC parts. 2 The lowest ambient operating temperature is referenced by TL; the highest ambient operating temperature is referenced by TH. 3 Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM). 82 MHz parts allow for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM; and132 MHz parts allow for 128 MHz system clock + 2% FM. MPC5554 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 3 Electrical Characteristics 3 Electrical Characteristics This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MCU. 3.1 Maximum Ratings Table 2. Absolute Maximum Ratings1 Spec Characteristic Symbol Min Max Unit 1 1.5 V core supply voltage 2 VDD -0.3 1.7 V 2 Flash program/erase voltage VPP -0.3 6.5 V 4 Flash read voltage VFLASH -0.3 4.6 V 5 SRAM standby voltage VSTBY -0.3 1.7 V 6 Clock synthesizer voltage VDDSYN -0.3 4.6 V 7 3.3 V I/O buffer voltage VDD33 -0.3 4.6 V 8 Voltage regulator control input voltage VRC33 -0.3 4.6 V 9 Analog supply voltage (reference to VSSA) VDDA -0.3 5.5 V VDDE -0.3 4.6 V VDDEH -0.3 6.5 V -1.05 -1.05 6.56 4.67 V 10 11 12 I/O supply voltage (fast I/O pads) 3 I/O supply voltage (slow and medium I/O pads) 3 voltage4 DC input VDDEH powered I/O pads VDDE powered I/O pads VIN 13 Analog reference high voltage (reference to VRL) VRH -0.3 5.5 V 14 VSS to VSSA differential voltage VSS - VSSA -0.1 0.1 V 15 VDD to VDDA differential voltage VDD - VDDA -VDDA VDD V 16 VREF differential voltage VRH - VRL -0.3 5.5 V 17 VRH to VDDA differential voltage VRH - VDDA -5.5 5.5 V 18 VRL to VSSA differential voltage VRL - VSSA -0.3 0.3 V 19 VDDEH to VDDA differential voltage VDDEH - VDDA -VDDA VDDEH V 20 VDDF to VDD differential voltage VDDF - VDD -0.3 0.3 V 21 VRC33 to VDDSYN differential voltage spec has been moved to Table 9 DC Electrical Specifications, Spec 43a. 22 VSSSYN to VSS differential voltage VSSSYN - VSS -0.1 0.1 V 23 VRCVSS to VSS differential voltage VRCVSS - VSS -0.1 0.1 V 24 Maximum DC digital input current 8 (per pin, applies to all digital pins)4 IMAXD -2 2 mA 25 Maximum DC analog input current 9 (per pin, applies to all analog pins) IMAXA -3 3 mA 26 Maximum operating temperature range 10 Die junction temperature TJ TL 150.0 oC 27 Storage temperature range TSTG -55.0 150.0 oC MPC5554 Microcontroller Data Sheet, Rev. 2.0 4 Freescale Semiconductor Electrical Characteristics Table 2. Absolute Maximum Ratings1 (continued) Spec 28 29 Characteristic Symbol Min Max Maximum solder temperature 11 Lead free (PbFree) Leaded (SnPb) TSDR -- 260.0 245.0 Moisture sensitivity level 12 MSL -- 3 Unit o C 1 Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond any of the listed maxima can affect device reliability or cause permanent damage to the device. 2 1.5 V 10% for proper operation. This parameter is specified at a maximum junction temperature of 150 oC. 3 All functional non-supply I/O pins are clamped to VSS and VDDE, or VDDEH. 4 AC signal overshoot and undershoot of up to 2.0 V of the input voltages is permitted for an accumulative duration of 60 hours over the complete lifetime of the device (injection current not limited for this duration). 5 Internal structures hold the voltage greater than -1.0 V if the injection current limit of 2 mA is met. Keep the negative DC voltage greater than -0.6 V on eTPUB[15] and SINB during the internal power-on reset (POR) state. 6 Internal structures hold the input voltage less than the maximum voltage on all pads powered by V DDEH supplies, if the maximum injection current specification is met (2 mA for all pins) and VDDEH is within the operating voltage specifications. 7 Internal structures hold the input voltage less than the maximum voltage on all pads powered by V DDE supplies, if the maximum injection current specification is met (2 mA for all pins) and VDDE is within the operating voltage specifications. 8 Total injection current for all pins (including both digital and analog) must not exceed 25 mA. 9 Total injection current for all analog input pins must not exceed 15 mA. 10 Lifetime operation at these specification limits is not guaranteed. 11 Moisture sensitivity profile per IPC/JEDEC J-STD-020D. 12 Moisture sensitivity per JEDEC test method A112. 3.2 Thermal Characteristics The shaded rows in the following table indicate information specific to a four-layer board. Table 3. MPC5554 Thermal Characteristics Spec 1 2 3 4 5 6 7 MPC5554 Thermal Characteristic Junction to ambient 1, 2, natural convection (one-layer board) Symbol 416 PBGA Unit RJA 24 C/W RJA 18 C/W Junction to ambient 1, 3, Junction to ambient 1, 3 (@200 ft./min., one-layer board) RJMA 19 C/W Junction to ambient 1, 3 (@200 ft./min., four-layer board 2s2p) RJMA 15 C/W RJB 9 C/W RJC 5 C/W JT 2 C/W Junction to board Junction to case 4 natural convection (four-layer board 2s2p) (four-layer board 2s2p) 5 Junction to package top 6, natural convection 1 Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal. 3 Per JEDEC JESD51-6 with the board horizontal. 4 Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. MPC5554 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 5 Electrical Characteristics 5 Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. 6 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. 3.2.1 3.2.2 General Notes for Specifications at Maximum Junction Temperature An estimation of the device junction temperature, TJ, can be obtained from the equation: TJ = TA + (RJA x PD) where: TA = ambient temperature for the package (oC) RJA = junction to ambient thermal resistance (oC/W) PD = power dissipation in the package (W) The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for estimations and comparisons. The difference between the values determined for the single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance depends on the: * Construction of the application board (number of planes) * Effective size of the board which cools the component * Quality of the thermal and electrical connections to the planes * Power dissipated by adjacent components Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance between the vias leave the planes virtually disconnected, the thermal performance is also greatly reduced. As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit board. The value obtained on a board with the internal planes is usually within the normal range if the application board has: * One oz (35 micron nominal thickness) internal planes * Components are well separated * Overall power dissipation on the board is less than 0.02 W/cm2 The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. MPC5554 Microcontroller Data Sheet, Rev. 2.0 6 Freescale Semiconductor Electrical Characteristics At a known board temperature, the junction temperature is estimated using the following equation: TJ = TB + (RJB x PD) where: TJ = junction temperature (oC) TB = board temperature at the package perimeter (oC/W) RJB = junction-to-board thermal resistance (oC/W) per JESD51-8 PD = power dissipation in the package (W) When the heat loss from the package case to the air does not factor into the calculation, an acceptable value for the junction temperature is predictable. Ensure the application board is similar to the thermal test condition, with the component soldered to a board with internal planes. The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal resistance: RJA = RJC + RCA where: RJA = junction-to-ambient thermal resistance (oC/W) RJC = junction-to-case thermal resistance (oC/W) RCA = case-to-ambient thermal resistance (oC/W) RJC is device related and is not affected by other factors. The thermal environment can be controlled to change the case-to-ambient thermal resistance, RCA. For example, change the air flow around the device, add a heat sink, change the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat sink to ambient. For most packages, a better model is required. A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple estimations and for computational fluid dynamics (CFD) thermal models. To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization parameter (JT) to determine the junction temperature by measuring the temperature at the top center of the package case using the following equation: TJ = TT + (JT x PD) where: TT = thermocouple temperature on top of the package (oC) JT = thermal characterization parameter (oC/W) PD = power dissipation in the package (W) The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple MPC5554 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 7 Electrical Characteristics so that the thermocouple junction rests on the package. Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire. References: Semiconductor Equipment and Materials International 805 East Middlefield Rd. Mountain View, CA., 94043 (415) 964-5111 MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC specifications are available on the web at http://www.jedec.org. * 1. C.E. Triplett and B. Joiner, "An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module," Proceedings of SemiTherm, San Diego, 1998, pp. 47-54. * 2. G. Kromann, S. Shidore, and S. Addison, "Thermal Modeling of a PBGA for Air-Cooled Applications," Electronic Packaging and Production, pp. 53-58, March 1998. * 3. B. Joiner and V. Adams, "Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling," Proceedings of SemiTherm, San Diego, 1999, pp. 212-220. 3.3 Package The MPC5554 is available in packaged form. Read the package options in Section 2, "Ordering Information." Refer to Section 4, "Mechanicals," for pinouts and package drawings. 3.4 EMI (Electromagnetic Interference) Characteristics Table 4. EMI Testing Specifications1 Spec Characteristic Minimum Typical Maximum Unit 0.15 -- 1000 MHz 1 Scan range 2 Operating frequency -- -- fMAX MHz 3 VDD operating voltages -- 1.5 -- V 4 VDDSYN, VRC33, VDD33, VFLASH, VDDE operating voltages -- 3.3 -- V 5 VPP, VDDEH, VDDA operating voltages -- 5.0 -- V 6 Maximum amplitude -- -- 142 323 dBuV 7 Operating temperature -- -- 25 oC 1 EMI testing and I/O port waveforms per SAE J1752/3 issued 1995-03. Qualification testing was performed on the MPC5554 and applied to the MPC5500 family as generic EMI performance data. 2 Measured with single-chip EMI program. 3 Measured with expanded EMI program. MPC5554 Microcontroller Data Sheet, Rev. 2.0 8 Freescale Semiconductor Electrical Characteristics 3.5 ESD (Electromagnetic Static Discharge) Characteristics Table 5. ESD Ratings1, 2 Characteristic Symbol Value Unit 2000 V R1 1500 C 100 pF ESD for human body model (HBM) HBM circuit description 500 (all pins) ESD for field induced charge model (FDCM) V 750 (corner pins) Number of pulses per pin: Positive pulses (HBM) Negative pulses (HBM) -- -- 1 1 -- -- Interval of pulses -- 1 second 1 2 All ESD testing conforms to CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. Device failure is defined as: if after exposure to ESD pulses, the device no longer meets the device specification requirements. Complete DC parametric and functional testing will be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. 3.6 Voltage Regulator Controller (VRC) and Power-On Reset (POR) Electrical Specifications The following table lists the VRC and POR electrical specifications: Table 6. VRC/POR Electrical Specifications Spec Characteristic Symbol Min Max Units 1 1.5 V (VDD) POR negated (ramp up) 1.5 V (VDD) POR asserted (ramp down) VPOR15 1.1 1.1 1.35 1.35 V 2 3.3 V (VDDSYN) POR asserted (ramp up) 3.3 V (VDDSYN) POR negated (ramp up) 3.3 V (VDDSYN) POR asserted (ramp down) 3.3 V (VDDSYN) POR negated (ramp down) VPOR33 0.0 2.0 2.0 0.0 0.30 2.85 2.85 0.30 V 3 RESET pin supply (VDDEH6) POR negated (ramp up)1 RESET pin supply (VDDEH6) POR asserted (ramp down) 1 VPOR5 2.0 2.0 2.85 2.85 V 4 VRC33 voltage before the regulator controller allows the pass transistor to start turning on VTRANS_START 1.0 2.0 5 VRC33 voltage when the regulator controller allows the pass transistor to completely turn on 2, 3 VTRANS_ON 2.0 2.85 6 VRC33 voltage greater than the voltage at which the VRC keeps the 1.5 V supply in regulation4, 5 VVRC33REG 3.0 -- 7 Current can be sourced by VRCCTL at Tj: IVRCCTL6 V V V mA - 55o C7 11.0 -- mA - 40o 11.0 -- mA 25 C 9.0 -- mA 150o 7.5 -- mA C o C MPC5554 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 9 Electrical Characteristics Table 6. VRC/POR Electrical Specifications (continued) Spec 8 Characteristic Voltage differential during power up such that: VDD33 can lag VDDSYN or VDDEH6, before VDDSYN and VDDEH6 reach the VPOR33 and VPOR5 minimums respectively. 9 Absolute value of slew rate on power supply pins 10 Required gain at Tj: IDD / IVRCCTL (@ fsys = fMAX)5, 6, 8, 9 Symbol Min Max Units VDD33_LAG -- 1.0 V -- 50 V/ms 70 -- mA 70 -- -- -- -- 500 -- BETA10 - 55o C7 - 40o C o 10 25 C 85 o 10 150 C 105 1 VIL_S (Table 9, Spec15) is guaranteed to scale with VDDEH6 down to VPOR5. Supply full operating current for the 1.5 V supply when the 3.3 V supply reaches this range. 3 It is possible to reach the current limit during ramp up--do not treat this event as short circuit current. 4 At peak current for device. 5 Requires compliance with Freescale's recommended board requirements and transistor recommendations. Board signal traces/routing from the VRCCTL package signal to the base of the external pass transistor and between the emitter of the pass transistor to the VDD package signals must have a maximum of 100 nH inductance and minimal resistance (less than 1 ). VRCCTL must have a nominal 1 F phase compensation capacitor to ground. VDD must have a 20 F (nominal) bulk capacitor (greater than 4 F over all conditions, including lifetime). Place high-frequency bypass capacitors consisting of eight 0.01 F, two 0.1 F, and one 1 F capacitors around the package on the VDD supply signals. 6 I VRCCTL is measured at the following conditions: VDD = 1.35 V, VRC33 = 3.1 V, VVRCCTL = 2.2 V. 7 Only available on devices that support -55o C. 8 Refer to Table 1 for the maximum operating frequency. 9 Values are based on I DD from high-use applications as explained in the IDD Electrical Specification. 10 BETA represents the worst-case external transistor. It is measured on a per-part basis and calculated as (I DD / IVRCCTL). 2 3.7 Power-Up/Down Sequencing Power sequencing between the 1.5 V power supply and VDDSYN or the RESET power supplies is required if using an external 1.5 V power supply with VRC33 tied to ground (GND). To avoid power-sequencing, VRC33 must be powered up within the specified operating range, even if the on-chip voltage regulator controller is not used. Refer to Section 3.7.2, "Power-Up Sequence (VRC33 Grounded)," and Section 3.7.3, "Power-Down Sequence (VRC33 Grounded)." Power sequencing requires that VDD33 must reach a certain voltage where the values are read as ones before the POR signal negates. Refer to Section 3.7.1, "Input Value of Pins During POR Dependent on VDD33." Although power sequencing is not required between VRC33 and VDDSYN during power up, VRC33 must not lead VDDSYN by more than 600 mV or lag by more than 100 mV for the VRC stage turn-on to operate within specification. Higher spikes in the emitter current of the pass transistor occur if VRC33 leads or lags VDDSYN by more than these amounts. The value of that higher spike in current depends on the board power supply circuitry and the amount of board level capacitance. MPC5554 Microcontroller Data Sheet, Rev. 2.0 10 Freescale Semiconductor Electrical Characteristics Furthermore, when all of the PORs negate, the system clock starts to toggle, adding another large increase of the current consumed by VRC33. If VRC33 lags VDDSYN by more than 100 mV, the increase in current consumed can drop VDD low enough to assert the 1.5 V POR again. Oscillations are possible when the 1.5 V POR asserts and stops the system clock, causing the voltage on VDD to rise until the 1.5 V POR negates again. All oscillations stop when VRC33 is powered sufficiently. When powering down, VRC33 and VDDSYN have no delta requirement to each other, because the bypass capacitors internal and external to the device are already charged. When not powering up or down, no delta between VRC33 and VDDSYN is required for the VRC to operate within specification. There are no power up/down sequencing requirements to prevent issues such as latch-up, excessive current spikes, and so on. Therefore, the state of the I/O pins during power up and power down varies depending on which supplies are powered. Table 7 gives the pin state for the sequence cases for all pins with pad type pad_fc (fast type). Table 7. Pin Status for Fast Pads During the Power Sequence VDDE VDD33 VDD POR Pin Status for Fast Pad Output Driver pad_fc (fast) Low -- -- Asserted Low VDDE Low Low Asserted High VDDE Low VDD Asserted High VDDE VDD33 Low Asserted High impedance (Hi-Z) VDDE VDD33 VDD Asserted Hi-Z VDDE VDD33 VDD Negated Functional Table 8 gives the pin state for the sequence cases for all pins with pad type pad_mh (medium type) and pad_sh (slow type). Table 8. Pin Status for Medium / Slow Pads During the Power Sequence VDDEH VDD POR Pin Status for Medium and Slow Pad Output Driver pad_mh (medium) pad_sh (slow) Low -- Asserted Low VDDEH Low Asserted High impedance (Hi-Z) VDDEH VDD Asserted Hi-Z VDDEH VDD Negated Functional The values in Table 7 and Table 8 do not include the effect of the weak-pull devices on the output pins during power up. Before exiting the internal POR state, the voltage on the pins goes to high-impedance until POR negates. When the internal POR negates, the functional state of the signal during reset applies and the weak-pull devices (up or down) are enabled as defined in the device Reference Manual. If VDD is too low to correctly propagate the logic signals, the weak-pull devices can pull the signals to VDDE and VDDEH. MPC5554 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 11 Electrical Characteristics To avoid this condition, minimize the ramp time of the VDD supply to a time period less than the time required to enable the external circuitry connected to the device outputs. 3.7.1 Input Value of Pins During POR Dependent on VDD33 When powering up the device, VDD33 must not lag the latest VDDSYN or RESET power pin (VDDEH6) by more than the VDD33 lag specification listed in Table 6, spec 8. This avoids accidentally selecting the bypass clock mode because the internal versions of PLLCFG[0:1] and RSTCFG are not powered and therefore cannot read the default state when POR negates. VDD33 can lag VDDSYN or the RESET power pin (VDDEH6), but cannot lag both by more than the VDD33 lag specification. This VDD33 lag specification applies during power up only. VDD33 has no lead or lag requirements when powering down. 3.7.2 Power-Up Sequence (VRC33 Grounded) The 1.5 V VDD power supply must rise to 1.35 V before the 3.3 V VDDSYN power supply and the RESET power supply rises above 2.0 V. This ensures that digital logic in the PLL for the 1.5 V power supply does not begin to operate below the specified operation range lower limit of 1.35 V. Because the internal 1.5 V POR is disabled, the internal 3.3 V POR or the RESET power POR must hold the device in reset. Since they can negate as low as 2.0 V, VDD must be within specification before the 3.3 V POR and the RESET POR negate. VDDSYN and RESET Power VDD 2.0 V 1.35 V VDD must reach 1.35 V before VDDSYN and the RESET power reach 2.0 V Figure 2. Power-Up Sequence (VRC33 Grounded) 3.7.3 Power-Down Sequence (VRC33 Grounded) The only requirement for the power-down sequence when VRC33 is grounded is that if VDD decreases to less than its operating range, VDDSYN or the RESET power must decrease to less than 2.0 V before the VDD power is allowed to increase to its operating range. This ensures that the digital 1.5 V logic, which is reset by the ORed POR only and can cause the 1.5 V supply to decrease below its specification, is reset properly. MPC5554 Microcontroller Data Sheet, Rev. 2.0 12 Freescale Semiconductor Electrical Characteristics 3.8 DC Electrical Specifications Table 9. DC Electrical Specifications Spec Characteristic Symbol Min Max Unit 1 Core supply voltage (average DC RMS voltage) VDD 1.35 1.65 V 2 Input/output supply voltage (fast input/output) VDDE 1.62 3.6 V 3 Input/output supply voltage (slow and medium input/output) VDDEH 3.0 5.25 V 4 3.3 V input/output buffer voltage VDD33 3.0 3.6 V 5 Voltage regulator control input voltage VRC33 3.0 3.6 V 1 6 Analog supply voltage VDDA 4.5 5.25 V 8 Flash programming voltage2 VPP 4.5 5.25 V 9 Flash read voltage VFLASH 3.0 3.6 V 10 SRAM standby voltage3 VSTBY 0.8 1.2 V 11 Clock synthesizer operating voltage VDDSYN 3.0 3.6 V 12 Fast input/output input high voltage VIH_F 0.65 x VDDE VDDE + 0.3 V 13 Fast input/output input low voltage VIL_F VSS - 0.3 0.35 x VDDE V 14 Medium and slow input high voltage VIH_S 0.65 x VDDEH VDDEH + 0.3 V 15 Medium and slow input low voltage VIL_S VSS - 0.3 0.35 x VDDEH V 16 Fast input hysteresis VHYS_F 0.1 x VDDE V 17 Medium and slow input hysteresis VHYS_S 0.1 x VDDEH V 18 Analog input voltage VINDC VSSA - 0.3 VDDA + 0.3 V 19 Fast output high voltage ( IOH_F = -2.0 mA ) VOH_F 0.8 x VDDE -- V 20 Slow and medium output high voltage IOH_S = -2.0 mA IOH_S = -1.0 mA VOH_S 0.80 x VDDEH 0.85 x VDDEH -- V 21 Fast output low voltage ( IOL_F = 2.0 mA ) VOL_F -- 0.2 x VDDE V 22 Slow and medium output low voltage IOL_S = 2.0 mA IOL_S = 1.0 mA VOL_S -- Load capacitance (fast I/O)4 DSC (SIU_PCR[8:9] ) = 0b00 = 0b01 = 0b10 = 0b11 CL 24 Input capacitance (digital pins) 25 26 23 V 0.20 x VDDEH 0.15 x VDDEH -- -- -- -- 10 20 30 50 pF pF pF pF CIN -- 7 pF Input capacitance (analog pins) CIN_A -- 10 pF Input capacitance: (Shared digital and analog pins AN[12]_MA[0]_SDS, AN[13]_MA[1]_SDO, AN[14]_MA[2]_SDI, and AN[15]_FCK) CIN_M -- 12 pF MPC5554 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 13 Electrical Characteristics Table 9. DC Electrical Specifications (continued) Spec Characteristic Symbol Min Max Unit IDD IDD IDD IDD -- -- -- -- 700 600 875 740 mA mA mA mA IDD IDD IDD IDD -- -- -- -- 609 522 760 643 mA mA mA mA IDD IDD IDD IDD -- -- -- -- 446 384 555 471 mA mA mA mA IDD_STBY IDD_STBY IDD_STBY -- -- -- 20 30 50 A A A IDD_STBY @ 60o C VSTBY @ 0.8 V VSTBY @ 1.0 V VSTBY @ 1.2 V IDD_STBY IDD_STBY IDD_STBY -- -- -- 70 100 200 A A A IDD_STBY @ 150o C (Tj) VSTBY @ 0.8 V VSTBY @ 1.0 V VSTBY @ 1.2 V IDD_STBY IDD_STBY IDD_STBY -- -- -- 1200 1500 2000 A A A VDD3311 IDD_33 -- 2 + (values derived from procedure of footnote 11) mA VFLASH IVFLASH -- 10 mA VDDSYN IDDSYN -- 15 mA IDD_A IREF IPP -- -- -- 20.0 1.0 25.0 mA mA mA 27a Operating Current 1.5 V Supplies @ 132 MHz: 5, 6 VDD (including VDDF max current) @1.65 V typical use 7, 8 VDD (including VDDF max current) @1.4 V typical use 7, 8 VDD (including VDDF max current) @1.65 V high use 8, 9 VDD (including VDDF max current) @1.4 V high use 8, 9 27b Operating Current 1.5 V Supplies @ 114 MHz: 5, 6 VDD (including VDDF max current) @1.65 V typical use 7, 8 VDD (including VDDF max current) @1.4 V typical use 7, 8 VDD (including VDDF max current) @1.65 V high use 8, 9 VDD (including VDDF max current) @1.4 V high use 8, 9 27c Operating Current 1.5 V Supplies @ 82 MHz: 5, 6 VDD (including VDDF max current) @1.65 V typical use 7, 8 VDD (including VDDF max current) @1.40 V typical use 7, 8 VDD (including VDDF max current) @1.65 V high use 8, 9 VDD (including VDDF max current) @1.40 V high use 8, 9 27d Refer to Figure 3 for an interpolation of this data.10 IDD_STBY @ 25o C VSTBY @ 0.8 V VSTBY @ 1.0 V VSTBY @ 1.2 V 28 29 Operating current 3.3 V supplies @ fMAX MHz Operating current 5.0 V supplies (12 MHz ADCLK): VDDA (VDDA0 + VDDA1) Analog reference supply current (VRH, VRL) VPP MPC5554 Microcontroller Data Sheet, Rev. 2.0 14 Freescale Semiconductor Electrical Characteristics Table 9. DC Electrical Specifications (continued) Spec 30 31 Characteristic Operating current VDDE12 supplies: VDDEH1 VDDE2 VDDE3 VDDEH4 VDDE5 VDDEH6 VDDE7 VDDEH8 VDDEH9 I/O input leakage current14 34 DC injection current (per pin) Analog input current, channel off 15 35a Analog input current, shared analog / digital pins (AN[12], AN[13], AN[14], AN[15]) 1 Max Unit IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 IDD7 IDD8 IDD9 -- -- -- -- -- -- -- -- -- Refer to Footnote 12 mA mA mA mA mA mA mA mA mA 10 20 20 110 130 170 A A A 10 20 20 100 130 170 A A A IACT_S 10 20 150 170 A A IINACT_D - 2.5 2.5 A IIC - 2.0 2.0 mA IINACT_A -150 150 nA IINACT_AD - 2.5 2.5 A VSS - VSSA - 100 100 mV VRL VSSA - 0.1 VSSA + 0.1 V VRL - VSSA -100 100 mV VRH VDDA - 0.1 VDDA + 0.1 V VRH - VRL 4.5 5.25 V IACT_F Slow / medium I/O weak pullup/down current13 3.0-3.6 V 4.5-5.5 V 33 35 Min Fast I/O weak pullup current13 1.62-1.98 V 2.25-2.75 V 3.00-3.60 V Fast I/O weak pulldown current13 1.62-1.98 V 2.25-2.75 V 3.00-3.60 V 32 Symbol 36 VSS to VSSA differential voltage16 37 Analog reference low voltage 38 VRL differential voltage 39 Analog reference high voltage 40 VREF differential voltage 41 VSSSYN to VSS differential voltage VSSSYN - VSS -50 50 mV 42 VRCVSS to VSS differential voltage VRCVSS - VSS -50 50 mV 43 VDDF to VDD differential voltage VDDF - VDD -100 100 mV 43a VRC33 to VDDSYN differential voltage VRC33 - VDDSYN -0.1 0.117 V VIDIFF - 2.5 2.5 V TA = (TL to TH) TL TH -- -- 50 44 Analog input differential signal range (with common mode 2.5 V) 45 Operating temperature range, ambient (packaged) 46 Slew rate on power-supply pins C V/ms | VDDA0 - VDDA1 | must be < 0.1 V. MPC5554 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 15 Electrical Characteristics 2 VPP can drop to 3.0 V during read operations. If standby operation is not required, connect VSTBY to ground. 4 Applies to CLKOUT, external bus pins, and Nexus pins. 5 Maximum average RMS DC current. 6 Figure 3 shows an illustration of the I DD_STBY values interpolated for these temperature values. 7 Average current measured on Automotive benchmark. 8 Peak currents can be higher on specialized code. 9 High use current measured while running optimized SPE assembly code with all code and data 100% locked in cache (0% miss rate) with all channels of the eMIOS and eTPU running autonomously, plus the eDMA transferring data continuously from SRAM to SRAM. Higher currents are possible if an "idle" loop that crosses cache lines is run from cache. Write code that avoids this condition. 10 Figure 3 shows an illustration of the IDD_STBY values interpolated for these temperature values. 11 Power requirements for the VDD33 supply depend on the frequency of operation, load of all I/O pins, and the voltages on the I/O segments. Refer to Table 11 for values to calculate power dissipation for specific operation. 12 Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a particular I/O segment, and the voltage of the I/O segment. Refer to Table 10 for values to calculate power dissipation for specific operation. The total power consumption of an I/O segment is the sum of the individual power consumptions for each pin on the segment. 13 Absolute value of current, measured at V and V . IL IH 14 Weak pullup/down inactive. Measured at V = 3.6 V and VDDEH = 5.25 V. Applies to pad types: pad_fc, pad_sh, and pad_mh. DDE 15 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each 8 oC to 12 oC, in the ambient temperature range of 50 oC to 125 oC. Applies to pad types: pad_a and pad_ae. 16 V SSA refers to both VSSA0 and VSSA1. | VSSA0 - VSSA1 | must be < 0.1 V. 17 Up to 0.6 V during power up and power down. 3 MPC5554 Microcontroller Data Sheet, Rev. 2.0 16 Freescale Semiconductor Electrical Characteristics Figure 3 shows an approximate interpolation of the ISTBY worst-case specification to help estimate the values at different voltages and temperatures. Refer to the IDD_STBY specifications (27d) in Table 9. The vertical lines shown at 25 C, 60 C, and 150 C in Figure 3 are the actual specifications listed in Table 9. Istby vs. Junction Tem p 2000 1900 1800 1700 1600 1500 1400 A uA 1300 1200 1100 1000 0.8V 900 800 1.2V 1.0V 700 600 500 400 300 200 100 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Tem p (C) Figure 3. ISTBY Worst-case Specifications MPC5554 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 17 Electrical Characteristics 3.8.1 I/O Pad Current Specifications The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The power consumption is the sum of all output pin currents for a segment. The output pin current can be calculated from Table 10 based on the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 10. Table 10. I/O Pad Average DC Current (TA = TL - TH)1 Frequency (MHz) Load2 (pF) Voltage (V) Drive Select / Slew Rate Control Setting Current (mA) 25 50 5.25 11 8.0 10 50 5.25 01 3.2 2 50 5.25 00 0.7 4 2 200 5.25 00 2.4 5 50 50 5.25 11 17.3 Spec Pad Type Symbol 1 2 3 6 Slow IDRV_SH 20 50 5.25 01 6.5 3.33 50 5.25 00 1.1 8 3.33 200 5.25 00 3.9 9 66 10 3.6 00 2.8 10 66 20 3.6 01 5.2 11 66 30 3.6 10 8.5 7 Medium IDRV_MH 12 66 50 3.6 11 11.0 13 66 10 1.98 00 1.6 14 66 20 1.98 01 2.9 15 66 30 1.98 10 4.2 16 66 50 1.98 11 6.7 17 56 10 3.6 00 2.4 18 56 20 3.6 01 4.4 19 56 30 3.6 10 7.2 20 56 50 3.6 11 9.3 56 10 1.98 00 1.3 22 56 20 1.98 01 2.5 23 56 30 1.98 10 3.5 24 56 50 1.98 11 5.7 25 40 10 3.6 00 1.7 26 40 20 3.6 01 3.1 27 40 30 3.6 10 5.1 21 Fast IDRV_FC 28 40 50 3.6 11 6.6 29 40 10 1.98 00 1.0 30 40 20 1.98 01 1.8 31 40 30 1.98 10 2.5 32 40 50 1.98 11 4.0 1 These values are estimates from simulation and are not tested. Currents apply to output pins only. 2 All loads are lumped. MPC5554 Microcontroller Data Sheet, Rev. 2.0 18 Freescale Semiconductor Electrical Characteristics 3.8.2 I/O Pad VDD33 Current Specifications The power consumption of the VDD33 supply dependents on the usage of the pins on all I/O segments. The power consumption is the sum of all input and output pin VDD33 currents for all I/O segments. The output pin VDD33 current can be calculated from Table 11 based on the voltage, frequency, and load on all fast (pad_fc) pins. The input pin VDD33 current can be calculated from Table 11 based on the voltage, frequency, and load on all pad_sh and pad_mh pins. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 11. Table 11. VDD33 Pad Average DC Current (TA = TL - TH)1 Spec Pad Type Symbol Frequency (MHz) Load2 (pF) VDD33 (V) VDDE (V) Drive Select Current (mA) Inputs 1 Slow I33_SH 66 0.5 3.6 5.5 NA 0.003 2 Medium I33_MH 66 0.5 3.6 5.5 NA 0.003 3 66 10 3.6 3.6 00 0.35 4 66 20 3.6 3.6 01 0.53 5 66 30 3.6 3.6 10 0.62 6 66 50 3.6 3.6 11 0.79 7 66 10 3.6 1.98 00 0.35 8 66 20 3.6 1.98 01 0.44 9 66 30 3.6 1.98 10 0.53 10 66 50 3.6 1.98 11 0.7 11 56 10 3.6 3.6 00 0.30 12 56 20 3.6 3.6 01 0.45 13 56 30 3.6 3.6 10 0.52 Outputs 14 56 50 3.6 3.6 11 0.67 56 10 3.6 1.98 00 0.30 16 56 20 3.6 1.98 01 0.37 17 56 30 3.6 1.98 10 0.45 18 56 50 3.6 1.98 11 0.60 19 40 10 3.6 3.6 00 0.21 20 40 20 3.6 3.6 01 0.31 21 40 30 3.6 3.6 10 0.37 15 Fast I33_FC 22 40 50 3.6 3.6 11 0.48 23 40 10 3.6 1.98 00 0.21 24 40 20 3.6 1.98 01 0.27 25 40 30 3.6 1.98 10 0.32 26 40 50 3.6 1.98 11 0.42 1 These values are estimated from simulation and not tested. Currents apply to output pins for the fast pads only and to input pins for the slow and medium pads only. 2 All loads are lumped. MPC5554 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 19 Electrical Characteristics 3.9 Oscillator and FMPLL Electrical Characteristics Table 12. FMPLL Electrical Specifications (VDDSYN = 3.0-3.6 V; VSS = VSSSYN = 0.0 V; TA = TL to TH) Spec Characteristic Symbol Minimum Maximum fref_crystal fref_ext fref_1:1 8 8 24 20 20 fsys / 2 Unit 1 PLL reference frequency range:1 Crystal reference External reference Dual controller (1:1 mode) 2 System frequency 2 fsys fICO(MIN) / 2RFD fMAX 3 MHz 3 System clock period tCYC -- 1 / fsys ns 4 Loss of reference frequency 4 fLOR 100 1000 kHz 5 Self-clocked mode (SCM) frequency 5 fSCM 7.4 17.5 MHz EXTAL input high voltage crystal mode 6 VIHEXT VXTAL + 0.4 V -- V All other modes (dual controller (1:1), bypass, external reference) VIHEXT (VDDE5 / 2) + 0.4 V -- V EXTAL input low voltage crystal mode 7 VILEXT -- VXTAL - 0.4 V V All other modes [dual controller (1:1), bypass, external reference] VILEXT -- (VDDE5 / 2) - 0.4 V V IXTAL 0.8 3 mA 6 7 MHz 8 XTAL current 8 9 Total on-chip stray capacitance on XTAL CS_XTAL -- 1.5 pF 10 Total on-chip stray capacitance on EXTAL CS_EXTAL -- 1.5 pF 11 Crystal manufacturer's recommended capacitive load CL Refer to crystal specification Refer to crystal specification pF Discrete load capacitance to connect to EXTAL CL_EXTAL -- (2 x CL) - CS_EXTAL - CPCB_EXTAL9 pF Discrete load capacitance to connect to XTAL CL_XTAL -- (2 x CL) - CS_XTAL - CPCB_XTAL9 pF tlpll -- 750 s tskew -2 2 ns 12 13 14 PLL lock time10 15 Dual controller (1:1) clock skew (between CLKOUT and EXTAL) 11, 12 16 Duty cycle of reference tDC 40 60 % 17 Frequency unLOCK range fUL -4.0 4.0 % fSYS 18 Frequency LOCK range fLCK -2.0 2.0 % fSYS MPC5554 Microcontroller Data Sheet, Rev. 2.0 20 Freescale Semiconductor Electrical Characteristics Table 12. FMPLL Electrical Specifications (continued) (VDDSYN = 3.0-3.6 V; VSS = VSSSYN = 0.0 V; TA = TL to TH) Spec Characteristic 19 CLKOUT period jitter,13, 14 measured at fSYS maximum: Peak-to-peak jitter (clock edge to clock edge) Long term jitter (averaged over a 2 ms interval) 20 Frequency modulation range limit 15 (do not exceed fsys maximum) 21 ICO frequency fico = [ fref_crystal x (MFD + 4) ] / (PREDIV + 1)16 fico = [ fref_ext x (MFD + 4) ] / (PREDIV + 1) 22 Predivider output frequency (to PLL) Symbol Minimum Maximum Unit -- -- 5.0 0.01 CMOD 0.8 2.4 %fSYS fico 48 fMAX MHz fPREDIV 4 2017 MHz CJITTER % fCLKOUT 1 Nominal crystal and external reference values are worst-case not more than 1%. The device operates correctly if the frequency remains within 5% of the specification limit. This tolerance range allows for a slight frequency drift of the crystals over time. The designer must thoroughly understand the drift margin of the source clock. 2 All internal registers retain data at 0 Hz. 3 Up to the maximum frequency rating of the device (refer to Table 1). 4 Loss of reference frequency is defined as the reference frequency detected internally, which transitions the PLL into self-clocked mode. 5 The PLL operates at self-clocked mode (SCM) frequency when the reference frequency falls below f LOR. SCM frequency is measured on the CLKOUT ball with the divider set to divide-by-two of the system clock. NOTE: In SCM, the MFD and PREDIV have no effect and the RFD is bypassed. 6 Use the EXTAL input high voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or resonators). (Vextal - Vxtal) must be 400 mV for the oscillator's comparator to produce the output clock. 7 Use the EXTAL input low voltage parameter when using the FlexCAN oscillator in crystal mode (no quartz crystals or resonators). (Vxtal - Vextal) must be 400 mV for the oscillator's comparator to produce the output clock. 8 I xtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded. 9 C PCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively. 10 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). From power up with crystal oscillator reference, the lock time also includes the crystal startup time. 11 PLL is operating in 1:1 PLL mode. 12 VDDE = 3.0-3.6 V. 13 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f . sys Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the jitter percentage for a given interval. CLKOUT divider is set to divide-by-two. 14 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of (jitter + Cmod). 15 Modulation depth selected must not result in fsys value greater than the fsys maximum specified value. RFD) sys = fico / (2 16 f 17 Maximum value for dual controller (1:1) mode is (fMAX / 2) with the predivider set to 1 (FMPLL_SYNCR[PREDIV] = 0b001). MPC5554 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 21 Electrical Characteristics 3.10 eQADC Electrical Characteristics Table 13. eQADC Conversion Specifications (TA = TL to TH) Spec Characteristic Symbol Minimum Maximum Unit FADCLK 1 12 MHz 13 + 2 (15) 14 + 2 (16) 13 + 128 (141) 14 + 128 (142) 1 ADC clock (ADCLK) frequency1 Conversion cycles Differential Single ended CC 2 3 Stop mode recovery time2 ADCLK cycles TSR 10 -- s 4 Resolution 3 -- 1.25 -- mV 5 INL: 6 MHz ADC clock INL6 -4 4 Counts3 6 INL: 12 MHz ADC clock INL12 -8 7 8 9 10 DNL: 6 MHz ADC clock DNL: 12 MHz ADC clock Offset error with calibration Full-scale gain error with calibration current 7, 8, 9, 10 8 Counts DNL6 -3 4 34 Counts DNL12 -6 4 64 Counts OFFWC -4 5 4 5 Counts GAINWC -8 6 86 Counts IINJ -1 1 mA 11 Disruptive input injection 12 Incremental error due to injection current. All channels are 10 k < Rs <100 k Channel under test has Rs = 10 k, IINJ = IINJMAX, IINJMIN EINJ -4 4 Counts 13 Total Unadjusted Error for single ended conversions with calibration11, 12, 13, 14, 15 TUE -4 4 Counts 1 Conversion characteristics vary with FADCLK rate. Reduced conversion accuracy occurs at maximum FADCLK rate. The maximum value is based on 800 KS/s and the minimum value is based on 20 MHz oscillator clock frequency divided by a maximum 16 factor. 2 Stop mode recovery time begins when the ADC control register enable bits are set until the ADC is ready to perform conversions. 3 At V RH - VRL = 5.12 V, one least significant bit (LSB) = 1.25, mV = one count. 4 Guaranteed 10-bit mono tonicity. 5 The absolute value of the offset error without calibration 100 counts. 6 The absolute value of the full scale gain error without calibration 120 counts. 7 Below disruptive current conditions, the channel being stressed has conversion values of: 0x3FF for analog inputs greater than VRH, and 0x000 for values less than VRL. This assumes that VRH VDDA and VRL VSSA due to the presence of the sample amplifier. Other channels are not affected by non-disruptive conditions. 8 Exceeding the limit can cause a conversion error on both stressed and unstressed channels. Transitions within the limit do not affect device reliability or cause permanent damage. 9 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values using VPOSCLAMP = VDDA + 0.5 V and VNEGCLAMP = - 0.3 V, then use the larger of the calculated values. 10 This condition applies to two adjacent pads on the internal pad. 11 The TUE specification is always less than the sum of the INL, DNL, offset, and gain errors due to canceling errors. 12 TUE does not apply to differential conversions. 13 Measured at 6 MHz ADC clock. TUE with a 12 MHz ADC clock is: -16 counts < TUE < 16 counts. 14 TUE includes all internal device errors such as internal reference variation (75% Ref, 25% Ref). 15 Depending on the input impedance, the analog input leakage current (Table 9. DC Electrical Specifications, spec 35a) can affect the actual TUE measured on analog channels AN[12], AN[13], AN[14], AN[15]. MPC5554 Microcontroller Data Sheet, Rev. 2.0 22 Freescale Semiconductor Electrical Characteristics 3.11 Spec Table 14. Flash Program and Erase Specifications (TA = TL to TH) Spec 3 1 2 3 4 5 6 H7Fa Flash Memory Electrical Characteristics Flash Program Characteristic Doubleword (64 bits) program time4 Symbol Min Typical1 Initial Max2 Max3 Unit Tdwprogram -- 10 -- 500 s Tpprogram -- 22 44 500 s 16 KB block pre-program and erase time T16kpperase -- 265 400 5000 ms 9 48 KB block pre-program and erase time T48kpperase -- 345 400 5000 ms 10 64 KB block pre-program and erase time T64kpperase -- 415 500 5000 ms 8 128 KB block pre-program and erase time T128kpperase -- 500 1250 7500 ms 11 Minimum operating frequency for program and erase operations6 -- 25 -- -- -- MHz 4 4 Page program time 7 5 Typical program and erase times assume nominal supply values and operation at 25 oC. Initial factory condition: 100 program/erase cycles, 25 oC, using a typical supply voltage measured at a minimum system frequency of 80 MHz. The maximum erase time occurs after the specified number of program/erase cycles. This maximum value is characterized but not guaranteed. Actual hardware programming times. This does not include software overhead. Page size is 256 bits (8 words). The read frequency of the flash can range up to the maximum operating frequency of the device. There is no minimum read frequency condition. Table 15. Flash EEPROM Module Life (TA = TL to TH) Spec 1 Characteristic Symbol Min. Typical1 Unit -- cycles 1a Number of program/erase cycles per block for 16 KB, 48 KB, and 64 KB blocks over the operating temperature range (TJ) P/E 100,000 1b Number of program/erase cycles per block for 128 KB blocks over the operating temperature range (TJ) P/E 1000 2 Data retention Blocks with 0-1,000 P/E cycles Blocks with 1,001-100,000 P/E cycles 100,000 cycles Retention 20 5 -- -- years Typical endurance is evaluated at 25o C. Product qualification is performed to the minimum specification. For additional information on the Freescale definition of typical endurance, refer to engineering bulletin EB619 Typical Endurance for Nonvolatile Memory. MPC5554 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 23 Electrical Characteristics Table 16 shows the FLASH_BIU settings versus frequency of operation. Refer to the device reference manual for definitions of these bit fields. Table 16. FLASH_BIU Settings vs. Frequency of Operation1 Maximum Frequency (MHz) DPFEN2 IPFEN2 PFLIM3 BFEN4 0b01 0b00 0b01 0b11 0b00 0b01 0b11 0b000 to 0b110 0b0 0b1 0b010 0b01 0b00 0b01 0b11 0b00 0b01 0b11 0b000 to 0b110 0b0 0b1 0b010 0b011 0b01 0b00 0b01 0b11 0b00 0b01 0b11 0b000 to 0b110 0b0 0b1 0b111 0b111 0b11 0b00 0b00 0b000 0b0 APC RWSC WWSC Up to and including 82 MHz5 0b001 0b001 Up to and including 102 MHz 6 0b001 Up to and including 132 MHz 7 Default setting after reset 1 2 3 4 5 6 7 Illegal combinations exist. Use entries from the same row in this table. For maximum flash performance, set to 0b11. For maximum flash performance, set to 0b110. For maximum flash performance, set to 0b1. 82 MHz parts allow for 80 MHz system clock + 2% frequency modulation (FM). 102 MHz parts allow for 100 MHz system clock + 2% FM. 132 MHz parts allow for 128 MHz system clock + 2% FM. 3.12 3.12.1 AC Specifications Pad AC Specifications Table 17. Pad AC Specifications (VDDEH = 5.0 V, VDDE = 1.8 V)1 Spec SRC / DSC (binary) Pad 11 1 Slow high voltage (SH) 01 00 11 2 Medium high voltage (MH) 01 00 Out Delay2, 3, 4 (ns) Rise / Fall4, 5 (ns) Load Drive (pF) 26 15 50 82 60 200 75 40 50 137 80 200 377 200 50 476 260 200 16 8 50 43 30 200 34 15 50 61 35 200 192 100 50 239 125 200 MPC5554 Microcontroller Data Sheet, Rev. 2.0 24 Freescale Semiconductor Electrical Characteristics Table 17. Pad AC Specifications (VDDEH = 5.0 V, VDDE = 1.8 V)1 (continued) Spec Out Delay2, 3, 4 (ns) SRC / DSC (binary) Pad Rise / Fall4, 5 (ns) Load Drive (pF) 2.7 10 2.5 20 2.4 30 2.3 50 00 3 01 Fast 3.1 10 11 1 2 3 4 5 4 Pullup/down (3.6 V max) -- -- 7500 50 5 Pullup/down (5.5 V max) -- -- 9000 50 These are worst-case values that are estimated from simulation (not tested). The values in the table are simulated at: VDD = 1.35-1.65 V; VDDE = 1.62-1.98 V; VDDEH = 4.5-5.5 V; VDD33 and VDDSYN = 3.0-3.6 V; and TA = TL to TH. This parameter is supplied for reference and is guaranteed by design (not tested). The output delay is shown in Figure 4. To calculate the output delay with respect to the system clock, add a maximum of one system clock to the output delay. The output delay and rise and fall are measured to 20% or 80% of the respective signal. This parameter is guaranteed by characterization rather than 100% tested. Table 18. De-rated Pad AC Specifications (VDDEH = 3.3 V, VDDE = 3.3 V)1 Spec SRC/DSC (binary) Pad 11 1 Slow high voltage (SH) 01 00 11 2 Medium high voltage (MH) 01 00 Out Delay2, 3, 4 (ns) Rise / Fall 3, 5 (ns) Load Drive (pF) 39 23 50 120 87 200 101 52 50 188 111 200 507 248 50 597 312 200 23 12 50 64 44 200 50 22 50 90 50 200 261 123 50 305 156 200 2.4 10 2.2 20 2.1 30 2.1 50 00 3 01 Fast 10 3.2 11 4 Pullup/down (3.6 V max) -- -- 7500 50 5 Pullup/down (5.5 V max) -- -- 9500 50 1 These are worst-case values that are estimated from simulation (not tested). The values in the table are simulated at: VDD = 1.35-1.65 V; VDDE = 3.0-3.6 V; VDDEH = 3.0-3.6 V; VDD33 and VDDSYN = 3.0-3.6 V; and TA = TL to TH. 2 This parameter is supplied for reference and guaranteed by design (not tested). MPC5554 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 25 Electrical Characteristics 3 The output delay, and the rise and fall, are calculated to 20% or 80% of the respective signal. The output delay is shown in Figure 4. To calculate the output delay with respect to the system clock, add a maximum of one system clock to the output delay. 5 This parameter is guaranteed by characterization rather than 100% tested. 4 VDD / 2 Pad internal data input signal Rising-edge out delay Falling-edge out delay VOH Pad output VOL Figure 4. Pad Output Delay 3.13 AC Timing 3.13.1 Reset and Configuration Pin Timing Table 19. Reset and Configuration Pin Timing1 Spec 1 Characteristic Symbol Min Max Unit 1 RESET pulse width tRPW 10 -- tCYC 2 RESET glitch detect pulse width tGPW 2 -- tCYC 3 PLLCFG, BOOTCFG, WKPCFG, RSTCFG setup time to RSTOUT valid tRCSU 10 -- tCYC 4 PLLCFG, BOOTCFG, WKPCFG, RSTCFG hold time from RSTOUT valid tRCH 0 -- tCYC Reset timing specified at: VDDEH = 3.0-5.25 V; VDD = 1.35-1.65 V; and TA = TL to TH. MPC5554 Microcontroller Data Sheet, Rev. 2.0 26 Freescale Semiconductor Electrical Characteristics 2 RESET 1 RSTOUT 3 PLLCFG BOOTCFG RSTCFG WKPCFG 4 Figure 5. Reset and Configuration Pin Timing 3.13.2 IEEE 1149.1 Interface Timing Table 20. JTAG Pin AC Electrical Characteristics1 Spec 1 Characteristic Symbol Min Max Unit 1 TCK cycle time tJCYC 100 -- ns 2 TCK clock pulse width (measured at VDDE / 2) tJDC 40 60 ns 3 TCK rise and fall times (40% to 70%) tTCKRISE -- 3 ns 4 TMS, TDI data setup time tTMSS, tTDIS 5 -- ns 5 TMS, TDI data hold time tTMSH, tTDIH 25 -- ns 6 TCK low to TDO data valid tTDOV -- 20 ns 7 TCK low to TDO data invalid tTDOI 0 -- ns 8 TCK low to TDO high impedance tTDOHZ -- 20 ns 9 JCOMP assertion time tJCMPPW 100 -- ns 10 JCOMP setup time to TCK low tJCMPS 40 -- ns 11 TCK falling-edge to output valid tBSDV -- 50 ns 12 TCK falling-edge to output valid out of high impedance tBSDVZ -- 50 ns 13 TCK falling-edge to output high impedance (Hi-Z) tBSDHZ -- 50 ns 14 Boundary scan input valid to TCK rising-edge tBSDST 50 -- ns 15 TCK rising-edge to boundary scan input invalid tBSDHT 50 -- ns These specifications apply to JTAG boundary scan only. JTAG timing specified at VDD = 1.35-1.65 V, VDDE = 3.0-3.6 V, VDD33 and VDDSYN = 3.0-3.6 V, and TA = TL to TH. Refer to Table 21 for Nexus specifications. MPC5554 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 27 Electrical Characteristics TCK 2 3 2 1 3 Figure 6. JTAG Test Clock Input Timing TCK 4 5 TMS, TDI 6 7 8 TDO Figure 7. JTAG Test Access Port Timing MPC5554 Microcontroller Data Sheet, Rev. 2.0 28 Freescale Semiconductor Electrical Characteristics TCK 10 JCOMP 9 Figure 8. JTAG JCOMP Timing MPC5554 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 29 Electrical Characteristics TCK 11 13 Output signals 12 Output signals 14 15 Input signals Figure 9. JTAG Boundary Scan Timing MPC5554 Microcontroller Data Sheet, Rev. 2.0 30 Freescale Semiconductor Electrical Characteristics 3.13.3 Nexus Timing Table 21. Nexus Debug Port Timing1 Spec Characteristic 1 MCKO cycle time 2 MCKO duty cycle 3 MCKO low to MDO data valid 3 3 3 5 Unit tMCYC 22 8 tCYC tMDC 40 60 % tMDOV -1.5 3.0 ns tMSEOV -1.5 3.0 ns 5 3 MCKO low to EVTO data valid tEVTOV -1.5 3.0 ns 6 EVTI pulse width tEVTIPW 4.0 -- tTCYC 7 EVTO pulse width tEVTOPW 1 -- tMCYC 4 8 TCK cycle time tTCYC 4 -- tCYC 9 TCK duty cycle tTDC 40 60 % 10 TDI, TMS data setup time tNTDIS, tNTMSS 8 -- ns 11 TDI, TMS data hold time tNTDIH, tNTMSH 5 -- ns VDDE = 2.25-3.0 V 0 12 ns VDDE = 3.0-3.6 V 0 10 ns -- -- -- 13 4 Max MCKO low to MSEO data valid 12 2 Min 4 TCK low to TDO data valid 1 Symbol RDY valid to tJOV MCKO5 -- JTAG specifications apply when used for debug functionality. All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified at VDD = 1.35-1.65 V, VDDE = 2.25-3.6 V, VDD33 and VDDSYN = 3.0-3.6 V, TA = TL to TH, and CL = 30 pF with DSC = 0b10. The Nexus AUX port runs up to 82 MHz. MDO, MSEO, and EVTO data is held valid until the next MCKO low cycle occurs. Limit the maximum frequency to approximately 16 MHz (VDDE = 2.25-3.0 V) or 20 MHz (VDDE = 3.0-3.6 V) to meet the timing specification for tJOV of [0.2 x tJCYC] as outlined in the IEEE-ISTO 5001-2003 specification. The RDY pin timing is asynchronous to MCKO and is guaranteed by design to function correctly. 1 2 MCKO 4 3 5 MDO MSEO EVTO Output Data Valid Figure 10. Nexus Output Timing MPC5554 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 31 Electrical Characteristics TCK 10 11 TMS, TDI 12 TDO Figure 11. Nexus TDI, TMS, TDO Timing 3.13.4 External Bus Interface (EBI) Timing Table 22 lists the timing information for the external bus: Table 22. Bus Operation Timing1 Spec Characteristic and Description 1 CLKOUT period 2 CLKOUT duty cycle 3 4 CLKOUT rise time CLKOUT fall time External Bus Frequency 2 Symbol 40 MHz 56 MHz 67 MHz Unit Min Max Min Max Min Max TC 24.4 -- 17.5 -- 15.2 -- ns tCDC 45% 55% 45% 55% 45% 55% TC -- --3 -- --3 -- --3 ns -- --3 -- --3 -- --3 ns tCRT tCFT Notes Signals are measured at 50% VDDE. MPC5554 Microcontroller Data Sheet, Rev. 2.0 32 Freescale Semiconductor Electrical Characteristics Table 22. Bus Operation Timing1 (continued) Spec Characteristic and Description CLKOUT positive edge to output signal invalid or Hi-Z (hold time) 5 Symbol 40 MHz Min tCOH Max 1.06 56 MHz Min Max 1.06 -- 1.5 67 MHz Min Unit 1.06 -- 1.5 Notes Max EBTS = 0 -- ns 1.5 EBTS = 1 External bus interface ADDR[8:31] BG4 BR5 BB CS[0:3] DATA[0:31] BDIP OE RD_WR TA TEA TS TSIZ[0:1] WE/BE[0:3] CLKOUT positive edge to output signal valid (output delay) 6 External Bus Frequency 2 Hold time selectable via SIU_ECCR [EBTS] bit. 10.06 tCOV 7.56 -- -- 11.0 6.06 -- 8.5 EBTS = 0 ns 7.0 EBTS = 1 Output valid time selectable via SIU_ECCR [EBTS] bit. External bus interface ADDR[8:31] BG 4 BR 5 BB CS[0:3] DATA[0:31] BDIP OE RD_WR TA TEA TS TSIZ[0:1] WE/BE[0:3] MPC5554 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 33 Electrical Characteristics Table 22. Bus Operation Timing1 (continued) Spec Characteristic and Description External Bus Frequency 2 Symbol 40 MHz 56 MHz 67 MHz Unit Min Max Min Max Min Max tCIS 10.0 -- 7.0 -- 5.0 -- ns tCIH 1.0 -- 1.0 -- 1.0 -- ns Notes Input signal valid to CLKOUT positive edge (setup time) 7 External bus interface ADDR[8:31] BG 5 BR 4 BB DATA[0:31] BDIP OE RD_WR TA TEA TS TSIZ[0:1] WE/BE[0:3] CLKOUT positive edge to input signal invalid (hold time) 8 1 2 3 4 5 6 External bus interface ADDR[8:31] BG 5 BR 4 BB DATA[0:31] BDIP OE RD_WR TA TEA TS TSIZ[0:1] WE/BE[0:3] EBI timing specified at: VDD = 1.35-1.65 V; VDDE = 1.6-3.6 V (unless stated otherwise); VDD33 and VDDSYN = 3.0-3.6 V; TA = TL to TH; and CL = 30 pF with DSC = 0b10. The external bus is limited to half the speed of the internal bus. Refer to fast pad timing in Table 17 and Table 18 (different values for 1.8 V and 3.3 V). Internal arbitration. External arbitration. The EBTS = 0 timings are tested and valid at VDDE = 2.25-3.6 V only, whereas EBTS = 1 timings are tested and valid at VDDE = 1.6-3.6 V. MPC5554 Microcontroller Data Sheet, Rev. 2.0 34 Freescale Semiconductor Electrical Characteristics Voh_f VDDE / 2 CLKOUT Vol_f 2 3 2 4 1 Figure 12. CLKOUT Timing VDDE / 2 CLKOUT 6 5 VDDE / 2 5 Output bus VDDE / 2 6 5 5 Output signal VDDE / 2 6 Output signal VDDE / 2 Figure 13. Synchronous Output Timing MPC5554 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 35 Electrical Characteristics CLKOUT VDDE / 2 7 8 Input bus VDDE / 2 7 8 Input signal VDDE / 2 Figure 14. Synchronous Input Timing 3.13.5 External Interrupt Timing (IRQ Signals) Table 23. External Interrupt Timing1 Spec 1 IRQ pulse-width low 2 IRQ pulse-width high 3 1 2 Characteristic 2 IRQ edge-to-edge time Symbol Min Max Unit tIPWL 3 -- tCYC TIPWH 3 -- tCYC tICYC 6 -- tCYC IRQ timing specified at: VDD = 1.35-1.65 V; VDDEH = 3.0-5.5 V; and TA = TL to TH. Applies when IRQ signals are configured for rising-edge or falling-edge events, but not both. MPC5554 Microcontroller Data Sheet, Rev. 2.0 36 Freescale Semiconductor Electrical Characteristics IRQ 2 1 3 Figure 15. External Interrupt Timing 3.13.6 eTPU Timing Table 24. eTPU Timing1 Spec 1 2 1 2 Characteristic eTPU input channel pulse width eTPU output channel pulse width Symbol Min Max Unit tICPW 4 -- tCYC tOCPW 22 -- tCYC eTPU timing specified at: VDDEH = 3.0-5.5 V; and TA = TL to TH. This specification does not include the rise and fall times. When calculating the minimum eTPU pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR). 2 eTPU output eTPU input and TCRCLK 1 Figure 16. eTPU Timing MPC5554 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 37 Electrical Characteristics 3.13.7 eMIOS Timing Table 25. eMIOS Timing1 Spec 1 2 Symbol Min Max Unit tMIPW 4 -- tCYC tMOPW 2 -- tCYC eMIOS input pulse width 2 1 Characteristic eMIOS output pulse width 1 eMIOS timing specified at: VDDEH = 3.0-5.5 V; and TA = TL to TH. This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the rise and fall times defined in the slew rate control field (SRC) in the pad configuration register (PCR). 2 eMIOS output eMIOS input 1 Figure 17. eMIOS Timing 3.13.8 DSPI Timing Table 26. DSPI Timing1 80 MHz Characteristic Spec 1 2 3 SCK cycle time2, 3 PCS to SCK After SCK 112 MHz 132 MHz Symbol delay4 delay5 Unit Min Max Min Max Min Max tSCK 25 ns 2.9 ms 17.9 ns 2.0 ms 15.2 ns 1.7 ms -- tCSC 23 -- 15 -- 13 -- ns 12 -- ns tASC 22 -- 14 -- tSDC (tSCK / 2) - 2 ns (tSCK / 2) + 2 ns (tSCK / 2) - 2 ns (tSCK / 2) + 2 ns tA -- 25 -- 25 -- 25 ns tDIS -- 25 -- 25 -- 25 ns (tSCK / 2) (tSCK / 2) - 2 ns + 2 ns 4 SCK duty cycle 5 Slave access time (SS active to SOUT driven) 6 Slave SOUT disable time (SS inactive to SOUT Hi-Z, or invalid) 7 PCSx to PCSS time tPCSC 4 -- 4 -- 4 -- ns 8 PCSS to PCSx time tPASC 5 -- 5 -- 5 -- ns ns MPC5554 Microcontroller Data Sheet, Rev. 2.0 38 Freescale Semiconductor Electrical Characteristics Table 26. DSPI Timing1 (continued) 80 MHz Spec 1 2 3 4 5 6 Characteristic 112 MHz 132 MHz Symbol tSUI 9 Data setup time for inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)6 Master (MTFE = 1, CPHA = 1) tHI 10 Data hold time for inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)6 Master (MTFE = 1, CPHA = 1) tSUO 11 Data valid (after SCK edge) Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) tHO 12 Data hold time for outputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) Unit Min Max Min Max Min Max 20 2 -4 20 -- -- -- -- 20 2 3 20 -- -- -- -- 20 2 6 20 -- -- -- -- ns ns ns ns -4 7 21 -4 -- -- -- -- -4 7 14 -4 -- -- -- -- -4 7 12 -4 -- -- -- -- ns ns ns ns -- -- -- -- 5 25 18 5 -- -- -- -- 5 25 14 5 -- -- -- -- 5 25 13 5 ns ns ns ns -5 5.5 8 -5 -- -- -- -- -5 5.5 4 -5 -- -- -- -- -5 5.5 3 -5 -- -- -- -- ns ns ns ns All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type M or MH. DSPI signals using pad types of S or SH have an additional delay based on the slew rate. DSPI timing is specified at: VDDEH = 3.0-5.5 V;TA = TL to TH; and CL = 50 pF with SRC = 0b11. The minimum SCK cycle time restricts the baud rate selection for the given system clock rate. These numbers are calculated based on two MPC55xx devices communicating over a DSPI link. The actual minimum SCK cycle time is limited by pad performance. The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. This number is calculated using the SMPL_PT field in DSPI_MCR set to 0b10. MPC5554 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 39 Electrical Characteristics 2 3 PCSx 1 4 SCK output (CPOL=0) 4 SCK output (CPOL=1) 9 SIN 10 First data Last data Data 12 SOUT First data 11 Data Last data Figure 18. DSPI Classic SPI Timing--Master, CPHA = 0 PCSx SCK output (CPOL=0) 10 SCK output (CPOL=1) 9 SIN Data First data 12 SOUT First data Last data 11 Data Last data Figure 19. DSPI Classic SPI Timing--Master, CPHA = 1 MPC5554 Microcontroller Data Sheet, Rev. 2.0 40 Freescale Semiconductor Electrical Characteristics 3 2 SS 1 4 SCK input (CPOL=0) 4 SCK input (CPOL=1) 5 First data SOUT 9 6 Data Last data Data Last data 10 First data SIN 11 12 Figure 20. DSPI Classic SPI Timing--Slave, CPHA = 0 SS SCK input (CPOL=0) SCK input (CPOL=1) 11 5 12 SOUT First data 9 SIN Data Last data Data Last data 6 10 First data Figure 21. DSPI Classic SPI Timing--Slave, CPHA = 1 MPC5554 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 41 Electrical Characteristics 3 PCSx 4 1 2 SCK output (CPOL=0) 4 SCK output (CPOL=1) 9 SIN 10 First data Last data Data 12 SOUT 11 First data Last data Data Figure 22. DSPI Modified Transfer Format Timing--Master, CPHA = 0 PCSx SCK output (CPOL=0) SCK output (CPOL=1) 10 9 SIN First data Data 12 SOUT First data Data Last data 11 Last data Figure 23. DSPI Modified Transfer Format Timing--Master, CPHA = 1 MPC5554 Microcontroller Data Sheet, Rev. 2.0 42 Freescale Semiconductor Electrical Characteristics 3 2 SS 1 SCK input (CPOL=0) 4 4 SCK input (CPOL=1) 12 11 5 First data SOUT Data Last data 10 9 Data First data SIN 6 Last data Figure 24. DSPI Modified Transfer Format Timing--Slave, CPHA = 0 SS SCK input (CPOL=0) SCK input (CPOL=1) 11 5 6 12 First data SOUT 9 Last data Data Last data 10 First data SIN Data Figure 25. DSPI Modified Transfer Format Timing--Slave, CPHA = 1 7 8 PCSS PCSx Figure 26. DSPI PCS Strobe (PCSS) Timing MPC5554 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 43 Electrical Characteristics 3.13.9 eQADC SSI Timing Table 27. EQADC SSI Timing Characteristics Spec Rating Symbol Minimum Typical Maximum Unit tFCK 2 -- 17 tSYS_CLK 2 FCK period (tFCK = 1 / fFCK) 1, 2 3 Clock (FCK) high time tFCKHT tSYS_CLK - 6.5 -- 9 x (tSYS_CLK + 6.5) ns 4 Clock (FCK) low time tFCKLT tSYS_CLK - 6.5 -- 8 x (tSYS_CLK + 6.5) ns 5 SDS lead / lag time tSDS_LL -7.5 -- +7.5 ns 6 SDO lead / lag time tSDO_LL -7.5 -- +7.5 ns 7 EQADC data setup time (inputs) tEQ_SU 22 -- -- ns 8 EQADC data hold time (inputs) tEQ_HO 1 -- -- ns 1 SS timing specified at VDDEH = 3.0-5.5 V, TA = TL to TH, and CL = 25 pF with SRC = 0b11. Maximum operating frequency varies depending on track delays, master pad delays, and slave pad delays. 2 FCK duty cycle is not 50% when it is generated through the division of the system clock by an odd number. 2 3 4 FCK 5 4 SDS 25th 6 SDO 1st (MSB) 5 2nd 26th External device data sample at FCK falling-edge 8 7 SDI 1st (MSB) 2nd 25th 26th EQADC data sample at FCK rising-edge Figure 27. EQADC SSI Timing MPC5554 Microcontroller Data Sheet, Rev. 2.0 44 Freescale Semiconductor Mechanicals 4 Mechanicals 4.1 MPC5554 416 PBGA Pinouts Figure 28, Figure 29, and Figure 30 show the pinout for the MPC5554 416 PBGA package. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A VSS VSTBY AN37 AN11 VDDA1 AN16 AN1 AN5 VRH AN23 AN27 AN28 AN35 VSSA0 AN15 ETRIG ETPUB ETPUB ETPUB ETPUB 1 18 20 24 27 B VDD VSS AN36 AN39 AN19 AN20 AN0 AN4 REF BYPC AN22 AN26 AN31 AN32 VSSA0 AN14 ETRIG ETPUB ETPUB ETPUB ETPUB MDO10 MDO7 0 21 25 28 31 MDO4 VDD VSS AN8 AN17 VSSA1 AN21 AN3 AN7 VRL AN25 AN30 AN33 VDDA0 AN13 ETPUB ETPUB ETPUB ETPUB MDO9 19 22 26 30 MDO6 AN29 AN34 VDDEH AN12 9 ETPUB ETPUB ETPUB ETPUB MDO5 16 17 23 29 MDO2 VDDEH 8 C VDD33 ETPUA ETPUA D 30 31 E VDD ETPUA ETPUA VDDEH 28 29 1 VSS AN38 AN9 AN10 AN18 AN2 AN6 AN24 16 17 18 19 20 21 GPIO 205 22 23 24 25 26 VDD VDD33 VSS MDO0 VSS MDO1 VSS VDDE7 VDD C VSS VDDE7 TCK TDI D VDDE7 TMS TDO TEST E MDO11 MDO8 MDO3 VDD A VDDE7 B ETPUA ETPUA ETPUA VDDEH F 24 27 26 1 MSEO0 JCOMP EVTI EVTO F G ETPUA ETPUA ETPUA ETPUA 23 22 25 21 MSEO1 MCKO GPIO 204 ETPUB G 15 H ETPUA ETPUA ETPUA ETPUA 20 19 18 17 RDY ETPUA ETPUA ETPUA ETPUA J 16 15 14 13 K ETPUA ETPUA ETPUA ETPUA 12 11 10 9 VSS VSS VSS VSS L ETPUA ETPUA ETPUA ETPUA 8 7 6 5 VSS VSS VSS VSS VSS VSS VDDE7 ETPUB ETPUB ETPUB ETPUB L 6 4 3 2 VSS VDDE7 TCRCLK ETPUB ETPUB B 1 0 VSS VDDE7 SOUTB PCSB3 PCSB0 PCSB1 N VSS PCSA3 PCSB4 SCKB PCSB2 P VSS VDDE2 VDDE2 VSS VSS VSS VSS ETPUA TCRCLK 0 A VDDE2 VDDE2 VSS VSS VSS VSS VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS VSS VSS VSS BDIP TEA P CS3 CS2 CS1 CS0 R WE3 WE2 WE1 WE0 VDDE2 VDDE2 VDDE2 T VDDE2 TSIZ0 RD_WR VDDE2 U ADDR 16 V ADDR 18 ADDR W 20 ADDR 22 ADDR 21 ADDR VDDE2 11 ADDR AA 24 ADDR 23 ADDR 13 ADDR 12 AB VDDE2 ADDR 25 ADDR 15 ADDR 14 ADDR 26 ADDR 27 ADDR 31 VSS VDD DATA 26 DATA 28 VDDE2 ADDR AD 28 ADDR 30 DATA 25 DATA 27 Y AC TSIZ1 TA VDD33 ADDR 17 TS ADDR 8 ADDR 19 ADDR 9 ADDR 10 ETPUB ETPUB H 14 13 VSS ETPUB ETPUB ETPUB ETPUB K 10 8 7 5 VDDE7 VDDE7 VDDE7 VDDE7 ETPUA ETPUA ETPUA ETPUA M 4 3 2 1 N GPIO 203 VDDEH ETPUB ETPUB ETPUB J 6 12 11 9 M VSS VSS PCSB5 SOUTA VDDE2 VDDE2 VDDE2 VDDE2 VSS VSS PCSA1 PCSA0 PCSA2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VSS VSS PCSA4 TXDA PCSA5 VFLASH U VSS SINA SINB SCKA R VPP T CNTXC RXDA RSTOUT RST CFG V RXDB CNRXC TXDB RESET W Note: NC WKP CFG No connect. AC22 & AD23 reserved BOOT CFG1 VDDEH PLL 6 CFG1 DATA 30 DATA 31 DATA 8 DATA 10 VDDE2 DATA 12 DATA 29 DATA 9 DATA 11 DATA 13 DATA 15 DATA 14 EMIOS EMIOS EMIOS EMIOS VDDEH VDDE5 4 21 12 8 2 NC EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA VDDE5 3 22 17 15 10 6 VRC VSS VSS SYN Y BOOT EXTAL AA CFG0 VDD VRC CTL PLL CFG0 XTAL AB VSS VDD VRC33 VDD SYN AC NC VSS VDD VSS VDD DATA 24 VDD33 GPIO 207 AE ADDR 29 VSS VDD DATA 17 DATA 19 DATA 21 DATA 23 DATA 0 DATA 2 DATA 4 DATA 6 OE BR BG EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA VDDE5 CLKOUT VSS 23 1 19 16 13 9 5 VDD AE AF VSS VDD DATA 16 DATA 18 VDDE2 DATA 20 DATA 22 GPIO 206 DATA 1 DATA 3 VDDE2 DATA 5 DATA 7 BB EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB CNRXB VDDE5 20 0 18 14 11 7 4 ENG CLK VSS AF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 25 26 15 16 17 18 19 20 21 22 23 24 VDD33 AD Figure 28. MPC5554 416 Package MPC5554 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 45 Mechanicals 1 2 3 4 5 6 7 8 9 10 11 12 13 A VSS VSTBY AN37 AN11 VDDA1 AN16 AN1 AN5 VRH AN23 AN27 AN28 AN35 B VDD VSS AN36 AN39 AN19 AN20 AN0 AN4 REF BYPC AN22 AN26 AN31 AN32 VDD VSS AN8 AN17 VSSA1 AN21 AN3 AN7 VRL AN25 AN30 AN33 VDD VSS AN38 AN9 AN10 AN18 AN2 AN6 AN24 AN29 AN34 C VDD33 D ETPUA ETPUA 30 31 E ETPUA ETPUA VDDEH 28 29 1 F ETPUA ETPUA ETPUA VDDEH 24 27 26 1 G ETPUA ETPUA ETPUA ETPUA 23 22 25 21 H ETPUA ETPUA ETPUA ETPUA 20 19 18 17 J ETPUA ETPUA ETPUA ETPUA 16 15 14 13 K ETPUA ETPUA ETPUA ETPUA 12 11 10 9 VSS VSS VSS VSS L ETPUA ETPUA ETPUA ETPUA 8 7 6 5 VSS VSS VSS VSS M ETPUA ETPUA ETPUA ETPUA 4 3 2 1 VDDE2 VDDE2 VSS VSS ETPUA TCRCLK 0 A VDDE2 VDDE2 VSS VSS VDD N BDIP TEA P CS3 CS2 CS1 CS0 VDDE2 VDDE2 VSS VSS R WE3 WE2 WE1 WE0 VDDE2 VDDE2 VSS VSS VDDE2 T VDDE2 TSIZ0 RD_WR VDDE2 VSS VDDE2 VDDE2 U ADDR 16 TSIZ1 TA VDD33 V ADDR 18 ADDR 17 TS ADDR 8 W ADDR 20 ADDR 19 ADDR 9 ADDR 10 Y ADDR 22 ADDR 21 ADDR VDDE2 11 AA ADDR 24 ADDR 23 ADDR 13 ADDR 12 AB VDDE2 ADDR 25 ADDR 15 ADDR 14 AC ADDR 26 ADDR 27 ADDR 31 VSS VDD DATA 26 DATA 28 VDDE2 DATA 30 DATA 31 DATA 8 DATA 10 VDDE2 AD ADDR 28 ADDR 30 VSS VDD DATA 24 DATA 25 DATA 27 DATA 29 VDD33 GPIO 207 DATA 9 DATA 11 DATA 13 AE ADDR 29 VSS VDD DATA 17 DATA 19 DATA 21 DATA 23 DATA 0 DATA 2 DATA 4 DATA 6 OE BR AF VSS VDD DATA 16 DATA 18 VDDE2 DATA 20 DATA 22 GPIO 206 DATA 1 DATA 3 VDDE2 DATA 5 DATA 7 1 2 3 4 5 6 7 8 9 10 11 12 13 VSS VDDE2 VDDE2 VDDE2 Figure 29. MPC5554 416 Package Left Side MPC5554 Microcontroller Data Sheet, Rev. 2.0 46 Freescale Semiconductor Mechanicals 14 15 16 17 18 19 20 21 GPIO 205 22 23 24 25 26 VDD VDD33 VSS VSSA0 AN15 ETRIG ETPUB ETPUB ETPUB ETPUB 1 18 20 24 27 VSSA0 AN14 ETRIG ETPUB ETPUB ETPUB ETPUB MDO10 MDO7 0 21 25 28 31 MDO4 MDO0 VSS VDDA0 AN13 ETPUB ETPUB ETPUB ETPUB MDO9 19 22 26 30 MDO6 MDO1 VSS VDDE7 VDD C VDDEH AN12 9 ETPUB ETPUB ETPUB ETPUB MDO5 16 17 23 29 MDO2 VDDEH 8 VSS VDDE7 TCK TDI D VDDE7 TMS TDO TEST E MSEO0 JCOMP EVTI EVTO F MSEO1 MCKO GPIO 204 ETPUB G 15 MDO11 MDO8 MDO3 GPIO 203 RDY A VDDE7 B ETPUB ETPUB H 14 13 VDDEH ETPUB ETPUB ETPUB J 6 12 11 9 ETPUB ETPUB ETPUB ETPUB K 10 8 7 5 VDDE7 VDDE7 VDDE7 VDDE7 VSS VSS VSS VDDE7 ETPUB ETPUB ETPUB ETPUB L 6 4 3 2 VSS VSS VSS VDDE7 TCRCLK ETPUB ETPUB B 1 0 VSS VSS VSS VDDE7 SOUTB PCSB3 PCSB0 PCSB1 N VSS VSS VSS VSS PCSA3 PCSB4 SCKB PCSB2 P VSS VSS VSS VSS PCSB5 SOUTA VDDE2 VDDE2 VSS VSS PCSA1 PCSA0 PCSA2 VDDE2 VDDE2 VSS VSS PCSA4 TXDA PCSA5 VFLASH U SINA CNTXC RXDA RSTOUT SINB M SCKA R VPP RST CFG T V RXDB CNRXC TXDB RESET W Note: DATA 12 DATA 15 DATA 14 NC WKP CFG No connect. AC22 & AD23 reserved EMIOS EMIOS EMIOS EMIOS VDDEH VDDE5 2 8 12 21 4 NC EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA VDDE5 3 6 10 15 17 22 BOOT CFG1 VRC VSS VSS SYN Y VDDEH PLL 6 CFG1 BOOT CFG0 VDD VRC CTL PLL CFG0 XTAL AB VSS VDD VRC33 VDD SYN AC NC VSS VDD EXTAL AA VDD33 AD BG EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA VDDE5 CLKOUT VSS 1 5 9 13 16 19 23 VDD AE BB EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB CNRXB VDDE5 0 4 7 11 14 18 20 ENG CLK VSS AF 25 26 14 15 16 17 18 19 20 21 22 23 24 Figure 30. MPC5554 416 Package Right Side MPC5554 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 47 Mechanicals 4.2 MPC5554 416-Pin Package Dimensions The package drawings of the MPC5554 416 pin TEPBGA package are shown in Figure 31. Figure 31. MPC5554 416 TEPBGA Package MPC5554 Microcontroller Data Sheet, Rev. 2.0 48 Freescale Semiconductor Mechanicals Figure 32. MPC5554 416 TEPBGA Package (continued) MPC5554 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 49 Revision History for the MPC5554 Data Sheet 5 Revision History for the MPC5554 Data Sheet Table 28 shows the revision history of the MPC5554 Data Sheet: . Table 28. MPC5554 Data Sheet Revision History Revision Substantial Changes Rev. 1.3 Published Rev 1.3 of MPC5554 Data Sheet Rev. 1.4 Following changes made (referencing page, section, table, and figure numbers of Rev 1.3): * Cosmetic font fixes adjusted document length. * Figure 1 updated * Section 3.3 updated * Table 4: footnote #1 updated * Table 6, Spec 10 updated * Table 9, Spec 29 and 30 updated * Table 12, title updated; Spec 2, 8, and 15 updated; Spec 22 added; footnote numbers adjusted for new footnotes * Table 17, Spec 1 and 2 updated * Table 18, Spec 1 and 2 updated * Table 21, Spec 7 updated; footnote numbers adjusted for new footnotes Rev. 1.4 Published Rev 1.4 of MPC5554 Data Sheet Rev. 2.0 Table 1, Ordering Information: * Footnote added to Freescale Part Number column * Table 2, Footnotes 6, 8, and 9 changed from 1mA to 2mA * Table 21, removed Footnote from Spec 1's minimum value * Figure added: Figure 32 (second page of package drawing) Rev. 2.0 Technical changes: * Table 1 Added MPC5554AZP132 part number. * Table 1 Split the Temperature column into two columns for minimum and maximum temperatures. * Designated TL as the minimum temperature, and TH as the maximum temperature, with TA indicating the temperature range (TA = TL to TH). * Replaced -40 with TL for the minimum temperature in spec 26 of Table 2. * Added -55C to spec 7, Current which can be sourced by VRCCTL, and spec 10, Required Gain, in Table 6. * Added footnote to specs 7 and 10 of Table 6 restricting -55C support to qualified devices. * Replaced -40.0 with TL and 125.0 with TH in spec 45, Operating Temperature Range, in Table 9. MPC5554 Microcontroller Data Sheet, Rev. 2.0 50 Freescale Semiconductor Revision History for the MPC5554 Data Sheet Table 28 shows a continuation of the MPC5554 Revision History: Table 28. MPC5554 Revision History (continued) Revision Substantive Change(s) Date Rev. 2.0 Table 2 Absolute Maximum Ratings: * Increased the maximum operating frequency values by 2 ns in the Max column for the 80 MHz and 112 MHz. * Reordered rows to group devices by lead-free package types in descending frequency order, and leaded package types. Figure 3 Added figure to show interpolated IDDSTBY values listed in Table 9. Table 12 FMPLL Electrical Characteristics: Grouped (2 x Cl) in Specs 12 and 13. Table 7 Power Sequence Pin Status for Fast Pads, updated paragraph. Table 8 Power Sequence Pin Status, updated preceding paragraph. Table 9 DC Electrical Specifications: * Changed wording of footnote 3. * Spec 28: Corrected conditional text error showing wrong frequency. * Spec 29: Deleted frequency information. Section 3.7.1, "Input Value of Pins During POR Dependent on VDD33" Updated paragraph to remove redundancy, Table 16 Flash BIU Settlings: Changed wording of footnote from "Can be changed after Analysis and Characterization" to "These values may change after characterization." Table 17 and Table 18: * Deleted the words `not' from footnote 2. * Changed from `This parameter is supplied for reference and is not guaranteed by design and not tested' to `This parameter is supplied for reference and is guaranteed by design and tested.' Table 22 Bus Operation Timing: Specs 5 and 6: corrected format to show the bus timing values for various frequencies with EBTS bit = 0 and EBTS bit = 1. Table 26 DSPI Timing: Added to beginning of footnote 1 `All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type M or MH. DSPI signals using pad types of S or SH have an additional delay based on the slew rate.' Table 27 EQADC SSI Timing Characteristics: * Combined footnotes 1 and 2. * Moved footnotes 1 and 2 to Spec 2 and deleted Spec 1. 02/06/07 MPC5554 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 51 Revision History for the MPC5554 Data Sheet Table 28. MPC5554 Revision History (continued) Revision Substantive Change(s) Date Rev. 2.0 Table 7 Power Sequence Pin Status for the Fast Pad: Changed preceding paragraph From: Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive current spikes, etc., the state of the I/O pins during power up/down varies depending on power. Prior to exiting POR, the pads are in a high impedance state (Hi-Z). To: There are no power up/down sequencing requirements to prevent issues such as latch-up, excessive current spikes, and so on. Therefore, the state of the I/O pins during power up/down varies depending on which supplies are powered. Section 3.7.1, "Input Value of Pins During POR Dependent on VDD33," changed: From: To avoid accidentally selecting the bypass clock because PLLCFG[0:1] and RSTCFG are not treated as ones (1s) when POR negates, VDD33 must not lag VDDSYN and the RESET pin power (VDDEH6) when powering the device by more than the VDD33 lag specification in Table 6. VDD33 individually can lag either VDDSYN or the RESET power pin (VDDEH6) by more than the VDD33 lag specification. VDD33 can lag one of the VDDSYN or VDDEH6 supplies, but cannot lag both by more than the VDD33 lag specification. This VDD33 lag specification only applies during power up. VDD33 has no lead or lag requirements when powering down. To: When powering the device, VDD33 must not lag VDDSYN and the RESET power pin (VDDEH6) by more than the VDD33 lag specification listed in Table 6. This avoids accidentally selecting the bypass clock mode because the internal versions of PLLCFG[0:1] and RSTCFG are not powered and therefore cannot read the default state when POR negates. VDD33 can lag VDDSYN or the RESET power pin (VDDEH6), but cannot lag both by more than the VDD33 lag specification. This VDD33 lag specification only applies during power up. VDD33 has no lead or lag requirements when powering down. Section 3.7.3, "Power-Down Sequence (VRC33 Grounded)" Deleted the underscore in ORed_POR to become ORed POR. Table 22 Bus Operation Timing: Specs 7 and 8: Added the following signals to Specs 7 and 8 the EBI section: OE, RD_WR, TEA, BDIP, BG, BR, BB, and TSIZ[0:1]. 02/07/07 Rev. 2.0 Table 6 VCR/POR Electrical Specifications - Added to Spec 2: 3.3 V (VDDSYN) POR negated (ramp down) Min 0.0 Max 0.30 V Min 0.0 Max 0.30 V 3.3 V (VDDSYN) POR asserted (ramp up) 3/12/07 Rev. 2.0 Page 2 and throughout: Replaced kilobytes with KB and megabytes with MB. Table 1 Orderable Part Numbers: Changed the maximum operating speed from 132 MHz to 135 MHz. Table 6 VCR/POR Electrical Specifications: Changed the order of the entries in spec 2 from: 0.0 0.30 V 3.3 V (VDDSYN) POR negated (ramp down) 2.0 2.85 V 3.3 V (VDDSYN) POR negated (ramp up) 3.3 V (VDDSYN) POR asserted (ramp down) 2.0 2.85 V 0.0 0.30 V 3.3 V (VDDSYN) POR asserted (ramp up) to: 3.3 V (VDDSYN) POR asserted (ramp up) 0.0 0.30 V 2.0 2.85 V 3.3 V (VDDSYN) POR negated (ramp up) 3.3 V (VDDSYN) POR asserted (ramp down) 2.0 2.85 V 3.3 V (VDDSYN) POR negated (ramp down) 0.0 0.30 V Table 12 FMPLL Electrical Characteristics: Added footnote to Spec 1 on the minimum and maximum values for: Crystal reference, External reference, and Dual controller entries. The footnote reads: `The device operates correctly if the frequency remains within 5% of the specification limit. This tolerance range allows for a slight frequency drift of the crystals over time. The designer must thoroughly understand the drift margin of the source clock.' 3/19/07 MPC5554 Microcontroller Data Sheet, Rev. 2.0 52 Freescale Semiconductor Revision History for the MPC5554 Data Sheet Table 28. MPC5554 Revision History (continued) Revision Substantive Change(s) Date Rev. 2.0 Table 14 Flash Program and Erase Specifications: Inserted new values for the H7Fa Flash pre-program and erase times and used the previous values for Typical and Initial Max values. * Typical Values -- 16 KB: from 325 to 265 48 KB: from 435 to 340 64 KB: from 525 to 400 128 KB: from 675 to 500 * Initial Max Values -- 16 KB: from 525 to 400 48 KB: from 525 to 400 64 KB: from 675 to 500 128 KB: from 1800 to 1250 Table 16 FLASH BIU Settings vs. Frequency of Operations: Changed footnote 6 from: `Allows for 128 MHz system clock with 2% frequency modulation' to: `132 MHz parts allow for 128 MHz system clock + 2% FM.' 3/19/07 Rev. 2.0 Table 27 EQADC SSI Timing Characteristics: Footnote 2: added `cycle' after `duty' to read: FCK duty cycle is not 50% when . . . . 3/26/07 Rev. 2.0 Table 12 FMPLL Electrical Specifications: * Changed Spec 21, column 2: substituted fref_crystal for fref in ICO frequency equation, and added the same equation but substituted fref_ext for fref for the external reference clock, giving: fico = [ fref_crystal x (MFD + 4) ] / (PREDIV + 1) fico = [ fref_ext x (MFD + 4) ] / (PREDIV + 1) * Changed Spec 22: from `maximum frequency for the predivider' to `20 MHz'. 4/25/07 Rev. 2.0 Table 21, Nexus Debug Port Timing. Changed Spec 12, TCK Low to TDO Data Valid, `VDDE = 3.0 to 3.6 volts' maximum value in column 4 from 9 to 10. Now reads `VDDE = 3.0-3.6 V' with a max value of 10. 4/27/07 Rev. 2.0 Table 2 Absolute Maximum Ratings: Added the name of the Spec 21, VRC33 to VDDSYN differential voltage and the name of the Table, DC Electrical Specifications, to which the Spec was moved. Table 4 EMI Testing Specifications, Spec 2: Added in the Max column a footnote that reads: Refer to Table 1 for the maximum operating frequency. Table 5 ESD Characteristics: Added (Electromagnetic Static Discharge) in the table title. Figure 3 ISTBY Worst-case Specifications: Replaced the ISTBY graph. Table 9 DC Electrical Specifications: * Corrected footnote 3 to read: If standby operation is not required, connect the VSTBY to ground. * Changed Spec 26: Changed `AN[12]_MA[1]_SDO' to `AN[13]_MA[1]_SDO'. Table 12 FMPLL Electrical Specifications: * Added to the beginning of footnote 1 `Nominal crystal and external references values are at worst-case not more than 1%'. * Changed Spec 22, column 4, Max Value from fMAX to 20, and added footnote 20 to read, `Maximum value for Dual Controller (1:1) mode is (fMAX / 2) with the predivider set to 1 (FMPLL_SYNCR[PREDIV] = 0b001).' Table 14 Flash Program and Erase Specifications: Spec 8, 128KB block pre-program and erase time, Max column value from 15,000 to 7,500. Table 15 Flash EEPROM Module Life (Full Temperature Change): Spec 1b, Min. column value changed from 10,000 to 1,000. Table 21 Nexus Debug Port Timing, Spec 12: Changed value in Max column from 9 to 10 for the VDDE = 3.0-3.6 V row. 5/3/07 MPC5554 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 53 Revision History for the MPC5554 Data Sheet Table 28. MPC5554 Revision History (continued) Revision Substantive Change(s) Date Rev. 2.0 Figure 1 MPC5500 Family Part Numbers: * Added footnote 1 to read: All devices are PPC5554, rather than MPC5554, until the product qualifications are complete. Not all configurations are available in the PPC parts. * Added footnote 2 `The lowest operating temperature is referenced by TL; the high operating temperature is referenced by TH.' 9/12/07 Rev. 2.0 Table 1, Orderable Information: * Added the sentence directly preceding: `Unless otherwise noted in this data sheet, all specifications apply from TL to TH.' * Footnote 2: added `ambient' between `lowest' and `operating' and `highest' and `operating.' Table 2 Absolute Maximum Ratings: * Spec 14, column 2, changed: `VSS differential voltage' to `VSS to VSSA differential voltage.' * Spec 15, column 2, changed: `VDD differential voltage' to `VDD to VDDA differential voltage.' * Footnote 1, added: `any of' between `beyond' and `the listed maxima.' * Deleted footnote 2: `Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress have not yet been determined.' 9/14/07 Rev. 2.0 Table 4 EMI Testing Specification: * Spec 2: Operating frequency, column 5: Maximum, changed to fMAX. * Footnote 2: Deleted `Refer to Table 1 for the maximum operating frequency.' Table 6 VRC/POR Electrical Specifications: * Subscript all symbol names that appear after the first underscore character. * Specs 7 and 10: added `at Tj ` at the end of the first line in the second column: Characteristic. * Spec 7: Added -55 C and inserted 11.0 in the Min. column. * Spec 10: Added -55 C and inserted 70.0 in the Min. column. * Removed `Tj ` after `150C' in the last line, second column: Characteristic. * Spec 10, second column, second line: added x-ref to footnote 6: `IVRCCTL is measured at the following conditions: VDD = 1.35 V, VRC33 = 3.1 V, VVRCCTL = 2.2 V.' * Spec 10, second column, second line, changed for all products: `(@ VDD = 1.35 V, fsys = fMAX)` to `(@ fsys = fMAX)' * Footnote 10: Deleted `Preliminary value. Final specification pending characterization." Table 7 Power Sequence Pin Status for Fast Pads: Table title changed to: Pin Status for Fast Pads During the Power-on Sequence. Table 8 Power Sequence Pin Status for Medium / Slow Pads: Table title changed to: Pin Status for Medium / Slow Pads During the Power-on Sequence. 9/14/07 MPC5554 Microcontroller Data Sheet, Rev. 2.0 54 Freescale Semiconductor Revision History for the MPC5554 Data Sheet Table 28. MPC5554 Revision History (continued) Revision Substantive Change(s) Date Rev. 2.0 Section 3.7.1, "Input Value of Pins During POR Dependent on VDD33:" Added the following text directly before this section and after Table 8 Pin Status for Medium / Slow Pads During the Power-on Sequence: `The values in Table 7 and Table 8 do not include the effect of the weak pull devices on the output pins during power up. 9/17/07 Before exiting the internal POR state, the voltage on the pins goes to high-impedance until POR negates. When the internal POR negates, the functional state of the signal during reset applies and the weak pull devices (up or down) are enabled as defined in the device Reference Manual. If VDD is too low to correctly propagate the logic signals, the weak-pull devices can pull the signals to VDDE and VDDEH. To avoid this condition, minimize the ramp time of the VDD supply to a time period less than the time required to enable the external circuitry connected to the device outputs.' Table 9 DC Electrical Specifications: * Column 2, Characteristics: row 20,' Slow / medium I/O output high voltage (IOH_S = -2.0 mA):' Created a left-justified second line and moved `IOH_S = -2.0 mA' from the 1st line to the second line and deleted the parentheses. Created a left-justified third line that reads `IOH_S = -1.0 mA.' * Column 4, Min: row 20, Added a blank line before and after `0.80 x VDDEH' and put `0.85 x VDDEH' on the last line. * Column 2, Characteristics, row 22,' Slow / medium I/O output low voltage (IOL_S = 2.0 mA):' Created a left-justified second line and moved `IOL_S = 2.0 mA.' from the 1st line to the second line and deleted the parentheses. Created a left-justified third line that reads `IOL_S = 1.0 mA.' * Column 5, Max: row 22, Added a blank line before and after `0.20 x VDDEH' and put `0.15 x VDDEH' on the last line. MPC5554 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 55 Revision History for the MPC5554 Data Sheet Table 28. MPC5554 Revision History (continued) Revision Substantive Change(s) Date Rev. 2.0 Table 12 FMPLL Electrical Characteristics: * Added (TA = TL - TH) to the second line of the table title. * Old footnote 2: `Nominal crystal and external reference values are worst-case not more than 1%. The device operates correctly if the frequency remains within 5% of the specification limit. This tolerance range allows for a slight frequency drift of the crystals over time. The designer must thoroughly understand the drift margin of the source clock.` was moved to the end of 1st row in column 2: `PLL reference frequency range.' moving the footnote location changed it to footnote 1. Deleted old footnote 2 from all Min and Max columns. * Deleted old footnote 18 from row 21, from the MAX column that reads: The ICO frequency can be higher than the maximum allowable system frequency. For this case, set the CMPLL synthesizer control register reduced frequency divider (FMPLL_SYNCR[RFD]) to divide-by-two (RFD = 0b001). Therefore, for a 40 MHz maximum device (system frequency), program the FMPLL to generate 80 MHz at the ICO output and then divide-by-two the RFD to provide the 40 MHz system clock.' Table 13 eQADC Conversion Specifications: Added (TA = TL - TH) to the table title. Table 14 Flash Program and Erase Specifications: * Added (TA = TL - TH) to the table title. * Moved footnote 1 from the table title to directly after the `Typical' in the column 5 header. * Footnote 2: Changed from: `Initial factory condition: 100 program/erase cycles, 25 oC, typical supply voltage, 80 MHz minimum system frequency.` To: `Initial factory condition: 100 program/erase cycles, 25 oC, using a typical supply voltage measured at a minimum system frequency of 80 MHz.' Table 15 Flash EEPROM Module Life Specifications: Replaced (Full Temperature Range) with (TA = TL - TH) in the table title. Table 16 Flash BIU Settings vs. Frequency of Operation: * Added footnote 1 to the end of the table title, The footnote reads: `Illegal combinations exist. Use entries from the same row in this table.' * Moved footnote 2:' For maximum flash performance, set to 0b11' to the `DPFEN' column header. * Deleted the x-refs in the `DPFEN' column for the rows. * Created a x-ref for footnote 2 and inserted in the `IPFEN' column header. * Deleted the x-refs in the `IPFEN' column for the rows. * Moved footnote 3:' For maximum flash performance, set to 0b110' to the `PFLIM' column header. * Deleted the x-refs in the `PFLIM' column for the rows. * Moved footnote 4:' For maximum flash performance, set to 0b1' to the `BFEN' column header. * Deleted the x-refs in the `BFEN' column for the rows. Table 27 eQADC SSI Timing Characteristics: * Deleted first header row that reads `CLOAD = 25 pF on all outputs. Pad drive strength set to maximum.' * Deleted from footnote 1: `FSYS = 132 MHz, VDD = 1.35-1.65 V, VDD33 and VDDSYN = 3.0-3.6 V.' and changed `CL = 50 pF' to `CL = 25 pF.' 9/20/07 MPC5554 Microcontroller Data Sheet, Rev. 2.0 56 Freescale Semiconductor Revision History for the MPC5554 Data Sheet Table 28. MPC5554 Revision History (continued) Revision Substantive Change(s) Date Rev. 2.0 Table 17 Pad AC Specifications 5 V: * Footnote 1, deleted `fSYS = 132 MHz.' * Footnote 2, changed from `tested' to `not tested.' * Footnote 3, changed from `Out delay. . .' to `The output delay. . .', * Changed from ` Add a maximum of one system clock to the output delay to get the output delay with respect to the system clock` to `To calculate the output delay with respect to the system clock, add a maximum of one system clock to the output delay.' * Footnote 4: changed `Delay' to `The output delay.' * Footnote 5: deleted `before qualification.' Table 18 De-rated Pad AC Specifications 3.3 V: * Footnote 2, changed from ` and tested' to `(not tested).' * Footnote 3, changed from `Out delay. . .' to `The output delay. . .', * Changed from `Add a maximum of one system clock to the output delay to get the output delay with respect to the system clock` to `To calculate the output delay with respect to the system clock, add a maximum of one system clock to the output delay.' * Footnote 4: changed `Delay' to `The output delay.' * Footnote 5: deleted `before qualification.' Table 19 Reset and Configuration Pin Timing: Footnote 1, deleted `fSYS = 132 MHz' Table 20 JTAG Pin AC Electrical Characteristics: Footnote 1, deleted: `, and CL = 30 pF with DSC = 0b10, SRC = 0b11' and changed `functional' to `Nexus.' Table 21 Nexus Debug Port Timing: Footnote 5, changed from `to MCKO. The timing is . . .' to: ` to MCKO and is . . .' Table 23 External Interrupt Timing: Footnote 1, deleted `fSYS = 132 MHz.' Table 24 eTPU Timing: Footnote 1, deleted `fSYS = 132 MHz.' Table 25 eMIOS Timing: Footnote 1, deleted `fSYS = 132 MHz.' 9/20/07 Rev. 2.0 Table 14 Flash Program and Erase Specifications: Changed the `Typical ` `values for: 48 KB: from 340 to 345 64 KB: from 400 to 415 Table 22Bus Timing Operation: * Spec 1: changed 40 MHz value from 25 to 24.4; changed 56 MHz value from 17.9 to 17.5. * Specs 7 and 8: added BB, BR, BG, and TSIZ[0:1] 9/27/07 Published MPC5554 Microcontroller Reference Manual Rev. 2.0 MPC5554 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 57 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. 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Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Document Number: MPC5554 Rev. 2.0 10/2007 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. 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