74ALVC16244MTD_NL - Fairchild Semiconductor

October 2001

Revised May 2005

74ALVC16244 Low Voltage 16-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs

74ALVC16244

Low Voltage 16-Bit Buffer/Line Driver

with 3.6V Tolerant Inputs and Outputs

General Descript ion

The AL VC16244 contains sixteen non-inverting buffers with

3-STATE outputs to be employed as a memory and

address driver, clock driver, or bus oriented transmitter/

receiver. The device is nibble (4-bit) controlled. Each nibble

has separate 3- S TATE con tro l inpu ts which can be sh orted

together for full 16-bit operation.

The 74ALVC16244 is designed for low voltage (1.65V to

3.6V) VCC applications with I/O capability up to 3.6V.

The 74ALVC16 244 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Features

■1.65V–3.6V VCC supply operation

■3.6V tolerant inputs and outputs

■tPD

3.0 ns max for 3.0V to 3.6V VCC

3.5 ns max for 2.3V to 2.7V VCC

6.0 ns max for 1.65V to 1.95V VCC

■Power-off high impedance inputs and outputs

■Supports live insertion and withdrawal (Note 1)

■Uses patented noise /E MI reduct ion c ircuitr y

■Latch-up conforms to JEDEC JED98

■ESD performa nce :

Human body model

2000V

Machine model

200V

■Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA)

Note 1: To ensure the high-impedance state during power up or power

down, OE should be tied to VCC through a pull-up resistor; the minimum

value of th e resistor is determin ed by the curr ent-so urcing capab ility of the

driver.

Ordering Code:

Note 2: BGA package av ailable in Tape an d R eel only.

Note 3: Devices al so av ailable in Ta pe and Reel. Specify by appending t he suffix lette r “X” to th e ordering co de.

Logic Symbol

Order Number Package Number Package Description

74ALVC16244GX

(Note 2) BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[Tape and Reel]

74ALVC16244MTD

(Note 3) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

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74ALVC16244

Connection Diagrams

Pin Assignment for TSSOP

Pin Assignment for FBGA

(Top Thru Vi ew)

Pin Descriptions

FBGA Pin Assignments

Truth Tables

HIGH Voltage Level

LOW Voltage Level

Immaterial (HIGH or LOW, inputs may not float)

High Impedance

Pin Names Description

OEnOutput Enable Input (Active LOW)

I0–I15 Inputs

O0–O15 Outputs

NC No Connect

123456

AO0NC OE1OE2NC I0

BO2O1NC NC I1I2

CO4O3VCC VCC I3I4

DO6O5GND GND I5I6

EO8O7GND GND I7I8

FO10 O9GND GND I9I10

GO12 O11 VCC VCC I11 I12

HO14 O13 NC NC I13 I14

JO15 NC OE4OE3NC I15

Inputs Outputs

OE1I0–I3O0–O3

LL L

LH H

HX Z

Inputs Outputs

OE3I8-I11 O8–O11

LL L

LH H

HX Z

Inputs Outputs

OE2I4-I7O4-O7

LL L

LH H

HX Z

Inputs Outputs

OE4I12-I15 O12-O15

LL L

LH H

HX Z

3 www.fairchildsemi.com

74ALVC16244

Functional Description

The 74ALVC16244 contains sixteen non-inverting buffers

with 3-STATE outputs. The device is nibble (4 bits) con-

trolled wi th ea ch nibb l e fun ction i ng ide nti ca lly, but indepe n-

dent of each other. The control pins may be shorted

together to obtain full 16-bit operation.The 3-STATE out-

puts are controlled by an Output Enable (OEn) input. When

OEn is LOW, the outputs are in the 2-state mode. When

OEn is HIGH, the standard outp uts a re in the high imped-

ance mode but this does not interfere with entering new

data into the inputs.

Logic Diagram

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74ALVC16244

Absolute Maximum Ratings(Note 4) Recommended Operating

Conditions (Note 6)

Note 4: The Absolute Maximum Ratings are those values beyond which

the saf ety of the device cannot be guarante ed. The device should not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the Absolute Maximum Rat-

ings. The “Recommended Operating Conditions” tab le wil l define the condi-

tio ns f or actual de v i c e operation.

Note 5: IO Absolute Maximum Rating must be observed, limited to 4.6V.

Note 6: Floa ti ng or unus ed contro l inputs must be held H IG H or LOW.

DC Electrical Characteristi cs

Supply Voltage (VCC)



0.5V to



4.6V

DC Input Voltage (VI)



0.5V to 4.6V

Output Voltage (VO) (Note 5)



0.5V to VCC



0.5V

DC Input Diode Current (IIK)





50 mA

DC Output Diode Current (IOK)





50 mA

DC Output Source/Sink Current

(IOH/IOL)

50 mA

DC VCC or GND Current per

Supply Pin (ICC or GND)

100 mA

Storage Temperature Range (TSTG)



C to



150

Power Supply

Operating 1.65V to 3.6V

Input Voltage (VI) 0V to VCC

Output Voltage (VO) 0V to VCC

Free Air Operating Temperature (TA)



C to



Minimum Input Edge Rate (

VIN

0.8V to 2.0V, VCC

3.0V 10 ns/V

Symbol Parameter Conditions VCC Min Max Units

(V)

VIH HIGH Level Input Voltage 1.65 - 1.95 0.65 x VCC V2.3 - 2.7 1.7

2.7 - 3.6 2.0

VIL LOW Level Input Voltage 1.65 - 1.95 0.35 x VCC V2.3 - 2.7 0.7

2.7 - 3.6 0.8

VOH HIGH Level Output Voltage IOH



100

A 1.65 - 3.6 VCC - 0.2

IOH



4 mA 1.65 1.2

IOH



6 mA 2.3 2.0

IOH



12 mA 2.3 1.7

2.7 2.2

3.0 2.4

IOH



24 mA 3.0 2

VOL LOW Level Output Voltage IOL

100

A 1.65 - 3.6 0.2

IOL

4 mA 1.65 0.45

IOL

6 mA 2.3 0.4

IOL

12 mA 2.3 0.7

2.7 0.4

IOL

24 mA 3.0 0.55

IIInput Leakage Current 0

3.6V 3.6

5.0

IOZ 3-STATE Output Leakage 0

3.6V 3.6

ICC Quiescent Supply Current VI

VCC or GND, IO

0 3.6 40

ICC Increase in ICC per Input VIH

VCC



0.6V 3 - 3.6 750

5 www.fairchildsemi.com

74ALVC16244

AC Electrical Characteristics

Capacitance

Symbol Parameter



C to



C, RL

500

Units

50 pF CL

30 pF

VCC

3.3V

0.3V VCC

2.7V VCC

2.5V

0.2V VCC

1.8V

0.15V

Min Max Min Max Min Max Min Max

tPHL, tPLH Propagation Delay 1.3 3 1.5 3.5 1.0 3.0 1.5 6.0 ns

tPZL, tPZH Output Enable Time 1.3 4.0 1.5 4.6 1.0 4.1 1.5 8.2 ns

tPLZ, tPHZ Output Disable Time 1.3 4.0 1.5 4.3 1.0 3.8 1.5 6.8 ns

Symbol Parameter Conditions TA



CUnits

VCC Typical

CIN Input Capacit ance VI

0V or VCC 3.3 6 pF

COUT Output Capacitance VI

0V or VCC 3.3 7 pF

CPD Power Dissipation Capacitance Outputs Enabled f

10 MHz, CL

0 pF 3.3 20 pF

2.5 20

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74ALVC16244

AC Loading and Waveforms

FIGURE 1. AC Test Circuit

Table 1: Values for Figure 1

Table 2: Variable Matrix

(Input Characteristics: f = 1MHz; tr = tf = 2ns; Z0 = 50

)

FIGURE 2. Waveform for Inverting and Non-Inverting Functions

FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic

FIGURE 4. 3-STATE Output Low Enable and Di sable Times for Low Volt age Logic

TEST SWITCH

tPLH, tPHL Open

tPZL, tPLZ VL

tPZH, tPHZ GND

Symbol VCC

3.3V

0.3V 2.7V 2.5V

0.2V 1.8V

0.15V

Vmi 1.5V 1.5V VCC/2 VCC/2

Vmo 1.5V 1.5V VCC/2 VCC/2

VXVOL



0.3V VOL



0.3V VOL



0.15V VOL



0.15V

VYVOH



0.3V VOH



0.3V VOH



0.15V VOH



0.15V

VL6V 6V VCC*2 VCC*2

7 www.fairchildsemi.com

74ALVC16244

Physical Dimensions inches (millimeters) unless otherwise noted

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

Package Number BGA54A

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74ALVC16244 Low Voltage 16-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Output s

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Package Number MTD48

Fairchild does no t assume any responsibility for use of any circui try described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r systems a re devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent in any componen t of a life support

device or system whose failure to perform can be rea-

sonabl y ex pect ed to cause the fa ilu re of the li fe su pp ort

device or system, or to affect its safety or effectiveness.