Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) 100-Pin TQFP & 165-Bump BGA Commercial Temp Industrial Temp 18Mb Pipelined and Flow Through Synchronous NBT SRAM Features * User-configurable Pipeline and Flow Through mode * NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization * Fully pin-compatible with both pipelined and flow through NtRAMTM, NoBLTM and ZBTTM SRAMs * IEEE 1149.1 JTAG-compatible Boundary Scan * 2.5 V or 3.3 V +10%/-10% core power supply * LBO pin for Linear or Interleave Burst mode * Pin-compatible with 2M, 4M, and 8M devices * Byte write operation (9-bit Bytes) * 3 chip enable signals for easy depth expansion * ZZ pin for automatic power-down * JEDEC-standard 100-lead TQFP and 165-bump FP-BGA packages Functional Description The GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) is an 18Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. 300 MHz-150 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable, ZZ and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. The GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edge-triggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. The GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) is implemented with GSI's high performance CMOS technology and is available in JEDEC-standard 100-pin TQFP and 165-bump FP-BGA packages. Parameter Synopsis Pipeline 3-1-1-1 Flow Through 2-1-1-1 Rev: 1.03a 5/2003 -300 -250 -200 -150 Unit tKQ(x18/x36) tCycle 2.5 3.3 2.5 4.0 3.0 5.0 3.8 6.7 ns ns Curr (x18) Curr (x32/x36) tKQ tCycle 335 390 280 330 230 270 185 210 mA mA 5.0 5.0 5.5 5.5 6.5 6.5 7.5 7.5 ns ns Curr (x18) Curr (x32/x36) 230 270 210 240 185 205 170 190 mA mA 1/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) A A E1 E2 NC NC BB BA E3 VDD VSS CK W CKE G ADV A A A A GS8161Z18AT Pinout NC NC NC VDDQ A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA5 VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC LBO A A A A A1 A0 TMS TDI VSS VDD TDO TCK A A A A A A A VSS NC NC DQB DQB VSS VDDQ DQB DQB FT VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 1M x 18 10 71 11 Top View 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev: 1.03a 5/2003 2/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) A A E1 E2 BD BC BB BA E3 VDD VSS CK W CKE G ADV A A A A GS8161Z36AT Pinout DQPC DQC DQC VDDQ DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA DQPA LBO A A A A A1 A0 TMS TDI VSS VDD TDO TCK A A A A A A A VSS DQC DQC DQC DQC VSS VDDQ DQC DQC FT VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 36 10 71 11 Top View 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev: 1.03a 5/2003 3/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) 100-Pin TQFP Pin Descriptions Symbol Type Description A 0, A 1 In Burst Address Inputs; Preload the burst counter A In Address Inputs CK In Clock Input Signal BA In Byte Write signal for data inputs DQA1-DQA9; active low BB In Byte Write signal for data inputs DQB1-DQB9; active low BC In Byte Write signal for data inputs DQC1-DQC9; active low BD In Byte Write signal for data inputs DQD1-DQD9; active low W In Write Enable; active low E1 In Chip Enable; active low E2 In Chip Enable--Active High. For self decoded depth expansion E3 In Chip Enable--Active Low. For self decoded depth expansion G In Output Enable; active low ADV In Advance/Load; Burst address counter control pin CKE In Clock Input Buffer Enable; active low NC -- No Connect DQA I/O Byte A Data Input and Output pins DQB I/O Byte B Data Input and Output pins DQC I/O Byte C Data Input and Output pins DQD I/O Byte D Data Input and Output pins ZZ In Power down control; active high FT In Pipeline/Flow Through Mode Control; active low LBO In Linear Burst Order; active low. VDD In Core power supply VSS In Ground VDDQ In Output driver power supply Rev: 1.03a 5/2003 4/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) 165 Bump BGA--x18 Commom I/O--Top View (Package D) 1 2 3 4 5 6 7 8 9 10 11 A NC A E1 BB NC E3 CKE ADV A A A A B NC A E2 NC BA CK W G A A NC B C NC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPA C D NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA D E NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA E F NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA F G NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA G H FT MCH NC VDD VSS VSS VSS VDD NC NC ZZ H J DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC J K DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC K L DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC L M DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC M N DQPB NC VDDQ VSS NC NC NC VSS VDDQ NC NC N P NC NC A A TDI A1 TDO A A A NC P R LBO NC A A TMS A0 TCK A A A A R 11 x 15 Bump BGA--13 mm x 15 mm Body--1.0 mm Bump Pitch Rev: 1.03a 5/2003 5/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) 165 Bump BGA--x32 Common I/O--Top View (Package D) 1 2 3 4 5 6 7 8 9 10 11 A NC A E1 BC BB E3 CKE ADV A A NC A B NC A E2 BD BA CK W G A A NC B C NC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC NC C D DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB D E DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB E F DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB F G DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB G H FT MCH NC VDD VSS VSS VSS VDD NC NC ZZ H J DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA J K DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA K L DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA L M DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA M N NC NC VDDQ VSS NC NC NC VSS VDDQ NC NC N P NC NC A A TDI A1 TDO A A A NC P R LBO NC A A TMS A0 TCK A A A A R 11 x 15 Bump BGA--13 mm x 15 mm Body--1.0 mm Bump Pitch Rev: 1.03a 5/2003 6/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) 165 Bump BGA--x36 Common I/O--Top View (Package D) 1 2 3 4 5 6 7 8 9 10 11 A NC A E1 BC BB E3 CKE ADV A A NC A B NC A E2 BD BA CK W G A A NC B C DQPC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPB C D DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB D E DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB E F DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB F G DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB G H FT MCH NC VDD VSS VSS VSS VDD NC NC ZZ H J DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA J K DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA K L DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA L M DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA M N DQPD NC VDDQ VSS NC NC NC VSS VDDQ NC DQPA N P NC NC A A TDI A1 TDO A A A NC P R LBO NC A A TMS A0 TCK A A A A R 11 x 15 Bump BGA--13 mm x 15 mm Body--1.0 mm Bump Pitch Rev: 1.03a 5/2003 7/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) GS8161Z18/32/36AD 165-Bump BGA Pin Description Symbol Type Description A 0, A 1 I Address field LSBs and Address Counter Preset Inputs A I Address Inputs DQA DQB DQC DQD I/O Data Input and Output pins BA , BB , BC , BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low NC -- No Connect CK I Clock Input Signal; active high CKE I Clock Input Buffer Enable; active low W I Write Enable; active low E1 I Chip Enable; active low E3 I Chip Enable; active low E2 I Chip Enable; active high G I Output Enable; active low ADV I Burst address counter advance enable; active high ZZ I Sleep mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active low TMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock MCH -- Must Connect High VDD I Core power supply VSS I I/O and Core Ground VDDQ I Output driver power supply Rev: 1.03a 5/2003 8/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) Sense Amps Memory Array Register 2 Write Data K Register 1 K D Write Data Q K FT DQa-DQn GS8161Z18/32/36A NBT SRAM Functional Block Diagram FT Register 2 Register 1 Control Logic 9/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. G CKE CK E3 E2 E1 BD BC BB BA W LBO ADV A0-An K K Data Coherency Match Read, Write and K Write Address Write Address K K D Q SA1 SA0 Burst Counter SA1' SA0' 18 Write Drivers Rev: 1.03a 5/2003 (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) Functional Details Clocking Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation. Pipeline Mode Read and Write Operations All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2 and E3). Deassertion of any one of the Enable inputs will deactivate the device. Function W BA BB BC BD Read H X X X X Write Byte "a" L L H H H Write Byte "b" L H L H H Write Byte "c" L H H L H Write Byte "d" L H H H L Write all Bytes L L L L L Write Abort/NOP L H H H H Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins. Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The Byte Write Enable inputs (BA, BB, BC & BD) determine which bytes will be written. All or none may be activated. A write cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock. Flow Through Mode Read and Write Operations Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow Through mode the read pipeline is one cycle shorter than in Pipeline mode. Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock. Rev: 1.03a 5/2003 10/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) Synchronous Truth Table Operation Type Address E1 E2 E3 ZZ ADV W Bx G CKE CK DQ Notes Deselect Cycle, Power Down D None H X X L L X X X L L-H High-Z Deselect Cycle, Power Down D None X X H L L X X X L L-H High-Z Deselect Cycle, Power Down D None X L X L L X X X L L-H High-Z Deselect Cycle, Continue D None X X X L H X X X L L-H High-Z Read Cycle, Begin Burst R External L H L L L H X L L L-H Q Read Cycle, Continue Burst B Next X X X L H X X L L L-H Q 1,10 NOP/Read, Begin Burst R External L H L L L H X H L L-H High-Z 2 Dummy Read, Continue Burst B Next X X X L H X X H L L-H High-Z 1,2,10 Write Cycle, Begin Burst W External L H L L L L L X L L-H D 3 Write Cycle, Continue Burst B Next X X X L H X L X L L-H D 1,3,10 NOP/Write Abort, Begin Burst W None L H L L L L H X L L-H High-Z 2,3 Write Abort, Continue Burst B Next X X X L H X H X L L-H High-Z 1,2,3,10 Current X X X L X X X X H L-H - None X X X H X X X X X X High-Z Clock Edge Ignore, Stall Sleep Mode 1 4 Notes: 1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Deselect cycle is executed first. 2. Dummy Read and Write abort can be considered NOP's because the SRAM performs no operation. A Write abort occurs when the W pin is sampled low but no Byte Write pins are active so no Write operation is performed. 3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during Write cycles. 4. If CKE High occurs during a pipelined Read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a Write cycle, the bus will remain in High Z. 5. X = Don't Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals are low 6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge. 7. Wait states can be inserted by setting CKE high. 8. This device contains circuitry that ensures all outputs are in High Z during power-up. 9. A 2-bit burst counter is incorporated. 10. The address counter is incriminated for all Burst continue cycles. Rev: 1.03a 5/2003 11/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) Pipelined and Flow Through Read Write Control State Diagram D B Deselect W R D R D W New Read New Write R W B B R B W R Burst Read W Burst Write D Key B D Notes: Input Command Code 1. The Hold command (CKE Low) is not shown because it prevents any state change. Transition Current State (n) 2. W, R, B, and D represent input command codes as indicated in the Synchronous Truth Table. Next State (n+1) n n+1 n+2 n+3 Clock (CK) Command Current State Next State Current State and Next State Definition for Pipelined and Flow Through Read/Write Control State Diagram Rev: 1.03a 5/2003 12/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) Pipeline Mode Data I/O State Diagram Intermediate B W R B Intermediate R High Z (Data In) D Data Out (Q Valid) W D Intermediate Intermediate W Intermediate R High Z B D Intermediate Key Notes: Input Command Code 1. The Hold command (CKE Low) is not shown because it prevents any state change. Transition Current State (n) Transition Intermediate State (N+1) n Next State (n+2) n+1 2. W, R, B, and D represent input command codes as indicated in the Truth Tables. n+2 n+3 Clock (CK) Command Current State Intermediate State Next State Current State and Next State Definition for Pipeline Mode Data I/O State Diagram Rev: 1.03a 5/2003 13/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) Flow Through Mode Data I/O State Diagram B W R B R High Z (Data In) Data Out (Q Valid) W D D W R High Z B D Key Notes: Input Command Code 1. The Hold command (CKE Low) is not shown because it prevents any state change. Transition Current State (n) 2. W, R, B, and D represent input command codes as indicated in the Truth Tables. Next State (n+1) n n+1 n+2 n+3 Clock (CK) Command Current State Next State Current State and Next State Definition for: Pipeline and Flow through Read Write Control State Diagram Rev: 1.03a 5/2003 14/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) Burst Cycles Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode. Burst Order The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables below for details. Mode Pin Functions Mode Name Pin Name Burst Order Control LBO Output Register Control FT Power Down Control ZZ State Function L Linear Burst H Interleaved Burst L Flow Through H or NC Pipeline L or NC Active H Standby, IDD = ISB Note: There are pull-up devices on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. Burst Counter Sequences Interleaved Burst Sequence Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 1st address 00 01 10 11 2nd address 01 10 11 00 2nd address 01 00 11 10 3rd address 10 11 00 01 3rd address 10 11 00 01 4th address 11 00 01 10 4th address 11 10 01 00 Note: The burst counter wraps to initial state on the 5th clock. Note: The burst counter wraps to initial state on the 5th clock. BPR 1999.05.18 Rev: 1.03a 5/2003 15/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by it's internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode. ~ ~ ~ ~ CK ~ ~ ~ ~ ~ ~ Sleep Mode Timing Diagram ZZ tZZS Sleep tZZR tZZH Designing for Compatibility The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipelinemode via the FT signal found on Pin 14. Not all vendors offer this option, however most mark Pin 14 as VDD or VDDQ on pipelined parts and VSS on flow through parts. GSI NBT SRAMs are fully compatible with these sockets. Rev: 1.03a 5/2003 16/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) Absolute Maximum Ratings (All voltages reference to VSS) Symbol Description Value Unit VDD Voltage on VDD Pins -0.5 to 4.6 V VDDQ Voltage in VDDQ Pins -0.5 to 4.6 V VI/O Voltage on I/O Pins -0.5 to VDDQ +0.5 ( 4.6 V max.) V VIN Voltage on Other Input Pins -0.5 to VDD +0.5 ( 4.6 V max.) V IIN Input Current on Any Pin +/-20 mA IOUT Output Current on Any I/O Pin +/-20 mA PD Package Power Dissipation 1.5 W TSTG Storage Temperature -55 to 125 o -55 to 125 o TBIAS Temperature Under Bias C C Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Rev: 1.03a 5/2003 17/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) Power Supply Voltage Ranges Parameter Symbol Min. Typ. Max. Unit 3.3 V Supply Voltage VDD3 3.0 3.3 3.6 V 2.5 V Supply Voltage VDD2 2.3 2.5 2.7 V 3.3 V VDDQ I/O Supply Voltage VDDQ3 3.0 3.3 3.6 V 2.5 V VDDQ I/O Supply Voltage VDDQ2 2.3 2.5 2.7 V Notes Notes: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. VDDQ3 Range Logic Levels Parameter Symbol Min. Typ. Max. Unit Notes VDD Input High Voltage VIH 2.0 -- VDD + 0.3 V 1 VDD Input Low Voltage VIL -0.3 -- 0.8 V 1 VDDQ I/O Input High Voltage VIHQ 2.0 -- VDDQ + 0.3 V 1,3 VDDQ I/O Input Low Voltage VILQ -0.3 -- 0.8 V 1,3 Notes: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. 3. Input Under/overshoot voltage must be -2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. VDDQ2 Range Logic Levels Parameter Symbol Min. Typ. Max. Unit Notes VDD Input High Voltage VIH 0.6*VDD -- VDD + 0.3 V 1 VDD Input Low Voltage VIL -0.3 -- 0.3*VDD V 1 VDDQ I/O Input High Voltage VIHQ 0.6*VDD -- VDDQ + 0.3 V 1,3 VDDQ I/O Input Low Voltage VILQ -0.3 -- 0.3*VDD V 1,3 Notes: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. 3. Input Under/overshoot voltage must be -2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. Rev: 1.03a 5/2003 18/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) Recommended Operating Temperatures Parameter Symbol Min. Typ. Max. Unit Notes Ambient Temperature (Commercial Range Versions) TA 0 25 70 C 2 Ambient Temperature (Industrial Range Versions) TA -40 25 85 C 2 Notes: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Undershoot Measurement and Timing Overshoot Measurement and Timing VIH 20% tKC VDD + 2.0 V VSS 50% 50% VDD VSS - 2.0 V 20% tKC VIL Capacitance (TA = 25oC, f = 1 MHZ, VDD = 2.5 V) Parameter Symbol Test conditions Typ. Max. Unit Input Capacitance CIN VIN = 0 V 4 5 pF Input/Output Capacitance CI/O VOUT = 0 V 6 7 pF Note: These parameters are sample tested. Package Thermal Characteristics Rating Layer Board Symbol Max Unit Notes Junction to Ambient (at 200 lfm) single RJA 40 C/W 1,2 Junction to Ambient (at 200 lfm) four RJA 24 C/W 1,2 Junction to Case (TOP) -- RJC 9 C/W 3 Notes: 1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance. 2. SCMI G-38-87 3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1 Rev: 1.03a 5/2003 19/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) AC Test Conditions Parameter Conditions Input high level VDD - 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level VDD/2 Output reference level VDDQ/2 Output load Fig. 1 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. Output Load 1 DQ 30pF* 50 VDDQ/2 * Distributed Test Jig Capacitance DC Electrical Characteristics Parameter Symbol Test Conditions Min Max Input Leakage Current (except mode pins) IIL VIN = 0 to VDD -1 uA 1 uA ZZ Input Current IIN1 VDD VIN VIH 0 V VIN VIH -1 uA -1 uA 1 uA 100 uA FT Input Current IIN2 VDD VIN VIL 0 V VIN VIL -100 uA -1 uA 1 uA 1 uA Output Leakage Current IOL Output Disable, VOUT = 0 to VDD -1 uA 1 uA Output High Voltage VOH2 IOH = -8 mA, VDDQ = 2.375 V 1.7 V -- Output High Voltage VOH3 IOH = -8 mA, VDDQ = 3.135 V 2.4 V -- Output Low Voltage VOL IOL = 8 mA -- 0.4 V Rev: 1.03a 5/2003 20/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Rev: 1.03a 5/2003 -- -- ZZ VDD - 0.2 V Device Deselected; All other inputs VIH or VIL Operating Current Standby Current Deselect Current 310 25 215 15 40 40 IDD IDDQ IDD IDDQ ISB ISB Pipeline Flow Through Pipeline Flow Through Flow Through Pipeline IDD 60 85 240 30 IDD IDDQ Flow Through IDD 345 45 IDD IDDQ Pipeline 0 to 70C 65 90 50 50 225 15 320 25 250 30 355 45 -40 to 85C -300 Symbol Mode Notes: 1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation. 2. All parameters listed are worst case scenario. (x18) Device Selected; All other inputs VIH or VIL Output open (x32/ x36) Test Conditions Parameter Operating Currents 60 85 40 40 200 10 260 20 220 20 290 40 0 to 70C 65 90 50 50 210 10 270 20 230 20 300 40 -40 to 85C -250 50 75 40 40 175 10 215 15 190 15 240 30 0 to 70C 55 80 50 50 185 10 225 15 200 15 250 30 -40 to 85C -200 50 60 40 40 160 10 170 15 175 15 190 20 0 to 70C 55 65 50 50 170 10 180 15 185 15 200 20 -40 to 85C -150 mA mA mA mA mA mA mA mA Unit Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 21/36 (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) AC Electrical Characteristics Pipeline Flow Through Parameter Symbol Clock Cycle Time tKC -300 -250 -200 -150 Unit Min Max Min Max Min Max Min Max 3.3 -- 4.0 -- 5.0 -- 6.7 -- ns Clock to Output Valid tKQ -- 2.5 -- 2.5 -- 3.0 -- 3.8 ns Clock to Output Invalid tKQX 1.5 -- 1.5 -- 1.5 -- 1.5 -- ns Clock to Output in Low-Z tLZ1 1.5 -- 1.5 -- 1.5 -- 1.5 -- ns Setup time tS 1.0 -- 1.2 -- 1.4 -- 1.5 -- ns Hold time tH 0.1 -- 0.2 -- 0.4 -- 0.5 -- ns Clock Cycle Time tKC 5.0 -- 5.5 -- 6.5 -- 7.5 -- ns Clock to Output Valid tKQ -- 5.0 -- 5.5 -- 6.5 -- 7.5 ns Clock to Output Invalid tKQX 3.0 -- 3.0 -- 3.0 -- 3.0 -- ns Clock to Output in Low-Z tLZ1 3.0 -- 3.0 -- 3.0 -- 3.0 -- ns Setup time tS 1.4 -- 1.5 -- 1.5 -- 1.5 -- ns Hold time tH 0.4 -- 0.5 -- 0.5 -- 0.5 -- ns Clock HIGH Time tKH 1.3 -- 1.3 -- 1.3 -- 1.5 -- ns Clock LOW Time tKL 1.5 -- 1.5 -- 1.5 -- 1.7 -- ns Clock to Output in High-Z tHZ1 1.5 2.5 1.5 2.5 1.5 3.0 1.5 3.0 ns G to Output Valid tOE -- 2.5 -- 2.5 -- 3.0 -- 3.8 ns 1 G to output in Low-Z tOLZ 0 -- 0 -- 0 -- 0 -- ns G to output in High-Z tOHZ1 -- 2.5 -- 2.5 -- 3.0 -- 3.8 ns ZZ setup time tZZS2 5 -- 5 -- 5 -- 5 -- ns ZZ hold time tZZH2 1 -- 1 -- 1 -- 1 -- ns ZZ recovery tZZR 20 -- 20 -- 20 -- 20 -- ns Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.03a 5/2003 22/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Q(B) tS tKQ tH C D(A) D tKC tKL tKH Read C Rev: 1.03a 5/2003 DQ A0-An tS Bn W A tH tH ADV tS tH E tS tH tS CKE CK tS tH Write A Pipeline Mode Timing (NBT) B Read B Suspend D(D) tS tKQX tKQ Write D Q(C) Suspend1 tS tH Write E Read E tKQ tLZ Deselect Q(E) tHZ tKQX Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) 23/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Q(C) tHZ tKQX D tH tS Rev: 1.03a 5/2003 tS D(A) DQ A0-An tS Bn W ADV A tH tH tS E CKE tS tH CK tS tH B tH tKH Write A Flow Through Mode Timing (NBT) Read B tKL Q(B) tKC Suspend C tKQ Read C tS tH Write D1 Suspend1 D(D) Write E tLZ Read E Q(E) Deselect tHZ tKQX Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) 24/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) JTAG Port Operation Overview The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDDQ. Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected. JTAG Pin Descriptions Pin Pin Name I/O Description TCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS Test Mode Select In The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. In The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level. TDI Test Data In TDO Test Data Out Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up. JTAG Port Registers Overview The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Rev: 1.03a 5/2003 25/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM's JTAG Port to another device in the scan chain with as little delay as possible. Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM's input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port's TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. JTAG TAP Block Diagram 0 Bypass Register 2 1 0 Instruction Register TDI TDO ID Code Register 31 30 29 * * * * 2 1 0 Boundary Scan Register n * * * * * * * * * 2 1 0 TMS Test Access Port (TAP) Controller TCK Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. Die Revision Code GSI Technology JEDEC Vendor ID Code I/O Configuration Not Used Presence Register ID Register Contents Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x36 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1 x18 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 Rev: 1.03a 5/2003 26/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) Tap Controller Instruction Set Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. JTAG Tap Controller State Diagram 1 0 Test Logic Reset 0 Run Test Idle 1 Select DR 1 Select IR 0 0 1 1 Capture DR Capture IR 0 0 Shift DR 1 1 Shift IR 0 1 1 Exit1 DR 0 Exit1 IR 0 0 Pause DR 1 Exit2 DR 1 Update DR 1 1 0 0 Pause IR 1 Exit2 IR 0 1 0 0 Update IR 1 0 Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Rev: 1.03a 5/2003 27/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to ShiftDR state then places the boundary scan register between the TDI and TDO pins. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM's input pins; therefore, the RAM's internal state is still determined by its input pins. Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register's contents, in parallel, on the RAM's data output drivers on the falling edge of TCK when the controller is in the Update-IR state. Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM's input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM's output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Rev: 1.03a 5/2003 28/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) JTAG TAP Instruction Set Summary Instruction Code Description Notes EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1 IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2 SAMPLE-Z 010 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. 1 RFU 011 Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1 SAMPLE/ PRELOAD 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. 1 GSI 101 GSI private instruction. 1 RFU 110 Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1 BYPASS 111 Places Bypass Register between TDI and TDO. 1 Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.03a 5/2003 29/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) JTAG Port Recommended Operating Conditions and DC Characteristics Parameter Symbol Min. Max. Unit Notes 3.3 V Test Port Input High Voltage VIHJ3 2.0 VDD3 +0.3 V 1 3.3 V Test Port Input Low Voltage VILJ3 -0.3 0.8 V 1 2.5 V Test Port Input High Voltage VIHJ2 0.6 * VDD2 VDD2 +0.3 V 1 2.5 V Test Port Input Low Voltage VILJ2 -0.3 0.3 * VDD2 V 1 TMS, TCK and TDI Input Leakage Current IINHJ -300 1 uA 2 TMS, TCK and TDI Input Leakage Current IINLJ -1 100 uA 3 TDO Output Leakage Current IOLJ -1 1 uA 4 Test Port Output High Voltage VOHJ 1.7 -- V 5, 6 Test Port Output Low Voltage VOLJ -- 0.4 V 5, 7 Test Port Output CMOS High VOHJC VDDQ - 100 mV -- V 5, 8 Test Port Output CMOS Low VOLJC -- 100 mV V 5, 9 Notes: 1. Input Under/overshoot voltage must be -2 V > Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC. 2. VILJ VIN VDDn 3. 0 V VIN VILJn 4. Output Disable, VOUT = 0 to VDDn 5. The TDO output driver is served by the VDDQ supply. 6. IOHJ = -4 mA 7. IOLJ = + 4 mA 8. IOHJC = -100 uA 9. IOHJC = +100 uA JTAG Port AC Test Conditions Parameter Conditions Input high level VDD - 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level VDDQ/2 Output reference level VDDQ/2 JTAG Port AC Test Load DQ 50 30pF* VDDQ/2 * Distributed Test Jig Capacitance Notes: 1. Include scope and jig capacitance. 2. Test conditions as as shown unless otherwise noted. Rev: 1.03a 5/2003 30/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) JTAG Port Timing Diagram tTKL tTKH tTKC TCK tTS tTH TMS TDI TDO tTKQ JTAG Port AC Electrical Characteristics Parameter Symbol Min Max Unit TCK Cycle Time tTKC 50 -- ns TCK Low to TDO Valid tTKQ -- 20 ns TCK High Pulse Width tTKH 20 -- ns TCK Low Pulse Width tTKL 20 -- ns TDI & TMS Set Up Time tTS 10 -- ns TDI & TMS Hold Time tTH 10 -- ns Boundary Scan (BSDL Files) For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications Engineering Department at: apps@gsitechnology.com. Rev: 1.03a 5/2003 31/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) TQFP Package Drawing TQFP Package Drawing L Description Min. Nom. Max A1 Standoff 0.05 0.10 0.15 A2 Body Thickness 1.35 1.40 1.45 b Lead Width 0.20 0.30 0.40 c Lead Thickness 0.09 D Terminal Dimension 21.9 22.0 20.1 D1 Package Body 19.9 20.0 20.1 E Terminal Dimension 15.9 16.0 16.1 E1 Package Body 13.9 14.0 14.1 e Lead Pitch L Foot Length L1 Lead Length Y Coplanarity Lead Angle L1 c Pin 1 Symbol 0.20 D D1 e b 0.65 0.45 0.60 0.75 1.00 A1 A2 0.10 Y 0 7 E1 E Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. BPR 1999.05.18 Rev: 1.03a 5/2003 32/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) Package Dimensions--165-Bump FPBGA (Package D) A1 CORNER TOP VIEW BOTTOM VIEW O0.10 M C O0.25 M C A B O0.40~0.50 (165x) 1 2 3 4 5 6 7 8 9 10 11 A1 CORNER 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R 1.0 14.0 150.07 1.0 A B C D E F G H I J K L M N P R A 1.0 1.0 0.15 C B C Rev: 1.03a 5/2003 SEATING PLANE 130.07 0.20(4x) 0.25~0.40 1.20 MAX. (0.26) 0.450.05 0.25 C 10.0 33/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) Ordering Information--GSI NBT Synchronous SRAM Org Part Number1 Type Package Speed2 (MHz/ns) TA3 1M x 18 GS8161Z18AT-300 Pipeline/Flow Through TQFP 300/5 C 1M x 18 GS8161Z18AT-250 Pipeline/Flow Through TQFP 250/5.5 C 1M x 18 GS8161Z18AT-200 Pipeline/Flow Through TQFP 200/6.5 C 1M x 18 GS8161Z18AT-150 Pipeline/Flow Through TQFP 150/7.5 C 1M x 18 GS8161Z18AD-300 Pipeline/Flow Through 165 BGA 300/5 C 1M x 18 GS8161Z18AD-250 Pipeline/Flow Through 165 BGA 250/5.5 C 1M x 18 GS8161Z18AD-200 Pipeline/Flow Through 165 BGA 200/6.5 C 1M x 18 GS8161Z18AD-150 Pipeline/Flow Through 165 BGA 150/7.5 C 512K x 32 GS8161Z32AD-300 Pipeline/Flow Through 165 BGA 300/5 C 512K x 32 GS8161Z32AD-250 Pipeline/Flow Through 165 BGA 250/5.5 C 512K x 32 GS8161Z32AD-200 Pipeline/Flow Through 165 BGA 200/6.5 C 512K x 32 GS8161Z32AD-150 Pipeline/Flow Through 165 BGA 150/7.5 C 512K x 36 GS8161Z36AT-300 Pipeline/Flow Through TQFP 300/5 C 512K x 36 GS8161Z36AT-250 Pipeline/Flow Through TQFP 250/5.5 C 512K x 36 GS8161Z36AT-200 Pipeline/Flow Through TQFP 200/6.5 C 512K x 36 GS8161Z36AT-150 Pipeline/Flow Through TQFP 150/7.5 C 512K x 36 GS8161Z36AD-300 Pipeline/Flow Through 165 BGA 300/5 C 512K x 36 GS8161Z36AD-250 Pipeline/Flow Through 165 BGA 250/5.5 C 512K x 36 GS8161Z36AD-200 Pipeline/Flow Through 165 BGA 200/6.5 C 512K x 36 GS8161Z36AD-150 Pipeline/Flow Through 165 BGA 150/7.5 C 1M x 18 GS8161Z18AT-300I Pipeline/Flow Through TQFP 300/5 I 1M x 18 GS8161Z18AT-250I Pipeline/Flow Through TQFP 250/5.5 I 1M x 18 GS8161Z18AT-200I Pipeline/Flow Through TQFP 200/6.5 I 1M x 18 GS8161Z18AT-150I Pipeline/Flow Through TQFP 150/7.5 I 1M x 18 GS8161Z18AD-300I Pipeline/Flow Through 165 BGA 300/5 I 1M x 18 GS8161Z18AD-250I Pipeline/Flow Through 165 BGA 250/5.5 I 1M x 18 GS8161Z18AD-200I Pipeline/Flow Through 165 BGA 200/6.5 I 1M x 18 GS8161Z18AD-150I Pipeline/Flow Through 165 BGA 150/7.5 I 512K x 32 GS8161Z32AD-300I Pipeline/Flow Through 165 BGA 300/5 I 512K x 32 GS8161Z32AD-250I Pipeline/Flow Through 165 BGA 250/5.5 I Status Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS8161Z18AT-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.03a 5/2003 34/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) Org Part Number1 Type Package Speed2 (MHz/ns) TA3 512K x 32 GS8161Z32AD-200I Pipeline/Flow Through 165 BGA 200/6.5 I 512K x 32 GS8161Z32AD-150I Pipeline/Flow Through 165 BGA 150/7.5 I 512K x 36 GS8161Z36AT-300I Pipeline/Flow Through TQFP 300/5 I 512K x 36 GS8161Z36AT-250I Pipeline/Flow Through TQFP 250/5.5 I 512K x 36 GS8161Z36AT-200I Pipeline/Flow Through TQFP 200/6.5 I 512K x 36 GS8161Z36AT-150I Pipeline/Flow Through TQFP 150/7.5 I 512K x 36 GS8161Z36AD-300I Pipeline/Flow Through 165 BGA 300/5 I 512K x 36 GS8161Z36AD-250I Pipeline/Flow Through 165 BGA 250/5.5 I 512K x 36 GS8161Z36AD-200I Pipeline/Flow Through 165 BGA 200/6.5 I 512K x 36 GS8161Z36AD-150I Pipeline/Flow Through 165 BGA 150/7.5 I Status Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS8161Z18AT-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.03a 5/2003 35/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc. Preliminary GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D) 18Mb Sync SRAM Data Sheet Revision History DS/DateRev. Code: Old; New Types of Changes Format or Content Page;Revisions;Reason * Creation of new datasheet 8161Z18A_r1 Content * Updated FT power numbers * Updated AC Characteristics table * Updated ZZ recovery time diagram * Updated AC Test Conditions table and removed Output Load 2 diagram 8161Z18A_r1_01; 8161Z18A_r1_02 Content * Removed extraneous VDDQ1 table on page 12 and changed VDDQ2 table to VDDQ * Removed pin locations from pin description table * Removed BSR table GS8161ZxxA_r1_02; GS8161ZxxA_r1_03 Content 8161Z18A_r1; 8161Z18A_r1_01 Rev: 1.03a 5/2003 * Entire datasheet rewritten due to design changes 36/36 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2001, Giga Semiconductor, Inc.