Rev: 1.03a 5/2003 1/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
300 MHz–150 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
100-Pin TQFP & 165-Bump BGA
Commercial Temp
Industrial Temp
Preliminary
Features
• User-configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
• Fully pin-compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 2.5 V or 3.3 V +10%/–10% core power supply
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ pin for automatic power-down
• JEDEC-standard 100-lead TQFP and 165-bump FP-BGA
packages
Functional Description
The GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
is an 18Mbit Synchronous Static SRAM. GSI's NBT SRAMs,
like ZBT, NtRAM, NoBL or other pipelined read/double late
write or flow through read/single late write SRAMs, allow
utilization of all available bus bandwidth by eliminating the
need to insert deselect cycles when the device is switched from
read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
may be configured by the user to operate in Pipeline or Flow
Through mode. Operating as a pipelined synchronous device,
in addition to the rising-edge-triggered registers that capture
input signals, the device incorporates a rising-edge-triggered
output register. For read cycles, pipelined SRAM output data is
temporarily stored by the edge triggered output register during
the access cycle and then released to the output drivers at the
next rising edge of clock.
The GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
is implemented with GSI's high performance CMOS
technology and is available in JEDEC-standard 100-pin TQFP
and 165-bump FP-BGA packages.
Parameter Synopsis
-300 -250 -200 -150 Unit
Pipeline
3-1-1-1
tKQ(x18/x36)
tCycle
2.5
3.3
2.5
4.0
3.0
5.0
3.8
6.7
ns
ns
Curr (x18)
Curr (x32/x36)
335
390
280
330
230
270
185
210
mA
mA
Flow Through
2-1-1-1
tKQ
tCycle
5.0
5.0
5.5
5.5
6.5
6.5
7.5
7.5
ns
ns
Curr (x18)
Curr (x32/x36)
230
270
210
240
185
205
170
190
mA
mA
Rev: 1.03a 5/2003 2/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
GS8161Z18AT Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
VSS
DQB
DQB
VSS
VDDQ
DQB
DQB
FT
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
VSS
VDDQ
VDDQ
VSS
DQA
DQA
VSS
VDDQ
DQA
DQA5
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
VSS
VDDQ
LBO
A
A
A
A
A1
A0
TMS
TDI
VSS
VDD
TDO
TCK
A
A
A
A
A
A
A
A
E1
E2
NC
NC
BB
BA
E3
CK
W
CKE
VDD
VSS
G
ADV
A
A
A
A
A
1M x 18
Top View
DQPA
A
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC 10099989796959493929190898887868584838281
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.03a 5/2003 3/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
GS8161Z36AT Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
VSS
DQC
DQC
VSS
VDDQ
DQC
DQC
FT
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
VSS
VDDQ
VDDQ
VSS
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
VSS
VDDQ
LBO
A
A
A
A
A1
A0
TMS
TDI
VSS
VDD
TDO
TCK
A
A
A
A
A
A
A
A
E1
E2
BD
BC
BB
BA
E3
CK
W
CKE
VDD
VSS
G
ADV
A
A
A
A
A
512K x 36
Top View
DQB
DQPB
DQB
DQB
DQB
DQA
DQA
DQA
DQA
DQPA
DQC
DQC
DQC
DQD
DQD
DQD
DQPD
DQC
DQPC
10099989796959493929190898887868584838281
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.03a 5/2003 4/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
100-Pin TQFP Pin Descriptions
Symbol Type Description
A0, A1In Burst Address Inputs; Preload the burst counter
A In Address Inputs
CK In Clock Input Signal
BAIn Byte Write signal for data inputs DQA1–DQA9; active low
BBIn Byte Write signal for data inputs DQB1–DQB9; active low
BCIn Byte Write signal for data inputs DQC1–DQC9; active low
BDIn Byte Write signal for data inputs DQD1–DQD9; active low
WIn Write Enable; active low
E1In Chip Enable; active low
E2In Chip Enable—Active High. For self decoded depth expansion
E3In Chip Enable—Active Low. For self decoded depth expansion
GIn Output Enable; active low
ADV In Advance/Load; Burst address counter control pin
CKE In Clock Input Buffer Enable; active low
NC — No Connect
DQAI/O Byte A Data Input and Output pins
DQBI/O Byte B Data Input and Output pins
DQCI/O Byte C Data Input and Output pins
DQDI/O Byte D Data Input and Output pins
ZZ In Power down control; active high
FT In Pipeline/Flow Through Mode Control; active low
LBO In Linear Burst Order; active low.
VDD In Core power supply
VSS In Ground
VDDQ In Output driver power supply
Rev: 1.03a 5/2003 5/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
165 Bump BGA—x18 Commom I/O—Top View (Package D)
1234567891011
ANC
AE1BB NC E3 CKE ADV AAAA
BNC
AE2NCBACK W G A ANC B
CNCNC
VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPA C
DNC
DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA D
ENC
DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA E
FNC
DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA F
GNC
DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA G
HFT
MCH NC VDD VSS VSS VSS VDD NC NC ZZ H
JDQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC J
KDQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC K
LDQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC L
MDQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC M
NDQPB NC VDDQ VSS NC NC NC VSS VDDQ NC NC N
PNCNC
AATDIA1 TDO A A ANC P
RLBO
NC AATMSA0 TCK AAAAR
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.03a 5/2003 6/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
165 Bump BGA—x32 Common I/O—Top View (Package D)
1234567891011
ANC
AE1BC BB E3 CKE ADV AANC A
BNC
AE2BDBA CK W G A ANC B
CNCNC
VDDQ VSS VSS VSS VSS VSS VDDQ NC NC C
DDQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB D
EDQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB E
FDQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB F
GDQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB G
HFT
MCH NC VDD VSS VSS VSS VDD NC NC ZZ H
JDQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA J
KDQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA K
LDQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA L
MDQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA M
NNCNC
VDDQ VSS NC NC NC VSS VDDQ NC NC N
PNCNC
AATDIA1 TDO A A ANC P
RLBO
NC AATMSA0 TCK AAAAR
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.03a 5/2003 7/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
165 Bump BGA—x36 Common I/O—Top View (Package D)
1234567891011
ANC
AE1BC BB E3 CKE ADV AANC A
BNC
AE2BDBA CK W G A ANC B
CDQPC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPB C
DDQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB D
EDQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB E
FDQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB F
GDQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB G
HFT
MCH NC VDD VSS VSS VSS VDD NC NC ZZ H
JDQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA J
KDQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA K
LDQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA L
MDQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA M
NDQPD NC VDDQ VSS NC NC NC VSS VDDQ NC DQPA N
PNCNC
AATDIA1 TDO A A ANC P
RLBO
NC AATMSA0 TCK AAAAR
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 1.03a 5/2003 8/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
GS8161Z18/32/36AD 165-Bump BGA Pin Description
Symbol Type Description
A0, A1I Address field LSBs and Address Counter Preset Inputs
A I Address Inputs
DQA
DQB
DQC
DQD
I/O Data Input and Output pins
BA, BB, BC, BDI Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
NC — No Connect
CK I Clock Input Signal; active high
CKE I Clock Input Buffer Enable; active low
WI Write Enable; active low
E1I Chip Enable; active low
E3I Chip Enable; active low
E2I Chip Enable; active high
GI Output Enable; active low
ADV I Burst address counter advance enable; active high
ZZ I Sleep mode control; active high
FT I Flow Through or Pipeline mode; active low
LBO I Linear Burst Order mode; active low
TMS I Scan Test Mode Select
TDI I Scan Test Data In
TDO O Scan Test Data Out
TCK I Scan Test Clock
MCH — Must Connect High
VDD I Core power supply
VSS I I/O and Core Ground
VDDQ I Output driver power supply
Rev: 1.03a 5/2003 9/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
GS8161Z18/32/36A NBT SRAM Functional Block Diagram
K
18
SA1
SA0 Burst
Counter
LBO
ADV
Memory
Array
G
CK
CKE
D Q
FT
DQa–DQn
K
SA1’
SA0’
D Q
Match
Write Address
Register 2
Write Address
Register 1
Write Data
Register 2
Write Data
Register 1
KK
KK
K
K
Sense Amps
Write Drivers
Read, Write and
Data Coherency
Control Logic
FT
A0–An
E3
E2
E1
W
BD
BC
BB
BA
Rev: 1.03a 5/2003 10/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2 and E3). Deassertion of any one of the Enable
inputs will deactivate the device.
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The
Byte Write Enable inputs (BA, BB, BC & BD) determine which bytes will be written. All or none may be activated. A write cycle
with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the
write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising
edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the
third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use
of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new
address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Function W BABBBCBD
Read H X X X X
Write Byte “a” L L H H H
Write Byte “b” L H L H H
Write Byte “c” L H H L H
Write Byte “d” L H H H L
Write all Bytes L L L L L
Write Abort/NOP L H H H H
Rev: 1.03a 5/2003 11/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
Synchronous Truth Table
Operation Type Address E1E2E3ZZ ADV W Bx GCKE CK DQ Notes
Deselect Cycle, Power Down D None H X X L L X X X L L-H High-Z
Deselect Cycle, Power Down D None X X H L L X X X L L-H High-Z
Deselect Cycle, Power Down D None X L X L L X X X L L-H High-Z
Deselect Cycle, Continue D None X X X L H X X X L L-H High-Z 1
Read Cycle, Begin Burst R External L H L L L H X L L L-H Q
Read Cycle, Continue Burst B Next X X X L H X X L L L-H Q 1,10
NOP/Read, Begin Burst R External L H L L L H X H L L-H High-Z 2
Dummy Read, Continue Burst B Next X X X L H X X H L L-H High-Z 1,2,10
Write Cycle, Begin Burst W External L H L L L L L X L L-H D 3
Write Cycle, Continue Burst B Next X X X L H X L X L L-H D 1,3,10
NOP/Write Abort, Begin Burst W None L H L L L L H X L L-H High-Z 2,3
Write Abort, Continue Burst B Next X X X L H X H X L L-H High-Z 1,2,3,10
Clock Edge Ignore, Stall Current X X X L X X X X H L-H - 4
Sleep Mode None X X X H X X X X X X High-Z
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Deselect
cycle is executed first.
2. Dummy Read and Write abort can be considered NOP’s because the SRAM performs no operation. A Write abort occurs when the W pin
is sampled low but no Byte Write pins are active so no Write operation is performed.
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during Write
cycles.
4. If CKE High occurs during a pipelined Read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a Write cycle, the bus
will remain in High Z.
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals
are low
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
Rev: 1.03a 5/2003 12/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
Deselect
New Read New Write
Burst Read Burst Write
W
R
B
R
B
W
DD
B
B
W
R
DB
W
R
DD
Pipelined and Flow Through Read Write Control State Diagram
Current State (n) Next State (n+1)
Transition
ƒ
Input Command Code
Key Notes:
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Synchronous Truth Table.
Clock (CK)
Command
Current State Next State
ƒ
n n+1 n+2 n+3
ƒƒƒ
Current State and Next State Definition for Pipelined and Flow Through Read/Write Control State Diagram
WR
Rev: 1.03a 5/2003 13/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
Intermediate Intermediate
Intermediate
Intermediate Intermediate
Intermediate
High Z
(Data In)
Data Out
(Q Valid)
High Z
BWB
R
B
D
R
W
R
W
DD
Pipeline Mode Data I/O State Diagram
Current State (n) Next State (n+2)
Transition
ƒ
Input Command Code
Key
Transition
Intermediate State (N+1)
Notes:
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Clock (CK)
Command
Current State Intermediate
ƒ
n n+1 n+2 n+3
ƒƒƒ
Current State and Next State Definition for Pipeline Mode Data I/O State Diagram
Next State
State
Rev: 1.03a 5/2003 14/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
High Z
(Data In)
Data Out
(Q Valid)
High Z
BWB
R
B
D
R
W
R
W
DD
Current State (n) Next State (n+1)
Transition
ƒ
Input Command Code
Key Notes:
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Flow Through Mode Data I/O State Diagram
Clock (CK)
Command
Current State Next State
ƒ
n n+1 n+2 n+3
ƒƒƒ
Current State and Next State Definition for: Pipeline and Flow through Read Write Control State Diagram
Rev: 1.03a 5/2003 15/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
Note:
There are pull-up devices on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip
will operate in the default states as specified in the above tables.
Burst Counter Sequences
BPR 1999.05.18
Mode Pin Functions
Mode Name Pin
Name State Function
Burst Order Control LBO L Linear Burst
H Interleaved Burst
Output Register Control FT L Flow Through
H or NC Pipeline
Power Down Control ZZ L or NC Active
H Standby, IDD = ISB
Linear Burst Sequence
N
ote: The burst counter wraps to initial state on the 5th clock.
Interleaved Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 10 11 00
3rd address 10 11 00 01
4th address 11 00 01 10
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 00 11 10
3rd address 10 11 00 01
4th address 11 10 01 00
Rev: 1.03a 5/2003 16/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipelinemode via the FT signal found
on Pin 14. Not all vendors offer this option, however most mark Pin 14 as VDD or VDDQ on pipelined parts and VSS on flow
through parts. GSI NBT SRAMs are fully compatible with these sockets.
CK
ZZ tZZR
tZZH
tZZS
~
~
~
~
Sleep
~
~
~
~~
~
Rev: 1.03a 5/2003 17/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to
Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of
time, may affect reliability of this component.
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol Description Value Unit
VDD Voltage on VDD Pins –0.5 to 4.6 V
VDDQ Voltage in VDDQ Pins –0.5 to 4.6 V
VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 (≤ 4.6 V max.) V
VIN Voltage on Other Input Pins –0.5 to VDD +0.5 (≤ 4.6 V max.) V
IIN Input Current on Any Pin +/–20 mA
IOUT Output Current on Any I/O Pin +/–20 mA
PDPackage Power Dissipation 1.5 W
TSTG Storage Temperature –55 to 125 oC
TBIAS Temperature Under Bias –55 to 125 oC
Rev: 1.03a 5/2003 18/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
Power Supply Voltage Ranges
Parameter Symbol Min. Typ. Max. Unit Notes
3.3 V Supply Voltage VDD3 3.0 3.3 3.6 V
2.5 V Supply Voltage VDD2 2.3 2.5 2.7 V
3.3 V VDDQ I/O Supply Voltage VDDQ3 3.0 3.3 3.6 V
2.5 V VDDQ I/O Supply Voltage VDDQ2 2.3 2.5 2.7 V
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
VDDQ3 Range Logic Levels
Parameter Symbol Min. Typ. Max. Unit Notes
VDD Input High Voltage VIH 2.0 —VDD + 0.3 V1
VDD Input Low Voltage VIL –0.3 —0.8 V 1
VDDQ I/O Input High Voltage VIHQ 2.0 —VDDQ + 0.3 V1,3
VDDQ I/O Input Low Voltage VILQ –0.3 —0.8 V 1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
VDDQ2 Range Logic Levels
Parameter Symbol Min. Typ. Max. Unit Notes
VDD Input High Voltage VIH 0.6*VDD —VDD + 0.3 V1
VDD Input Low Voltage VIL –0.3 —0.3*VDD V1
VDDQ I/O Input High Voltage VIHQ 0.6*VDD —VDDQ + 0.3 V1,3
VDDQ I/O Input Low Voltage VILQ –0.3 —0.3*VDD V1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
Rev: 1.03a 5/2003 19/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
Note: These parameters are sample tested.
Notes:
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-
ature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1
Recommended Operating Temperatures
Parameter Symbol Min. Typ. Max. Unit Notes
Ambient Temperature (Commercial Range Versions) TA02570°C2
Ambient Temperature (Industrial Range Versions) TA–40 25 85 °C2
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 2.5 V)
Parameter Symbol Test conditions Typ. Max. Unit
Input Capacitance CIN VIN = 0 V 45pF
Input/Output Capacitance CI/O VOUT = 0 V 67pF
Package Thermal Characteristics
Rating Layer Board Symbol Max Unit Notes
Junction to Ambient (at 200 lfm) single RΘJA 40 °C/W 1,2
Junction to Ambient (at 200 lfm) four RΘJA 24 °C/W 1,2
Junction to Case (TOP) —RΘJC 9°C/W 3
20% tKC
V
SS – 2.0 V
50%
VSS
VIH
Undershoot Measurement and Timing Overshoot Measurement and Timing
20% tKC
VDD + 2.0 V
50%
VDD
VIL
Rev: 1.03a 5/2003 20/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
AC Test Conditions
Parameter Conditions
Input high level VDD – 0.2 V
Input low level 0.2 V
Input slew rate 1 V/ns
Input reference level VDD/2
Output reference level VDDQ/2
Output load Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
DC Electrical Characteristics
Parameter Symbol Test Conditions Min Max
Input Leakage Current
(except mode pins) IIL VIN = 0 to VDD –1 uA 1 uA
ZZ Input Current IIN1
VDD ≥ VIN ≥ VIH
0 V ≤ VIN ≤ VIH
–1 uA
–1 uA
1 uA
100 uA
FT Input Current IIN2
VDD ≥ VIN ≥ VIL
0 V ≤ VIN ≤ VIL
–100 uA
–1 uA
1 uA
1 uA
Output Leakage Current IOL Output Disable, VOUT = 0 to VDD –1 uA 1 uA
Output High Voltage VOH2 IOH = –8 mA, VDDQ = 2.375 V 1.7 V —
Output High Voltage VOH3 IOH = –8 mA, VDDQ = 3.135 V 2.4 V —
Output Low Voltage VOL IOL = 8 mA —0.4 V
DQ
VDDQ/2
50Ω30pF*
Output Load 1
* Distributed Test Jig Capacitance
Rev: 1.03a 5/2003 21/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
Operating Currents
Notes:
1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation.
2. All parameters listed are worst case scenario.
Parameter Test Conditions Mode Symbol
-300 -250 -200 -150
Unit
0
to 70°C
–40
to 85°C
0
to 70°C
–40
to 85°C
0
to 70°C
–40
to 85°C
0
to 70°C
–40
to 85°C
Operating
Current
Device Selected;
All other inputs
≥VIH or ≤ VIL
Output open
(x32/
x36)
Pipeline IDD
IDDQ
345
45
355
45
290
40
300
40
240
30
250
30
190
20
200
20 mA
Flow Through IDD
IDDQ
240
30
250
30
220
20
230
20
190
15
200
15
175
15
185
15 mA
(x18)
Pipeline IDD
IDDQ
310
25
320
25
260
20
270
20
215
15
225
15
170
15
180
15 mA
Flow Through IDD
IDDQ
215
15
225
15
200
10
210
10
175
10
185
10
160
10
170
10 mA
Standby
Current ZZ ≥ VDD – 0.2 V —
Pipeline ISB 40 50 40 50 40 50 40 50 mA
Flow Through ISB 40 50 40 50 40 50 40 50 mA
Deselect
Current
Device Deselected;
All other inputs
≥ VIH or ≤ VIL
—
Pipeline IDD 85 90 85 90 75 80 60 65 mA
Flow Through IDD 60 65 60 65 50 55 50 55 mA
Rev: 1.03a 5/2003 22/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
AC Electrical Characteristics
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times
as specified above.
Parameter Symbol -300 -250 -200 -150 Unit
Min Max Min Max Min Max Min Max
Pipeline
Clock Cycle Time tKC 3.3 —4.0 —5.0 —6.7 —ns
Clock to Output Valid tKQ —2.5 —2.5 —3.0 —3.8 ns
Clock to Output Invalid tKQX 1.5 —1.5 —1.5 —1.5 —ns
Clock to Output in Low-Z tLZ11.5 —1.5 —1.5 —1.5 —ns
Setup time tS 1.0 —1.2 —1.4 —1.5 —ns
Hold time tH 0.1 —0.2 —0.4 —0.5 —ns
Flow Through
Clock Cycle Time tKC 5.0 —5.5 —6.5 —7.5 —ns
Clock to Output Valid tKQ —5.0 —5.5 —6.5 —7.5 ns
Clock to Output Invalid tKQX 3.0 —3.0 —3.0 —3.0 —ns
Clock to Output in Low-Z tLZ13.0 —3.0 —3.0 —3.0 —ns
Setup time tS 1.4 —1.5 —1.5 —1.5 —ns
Hold time tH 0.4 —0.5 —0.5 —0.5 —ns
Clock HIGH Time tKH 1.3 —1.3 —1.3 —1.5 —ns
Clock LOW Time tKL 1.5 —1.5 —1.5 —1.7 —ns
Clock to Output in
High-Z tHZ11.5 2.5 1.5 2.5 1.5 3.0 1.5 3.0 ns
G to Output Valid tOE —2.5 —2.5 —3.0 —3.8 ns
G to output in Low-Z tOLZ10—0—0—0—ns
G to output in High-Z tOHZ1—2.5 —2.5 —3.0 —3.8 ns
ZZ setup time tZZS25—5—5—5—ns
ZZ hold time tZZH21—1—1—1—ns
ZZ recovery tZZR 20 —20 —20 —20 —ns
Rev: 1.03a 5/2003 23/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
Pipeline Mode Timing (NBT)
Write A Read B Suspend Read C Write D Suspend1 Write Read E Deselect
tHZ
tKQX
tKQ
tLZ
tS
tKQXtKQ
tKQ
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tKCtKC
tKLtKL
tKHtKH
AB CD
D(A) Q(B) Q(C) D(D) Q(E)
E
CK
CKE
E
ADV
W
Bn
A0–An
DQ
Rev: 1.03a 5/2003 24/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
Flow Through Mode Timing (NBT)
Write A Read B Suspend Read C Write D1 Suspend1 Write Read E Deselect
tHZ
tKQXtLZ
tHZ
tKQXtKQ
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tKCtKC
tKLtKL
tKHtKH
AB CD E
D(A) Q(B) Q(C) D(D) Q(E)
CK
CKE
E
ADV
W
Bn
A0–An
DQ
Rev: 1.03a 5/2003 25/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output
drivers are powered by VDDQ.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and
0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising
edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI
and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
JTAG Pin Descriptions
Pin Pin Name I/O Description
TCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TMS Test Mode Select In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
TDI Test Data In In
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
TDO Test Data Out Out
Output that is active depending on the state of the TAP state machine. Output changes in
response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
Rev: 1.03a 5/2003 26/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Die
Revision
Code
Not Used I/O
Configuration
GSI Technology
JEDEC Vendor
ID Code
Presence Register
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
x36 XXXX0000000000001000000110110011
x18 XXXX0000000000001010000110110011
Instruction Register
ID Code Register
Boundary Scan Register
012
012
····
31 30 29
012
···
······
n
0
Bypass Register
TDI TDO
TMS
TCK Test Access Port (TAP) Controller
Rev: 1.03a 5/2003 27/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
JTAG Tap Controller State Diagram
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when
the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices
in the scan path.
Select DR
Capture DR
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
Select IR
Capture IR
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
Test Logic Reset
Run Test Idle
0
0
1
0
1
1
0
0
1
1
1
0
0
1
1
0
00
0
1
1
0 0
110
0
0
1
111
Rev: 1.03a 5/2003 28/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruc-
tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan
Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the
Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it
is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although
allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be
stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be
paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-
DR state then places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The
EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins.
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST
command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK when
the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the
sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in
parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the value of the
Boundary Scan Register location with which each output pin is associated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID
register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any
time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the Bound-
ary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
Rev: 1.03a 5/2003 29/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
JTAG TAP Instruction Set Summary
Instruction Code Description Notes
EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1
IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2
SAMPLE-Z 010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.
1
RFU 011 Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1
SAMPLE/
PRELOAD 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO. 1
GSI 101 GSI private instruction. 1
RFU 110 Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1
BYPASS 111 Places Bypass Register between TDI and TDO. 1
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 1.03a 5/2003 30/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter Symbol Min. Max. Unit Notes
3.3 V Test Port Input High Voltage VIHJ3 2.0 VDD3 +0.3 V1
3.3 V Test Port Input Low Voltage VILJ3 –0.3 0.8 V 1
2.5 V Test Port Input High Voltage VIHJ2 0.6 * VDD2 VDD2 +0.3 V1
2.5 V Test Port Input Low Voltage VILJ2 –0.3 0.3 * VDD2 V1
TMS, TCK and TDI Input Leakage Current IINHJ –300 1 uA 2
TMS, TCK and TDI Input Leakage Current IINLJ –1 100 uA 3
TDO Output Leakage Current IOLJ –11uA4
Test Port Output High Voltage VOHJ 1.7 —V5, 6
Test Port Output Low Voltage VOLJ —0.4 V 5, 7
Test Port Output CMOS High VOHJC VDDQ – 100 mV —V5, 8
Test Port Output CMOS Low VOLJC —100 mV V 5, 9
Notes:
1. Input Under/overshoot voltage must be –2 V > Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
2. VILJ ≤ VIN ≤ VDDn
3. 0 V ≤ VIN ≤ VILJn
4. Output Disable, VOUT = 0 to VDDn
5. The TDO output driver is served by the VDDQ supply.
6. IOHJ = –4 mA
7. IOLJ = + 4 mA
8. IOHJC = –100 uA
9. IOHJC = +100 uA
Notes:
1. Include scope and jig capacitance.
2. Test conditions as as shown unless otherwise noted.
JTAG Port AC Test Conditions
Parameter Conditions
Input high level VDD – 0.2 V
Input low level 0.2 V
Input slew rate 1 V/ns
Input reference level VDDQ/2
Output reference level VDDQ/2
DQ
VDDQ/2
50Ω30pF*
JTAG Port AC Test Load
* Distributed Test Jig Capacitance
Rev: 1.03a 5/2003 31/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
JTAG Port Timing Diagram
JTAG Port AC Electrical Characteristics
Boundary Scan (BSDL Files)
For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications
Engineering Department at: apps@gsitechnology.com.
Parameter Symbol Min Max Unit
TCK Cycle Time tTKC 50 —ns
TCK Low to TDO Valid tTKQ —20 ns
TCK High Pulse Width tTKH 20 —ns
TCK Low Pulse Width tTKL 20 —ns
TDI & TMS Set Up Time tTS 10 —ns
TDI & TMS Hold Time tTH 10 —ns
tTKQ
tTS tTH
tTKH tTKL
TCK
TMS
TDI
TDO
tTKC
Rev: 1.03a 5/2003 32/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
TQFP Pack age Drawin g
BPR 1999.05.18
D1
D
E1
E
Pin 1
b
e
c
L
L1
A2
A1
Y
θ
TQFP Package Drawing
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
Symbol Description Min. Nom. Max
A1 Standoff 0.05 0.10 0.15
A2 Body Thickness 1.35 1.40 1.45
b Lead Width 0.20 0.30 0.40
c Lead Thickness 0.09 0.20
D Terminal Dimension 21.9 22.0 20.1
D1 Package Body 19.9 20.0 20.1
E Terminal Dimension 15.9 16.0 16.1
E1 Package Body 13.9 14.0 14.1
e Lead Pitch 0.65
L Foot Length 0.45 0.60 0.75
L1 Lead Length 1.00
Y Coplanarity 0.10
θLead Angle 0°7°
Rev: 1.03a 5/2003 33/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
Package Dimensions—165-Bump FPBGA (Package D)
A
B
C
D
E
F
G
H
I
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1
A1 CORNER TOP VIEW A1 CORNER
BOTTOM VIEW
1.0 1.0
10.0
1.01.0
14.0
13±0.07
15±0.07
A
B
0.20(4x)
Ø0.10
Ø0.25
C
C A B
M
M
Ø0.40~0.50 (165x)
CSEATING PLANE
0.15 C
0.25~0.40
1.20 MAX.
0.45±0.05
0.25 C
(0.26)
Rev: 1.03a 5/2003 34/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
Ordering Information—GSI NBT Synchronous SRAM
Org Part Number1Type Package Speed2
(MHz/ns) TA3Status
1M x 18 GS8161Z18AT-300 Pipeline/Flow Through TQFP 300/5 C
1M x 18 GS8161Z18AT-250 Pipeline/Flow Through TQFP 250/5.5 C
1M x 18 GS8161Z18AT-200 Pipeline/Flow Through TQFP 200/6.5 C
1M x 18 GS8161Z18AT-150 Pipeline/Flow Through TQFP 150/7.5 C
1M x 18 GS8161Z18AD-300 Pipeline/Flow Through 165 BGA 300/5 C
1M x 18 GS8161Z18AD-250 Pipeline/Flow Through 165 BGA 250/5.5 C
1M x 18 GS8161Z18AD-200 Pipeline/Flow Through 165 BGA 200/6.5 C
1M x 18 GS8161Z18AD-150 Pipeline/Flow Through 165 BGA 150/7.5 C
512K x 32 GS8161Z32AD-300 Pipeline/Flow Through 165 BGA 300/5 C
512K x 32 GS8161Z32AD-250 Pipeline/Flow Through 165 BGA 250/5.5 C
512K x 32 GS8161Z32AD-200 Pipeline/Flow Through 165 BGA 200/6.5 C
512K x 32 GS8161Z32AD-150 Pipeline/Flow Through 165 BGA 150/7.5 C
512K x 36 GS8161Z36AT-300 Pipeline/Flow Through TQFP 300/5 C
512K x 36 GS8161Z36AT-250 Pipeline/Flow Through TQFP 250/5.5 C
512K x 36 GS8161Z36AT-200 Pipeline/Flow Through TQFP 200/6.5 C
512K x 36 GS8161Z36AT-150 Pipeline/Flow Through TQFP 150/7.5 C
512K x 36 GS8161Z36AD-300 Pipeline/Flow Through 165 BGA 300/5 C
512K x 36 GS8161Z36AD-250 Pipeline/Flow Through 165 BGA 250/5.5 C
512K x 36 GS8161Z36AD-200 Pipeline/Flow Through 165 BGA 200/6.5 C
512K x 36 GS8161Z36AD-150 Pipeline/Flow Through 165 BGA 150/7.5 C
1M x 18 GS8161Z18AT-300I Pipeline/Flow Through TQFP 300/5 I
1M x 18 GS8161Z18AT-250I Pipeline/Flow Through TQFP 250/5.5 I
1M x 18 GS8161Z18AT-200I Pipeline/Flow Through TQFP 200/6.5 I
1M x 18 GS8161Z18AT-150I Pipeline/Flow Through TQFP 150/7.5 I
1M x 18 GS8161Z18AD-300I Pipeline/Flow Through 165 BGA 300/5 I
1M x 18 GS8161Z18AD-250I Pipeline/Flow Through 165 BGA 250/5.5 I
1M x 18 GS8161Z18AD-200I Pipeline/Flow Through 165 BGA 200/6.5 I
1M x 18 GS8161Z18AD-150I Pipeline/Flow Through 165 BGA 150/7.5 I
512K x 32 GS8161Z32AD-300I Pipeline/Flow Through 165 BGA 300/5 I
512K x 32 GS8161Z32AD-250I Pipeline/Flow Through 165 BGA 250/5.5 I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8161Z18AT-150IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.03a 5/2003 35/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
512K x 32 GS8161Z32AD-200I Pipeline/Flow Through 165 BGA 200/6.5 I
512K x 32 GS8161Z32AD-150I Pipeline/Flow Through 165 BGA 150/7.5 I
512K x 36 GS8161Z36AT-300I Pipeline/Flow Through TQFP 300/5 I
512K x 36 GS8161Z36AT-250I Pipeline/Flow Through TQFP 250/5.5 I
512K x 36 GS8161Z36AT-200I Pipeline/Flow Through TQFP 200/6.5 I
512K x 36 GS8161Z36AT-150I Pipeline/Flow Through TQFP 150/7.5 I
512K x 36 GS8161Z36AD-300I Pipeline/Flow Through 165 BGA 300/5 I
512K x 36 GS8161Z36AD-250I Pipeline/Flow Through 165 BGA 250/5.5 I
512K x 36 GS8161Z36AD-200I Pipeline/Flow Through 165 BGA 200/6.5 I
512K x 36 GS8161Z36AD-150I Pipeline/Flow Through 165 BGA 150/7.5 I
Org Part Number1Type Package Speed2
(MHz/ns) TA3Status
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8161Z18AT-150IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.03a 5/2003 36/36 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161Z18A(T/D)/GS8161Z32A(D)/GS8161Z36A(T/D)
Preliminary
18Mb Sync SRAM Data Sheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content Page;Revisions;Reason
8161Z18A_r1 • Creation of new datasheet
8161Z18A_r1;
8161Z18A_r1_01 Content
• Updated FT power numbers
• Updated AC Characteristics table
• Updated ZZ recovery time diagram
• Updated AC Test Conditions table and removed Output Load
2 diagram
8161Z18A_r1_01;
8161Z18A_r1_02 Content
• Removed extraneous VDDQ1 table on page 12 and changed
VDDQ2 table to VDDQ
• Removed pin locations from pin description table
• Removed BSR table
GS8161ZxxA_r1_02;
GS8161ZxxA_r1_03 Content • Entire datasheet rewritten due to design changes
