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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DLow rDS(on) ...5 Ω Typical
DAvalanche Energy . . . 30 mJ
DEight Power DMOS-Transistor Outputs of
150-mA Continuous Current
D500-mA Typical Current-Limiting Capability
DOutput Clamp Voltage ...50 V
DDevices Are Cascadable
DLow Power Consumption
description
The TPIC6B595 is a monolithic, high-voltage,
medium-current power 8-bit shift register
designed for use in systems that require relatively
high load power. The device contains a built-in
voltage clamp on the outputs for inductive
transient protection. Power driver applications
include relays, solenoids, and other medium-
current or high-voltage loads.
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage
register. Data transfers through both the shift and
storage registers on the rising edge of the
shift-register clock (SRCK) and the register clock
(RCK), respectively. The storage register
transfers data to the output buffer when shift-
register clear (SRCLR) is high. When SRCLR is
low , the input shift register is cleared. When output
enable (G) is held high, all data in the output
buffers is held low and all drain outputs are off.
When G is held low, data from the storage register
is transparent to the output buffers. When data in
the output buffers is low, the DMOS-transistor
outputs are off. When data is high, the DMOS-
transistor outputs have sink-current capability.
The serial output (SER OUT) allows for cascading
of the data from the shift register to additional
devices.
Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and 150-mA continuous sink-
current capability. Each output provides a 500-mA typical current limit at TC = 25°C. The current limit decreases
as the junction temperature increases for additional device protection.
The TPIC6B595 is characterized for operation over the operating case temperature range of −40°C to 125°C.
Copyright 1995 − 2005, Texas Instruments Incorporated
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1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
VCC
SER IN
DRAIN0
DRAIN1
DRAIN2
DRAIN3
SRCLR
G
GND
NC
GND
SER OUT
DRAIN7
DRAIN6
DRAIN5
DRAIN4
SRCK
RCK
GND
DW OR N PACKAGE
(TOP VIEW)
logic symbol†
2
SRG8
†This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
9
12
8
13
3
EN3
C2
R
C1
1D
G
RCK
SRCLR
SRCK
SER IN 4
6
5
14
7
16
15
18
17
DRAIN0
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
SER OUT
2
NC − No internal connection
SLIS032A − JULY 1995 − REVISED MAY 2005
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
G
RCK
SRCLR
SRCK
SER IN CLR
D
C1
DC2
CLR
D
C1
SER OUT
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
DC2
DC2
DC2
DC2
DC2
DC2
DC2
4DRAIN0
5DRAIN1
10, 11, 19 GND
6DRAIN2
7DRAIN3
14 DRAIN4
15 DRAIN5
16 DRAIN6
17 DRAIN7
9
8
3
12
13
18
SLIS032A − JULY 1995 − REVISED MAY 2005
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schematic of inputs and outputs
EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS
VCC
Input
GND GND
DRAIN
50 V
20 V
25 V
12 V
absolute maximum ratings over recommended operating case temperature range (unless
otherwise noted)†
Logic supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic input voltage range, VI −0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power DMOS drain-to-source voltage, VDS (see Note 2) 50 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous source-to-drain diode anode current 500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed source-to-drain diode anode current (see Note 3) 1 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed drain current, each output, all outputs on, ID, TC = 25°C (see Note 3) 500 mA. . . . . . . . . . . . . . . . . . .
Continuous drain current, each output, all outputs on, ID, TC = 25°C 150 mA. . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak drain current single output, IDM,TC = 25°C (see Note 3) 500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-pulse avalanche energy, EAS (see Figure 4) 30 mJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Avalanche current, IAS (see Note 4) 500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ −40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature range, TC −40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. Each power DMOS source is internally connected to GND.
3. Pulse duration ≤ 100 µs and duty cycle ≤ 2%.
4. DRAIN supply voltage = 15 V, starting junction temperature (TJS) = 25°C, L = 200 mH, IAS = 0.5 A (see Figure 4).
DISSIPATION RATING TABLE
PACKAGE TC ≤ 25°C
POWER RATING DERATING FACTOR
ABOVE TC = 25°CTC = 125°C
POWER RATING
DW 1389 mW 11.1 mW/°C278 mW
N1050 mW 10.5 mW/°C263 mW
SLIS032A − JULY 1995 − REVISED MAY 2005
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN MAX UNIT
Logic supply voltage, VCC 4.5 5.5 V
High-level input voltage, VIH 0.85 VCC V
Low-level input voltage, VIL 0.15 VCC V
Pulsed drain output current, TC = 25°C, VCC = 5 V (see Notes 3 and 5) −500 500 mA
Setup time, SER IN high before SRCK↑, tsu (see Figure 2) 20 ns
Hold time, SER IN high after SRCK↑, th (see Figure 2) 20 ns
Pulse duration, tw (see Figure 2) 40 ns
Operating case temperature, TC−40 125 °C
electrical characteristics, VCC = 5 V, TC = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(BR)DSX Drain-to-source breakdown voltage ID = 1 mA 50 V
VSD Source-to-drain diode forward
voltage IF = 100 mA 0.85 1 V
VOH
High-level output voltage,
IOH = −20 µA, VCC = 4.5 V 4.4 4.49
V
VOH
High-level output voltage,
SER OUT IOH = −4 mA, VCC = 4.5 V 4 4.2 V
VOL
Low-level output voltage,
IOL = 20 µA, VCC = 4.5 V 0.005 0.1
V
VOL
Low-level output voltage,
SER OUT IOL = 4 mA, VCC = 4.5 V 0.3 0.5 V
IIH High-level input current VCC = 5.5 V, VI = VCC 1µA
IIL Low-level input current VCC = 5.5 V, VI = 0 −1 µA
ICC
Logic supply current
VCC = 5.5 V
All outputs off 20 100
A
ICC Logic supply current VCC = 5.5 V All outputs on 150 300 µA
ICC(FRQ) Logic supply current at frequency fSRCK = 5 MHz,CL = 30 pF,
All outputs off, See Figures 2 and 6 0.4 5 mA
INNominal current VDS(on) = 0.5 V,
IN = ID,T
C = 85°CSee Notes 5, 6, and 7 90 mA
IDSX
Off-state drain current
VDS = 40 V, VCC = 5.5 V 0.1 5
A
IDSX Off-state drain current VDS = 40 V, VCC = 5.5 V, TC = 125°C0.15 8 µA
ID = 100 mA, VCC = 4.5 V 4.2 5.7
rDS(on) Static drain-source on-state
resistance ID = 100 mA, TC = 125°C,
VCC = 4.5 V See Notes 5 and 6
and Figures 7 and 8 6.8 9.5 Ω
resistance
ID = 350 mA, VCC = 4.5 V
and Figures 7 and 8
5.5 8
NOTES: 3. Pulse duration ≤ 100 µs and duty cycle ≤ 2%.
5. Technique should limit TJ − TC to 10°C maximum.
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
7. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a
voltage drop of 0.5 V at TC = 85°C.
SLIS032A − JULY 1995 − REVISED MAY 2005
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics, VCC = 5 V, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low-to-high-level output from G 150 ns
tPHL Propagation delay time, high-to-low-level output from G
CL = 30 pF, ID = 100 mA,
90 ns
trRise time, drain output
CL = 30 pF, ID = 100 mA,
See Figures 1, 2, and 9 200 ns
tfFall time, drain output
See Figures 1, 2, and 9
200 ns
taReverse-recovery-current rise time
IF = 100 mA, di/dt = 20 A/µs,
100
ns
trr Reverse-recovery time
IF = 100 mA, di/dt = 20 A/µs,
See Notes 5 and 6 and Figure 3 300 ns
NOTES: 5. Technique should limit TJ − TC to 10°C maximum.
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
thermal resistance
PARAMETER TEST CONDITIONS MIN MAX UNIT
RθJA
Thermal resistance, junction-to-ambient
DW package
All 8 outputs with equal power
90
°C/W
R
θJA
Thermal resistance, junction-to-ambient
N package
All 8 outputs with equal power
95 °
C/W
PARAMETER MEASUREMENT INFORMATION
TEST CIRCUIT
5 V
VCC
DRAIN
GND
SRCLR
SER IN
RL = 235 Ω
CL = 30 pF
(see Note B)
VOLTAGE WAVEFORMS
G
Output
SRCK
RCK
Word
Generator
(see Note A)
76543210 5 V
SRCK
5 V
G
5 V
SER IN
RCK
SRCLR
5 V
5 V
DUT
24 V
DRAIN1
24 V
0 V
0 V
0 V
0.5
V
0 V
10, 11, 19
8
13
3
12
9
0 V
4−7,
14−17
ID
2
NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 1. Resistive-Load Test Circuit and Voltage Waveforms
SLIS032A − JULY 1995 − REVISED MAY 2005
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
4−7,
14−17
TEST CIRCUIT
SWITCHING TIMES
G
5 V
50%
24 V
0.5 V
90%
10%
tPLH
tr
50%
90% 10%
tPHL
tf
SRCK
5 V
50%
SER IN 5 V
50% 50%
tsu th
tw
INPUT SETUP AND HOLD WAVEFORMS
5 V 24 V
VCC
DRAIN
SRCLR
SER IN
RL = 235 Ω
CL = 30 pF
(see Note B)
G
Output
SRCK
RCK
DUT
GND
Output
Word
Generator
(see Note A)
10, 11, 19
8
13
3
12
9
0 V
0 V
0 V
ID
2
NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 2. Test Circuit, Switching Times, and Voltage Waveforms
0.1 A
IF
0
IRM
25% of IRM
ta
trr
di/dt = 20 A/µs
+
−
2500 µF
250 V
L = 1 mH
IF
(see Note A)
RG
VGG
(see Note B)
Driver
TP A
50 Ω
Circuit
Under
Test
DRAIN
25 V
t1t3
t2
TP K
TEST CIRCUIT CURRENT WAVEFORM
NOTES: A. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the
TP A test point.
B. The VGG amplitude and RG are adjusted for di/dt = 20 A/µs. A VGG double-pulse train is used to set IF = 0.1 A, where t1 = 10 µs,
t2 = 7 µs, and t3 = 3 µs.
Figure 3. Reverse-Recovery-Current Test Circuit and Waveforms of Source-to-Drain Diode
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
15 V
10.5 Ω
200 mH
SINGLE-PULSE AVALANCHE ENERGY TEST CIRCUIT
twtav
IAS = 0.5 A
V(BR)DSX = 50 V
VOLTAGE AND CURRENT WAVEFORMS
Input
ID
VDS
See Note B
VCC
DRAIN
SRCLR
SER IN
G
SRCK
RCK
Word
Generator
(see Note A)
DUT
GND
5 V
VDS
ID
2
8
13
3
12
9
10, 11, 19
4−7,
14−17
5 V
0 V
MIN
NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω.
B. Input pulse duration, tw, is increased until peak current IAS = 0.5 A.
Energy test level is defined as EAS = IAS × V(BR)DSX × tav/2 = 30 mJ.
Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms
TYPICAL CHARACTERISTICS
2
1
10
4
0.1 0.2 10.4 2 104
0.2
0.1
0.4
I − Peak Avalanche Current − A
AS
PEAK AVALANCHE CURRENT
vs
TIME DURATION OF AVALANCHE
tav − Time Duration of Avalanche − ms
TC = 25°C
Figure 5
I − Supply Current − mA
CC
SUPPLY CURRENT
vs
FREQUENCY
f − Frequency − MHz
1
0.5
0
0.1 1 10
1.5
2
100
2.5
VCC = 5 V
TC = −40°C to 125°C
Figure 6
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TYPICAL CHARACTERISTICS
Figure 7
10
8
4
2
0
6
0 100 200 300 400
14
12
16
DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
18
500 600 700
ID − Drain Current − mA
VCC = 5 V
See Note A
TC = 25°C
TC = −40°C
TC = 125°C
Ω
DS(on)− Drain-to-Source On-State Resistance −r
Figure 8
VCC − Logic Supply Voltage − V
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
LOGIC SUPPLY VOLTAGE
4
3
1
04 4.5 5 5.5
5
7
8
6 6.5 7
6
2
TC = 125°C
TC = 25°C
TC = − 40°C
ID = 100 mA
See Note A
Ω
DS(on)− Static Drain-to-Source On-State Resistance −r
Switching Time − ns
SWITCHING TIME
vs
CASE TEMPERATURE
−50 T
C
− Case Temperature − °C
ID = 100 mA
See Note A
200
150
100
50
250
300
tPHL
tPLH
tr
tf
−25 0 25 50 75 100 125
Figure 9
NOTE C: Technique should limit TJ − TC to 10°C maximum.
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THERMAL INFORMATION
Figure 10
− Maximum Continuous Drain Current
MAXIMUM CONTINUOUS
DRAIN CURRENT OF EACH OUTPUT
vs
NUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
N − Number of Outputs Conducting Simultaneously
of Each Output − A
D
I
012345678
VCC = 5 V
TC = 25°C
TC = 125°C
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
TC = 100°C
Figure 11
− Maximum Peak Drain Current of Each Output − A
MAXIMUM PEAK DRAIN CURRENT
OF EACH OUTPUT
vs
NUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
D
N − Number of Outputs Conducting Simultaneously
I
0.15
0.05
0.4
012 34 5
0.3
0.2
0.35
0.5
678
0.45
0.25
0.1 VCC = 5 V
TC = 25°C
d = tw/tperiod
= 1 ms/tperiod
d = 10%
d = 20%
d = 50%
d = 80%
Revision History
DATE REV PAGE SECTION DESCRIPTION
5/18/05 A 5 Figure 1 Changed SRCLR timing diagram
7/1995 * Original reversion
NOTE:Page numbers for previous revisions may differ from page numbers in the current version.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPIC6B595DW ACTIVE SOIC DW 20 25 TBD CU NIPDAU Level-1-220C-UNLIM
TPIC6B595DWG4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPIC6B595DWR ACTIVE SOIC DW 20 2000 TBD CU NIPDAU Level-1-220C-UNLIM
TPIC6B595DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPIC6B595N ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 29-May-2007
Addendum-Page 1
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