PCM1744 - Texas Instruments - Datasheet.Directory

1PCM1744

24 Bits, 96kHz,

Sampling Stereo Audio

DIGITAL-TO-ANALOG CONVERTER

PCM1744

DESCRIPTION

The PCM1744 is a complete low cost stereo audio

digital-to-analog converter (DAC), operating off of a

256fS or 384fS system clock. The DAC contains a 3rd-

order ∆Σ modulator, a digital interpolation filter, and

an analog output amplifier. The PCM1744 accepts

24-bit input data in a I2S format.

The digital filter performs an 8x interpolation function

and includes de-emphasis at 44.1kHz. The PCM1744

can accept digital audio sampling frequencies from

16kHz to 96kHz, always at 8X oversampling.

The PCM1744 is ideal for low-cost, CD-quality con-

sumer audio applications.

FEATURES

●COMPLETE STEREO DAC: Includes Digital

Filter and Output Amp

●DYNAMIC RANGE: 95dB

●MULTIPLE SAMPLING FREQUENCIES:

Up to 96kHz

●8x OVERSAMPLING DIGITAL FILTER

●SYSTEM CLOCK: 256fS/384fS

●24-BIT I2S DATA INPUT FORMAT

●SMALL 14-PIN SOIC PACKAGE

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For most current data sheet and other product

information, visit www.burr-brown.com

Serial

Input

I/F

Mode

Control

I/F

8X Oversampling

Digital Filter

SCKI

256f

/384f

GND

Multi-level

Delta-Sigma

Modulator

OUT

CAP

DAC

Multi-level

Delta-Sigma

Modulator

Low-pass

Filter

Low-pass

Filter

OUT

DAC

FORMAT

LRCIN

DIN

BCKIN

DM Power Supply

PCM1744

SBAS130

PCM1744

SPECIFICATIONS

All specifications at +25°C, +VCC = +5V, fS = 44.1kHz, and 18-bit input data, SYSCLK = 384fS, unless otherwise noted.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes

no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change

without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant

any BURR-BROWN product for use in life support devices and/or systems.

PCM1744

PARAMETER CONDITIONS MIN TYP MAX UNITS

RESOLUTION 24 Bits

DATA FORMAT

Audio Data Interface Format I2S

Audio Data Format Two’s Binary Complement

Sampling Frequency (fS)16 96 kHz

Internal System Clock Frequency 256fS/384fS

DIGITAL INPUT/OUTPUT

Logic Level TTL

Input Logic Level

VIH(1) 2.0 VDC

VIL(1) 0.8 VDC

Input Logic Current: IIN(1) ±0.8 µA

DYNAMIC PERFORMANCE(2) f = 991kHz

THD+N at FS (0dB) –83 –79 dB

THD+N at –60dB –32 dB

Dynamic Range EIAJ, A-weighted 90 95 dB

Signal-to-Noise Ratio EIAJ, A-weighted 90 97 dB

Channel Separation 88 95 dB

DC ACCURACY

Gain Error ±1.0 ±10.0 % of FSR

Gain Mismatch, Channel-to-Channel ±1.0 ±5.0 % of FSR

Bipolar Zero Error VOUT = VCC/2 at BPZ ±20 ±50 mV

ANALOG OUTPUT

Output Voltage Full Scale (0dB) 0.62 x VCC Vp-p

Center Voltage VCC/2 VDC

Load Impedance AC Load 10 kΩ

DIGITAL FILTER PERFORMANCE

Passband 0.445 fS

Stopband 0.555 fS

Passband Ripple ±0.17 dB

Stopband Attenuation –35 dB

Delay Time 11.125/fSsec

INTERNAL ANALOG FILTER

–3dB Bandwidth 100 kHz

Passband Response f = 20kHz –0.16 dB

POWER SUPPLY REQUIREMENTS

Voltage Range 4.5 5 5.5 VDC

Supply Current 13 18 mA

Power Dissipation 65 90 mW

TEMPERATURE RANGE

Operation –25 +85 °C

Storage –55 +125 °C

NOTES: (1) Pins 1, 2, 3, 12, 13, 14: LRCIN, DIN, BCKIN, DM, FORMAT, SCKI. (2) Dynamic performance specs are tested with 20kHz low pass filter and THD+N

specs are tested with 30kHz LPF, 400Hz HPF, Average-Mode.

3PCM1744

PIN ASSIGNMENTS

PIN NAME I/O FUNCTION

1(1) LRCIN IN Sample Rate Clock Input

2(1) DIN IN Audio Data Input

3(1) BCKIN IN Bit Clock Input for Audio Data.

4 NC — No Connection

5 CAP — Common Pin of Analog Output Amp

OUTR OUT Right-Channel Analog Output

7 GND — Ground

CC — Power Supply

OUTL OUT Left-Channel Analog Output

10 NC — No Connection

11 NC — No Connection

12(2) DM IN De-Emphasis Control

HIGH: De-emphasis ON

LOW: De-emphasis OFF

13(2) TEST — Test Pin. Must be left open.

14(1) SCKI IN System Clock Input (256fS or 384fS)

NOTE: (1) Schmitt-Trigger input. (2) Schmitt-Trigger input with internal pull-up.

PIN CONFIGURATION

TOP VIEW SOIC

ABSOLUTE MAXIMUM RATINGS

Power Supply Voltage ......................................................................+6.5V

+VCC to +VDD Difference ................................................................... ±0.1V

Input Logic Voltage .................................................. –0.3V to (VDD + 0.3V)

Power Dissipation .......................................................................... 290mW

Operating Temperature Range ......................................... –25°C to +85°C

Storage Temperature...................................................... –55°C to +125°C

Lead Temperature (soldering, 5s).................................................. +260°C

Thermal Resistance,

JA ..............................................................+90°C/W

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown

recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

ESD damage can range from subtle performance degradation

to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric

changes could cause the device not to meet its published

specifications.

PACKAGE SPECIFIED

DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT PACKAGE NUMBER(1) RANGE MARKING NUMBER(2) MEDIA

PCM1744 SO-14 235 –25°C to +85°C PCM1744U PCM1744U Rails

" " " " PCM1744U PCM1744U/2K Tape and Reel

NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book, or visit the Burr-Brown web site

at www.burr-brown.com. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering

2000 pieces of “PCM1744U/2K” will get a single 2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown

IC Data Book.

PACKAGE/ORDERING INFORMATION

LRCIN

DIN

BCKIN

CAP

OUT

GND

SCKI

TEST

OUT

PCM1744

TYPICAL PERFORMANCE CURVES

At TA = +25°C, +VCC = +5V, fS = 44.1kHz, SYSCLK = 256fS, unless otherwise noted.

DYNAMIC PERFORMANCE

THD+N vs TEMPERATURE

Temperature (°C)

THD+N at 0dB (%)

0.009

0.008

0.007

0.006

0.005

0.004

0.003

0.002

0.001

0–25 0 25 50 75 85 100

THD+N at –60dB (%)

3.2

3.1

3.0

2.9

2.8

2.7

2.6

2.5

2.4

2.3

–60dB

0dB

SNR, DYNAMIC RANGE vs TEMPERATURE

Temperature (°C)

SNR (dB)

–25 0 25 50 75 85 100

Dynamic Range (dB)

Dynamic Range

SNR

THD+N vs POWER SUPPLY

(V)

THD+N at 0dB (%)

0.009

0.008

0.007

0.006

0.005

0.004

0.003

0.002

0.001

04.5 4.75 5.0 5.25 5.5

THD+N at –60dB (%)

3.2

3.1

3.0

2.9

2.8

2.7

2.6

2.5

2.4

2.3

–60dB

0dB

SNR, DYNAMIC RANGE vs POWER SUPPLY

(V)

SNR (dB)

4.5 4.75 5.0 5.25 5.5

Dynamic Range (dB)

Dynamic Range

SNR

THD+N vs SAMPLING RATE

Sampling Rate (kHz)

THD+N at 0dB (%)

0.016

0.014

0.012

0.01

0.008

0.006

0.004

5.2

4.7

4.2

3.7

3.2

2.7

2.2

44.1 48 88.2 96

THD+N AT –60dB (%)

–60dB

0dB

SNR, DYNAMIC RANGE vs SAMPLING RATE

Sampling Rate (kHz)

SNR (dB)

44.1 48 88.2 96

Dynamic Range (dB)

Dynamic Range

SNR

5PCM1744

TYPICAL PERFORMANCE CURVES

At TA = +25°C, +VCC = +VDD = +5V, fS = 44.1kHz, and 18-bit input data, SYSCLK = 384fS, unless otherwise noted.

DIGITAL FILTER

0 0.4536f

1.3605f

2.2675f

3.1745f

4.0815f

–20

–40

–60

–80

–100

OVERALL FREQUENCY CHARACTERISTIC

Frequency (Hz)

PASSBAND RIPPLE CHARACTERISTIC

–0.2

–0.4

–0.6

–0.8

–1 0 0.1134fS0.2268fS0.3402fS0.4535fS

Frequency (Hz)

DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz)

Frequency (kHz)

Level (dB)

–2

–4

–6

–8

–10

–12 0 5 10 15 20 25

DE-EMPHASIS FREQUENCY ERROR (44.1kHz)

Frequency (kHz)

Error (dB)

0.6

0.4

0.2

0.0

–0.2

–0.4

–0.6 0 4999.8375 9999.675 14999.5125 19999.35

PCM1744

FIGURE 1. I2S Data Input Timing.

FIGURE 2. Audio Data Input Timing.

SYSTEM CLOCK

The system clock for PCM1744 must be either 256fS or

384fS, where fS is the audio sampling frequency (LRCIN),

typically 32kHz, 44.1kHz, 48kHz, 88.2kHz or 96kHz. The

system clock is used to operate the digital filter and the noise

shaper. The system clock input (SCKI) is at pin 14. Timing

conditions for SCKI are shown in Figure 3.

PCM1744 has a system clock detection circuit which auto-

matically detects the frequency, either 256fS or 384fS. The

system clock should be synchronized with LRCIN (pin 1),

but PCM1744 can compensate for phase differences. If the

phase difference between LRCIN and system clock is greater

System Clock Pulse Width High tSCKIH 13ns (min)

System Clock Pulse Width Low tSCKIL 13ns (min)

FIGURE 3. System Clock Timing Requirements.

LRCKIN

BCKIN

DIN

1.4V

BCH

BCL

BCKIN Pulse Cycle Time

BCKIN Pulse Width High

BCKIN Pulse Width Low

BCKIN Rising Edge to LRCIN Edge

LRCIN Edge to BCKIN Rising Edge

DIN Set-up Time

DIN Hold Time

: t

BCY

: t

BCH

: t

BCL

: t

: 100ns (min)

: 50ns (min)

: 30ns (min)

BCY

tSCKIH

SCKI

tSCKIL

2.0V

0.8V

123 20 21

1/f

L_ch R_ch

MSB LSB

22 23 24 2120 22 23 24

LRCIN (pin 1)

BCKIN (pin 3)

AUDIO DATA WORD = 24-BIT

DIN (pin 2) 123

MSB LSB

7PCM1744

than ±6 bit clocks (BCKIN), the synchronization is per-

formed automatically. The analog outputs are forced to a

bipolar zero state (VCC/2) during the synchronization func-

tion. Table I shows the typical system clock frequency

inputs for the PCM1744.

SYSTEM CLOCK

FREQUENCY (MHz)

256fS384fS

32kHz 8.192 12.288

44.1kHz 11.2896 16.9340

48kHz 12.288 18.432

88.2kHz 22.5792 33.868

96kHz 24.576 36.864

SAMPLING

RATE (LRCIN)

TABLE I. System Clock Frequencies vs Sampling Rate.

TYPICAL CONNECTION DIAGRAM

Figure 4 illustrates the typical connection diagram for

PCM1744 used in a stand-alone application.

INPUT DATA FORMAT

PCM1744 can accept input data a 24-bit I2S format, as

shown in Figure 1.

FIGURE 5. Internal Power-On Reset Timing.

FIGURE 4. Typical Connection Diagram.

RESET

PCM1744 has an internal power-on reset circuit. The internal

power-on reset initializes (resets) when the supply voltage

VCC > 2.2V (typ). The power-on reset has an initialization

period equal to 1024 system clock periods after VCC > 2.2V.

During the initialization period, the outputs of the DAC are

invalid, and the analog outputs are forced to VCC/2. Figure 5

illustrates the power-on reset and reset-pin reset timing.

DE-EMPHASIS CONTROL

Pin 12 (DM) enables PCM1744’s de-emphasis function. De-

emphasis operates only at 44.1kHz.

0 De-emphasis OFF

1 De-emphasis ON (44.1kHz)

TABLE II. De-emphasis Control Selection.

1024 system (= SCKI) clocks

Reset Reset Removal

2.6V

2.2V

1.8V

Internal Reset

SCKI Clock

DIN

BCKIN

LRCIN

TEST

SCKI

PCM

Audio Data

Processor

256f

384f

System Clock

GND

De-Emphasis Control

Lch Analog Out

+5V Analog

Rch Analog Out

OUT

CAP

PCM1744

+10µF

Post

LPF

Post

LPF

10µF

PCM1744

APPLICATION

CONSIDERATIONS

DELAY TIME

There is a finite delay time in delta-sigma converters. In A/D

converters, this is commonly referred to as latency. For a

delta-sigma D/A converter, delay time is determined by the

order number of the FIR filter stage, and the chosen sampling

rate. The following equation expresses the delay time of

PCM1744:

TD = 11.125 x 1/fS

For fS = 44.1kHz, TD = 11.125/44.1kHz = 251.4µs

Applications using data from a disc or tape source, such as

CD audio, CD-Interactive, Video CD, DAT, Minidisc,

etc., generally are not affected by delay time. For some

professional applications such as broadcast audio for stu-

dios, it is important for total delay time to be less than 2ms.

OUTPUT FILTERING

For testing purposes all dynamic tests are done on the

PCM1744 using a 20kHz low-pass filter. This filter limits

the measured bandwidth for THD+N, etc. to 20kHz. Failure

to use such a filter will result in higher THD+N and lower

SNR and dynamic range readings than are found in the

specifications. The low-pass filter removes out-of-band noise.

Although it is not audible, it may affect dynamic specifica-

tion numbers.

The performance of the internal low pass filter from DC to

24kHz is shown in Figure 6. The higher frequency roll-off of

the filter is shown in Figure 7. If the user’s application has

the PCM1744 driving a wideband amplifier, it is recom-

mended to use an external low-pass filter. A simple 3rd-

order filter is shown in Figure 8. For some applications, a

passive RC filter or 2nd-order filter may be adequate.

BYPASSING POWER SUPPLIES

The power supplies should be bypassed as close as possible

to the unit. It is also recommended to include a 0.1µF ceramic

capacitor in parallel with the 10µF tantalum bypass capacitor.

FIGURE 6. Low-Pass Filter Frequency Response.

FIGURE 7. Low-Pass Filter Wideband Frequency Response.

FIGURE 8. 3rd-Order LPF.

1.0

0.5

–0.5

–1.0

20 Frequency (Hz)

100 1k 10k 24k

INTERNAL ANALOG FILTER FREQUENCY RESPONSE

(20Hz~24kHz, Expanded Scale)

–5

–10

–15

–20

–25

–30

–35

–40

–45

–50

–55

10 100 1k 10k 100k 1M 10M

Frequency (Hz)

–60

INTERNAL ANALOG FILTER FREQUENCY RESPONSE

(10Hz~10MHz)

10kΩ

1500pF

100pF

680pF

SIN

–

–90

–180

–270

–360

100 1k 10k 100k 1M

GAIN vs FREQUENCY

Frequency (Hz)

Phase (°)

–14

–34

–54

–74

–94

Gain (dB)

Gain

Phase

OPA134

9PCM1744

FIGURE 9. 5-Level ∆Σ Modulator Block Diagram.

FIGURE 10. Quantization Noise Spectrum.

THEORY OF OPERATION

The delta-sigma section of PCM1744 is based on a 5-level

amplitude quantizer and a 3rd-order noise shaper. This

section converts the oversampled input data to 5-level delta-

sigma format. A block diagram of the 5-level delta-sigma

modulator is shown in Figure 9. This 5-level delta-sigma

modulator has the advantage of stability and clock jitter over

the typical one-bit (2-level) delta-sigma modulator.

The combined oversampling rate of the delta-sigma modu-

lator and the internal 8x interpolation filter is 96fS for a

384fS system clock, and 64fS for a 256fS system clock. The

theoretical quantization noise performance of the 5-level

delta-sigma modulator is shown in Figure 10.

5-LEVEL DELTA SIGMA MODULATOR

Frequency (kHz)

Gain (–dB)

–20

–40

–60

–80

–100

–120

–140

–160 0 5 10 15 20 25

Out

48f

(384f

)

64f

(256f

)

In 8f

24-Bit

+++

5-level Quantizer

–

–1

–

–1

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

Customers are responsible for their applications using TI components.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.