1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
SCLK
FS
SDI
EOC/INT
SDO
DGND
DVDD
CS
A0
A1
A2
A3
CSTART
AVDD
AGND
COMP
REFM
REFP
AGND
AVDD
A7
A6
A5
A4
TLC3578, TLC2578
DW OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SCLK
FS
SDI
EOC/INT
SDO
DGND
DVDD
CS
A0
A1
CSTART
AVDD
AGND
COMP
REFM
REFP
AGND
AVDD
A3
A2
TLC3574, TLC2574
DW, N, OR PW PACKAGE
(TOP VIEW)
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SLAS262C − O C TOBER 2000 − REVISED MAY 2003
1
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D14-Bit Resolution for TLC3574/78, 12-Bit for
TLC2574/2578
DMaximum Throughput 200-KSPS
DMultiple Analog Inputs:
− 8 Single-Ended Channels for
TLC3578/2578
− 4 Single-Ended Channels for
TLC3574/2574
DAnalog Input Range: ±10 V
DPseudodifferential Analog Inputs
DSPI/DSP-Compatible Serial Interfaces With
SCLK up to 25-MHz
DBuilt-In Conversion Clock and 8x FIFO
DSingle 5-V Analog Supply; 3-/5-V Digital
Supply
DLow-Power
− 5.8 mA in Normal Operation
− 20 µA in Power Down
DProgrammable Autochannel Sweep and
Repeat
DHardware-Controlled, Programmable
Sampling Period
DHardware Default Configuration
DINL: TLC3574/78: ±1 LSB;
TLC2574/78: ±0.5 LSB
DDNL: TLC3574/78: ±0.5 LSB;
TLC2574/78: ±0.5 LSB
DSINAD: TLC3574/78: 79 dB;
TLC2574/78: 72 dB
DTHD: TLC3574/78: −82 dB;
TLC2574/78: −82 dB
description
The TLC3574, TLC3578, TLC2574, and TLC2578 are a family of high-performance, low-power, CMOS
analog-to-digital converters (ADC). TLC3574/78 is a 14-bit ADC; TLC2574/78 is a 12-bit ADC. All parts operate
from single 5-V analog power supply and 3-V to 5-V digital supply. The serial interface consists of four digital
input [chip select (CS), frame sync (FS), serial input-output clock (SCLK), serial data input (SDI)], and a 3-state
serial data output (SDO). CS (works as SS, slave select), SDI, SDO and SCLK form an SPI interface. FS, SDI,
SDO, and SCLK form DSP interface. The frame sync signal (FS) indicates the start of a serial data frame being
transferred. When multiple converters connect to one serial port of a DSP, CS works as the chip select to allow
the host DSP to access the individual converter. CS can be tied to ground if only one converter is used. FS must
be tied to DVDD if it is not used (such as in an SPI interface). When SDI is tied to DVDD, the device is set in
hardware default mode after power on and no software configuration is required. In the simplest case, only three
wires (SDO, SCLK, and CS or FS) are needed to interface with the host.
Copyright 2000 − 2003, Texas Instruments Incorporated
!"#$%&'#! ( )*$$+!' &( #" ,*-.)&'#! /&'+0
$#/*)'( )#!"#$% '# (,+)")&'#!( ,+$ '1+ '+$%( #" +2&( !('$*%+!'(
('&!/&$/ 3&$$&!'40 $#/*)'#! ,$#)+((!5 /#+( !#' !+)+((&$.4 !).*/+
'+('!5 #" &.. ,&$&%+'+$(0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
±
SLAS262C − O C TOBER 2000 − REVISED MAY 2003
2WWW.TI.COM
description (continued)
In addition to being a high-speed ADC with versatile control capability, these devices have an on-chip analog
multiplexer (MUX) that can select any analog input or one of three self-test voltages. The sample-and-hold
function is automatically started after the fourth SCLK (normal sampling) or can be controlled by a special pin,
CSTART, to extend the sampling period (extended sampling). The normal sampling period can also be
programmed as short sampling (12 SCLKs) or long sampling (44 SCLKs) to accommodate the faster SCLK
operation popular among high-performance signal processors. The TLC3574/78 and TLC2574/78 are
designed to operate with low-power consumption. The power saving feature is further enhanced with
autopower-down mode and programmable conversion speeds. The conversion clock (internal OSC) is built in.
The converter can also use an external SCLK as the conversion clock for maximum flexibility. The TLC3574/78
and TLC2574/78 are specified with bipolar input and a full scale range of ±10 V.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA20-TSSOP
(PW) 20-SOIC
(DW) 20-PDIP
(N) 24-SOIC
(DW) 24-TSSOP
(PW)
−40°C to 85°C
TLC2574IPW TLC2574IDW TLC2574IN TLC2578IDW TLC2578IPW
−40°C to 85°CTLC3574IPW TLC3574IDW TLC3574IN TLC3578IDW TLC3578IPW
functional block diagram
Analog
MUX
Signal
Scaling
Command
Decode
CMR (4 MSBs)
SAR
ADC
OSC
Conversion
Clock
FIFO
X8
Control
Logic
4-Bit
Counter
SDO
EOC/INT
DVDD AVDD
DGND AGND
CSTART
FS
CS
SCLK
SDI CFR
REFM
COMP
REFP
X8†
A0
A1
A2
A3
A4
A5
A6
A7
X4‡
A0
A1
A2
A3
X
X
X
X
†TLC3578, TLC2578
‡TLC3574, TLC2574
NOTE: 4-Bit counter counts the CLOCK, SCLK. The CLOCK is gated in by CS falling edge if CS initiates the conversion operation cycle, or gated
in by the rising edge of FS if FS initiates the operation cycle. SCLK is disabled for serial interface when CS is high.
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SLAS262C − O C TOBER 2000 − REVISED MAY 2003
3
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equivalent input circuit
Equivalent Digital Input Circuit
Digital Input
VDD
3.94 kΩ
6.6 kΩ
9.9 kΩ
Bipolar Signal Scaling
1.5 kΩ
Ron
MUX
C(sample)= 30 pF
REFP
REFM
Ain
Diode Turn on Voltage: 35 V
Equivalent Analog Input Circuit
Terminal Functions
TERMINAL
NO.
I/O
DESCRIPTION
NAME TLC3574
TLC2574 TLC3578
TLC2578
I/O
DESCRIPTION
A0
A1
A2
A3
A0
A1
A2
A3
A4
A5
A6
A7
9
10
11
12
9
10
11
12
13
14
15
16
I Analog signal inputs. Analog input signals applied to these terminals are internally multiplexed. The
driving source impedance should be less than or equal to 25 Ω for normal sampling. For larger
source impedance, use the external hardware conversion start signal CSTART (the low time of
CSTART controls the sampling period) or reduce the frequency of SCLK to increase the sampling
time.
AGND 14, 18 18, 22 IAnalog ground return for the internal circuitry. Unless otherwise noted, all analog voltage
measurements are with respect to AGND.
AVDD 13, 19 17, 23 IAnalog supply voltage
COMP 17 21 I Internal compensation pin. Install compensation capacitors 0.1 µF between this pin and AGND.
CS 8 8 I Chip select. When CS is high, SDO is in high-impedance state, SDI is ignored, and SCLK is
disabled to clock data, but works as conversion clock source if programmed. The falling edge of
CS input resets the internal 4-bit counter, enables SDI and SCLK, and removes SDO from
high-impedance state.
If FS is high at CS falling edge, CS falling edge initiates the operation cycle. CS works as slave
select (SS) to provide an SPI interface.
If FS is low at CS falling edge, FS rising edge initiates the operation cycle. CS can be used as chip
select to allow host to access the individual converter.
CSTART 20 24 I External sampling trigger signal, which initiates the sampling from a selected analog input channel
when the device works in extended sampling mode (asynchronous sampling). A high-to-low
transition starts the sampling of the analog input signal. A low-to-high transition puts the S/H in hold
mode and starts the conversion. The low time of the CSTART signal controls the sampling period.
CSTART signal must stay low long enough for proper sampling. CSTART must stay high long
enough after the low-to-high transition for the conversion to finish maturely. The activation of
CSTART is independent of SCLK and the level of CS and FS. However, the first CSTART cannot
be issued before the rising edge of the eleventh SCLK. Tie this pin to DVDD if not used.
DGND 6 6 I Digital ground return for the internal circuitry
DVDD 7 7 I Digital supply voltage
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SLAS262C − O C TOBER 2000 − REVISED MAY 2003
4WWW.TI.COM
Terminal Functions (Continued)
TERMINAL
NO.
I/O
DESCRIPTION
NAME TLC3574
TLC2574 TLC3578
TLC2578
I/O
DESCRIPTION
EOC(INT) 4 4 O End of conversion (EOC) or interrupt to host processor (INT)
EOC: used in conversion mode 00 only. EOC goes from high to low at the end of the sampling and
remains low until the conversion is complete and data is ready.
INT: Interrupt to the host processor. The falling edge of INT indicates data is ready for output. INT
is cleared by the following CS↓, FS↑, or CSTART↓.
FS 2 2 I Frame sync input from DSP. The rising edge of FS indicates the start of a serial data frame being
transferred (coming into or being sent out of the device). If FS is low at the falling edge of CS, the
rising edge of FS initiates the operation cycle, resets the internal 4-bit counter, and enables SDI,
SDO, and SCLK. Tie this pin to DVDD if FS is not used to initiate the operation cycle.
REFM 16 20 I External low reference input. Connect REFM to AGND.
REFP 15 19 I External positive reference input. The range of maximum input voltage is determined by the
difference between the voltage applied to this terminal and to the REFM terminal. Always install
decoupling capacitors (10 µF in parallel with 0.1 µF) between REFP and REFM.
SCLK 1 1 I Serial clock input from the host processor to clock in the input from SDI and clock out the output
via SDO. It can also be used as the conversion clock source when the external conversion clock
is selected (see Table 2). When CS is low , SCLK is enabled. When CS is high, SCLK is disabled
for the data transfer, but can still work as the conversion clock source.
SDI 3 3 I Serial data input. The first 4 MSBs, ID[15:12], are decoded as one 4-bit command. All trailing bits,
except for the WRITE CFR command, are filled with zeros. The WRITE CFR command requires
additional 12-bit data. The MSB of input data, ID(15), is latched at the first falling edge of SCLK
following FS falling edge if FS starts the operation, or latched at the falling edge of first SCLK
following CS falling edge when CS initiates the operation.
The remaining input data (if any) is shifted in on the rising edge of SCLK and latched on the falling
edge of SCLK. The input via SDI is ignored after the 4-bit counter counts to 16 (clock edges) or a
low-to-high transition of CS, whichever happens first. Refer to the timing specification for the timing
requirements. Tie SDI to DVDD if using hardware default mode (refer to Device Initialization).
SDO 5 5 O The 3-state serial output for the A/D conversion result. All data bits are shifted out through SDO.
SDO is in the high-impedance state when CS is high. SDO is released after a CS falling edge. The
output format is MSB (OD15) first.
When FS initiates the operation, the MSB of output via SDO, OD(15), is valid before the first falling
edge of SCLK following the falling edge of FS.
When CS initiates the operation, the MSB, OD(15), is valid before the first falling edge of SCLK
following the CS falling edge.
The remaining data bits (if any) are shifted out on the rising edge of SCLK and are valid before the
falling edge of SCLK. Refer to the timing specification for the details.
In select/conversion operation, the first 14 bits (for TLC3574/78) or the first 12 bits (for TLC2574/78)
are the results from the previous conversion (data). In a READ FIFO operation, this data is from
FIFO. In both cases, the last two bits (for TLC3574/78) or the last four bits (for TLC2574/78) are
don’t care.
In a WRITE operation, the output from SDO must be ignored.
SDO goes into high-impedance state at the 16th falling edge of SCLK after the operation cycle is
initiated. SDO is in high-impedance state during conversions in modes 01, 10, and 11.
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absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, GND to AVDD and DVDD −0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog input voltage range −17 V to 17 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog input current 100 mA MAX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference input voltage AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range −0.3 V to DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ −40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1.16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under electrical characteristics and timing
characteristics is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
general electrical characteristics over recommended operating free-air temperature range,
single-ended input, normal long sampling, 200 KSPS, AVDD = 5 V, VREFP = 4 V, VREFM = 0 V,
SCLK frequency = 25 MHz, fixed channel at CONV mode 00, analog input signal source resistance
= 25 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
Digital Input
VIH
High-level digital input voltage
DVDD = 5 V 3.8
V
V
IH
High-level digital input voltage
DVDD = 3 V 2.1
V
VIL
Low-level digital input voltage
DVDD = 5 V 0.8
V
V
IL
Low-level digital input voltage
DVDD = 3 V 0.6
V
IIH High-level digital input current VI = DVDD 0.005 2.5 µA
IIL Low-level digital input current VI = DGND −2.5 −0.005 µA
Input capacitance 20 25 pF
Digital Output
VOH
High-level digital output at 30 pF load
Io = −0.2 mA
DVDD = 5 V 4.2
V
V
OH
High-level digital output at 30 pF load
I
o
= −0.2 mA
DVDD = 3 V 2.4
V
DVDD = 5 V
Io = 0.8 mA 0.4
VOL
Low-level digital output at 30 pF load
DV
DD
= 5 V
Io = 50 µA 0.1
V
V
OL
Low-level digital output at 30 pF load
DVDD = 3 V
Io = 0.8 mA 0.4
V
DV
DD
= 3 V
Io = 50 µA 0.1
IOZ
Off-state output current
VO = DVDD
CS = DVDD
0.02 1
µA
I
OZ
Off-state output current
(high-impedance state) VO = DGND
CS = DV
DD −1 0.02 µ
A
Power Supply
AVDD
Supply voltage
4.75 5 5.5 V
DVDD
Supply voltage
2.7 5 5.5 V
ICC
Power supply cur-
AVDD current
AlCC Conversion clock is internal OSC,
AVDD = 5.5 V − 4.5 V, CS = DGND,
4.2 5
mA
I
CC
Power supply cur-
rent DVDD current
DlCC
AV
DD
= 5.5 V − 4.5 V, CS = DGND,
Excluding bipolar input biasing current 1.6 2.0
mA
ICC
(autopwrdn): Autopower-down power supply
For all digital inputs = DVDD or DGND
,
AVDD = 5.5 V, Excluding bipolar input
SCLK OFF 20
µA
CC
(autopwrdn): Autopower-down
power
supply
current
DD
AV
DD
= 5.5 V, Excluding bipolar input
biasing current, external reference SCLK ON 175 230 µ
A
Operating temperature −40 85 °C
†All typical values are at TA = 25°C.
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SLAS262C − O C TOBER 2000 − REVISED MAY 2003
6WWW.TI.COM
general electrical characteristics over recommended operating free-air temperature range, single-
ended input, normal long sampling, 200 KSPS, AVDD = 5 V, VREFP = 4 V, VREFM = 0 V,
SCLK frequency = 25 MHz, fixed channel at CONV mode 00, analog input signal source
resistance = 25 Ω (unless otherwise noted)
TLC3574/78 and TLC2574/78
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
Resolution 14 bits
Analog Input
Voltage range −10 10 V
Selected analog input channel bias current
Selected channel at 10 V 0.8 1.6
mA
Selected analog input channel bias current Selected channel at –10 V −1.6 −1.2 mA
Impedance 10 kΩ
Capacitance 30 pF
Reference
VREFP Positive reference voltage 3.96 4 4.04 V
VREFM Negative reference voltage 0 AGND V
Input impedance
No conversion (AVDD = 5V, CS= DVDD,
SCLK=DGND) 100 MΩ
Input impedance Normal long sampling (AVDD = 5V, CS=DGND,
SCLK = 25 MHz, External conversion clock) 8.3 12.5 kΩ
No conversion (AVDD = 5 V,
SCLK = DGND, CS = DVDD)1.5 µA
Reference current Normal long sampling (AVDD = 5 V, CS = DGND,
External conversion clock, SCLK = 25 MHz,
VREF = 5 V) 0.4 0.6 mA
Internal oscillation frequency DVDD = 2.7 V – 5.5 V 6.5 MHz
Internal OSC, 6.5 MHz minimum
TLC3574/78 2.785
t(conv)
Conversion time
Internal OSC, 6.5 MHz minimum TLC2574/78 2.015
S
t(conv) Conversion time
Conversion clock is external source,
TLC3574/78 2.895 µS
Conversion clock is external source,
SCLK = 25 MHz (see Note 1) TLC2574/78 2.095
Acquisition time Normal short sampling 1.2 µS
Throughput rate (see Note 2) Normal long sampling, fixed channel
in mode 00 or 01 200 KSPS
†All typical values are at TA = 25°C.
NOTES: 1. Conversion time t(conv) is (18 ×4× SCLK) + 15 ns for TLC3574/78. Conversion time is (13 ×4 × SCLK) + 15 ns for TLC2574/78.
2. This is for a fixed channel in conversion mode 00 or 01. When switching the channels, additional multiplexer setting time is required
to overcome the memory effect of the charge redistribution DAC.
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AC/DC performance over recommended operating free-air temperature range, single-ended input,
normal long sampling, 200 KSPS, AVDD = 5 V, VREFP = 4 V, VREFM = 0 V, SCLK frequency = 25 MHz,
fixed channel at CONV mode 00, analog input signal source resistance = 25 Ω (unless otherwise
noted)
TLC3574/78 DW and PW package device AC/DC performance
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
DC Accuracy—Normal Long Sampling
ELIntegral linearity error See Note 3 −1.5 ±1 1.5 LSB
EDDifferential linearity error −1 ±0.5 1 LSB
EOBipolar zero error See Note 4 −0.30 ±0.08 0.36 %FS
EFS(+) Positive full scale error See Note 4 −0.55 ±0.04 0.61 %FS
EFS(−) Negative full scale error See Note 4 −0.30 ±0.13 0.79 %FS
DC Accuracy—Normal Short Sampling
ELIntegral linearity error See Note 3 ±1 LSB
EDDifferential linearity error ±0.5 LSB
EOBipolar zero error See Note 4 ±0.08 %FS
EFS(+) Positive full scale error See Note 4 ±0.04 %FS
EFS(−) Negative full scale error See Note 4 ±0.13 %FS
AC Accuracy (see Note 3)—Normal Long Sampling
SINAD
Signal-to-noise ratio + distortion
fi = 20 kHz 76 79
dB
SINAD
Signal-to-noise ratio + distortion
fi = 100 kHz 75
dB
THD
Total harmonic distortion
fi = 20 kHz −82 −77
dB
THD
Total harmonic distortion
fi = 100 kHz −78
dB
SNR
Signal-to-noise ratio
fi = 20 kHz 78 80
dB
SNR
Signal-to-noise ratio
fi = 100 kHz 78
dB
ENOB
Effective number of bits
fi = 20 kHz 12.3 12.8
Bits
ENOB
Effective number of bits
fi = 100 kHz 12.2
Bits
SFDR
Spurious free dynamic range
fi = 20 kHz 78 84
dB
SFDR
Spurious free dynamic range
fi = 100 kHz 79
dB
Channel-to-channel isolation Fixed channel in conversion mode 00, fi = 35 kHz,
See Notes 2 and 5 81 dB
Analog input bandwidth
Full power bandwidth, −3 dB 1 MHz
Analog input bandwidth Full power bandwidth, −1 dB 700 kHz
†All typical values are at TA = 25°C.
NOTES: 2. This is for a fixed channel in conversion mode 00 or 01. When switching the channels, additional multiplexer setting time is required
to overcome the memory effect of the charge redistribution DAC.
3. Linear error is the maximum deviation from the best fit straight line through the A/D transfer characteristics.
4. Bipolar zero error is the difference between 10000000000000 and the converted output for zero input voltage; positive full-scale error
is the difference between 11111111111111 and the converted output for positive full-scale input voltage (10 V); negative full-scale
error is the difference between 00000000000000 and the converted output for negative full-scale input voltage (−10 V).
5. It is measured by applying a full-scale of 35 kHz signal to other channels and determining how much the signal is attenuated in the
channel of interest. The converter samples this examined channel continuously. The channel-to-channel isolation is degraded if t h e
converter samples different channels alternately.
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TLC3574/78 DW and PW package device AC/DC performance (continued)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
AC Accuracy—Normal Short Sampling
SINAD
Signal-to-noise ratio + distortion
fi = 20 kHz 79
dB
SINAD
Signal-to-noise ratio + distortion
fi = 100 kHz 75
dB
THD
Total harmonic distortion
fi = 20 kHz −82
dB
THD
Total harmonic distortion
fi = 100 kHz −78
dB
SNR
Signal-to-noise ratio
fi = 20 kHz 80
dB
SNR
Signal-to-noise ratio
fi = 100 kHz 78
dB
ENOB
Effective number of bits
fi = 20 kHz 12.8
Bits
ENOB
Effective number of bits
fi = 100 kHz 12.2
Bits
SFDR
Spurious free dynamic range
fi = 20 kHz 84
dB
SFDR
Spurious free dynamic range
fi = 100 kHz 79
dB
Channel-to-channel isolation Fixed channel in conversion mode 00, fi= 35 kHz,
See Notes 2 and 5 81 dB
Analog input bandwidth
Full power bandwidth, −3 dB 1 MHz
Analog input bandwidth Full power bandwidth, −1 dB 700 kHz
†All typical values are at TA = 25°C.
NOTES: 2. This is for a fixed channel in conversion mode 00 or 01. When switching the channels, additional multiplexer setting time is required
to overcome the memory effect of the charge redistribution DAC.
5. It is measured by applying a full-scale of 35 kHz signal to other channels and determining how much the signal is attenuated in the
channel of interest. The converter samples this examined channel continuously. The channel-to-channel isolation is degraded if t h e
converter samples different channels alternately.
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TLC3574I N package device AC/DC performance
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
DC Accuracy—Normal Long Sampling
ELIntegral linearity error See Note 3 −1.5 ±1 1.5 LSB
EDDifferential linearity error −1 ±0.8 1.5 LSB
EOBipolar zero error See Note 4 −0.30 ±0.08 0.36 %FS
EFS(+) Positive full scale error See Note 4 −0.55 ±0.04 0.61 %FS
EFS(−) Negative full scale error See Note 4 −0.30 ±0.13 0.79 %FS
DC Accuracy—Normal Short Sampling
ELIntegral linearity error See Note 3 ±1.8 LSB
EDDifferential linearity error ±0.8 LSB
EOBipolar zero error See Note 4 ±0.08 %FS
EFS(+) Positive full-scale error See Note 4 ±0.04 %FS
EFS(−) Negative full-scale error See Note 4 ±0.13 %FS
AC Accuracy (see Note 3)—Normal Long Sampling
SINAD
Signal-to-noise ratio + distortion
fi = 20 kHz 75 78
dB
SINAD
Signal-to-noise ratio + distortion
fi = 100 kHz 75
dB
THD
Total harmonic distortion
fi = 20 kHz −82 −77
dB
THD
Total harmonic distortion
fi = 100 kHz −75
dB
SNR
Signal-to-noise ratio
fi = 20 kHz 78 80
dB
SNR
Signal-to-noise ratio
fi = 100 kHz 76
dB
ENOB
Effective number of bits
fi = 20 kHz 12.2 12.7
Bits
ENOB
Effective number of bits
fi = 100 kHz 12.2
Bits
SFDR
Spurious free dynamic range
fi = 20 kHz 78 83
dB
SFDR
Spurious free dynamic range
fi = 100 kHz 75
dB
Channel-to-channel isolation Fixed channel in conversion mode 00, fi = 35 kHz,
See Notes 2 and 5 81 dB
Analog input bandwidth
Full power bandwidth, −3 dB 1 MHz
Analog input bandwidth Full power bandwidth, −1 dB 700 kHz
†All typical values are at TA = 25°C.
NOTES: 2. This is for a fixed channel in conversion mode 00 or 01. When switching the channels, additional multiplexer setting time is required
to overcome the memory effect of the charge redistribution DAC.
3. Linear error is the maximum deviation from the best fit straight line through the A/D transfer characteristics.
4. Bipolar zero error is the difference between 10000000000000 and the converted output for zero input voltage; positive full-scale error
is the difference between 11111111111111 and the converted output for positive full-scale input voltage (10 V); negative full-scale
error is the difference between 00000000000000 and the converted output for negative full-scale input voltage (−10 V).
5. It is measured by applying a full-scale of 35 kHz signal to other channels and determining how much the signal is attenuated in the
channel of interest. The converter samples this examined channel continuously. The channel-to-channel isolation is degraded if t h e
converter samples different channels alternately.
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TLC3574I N package device AC/DC performance (continued)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
AC Accuracy—Normal Short Sampling
SINAD
Signal-to-noise ratio + distortion
fi = 20 kHz 76
dB
SINAD
Signal-to-noise ratio + distortion
fi = 100 kHz 70
dB
THD
Total harmonic distortion
fi = 20 kHz −81
dB
THD
Total harmonic distortion
fi = 100 kHz −74
dB
SNR
Signal-to-noise ratio
fi = 20 kHz 78
dB
SNR
Signal-to-noise ratio
fi = 100 kHz 75
dB
ENOB
Effective number of bits
fi = 20 kHz 12.3
Bits
ENOB
Effective number of bits
fi = 100 kHz 11.3
Bits
SFDR
Spurious free dynamic range
fi = 20 kHz 83
dB
SFDR
Spurious free dynamic range
fi = 100 kHz 75
dB
Channel-to-channel isolation Fixed channel in conversion mode 00, fi= 35 kHz,
See Notes 2 and 5 81 dB
Analog input bandwidth
Full power bandwidth, −3 dB 1 MHz
Analog input bandwidth Full power bandwidth, −1 dB 700 kHz
†All typical values are at TA = 25°C.
NOTES: 2. This is for a fixed channel in conversion mode 00 or 01. When switching the channels, additional multiplexer setting time is required
to overcome the memory effect of the charge redistribution DAC.
5. It is measured by applying a full-scale of 35 kHz signal to other channels and determining how much the signal is attenuated in the
channel of interest. The converter samples this examined channel continuously. The channel-to-channel isolation is degraded if t h e
converter samples different channels alternately.
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TLC2574/78 DW and PW package devices AC/DC performance
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
DC Accuracy
ELIntegral linearity error See Note 6 −1 ±0.5 1 LSB
EDDifferential linearity error −1 ±0.5 1 LSB
EOBipolar zero error See Note 7 −0.30 ±0.08 0.36 %FS
EFS(+) Positive full scale error See Note 7 −0.55 ±0.04 0.61 %FS
EFS(−) Negative full scale error See Note 7 −0.30 ±0.13 0.79 %FS
AC Accuracy
SINAD
Signal-to-noise ratio + distortion
fi = 20 kHz 70 72
dB
SINAD Signal-to-noise ratio + distortion fi = 100 kHz 70 dB
THD
Total harmonic distortion
fi = 20 kHz −82 −76
dB
THD Total harmonic distortion fi = 100 kHz −80 dB
SNR
Signal-to-noise ratio
fi= 20 kHz 71 72
dB
SNR Signal-to-noise ratio fi = 100 kHz 71 dB
ENOB
Effective number of bits
fi = 20 kHz 11.3 11.7
Bits
ENOB Effective number of bits fi = 100 kHz 11.3 Bits
SFDR
Spurious free dynamic range
fi = 20 kHz 78 83
dB
SFDR Spurious free dynamic range fi = 100 kHz 80 dB
Analog input bandwidth
Full power bandwidth, −3 dB 1 MHz
Analog input bandwidth Full power bandwidth, −1 dB 700 kHz
Channel-to-channel Isolation Fixed channel in conversion mode 00, fi = 35 kHz,
See Note 8 81 dB
†All typical values are at TA = 25°C.
NOTES: 6. Linear error is the maximum deviation from the best fit straight line through the A/D transfer characteristics.
7. Bipolar zero error is the difference between 100000000000 and the converted output for zero input voltage; positive full-scale error
is the difference between 111111111111 and the converted output for positive full-scale input voltage (10 V); negative full-scale error
is the difference between 000000000000 and the converted output for negative full-scale input voltage (−10 V).
8. It is measured by applying a full-scale of 35 kHz signal to other channels and determining how much the signal is attenuated in the
channel of interest. The converter samples this examined channel continuously. The channel-to-channel isolation is degraded if t h e
converter samples different channels alternately.
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TLC2574I N package device AC/DC performance
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
DC Accuracy
ELIntegral linearity error see Note 6 −1 ±0.7 1 LSB
EDDifferential linearity error −1 ±0.7 1 LSB
EOBipolar zero error see Note 7 −0.30 ±0.08 0.36 %FS
EFS(+) Positive full-scale error see Note 7 −0.55 ±0.04 0.61 %FS
EFS(−) Negative full-scale error see Note 7 −0.30 ±0.13 0.79 %FS
AC Accuracy
SINAD
Signal-to-noise + distortion
fi = 20 kHz 70 72
dB
SINAD Signal-to-noise + distortion fi = 100 kHz 70 dB
THD
Total harmonic distortion
fi = 20 kHz −82 −76
dB
THD Total harmonic distortion fi = 100 kHz −75 dB
SNR
Signal-to-noise ratio
fi= 20 kHz 70 72
dB
SNR Signal-to-noise ratio fi = 100 kHz 71 dB
ENOB
Effective number of bits
fi = 20 kHz 11.3 11.7
Bits
ENOB Effective number of bits fi = 100 kHz 11.3 Bits
SFDR
Spurious free dynamic range
fi = 20 kHz 77 83
dB
SFDR Spurious free dynamic range fi = 100 kHz 75 dB
Analog input bandwidth
Full power bandwidth, −3 dB 1 MHz
Analog input bandwidth Full power bandwidth, −1 dB 700 kHz
Channel-to-channel Isolation Fixed channel in conversion mode 00, fi = 35 kHz,
See Note 8 81 dB
†All typical values are at TA = 25°C.
NOTES: 6. Linear error is the maximum deviation from the best fit straight line through the A/D transfer characteristics.
7. Bipolar zero error is the difference between 100000000000 and the converted output for zero input voltage; positive full-scale error
is the difference between 111111111111 and the converted output for positive full-scale input voltage (10 V); negative full-scale error
is the difference between 000000000000 and the converted output for negative full-scale input voltage (−10 V).
8. It is measured by applying a full-scale of 35 kHz signal to other channels and determining how much the signal is attenuated in the
channel of interest. The converter samples this examined channel continuously. The channel-to-channel isolation is degraded if t h e
converter samples different channels alternately.
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timing requirements over recommended operating free-air temperature range, AVDD = 5 V,
DVDD = 5 V, VREFP = 4 V, VREFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted)
SCLK, SDI, SDO, EOC and INT
PARAMETERS MIN TYP MAX UNIT
tc(1)
Cycle time of SCLK, 25 pF load (see Note 10)
DVDD = 2.7 V 100
ns
tc(1) Cycle time of SCLK, 25 pF load (see Note 10) DVDD = 5 V 40 ns
tw(1) Pulse width of SCLK High, at 25-pF load 40% 60% tc(1)
tr(1)
Rise time for INT and EOC, at 10-pF load
DVDD = 5 V 6
ns
tr(1) Rise time for INT and EOC, at 10-pF load DVDD = 2.7 V 10 ns
tf(1)
Fall time for INT and EOC, at 10-pF load
DVDD = 5 V 6
ns
tf(1) Fall time for INT and EOC, at 10-pF load DVDD = 2.7 V 10 ns
tsu(1) Setup time, new SDI valid (reaches 90% final level) before the falling edge of SCLK, at 25-pF load 6 − ns
th(1) Hold time, old SDI hold (reaches 10% of old data level) after falling edge of SCLK, at 25-pF load 0 − ns
td(1)
Delay time, new SDO valid (reaches 90% of final level) after SCLK rising edge, at 10-pF
DVDD = 5 V 0 10
ns
td(1)
Delay time, new SDO valid (reaches 90% of final level) after SCLK rising edge, at 10-pF
load (see Note 11) DVDD = 2.7 V 0 23 ns
th(2) Hold time, old SDO hold (reaches 10% of old data level) after SCLK rising edge, at 10-pF load 0 − ns
td(2) Delay time, delay from the falling edge of 16th SCLK to EOC falling edge, normal sampling, at 10-pF load 0 6 ns
td(3) Delay time, delay from the falling edge of 16th SCLK to INT falling edge, at 10-pF load (see Notes 11 and 12) t(conv) t(conv)+6 ns
NOTES: 9. The minimum pulse width of SCLK high and low is 12.5 ns.
10. Specified by design
11. For normal short sampling, td(3) is the delay from the falling edge of 16th SCLK to the falling edge of INT.
For normal long sampling, td(3) is the delay from the falling edge of 48th SCLK to the falling edge of INT. Conversion time, t(conv),
is equal to 18 × OSC +15 ns (for TLC3574 and TLC3578) or 13 × OSC + 15 ns (for TLC2574 and TLC2578) when using internal
OSC as conversion clock, or 72 × tc(1) + 15 ns (for TLC3574 and TLC3578) or 52 × tc(1) + 15 ns (for TLC2574 and TLC2578) when
external SCLK is conversion clock source.
90%
10%
ID15
OD1 OD0
ID1
Hi-Z
50%
116
OD15
Don’t Care ID0
OR
VIH
VIL
tw(1)
tc(1)
tsu(1) th(1)
th(2)
td(1)
td(2) †tr(1)
tf(1) td(3) ‡
Hi-Z
Don’t Care
tf(1) tr(1)
CS
SCLK
SDI
SDO
EOC
INT
†For normal long sampling, td(2) is the delay time of EOC low after the falling edge of 48th SCLK.
‡For normal long sampling, td(3) is the delay time of INT low after the falling edge of 48th SCLK.
− − − − The dotted line means signal may or may not exist, depending on application. It must be ignored.
Normal sampling mode, CS initiatesthe conversion, FS must be tied to high. When CS is high, SDO is in Hi-Z, all inputs (FS, SCLK,
SDI) are inactive and are ignored.
Figure 1. Critical Timing for SCLK, SDI, SDO, EOC and INT
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timing requirements over recommended operating free-air temperature range, AVDD = 5 V,
DVDD = 5 V, VREFP = 4 V , VREFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted) (continued)
CS trigger
PARAMETERS MIN TYP MAX UNIT
tsu(2) Setup time, CS falling edge before SCLK rising edge, at 25-pF load 12 ns
td(4) Delay time, delay time from the falling edge of 16th SCLK to CS rising edge, at 25 pF load
(see Note 12) 5 ns
tw(2) Pulse width of CS high, at 25-pF load 1 tc(1)
td(5)
Delay time, delay from CS falling edge to MSB of SDO valid (reaches 90%
DVDD = 5 V 0 12
ns
td(5)
Delay time, delay from CS falling edge to MSB of SDO valid (reaches 90%
final level), at 10 pF load DVDD = 2.7 V 0 30†ns
td(6) Delay time, delay from CS rising edge to SDO 3-state, at 10-pF load 0 6 ns
td(7)
Delay time, delay from CS falling edge to INT rising edge, at 10-pF load
DVDD = 5 V 0 6
ns
td(7) Delay time, delay from CS falling edge to INT rising edge, at 10-pF load DVDD = 2.7 V 0 16†ns
†Specified by design
NOTE 12: For normal short sampling, td(4) is the delay time from the falling edge of 16th SCLK to CS rising edge.
For normal long sampling, td(4) is the delay time from the falling edge of 48th SCLK to CS rising edge.
Hi-Z
ID15
OD1 OD0
ID1
116
OD15
Don’t Care ID0
OR
tsu(2) td(4) tw(2)
td(7)
td(5)
Hi-Z Hi-Z
Don’t Care
VIH
VIL
CS
SCLK
SDI
SDO
EOC
INT
td(6)
Don’t Care
OD7OD15
− − − − The dotted line means signal may or may not exist, depending on application. It must be ignored.
Normal sampling mode, CS initiates the conversion, FS must be tied to high. When CS is high, SDO is in Hi-Z, all inputs (FS, SCLK,
SDI) are inactive and are ignored.
Figure 2. Critical Timing for CS Trigger
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timing requirements over recommended operating free-air temperature range, AVDD = 5 V,
DVDD = 5 V, VREFP = 4 V , VREFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted) (continued)
FS trigger
PARAMETERS MIN TYP MAX UNIT
td(8) Delay time, delay from CS falling edge to FS rising edge at 25-pF load 0.5 tc(1)
tsu(3) Setup time, FS rising edge before SCLK falling edge at 25-pF load 0.25×tc(1) 0.5×tc(1)+ 5 ns
tw(3) Pulse width of FS high, at 25-pF load 0.75×tc(1) tc(1) 1.25×tc(1) ns
td(9)
Delay time, delay from FS rising edge to MSB of SDO valid
DVDD = 5 V 26
ns
td(9)
Delay time, delay from FS rising edge to MSB of SDO valid
(reaches 90% final level), at 10-pF load DVDD = 2.7 V 30† ns
td(10) Delay time, delay from FS rising edge to next FS rising edge, at 25-pF load Required
sampling time +
conversion time ns
td(11)
Delay time, delay from FS rising edge to INT rising edge, at
DVDD = 5 V 0 6
ns
td(11)
Delay time, delay from FS rising edge to INT rising edge, at
10-pF load DVDD = 2.7 V 0 16† ns
†Specified by design
ID15
OD1 OD0
ID1
Hi-Z
116
OD15
ID0Don’t Care ID15
OD15
OR
td(10)
tw(3)
td(8)
tsu(3)
td(9)
td(11)
Don’t Care Don’t Care
Don’t Care
Hi-Z
VIH
VIL
VOH
VOH
CS
FS
SCLK
SDI
SDO
EOC
INT
− − − − The dotted line means signal may or may not exist, depending on application. It must be ignored.
Normal sampling mode, FS initiates the conversion, CS can be tied to low. When CS is high, SDO is in Hi-Z, all inputs (FS, SCLK,
SDI) are inactive and are ignored.
Figure 3. Critical Timing for FS Trigger
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timing requirements over recommended operating free-air temperature range, AVDD = 5 V,
DVDD = 5 V, VREFP = 4 V , VREFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted) (continued)
CSTART trigger
PARAMETERS MIN TYP MAX UNIT
td(12) Delay time, delay from CSTART rising edge to EOC falling edge, at 10-pF
load 0 15 21 ns
tw(4) Pulse width of CSTART low, at 25-pF load (see Note 13) t(sample_reg)+0.4 µs
td(13) Delay time, delay from CSTART rising edge to CSTART falling edge, at 25-pF
load (see Note 13 and 14) t(conv)+15 ns
td(14) Delay time, delay from CSTART rising edge to INT falling edge, at 10-pF
load (see Note 13 and 14) t(conv)+15 t(conv)+21 ns
td(15) Delay time, delay from CSTART falling edge to INT rising edge, at 10-pF
load 0 6 ns
NOTES: 13. The pulse width of the CSTART must be not less than the required sampling time.
The delay from CSTART rising edge to following CSTART falling edge must be not less than the required conversion time.
The delay from CSTART rising edge to the INT falling edge is equal to the conversion time.
14. The maximum rate of SCLK is 25 MHz for normal long sampling and 10 MHz for normal short sampling.
t(conv)
OR
tw(4) td(13)
td(12)
td(14)
td(15)
CSTART
EOC
INT
Figure 4. Critical Timing for Extended Sampling (CSTART Trigger)
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circuit description
converter
The converters include a successive-approximation ADC utilizing a charge redistribution DAC. Figure 5 shows
a simplified block diagram of the ADC. The sampling capacitor acquires the signal on Ain during the sampling
period. When the conversion process starts, the control logic directs the charge redistribution DAC to add and
subtract fixed amounts of charge from the sampling capacitor to bring the comparator into a balanced condition.
When balanced, the conversion is complete and the ADC output code is generated.
Charge
Redistribution
DAC
Control
Logic
_
+
REFM
Ain ADC Code
C(sample)
Figure 5. Simplified Block Diagram of the Successive-Approximation System
analog input range and internal test voltages
TLC3578 and TLC2578 have 8 analog inputs (TLC3574 and TLC2574 have 4) and three test voltages. The
inputs are selected by the analog multiplexer according to the command entered (see Table 1). The input
multiplexer is a break-before-make type to reduce input-to-input noise injection resulting from channel
switching.
All converters are specified for bipolar input range of ±10 V. The input signal is scaled to 0–4 V at the SAR ADC
input via the bipolar scaling circuit (see the functional block diagram and the equivalent analog input circuit):
–10 V to 0 V, 10 V to 4 V, and 0 V to 2 V.
analog input mode
Two input signal modes can be selected: single-ended input and pseudodifferential input.
_
+
Charge
Redistribution
DAC
Control
Logic
Ain(+)
REFM
ADC Code
S1
Ain(−)
When sampling, S1 is closed and S2 connects to Ain(−).
During conversion, S1 is open and S2 connects to REFM.
Figure 6. Simplified Pseudodifferential Input Circuit
Pseudodifferential input refers to the negative input, Ain(−). Its voltage is limited in magnitude to ±1 V. The input
frequency limit of Ain(−) is the same as the positive input Ain(+). This mode is normally used for ground noise
rejection or dc offset.
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analog input mode (continued)
When pseudodifferential mode is selected, only two analog input channel pairs are available for the TLC3574
and TLC2574 and four channel pairs for the TLC3578 and TLC2578, because half the inputs are used as the
negative input.
Analog
MUX SAR
ADC
X8†
A0
A1
A2
A3
A4
A5
A6
A7
X4‡
A0
A1
A2
A3
X
X
X
X
X8†
A0(+) Pair A
A1(−)
A2(+) Pair B
A3(−)
A4(+) Pair C
A5(−)
A6(+) Pair D
A7(−)
X4‡
A0(+) Pair A
A1(−)
A2(+) Pair B
A3(−) Analog
MUX SAR
ADC
Single Ended Pseudodifferential
†TLC3578 and TLC2578
‡TLC3574 and TLC2574
Figure 7. Pin Assignment of Single-Ended Input vs Pseudodifferential Input
reference voltage
The external reference is applied to the reference-input pins (REFP and REFM). REFM should connect to
analog ground. REFP is 4 V. Install decoupling capacitors (10 µF in parallel with 0.1 µF) between REFP and
REFM, and compensation capacitors (0.1 µF) between COMP and AGND.
ideal conversion characteristics
00000000000000
00000000000001
00000000000010
01111111111111
10000000000000
10000000000001
11111111111111
11111111111110
11111111111101
16381
16383
16382
8192
8193
8191
0
1
2
01111111111111
01111111111110
01111111111101
00000000000001
00000000000000
11111111111111
10000000000010
10000000000001
10000000000000
Binary
BOB
2s Complement
BTC
VFS− = −10 V
−9.99939 V
−9.99878 V
−9.99756 V
−0.61 mV 9.99756 V
0.61 mV
VBZS = 0.0 V
VFS+ = 10 V
1LSB = 1.22 mV
Bipolar Analog Input Voltage
Step
Digital Output Code
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circuit description (continued)
data format
INPUT DATA FORMAT (BINARY)
MSB LSB
ID[15:12] ID[11:0]
Command Configuration data field or filled with zeros
OUTPUT DATA FORMAT (READ CONVERSION/FIFO)
TLC3574 and TLC3578 TLC2574 and TLC2578
MSB LSB MSB LSB
OD[15:2] OD[1:0] OD[15:4] OD[3:0]
Conversion result Don’t Care Conversion result Don’t Care
14-BIT (TLC3574/78) 12-BIT (TLC2574/78)
Bipolar Input, Offset Binary: (BOB)
Negative full scale code = VFS− = 0000h, Vcode = −10 V
Midscale code = VBZS = 2000h, Vcode = 0 V
Positive full scale code = VFS+ = 3FFFh, Vcode = 10 V − 1 LSB
Bipolar Input, Binary 2s Complement: (BTC)
Negative full scale code = VFS− = 2000 h, Vcode = −10 V
Midscale code = VBZS = 0000h, Vcode = 0 V
Positive full scale code = VFS+ = 1FFFh, Vocde = 10 V − 1 LSB
Bipolar Offset Binary Output: (BOB)
Negative full scale code = 000h, Vcode = −10 V
Midscale code = 800h, Vcode = 0 V
Positive full scale code = FFFh, Vcode = 10 V − 1 LSB
Bipolar Input, Binary 2s Complement: (BTC)
Negative full scale code = 800 h, Vcode = −10 V
Midscale code = 000h, Vcode = 0 V
Positive full scale code = 7FFh, Vocde = 10 V − 1 LSB
operation description
The converter samples the selected analog input signal, then converts the sample into digital output according
to the selected output format. The converter has four digital input pins (SDI, SCLK, CS, and FS) and one digital
output pi n (S D O ) t o communicate with the host device. SDI is a serial data input pin, SDO is a serial data output
pin, and SCLK is a serial clock from host device. This clock is used to clock the serial data transfer. It can also
be used as conversion clock source (see Table 2). CS and FS are used to start the operation. The converter
has a CSTART pin for external hardware sampling and conversion trigger, and INT/EOC for interrupt purpose.
device initialization
After power on, the status of EOC/INT is initially high, and the input data register is set to all zeros. The device
must be initialized before starting conversion. The initialization procedure depends on the working mode. The
first conversion result must be ignored after power on.
Hardware Default Mode: Nonprogrammed mode, default. After power on, two consecutive active cycles
initiated b y C S or FS put the device into hardware default mode if SDI is tied to DVDD. Each of these cycles must
last 16 SCLK at least. These cycles initialize the converter and load CFR register with 800h (bipolar of fset binary
output code, normal long sampling, internal OSC, single-ended input, one-shot conversion mode, and EOC/INT
pin as INT). No additional software configuration is required.
Software Programmed Mode: Programmed. If the converter needs to be configured, The host must write
A000H into converters first after power on, then performs the WRITE CFR operation to configure the device.
start of operation cycle
Each operation consists of several actions that the converter takes according to the command from the host.
The operation cycle includes three periods: command period, sampling period, and conversion period. In the
command period, the device decodes the command from host. In the sampling period, the device samples the
selected analog signal according to the command. In the conversion period, the sample of the analog signal
is converted to digital format. The operation cycle starts from the command period, which is followed by one
or several sampling and conversion periods (depending on the setting), and finishes at the end of last
conversion period. The operation is initiated by the falling edge of CS or the rising edge of FS.
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start of operation cycle (continued)
CS initiates the operation: I f FS is high at the falling edge of CS, the falling edge of CS initiates the operation.
When C S is high, SDO is in high-impedance state, the signals on SDI are ignored, and SCLK is disabled to clock
the serial data. The falling edge of CS resets the internal 4-bit counter and enables SDO, SDI, and SCLK. The
MSB of the input data via SDI, ID(15), is latched at the first falling edge of SCLK following the falling edge of
CS. The MSB of output data from SDO, OD(15), is valid before this SCLK falling edge. This mode works as an
SPI interface when CS is used as SLAVE SELECT (SS). It also can be used as normal DSP interface if CS
connects to the frame sync output of the host DSP. FS must be tied to high in this mode.
FS initiates the operation: If FS is low at the falling edge of CS, the rising edge of FS initiates the operation.
It resets the internal 4-bit counter, and enables SDI, SDO, and SCLK. The ID(15) is latched at the first falling
edge of SCLK following the falling edge of FS. OD(15) is valid before this falling edge of SCLK. This mode is
used to interface the converter with a serial port of the host DSP. The FS of the device is connected to the frame
sync of the host DSP. When several devices are connected to one DSP serial port, CS is used as chip select
to allow the host DSP to access each device individually. If only one converter is used, CS can be tied to low.
After the initiation, the remaining SDI data bits (if any) are shifted in and the remaining bits of SDO (if any) are
shifted out at the rising edge of SCLK. The input data are latched at the falling edge of SCLK, and the output
data are valid before the falling edge of SCLK. After the 4-bit counter reaches 16, the SDO goes to
high-impedance state. The output data from SDO is the previous conversion result in one shot conversion
mode, or the contents in the top of FIFO when FIFO is used (refer to Figure 20).
command period
After the rising edge of FS (FS triggers the operation) or the falling edge of CS (CS triggers the operation), SDI,
SDO, and SCLK are enabled. The first four SCLK clocks form the command period. The four MSBs of input data,
ID[15:12], are shifted in and decoded. These bits represent one of the 4-bit commands from the host, which
defines the required operation (see Table 1). The four MSB of output, OD[15:12], are also shifted out via SDO
during this period.
The commands are SELECT/CONVERSION, WRITE CFR, FIFO READ, and HARDWARE DEFAULT. The
SELECT/CONVERSION command includes SELECT ANALOG INPUT and SELECT TEST commands. All
cause a select/conversion operation. They select the analog signal being converted, and start the
sampling/conversion process after the selection. WRITE CFR causes the configuration operation, which writes
the device configuration information into CFR register. FIFO READ reads the contents in FIFO. Hardware
default mode sets the device into the hardware default mode.
After the command period, the remaining 12 bits of SDI are written into the CFR register to configure the device
if the command is WRITE CFR. Otherwise, these bits are ignored. The configuration is retained in the
autopower-down state. If the SCLK stops (while CS remains low) after the first eight bits are entered, the next
eight bits can be entered after the SCLK resumes. The data on SDI are ignored after the 4-bit counter counts
to 16 (falling edge of SCLK) or the low-to-high transition of CS, whichever happens first.
The remaining 12 bits of output data are shifted out from SDO if the command is SELECT/CONVERSION or
FIFO READ. Otherwise, the data on SDO must be ignored. In any case, the SDO goes into high-impedance
state after the 4-bit counter counts to 16 (falling edge of SCLK) or the low-to-high transition of CS, whichever
happens first.
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command period (continued)
Table 1. Command Set (CMR)
SDI Bit D[15:12]
TLC3578 / 2578 COMMAND
TLC3574 / 2574 COMMAND
BINARY HEX
TLC3578 / 2578 COMMAND
TLC3574 / 2574 COMMAND
0000b 0h SELECT analog input channel 0 SELECT analog input channel 0
0001b 1h SELECT analog input channel 1 SELECT analog input channel 1
0010b 2h SELECT analog input channel 2 SELECT analog input channel 2
0011b 3h SELECT analog input channel 3 SELECT analog input channel 3
0100b 4h SELECT analog input channel 4 SELECT analog input channel 0
0101b 5h SELECT analog input channel 5 SELECT analog input channel 1
0110b 6h SELECT analog input channel 6 SELECT analog input channel 2
0111b 7h SELECT analog input channel 7 SELECT analog input channel 3
1000b 8h Reserved
1001b 9h Reserved
1010b Ah WRITE CFR, the last 12 bits of SDI are written into CFR. This command resets FIFO.
1011b Bh SELECT TEST, voltage = (REFP+REFM)/2 (see Note 15)
1100b Ch SELECT TEST, voltage = REFM (see Note 16)
1101b Dh SELECT TEST, voltage = REFP (see Note 17)
1110b Eh FIFO READ, FIFO contents is shown on SDO; (see Note 18)
1111b Fh HARDWARE DEFAULT mode, CFR is loaded with 800h
NOTES: 15. The output code = mid-scale code + bipolar zero error
16. The output code = negative full-scale code + negative full-scale error
17. The output code = positive full-scale code + positive full-scale error
18. The TLC3574 and TLC3578, OD [15:2] is conversion result, OD [1:0] don’t care
The TLC2574 and TLC2578, OD [15:4] is conversion result, OD [3:0] don’t care
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detailed description (continued)
Table 2. Configuration Register (CFR) Bit Definition
SDI BIT DEFINITION
D11 Always 1. Otherwise the performance is degraded.
D10 Conversion output code format select:
0: BOB (bipolar offset binary); 1: BTC (binary 2s complement)
D9 Sample period select for normal sampling. Don’t care in extended sampling.
D9
0: Long sampling (4x) 44 SCLKs; 1: Short sampling 12 SCLKs
D8 Conversion clock source select:
0: Conversion clock = Internal OSC; 1: Conversion clock = SCLK/4
D7 Input mode select:
0: Single-ended; 1: Pseudodifferential. Pin configuration shown below.
Pin Configuration of TLC3578 and TLC2578 Pin Configuration of TLC3574 and TLC2574
Pin No. Single-ended Pseudodifferential polarity Pin No. Single-ended Pseudodifferential polarity
9
10 A0
A1 Plus
Minus Pair A 9
10 A0
A1 PLUS
MINUS Pair A
11
12 A2
A3 Plus
Minus Pair B 11
12 A2
A3 PLUS
MINUS Pair B
13
14 A4
A5 Plus
Minus Pair C
15
16 A6
A7 Plus
Minus Pair D
D[6:5] Conversion mode select
00: One shot mode
01: Repeat mode
10: Sweep mode
11: Repeat sweep mode.
D[4:3] Sweep auto sequence select (Note: These bits only take effect in conversion mode 10 and 11.)
D[4:3]
TLC3578 and TLC2578 TLC3574 and TLC2574
Single-ended (by ch) Pseudodifferential (by pair) Single-ended (by ch) Pseudodifferential (by pair)
00: 0−1−2−3−4−5−6−7
01: 0−2−4−6−0−2−4−6
10: 0−0−2−2−4−4−6−6
11: 0−2−0−2−0−2−0−2
00: N/A
01: A−B−C−D−A−B−C−D
10: A−A−B−B−C−C−D−D
11: A−B−A−B−A−B−A−B
00: 0−1−2−3−0−1−2−3
01: 0−2−0−2−0−2−0−2
10: 0−0−1−1−2−2−3−3
11: 0−0−0−0−2−2−2−2
00: N/A
01: A−B−A−B−A−B−A−B
10: N/A
11: A−A−A−A−B−B−B−B
D2 EOC/INT pin function select
0: Pin used as INT 1: Pin used as EOC ( for mode 00 only)
D[1:0] FIFO trigger level (sweep sequence length). Don’t care in one shot mode.
00: Full (INT generated after FIFO Level 7 filled)
01: 3/4 (INT generated after FIFO Level 5 filled)
10: 1/2 (INT generated after FIFO Level 3 filled)
11: 1/4 (INT generated after FIFO Level 1 filled)
sampling period
The sampling period follows the command period. The selected signal is sampled during this time. The device
has three different sampling modes: normal short mode, normal long mode, and extended mode.
Normal Short Sampling Mode: Sampling time is controlled by the SCLK and lasts 12 SCLK periods. At the
end of sampling, the converter automatically starts the conversion period. After the configuration, the normal
sampling starts automatically after the falling edge of fourth SCLK that follows the falling edge of CS if CS
triggers the operation, or follows the rising edge of FS if FS initiates the operation, except the FIFO READ and
WRITE CFR commands.
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sampling period (continued)
Normal Long Sampling Mode: It is the same as normal short sampling, except that it lasts 44 SCLKs periods
to complete the sampling.
Extended Sampling Mode: The external signal, CSTART, triggers sampling and conversion. SCLK is not used
for sampling. SCLK is also not needed for conversion if the internal conversion clock is selected. The falling edge
of CSTART begins the sampling of the selected analog input. The sampling continues while CSTART is low.
The rising edge of CSTART ends the sampling, and starts the conversion (with about 15 ns internal delay). The
occurrence of CSTART is independent of SCLK clock, CS, and FS. However, the first CSTART cannot occur
before the rising edge of the 11th SCLK. In other words, the falling edge of first CSTART can happen at or after
the rising edge of 11th SCLK , but not before. The device enters the extended sampling mode at the falling edge
of CSTART and exits this mode once CSTART goes to high followed by two consecutive falling edges of CS
or two consecutive rising edges of FS (such as one read data operations followed by WRITE CFR). The first
CS or FS does not cause conversion. Extended mode is used when a fast SCLK is not suitable for sampling,
or when extended sampling period is needed to accommodate different input signal source impedance.
conversion period
The conversion period is the third portion of the operation cycle. It begins after the falling edge of 16th SCLK
for the normal short sampling mode, or after the falling edge of 48th SCLK for the normal long sampling, or on
the rising edge of CSTART (with 15 ns internal delay) for the extended sampling mode.
The conversion takes 18 conversion clocks plus 15 ns for TLC3574/78, 13 conversion clocks plus 15 ns for the
TLC2574/78. The conversion clock source can be an internal oscillator, OSC, or an external clock, SCLK. The
conversion clock is equal to the internal OSC if the internal clock is used, or equal to four SCLKs when the
external clock is programmed. To avoid the premature termination of conversion, enough time for the conversion
must be allowed between consecutive triggers. EOC goes to low at the beginning of the conversion period and
goes to high at the end of the conversion period. INT goes to low at the end of this period, too.
conversion mode
Four different conversion modes (mode 00, 01, 10, 11) are available. The operation of each mode is slightly
different, depending on how the converter samples and what host interface is used. Do not mix different types
of triggers throughout the repeat or sweep operations.
ONE SHOT Mode (Mode 00): Each operation cycle performs one sampling and one conversion for the selected
channel. FIFO is not used. When EOC is selected, it is generated while the conversion period is in progress.
Otherwise, INT is generated after the conversion is done. The result is output through the SDO pin during the
next select/conversion operation.
REPEAT Mode (Mode 01): Each operation cycle performs multiple samplings and conversions for a fixed
channel selected according to the 4-bit command. The results are stored in the FIFO. The number of samples
to be taken equals the FIFO threshold programmed via D[1:0] in CFR register. Once the threshold is reached,
INT is generated, and the operation ends. If the FIFO is not read after the conversions, the data is replaced in
the next operation. The operation of this mode starts with the WRITE CFR commands to set conversion mode
01, then the SELECT/CONVERSION commands, followed by a number of samplings and conversions of the
fixed channel (triggered by CS, FS, or CSTART) until the FIFO threshold is hit. If C S or FS triggers the sampling,
the data on SDI must be any one of the SELECT CHANNEL commands. However, this data is a dummy code
for setting the converter in conversion state. It does not change the existing channel selection set at the start
of the operation until the FIFO is full. After the operation finishes, the host can read the FIFO, then reselect the
channel and start the next REPEAT operation again; or immediately reselect the channel and start next REPEAT
operation (by issuing CS or FS or CSTART); or reconfigure the converter then start new operation according
to the new setting. If CSTART triggers the sampling, host can also immediately start the next REPEAT operation
(on the current channel) after the FIFO is full. Besides, if FS initiates the operation and CSTART triggers the
samplings and conversions, CS must not toggle during the conversion. This mode allows the host to set up the
converter, continue monitoring a fixed input, and to get a set of samples as needed.
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conversion mode (continued)
SWEEP Mode (Mode 10): During each operation, all of the channels listed in the SWEEP SEQUENCE (D[4:3]
of CFR register) are sampled and converted one time according to the programmed sequence. The results are
stored in the FIFO. When the FIFO threshold is reached, an interrupt (INT) is generated, and the operation ends.
If the FIFO threshold is reached before all of the listed channels are visited, the remaining channels are ignored.
This allows the host to change the sweep sequence length. The mode 10 operation starts with the WRITE CFR
command to set the sweep sequence. The following triggers (CS, FS, or CSTART, depending on the interface)
start the samplings and conversions of the listed channels in sequence until the FIFO threshold is hit. If CS or
FS starts the sampling, the SDI data must be any one of the SELECT commands to set the converter in
conversion state. However, this command is a dummy code. It does not change the existing conversion
sequence. After the FIFO is full, the converter waits for FIFO READ. It does nothing before the FIFO READ or
WRITE CFR command is issued. The host must read the FIFO completely or WRITE CFR. If CSTART triggers
the samplings, the host must issue an extra SELECT/CONVERSION command (select any channel) via CS or
FS after the FIFO READ or WRITE CFR. This extra period is named the arm period and is used to set the
converter into conversion state, but does not affect the existing conversion sequence. If FS initiates the
operation and CSTART triggers the samplings and conversions, CS must not toggle during the conversion.
REPEAT SWEEP Mode (Mode 11): This mode works in the same way as mode 10, except that it is not
necessary to read the FIFO before the next operation after the FIFO threshold is hit. The next sweep can repeat
immediately, but the contents in the FIFO are replaced by the new results. The host can read the FIFO
completely, then issue next SWEEP; or repeat the SWEEP immediately (with the existing sweep sequence) by
issuing sampling/conversion triggers (CS, FS or CSTART); or change the device setting with the WRITE CFR
command.
The memory effect of charge redistribution DAC exists when the mux switches from one channel to another.
This degrades the channel-to-channel isolation if the channel changes after each conversion. For example, in
mode 10 and 11, the isolation is about 70 dB for the sweep sequence 0-1-2-3-4. The memory effect can be
reduced by increasing the sampling time or using sweep sequence 0-0-2-2-4-4-6-6 and ignoring the first sample
of each channel.
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operation cycle timing
4 SCLKs
4-bit Command 12-bit CFR Data (Optional)
12 SCLKs for Short
44 SCLKs for Long
4 SCLKs 12 SCLKs for Short
44 SCLKs for Long
Delay From
SDI
2-bit Don’t Care14-bit Data (Previous Conversion)
SDO
SDI
SDO
15 ns
15 nS
Active FS
t(setup)†t(sample) t(convert) t(overhead)
t(delay)†t(setup)†t(sample) t(convert) t(overhead)
CSTAR (For Extended Sampling) occurs at
or after the rising edge of eleventh SCLK
CSTAR (For Extended Sampling) occurs at
or after the rising edge of eleventh SCLK
CS Initiates
Operation
FS Initiates
Operation
18 OSC for Internal OSC‡
72 SCLK for External Clock
18 OSC for Internal OSC‡
72 SCLK for External Clock
4-bit Command 12-bit CFR Data (Optional)
2-bit Don’t Care
Active CS (FS Is T ied to High)
Active CS (CS Can Be Tied to Low)
14-bit Data (Previous Conversion)
§
§
CS
Low to FS High
†Non JEDEC terms used.
‡18 internal OSC or 72 SCLK for TLC3574 and TLC3578,
13 internal OSC or 52 SCLK for TLC2574 and TLC2578.
§For TLC3574 and TLC3578, 14-bits are result of previous conversion, last two bits are don’t care. For TLC2574 and TLC2578, 12-bits are result
of previous conversion, last four bits are don’t care.
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26 WWW.TI.COM
operation cycle timing (continued)
After the operation finished, the host has several choices. Table 3 summarizes of operation options.
Table 3. Operation Options
MODE
CONVERSION IS INITIATED BY
MODE
CS FS CSTART
00 1. Issue new Select/Read operation to
read data and start new conversion.
2. Reconfigure the device.
1. Issue new Select/Read operation to
read data and start new conversion.
2. Reconfigure the device.
1. Issue new CSTART to start next
conversion; old data lost.
2. Issue new Select/Read operation to
read data—Issue new CSTART to
start new conversion.
3. Reconfigure the device.
01 1. Read FIFO—Select Channel—Start
new conversion. Channel must be
selected after FIFO READ.
2. Select Channel—Start new
conversion (old data lost)
3. Configure device again.
1. Read FIFO—Select Channel—Start
new conversion. Channel must be
selected after FIFO READ.
2. Select Channel—Start new
conversion (old data lost)
3. Configure device again.
1. Read FIFO—Select channel—Start
new conversion. Channel must be
selected after FIFO READ.
2. Start new conversion (old data lost)
with existing setting.
3. Configure device again.
10 1. Read FIFO—Start new conversion
with existing setting.
2. Configure device—New conversion
(old data lost)
1. Read FIFO—Start new conversion
with existing setting.
2. Configure device—New conversion
(old data lost)
1. Read FIFO—Arm Period—Start new
conversion with existing setting
2. Configure device—Arm Period—New
conversion (old data lost)
11 1. Read FIFO—Start new conversion
with existing setting.
2. Start new conversion with the existing
setting.
3. Configure device—Start new
conversion with new setting.
1. Read FIFO—Start new conversion
with existing setting
2. Start new conversion with the existing
setting.
3. Configure Device—Start new
conversion with new setting.
1. Read FIFO—Arm Period—Start new
Conversion with existing setting
2. Start new conversion with existing
setting. (old data lost)
3. Configure device—Arm Period—New
conversion with new setting.
operation timing diagrams
The nonconversion operation includes FIFO READ and WRITE CFR. Both do not perform a conversion. The
conversion operation performs one of four types of conversion: mode 00, 01, 10 and 11
write cycle (WRITE CFR Command): Write cycle does not generate EOC or INT, nor does it carry out any
conversion.
1235
46713 14 15 16 1
ID15 1D14 ID13 1D12
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
12
ID15
ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌ
ÌÌ
ÌÌ
ÌÌÌÌ
ÌÌÌÌ
ID11 ID10 ID9 ID4 ID3 ID2 ID1 ID0
OR
CS
FS
SDI
INT
EOC
SDO Hi-Z
The dotted lines means signal may or may not exist.
ÌÌÌ
Don’t care
Figure 8. Write Cycle, FS Initiates Operation
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operation timing diagrams (continued)
123 546
713 14 15 16 1
ID15 1D14 ID13 1D12
ÌÌÌ
ÌÌÌ
Ì
Ì
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
12
ID15
ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌ
ÌÌ
ÌÌÌ
ID14ID11 ID10 ID9 ID4 ID3 ID2 ID1 ID0
ÌÌ
ÌÌ
OR
ÌÌÌ
ÌÌÌ
Don’t Care
CS
FS = High
SDI
INT
EOC
SDO Hi-Z
The dotted lines means signal may or may not exist.
Figure 9. Write Cycle, CS Initiates Operation, FS = 1
FIFO READ Operation: When the FIFO is used, the first command after INT is generated is assumed to be
the FIFO READ. The first FIFO content is output immediately before the command is decoded. If this command
is not FIFO READ, the output is terminated. Using more layers of FIFO reduces the time taken to read multiple
conversion results, because the read cycle does not generate an EOC or INT, nor does it make a data
conversion. Once the FIFO is read, the entire contents in FIFO must be read out. Otherwise, the remaining data
is lost.
ÌÌÌ
ÌÌÌ
123 5
467 13
14 15 16 1
ID15 1D14 ID13 1D12
OD11 OD10 OD9 OD4 OD3 OD2
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
12
ID15 ID14
OD15 OD14 OD13 OD12 OD15
ÌÌ
ÌÌ
ÌÌ
ÌÌ
OD14
OR
SCLK
CS
FS = High
SDI
INT
EOC
SDO
OD[15:2] (for TLC3574/78) or OD[15:4](for TLC2574/78) is the FIFO content.
ÌÌ
ÌÌ
Don’t Care
Hi-Z
The dotted lines means signal may or may not exist.
Figure 10. FIFO Read Cycle, CS Initiates Operation, FS = 1
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28 WWW.TI.COM
conversion operation
CS
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
123 5467 13 14 15 1
ID15 ID14 ID13 1D12
ÌÌ
ÌÌ
ÌÌÌ
ÌÌÌ
12
ID15
OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD4 OD2 OD15
48 SCLKs for Long Sampling
16 SCLKs for Short Sampling
SDO goes to Hi−Z after 16th SCLK
ÌÌÌ
ÌÌ
16
Hi−Z
ÌÌ
ÌÌ
ÌÌÌ
ÌÌÌ
t(conv)
t(SAMPLE)
FS in High
SDI
INT
EOC
SDO
OR Previous Conversion Result
Select Channel
OD3
OD[15:2] (for TLC3574/78) or OD [15:4] (for TLC2574/78) is the result of previous conversion.
ÌÌ
ÌÌ
Don’t Care
The dotted line means signal may or may not exist.
Figure 11. Mode 00, CS Initiates Operation
ÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌ
123 5467 131415 1
ID15 1D14 ID13 1D12
ÌÌÌ
ÌÌÌ
12
ID15
ÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌ
ÌÌ
ÌÌ
OD14 OD13 OD12 OD11 OD10 OD9 OD4OD15 OD15OD2OD3
48 SCLKs for Long Sampling
16 SCLKs for Short Sampling
ÌÌ
ÌÌ
16
Hi-Z
SDO Goes Through Hi-Z After 16 SCLK
Previous Conversion Result
Select Channel
t(SAMPLE) t(conv)
SCLK
CS
FS
SDI
INT
EOC
SDO
OR
OD[15:2] (for TLC3574/78) or OD[15:4](for TLC2574/78) is the result of previous conversion.
ÌÌÌ
ÌÌÌ
Don’t Care
The dotted line means signal may or may not exist.
Figure 12. Mode 00, FS Initiates Operation
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conversion operation (continued)
***
ÌÌÌÌ
Hi-Z
** **
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌ
Data Lost Hi-Z
** Select Channel
Possible
Signal
t(sample)
t(convert)
Select Channel
16 SCLK Select Channel
16 SCLK
Previous Conversion Result
CS Tied to Low
CSTART
FS
SDI
INT
EOC
SDO Hi-Z
OR Conversion Result
ÌÌ
ÌÌ
Don’t Care
Possible Signal
Figure 13. Mode 00, CSTART Triggers Sampling/Conversion, FS Initiates Select
**
ÌÌÌ
ÌÌ
ÌÌ
ÌÌ
Hi-Z
ÌÌ
ÌÌÌ
*** * **
*
ÌÌÌ
*
ÌÌÌ
*
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
Select CH1 Select CH2
1/4 FIFO FULL 1/4 FIFO FULL
Ì
Ì
Don’t Care
*** −− WRITE CFR
** −− Select Channel
* −− FIFO Read
**
ÌÌÌ
ÌÌÌ
**
ÌÌÌ
ÌÌÌ
Select Any
Channel Select Any
Channel
Possible Signal
DATA1 of CH1 DATA2 of CH1
MODE 01, FS Activates Conversion, FIFO Threshold = 1/4 Full
Read FIFO After Threshold Is Hit
CS
FS
SDI
SDO
INT
DATA1 of CH2 DATA2 of CH2
Figure 14. Mode 01, FS Initiates Operations
**
ÌÌ
ÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
Hi-Z
ÌÌ
ÌÌ
ÌÌÌ
ÌÌÌ
***
ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌ
***
*
ÌÌÌ
ÌÌÌ
*
ÌÌ
ÌÌ
*
ÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌ
ÌÌ
1/4 FIFO FULL 1/4 FIFO FULL
ÌÌ
Don’t Care
*** −− WRITE CFR
** −− Select Channel
* −− FIFO Read
Select CH1 Select CH2
DATA1 of CH1 DATA2 of CH1 DATA1 of CH2 DATA2 of CH2
MODE 01, FS Initiates Select Period, CSTART Activates Conversion, FIFO Threshold = 1/4 Full,
Read FIFO After Threshold Is Hit
CS
FS
CSTART
SDI
SDO
INT
Possible Signal
Figure 15. Mode 01, CSTART Triggers Samplings/Conversions
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30 WWW.TI.COM
conversion operation (continued)
1st Sweep
1st FIFO Read
Configure
2nd FIFO Read
Ì
Ì
***
ÌÌ
CH0 CH1 CH2 CH3 CH0
ÌÌ
ÌÌ
ÌÌ
ÌÌ
*
ÌÌ
ÌÌ
*
ÌÌ
ÌÌ
*
ÌÌ
ÌÌ
*
ÌÌ
ÌÌ
*
Hi-Z
*** Command = Configure Write for Mode 10, FIFO
Threshold = 1/2 Full, Sweep Sequence: 0−1−2−3
** COMMAND = Select Any Channel
* COMMAND = Read FIFO
** ** ** **
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
Ì
Ì
** ** ** **
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÌÌÌ
Conversion
From CH0 Conversion
From CH3 Conversion
From CH0 Conversion
From CH3
2nd Sweep
Using Existing
Configuration
Read FIFO After FIFO Threshold Is Hit
CS
FS
SDI
INT
SDO
ÌÌ
ÌÌ
Don’t Care
Figure 16. Mode 10, FS Initiates Operations
1st Sweep
1st FIFO Read
Configure
2nd FIFO Read
Hi-Z
*** Command = Configure Write for Mode 10, FIFO
Threshold = 1/2 Full, Sweep Sequence: 0−0−2−2
** COMMAND = Select Any Channel
* COMMAND = Read FIFO
Conversion
From CH0 Conversion
From CH2 Conversion
From CH0 Conversion
From CH2
2nd Sweep
Using Existing
Configuration
Read FIFO After FIFO Threshold Is Hit, FS Initiates Select Period
CS Tied
to Low
FS
SDI
INT
Ì
Ì
***
ÌÌÌ
ÌÌÌ
CH0 CH0 CH2 CH2
ÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌ
CH0
ÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌ
*
ÌÌÌ
ÌÌÌ
*
ÌÌ
ÌÌ
*
ÌÌ
ÌÌ
*
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
***
ÌÌ
ÌÌ
SDO
**
CSTART
ÌÌ
ÌÌ
Don’t Care
Figure 17. Mode 10, CSTART Initiates Operations
START 2nd Round SWEEP CONVERSION,
the DATA of the 1st Round Are Lost
CS
FS=High
SDI
INT
SDO
READ the DATA of 2nd
Sweep From FIFO
Ì
ÌÌ
ÌÌ
CH1 CH3CH2CH0
ÌÌ
ÌÌ
ÌÌÌ
ÌÌ
ÌÌ
START 2nd Sweep conversion immediately (NO FIFO READ) after the 1st SWEEP completed.
***
Ì
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌ
ÌÌÌÌ
Ì
Ì
*** Command = Configure Write for Mode 11, FIFO
Threshold = 1/2 Full, Sweep Sequence: 0−1−2−3
** COMMAND = Select Any Channel
* COMMAND = Read FIFO
**** ** ** ** ** ** ** * * * * **
Configure Conversion
From CH0 Conversion
From CH3 Conversion
From CH3 Conversion
From CH0
Conversion
From CH0
ÌÌ
Don’t Care
Figure 18. Mode 11, CS Initiates Operations
±
SLAS262C − O C TOBER 2000 − REVISED MAY 2003
31
WWW.TI.COM
conversion operation (continued)
CS
FS
SDI
INT
SDO
*** Command = Configure Write for Mode 11, FIFO
Threshold = 1/2 Full, Sweep Sequence: 0−0−2−2
** COMMAND = Select Any Channel
* COMMAND = Read FIFO
*
Configure Conversion
From CH0 Conversion
From CH2 Conversion
From CH2
Conversion
From CH0
1st SWEEP
1st FIFO Read
REPEAT
2nd FIFO Read
ÌÌ
ÌÌ
CH0 CH0 CH2 CH2 CH0
ÌÌÌÌÌÌÌÌÌÌÌ
ÌÌ
ÌÌ
ÌÌÌ
ÌÌÌÌÌÌÌÌÌ
ÌÌ
READ FIFO after 1st SWEEP Completed
Ì
CSTART
*** ** ****** *
Possible Signal
Ì
Ì
Don’t Care
Figure 19. Mode 11, CSTART Triggers Samplings/Conversions, FS Initiates SELECT Operation
conversion clock and conversion speed
The conversion clock source can be the internal OSC, or the external clock, SCLK. The conversion clock is equal
to the internal OSC if the internal clock is used, or equal to SCLK/4 when the external clock is selected. It takes
18 conversion clocks plus 15 ns to finish the conversion for TLC3574 and TLC3578, and 13 conversion clocks
plus 15 ns for the TLC2574 and TLC2578. If the external clock is selected, the conversion time (not including
sampling time) is 18X(4/fSCLK)+15 ns for TLC3574 and TLC3578 and 13X(4/fSCLK)+15 ns for TLC2574 and
TLC2578. Table 4 shows the maximum conversion rate (including sampling time) when the analog input source
resistor is 25 Ω.
Table 4. Maximum Conversion Rate
DEVICE SAMPLING MODE CONVERSION CLK MAX SCLK
(MHz) CONVERSION
TIME (µs) RATE
(KSPS)
SHORT (16 SCLK) External SCLK/4 10 8.815 113.4
TLC3574/78
LONG (48 SCLK) External SCLK/4 25 4.815 207.7
TLC3574/78
(Rs = 25 Ω)SHORT (16 SCLK) Internal 6.5 MHz 10 4.384 228.0
(Rs = 25 )
LONG (48 SCLK) Internal 6.5 MHz 25 4.705 212.5
SHORT (16 SCLK) Exernal SCLK/4 10 6.815 146.7
TLC2574/78
LONG (48 SCLK) External SCLK/4 25 4.015 249.1
TLC2574/78
(Rs = 25 Ω)SHORT (16 SCLK) Internal 6.5 MHz 10 3.615 276.6
(Rs = 25 )
LONG (48 SCLK) Internal 6.5 MHz 25 3.935 254.1
±
SLAS262C − O C TOBER 2000 − REVISED MAY 2003
32 WWW.TI.COM
FIFO operation
76543210ADC
×8
FIFO
SOD
Serial
FIFO Full FIFO 3/4 Full
FIFO 1/2 FullFIFO 1/4 Full
FIFO Threshold Pointer
Figure 20. FIFO Structure
FIFO operation (continued)
The device has an 8-level FIFO that can be programmed for different thresholds. An interrupt is sent to the host
after the preprogrammed threshold is reached. The FIFO is used to store conversion results in mode 01, 10,
and 11, from either a fixed channel or a series of channels according to the preprogrammed sweep sequence.
For example, an application may require eight measurements from channel 3. In this case, if the threshold is
set to full, the FIFO is filled with 8 data conversions sequentially taken from channel 3. Another application may
require data from channel 0, 2, 4, and 6 in that order. The threshold is set to 1/2 full and sweep sequence is
selected as 0−2−4−6−0−2−4−6. An interrupt is sent to the host as soon as all four data conversions are in the
FIFO. FIFO is reset after power on and WRITE CFR operation. The contents of the FIFO are retained during
autopower down.
Autopower-Down Mode: The device enters the autopower-down state at the end of conversion. The power
current is about 20 µA if SCLK stops, and 120 µA maximum if SCLK is running. Active CS , FS, or CSTART
resumes the device from power-down state. The bipolar input current is not turned off when device is in
power-down mode.
The configuration register is not affected by the power-down mode but the SWEEP operation sequence must
be started over again. All FIFO contents are retained in power-down mode.
±
SLAS262C − O C TOBER 2000 − REVISED MAY 2003
33
WWW.TI.COM
TYPICAL CHARACTERISTICS
Figure 21
INTEGRAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
Digital Output Code
INL − Integral Nonlinearity − LSB
0.5
−0.5 0 2000 4000 6000 8000 10000
1
1.5
2
12000 14000 16000
0
Reference = 4 V
AVDD = 5 V, TA = 25°C
−0.6
−0.4
−0.2
−0.0
0.2
0.4
0.6
0 2000 4000 6000 8000 10000 12000 14000 16000
DIFFERENTIAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
Digital Output Code
Reference = 4 V
AVDD = 5 V, TA = 25°C
DNL − Differential Nonlinearity − LSB
Figure 22
±
SLAS262C − O C TOBER 2000 − REVISED MAY 2003
34 WWW.TI.COM
TYPICAL CHARACTERISTICS
Figure 23
0.4
0.7
1
1.3
−40.00 25 85
INL (LSB) and DNL (LSB)
INL (LSB) AND DNL (LSB)
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
DNL
INL
Reference = 4 V
AVDD = 5 V
Figure 24
TA − Free-Air Temperature − °C
0.200
0.100
−40.00 25
0.300
0.400
BIPOLAR ZERO ERROR, POSITIVE FULL SCALE ERROR
AND NEGATIVE FULL SCALE ERROR (% FS)
vs
FREE-AIR TEMPERATURE
0.500
85
Reference = 4 V
AVDD = 5 V
Negative Full Scale Error
Positive Full Scale Error
E0,EFS(+) (%FS)and EFS(−)
Bipolar Zero Error
Figure 25
−180
−160
−140
−120
−100
−80
−60
−40
−20
0
0.0 24.4 48.8 73.2 97.6
FFT OF SNR (dB)
f − Frequency − kHz
0
−20
−40
−60
−80
−100
−120
−140
−160
−180 0 24.4 48.8 73.2 97.7
FFT of SNR − dB
Reference = 4 V
AVDD = 5 V
TA = 25°C
200 KSPS
Input Signal = 20 kHz, 0dB
±
SLAS262C − O C TOBER 2000 − REVISED MAY 2003
35
WWW.TI.COM
TYPICAL CHARACTERISTICS
Figure 26
fI − Input Signal Frequency − Hz
76
74
721 k 20 k 40 k
SINAD − dB
78
80
SINAD
vs
INPUT SIGNAL FREQUENCY
82
60 k 80 k
Reference = 4 V
AVDD = 5 V
TA = 25°C
100 k
Figure 27
12
11.61 k 20 k 40 k 60 k
ENOB − (Bits)
12.4
12.8
ENOB
vs
INPUT SIGNAL FREQUENCY
13.2
80 k
Reference = 4 V
AVDD = 5 V
TA = 25°C
fI − Input Signal Frequency − Hz 100 k
Figure 28
−841 k 20 k 40 k 60 k
THD − Total Harmonic Distortion − dB
−82
−80
TOTAL HARMONIC DISTORTION
vs
INPUT SIGNAL FREQUENCY
−78
100 k
Reference = 4 V
AVDD = 5 V
TA = 25°C
fI − Input Signal Frequency − Hz
80 k
Figure 29
79
771 k 20 k 40 k 60 k
SFDR − dB
81
83
SFDR
vs
INPUT SIGNAL FREQUENCY
85
100 k
Reference = 4 V
AVDD = 5 V
TA = 25°C
fI − Input Signal Frequency − Hz
80 k
±
SLAS262C − O C TOBER 2000 − REVISED MAY 2003
36 WWW.TI.COM
TYPICAL CHARACTERISTICS
Figure 30
5
−40.00 25
5.2
5.4
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
5.6
85
Reference = 4 V
AVDD = 5 V
ICC − Supply Current − mA
TA − Free-Air Temperature − °CFigure 31
2
−40 25
3
SUPPLY CURRENT AT AUTOPOWER DOWN
vs
FREE-AIR TEMPERATURE
4
85
CC
I Supply Current − −Aµ
TA − Free-Air Temperature − °C
Reference = 4 V
AVDD = 5 V
SCLK Stops
Autopower Down
±
SLAS262C − O C TOBER 2000 − REVISED MAY 2003
37
WWW.TI.COM
APPLICATION INFORMATION
interface with host
Figure 32 shows the examples of the interface between a single converter and host DSP (TMS320C54xDSP)
or microprocessor. The C54x is set as FWID=1 (active pulse width=1CLK); (R/X) DATDLY=1 (1 bit data delay);
CLK(X/R)P=0 (transmit data are clocked out at rising edge of CLK, receive data are sampled on falling edge
of CLK); and FS(X/R)P=1 (FS is active high). If multiple converters connect to the same C54x, use CS as chip
select.
The host microprocessor is set as the SPI master, CPOL=0 (active high clock), and CPHA=1 (transmit data is
clock out at rising edge of CLK, receive data are sampled at falling edge of CLK). 16 bits (or more) per transfer
is required.
FSR
FSX
DX
DR
CLKR
CLKX
IRQ
TMS320C54X Converter
10 kΩ
VDD
CS
FS
SDI
SDO
SCLK
INT/EOC
Ain
Single Converter Connects to DSP
SS
MOSI
MISO
SCK
IRQ
Host
Microprocessor Converter
10 kΩ
VDD
CS
FS
SDI
SDO
SCLK
INT/EOC
Converter Connects to Microprocessor
10 kΩ
Ain
Figure 32. Typical Interface to Host DSP and Microprocessor
sampling time analysis
Figure 33 shows the equivalent circuit to evaluate the required sampling time. Req is the Thevenin equivalent
resistor (Req = 3.5 K). The C(sampling) is sampling capacitor (30 pF maximum).
To get 1/4 LSB accuracy, the sampling capacitor, Csampling, has to be charged to
VC = VS ± voltage of 1/4 LSB = VS ± (VS/65532) for 14 bit converter (TLC3574 and TLC3578)
= VS ± (VS/16384) for 12 bit converter (TLC2574 and TLC2578)
During the sampling time t(sampling), C(sampling) is charge to
VC+VSȧ
ȱ
Ȳ1–exp ǒ–t(sampling)
Req C(sampling)Ǔȧ
ȳ
ȴ
Therefore, the required sampling time is
t(sampling) = Req × C(sampling) × In (65532) for 14-bit (TLC3574 and TLC3578)
t(sampling) = Req × C(sampling) × In (16384) for 12-bit (TLC2574 and TLC2578).
TMS320C54x is a trademark of Texas Instruments.
±
SLAS262C − O C TOBER 2000 − REVISED MAY 2003
38 WWW.TI.COM
APPLICATION INFORMATION
3.94 kΩ
6.6 kΩ
9.9 kΩ
Bipolar Signal
Scaling
1.5 kΩ Max
Ron
MUX
C(sample)
= 30 pF
Converter
REFP
REFM
C(sample)
= 30 pF Max
Req
Vs
Req = Thevenin Equivalent Resistance
Vs = Thevenin Equivalent Voltage
Ain
Figure 33. Equivalent Input Circuit Including the Driving Source
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLC2574IDW ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2574IDWG4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2574IPW ACTIVE TSSOP PW 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2574IPWG4 ACTIVE TSSOP PW 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2578IDW ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2578IDWG4 ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC2578IPW ACTIVE TSSOP PW 24 60 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC2578IPWG4 ACTIVE TSSOP PW 24 60 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC2578IPWR ACTIVE TSSOP PW 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC2578IPWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC3574IDW ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC3574IDWG4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC3574IDWR ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC3574IDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC3574IPW ACTIVE TSSOP PW 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC3574IPWG4 ACTIVE TSSOP PW 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC3578IDW ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC3578IDWG4 ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC3578IDWR ACTIVE SOIC DW 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC3578IDWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC3578IPW ACTIVE TSSOP PW 24 60 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC3578IPWG4 ACTIVE TSSOP PW 24 60 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC3578IPWR ACTIVE TSSOP PW 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC3578IPWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
PACKAGE OPTION ADDENDUM
www.ti.com 6-Oct-2008
Addendum-Page 1
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 6-Oct-2008
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLC2578IPWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
TLC3578IPWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC2578IPWR TSSOP PW 24 2000 367.0 367.0 38.0
TLC3578IPWR TSSOP PW 24 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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