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availability and additional information.
© 1998
MOS INTEGRATED CIRCUIT
µ
µ µ
µ
PD16780A
300 OUTPUT TFT-LCD SOURCE DRIVER
DATA SHEET
Document No. S14606EJ1V0DS00 (1st edition)
Date Published November 2000 NS CP(K)
Printed in Japan
The mark ★ shows ma
j
or revised
p
oints.
DESCRIPTION
The
µ
PD16780A is a source driver for 300-output TFT-LCDs, providing support for only striped pixel array LDCs..
The driver consists of a shift register for generating the sampling timing and sample & hold circuits for sampling the
analog voltage. The high picture quality obtained by the alternate sample & hold execution of the two types of on-
chip sample & hold circuits enables employment in applications such as car navigation panels.
FEATURES
• 5.0 V Drive (Dynamic range 4.6 VP-P, VDD2 = 5.0 V)
• 300 Output channel
• fCLK = 20 MHz MAX. (VDD1 = 3.0 V)
• 1-phase/3-phase sampling clocks supported
• Corresponds only to LCD of Stripe array color filter
• Two on-chip sample-and-hold circuits
• Small output deviation between pins (deviation between chip pins: ±20 mV MAX.)
• Switch between right and left shift using the R,/L pin
• Logic power supply voltage (VDD1): 3.0 to 5.5 V
• Driver power supply voltage(VDD2): 5.0 ± 0.5 V
ORDERING INFORMATION
Part Number Package
µ
PD16780AN-xxx TCP (TAB package)
Remark The TCP’s external shape is customized. To order the required shape, so please contact one of out sales
representatives.
Data Sheet S14606EJ1V0DS
2
µ
µ µ
µ
PD16780
A
1. BLOCK DIAGRAM
S
1
S
2
S
299
S
300
C
1
C
2
C
99
C
100
100-bit Shift Register
Level Shifter
Sample And Hold
STHR STHL
V
DD1
(3.3/5.0 V)
V
SS1
V
DD2
(5.0 V)
V
SS2
V
SS3
R,/L
CLK
1
to CLK
3
MODE
C
1
C
2
C
3
CX
Remark /xxx indicates active low signal.
2. SAMPLE-AND HOLD CIRCUIT AND OUTPUT CIRCUIT
–
+
–
+
SW
SW
S
n
C
H1
V
SS3
C
H1
V
SS3
SW
S&H
1
SW
S&H
2
Video Line (C
n
)
SHPn
CX
Data Sheet S14606EJ1V0DS 3
µ
µ µ
µ
PD16780
A
3. PIN CONFIGURATION (
µ
µµ
µ
PD16780AN-xxx) (COPPER FOIL SURFACE, FACE UP)
S300
S299
S298
STHL
VDD2
VSS2
C1
C2
C3 Copper foil
VDD1 surface
CLK1
CLK2
CLK3
MODE
R,/L
CX
TEST
VSS1
VSS3
VSS2
VDD2 S3
STHR S2
S1
Remark This figure does not specify the TCP package.
Data Sheet S14606EJ1V0DS
4
µ
µ µ
µ
PD16780
A
4. PIN FUNCTIONS
Pin Sy m bol Pin Name Description
C1, C2, C3Video s i gnal i nput These pins are i nput video si gnal s R,G, and B .
S1 to S300 Video signal out put These pins are output video signals, whi ch have been sam pl ed and hol d.
The relations hi p bet ween the video s i gnal i nput (C1, C2, C3) and video signal out put is
shown below.
C1: S3n-2 (n = 1, 2, ··········100)
C2: S3n-1
C3: S3n
STHR,
STHL
Cascade I / O These pins are i nputs/out put s for the s tart pulse for sample and hol d t i ming.
High level of STHR/STHL is read at ri sing edge of CLK and start s ampling vi deo
signal. S T HR serves as the input pi n and STHL serves as output pi n for the right shift.
For left shift, STHL serves as the input pins and STHR serves as the output pin.
R,/L Shift direction switching
input
The shift di rections of the shif t regi sters are as follows .
R,/L = H: STHR input, S1 → S300, STHL out put.
R,/L = L: STHL input, S300 → S1, STHR output.
CLK1 to CLK3Shift cloc k input The start pul se is read at ri sing edge of CLK. The sampli ng pul se SHPn is generat ed
at risi ng edge of CLK. For detail s, refer t o 6. TIMING CHART.
The relations hi p bet ween the clocks and the output pins i s shown below.
(1) When MODE = L or open (sequential sam pl i ng)
CLK1 R,/L = H: S3n-2
R,/L = L: S3n
CLK2 :S3n-1
CLK3 R,/L = H: S3n
R,/L = L: S3n-2
(1) When MODE = H (si multaneous sampling)
CLK1: S3n-2, S3n-1, S3n (n = 1,2,·····100)
CLK2: Connect VDD1 or VSS1
CLK3: Connect VDD1 or VSS1
MODE Mode select signal i nput
pin
This pin is used to s el ect whether t he three analog input s i gnal s, C1, C2, and C3 are
sampled s i m ul taneously or sequentially (This pin i s pulled down in the IC).
MODE = H: S i multaneous sampling
MODE = L or open: S equential sam pl i ng
CX Hold capaci tance cont rol
input
Two Sample & hol d circuit s are switched.
CX = H S&H1: S ampling, S&H2: Output
CX = L S&H1: Output, S&H2: Sampling
TEST Test pin Fix thi s pin to the L level.
VDD1 Logic power suppl y 3.0 to 5.5 V
VDD2 Driver power suppl y 5.0 V ± 0.5 V
VSS1 Logic ground Grounding
VSS2 Driver ground Grounding
VSS3 Sample & hol d ground It is ground of Sample & hol d capacit ance. Supply this terminal with the st abl e GND.
Data Sheet S14606EJ1V0DS 5
µ
µ µ
µ
PD16780
A
Cautions 1. To prevent latch-up-breakdown, the power should be turned on in order VDD1, Logic input VDD2,
video signal input. It should be turned off in the opposite order. This relationship should be
followed during transition periods as well.
2. The sampling of the video signal of this IC is only the simultaneous 3 output sampling of C1, C2,
C3. Incidentally, it is designing abound of the input of the video signal in 10 MHz MAX.
If a video signal with a higher frequency is input, the data may not be correctly displayed.
3. Recommend a bypass capacitor of about 0.1
µ
µµ
µ
F with good high-frequency characteristics
between VDD1 and VSS1, and VDD2 and VSS2 in each driver IC.
4. If noise is superimposed on the start pulse pin, the data may not be displayed. For this reason,
be sure to input CX signal during the vertical blanking period.
5. If the start pulse width is extended by half the clock or longer, the sampling start timing SHP1
does not change from normal timing; therefore, the sampling operation is performed normally.
5. FUNCTION DESCRIPTION
5.1 Switching of Sample & Hold Circuits
Two sample-and-hold circuits are switched.
CX Output Sample & hol d operation
L Sample & Hol d Ci rcuit 1 (S&H1) Sample & Hol d Ci rcuit 2 (S&H2)
H Sample & Hol d Ci rcuit 2 (S&H2) Sample & Hold Circuit 1 (S&H1)
5.2 Sample & Hold and Output
Relation between video signals C1, C2 and C3 and output pins and two sample & hold circuits.
CX S1 (S300)S
2 (S299)S
3 (S298)S
4 (S297) ··· S299 (S2)S
300 (S1)
L Sampling C1-2 (C3-2)C
2-2 (C2-2)C
3-2 (C1-2)C
1-2 (C3-2) ··· C2-2 (C2-2)C
3-2 (C1-2)
Output C1-1 (C3-1)C
2-1 (C2-1)C
3-1 (C1-1)C
1-1 (C3-1) ··· C2-1 (C2-1)C
3-1 (C1-1)
H Sampling C1-1 (C3-1)C
2-1 (C2-1)C
3-1 (C1-1)C
1-1 (C3-1) ··· C2-1 (C2-1)C
3-1 (C1-1)
Output C1-2 (C3-2)C
2-2 (C2-2)C
3-2 (C1-2)C
1-2 (C3-2) ··· C2-2 (C2-2)C
3-2 (C1-2)
Remark Cm-n = m: Video input, n: Sample & Hold
Data Sheet S14606EJ1V0DS
6
µ
µ µ
µ
PD16780
A
6. TIMING CHART
6.1 1-Phase simultaneous sampling
CLK
1
STHR
(STHL)
STHR
(STHL)
SHP
1
-SHP
3
(SHP
300
-SHP
298
)
S
1
-S
3
(S
300
-S
298
)
S
1
-S
3
(S
300
-S
298
)
S
4
-S
6
(S
297
-S
295
)
S
295
-S
297
(S
6
-S
4
)
S
298
-S
300
(S
3
-S
1
)
S
4
-S
6
(S
297
-S
295
)
S
7
-S
9
(S
294
-S
292
)
SHP
4
-SHP
6
(SHP
297
-SHP
295
)
SHP
1
-SHP
3
(SHP
300
-SHP
298
)
SHP
4
-SHP
6
(SHP
297
-SHP
295
)
SHP
295
-SHP
297
(SHP
6
-SHP
4
)
SHP
298
-SHP
300
(SHP
3
-SHP
1
)
SHP
7
-SHP
9
(SHP
294
-SHP
292
)
1 2 3 (1) (2) (3)99 100
Data Sheet S14606EJ1V0DS 7
µ
µ µ
µ
PD16780
A
6.2 3-phase sequential sampling, right shift
CLK1
STHR
SHP2
SHP298
SHP299
SHP4
SHP1
123 100
4
CLK2
CLK3
SHP3
SHP300
S
298
S
299
S
300
S
1
S
2
S
3
S
4
Data Sheet S14606EJ1V0DS
8
µ
µ µ
µ
PD16780
A
6.3 3-phase sequential sampling, left shift
CLK1
STHL
SHP2
SHP298
SHP299
SHP1
123 100
4
CLK2
CLK3
SHP3
SHP300
S
1
S
2
S
3
SHP297
S
297
S
299
S
298
S
300
Data Sheet S14606EJ1V0DS 9
µ
µ µ
µ
PD16780
A
7. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = +25°
°°
°C, VSS1 =VSS2 = 0 V)
Parameter Symbol Rating Unit
Logic Part Supply Vol tage VDD1 −0.3 to +7.0 V
Driver Part Supply V oltage VDD2 −0.3 to +7.0 V
Input Vol tage VI−0.3 to V DD1/2 + 0.3 V
Output Vol t age VO−0.3 to V DD1/2 + 0.3 V
Operating Ambi ent Temperature TA−30 to +85 °C
Storage Temperat ure Tstg −55 to +125 °C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Range (TA = −
−−
−30 to +85°
°°
°C, VDD2 ≥
≥≥
≥ VDD1, VSS1 = VSS2 = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Logic Part Supply Vol tage VDD1 3.0 5.5 V
Driver Part Supply V oltage VDD2 4.5 5.0 5.5 V
Video Input V ol tage VVI VSS2 + 0.2 VDD2 − 0.2 V
Driver Part Output Voltage VO2 VSS2 + 0.2 VDD2 − 0.2 V
Maximum Clock Frequency fCLK CLK1 to CLK320 MHz
Output Load Capaci tance CL1 output 50 pF
Data Sheet S14606EJ1V0DS
10
µ
µ µ
µ
PD16780
A
Electrical Characteristics (TA = –30 to +85°C, VDD1 = 3.0 to 5.5 V, VDD2 = 5.0 V ±
±±
± 0.5 V, VDD2 ≥
≥≥
≥ VDD1,
VSS1 = VSS2 = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Low-Level Driv er Part Output Voltage VVOL VSS2 + 0.2 V
High-Level Driver Part Out put Voltage VVOH
S1 to S300
VDD2 – 0.2 V
High-Level I nput Voltage VIH 0.7 VDD1 VDD1 V
Low-Level Input Voltage VIL
CLK, ST HR (L), R,/L, CX,
MODE VSS1 0.3 VDD1 V
Exc ept for MODE pin –1.0 +1.0
µ
A
VI = 0 V –10 +10
µ
A
Input Leak Current IIL
MODE pin
VI = VDD1 = 5 V 30 300
µ
A
High-Level Out put Voltage VLOH ST HR (STHL), IOH = –1.0 m A 0.85 VDD1 V
Low-Level Output Voltage VLOH ST HR (STHL), IOL = +1.0 m A 0.15 VDD1 V
VREF1 VDD2 = 5.0 V, VVI = 0.5 V ,
TA = 25°C
0.5 V
VREF2 VDD2 = 5.0 V, VVI = 2.5 V ,
TA = 25°C
2.5 V
Reference Vol tage
VREF3 VDD2 = 5.0 V, VVI = 4.5 V ,
TA = 25°C
4.5 V
∆VVO1 VDD2 = 5.0 V, VVI = 0.5 V,
TA = 25°C
±20 mV
∆VVO2 VDD2 = 5.0 V, VVI = 2.5 V,
TA = 25°C
±20 mV
Output Vol tage Deviati on
∆VVO3 VDD2 = 5.0 V, VVI = 4.5 V,
TA = 25°C
±20 mV
Logic Dynam ic Current Cons um ption IDD1 VDD1 = 5.0 V wi t h no loadNote 1.0 3.5 mA
Driver Dynamic Current Consumption I DD2 VDD2 = 5.0 V with no l oadNote 7.0 10.0 mA
Note fCLK = 15 MHz, fCX = 17 kHz.
★
Data Sheet S14606EJ1V0DS 11
µ
µ µ
µ
PD16780
A
Switching Characteristics (TA = –30 to +85°
°°
°C, VDD1 = 3.0 to 5.5 V, VDD2 = 5.0 V ± 0.5 V, VDD2 ≥
≥≥
≥ VDD1,
VSS1 = VSS2 = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
tPHL1 743nsStart Pulse Delay Time
tPLH1
CL = 20 pF
CLK → ST HL(STHR) 743ns
tPLH2 8
µ
s
tPLH3 16
µ
s
tPHL2 8
µ
s
Driver Output Del ay Time
tPHL3
VDD2 = 5.0 V
RL = 2 kΩ
CL = 25 pF x 2
16
µ
s
CI1 STHR(STHL), T A=25°C1020pF
CI2 C1,C2,C3, TA=25°C4060pF
Input Capaci tance
CI3 STHR(STHL),C1,C2,C3
excluded i nput, TA=25°C
715pF
Timing Requirement (TA = –30 to +85°
°°
°C, VDD1 = 3.0 to 5.5 V, VSS1 = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Clock Pulse Widt h PWCLK CLK1 to CLK350 ns
Clock Pulse High Period PWCLK(H) 15 ns
Clock Pulse Low Pe ri od PWCLK(L) 15 ns
Clock Delay Time tCL1-2
tCL2-3 16.6
PWCLK
2
ns
Start P ulse Setup Time tsetup 7ns
Start P ulse Setup Time thold 7ns
Start Pulse – CX Ti m e tSTH-CX 50 ns
CX Setup Tim e tCXsetup 1.0
µ
s
CX Hold Ti m e tCXhold 50 ns
CLK Stop Period tCLKstop Refer to 8. SWITHING CHARACTE RISTI CS
WAVEFORM.
Remark Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.
★
Data Sheet S14606EJ1V0DS
12
µ
µ µ
µ
PD16780
A
8. SWITCHING CHARACTERISTICS WAVEFORM (R,/L=H)
Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.
8.1 1-Phase simultaneous sampling
VDD1
2104014003991021011003210
tCLKstop : It is possible for the clock among this to stop.
VSS1
VDD1
VSS1
VDD1
VSS1
VDD1
VSS1
VDD1
VSS1
VDD1
VSS1
tPLH3
tCXsetup
INVALIDINVALID
tPHL1tPLH1
tholdtsetup
PWCLK
PWCLK(L)PWCLK(H)
tPLH1 tPHL1
S1 to S
3
S301 to
S
303
S298 to
S
300
S295 to
S
297
S7 to
S
9
S4 to S
6
S1 to S
3
S
1198
to
S
1200
S
1195
to
S
1197
tCXhold
tPLH2
tPHL2
Target Voltage ± 0.1 VDD1
Target Voltage ± 20 mV
tPHL3
CLK1
STHR
(1st Dr.)
C1 to C3
STHL
(1st Dr.)
STHL
(4th Dr.)
CX
Sn
(VOUT)
tSTH-CX
Data Sheet S14606EJ1V0DS 13
µ
µ µ
µ
PD16780
A
8.2 3-phase sequential sampling
VDD1
2104014003991021011003210
tCLKstop : It is possible for the clock among this to stop.
VSS1
VDD1
VSS1
VDD1
VSS1
VDD1
VSS1
VDD1
VSS1
VDD1
VSS1
tPLH3
tCXsetup
INVALIDINVALID
tPHL1tPLH1
tholdtsetup
PWCLK
PWCLK(L)PWCLK(H)
tPLH1 tPHL1
S
1
S
301
S
298
S
295
S
7
S
4
S
1
S
1198
S
1195
tCXhold
tPLH2
tPHL2
Target Voltage ± 0.1 VDD1
Target Voltage ± 20 mV
tPHL3
CLK1
STHR
(1st Dr.)
C1
STHL
(1st Dr.)
STHL
(4th Dr.)
CX
tSTH-CX
VDD1
2104014003991021011003210
VSS1
CLK2
VDD1
1040110210121
VSS1
CLK3
VDD1
VSS1
INVALIDINVALID S
2
S
302
S
5
S
2
C2
VDD1
VSS1
INVALIDINVALID S
3
S
303
S
300
S
297
S
6
S
3
S
1200
S
1197
C3
S
1196
S
1199
S
299
S
296
0100 399 400
Sn
(VOUT)
tCL1-2
tCL2-3
★
Data Sheet S14606EJ1V0DS
14
µ
µ µ
µ
PD16780
A
9. RECOMMENDED MOUNTING CONDITIONS
The following conditions must be met for mounting conditions of the
µ
PD16780A.
For more details, refer to the Semiconductor Device Mounting Technology Manual(C10535E).
Please consult with our sales offices in case other mounting process is used, or in case the mounting is done under
different conditions.
µ
PD16780AN-xxx : TCP(TAB Package)
Mounting Condition Mounting Met hod Condition
Soldering Heating tool 300 to 350°C, heating for 2 to 3 sec ; press ure 100g(per
solder)
Thermocompression
ACF
(Adhesive Conductive
Film)
Temporary bonding 70 t o 100°C ; pressure 3 to 8 kg/cm2; time 3 to 5
sec. Real bondi ng 165 to 180°C pressure 25 t o 45 kg/cm 2 time 30 to
40 secs (When using the anis otropy conduc tive fi l m S UM IZAC1003 of
Sumitomo Bakeli te, Ltd).
Caution To find out the detailed conditions for mounting the ACF part, please contact the ACF
manufacturing company. Be sure to avoid using two or more mounting methods at a time.
Data Sheet S14606EJ1V0DS 15
µ
µ µ
µ
PD16780
A
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
µ
µµ
µ
PD16780A
Reference Documents
NEC Semiconductor Device Reliability/Quality Control System(C10983E)
Quality Grades to NEC’s Semiconductor Devices(C11531E)
M8E 00. 4
The information in this document is current as of November, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document .
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
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agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
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and visual equipment, home electronic appliances, machine tools, personal electronic equipment
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systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
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The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
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(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
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•
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