EL7457CUZ-T13 - Intersil Corporation

FN7288.4

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

EL7457

40MHz Non-Inverting Quad CMOS Driver

The EL7457 is a high speed, non-inverting, quad CMOS

driver. It is capable of running at clock rates up to 40MHz

and features 2A peak drive capability and a nominal

on-resistance of just 3Ω. The EL7457 is ideal for driving

highly capacitive loads, such as storage and vertical clocks

in CCD applications. It is also well suited to ATE pin driving,

level-shifting, and clock-driving applications.

The EL7457 is capable of running from single or dual power

supplies while using ground referenced inputs. Each output

can be switched to either the high (VH) or low (VL) supply

pins, depending on the related input pin. The inputs are

compatible with both 3V and 5V CMOS and TTL logic. The

output enable (OE) pin can be used to put the outputs into a

high-impedance state. This is especially useful in CCD

applications, where the dr iver should be disabled during

power down.

The EL7457 also features very fast rise and fall times which

are matched to within 1ns. The propagation delay is also

matched between rising and fallin g edges to within 2ns.

The EL7457 is availa ble in 16-pin QSOP, 16-pin SO

(0.150"), and 16-pin QFN packages. All are specified for

operation over the full -40°C to +85°C temper ature range.

Pinouts

Features

• Clocking speeds up to 40MHz

• 4 channels

• 12ns tR/tF at 1000pF CLOAD

• 1ns rise and fall time match

• 1.5ns prop delay match

• Low quie scent current - <1mA

• Fast output enable functio n - 12ns

• Wide output voltage range

•8V ≥ VL ≥ -5V

•-2V ≤ VH ≤ 16.5V

• 2A peak drive

•3Ω on resistance

• Input level shifters

• TTL/CMOS input-compatible

• Pb-free (RoHS compliant)

Applications

• CCD drivers

• Digital cameras

• Pin drivers

• Clock/line drivers

• Ultrasound transducer drivers

• Ultrasonic and RF generators

• Level shifting

8 9

INB

GND

INC

IND

VS-

OUTD

INA

VS+

OUTA

OUTB

OUTC

THERMAL

PAD*

INA

INB

GND

INC

IND

VS+

OUTA

OUTB

OUTC

OUTD

VS-

EL7457

[16-PIN SO (0.150”),

QSOP (0.150”)]

TOP VIEW

EL7457

[16-PIN QFN (4X4MM)]

TOP VIEW

* THERMAL PAD CONNECTED

TO PIN 7 (VS-)

Data Sheet January 26, 2012

2FN7288.4

January 26, 2012

Ordering Information

PART NUMBER

(Notes 2, 3) PART

MARKING TEMP.

RANGE (°C) PACKAGE

(Pb-free) PKG.

DWG. #

EL7457CUZ 7457CUZ -40°C to +85°C 16 Ld QSOP (0.150”) MDP0040

EL7457CUZ-T13 (Note 1) 7457CUZ -40°C to +85°C 16 Ld QSOP (0.150”) MDP0040

EL7457CUZ-T7 (Note 1) 7457CUZ -40°C to +85°C 16 Ld QSOP (0.150”) MDP0040

EL7457CUZ-T7A (Note 1) 7457CUZ -40°C to +85°C 16 Ld QSOP (0.150”) MDP0040

EL7457CSZ EL7457CSZ -40°C to +85°C 16 Ld SO (0.150”) MDP0027

EL7457CSZ-T13 (Note 1) EL7457CSZ -40°C to +85°C 16 Ld SO (0.150”) MDP0027

EL7457CSZ-T7 (Note 1) EL7457CSZ -40°C to +85°C 16 Ld SO (0.150”) MDP0027

EL7457CSZ-T7A (Note 1) EL7457CSZ -40°C to +85°C 16 Ld SO (0.150”) MDP0027

EL7457CLZ 7457CLZ -40°C to +85°C 16 Ld QFN (4x4mm) L16.4X4H

EL7457CLZ-T13 (Note 1) 7457CLZ -40°C to +85°C 16 Ld QFN (4x4mm) L16.4X4H

EL7457CLZ-T7 (Note 1) 7457CLZ -40°C to +85°C 16 Ld QFN (4x4mm) L16.4X4H

EL7457CLZ-T7A (Note 1) 7457CLZ -40°C to +85°C 16 Ld QFN (4x4mm) L16.4X4H

NOTES:

1. Please refer to TB347 for details on reel specifications.

2. Th ese Intersil Pb-free pla stic packaged pr oducts emplo y special Pb-free mat erial sets, mo lding compounds/di e attach mater ials, and 100% matte tin

plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free

products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for EL7457. For more information on MSL please see tech brief TB363.

EL7457

3FN7288.4

January 26, 2012

Absolute Maximum Ratings (TA = 25°C) Thermal Information

Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . .+18V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .VS- -0.3V, VS+ +0.3V

Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C

Thermal Resistance θJA (°C/W) θJC (°C/W)

16 Ld QFN (Notes 4, 5) . . . . . . . . . . . . 43 5

16 Ld SOIC (Notes 6, 7). . . . . . . . . . . . 73 45

16 Ld QSOP (Note 6). . . . . . . . . . . . . . 112 N/A

Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C

Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves

Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

Tech Brief TB379.

5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.

6. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

7. For θJC, the “case temp” location is taken at the package top center.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests

are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA

Electrical Specifications VS+ = +5V, VS- = -5V, VH = +5V, VL = -5V, TA = 25°C, unless otherwise specified.

PARAMETER DESCRIPTION CONDITION MIN

(Note 8) TYP MAX

(Note 8) UNIT

INPUT

VIH Logic “1” Input Voltage 2.0 V

IIH Logic “1” Input Current VIH = 5V 0.1 10 µA

VIL Logic “0” Input Voltage 0.8 V

IIL Logic “0” Input Current VIL = 0V 0.1 10 µA

CIN Input Capacitance 3.5 pF

RIN Input Resistance 50 MΩ

OUTPUT

ROH ON Resistance VH to OUTx IOUT = -100mA 4.5 6 Ω

ROL ON Resistance VL to OUTx IOUT = +100mA 4 6 Ω

ILEAK Output Leakage Current VH = VS+, VL = VS-0.110µA

IPK Peak Output Current Source 2.0 A

Sink 2.0 A

POWER SUPPLY

ISPower Supply Current Inputs = VS+0.51.5mA

SWITCHING CHARACTERISTICS

tRRise Time CL = 1000pF 13.5 ns

tFFall Time CL = 1000pF 13 ns

tRFΔtR, tF Mismatch CL = 1000pF 0.5 ns

tD+ Turn-Off Delay Time CL = 1000pF 12.5 ns

tD- Turn-On Delay Time CL = 1000pF 14.5 ns

tDD tD-1 - tD-2 Mismatch CL = 1000pF 2 ns

tENABLE Enable Delay Time 12 ns

EL7457

4FN7288.4

January 26, 2012

tDISABLE Disable Delay Time 12 ns

Electrical Specifications VS+ = +5V, VS- = -5V, VH = +5V, VL = -5V, TA = 25°C, unless otherwise specified.

PARAMETER DESCRIPTION CONDITION MIN

(Note 8) TYP MAX

(Note 8) UNIT

Electrical Specifications VS+ = +15V, VS- = 0V, VH = +15V, VL = 0V, TA = 25°C, unless otherwise specified

PARAMETER DESCRIPTION CONDITION MIN

(Note 8) TYP MAX

(Note 8) UNIT

INPUT

VIH Logic “1” Input Voltage 2.4 V

IIH Logic “1” Input Current VIH = 5V 0.1 10 µA

VIL Logic “0” Input Voltage 0.8 V

IIL Logic “0” Input Current VIL = 0V 0.1 10 µA

CIN Input Capacitance 3.5 pF

RIN Input Resistance 50 MΩ

OUTPUT

ROH ON Resistance VH to OUT IOUT = -100mA 3.5 5 Ω

ROL ON Resistance VL to OUT IOUT = +100mA 3 5 Ω

ILEAK Output Leakage Current VH = VS+, VL = VS-0.110µA

IPK Peak Output Current Source 2.0 A

Sink 2.0 A

POWER SUPPLY

ISPower Supply Current Inputs = VS+0.82mA

SWITCHING CHARACTERISTICS

tRRise Time CL = 1000pF 11 ns

tFFall Time CL = 1000pF 12 ns

tRFΔtR, tF Mismatch CL = 1000pF 1 ns

tD+ Turn-Off Delay Time CL = 1000pF 11.5 ns

tD- Turn-On Delay Time CL = 1000pF 13 ns

tDD tD-1 - tD-2 Mismatch CL = 1000pF 1.5 ns

tENABLE Enable Delay Time 12 ns

tDISABLE Disable Delay Time 12 ns

NOTE:

8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

EL7457

5FN7288.4

January 26, 2012

Typical Performance Curves

FIGURE 1. SWITCH THRESHOLD vs SUPPLY VOLTAGE FIGURE 2. QUIESCENT SUPPLY CURRENT vs SUPPLY

VOLTAGE

FIGURE 3. “ON” RESISTANCE vs SUPPLY VOLTAGE FIGURE 4. RISE/FALL TIME vs SUPPLY VOLTAGE

FIGURE 5. RISE/FALL TIME vs TEMPERATURE FIGURE 6. PROPAGATION DELAY vs SUPPLY VOLTAGE

T=25°C HIGH LIMIT=2.4V

LOW LIMIT=0.8V

HYSTERESIS

1.8

1.6

1.4

1.2

15 7 10 12 15

SUPPLY VOLTAGE (V)

INPUT VOLTAGE (V)

T=25°C

ALL INPUTS=0

ALL INPUTS=VS+

1.6

1.2

0.8

05 7 10 12 15

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (V)

0.4

IOUT=100mA

T=25°C

VL TO OUT

25 7 10 12 15

SUPPLY VOLTAGE (V)

“ON” RESISTANCE (Ω)

VH TO OUT

CL=1000pF

T=25°C

55 7 10 12 15

SUPPLY VOLTAGE (V)

RISE/FALL TIME (ns)

CL=1000pF

VS+=15V

-50 0 50 100 125

TEMPERATURE (°C)

RISE/FALL TIME (ns)

25 75-25

CL=1000pF

551015

SUPPLY VOLTAGE (V)

DELAY TIME (ns)

127

tD2

tD1

EL7457

6FN7288.4

January 26, 2012

FIGURE 7. PROPAGATION DELAY vs TEMPERATURE FIGURE 8. RISE/FALL TIME vs LOAD

FIGURE 9. SUPPLY CURRENT PER CHANNEL vs CAPACITIVE LOAD

Typical Performance Curves (Continued)

CL=1000pF

VS+=15V

-50 0 50 100 125

TEMPERATURE (°C)

DELAY TIME (ns)

25 75-25

tD2

tD1

VS+=15V

140

120

100

100 1K 4.7K 10K

LOAD CAPACITANCE (pF)

RISE/FALL TIME (ns)

tFtR

2.2K470

VS+=VH=10V

VS-=VL=0V

f=100kHz

100 1K 10K

LOAD CAPACITANCE (pF)

SUPPLY CURRENT (mA)

EL7457

7FN7288.4

January 26, 2012

Timing Diagram

Standard Test Configuration (CS/CU)

TABLE 1. NOMINAL OPERATING VOLTAGE RANGE

PIN MIN MAX

VS+ to VS- 5V 16.5V

VS- to GND -5V 0V

VHVS- + 2.5V VS+

VLVS-V

S+

VH to VL0V 16.5V

VL to VS-0V 8V

90%

10%

OUTPUT

2.5V

INPUT

tD+

tD-

8 9

4.7µF 0.1µF

INA

INB

INC

IND

10kΩ

VS+

VS-

OUTD

OUTC

OUTB

OUTA

VS+

0.1µF 4.7µF

1000pF

0.1µF 4.7µF

1000pF

0.1µF 4.7µF

EL7457

8FN7288.4

January 26, 2012

Pin Descriptions

16-PIN

QSOP (0.150”),

SO (0.150”) 16-PIN QFN

(4x4mm) NAME FUNCTION EQUIVALENT CIRCUIT

1 15 INA Input channel A

CIRCUIT 1

2 16 OE Output Enable (Reference Circuit 1)

3 1 INB Input channel B (Reference Circuit 1)

4 2, 3 VL Low voltage input pin

5 4 GND Input logic ground

6, 13 NC No connection

7 5 INC Input channel C (Reference Circuit 1)

8 6 IND Input channel D (Reference Circuit 1)

9 7 VS- Negative supply voltage

10 8 OUTD Output channel D

CIRCUIT 2

11 9 OUTC Output channel C (Reference Circuit 2)

12 10, 11 VH High voltage input pin

14 12 OUTB Output channel B (Reference Circuit 2)

15 13 OUTA Output channel A (Reference Circuit 2)

16 14 VS+ Positive supply voltage

VS-VS-

VS+

INPUT

VS-

VS+

OUTPUT

VS-

EL7457

9FN7288.4

January 26, 2012

Block Diagram

Applications Information

Product Descr iption

The EL7457 is a high performance 40MHz high speed quad

driver. Each channel of the EL7457 consi sts of a single

P-channel high side driver and a single N-channel low side

driver . These 3Ω devices will pull the output (OUTX) to either

the high or low voltage, on VH and VL respectively,

depending on the input logic signal (INX). It should be noted

that there is only one set of high and low voltage pins.

A common output enable (OE) pin is available on the

EL7457. This pin, when pulled low will pu t all outputs in to

the high impedance state.

The EL7457 is available in 16-pin SO (0.150"), 16-pin

QSOP, and ultra-small 16-pin QFN packages. The relevant

package should be chosen depending on the calculated

power dissipation.

Supply Voltage Range and Input Compatibility

The EL7457 is designed for operation on supplies from 5V to

15V with 1 0% toleran ce (i.e. 4.5V to 18V). The t able on page

6 shows the specifications for the relationship between the

VS+, VS-, VH, VL, and GND pins. The EL7457 does not

contain a true analog switch and therefore VL should always

be less than VH.

All input pins are compatible with both 3V and 5V CMOS

signals With a positive supply (VS+) of 5V, the EL7457 is

also compatible with TTL inputs.

Power Supply Bypassing

When using the EL7457, it is very important to use adequate

power supply bypassing. The high switching currents

developed by the EL7457 necessitate the use of a bypass

capacitor on both the positive and negative supplies. It is

recommended that a 4.7µF tantalum capacitor be used in

parallel with a 0.1µF low-inductance ceramic MLC capacitor.

These should be placed as close to the supply pins as

possible. It is also recommended that the VH and VL pins

have some level of bypassing, especially if the EL7457 is

driving highly capacitive loads.

Power Dissipation Calculation

When switching at high speeds, or driving heavy loads, the

EL7457 drive capability is limited by the rise in die

temperature brought about by internal power dissipation. For

reliable operation die temperature must be kept below

TJMAX (125°C). It is necessary to calculate the power

dissipation for a given application prior to selecting package

type.

Power dissipation may be calculated:

where:

VS is the total power supply to the EL7457 (from VS+ to

VS-)

VOUT is the swing on the ou tp ut (VH - VL)

CL is the load capacitance

CINT is the internal load capacitance (80pF max)

IS is the quiescent supply current (3mA max)

f is frequency

Having obtained the application’s power dissipation, the

maximum junction temperature can be calculated:

where:

TJMAX is the maximum junction temperature (125 °C)

TMAX is the maximum ambient operating temperature

PD is the power dissipation calculated above

θJA is the thermal resistance, junction to ambient, of the

application (package + PCB combination). Refer to the

Package Power Dissipation curves on page 6.

3-STATE

CONTROL

LEVEL

SHIFTER OUTPUT

INPUT

VS+

GND

VS-

PD VSIS

×()CINT VS

×f×()CLVOUT

×f×()+

∑

+= (EQ. 1)

TJMAX TMAX ΘJA PD×+= (EQ. 2)

EL7457

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third pa rties which may result

from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of Intersil or its subsidiari es.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7288.4

January 26, 2012

EL7457

Quarter Size Outline Plastic Packages Family (QSOP)

0.010 CAB

SEATING

PLANE

DETAIL X

EE1

1(N/2)

(N/2)+1

PIN #1

I.D. MARK

0.004 C

SEE DETAIL "X"

4°±4°

GAUGE

PLANE

0.010

0.007 CAB

MDP0040

QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY

SYMBOL

INCHES

TOLERANCE NOTESQSOP16 QSOP24 QSOP28

A 0.068 0.068 0.068 Max. -

A1 0.006 0.006 0.006 ±0.002 -

A2 0.056 0.056 0.056 ±0.004 -

b 0.010 0.010 0.010 ±0.002 -

c 0.008 0.008 0.008 ±0.001 -

D 0.193 0.341 0.390 ±0.004 1, 3

E 0.236 0.236 0.236 ±0.008 -

E1 0.154 0.154 0.154 ±0.004 2, 3

e 0.025 0.025 0.025 Basic -

L 0.025 0.025 0.025 ±0.009 -

L1 0.041 0.041 0.041 Basic -

N 16 24 28 Reference -

Rev. F 2/07

NOTES:

1. Plastic or metal protrusions of 0.006” maximum per side are not

included.

2. Plastic interlead protrusions of 0.010” maximum per side are not

included.

3. Dimensions “D” and “E1” are measur ed at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

11 FN7288.4

January 26, 2012

EL7457

Small Outline Package Family (SO)

GAUGE

PLANE

A1 L

DETAIL X 4° ±4°

SEATING

PLANE

0.010 BMCA

0.004 C

0.010 BMCA

(N/2)

NN (N/2)+1

PIN #1

I.D. MARK

h X 45°

SEE DETAIL “X”

0.010

MDP0027

SMALL OUTLINE PACKAGE FAMILY (SO)

SYMBOL

INCHES

TOLERANCE NOTESSO-8 SO-14

SO16

(0.150”)

SO16 (0.300”)

(SOL-16)

SO20

(SOL-20)

SO24

(SOL-24)

SO28

(SOL-28)

A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -

A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 -

A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -

b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -

c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 -

D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3

E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -

E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3

e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -

L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -

L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -

h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -

N 8 14 16 16 20 24 28 Reference -

Rev. M 2/07

NOTES:

1. Plastic or metal protrusions of 0.006” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions “D” and “E1” are measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994

12 FN7288.4

January 26, 2012

EL7457

Package Outline Drawing

L16.4x4H

16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 0, 1/12

located within the zone indicated. The pin #1 identifier may be

Unless otherwise specified, tolerance : Decimal ± 0.05

Tiebar shown (if present) is a non-functional feature.

The configuration of the pin #1 identifier is optional, but must be

between 0.15mm and 0.30mm from the terminal tip.

Dimension applies to the metallized terminal and is measured

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to ASME Y14.5m-1994.

either a mold or mark feature.

Dimensions are in millimeters.1.

NOTES:

BOTTOM VIEW

DETAIL "X"

SIDE VIEW

TYPICAL RECOMMENDED LAND PATTERN

TOP VI EW

SEE DETAIL "X"

0.30 ±0.05

BASE PLANE

PIN #1

( 3 . 6 TYP )

(12x0.65)

(16x0.30) 0 . 20 REF

+0.03/-0.02

0.10 CM

INDEX AREA

(4X) 0.15

PIN 1

4.00

0.65

12X

4X 1.95

SEATING PLANE

0.10 C

16x 0.550±0.05

2.40

( 2.40)

0.90±0.10

(16x0.75)

2.40

INDEX AREA