1
®
FN6703.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6745A
Improved Bridge Controller with Precision
Dead Time Control
The ISL6745A is a low-cost double-ended voltage-mode
PWM controller designed for half-bridge and full-b ri dge
power supplies and line-regulated bus converters. It
provides precise control of switching frequency, adjustable
soft-start, and overcurrent shutdown. In addition, the
ISL6745A allows for accurate adjustment of MOSFET
non-overlap time (“deadtime”) with deadtimes as low as
35ns, allowing power engineers to optimize the efficiency of
open-loop bus converters. The ISL6745A also includes a
control voltage input for closed-loop PWM and line voltage
feed-forward functions. The ISL6745A is identical to the
ISL6745, but is optimized for higher noi se environments.
Low start-up and operating currents allow for easy biasing in
both AC/DC and DC/DC applications. This advanced
BiCMOS design also features adjustable switching
frequency up to 1MHz, 1A FET drivers, and very low
propagation delays for a fast response to overcurrent faults.
The ISL6745A is available in a space-saving MSOP-10
package and is guaranteed to meet rated specifications over
a wide -40°C to +105°C temperature range.
Features
• Precision Duty Cycle and Deadtime Control
• 100µA Start-up Current
• Adjustable Delayed Overcurrent Shutdown and Re-Start
• Adjustable Oscillator Frequency Up to 2MHz
• 1A MOSFET Gate Drivers
• Adjustable Soft-Start
• Internal Over-Temperature Protection
• 35ns Control to Output Propagation Delay
• Small Size and Minimal External Comp onent Count
• Input Undervoltage Protection
• Pb-Free (RoHS Compliant)
Applications
• Half-bridge Converters
• Full-bridge Converters
• Line-regulated Bus Converters
• AC/DC Power Supplies
• Telecom, Datacom, and File Server Power
Ordering Information
PART
NUMBER
(Note) PART
MARKING
TEMP.
RANGE
(°C) PACKAGE
(Pb-Free) PKG.
DWG. #
ISL6745AAUZ* 6745A -40 to +105 10 Ld MSOP M10.118
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
Pinout ISL6745A
(10 LD MSOP)
TOP VIEW
SS 1
RTD
VERR
CS
CT GND
OUTA
OUTB
VDDP
VDD
2
3
4
56
7
8
9
10
Data Sheet September 11, 2008
2FN6703.1
September 11, 2008
ISL6745A
VBIAS
5.00V
GND
VDD VBIAS
UVLO
RTD
0.8V
PEAK
VALLEY
CT
IDCH
ON
CLK
RESET
DOMINANT
FL
OUTA
OUTB
CS
PWM COMPARATOR
0.6V
OC DETECT
VBIAS
PWM LATCH
SET
DOMINANT
ON
OC LATCH
3.9V
0.27VSS LOW
SS
FAULT LATCH
SET DOMINANT
FL
INTERNAL
OT SHUT DO WN
130°C - 150°C
BG
VBIAS
VBIAS UV
BG
PWM TOGGLE
+
-
+
-
+
-
+
-
+
-
+
-
+
-
IRTD
I DCH= 55 x
IRTD
S
R
Q
Q
S
R
Q
Q
S
R
Q
Q
S
R
Q
Q
TQ
Q
Q
Q
50µs
RETRIGGERABLE
ONE SHOT
SS
4.65V ↓ 4.80V ↑
SS CLAM P
4.0V
+
-+
-
VBIAS
SS CHARGED
ON
VBIAS
160µA
70µA
15µA
VDDP
2.8V
2.0V
0.8 SS
CT
0.8
VERR
+
-
-
VBIA
S15µA
Internal Architecture
3FN6703.1
September 11, 2008
ISL6745A
Typical Application - Telecom DC/DC Converter
VIN+
VIN-
RETURN
T2
CR4
R3
C4 C5
R1
Q3
R5
36V TO 75V
(100V M ax.)
U1
ISL6745A
CR3
L1
T1
R2
VR1
+ VOU T
C10
C1
Q1
Q2
C2
C2 C3
CR1
CR2
+
CS
CT
OUTB
OUTA
GND
RTD
SS
1
2
3
4
56
7
8
VDD
VERR
VDDP 9
10
HS
LI
HI
HB
VDD
1
2
3
4 5
6
LO
HO
VSS 7
8
U2
ISL2100A
U3
C7
R6
U4
TL431
R10
R11
VR2
R4
R7
R8
R9
C6
C8
C9
4FN6703.1
September 11, 2008
Absolute Maximum Ratings Thermal Information
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . GND - 0.3V to +20.0V
OUTA, OUTB. . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VDD
Signal Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 5V
Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1A
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . 9V to 16V
Thermal Resistance (Typical, Note 1) θJA (°C/W)
10 Lead MSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Maximum Junction Temperature . . . . . . . . . . . . . . .-55°C to +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. All voltages are to be measured with respect to GND, unless otherwise specified.
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram on page 2 and Typical
Application schematic on page 3. 9V < VDD < 16V, RTD = 51.1kΩ, CT = 470pF, TA = -40°C to +105°C, Typical
values are at T A = +25°C; Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not production tested.
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
SUPPLY VOLTAGE
Start-Up Current, IDD VDD< START Threshold - - 175 µA
Operating Current, IDD COUTA,B = 1nF - 5 8.5 mA
UVLO START Threshold 5.9 6.3 6.6 V
UVLO STOP Threshold 5.3 5.7 6.3 V
Hysteresis -0.6- V
CURRENT SENSE
Current Limit Threshold 0.55 0.6 0.65 V
CS to OUT Delay (Note 3) - 35 - ns
CS Sink Current 810-mA
Input Bias Current -1 - 1 µA
PULSE WIDTH MODULATOR
Minimum Duty Cycle VERROR < CT Offset - - 0 %
Maximum Duty Cycle CT = 470pF, RTD = 51.1kΩ-94-%
CT = 470pF, RTD = 1.1kΩ (Note 3) - 99 - %
VERR to PWM Comparator Input Gain - 0.8 - V/V
CT to PWM Comparator Input Gain (Note 3) - 1 - V/V
SS to PWM Comparator Input Gain (Note 3) - 0.8 - V/V
OSCILLATOR
Charge Current TA = +25°C 143 156 170 µA
RTD Voltage 1.925 2 2.075 V
Discharge Current Gain 45 - 65 µA/µA
CT Valley Voltage 0.75 0.8 0.85 V
CT Peak Voltage 2.70 2.80 2.90 V
ISL6745A
5FN6703.1
September 11, 2008
SOFT-START
Net Charging Current 45 - 68 µA
SS Clamp Voltage 3.8 4.0 4.2 V
Overcurrent Shutdown Threshold Voltage (Note 3) - 3.9 - V
Overcurrent Discharge Current 12 15 23 µA
Reset Threshold Voltage 0.25 0.27 0.31 V
OUTPUT
High Level Output Voltage (VOH) VDD - VOUTA or VOUTB,
IOUT = -100mA -0.52.0V
Low Level Output Voltage (VOL) IOUT = 100mA - 0.5 1.0 V
Rise Time CGATE = 1nF, VDD = 12V - 17 60 ns
Fall Time CGATE = 1nF, VDD = 12V - 20 60 ns
THERMAL PROTECTION
Thermal Shutdown (Note 3) - 145 - °C
Thermal Shutdown Clear (Note 3) - 130 - °C
Hysteresis, Internal Protection (Note 3) - 15 - °C
NOTES:
3. Limits established by characterization and are not production tested.
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram on page 2 and Typical
Application schematic on page 3. 9V < VDD < 16V, RTD = 51.1kΩ, CT = 470pF, TA = -40°C to +105°C, Typical
values are at T A = +25°C; Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not production tested. (Continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
ISL6745A
6FN6703.1
September 11, 2008
Typical Performance Curves
FIGURE 1. OSCILLATOR CT DISCHARGE C URRENT GAIN FIGURE 2. DEADTIME vs CAPACITANCE
FIGURE 3. CAP ACITANCE vs OSCILLA T OR FREQUENCY
(RTD = 49.9kΩ)FIGURE 4. CHARGE CURRENT vs TEMPERATURE
FIGURE 5. TIMING CAPACITOR VOLTAGE vs RTD
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10
40
45
50
55
60
65
RTD CURRENT (mA)
CT DISCHARGE CURRENT GAIN
10 20 30 40 50 60 70 80 90 100
10
100
1-103
1-104
RTD (kΩ)
DEADTIME (ns)
CT = 270pF
CT = 100pF
CT = 470pF
CT = 1000pF
CT = 680pF
100 200 300 400 500 600 700 800 900 1k
0
100
200
300
400
500
600
CT (pF)
OSCILLATOR FREQUENCY (kHz)
-40 -25 -10 5 35 50 65 80 95 110
0.95
0.97
0.98
0.99
1.01
1.03
TEMPERATURE (°C)
NORMALIZED CHARGING CURRENT
1.02
1.00
20
0.96
0 102030 5060708090100
0.98
1.00
1.02
1.03
1.05
1.07
RTD (kΩ)
NORMALIZED VOLTAGE
1.06
1.04
40
0.99
1.01
ISL6745A
7FN6703.1
September 11, 2008
Pin Descriptions
VDD - VDD is the power connection for the IC. To optimize
noise immunity, bypass VDD to GND with a ceramic
capacitor as close to the VDD and GND pins as possible.
The total supply current, IDD, will be depende nt on the load
applied to outputs OUTA and OUTB. Total IDD current is the
sum of the quiescent current and the average output current.
Knowing the operating frequency, FSW, and the output
loading capacitance charge, Q, per output, the average
output current can be calculated from Equation 1:
RTD - This is the oscillator timing capacitor discharge current
control pin. A resistor is connected between this pin and
GND. The current flowing through the resistor determines
the magnitude of the disch arge current. The discharge
current is nominally 55x this current. The PWM deadtime is
determined by the timing capacitor discharge duration.
CT - The oscillator timing capacitor is connected between
this pin and GND.
CS - This is the input to the overcurrent protection comparator.
The overcurrent comparator threshold is set at 0.600V nominal.
The CS pin is shorted to GND at the end of each switching
cycle. Depending on the current sensing source impedance, a
series input resistor may be required due to the delay between
the internal clock and the external power switch.
Exceeding the overcurrent th reshold will start a delayed
shutdown sequence. Once an overcurrent condition is
detected, the soft-start charge current source is disabled.
The soft-start capacitor begins discharging through a 15µA
current source, and if it discharges to less than 3.9V
(Sustained Overcurrent Threshold), a shutdown condition
occurs and the OUTA and OUTB outputs are forced low.
When the soft-start voltage reaches 0.27V (Reset
Threshold) a soft-st art cycle begins.
If the overcurrent condition ceases, and then an additional
50µs period elapses before the shutdown threshold is
reached, no shutdown occurs. The SS charging current is
re-enabled and the soft-start voltage is allowed to recover.
GND - Reference and power ground for all functions on this
device. Due to high peak currents and high frequency
operation, a low impedance layout is necessary. Ground
planes and short traces are highly recommended.
OUTA and OUTB - Alternate half cycle output stages. Each
output is capable of 1A peak currents for driving power
MOSFETs or MOSFET drivers. Each output provides very
low impedance to overshoot and undershoo t.
SS - Connect the soft-st art timing capacitor between this pin
and GND to control the duration of sof t -st art. The val ue of th e
capacitor determines the rate of increase of the duty cycle
during start-up, con trols the overcurrent shutdown delay, and
the overcurrent and short circuit hi ccup rest art period .
VERR - The inverting input of the PWM comparator. The
error voltage is applied to this pin to control the duty cycle.
Increasing the signal level increases th e duty cycle. Th e
node may be driven with an external error amplifier or an
opto-coupler.
VDDP - VDDP is the separate collector supply to the gate
drive. Having a separate VDDP pin helps isolate the analog
circuitry from the high power gate drive noise.
Functional Description
Features
The ISL6745A PWM is an excellent choice for low cost
bridge topologies for applications requiring accurate
frequency and deadtime control. Among its many features
are 1A FET drivers, adjustable soft-start, overcurrent
protection and internal thermal protection, allowing a highly
flexible design with minimal external compon ents.
Oscillator
The ISL6745A has an oscillator with a frequency range to
2MHz, programmable using a resistor RTD and capacitor CT.
The switching period may be considered to be the sum of
the timing capacitor charge and discharge durations. The
charge duration is determined by CT and the internal current
source (assumed to be 160µA in the formula). The discharge
duration is determined by RTD and CT.
where TC and TD are the approximate charge and discharge
times, respectively, TOSC is the oscillator free running
period, and FOSC is the oscillator frequency. One output
switching cycle requires two oscillator cycles. The actual
times will be slightly longer than calculated due to internal
propagation delays of approximately 5ns/transition. This
delay adds directly to the switching duration, and also
causes overshoot of the timing capacitor peak and valley
voltage thresholds, effectively increasing the peak-to-peak
voltage on the timing capacitor. Additionally, if very low
charge and discharge currents are used, there will be an
increased error due to the input impedance at the CT pin.
The above formulae help with the estimation of the
frequency. Practically, effects like stray capacitances that
affect the overall CT capacitance, variation in RTD voltage
and charge current over-temperature, etc. exist, and are
best evaluated in-circuit. Equation 2 follows from the basic
capacitor current equation, . In this case, with
(EQ. 1)
IOUT 2QF
SW
••=A
TC1.25 4
×10 CT
•≈ s(EQ. 2)
TD1
CTDisch eCurrentGainarg
-----------------------------------------------------------------------------RTD
•CT
•≈ s(EQ. 3)
TOSC TCTD
+1
FOSC
----------------
== s(EQ. 4)
iCtd
dV
×=
ISL6745A
8FN6703.1
September 11, 2008
variation in dV with RTD (Figure 5), and in charge current
(Figure 4), results from Equation 2 would differ from the
calculated frequency. The typical performance curves may
be used as a tool along with the previous equations as a
more accurate tool to estimate the operating frequency more
accurately.
The maximum duty cycle, D, and deadtime, DT, can be
calculated from:
Soft-Start Operation
The ISL6745A features a soft-start using an external
capacitor in conjunction with an internal current source.
Soft-start reduces stresses and surge currents during
start-up.
The oscillator capacitor signal, CT, is compared to the
soft-st art voltage, SS, in the SS comp arator which drives the
PWM latch. While the SS voltage is less than 3.5V, duty
cycle is limited. The output pulse width increases as the
soft-start capacitor voltage increases up to 3.5V. This has
the effect of increasing the duty cycle from zero to the
maximum pulse width during the soft-start period. When the
soft-start voltage exceeds 3.5V, so ft-start is completed.
Soft-start occurs during start-up and af ter recovery from an
overcurrent shut down. The soft-st a rt volt age is clamped to 4V.
Gate Drive
The ISL6745A is capable of sourcing and sinkin g 1A peak
current, and may also be used in conjunction with a
MOSFET driver such as the ISL6700 for level shifting. To
limit the peak current through the IC, an external resistor
may be placed between the totem-pole output of the IC
(OUTA or OUTB pin) and the gate of the MOSFET. This
small series resistor also damp s any oscillations caused by
the resonant tank of the parasitic inductances in the traces of
the board and the FET ’s input capacitance.
Overcurrent Operation
Overcurrent delayed shutdown is enabled once the soft-start
cycle is complete. If an overcurrent condition is detected, the
soft-start charging current source is disabled and the
soft-start capacitor is allowed to discharge through a 15µA
source. At the same time a 50µs retriggerable one-shot timer
is activated. It remains active for 50µs after the overcurrent
condition ceases. If the soft-start capacitor discharges to
3.9V, the output is disabled. This state continues until the
soft-start voltage reaches 270mV, at which time a new
soft-start cycle is initiated. If the overcurrent condition stops
at least 50µs prior to the soft-start voltage reaching 3.9V, the
soft-start charging currents revert to normal operation and
the soft-start voltage is allowed to recover.
Thermal Protection
An internal temperature sensor protects the device should
the junction temperature excee d +14 5°C. There is
approximately +15°C of hysteresis.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. VDD should
be bypassed directly to GND with good high frequency
capacitance.
DT
CTOSC
⁄=(EQ. 5)
DT 1 D–()TOSC
⋅=s(EQ. 6)
ISL6745A
9
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent right s of Int ersi l or it s sub sidi aries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6703.1
September 11, 2008
ISL6745AISL6745A
Mini Small Outline Plastic Packages (MSOP)
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums and to be determined at Datum plane
.
11. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only
L
0.25
(0.010)
L1
R1
R
4X θ
4X θ
GAUGE
PLANE
SEATING
PLANE
EE1
N
12
TOP VIEW
INDEX
AREA
-C-
-B-
0.20 (0.008) ABC
SEATING
PLANE
0.20 (0.008) C
0.10 (0.004) C
-A-
-H-
SIDE VIEW
b
e
D
A
A1
A2
-B-
END VIEW
0.20 (0.008) CD
E1
C
L
C
a
- H -
-A - - B -
- H -
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.037 0.043 0.94 1.10 -
A1 0.002 0.006 0.05 0.15 -
A2 0.030 0.037 0.75 0.95 -
b 0.007 0.011 0.18 0.27 9
c 0.004 0.008 0.09 0.20 -
D 0.116 0.120 2.95 3.05 3
E1 0.116 0.120 2.95 3.05 4
e 0.020 BSC 0.50 BSC -
E 0.187 0.199 4.75 5.05 -
L 0.016 0.028 0.40 0.70 6
L1 0.037 REF 0.95 REF -
N10 107
R 0.003 - 0.07 - -
R1 0.003 - 0.07 - -
5o15o5o15o-
α0o6o0o6o-
Rev. 0 12/02
θ
