Features High speed tsa = 25 ns @ CMOS for optimum speed/power e Low active power 825 mW @ Low standby power 165mW e Automatic power-down when deselected @ TTL-compatible inputs and outputs 9 SEMICONDUCTOR WBE D Ml 2549662 G006300 & Emcyp TUCIIOS5 _- PRELIMINARY CY7C107 Functional Description The CY7C107 is a high-performance CMOS static RAM organized as 1,048,576 words by 1 bit. Easy memory expansion is provided by an active LOW chip enable (CE) and three-state drivers. The device has an automatic power-down feature that reduces power consumption by more than 70% when deselected. Writing to the device is accomplished by taking chip enable (CE) and write enable (WE) inputs LOW. Data on the input pin (Dyy) is written into the memory location specified on the address pins (Ag through A1g). 1M x 1 Static R/W RAM Reading from the device is accomplished by taking chip enable (CE) LOW while write enable (WE) remains HIGH. Under these conditions, the contents of the memory loca- tion specified by the address pins will appear on the data output (Dour) pin. The output pin (Dour) is placed in a high- impedance state when the device is dese- lected (CE HIGH) or during a write opera- tion (CE and WE LOW). The CY7C107 is available in 32-pin leadless chip carriers and standard 28-pin, 400-mil- wide DIPs and SOJs. Logic Block Diagram <I Ow INPUT BUFFER Ao Ay & Az > 8 A a 512 x 2048 Ae ARRAY D Am 2 or Ar as POWER BecoDER | foot Le BRRRRERRRRE feregzegres WE <eececi ee ecgeg Ct071 Pin Configurations DIP/SOJ Top View APS PSS FP KF IFS F c107-3 BT PREVI TEE 107-2 Selection Guide Time (ns Current (mA) Maximum Current (mA) 710725 25 Commercial Military 2-38 71107-35 7C10745 45 125 125CYPRESS SEMICONDUCTOR Bey ree J+46-23-05 nN CY7C107 Sa SEMICONDUCTOR Maximum Ratings ~ (Abovewhich the useful life maybe impaired. Foruserguidelines, Static Discharge Voltage ...........- Su neeeneeees >2001V not tested.) (per MIL-STD-883, Method 3015} : Storage Temperature .....cc.eeeeeee 65Cto +150C = Latch UpCurrent .......-.-. eee seceeeeserees >200 mA Ambient Temperaturewith : PowerApplied vi..ccsssecesseceeeeee ~55Cto +125C Operating Range i YL Ambient . Supply Voltage on Vcc Relative toGND[ . 0.5V to +7.0V Range Temperaturel2I Veo DC Voltage Applied to Outputs in HighZ States. sevetevesasesene OSV to 7.0V Commercial OCto +70C SV = 10% DC Input Voltagel] ....., beeneeneeas we. O05Vto +7.0V Military ~ 55C to +125C 5V + 10% Current into Outputs (Low) ......... cee eeeeees vee 20mMA Electrical Characteristics!3] Overthe Operating Range 71107-25 7C10735 7C107~45 Parameters Description Test Conditions Min. | Max. | Min. | Max. | Min. | Max. | Units Vor OutputHIGH Voltage | Voc = Min., lon = 4.0mA 2.4 24 24 |. Vv Vo. Output LOW Voltage | Vcc = Min., Io, = 8.0 mA 0.4 0.4 0.4 v Vier Input HIGH Voltage 22 | Veo | 22 | Vee 1 22 | Vee) V +03 +0.3 +03 Vit Input LOW Voltagel!] -~03] 08 |-03] 08 |-03} 08 | Vv Ix Input Load Current GND < Vi < Vcc -10 | +10 | 10 | +10 | ~10 | +10 | pA loz Output Leakage GND < V; < Veo, -10 | +10 |} -10 | +10 | -10 | +10 | pA Current Output Disabled Tos Output Short Vcc = Max., Vout = GND 300 300 - 300 | mA Circuit Currentl4] Icc Vcc Operating Veco = Max, Iour = | Com'l 150. 125 11S | mA Supply Current OmA, f= fax = litre Mil 150 125 115 Ispi AutomaticCE Max.. Voc, CE > Vi, | Com! 30 25 25 mA Power-Down Current] Vin >Voror Vin < Vir TTL Inputs = f Max Mit 35 30 30 Isp2 Automatic CE Max. Vcc, Conmt 10 10 10 mA Power-DownCurrent | CE> Vcc -0.3V, Vin> CMOS Inputs Vec 0.3V or ; Vin < 03V,f=0 Mil 10 10 10 Capacitance!! - Parameters Description Test Conditions Max. Units Cin InputCapacitance Ta = 25C, f= 1 MHz, _ 10 pF Cour OutputCapacitance Voc = 5.0V 12 pF Notes: 1, Vit qin) = 2.0V for pulse durations of less than 20 ns, 4, Notmore than 1 outputshouldbe shorted atonetime. Durationofthe 2. Taisthe instant on case temperature, short circuit should nat exceed 30 seconds. 3. Seethe last page of thisspecificationforGroupAsubgrouptestingin- 5. Testedinitially and after any design or process changes that may affect these parameters. formation. 2-39 WBE D e5a%bbe OOOb301 T EacyP SRAMs aCYPRESS SEMICONDUCTOR WBE D = T-46-23-05 MM 254%bbe O00b302 1 EMCYP PRELIMINARY CY7C107 AC Test Loads and Waveforms . Al 4802 Ai 480g BV On BV O- We ALL INPUT PULSES wT tl. | Ce wor bossa oer 2560 INCLUDING L INCLUDING | JIG AND == JIG AND == SCOPE - Scope ~ - (a) (b) 6107-5 Equivalentto: THEVENIN EQUIVALENT 1678 OUTPUT Oa i 1.73 Switching Characteristicsl2.6 Over the Operating Range Gi07-6 7C107-25 7C10735 7C107-45 Parameters Description Min. | Max. | Min. | Max. | Min. | Max. | Units READ CYCLE trc Read Cycle Time 25 35 45 ns taa Address to Data Valid 25 35 45 ns toHa Data Hold from AddressChange 3 5 5 ns tace CE LOW to Data Valid 25 35 45 ns iLzce CE LOW to Low Zl" 5 | 5 5 tHzcR CE HIGH to High Zl, 81 10 15 20 ns tpu CELOW to Power-Up 0 0 0 his tpp CE HIGH to Power-Down 25 35 45 ns WRITE CYCLED! twe Write Cycle Time 25 35 45 ns tsce. CE LOW to Write End 20 25 30 ns taw Address Set-Up to Write End 20 25 30 ns tHa Address Hold from Write End 0 0 0 ns tsa Address Set-Up to Write Start 0 0 0 ns tpwE WE Pulse Width 20 25 30 ns tsp Data Set-Up to Write End 15 20 25 ns tap Data Hold from Write End 0 0 0 ns tLZWE WE HIGH to Low ZU] 5 5 5 ns tuzweE WELOW to High Zl? 8] 15 20 25 ns Notes: 6. Testconditions assume signal transition time of 5 ns orless, timing ref- erence levelsof 1.5, input pulse levels of 0 to 3.0V, and outputloading of the specified Ior/lop and 30-pF load capacitance. 7. At any given temperature and voltage condition, tuzce is less than tizce and tyzwe is less than tuzwe for any given device. 8. tuzce and tyzwe are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads, Transition is measured +500 mV from steady state voltage. The internal write time of the memory is defined by the overlap of CE LOW and WELOW.CE and WE must be LOW toinitiate a write, and the transition ofany of these signals can terminate thewrite. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.CYPRESS SEMICONDUCTOR GbE D ES 258%bb2 0006303 3 EacyP PRELIMINARY CY7C107 : 2 CYPRESS Sees SEMICONDUCTOR Switching Waveforms T-46-23-05 Read Cycle No, 110 14] >! tac ADDRESS Ke _ j x } SRAMs *| taa > torn > | DATA OUT PREVIOUS DATA VALID KxxX x DATA VALID . 107-4 Read Cycle No, 2U14 123 . ADDRESS x 1 CE N tac > YY \ : : : : . : /) tack - pe tizce __ re thizce IGH HIGH IMPEDANCE IMPEDANCE DATA OUT CREEK DATA VALID ee teo e tpy , surrey Ice a 50% CURRENT 50% - iSB c107-6 Write Cycle No. t (CE Controlied)[3] two ADDRESS tsp DATA IN DATA VALID HIGH IMPEDANCE DATA OUT 107-5 Notes: __ __ _ 10. Device is continuously selected. CE = Vy. 13. If CE goes HIGHsimultaneausly with WEgoing HIGH, the output re- 11. WEis HIGH for read cycle. mains in a high-impedance state. 12. Address valid prior to or coincident with CE transition LOW. 2-41CYPRESS SEMICONDUCTOR UbE D MM 2589bb2 0006304 5 EACYP = ae PRELIMINARY CY7C107 SSS S&S SEMICONDUCTOR Switching Waveforms _ T-46-23-05 Write Cycle No. 2 (WE Controlled)(131 ADDRESS Ce tpwe WE tso tuo DATA IN DATA VALID tHzwe tiawe HIGH IMPEDANCE cto7-7 Truth Table CE | WE Dout Mode Power H {j X | HighZ Power-Down Standby (Isp) L | H | DataOut Read Active (Icc) L | L | Highz Write Active (Icc) 2-42CYPRESS SEMICONDUCTOR PRELIMINARY CY7C107 Ordering Information T-46-23-05 Speed Package } Operating Speed | Package | Operating (us) Ordering Code Type Range (ns) Ordering Code Type Range 25 CY7C10725DC D41 | Commercial 45 CY7C10745DC D41 Commercial CY7C107-25LC L75 CY7C10745LC L75 CY7C10725PC P41 CY7C10745PC P4i CY7C107-25VC V28 CY7C10745VC V28 CY7C10725DMB D41 | Military CY7C10745DMB D41 Military CY7C107-25LMB L75 CY7C107--45LMB L715 35 CY7C107-35DC D41 Commercial CY7C10735LC Lis CY7C107~35PC P41 CY7C107~35VC v28 CY7C10735DMB D41 Military CY7C10735LMB L75 MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Switching Characteristics Parameters Subgroups - Parameters Subgroups Vou 1,2,3 READ CYCLE Vou 1,2,3 trc 7, 8, 9, 10, 11 Vin 1,2,3 taa 7, 8,9, 10, 14 Vir Max. 1, 2,3 toHa 7, 8, 9, 10, 11 ix 1,2,3 tACE 7,8, 9, 10, 11 loz 1,2,3 WRITE CYCLE Icc 1,2,3 twc 7, 8,9, 10, 11 Ispi 1,2,3 tscr 7, 8,9, 10, 11 Ispo 1,2,3 taw 7,8, 9, 10, 11 tHa 7,8, 9, 10, 11 Document #: 38-00150-B tsa 78,9, 1011 we 7, 8,9, 10, 11 tsp 7, 8, 9, 10, 11 tup 7, 8, 9, 16, 11 2-43 4BE D Ea 2589662 0006305 7 ENCYP. SRAMs e