MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DLow Supply-Voltage Range: 1.8 V to 3.6 V
DUltralow-Power Consumption:
− Active Mode: 400 μA at 1 MHz, 2.2 V
− Standby Mode: 1.3 μA
− Off Mode (RAM Retention): 0.22 μA
DFive Power-Saving Modes
DWake-Up From Standby Mode in Less
Than 6 μs
D16-Bit RISC Architecture, Extended
Memory, 125-ns Instruction Cycle Time
DThree Channel Internal DMA
D12-Bit A/D Converter With Internal
Reference, Sample-and-Hold, and Autoscan
Feature
DThree Configurable Operational Amplifiers
DDual 12-Bit Digital-to-Analog (D/A)
Converters With Synchronization
D16-Bit Timer_A With Three
Capture/Compare Registers
D16-Bit Timer_B With Seven
Capture/Compare-With-Shadow Registers
DOn-Chip Comparator
DSupply Voltage Supervisor/Monitor With
Programmable Level Detection
DSerial Communication Interface (USART1),
Select Asynchronous UART or
Synchronous SPI by Software
DUniversal Serial Communication Interface
− Enhanced UART Supporting
Auto-Baudrate Detection
− IrDA Encoder and Decoder
− Synchronous SPI
− I2CTM
DSerial Onboard Programming,
Programmable Code Protection by Security
Fuse
DBrownout Detector
DBasic Timer With Real Time Clock Feature
DIntegrated LCD Driver up to 160 Segments
With Regulated Charge Pump
DFamily Members Include:
− MSP430xG4616:
92KB+256B Flash or ROM Memory
4KB RAM
− MSP430xG4617:
92KB+256B Flash or ROM Memory,
8KB RAM
− MSP430xG4618:
116KB+256B Flash or ROM Memory,
8KB RAM
− MSP430xG4619:
120KB+256B Flash or ROM Memory,
4KB RAM
DFor Complete Module Descriptions, See the
MSP430x4xx Family User’s Guide
(
literature number SLAU056
)
description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is o p t i m i zed to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 6 μs.
The MSP430xG461x series are microcontroller configurations with two 16-bit timers, a high-performance 12-bit
A/D converter, dual 12-bit D/A converters, three configurable operational amplifiers, one universal serial
communication interface (USCI), one universal synchronous/asynchronous communication interface
(USART), DMA, 80 I/O pins, and a liquid crystal display (LCD) driver with regulated charge pump.
Typical applications for this device include portable medical applications and e-meter applications.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
AVAILABLE OPTIONS{
PACKAGED DEVICES}
TAPLASTIC 100-PIN TQFP
(PZ) PLASTIC 113-BALL BGA
(ZQW)
MSP430FG4616IPZ MSP430FG4616IZQW
MSP430FG4617IPZ MSP430FG4617IZQW
MSP430FG4618IPZ MSP430FG4618IZQW
40°Cto85°C
MSP430FG4619IPZ MSP430FG4619IZQW
−40°C to 85°CMSP430CG4616IPZ MSP430CG4616IZQW
MSP430CG4617IPZ MSP430CG4617IZQW
MSP430CG4618IPZ MSP430CG4618IZQW
MSP430CG4619IPZ MSP430CG4619IZQW
†For the most current package and ordering information, see the Package Option
Addendum at the end of this document, or see the TI
web site at www.ti.com.
‡Package drawings, thermal data, and symbolization are available at
www.ti.com/packaging.
DEVELOPMENT TOOL SUPPORT
All MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging
and programming through easy-to-use development tools. Recommended hardware options include:
DDebugging and Programming Interface
− MSP-FET430UIF (USB)
− MSP-FET430PIF (Parallel Port)
DDebugging and Programming Interface with Target Board
− MSP-FET430U100 (for PZ package)
DStandalone Target Board
− MSP-TS430PZ100 (for PZ package)
DProduction Programmer
− MSP-GANG430
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
pin designation, MSP430xG461xIPZ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P1.7/CA1
P6.1/A1/OA0O
P6.0/A0/OA0I0
RST/NMI
XT2IN
XT2OUT
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1.6/CA0
P2.3/TB2
P9,2/S15
P9.1/S16
P9.0/S17
P8.5/S20
P8.0/S25
P7.7/S26
P7.6/S27
P7.5/S28
P7.4/S29
P7.2/UCA0SOMI/S31
P4.7/UCA0RXD/S34
P7.3/UCA0CLK/S30
P1.0/TA0
TDI/TCLK
TDO/TDI
P8.4/S21
SS1
DV
P6.2/A2/OA0I1
P1.2/TA1
P8.1/S24
P4.6/UCA0TXD/S35
DVCC1
P6.3/A3/OA1O
P6.4/A4/OA1I0
P6.5/A5/OA2O
P6.6/A6/DAC0/OA2I0
P6.7/A7/DAC1/SVSIN
VREF+
XIN
XOUT
VeREF+/DAC0
VREF−/VeREF−
P5.1/S0/A12/DAC1
P5.0/S1/A13/OA1I1
P10.7/S2/A14/OA2I1
P10.6/S3/A15
P10.5/S4
P10.4/S5
P10.3/S6
P10.2/S7
P10.1/S8
P10.0/S9
P9.7/S10
P9.6/S11
P9.5/S12
P9.4/S13
P2.4/UCA0TXD
P2.5/UCA0RXD
P2.6/CAOUT
P2.7/ADC12CLK/DMAE0
P3.0/UCB0STE
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK
P3.4/TB3
P3.5/TB4
P3.6/TB5
P3.7/TB6
P4.0/UTXD1
P4.1/URXD1
DVSS2
DVCC2
LCDCAP/R33
P5.7/R23
P5.6/LCDREF/R13
P5.5/R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P4.2/STE1/S39
P8.6/S19
P8.3/S22
P8.2/S23
P7.0/UCA0STE/S33
P7.1/UCA0SIMO/S32
P4.5/UCLK1/S36
P4.4/SOMI1/S37
P4.3/SIMO1/S38
CC
AV
SS
AV
TCK
TMS
P1.1/TA0/MCLK
P2.0/TA2
P2.1/TB0
P2.2/TB1
MSP430xG4616IPZ
MSP430xG4617IPZ
MSP430xG4618IPZ
MSP430xG4619IPZ
P9.3/S14
P8.7/S18
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
pin designation, MSP430xG461xIZQW (top view)
A
B
C
D
E
F
G
H
J
K
L
M
123456789101112
NOTE: For terminal assignments, see the MSP430xG461x Terminal Functions table.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Oscillators
FLL+
RAM
4kB
8kB
8kB
4kB
Brownout
Protection
SVS/SVM
RST/NMI
DVCC1/2 DVSS1/2
MCLK
Watchdog
WDT+
15/16−Bit
Timer_A3
3CC
Registers
8MHz
CPUX
incl.16
Registers
XOUT/
XT2OUT
OA0,OA1,
OA2
3 Op Amps
Basic T imer
&
Real−Time
Clock
JTAG
Interface
LCD_A
160
Segments
1,2,3,4 Mux
Ports P1/P2
2x8 I/O
Interrupt
capability
USCI_A0:
UART,
IrDA,SPI
USCI_B0:
SPI,I2C
Comparator
_A
Flash(FG)
ROM(CG)
120kB
116kB
92kB
92kB
Hardware
Multiplier
MPY,
MPYS,
MAC,
MACS
Timer_B7
7CC
Registers,
Shadow
Reg
ADC12
12−Bit
12
Channels
DAC12
12−Bit
2Channels
Voltage out
USART1
UART,SPI
DMA
Controller
3 Channels
Ports
P3/P4
P5/P6
4x8 I/O
Ports
P7/P8
P9/P10
4x8/2x16 I/O
AVCC AVSS P1.x/P2.x
2x8
P3.x/P4.x
P5.x/P6.x
4x8
P7.x/P8.x
P9.x/P10.x
4x8/2x16
XIN/
XT2IN 22
SMCLK
ACLK
MDB
MAB
Enhanced
Emulation
(FG only)
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME NO.
PZ NO.
ZQW I/O DESCRIPTION
DVCC1 1 A1 Digital supply voltage, positive terminal
P6.3/A3/OA1O 2 B1 I/O General-purpose digital I/O / analog input a3—12-bit ADC / OA1 output
P6.4/A4/OA1I0 3 B2 I/O General-purpose digital I/O / analog input a4—12-bit ADC / OA1 input multiplexer
on +terminal and −terminal
P6.5/A5/OA2O 4 C2 I/O General-purpose digital I/O / analog input a5—12-bit ADC / OA2 output
P6.6/A6/DAC0/OA2I0 5 C1 I/O General-purpose digital I/O / analog input a6—12-bit ADC / DAC12.0 output / OA2
input multiplexer on +terminal and −terminal
P6.7/A7/DAC1/SVSIN 6 C3 I/O General-purpose digital I/O / analog input a7—12-bit ADC / DAC12.1 output /
analog input to brownout, supply voltage supervisor
VREF+ 7 D2 O Output of positive terminal of the reference voltage in the ADC
XIN 8 D1 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT 9 E1 O Output terminal of crystal oscillator XT1
VeREF+/DAC0 10 E2 I/O Input for an external reference voltage to the ADC / DAC12.0 output
VREF−/VeREF− 11 E4 I Negative terminal for the ADC reference voltage for both sources, the internal
reference voltage, or an external applied reference voltage
P5.1/S0/A12/DAC1 (see Note 1) 12 F1 I/O General-purpose digital I/O / LCD segment output 0 / analog input a12 − 12−bit
ADC / DAC12.1 output
P5.0/S1/A13/OA1I1 (see Note 1) 13 F2 I/O General-purpose digital I/O / LCD segment output 1 / analog input a13 − 12−bit
ADC/OA1 input multiplexer on +terminal and −terminal
P10.7/S2/A14/OA2I1 (see Note 1) 14 E5 I/O General-purpose digital I/O / LCD segment output 2 / analog input a14 − 12−bit
ADC/OA2 input multiplexer on +terminal and −terminal
P10.6/S3/A15 (see Note 1) 15 G1 I/O General-purpose digital I/O / LCD segment output 3 / analog input a15 − 12−bit
ADC
P10.5/S4 16 G2 I/O General-purpose digital I/O / LCD segment output 4
P10.4/S5 17 F4 I/O General-purpose digital I/O / LCD segment output 5
P10.3/S6 18 H1 I/O General-purpose digital I/O / LCD segment output 6
P10.2/S7 19 H2 I/O General-purpose digital I/O / LCD segment output 7
P10.1/S8 20 F5 I/O General-purpose digital I/O / LCD segment output 8
P10.0/S9 21 J1 I/O General-purpose digital I/O / LCD segment output 9
P9.7/S10 22 J2 I/O General-purpose digital I/O / LCD segment output 10
P9.6/S11 23 G4 I/O General-purpose digital I/O / LCD segment output 11
P9.5/S12 24 K1 I/O General-purpose digital I/O / LCD segment output 12
P9.4/S13 25 L1 I/O General-purpose digital I/O / LCD segment output 13
P9.3/S14 26 M2 I/O General-purpose digital I/O / LCD segment output 14
P9.2/S15 27 K2 I/O General-purpose digital I/O / LCD segment output 15
P9.1/S16 28 L3 I/O General-purpose digital I/O / LCD segment output 16
P9.0/S17 29 M3 I/O General-purpose digital I/O / LCD segment output 17
P8.7/S18 30 H4 I/O General-purpose digital I/O / LCD segment output 18
P8.6/S19 31 L4 I/O General-purpose digital I/O / LCD segment output 19
P8.5/S20 32 M4 I/O General-purpose digital I/O / LCD segment output 20
P8.4/S21 33 G5 I/O General-purpose digital I/O / LCD segment output 21
P8.3/S22 34 L5 I/O General-purpose digital I/O / LCD segment output 22
NOTES: 1. Segments S 0 through S3 are disabled when the LCD charge pump feature is enabled (LCDCPEN = 1) and cannot be used together
with the LCD charge pump. In addition, when using segments S0 through S3 with an external LCD voltage supply, VLCD ≤AVCC.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
NAME NO.
PZ NO.
ZQW I/O DESCRIPTION
P8.2/S23 35 M5 I/O General-purpose digital I/O / LCD segment output 23
P8.1/S24 36 H5 I/O General-purpose digital I/O / LCD segment output 24
P8.0/S25 37 J5 I/O General-purpose digital I/O / LCD segment output 25
P7.7/S26 38 M6 I/O General-purpose digital I/O / LCD segment output 26
P7.6/S27 39 L6 I/O General-purpose digital I/O / LCD segment output 27
P7.5/S28 40 J6 I/O General-purpose digital I/O / LCD segment output 28
P7.4/S29 41 M7 I/O General-purpose digital I/O / LCD segment output 29
P7.3/UCA0CLK/S30 42 H6 I/O General-purpose digital I/O / external clock input − USCI_A0/UART or SPI mode, clock
output − USCI_A0/SPI mode / LCD segment 30
P7.2/UCA0SOMI/S31 43 L7 I/O General-purpose digital I/O / slave out/master in of USCI_A0/SPI mode / LCD segment
output 31
P7.1/UCA0SIMO/S32 44 M8 I/O General-purpose digital I/O / slave in/master out of USCI_A0/SPI mode / LCD segment
output 32
P7.0/UCA0STE/S33 45 L8 I/O General-purpose d i gital I/O / slave transmit enable—USCI_A0/SPI mode / LCD segment
output 33
P4.7/UCA0RXD/S34 46 J7 I/O General-purpose digital I/O / receive data in − USCI_A0/UART or IrDA mode / LCD
segment output 34
P4.6/UCA0TXD/S35 47 M9 I/O General-purpose digital I/O / transmit data out − USCI_A0/UART or IrDA mode / LCD
segment output 35
P4.5/UCLK1/S36 48 L9 I/O General-purpose digital I/O / external clock input − USART1/UART or SPI mode,
clock output − USART1/SPI MODE / LCD segment output 36
P4.4/SOMI1/S37 49 H7 I/O General-purpose digital I/O / slave out/master in of USART1/SPI mode / LCD segment
output 37
P4.3/SIMO1/S38 50 M10 I/O General-purpose digital I/O / slave in/master out of USART1/SPI mode / LCD segment
output 38
P4.2/STE1/S39 51 M11 I/O General-purpose d i g i t a l I / O / slave transmit enable—USART1/SPI mode / LCD segment
output 39
COM0 52 L10 O COM0−3 are used for LCD backplanes.
P5.2/COM1 53 L12 I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
P5.3/COM2 54 J8 I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
P5.4/COM3 55 K12 I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
P5.5/R03 56 K11 I/O General-purpose digital I/O / Input port of lowest analog LCD level (V5)
P5.6/LCDREF/R13 57 J12 I/O General-purpose digital I/O / External reference voltage input for regulated LCD voltage
/ Input port of third most positive analog LCD level (V4 or V3)
P5.7/R23 58 J11 I/O General-purpose digital I/O / Input port of second most positive analog LCD level (V2)
LCDCAP/R33 59 H11 I LCD capacitor connection / Input/output port of most positive analog LCD level (V1)
DVCC2 60 H12 Digital supply voltage, positive terminal
DVSS2 61 G12 Digital supply voltage, negative terminal
P4.1/URXD1 62 G11 I/O General-purpose digital I/O / receive data in—USART1/UART mode
P4.0/UTXD1 63 H9 I/O General-purpose digital I/O / transmit data out—USART1/UART mode
P3.7/TB6 64 F12 I/O General-purpose digital I/O / Timer_B7 CCR6. Capture: CCI6A/CCI6B input, compare:
Out6 output
P3.6/TB5 65 F11 I/O General-purpose digital I/O / Timer_B7 CCR5. Capture: CCI5A/CCI5B input, compare:
Out5 output
P3.5/TB4 66 G9 I/O General-purpose digital I/O / Timer_B7 CCR4. Capture: CCI4A/CCI4B input, compare:
Out4 output
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
NAME NO.
PZ NO.
ZQW I/O DESCRIPTION
P3.4/TB3 67 E12 I/O General-purpose digital I/O / Timer_B7 CCR3. Capture: CCI3A/CCI3B input, compare: Out3
output
P3.3/UCB0CLK 68 E11 I/O General-purpose digital I/O / external clock input—USCI_B0/UART or SPI mode, clock
output—USCI_B0/SPI mode
P3.2/UCB0SOMI/
UCB0SCL 69 F9 I/O General-purpose digital I/O / slave out/master in of USCI_B0/SPI mode /I2C
clock—USCI_B0/I2C mode
P3.1/UCB0SIMO/
UCB0SDA 70 D12 I/O General-purpose digital I/O / slave in/master out of USCI_B0/SPI mode, I2C
data—USCI_B0/I2C mode
P3.0/UCB0STE 71 D11 I/O General-purpose digital I/O / slave transmit enable—USCI_B0/SPI mode
P2.7/ADC12CLK/
DMAE0 72 E9 I/O General-purpose d i gital I/O / conversion clock—12-bit ADC / DMA Channel 0 external trigger
P2.6/CAOUT 73 C12 I/O General-purpose digital I/O / Comparator_A output
P2.5/UCA0RXD 74 C11 I/O General-purpose digital I/O / receive data in—USCI_A0/UART or IrDA mode
P2.4/UCA0TXD 75 B12 I/O General-purpose digital I/O / transmit data out—USCI_A0/UART or IrDA mode
P2.3/TB2 76 A11 I/O General-purpose digital I/O / Timer_B7 CCR2. Capture: CCI2A/CCI2B input, compare: Out2
output
P2.2/TB1 77 E8 I/O General-purpose digital I/O / T imer_B7 CCR1. Capture: CCI1A/CCI1B input, compare: Out1
output
P2.1/TB0 78 D8 I/O General-purpose digital I/O / T imer_B7 CCR0. Capture: CCI0A/CCI0B input, compare: Out0
output
P2.0/TA2 79 A10 I/O General-purpose digital I/O / T imer_A Capture: CCI2A input, compare: Out2 output
P1.7/CA1 80 B10 I/O General-purpose digital I/O / Comparator_A input
P1.6/CA0 81 A9 I/O General-purpose digital I/O / Comparator_A input
P1.5/TACLK/ACLK 82 B9 I/O General-purpose digital I/O / Timer_A, clock signal TACLK input / ACLK output (divided by
1, 2, 4, or 8)
P1.4/TBCLK/SMCLK 83 B8 I/O General-purpose digital I/O / input clock TBCLK—Timer_B7 / submain system clock SMCLK
output
P1.3/TBOUTH/SVSOUT 84 A8 I/O General-purpose digital I/O / switch all PWM digital output ports to high
impedance—Timer_B7 TB0 to TB6 / SVS: output of SVS comparator
P1.2/TA1 85 D7 I/O General-purpose digital I/O / Timer_A, Capture: CCI1A input, compare: Out1 output
P1.1/TA0/MCLK 86 E7 I/O General-purpose digital I/O / Timer_A. Capture: CCI0B input / MCLK output.
Note: TA0 is only an input on this pin / BSL receive
P1.0/TA0 87 A7 I/O General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output / BSL
transmit
XT2OUT 88 B7 O Output terminal of crystal oscillator XT2
XT2IN 89 B6 I Input port for crystal oscillator XT2. Only standard crystals can be connected.
TDO/TDI 90 A6 I/O Test data output port. TDO/TDI data output or programming data input terminal
TDI/TCLK 91 D6 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TMS 92 E6 I Test mode select. TMS is used as an input port for device programming and test.
TCK 93 A5 I Test clock. TCK is the clock input port for device programming and test.
RST/NMI 94 B5 I Reset input or nonmaskable interrupt input port
P6.0/A0/OA0I0 95 A4 I/O General-purpose digital I/O / analog input a0—12-bit ADC / OA0 input multiplexer on
+ terminal and − terminal
P6.1/A1/OA0O 96 D5 I/O General-purpose digital I/O / analog input a1—12-bit ADC / OA0 output
P6.2/A2/OA0I1 97 B4 I/O General-purpose digital I/O / analog input a2—12-bit ADC / OA0 input multiplexer on
+ terminal and − terminal
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
NAME NO.
PZ NO.
ZQW I/O DESCRIPTION
AVSS 98 A3 Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator, comparator_A,
port 1
DVSS1 (see Note 1) 99 B3 Digital supply voltage, negative terminal
AVCC 100 A2 Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator, comparator_A,
port 1; must not power up prior to DVCC1/DVCC2.
NOTE 1: All unassigned ball locations on the ZQW package should be electrically tied to the ground supply. The shortest ground return path to
the device should be established via ball location B3.
General-Purpose Register
Program Counter
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
R5
R12
R13
General-Purpose Register
General-Purpose Register
R6
R7
General-Purpose Register
General-Purpose Register
R8
R9
General-Purpose Register
General-Purpose Register
R10
R11
General-Purpose Register
General-Purpose Register
R14
R15
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
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short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
Peripherals ar e c onnected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
The MSP430xG461x device family utilizes the
MSP430X CPU and is completely backwards
compatible with the MSP430 CPU. For a complete
description of the MSP430X CPU, see the
MSP430x4xx Family User’s Guide (SLAU056).
instruction set
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the
expanded address range. Each instruction can
operate on word and byte data. Table 1 shows
examples of the three types of instruction formats;
Table 2 shows the address modes.
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Table 1. Instruction Word Formats
Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 −−−> R5
Single operands, destination only e.g., CALL R8 PC −−>(TOS), R8−−> PC
Relative jump, un/conditional e.g., JNE Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE S D SYNTAX EXAMPLE OPERATION
Register FFMOV Rs,Rd MOV R10,R11 R10 —> R11
Indexed F F MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)—> M(6+R6)
Symbolic (PC relative) F F MOV EDE,TONI M(EDE) —> M(TONI)
Absolute F F MOV & MEM, & TCDAT M(MEM) —> M(TCDAT)
Indirect FMOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) —> M(Tab+R6)
Indirect
autoincrement FMOV @Rn+,Rm MOV @R10+,R11 M(R10) —> R11
R10 + 2—> R10
Immediate FMOV #X,TONI MOV #45,TONI #45 —> M(TONI)
NOTE: S = source D = destination
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operating modes
The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
DActive mode (AM)
− All clocks are active
DLow-power mode 0 (LPM0)
− CPU is disabled
− ACLK and SMCLK remain active. MCLK is disabled
− FLL+ loop control remains active
DLow-power mode 1 (LPM1)
− CPU is disabled
− FLL+ loop control is disabled
− ACLK and SMCLK remain active, MCLK is disabled
DLow-power mode 2 (LPM2)
− CPU is disabled
− MCLK, FLL+ loop control and DCOCLK are disabled
− DCO’s dc-generator remains enabled
− ACLK remains active
DLow-power mode 3 (LPM3)
− CPU is disabled
− MCLK, FLL+ loop control, and DCOCLK are disabled
− DCO’s dc-generator is disabled
− ACLK remains active
DLow-power mode 4 (LPM4)
− CPU is disabled
− ACLK is disabled
− MCLK, FLL+ loop control, and DCOCLK are disabled
− DCO’s dc-generator is disabled
− Crystal oscillator is stopped
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interrupt vector addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FFC0h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 3. Interrupt Sources, Flags, and Vectors of MSP430xG461x Configurations
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD
ADDRESS PRIORITY
Power-Up
External Reset
Watchdog
Flash Memory
WDTIFG
KEYV
(see Note 1 and 5)
Reset 0FFFEh 31, highest
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1, 2, and 5)
(Non)maskable
(Non)maskable
(Non)maskable 0FFFCh 30
Timer_B7 TBCCR0 CCIFG0 (see Note 2) Maskable 0FFFAh 29
Timer_B7 TBCCR1 CCIFG1 ... TBCCR6 CCIFG6,
TBIFG (see Notes 1 and 2) Maskable 0FFF8h 28
Comparator_A CAIFG Maskable 0FFF6h 27
Watchdog Timer+ WDTIFG Maskable 0FFF4h 26
USCI_A0/USCI_B0 Receive UCA0RXIFG, UCB0RXIFG (see Note 1) Maskable 0FFF2h 25
USCI_A0/USCI_B0 Transmit UCA0TXIFG, UCB0TXIFG (see Note 1) Maskable 0FFF0h 24
ADC12 ADC12IFG (see Notes 1 and 2) Maskable 0FFEEh 23
Timer_A3 TACCR0 CCIFG0 (see Note 2) Maskable 0FFECh 22
Timer_A3 TACCR1 CCIFG1 and TACCR2 CCIFG2,
TAIFG (see Notes 1 and 2) Maskable 0FFEAh 21
I/O Port P1 (Eight Flags) P1IFG.0 to P1IFG.7 (see Notes 1 and 2) Maskable 0FFE8h 20
USART1 Receive URXIFG1 Maskable 0FFE6h 19
USART1 Transmit UTXIFG1 Maskable 0FFE4h 18
I/O Port P2 (Eight Flags) P2IFG.0 to P2IFG.7 (see Notes 1 and 2) Maskable 0FFE2h 17
Basic Timer1/RTC BTIFG Maskable 0FFE0h 16
DMA DMA0IFG, DMA1IFG, DMA2IFG
(see Notes 1 and 2) Maskable 0FFDEh 15
DAC12 DAC12.0IFG, DAC12.1IFG (see Notes 1 and 2) Maskable 0FFDCh 14
0FFDAh 13
Reserved Reserved (see Note 4) ... ...
Reserved
Reserved
(see
Note
4)
0FFC0h 0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh).
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
4. The interrupt vectors at addresses 0FFDAh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
5. Access and key violations, KEYV and ACCVIFG, only applicable to F devices.
MSP430xG461x
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special function registers (SFRs)
The MSP430 SFRs are located in the lowest address space and are organized as byte mode registers. SFRs
should be accessed with byte instructions.
interrupt enable 1 and 2
7654 0
OFIE WDTIE
321
rw–0 rw–0 rw–0
Address
0h ACCVIE NMIIE
rw–0
WDTIE Watchdog-timer interrupt enable. Inactive if watchdog mode is selected.
Active if watchdog timer is configured as a general-purpose timer.
OFIE Oscillator-fault-interrupt enable
NMIIE Nonmaskable-interrupt enable
ACCVIE Flash access violation interrupt enable
7654 0321
Address
01h
rw–0
BTIE UTXIE1 URXIE1
rw–0 rw–0
UCA0TXIE UCA0RXIE
rw–0 rw–0
UCB0TXIE UCB0RXIE
rw–0 rw–0
UCA0RXIE USCI_A0 receive-interrupt enable
UCA0TXIE USCI_A0 transmit-interrupt enable
UCB0RXIE USCI_B0 receive-interrupt enable
UCB0TXIE USCI_B0 transmit-interrupt enable
URXIE1 USART1 UART and SPI receive-interrupt enable
UTXIE1 USART1 UART and SPI transmit-interrupt enable
BTIE Basic timer interrupt enable
MSP430xG461x
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interrupt flag register 1 and 2
7654 0
OFIFG WDTIFG
321
rw–0 rw–1 rw–(0)
Address
02h NMIIFG
WDTIFG: Set on watchdog timer overflow (in watchdog mode) or security key violation
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode
OFIFG: Flag set on oscillator fault
NMIIFG: Set via RST/NMI pin
7654 0321
Address
03h BTIFG
rw–0
UTXIFG1 URXIFG1
rw–1 rw–0
UCA0TXIFG UCA0RXIFG
rw–0 rw–0
UCB0TXIFG UCB0RXIFG
rw–0 rw–0
UCA0RXIFG USCI_A0 receive-interrupt flag
UCA0TXIFG USCI_A0 transmit-interrupt flag
UCB0RXIFG USCI_B0 receive-interrupt flag
UCB0TXIFG USCI_B0 transmit-interrupt flag
URXIFG0: USART1: UART and SPI receive flag
UTXIFG0: USART1: UART and SPI transmit flag
BTIFG: Basic timer flag
module enable registers 1 and 2
7654 0321
Address
04h
7654 0
UTXE1 321
rw–0 rw–0
Address
05h URXE1
USPIE1
URXE1: USART1: UART mode receive enable
UTXE1: USART1: UART mode transmit enable
USPIE1: USART1: SPI mode transmit and receive enable
Legend rw:
rw-0,1: Bit can be read and written.
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
rw-(0,1): SFR bit is not present in device
MSP430xG461x
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memory organization
MSP430FG4616 MSP430FG4617 MSP430FG4618 MSP430FG4619
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
92KB
0FFFFh − 0FFC0h
018FFFh − 002100h
92KB
0FFFFh − 0FFC0h
019FFFh − 003100h
116KB
0FFFFh − 0FFC0h
01FFFFh − 003100h
120KB
0FFFFh − 0FFC0h
01FFFFh − 002100h
RAM (Total) Size 4KB
020FFh − 01100h 8KB
030FFh − 01100h 8KB
030FFh − 01100h 4KB
020FFh − 01100h
Extended Size 2KB
020FFh − 01900h 6KB
030FFh − 01900h 6KB
030FFh − 01900h 2KB
020FFh − 01900h
Mirrored Size 2KB
018FFh − 01100h 2KB
018FFh − 01100h 2KB
018FFh − 01100h 2KB
018FFh − 01100h
Information memory Size
Flash 256 Byte
010FFh − 01000h 256 Byte
010FFh − 01000h 256 Byte
010FFh − 01000h 256 Byte
010FFh − 01000h
Boot memory Size
ROM 1KB
0FFFh − 0C00h 1KB
0FFFh − 0C00h 1KB
0FFFh − 0C00h 1KB
0FFFh − 0C00h
RAM
(mirrored at
018FFh − 01100h)
Size 2KB
09FFh − 0200h 2KB
09FFh − 0200h 2KB
09FFh − 0200h 2KB
09FFh − 0200h
Peripherals 16 bit
8 bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
MSP430CG4616 MSP430CG4617 MSP430CG4618 MSP430CG4619
Memory
Main: interrupt vector
Main: code memory
Size
ROM
ROM
92KB
0FFFFh − 0FFC0h
018FFFh − 002100h
92KB
0FFFFh − 0FFC0h
019FFFh − 003100h
116KB
0FFFFh − 0FFC0h
01FFFFh − 003100h
120KB
0FFFFh − 0FFC0h
01FFFFh − 002100h
RAM (Total) Size 4KB
020FFh − 01100h 8KB
030FFh − 01100h 8KB
030FFh − 01100h 4KB
020FFh − 01100h
Extended Size 2KB
020FFh − 01900h 6KB
030FFh − 01900h 6KB
030FFh − 01900h 2KB
020FFh − 01900h
Mirrored Size 2KB
018FFh − 01100h 2KB
018FFh − 01100h 2KB
018FFh − 01100h 2KB
018FFh − 01100h
Information memory Size
ROM 256 Byte
010FFh − 01000h 256 Byte
010FFh − 01000h 256 Byte
010FFh − 01000h 256 Byte
010FFh − 01000h
Boot memory
(Optional on CG) Size
ROM 1KB
0FFFh − 0C00h 1KB
0FFFh − 0C00h 1KB
0FFFh − 0C00h 1KB
0FFFh − 0C00h
RAM
(mirrored at
018FFh − 01100h)
Size 2KB
09FFh − 0200h 2KB
09FFh − 0200h 2KB
09FFh − 0200h 2KB
09FFh − 0200h
Peripherals 16 bit
8 bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
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bootstrap loader (BSL)
The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access
to the MSP430 memory via the BSL is protected by user-defined password. A bootstrap loader security key is
provided at address 0FFBEh to disable the BSL completely or to disable the erasure of the flash if an invalid
password is supplied. The BSL is optional for ROM-based devices. For complete description of the features of
the BSL and its implementation, see the application report Features of the MSP430 Bootstrap Loader, literature
number SLAA089.
BSLKEY DESCRIPTION
00000h Erasure of flash disabled if an invalid password is supplied
0AA55h BSL disabled
any other value BSL enabled
BSL FUNCTION PZ/ZQW PACKAGE PINS
Data Transmit 87/A7 − P1.0
Data Receive 86/E7 − P1.1
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
DFlash memory has n segments of main memory and two segments of information memory (A and B) of
128 bytes each. Each segment in main memory is 512 bytes in size.
DSegments 0 to n may be erased in one step, or each segment may be individually erased.
DSegments A and B can be erased individually, or as a group with segments 0 to n.
Segments A and B are also called information memory.
DNew devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
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peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x4xx Family User’s Guide (SLAU056).
DMA controller
The DMA controller allows movement of data from one memory address to another without CPU intervention.
For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system
power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to
or from a peripheral.
oscillator and system clock
The clock system in the MSP430xG461x family of devices is supported by the FLL+ module, which includes
support for a 32768-Hz watch crystal oscillator, an internal digitally controlled oscillator (DCO), and a
high-frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low
system cost and low power consumption. The FLL+ features digital frequency locked loop (FLL) hardware that,
in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch
crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 μs. The
FLL+ module provides the following clock signals:
DAuxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal
DMain clock (MCLK), the system clock used by the CPU
DSub-Main clock (SMCLK), the subsystem clock used by the peripheral modules
DACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8
brownout, supply voltage supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power-on
and power-off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user
selectable level and supports both supply voltage supervision (the device is automatically reset) and supply
voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not
have ramped to VCC(min) at that time. The user must insure the default FLL+ settings are not changed until VCC
reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
digital I/O
There are ten 8-bit I/O ports implemented—ports P1 through P10:
DAll individual I/O bits are independently programmable.
DAny combination of input, output, and interrupt conditions is possible.
DEdge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
DRead/write access to port-control registers is supported by all instructions.
DPorts P7/P8 and P9/P10 can be accessed word-wise as ports PA and PB respectively.
Basic Timer1 and Real-Time Clock
The Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. Basic Timer1 is extended to provide an integrated real-time clock
(RTC). A n i n t e r n a l calendar compensates for months with less than 31 days and includes leap-year correction.
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LCD_A drive with regulated charge pump
The LCD_A driver generates the segment and common signals required to drive an LCD display. The LCD_A
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.
The module can provide a LCD voltage independent of the supply voltage with its integrated charge pump.
Furthermore it is possible to control the level of the LCD voltage and, thus, contrast by software.
watchdog timer (WDT+)
The primary function of the WDT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be configured as an interval timer and can generate interrupts at selected time
intervals.
universal serial communication interface (USCI)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols like SPI (3 or 4 pin), I2C and asynchronous communication protocols like UART,
enhanced UART with automatic baudrate detection, and IrDA.
The USCI_A0 module provides support for SPI (3 or 4 pin), UART, enhanced UART and IrDA.
The USCI_B0 module provides support for SPI (3 or 4 pin) and I2C.
USART1
The hardware universal synchronous/asynchronous receive transmit (USART) peripheral module is used for
serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART
communication protocols, using double-buffered transmit and receive channels.
hardware multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs 16 16,
16 8, 8 16, and 8 8 bit operations. The module is capable of supporting signed and unsigned multiplication,
as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.
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Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input Pin Number Device Input Module Input Module Module Output Output Pin Number
PZ/ZQW
Device
Input
Signal
Module
Input
Name
Module
Block
Module
Output
Signal PZ/ZQW
82/B9 - P1.5 TACLK TACLK
ACLK ACLK
Timer
NA
SMCLK SMCLK Timer NA
82/B9 - P1.5 TACLK INCLK
87/A7 - P1.0 TA0 CCI0A 87/A7 - P1.0
86/E7 - P1.1 TA0 CCI0B
CCR0
TA0
DVSS GND CCR0 TA0
DVCC VCC
85/D7 - P1.2 TA1 CCI1A 85/D7 - P1.2
CAOUT (internal) CCI1B
CCR1
TA1
ADC12 (internal)
DVSS GND CCR1 TA1
DVCC VCC
79/A10 - P2.0 TA2 CCI2A 79/A10 - P2.0
ACLK (internal) CCI2B
CCR2
TA2
DVSS GND CCR2 TA2
DVCC VCC
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Timer_B7
Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_B7 Signal Connections
Input Pin Number Device Input Module Input Module Module Output Output Pin Number
PZ/ZQW
Device
Input
Signal
Module
Input
Name
Module
Block
Module
Output
Signal PZ/ZQW
83/B8 - P1.4 TBCLK TBCLK
ACLK ACLK
Timer
NA
SMCLK SMCLK Timer NA
83/B8 - P1.4 TBCLK INCLK
78/D8 - P2.1 TB0 CCI0A 78/D8 - P2.1
78/D8 - P2.1 TB0 CCI0B
CCR0
TB0
ADC12 (internal)
DVSS GND CCR0 TB0
DVCC VCC
77/E8 - P2.2 TB1 CCI1A 77/E8 - P2.2
77/E8 - P2.2 TB1 CCI1B
CCR1
TB1
ADC12 (internal)
DVSS GND CCR1 TB1
DVCC VCC
76/A11 - P2.3 TB2 CCI2A 76/A11 - P2.3
76/A11 - P2.3 TB2 CCI2B
CCR2
TB2
DVSS GND CCR2 TB2
DVCC VCC
67/E12 - P3.4 TB3 CCI3A 67/E12 - P3.4
67/E12 - P3.4 TB3 CCI3B
CCR3
TB3
DVSS GND CCR3 TB3
DVCC VCC
66/G9 - P3.5 TB4 CCI4A 66/G9 - P3.5
66/G9 - P3.5 TB4 CCI4B
CCR4
TB4
DVSS GND CCR4 TB4
DVCC VCC
65/F11 - P3.6 TB5 CCI5A 65/F11 - P3.6
65/F11 - P3.6 TB5 CCI5B
CCR5
TB5
DVSS GND CCR5 TB5
DVCC VCC
64/F12 - P3.7 TB6 CCI6A 64/F12 - P3.7
ACLK (internal) CCI6B
CCR6
TB6
DVSS GND CCR6 TB6
DVCC VCC
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Comparator_A
The primary function of the comparator_A module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
ADC12
The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator and a 16 word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without
any CPU intervention.
DAC12
The DAC12 module is a 12-bit, R-ladder, voltage output DAC. The DAC12 may be used in 8- or 12-bit mode,
and may be used in conjunction with the DMA controller. When multiple DAC12 modules are present, they may
be grouped together for synchronous operation.
OA
The MSP430xG461x has three configurable low-current general-purpose operational amplifiers. Each OA input
and output terminal is software-selectable and offer a flexible choice of connections for various applications.
The OA op amps primarily support front-end analog signal conditioning prior to analog-to-digital conversion.
OA Signal Connections
Input Pin
Number Device Input
Signal
Module Input
Name
Module
Block
Module
Out
p
ut Device
Out
p
ut
Output Pin
Number
PZ Signal Name Block
Output
Signal
Output
Signal PZ
95 - P6.0 OA0I0 OA0I0 OA0O 96 - P6.1
97 - P6.2 OA0I1 OA0I1 OA0O ADC12 (internal)
DAC12_0OUT
(internal) DAC12_0OUT OA0 OA0OUT
DAC12_1OUT
(internal) DAC12_1OUT
3 - P6.4 OA1I0 OA1I0 OA1O 2 - P6.3
13 - P5.0 OA1I1 OA1I1 OA1O 13- P5.0
DAC12_0OUT
(internal) DAC12_0OUT OA1 OA1OUT OA1O ADC12 (internal)
DAC12_1OUT
(internal) DAC12_1OUT
5 - P6.6 OA2I0 OA2I0 OA2O 4 - P6.5
14 - P10.7 OA2I1 OA2I1 OA2O 14 - P10.7
DAC12_0OUT
(internal) DAC12_0OUT OA2 OA2OUT OA2O ADC12 (internal)
DAC12_1OUT
(internal) DAC12_1OUT
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog+ Watchdog timer control WDTCTL 0120h
Timer_B7 Capture/compare register 6 TBCCR6 019Eh
_
Capture/compare register 5 TBCCR5 019Ch
Capture/compare register 4 TBCCR4 019Ah
Capture/compare register 3 TBCCR3 0198h
Capture/compare register 2 TBCCR2 0196h
Capture/compare register 1 TBCCR1 0194h
Capture/compare register 0 TBCCR0 0192h
Timer_B register TBR 0190h
Capture/compare control 6 TBCCTL6 018Eh
Capture/compare control 5 TBCCTL5 018Ch
Capture/compare control 4 TBCCTL4 018Ah
Capture/compare control 3 TBCCTL3 0188h
Capture/compare control 2 TBCCTL2 0186h
Capture/compare control 1 TBCCTL1 0184h
Capture/compare control 0 TBCCTL0 0182h
Timer_B control TBCTL 0180h
Timer_B interrupt vector TBIV 011Eh
Timer_A3 Capture/compare register 2 TACCR2 0176h
_
Capture/compare register 1 TACCR1 0174h
Capture/compare register 0 TACCR0 0172h
Timer_A register TAR 0170h
Capture/compare control 2 TACCTL2 0166h
Capture/compare control 1 TACCTL1 0164h
Capture/compare control 0 TACCTL0 0162h
Timer_A control TACTL 0160h
Timer_A interrupt vector TAIV 012Eh
Hardware Sum extend SUMEXT 013Eh
Multiplier Result high word RESHI 013Ch
Result low word RESLO 013Ah
Second operand OP2 0138h
Multiply signed + accumulate/operand1 MACS 0136h
Multiply + accumulate/operand1 MAC 0134h
Multiply signed/operand1 MPYS 0132h
Multiply unsigned/operand1 MPY 0130h
Flash Flash control 3 FCTL3 012Ch
(FG devices only) Flash control 2 FCTL2 012Ah
Flash control 1 FCTL1 0128h
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map (continued)
PERIPHERALS WITH WORD ACCESS (CONTINUED)
DMA DMA module control 0 DMACTL0 0122h
DMA module control 1 DMACTL1 0124h
DMA interrupt vector DMAIV 0126h
DMA Channel 0 DMA channel 0 control DMA0CTL 01D0h
DMA channel 0 source address DMA0SA 01D2h
DMA channel 0 destination address DMA0DA 01D6h
DMA channel 0 transfer size DMA0SZ 01DAh
DMA Channel 1 DMA channel 1 control DMA1CTL 01DCh
DMA channel 1 source address DMA1SA 01DEh
DMA channel 1 destination address DMA1DA 01E2h
DMA channel 1 transfer size DMA1SZ 01E6h
DMA Channel 2 DMA channel 2 control DMA2CTL 01E8h
DMA channel 2 source address DMA2SA 01EAh
DMA channel 2 destination address DMA2DA 01EEh
DMA channel 2 transfer size DMA2SZ 01F2h
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map (continued)
PERIPHERALS WITH WORD ACCESS (CONTINUED)
ADC12 Conversion memory 15 ADC12MEM15 015Eh
See also Peripherals Conversion memory 14 ADC12MEM14 015Ch
See
also
Peripherals
With Byte Access Conversion memory 13 ADC12MEM13 015Ah
y
Conversion memory 12 ADC12MEM12 0158h
Conversion memory 11 ADC12MEM11 0156h
Conversion memory 10 ADC12MEM10 0154h
Conversion memory 9 ADC12MEM9 0152h
Conversion memory 8 ADC12MEM8 0150h
Conversion memory 7 ADC12MEM7 014Eh
Conversion memory 6 ADC12MEM6 014Ch
Conversion memory 5 ADC12MEM5 014Ah
Conversion memory 4 ADC12MEM4 0148h
Conversion memory 3 ADC12MEM3 0146h
Conversion memory 2 ADC12MEM2 0144h
Conversion memory 1 ADC12MEM1 0142h
Conversion memory 0 ADC12MEM0 0140h
Interrupt-vector-word register ADC12IV 01A8h
Inerrupt-enable register ADC12IE 01A6h
Inerrupt-flag register ADC12IFG 01A4h
Control register 1 ADC12CTL1 01A2h
Control register 0 ADC12CTL0 01A0h
DAC12 DAC12_1 data DAC12_1DAT 01CAh
DAC12_1 control DAC12_1CTL 01C2h
DAC12_0 data DAC12_0DAT 01C8h
DAC12_0 control DAC12_0CTL 01C0h
Port PA Port PA selection PASEL 03Eh
Port PA direction PADIR 03Ch
Port PA output PAOUT 03Ah
Port PA input PAIN 038h
Port PB Port PB selection PBSEL 00Eh
Port PB direction PBDIR 00Ch
Port PB output PBOUT 00Ah
Port PB input PBIN 008h
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS
OA2 Operational Amplifier 2 control register 1
Operational Amplifier 2 control register 0 OA2CTL1
OA2CTL0 0C5h
0C4h
OA1 Operational Amplifier 1 control register 1
Operational Amplifier 1 control register 0 OA1CTL1
OA1CTL0 0C3h
0C2h
OA0 Operational Amplifier 0 control register 1
Operational Amplifier 0 control register 0 OA0CTL1
OA0CTL0 0C1h
0C0h
LCD_A LCD Voltage Control 1
LCD Voltage Control 0
LCD Voltage Port Control 1
LCD Voltage Port Control 0
LCD memory 20
:
LCD memory 16
LCD memory 15
:
LCD memory 1
LCD control and mode
LCDAVCTL1
LCDAVCTL0
LCDAPCTL1
LCDAPCTL0
LCDM20
:
LCDM16
LCDM15
:
LCDM1
LCDCTL
0AFh
0AEh
0ADh
0ACh
0A4h
:
0A0h
09Fh
:
091h
090h
ADC12 ADC memory-control register 15 ADC12MCTL15 08Fh
(Memory control
registers require byte
ADC memory-control register 14 ADC12MCTL14 08Eh
registers require byte
access)
ADC memory-control register 13 ADC12MCTL13 08Dh
access
)
ADC memory-control register 12 ADC12MCTL12 08Ch
ADC memory-control register 11 ADC12MCTL11 08Bh
ADC memory-control register 10 ADC12MCTL10 08Ah
ADC memory-control register 9 ADC12MCTL9 089h
ADC memory-control register 8 ADC12MCTL8 088h
ADC memory-control register 7 ADC12MCTL7 087h
ADC memory-control register 6 ADC12MCTL6 086h
ADC memory-control register 5 ADC12MCTL5 085h
ADC memory-control register 4 ADC12MCTL4 084h
ADC memory-control register 3 ADC12MCTL3 083h
ADC memory-control register 2 ADC12MCTL2 082h
ADC memory-control register 1 ADC12MCTL1 081h
ADC memory-control register 0 ADC12MCTL0 080h
USART1 Transmit buffer U1TXBUF 07Fh
Receive buffer U1RXBUF 07Eh
Baud rate U1BR1 07Dh
Baud rate U1BR0 07Ch
Modulation control U1MCTL 07Bh
Receive control U1RCTL 07Ah
Transmit control U1TCTL 079h
USART control U1CTL 078h
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
USCI USCI I2C Slave Address UCBI2CSA 011Ah
USCI I2C Own Address UCBI2COA 0118h
USCI Synchronous Transmit Buffer UCBTXBUF 06Fh
USCI Synchronous Receive Buffer UCBRXBUF 06Eh
USCI Synchronous Status UCBSTAT 06Dh
USCI I2C Interrupt Enable UCBI2CIE 06Ch
USCI Synchronous Bit Rate 1 UCBBR1 06Bh
USCI Synchronous Bit Rate 0 UCBBR0 06Ah
USCI Synchronous Control 1 UCBCTL1 069h
USCI Synchronous Control 0 UCBCTL0 068h
USCI Transmit Buffer UCATXBUF 067h
USCI Receive Buffer UCARXBUF 066h
USCI Status UCASTAT 065h
USCI Modulation Control UCAMCTL 064h
USCI Baud Rate 1 UCABR1 063h
USCI Baud Rate 0 UCABR0 062h
USCI Control 1 UCACTL1 061h
USCI Control 0 UCACTL0 060h
USCI IrDA Receive Control UCAIRRCTL 05Fh
USCI IrDA Transmit Control UCAIRTCTL 05Eh
USCI LIN Control UCAABCTL 05Dh
Comparator_A Comparator_A port disable CAPD 05Bh
p
_Comparator_A control 2 CACTL2 05Ah
Comparator_A control 1 CACTL1 059h
BrownOUT, SVS SVS control register (Reset by brownout signal) SVSCTL 056h
FLL+Clock FLL+ Control 1 FLL_CTL1 054h
FLL+ Control 0 FLL_CTL0 053h
System clock frequency control SCFQCTL 052h
System clock frequency integrator SCFI1 051h
System clock frequency integrator SCFI0 050h
RTC (Basic Timer 1) Real Time Clock Year High Byte RTCYEARH 04Fh
()
Real Time Clock Year Low Byte RTCYEARL 04Eh
Real Time Clock Month RTCMON 04Dh
Real Time Clock Day of Month RTCDAY 04Ch
Basic Timer1 Counter 2 BTCNT2 047h
Basic Timer1 Counter 1 BTCNT1 046h
Real Time Counter 4
(Real Time Clock Day of Week) RTCNT4
(RTCDOW) 045h
Real Time Counter 3
(Real Time Clock Hour) RTCNT3
(RTCHOUR) 044h
Real Time Counter 2
(Real Time Clock Minute) RTCNT2
(RTCMIN) 043h
Real Time Counter 1
(Real Time Clock Second) RTCNT1
(RTCSEC) 042h
Real Time Clock Control RTCCTL 041h
Basic Timer1 Control BTCTL 040h
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
Port P10 Port P10 selection P10SEL 00Fh
Port P10 direction P10DIR 00Dh
Port P10 output P10OUT 00Bh
Port P10 input P10IN 009h
Port P9 Port P9 selection P9SEL 00Eh
Port P9 direction P9DIR 00Ch
Port P9 output P9OUT 00Ah
Port P9 input P9IN 008h
Port P8 Port P8 selection P8SEL 03Fh
Port P8 direction P8DIR 03Dh
Port P8 output P8OUT 03Bh
Port P8 input P8IN 039h
Port P7 Port P7 selection P7SEL 03Eh
Port P7 direction P7DIR 03Ch
Port P7 output P7OUT 03Ah
Port P7 input P7IN 038h
Port P6 Port P6 selection P6SEL 037h
Port P6 direction P6DIR 036h
Port P6 output P6OUT 035h
Port P6 input P6IN 034h
Port P5 Port P5 selection P5SEL 033h
Port P5 direction P5DIR 032h
Port P5 output P5OUT 031h
Port P5 input P5IN 030h
Port P4 Port P4 selection P4SEL 01Fh
Port P4 direction P4DIR 01Eh
Port P4 output P4OUT 01Dh
Port P4 input P4IN 01Ch
Port P3 Port P3 selection P3SEL 01Bh
Port P3 direction P3DIR 01Ah
Port P3 output P3OUT 019h
Port P3 input P3IN 018h
Port P2 Port P2 selection P2SEL 02Eh
Port P2 interrupt enable P2IE 02Dh
Port P2 interrupt-edge select P2IES 02Ch
Port P2 interrupt flag P2IFG 02Bh
Port P2 direction P2DIR 02Ah
Port P2 output P2OUT 029h
Port P2 input P2IN 028h
Port P1 Port P1 selection P1SEL 026h
Port P1 interrupt enable P1IE 025h
Port P1 interrupt-edge select P1IES 024h
Port P1 interrupt flag P1IFG 023h
Port P1 direction P1DIR 022h
Port P1 output P1OUT 021h
Port P1 input P1IN 020h
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
Special functions SFR module enable 2 ME2 005h
p
SFR module enable 1 ME1 004h
SFR interrupt flag 2 IFG2 003h
SFR interrupt flag 1 IFG1 002h
SFR interrupt enable 2 IE2 001h
SFR interrupt enable 1 IE1 000h
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Voltage range applied at VCC to VSS −0.3 V to 4.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any pin (see Note) −0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diode current at any device terminal . ±2 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg: Unprogrammed device −55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programmed device −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied
to the TDI/TCLK pin when blowing the JTAG fuse.
recommended operating conditions
MIN NOM MAX UNITS
Supply voltage during program execution (see Note 1),
VCC (AVCC = DVCC1/2 = VCC)MSP430xG461x 1.8 3.6 V
Supply voltage during flash memory programming (see Note 1),
VCC (AVCC = DVCC1/2 = VCC)MSP430FG461x 2.7 3.6 V
Supply voltage during program execution,
SVS enabled and PORON = 1 (see Note 1 and Note 2),
VCC (AVCC = DVCC1/2 = VCC)MSP430xG461x 2 3.6 V
Supply voltage (see Note 1), VSS (AVSS = DVSS1/2 = VSS) 0 0 V
Operating free-air temperature range, TAMSP430xG461x −40 85 °C
LFXT1 t l f f
LF selected, XTS_FLL = 0 Watch crystal 32.768
LFXT1 crystal frequency, f(LFXT1)
(see Note 2)
XT1 selected, XTS_FLL = 1 Ceramic resonator 450 8000 kHz
(
see
N
o
t
e
2)
XT1 selected, XTS_FLL = 1 Crystal 1000 8000
kHz
XT2 crystal frequency f
Ceramic resonator 450 8000
kHz
XT2 crystal frequency, f(XT2) Crystal 1000 8000 kHz
VCC = 1.8 V DC 3.0
Processor frequency (signal MCLK), f
(
S
y
stem
)
VCC = 2.0 V DC 4.6 MHz
Processor
frequency
(signal
MCLK),
f(System)
VCC = 3.6 V DC 8.0
MHz
NOTES: 1. It is recommended to power AVCC and DVCC from the same source. A maximum dif ference of 0.3 V between AVCC and DVCC can
be tolerated during power up and operation.
2. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing the supply
voltage. POR is going inactive when the supply voltage is raised above the minimum supply voltage plus the hysteresis of the SVS
circuitry.
3. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
1.8 3.62.7 3
3.0 MHz
8.0 MHz
Supply Voltage − V
Supply voltage range, MSP430FG461x,
during flash memory programming
Supply voltage range,
MSP430xG461x, during
program execution
2.0
4.6 MHz
fSystem (MHz)
Figure 1. Frequency vs Supply Voltage, Typical Characteristic
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
supply current into AVCC + DVCC excluding external current
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Active mode (see Note 1 and Note 4)
f f 1MH
CG461x
T40°Cto85°C
VCC = 2.2 V 280 370
A
I
()
f(MCLK) = f(SMCLK) = 1 MHz,
f
(ACLK)
= 32
,
768 Hz CG461x TA = −40°C to 85°CVCC = 3 V 470 580 μA
I(AM)
f(ACLK)
=
32
,
768
Hz
XTS=0, SELM=(0,1)
(FG461x: Program executes from
FG461x
T40°Cto85°C
VCC = 2.2 V 400 480
A
(FG461x: Program executes from
flash) FG461x TA = −40°C to 85°CVCC = 3 V 600 740 μA
I
Low-power mode (LPM0) xG461x
T40°Cto85°C
VCC = 2.2 V 45 70
A
I(LPM0)
Low power
mode
(LPM0)
(see Note 1 and Note 4)
xG461x
TA = −40°C to 85°CVCC = 3 V 75 110 μA
I
Low-power mode (LPM2),
f
(MCLK)
= f
(SMCLK)
= 0 MHz,
T40°Cto85°C
VCC = 2.2 V 11 20
A
I(LPM2)
f(MCLK)
=
f
(SMCLK)
=
0
MHz
,
f(ACLK) = 32,768 Hz, SCG0 = 0 (see Note 2 and
Note 4)
TA = −40°C to 85°CVCC = 3 V 17 24 μA
Low power mode (LPM3)
TA = −40°C 1.3 4.0
Low-power mode (LPM3)
f(MCLK)
=
f(SMCLK)
=
0 MHz,
TA = 25°C
V22V
1.3 4.0
f
(MCLK) =
f
(SMCLK) =
0
MHz
,
f
(
ACLK
)
= 32,768 Hz, SCG0 = 1 TA = 60°CVCC = 2.2 V 2.22 6.5
I
f(ACLK)
32,768
Hz,
SCG0
1
Basic Timer1 enabled, ACLK selected
LCD A enabled LCDCPEN 0;
TA = 85°C 6.5 15.0
A
I(LPM3) LCD_A enabled, LCDCPEN = 0;
(static mode; fLCD
=
f(ACLK) /32)
TA = −40°C 1.9 5.0 μA
(static
mode;
f
LCD =
f
(ACLK)
/32)
(see Note 2 and Note 3 and Note 4) TA = 25°C
V3V
1.9 5.0
(see
Note
2
and
Note
3
and
Note
4)
TA = 60°CVCC = 3 V 2.5 7.5
TA = 85°C 7.5 18.0
Low power mode (LPM3)
TA = −40°C 1.5 5.5
Low-power mode (LPM3)
f(MCLK)
=
f(SMCLK)
=
0 MHz,
TA = 25°C
V22V
1.5 5.5
f
(MCLK) =
f
(SMCLK) =
0
MHz
,
f
(
ACLK
)
= 32,768 Hz, SCG0 = 1 TA = 60°CVCC = 2.2 V 2.8 7.0
I
f(ACLK)
32,768
Hz,
SCG0
1
Basic Timer1 enabled, ACLK selected
LCD A enabled LCDCPEN 0;
TA = 85°C 7.2 17.0
A
I(LPM3) LCD_A enabled, LCDCPEN = 0;
(4
−
mux mode; fLCD
=
f(ACLK) /32)
TA = −40°C 2.5 6.5 μA
(4
−
mux
mode;
f
LCD =
f
(ACLK)
/32)
(see Note 2 and Note 3 and Note 4) TA = 25°C
V3V
2.5 6.5
(see
Note
2
and
Note
3
and
Note
4)
TA = 60°CVCC = 3 V 3.2 8.0
TA = 85°C 8.5 20.0
TA = −40°C 0.13 1.0
TA = 25°C
V22V
0.22 1.0
Low-power mode (LPM4)
TA = 60°CVCC = 2.2 V 0.9 2.5
I
L
ow-power mo
d
e
(LPM4)
f
(MCLK)
= 0 MHz, f
(SMCLK)
= 0 MHz, TA = 85°C 4.3 12.5
A
I(LPM4)
f(MCLK)
=
0
MHz
,
f(SMCLK)
=
0
MHz
,
f(ACLK) = 0 Hz, SCG0 = 1
( Nt2 dNt4)
TA = −40°C 0.13 1.6 μA
(ACLK)
(see Note 2 and Note 4) TA = 25°C
V3V
0.3 1.6
TA = 60°CVCC = 3 V 1.1 3.0
TA = 85°C 5.0 15.0
NOTES: 1. Timer_B is clocked by f(DCOCLK) = f(DCO) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
2. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
3. The LPM3 currents are characterized with a Micro Crystal CC4V−T1A (9 pF) crystal and OSCCAPx = 1h.
4. Current for brownout included.
Current consumption of active mode versus system frequency, F version:
I(AM) = I(AM) [1 MHz] × f(System) [MHz]
Current consumption of active mode versus supply voltage, F version:
I(AM) = I(AM) [3 V] + 200 μA/V × (VCC – 3 V)
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Schmitt-trigger inputs − Ports P1 to P10, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
Positive going input threshold voltage
VCC = 2.2 V 1.1 1.55
V
VIT+ Positive-going input threshold voltage VCC = 3 V 1.5 1.98 V
V
Negative going input threshold voltage
VCC = 2.2 V 0.4 0.9
V
VIT− Negative-going input threshold voltage VCC = 3 V 0.9 1.3 V
V
Input voltage hysteresis (V V )
VCC = 2.2 V 0.3 1.1
V
Vhys Input voltage hysteresis (VIT+ − VIT−)VCC = 3 V 0.5 1 V
inputs Px.x, TAx, TBx
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
t
External interrupt timing
Port P1, P2: P1.x to P2.x, external trigger signal 2.2 V 62
ns
t(int) External interrupt timing
Port
P1,
P2:
P1.x
to
P2.x,
external
trigger
signal
for the interrupt flag, (see Note 1) 3 V 50 ns
t
Timer_A, Timer_B capture TA0, TA1, TA2 2.2 V 62
ns
t(cap)
Timer
_
A,
Timer
_
B
capture
timing TB0, TB1, TB2, TB3, TB4, TB5, TB6 3 V 50 ns
f(TAext) Timer_A, Timer_B clock
frequency externally applied
TACLK TBCLK INCLK: t=t
2.2 V 8
MHz
f(TBext) frequency externally applied
to pin TACLK, TBCLK, INCLK: t(H) = t(L) 3 V 10 MHz
f(TAint) Timer_A, Timer_B clock
SMCLK or ACLK signal selected
2.2 V 8
MHz
f(TBint)
Timer
_
A,
Timer
_
B
clock
frequency SMCLK or ACLK signal selected 3 V 10 MHz
NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) parameters are met. It may be set even with trigger signals
shorter than t(int).
leakage current − Ports P1 to P10 (see Note 1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Ilkg(Px.y) Leakage
current Port Px V(Px.y) (see Note 2)
(1 ≤ x ≤ 10, 0 ≤ y ≤ 7) VCC = 2.2 V/3 V ±50 nA
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The port pin must be selected as input.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − Ports P1 to P10
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOH(max) = −1.5 mA, VCC = 2.2 V, See Note 1 VCC−0.25 VCC
V
High level output voltage
IOH(max) = −6 mA, VCC = 2.2 V, See Note 2 VCC−0.6 VCC
V
VOH High-level output voltage IOH(max) = −1.5 mA, VCC = 3 V, See Note 1 VCC−0.25 VCC V
IOH(max) = −6 mA, VCC = 3 V, See Note 2 VCC−0.6 VCC
IOL(max) = 1.5 mA, VCC = 2.2 V, See Note 1 VSS VSS+0.25
V
Low level output voltage
IOL(max) = 6 mA, VCC = 2.2 V, See Note 2 VSS VSS+0.6
V
VOL Low-level output voltage IOL(max) = 1.5 mA, VCC = 3 V, See Note 1 VSS VSS+0.25 V
IOL(max) = 6 mA, VCC = 3 V, See Note 2 VSS VSS+0.6
NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the maximum
specified voltage drop.
2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to satisfy the maximum
specified voltage drop.
output frequency
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
(1 ≤x≤10 0 ≤y≤7)
CL = 20 pF, VCC = 2.2 V DC 10 MHz
f(Px.y) (1 ≤ x ≤ 10, 0 ≤ y ≤ 7)
CL
=
20
pF
,
IL = ±1.5 mA VCC = 3 V DC 12 MHz
f(MCLK) P1.1/TA0/MCLK,
V22V
10
MHz
f(SMCLK) P1.4/TBCLK/SMCLK, CL = 20 pF VCC = 2.2 V 10 MHz
f(ACLK) P1.5/TACLK/ACLK
CL
20
pF
VCC = 3 V DC 12 MHz
P1.5/TACLK/ACLK,
f(ACLK) = f(LFXT1) = f(XT1) 40% 60%
P1
.
5/TACLK/ACLK
,
CL = 20 pF f(ACLK) = f(LFXT1) = f(LF) 30% 70%
CL
20
pF
VCC = 2.2 V / 3 V f(ACLK) = f(LFXT1) 50%
P1.1/TA0/MCLK
,
f(MCLK) = f(XT1) 40% 60%
t(Xdc) Duty cycle of output frequency
P1
.
1/TA0/MCLK
,
CL = 20 pF,
VCC = 2.2 V / 3 V f(MCLK) = f(DCOCLK) 50%−
15 ns 50% 50%+
15 ns
P1.4/TBCLK/SMCLK
,
f(SMCLK) = f(XT2) 40% 60%
P1
.
4/TBCLK/SMCLK
,
CL = 20 pF,
VCC = 2.2 V / 3 V f(SMCLK) = f(DCOCLK) 50%−
15 ns 50% 50%+
15 ns
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics − outputs
Figure 2
VOL − Low-Level Output Voltage − V
0.0
5.0
10.0
15.0
20.0
25.0
0.0 0.5 1.0 1.5 2.0 2.5
VCC = 2.2 V
P2.0
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
OL
I − Typical Low-Level Output Current − mA
Figure 3
VOL − Low-Level Output Voltage − V
0.0
10.0
20.0
30.0
40.0
50.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCC = 3 V
P2.0
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
OL
I − Typical Low-Level Output Current − mA
Figure 4
VOH − High-Level Output Voltage − V
−25.0
−20.0
−15.0
−10.0
−5.0
0.0
0.0 0.5 1.0 1.5 2.0 2.5
VCC = 2.2 V
P2.0
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
OH
I − Typical High-Level Output Current − mA
Figure 5
VOH − High-Level Output Voltage − V
−50.0
−40.0
−30.0
−20.0
−10.0
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCC = 3 V
P2.0
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
OH
I − Typical High-Level Output Current − mA
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
wake-up LPM3
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f = 1 MHz 6
td
(
LPM3
)
Delay time f = 2 MHz VCC = 2.2 V/3 V 6μs
td(LPM3)
Delay
time
f = 3 MHz
VCC
2.2
V/3
V
6
μs
RAM
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRAMh CPU halted (see Note 1) 1.6 V
NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution
should take place during this supply voltage condition.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
LCD_A
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VCC(LCD) Supply voltage (see Note 2) Charge pump enabled
(LCDCPEN = 1; VLCDx > 0000) 2.2 3.6 V
ICC(LCD) Supply current (see Note 2 )
VLCD(typ)=3 V; LCDCPEN = 1,
VLCDx= 1000; all segments on,
fLCD = fACLK/32,
no LCD connected (see Note 4)
TA = 25°C
2.2 V 3μA
CLCD Capacitor on LCDCAP
(see Note 1 and Note 3) Charge pump enabled
(LCDCPEN = 1; VLCDx > 0000) 4.7 μF
fLCD LCD frequency 1.1 kHz
VLCDx = 0000 VCC
VLCDx = 0001 2.60
VLCDx = 0010 2.66
VLCDx = 0011 2.72
VLCDx = 0100 2.78
VLCDx = 0101 2.84
VLCDx = 0110 2.90
V
LCD voltage (see Note 3)
VLCDx = 0111 2.96
V
VLCD LCD voltage (see Note 3) VLCDx = 1000 3.02 V
VLCDx = 1001 3.08
VLCDx = 1010 3.14
VLCDx = 1011 3.20
VLCDx = 1100 3.26
VLCDx = 1101 3.32
VLCDx = 1110 3.38
VLCDx = 1111 3.44 3.60
RLCD LCD driver output impedance VLCD=3 V; CPEN = 1;
VLCDx = 1000, ILOAD = 10 μΑ 2.2 V 10 kΩ
NOTES: 1. Enabling the internal charge pump with an external capacitor smaller than the minimum specified might damage the device.
2. Refer to the supply current specifications I(LPM3) for additional current specifications with the LCD_A module active.
3. Segments S 0 through S3 are disabled when the LCD charge pump feature is enabled (LCDCPEN = 1) and cannot be used together
with the LCD charge pump. In addition, when using segments S0 through S3 with an external LCD voltage supply, VLCD ≤AVCC.
4. Connecting an actual display will increase the current consumption depending on the size of the LCD.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Comparator_A (see Note 1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
CAON 1 CARSEL 0 CAREF 0
VCC = 2.2 V 25 40
A
I(CC) CAON=1, CARSEL=0, CAREF=0 VCC = 3 V 45 60 μA
I
CAON=1, CARSEL=0, CAREF=1/2/3,
No load at P1 6/CA0 and
VCC = 2.2 V 30 50
A
I(Refladder/RefDiode) No load at P1.6/CA0 and
P1.7/CA1 VCC = 3 V 45 71 μA
V(Ref025) Voltage @ 0.25 VCC node
VCC
PCA0=1, CARSEL=1, CAREF=1,
No load at P1.6/CA0 and P1.7/CA1 VCC = 2.2 V / 3 V 0.23 0.24 0.25
V(Ref050) Voltage @ 0.5 VCC node
VCC
PCA0=1, CARSEL=1, CAREF=2,
No load at P1.6/CA0 and P1.7/CA1 VCC = 2.2V / 3 V 0.47 0.48 0.5
V
PCA0=1, CARSEL=1, CAREF=3,
No load at P1 6/CA0 and P1 7/CA1;
VCC = 2.2 V 390 480 540
mV
V(RefVT) No load at P1.6/CA0 and P1.7/CA1;
TA = 85°CVCC = 3 V 400 490 550 mV
VIC Common-mode input
voltage range CAON=1 VCC = 2.2 V / 3 V 0 VCC−1 V
Vp−VSOffset voltage See Note 2 VCC = 2.2 V / 3 V −30 30 mV
Vhys Input hysteresis CAON = 1 VCC = 2.2 V / 3 V 0 0.7 1.4 mV
TA = 25°C, VCC = 2.2 V 160 210 300
ns
t
TA
=
25 C
,
Overdrive 10 mV, without filter: CAF = 0 VCC = 3 V 80 150 240 ns
t(response LH) TA = 25°CVCC = 2.2 V 1.4 1.9 3.4
s
TA
=
25 C
Overdrive 10 mV, with filter: CAF = 1 VCC = 3 V 0.9 1.5 2.6 μs
TA = 25°CVCC = 2.2 V 130 210 300
ns
t
TA
=
25 C
Overdrive 10 mV, without filter: CAF = 0 VCC = 3 V 80 150 240 ns
t(response HL) TA = 25°C, VCC = 2.2 V 1.4 1.9 3.4
s
TA
=
25 C
,
Overdrive 10 mV, with filter: CAF = 1 VCC = 3 V 0.9 1.5 2.6 μs
NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification.
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical characteristics
TA − Free-Air Temperature − °C
400
450
500
550
600
650
−45 −25 −5 15 35 55 75 95
VCC = 3 V
Figure 6. V
(
RefVT
)
vs Temperature
VREF − Reference Voltage − mV
Typical
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
Figure 7. V
(
RefVT
)
vs Temperature
TA − Free-Air Temperature − °C
400
450
500
550
600
650
−45 −25 −5 15 35 55 75 95
VCC = 2.2 V
Typical
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
VREF − Reference Voltage − mV
_
+
CAON
0
1
V+ 0
1
CAF
Low-Pass Filter
τ ≈ 2 μs
To Internal
Modules
Set CAIFG
Flag
CAOUT
V−
VCC
1
0 V
0
Figure 8. Block Diagram of Comparator_A Module
Overdrive VCAOUT
t(response)
V+
V−
400 mV
Figure 9. Overdrive Definition
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
POR/brownout reset (BOR) (see Note 1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(BOR) 2000 μs
VCC(start) dVCC/dt ≤ 3 V/s (see Figure 10) 0.7 × V(B_IT−) V
V(B_IT−) Brownout dVCC/dt ≤ 3 V/s (see Figure 10 through Figure 12) 1.79 V
Vhys(B_IT−) (see Notes 2 and 3) dVCC/dt ≤ 3 V/s (see Figure 10) 70 130 210 mV
t(reset) Pulse length needed at RST/NMI pin to accepted reset
internally, VCC = 2.2 V/3 V 2μs
NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data.
2. The voltage level V(B_IT−) + Vhys(B_IT−) is ≤ 1.89V.
3. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT−) + Vhys(B_IT−). The default
FLL+ settings must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired
operating frequency. See the MSP430x4xx Family User’s Guide for more information on the brownout/SVS circuit.
typical characteristics
0
1
td(BOR)
VCC
V(B_IT−)
Vhys(B_IT−)
VCC(start)
Figure 10. POR/Brownout Reset (BOR) vs Supply Voltage
VCC(drop)
VCC
3 V tpw
0
0.5
1
1.5
2
0.001 1 1000
Typical Conditions
1 ns 1 ns
tpw − Pulse Width − μst
pw − Pulse Width − μs
VCC = 3 V
VCC(drop)− V
Figure 11. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical characteristics (continued) VCC
0
0.5
1
1.5
2
VCC(drop)
tpw
tpw − Pulse Width − μs
VCC(drop)− V
3 V
0.001 1 1000 tftr
tpw − Pulse Width − μs
tf = tr
Typical Conditions
VCC = 3 V
Figure 12. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
SVS (supply voltage supervisor/monitor) (see Note 1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
dVCC/dt > 30 V/ms (see Figure 13) 5 150
μs
t(SVSR) dVCC/dt ≤ 30 V/ms 2000 μs
td(SVSon) SVS on, switch from VLD = 0 to VLD ≠ 0, VCC = 3 V 150 300 μs
tsettle VLD ≠ 0‡12 μs
V(SVSstart) VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 13) 1.55 1.7 V
VLD = 1 70 120 155 mV
Vh
y
s
(
SVS_IT−
)
VCC/dt ≤ 3 V/s (see Figure 13) VLD = 2 .. 14 V(SVS_IT−)
x 0.001 V(SVS_IT−)
x 0.016
Vhys(SVS
_
IT
−
)
VCC/dt ≤ 3 V/s (see Figure 13), external voltage applied
on A7 VLD = 15 4.4 20 mV
VLD = 1 1.8 1.9 2.05
VLD = 2 1.94 2.1 2.23
VLD = 3 2.05 2.2 2.35
VLD = 4 2.14 2.3 2.46
VLD = 5 2.24 2.4 2.58
VLD = 6 2.33 2.5 2.69
V/dt ≤3 V/s (see Figure 13)
VLD = 7 2.46 2.65 2.84
V(SVS IT )
VCC/dt ≤ 3 V/s (see Figure 13) VLD = 8 2.58 2.8 2.97
V
V
(SVS_IT−) VLD = 9 2.69 2.9 3.10
V
VLD = 10 2.83 3.05 3.26
VLD = 11 2.94 3.2 3.39
VLD = 12 3.11 3.35 3.58†
VLD = 13 3.24 3.5 3.73†
VLD = 14 3.43 3.7†3.96†
VCC/dt ≤ 3 V/s (see Figure 13), external voltage applied
on A7 VLD = 15 1.1 1.2 1.3
ICC(SVS)
(see Note 1) VLD ≠ 0, VCC = 2.2 V/3 V 10 15 μA
†The recommended operating voltage range is limited to 3.6 V.
‡tsettle is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value somewhere
between 2 and 15. The overdrive is assumed to be > 50 mV.
NOTE 1: The current consumption of the SVS module is not included in the ICC current consumption data.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
41
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical characteristics
VCC(start)
VCC
V(B_IT−)
Brownout
Region
V(SVSstart)
V(SVS_IT−)
Software Sets VLD>0:
SVS is Active
td(SVSR)
undefined
Vhys(SVS_IT−)
0
1
td(BOR)
Brownout
0
1
td(SVSon)
td(BOR)
0
1
Set POR
Brown-
Out
Region
SVS Circuit is Active From VLD > to VCC < V(B_IT−)
SVSOut
Vhys(B_IT−)
Figure 13. SVS Reset (SVSR) vs Supply Voltage
0
0.5
1
1.5
2
VCC
VCC
1 ns 1 ns
tpw
tpw − Pulse Width − μs
3 V
1 10 1000
tftr
t − Pulse Width − μs
100
tpw
3 V
tf = tr
Rectangular Drop
Triangular Drop
VCC(drop)
VCC(drop)− V
VCC(drop)
Figure 14. VCC(drop) With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
DCO
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
f(DCOCLK) N(DCO)=01Eh, FN_8=FN_4=FN_3=FN_2=0, D = 2; DCOPLUS= 0 2.2 V/3 V 1 MHz
f
FN 8 FN 4 FN 3 FN 2 0 ; DCOPLUS 1
2.2 V 0.3 0.65 1.25
MHz
f(DCO=2) FN_8=FN_4=FN_3=FN_2=0 ; DCOPLUS = 1 3 V 0.3 0.7 1.3 MHz
f
FN 8 FN 4 FN 3 FN 2 0; DCOPLUS 1
2.2 V 2.5 5.6 10.5
MHz
f(DCO=27) FN_8=FN_4=FN_3=FN_2=0; DCOPLUS = 1 3 V 2.7 6.1 11.3 MHz
f
FN 8 FN 4 FN 3 0 FN 2 1; DCOPLUS 1
2.2 V 0.7 1.3 2.3
MHz
f(DCO=2) FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1 3 V 0.8 1.5 2.5 MHz
f
FN 8 FN 4 FN 3 0 FN 2 1; DCOPLUS 1
2.2 V 5.7 10.8 18
MHz
f(DCO=27) FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1 3 V 6.5 12.1 20 MHz
f
FN 8 FN 4 0 FN 3 1 FN 2 x; DCOPLUS 1
2.2 V 1.2 2 3
MHz
f(DCO=2) FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1 3 V 1.3 2.2 3.5 MHz
f
FN 8 FN 4 0 FN 3 1 FN 2 x; DCOPLUS 1
2.2 V 9 15.5 25
MHz
f(DCO=27) FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1 3 V 10.3 17.9 28.5 MHz
f
FN 8 0 FN 4 1 FN 3 FN 2 x; DCOPLUS 1
2.2 V 1.8 2.8 4.2
MHz
f(DCO=2) FN_8=0, FN_4= 1, FN_3= FN_2=x; DCOPLUS = 1 3 V 2.1 3.4 5.2 MHz
f
FN 8 0 FN 4 1 FN 3 FN 2 x; DCOPLUS 1
2.2 V 13.5 21.5 33
MHz
f(DCO=27) FN_8=0, FN_4=1, FN_3= FN_2=x; DCOPLUS = 1 3 V 16 26.6 41 MHz
f
FN 8 1 FN 4 FN 3 FN 2 x; DCOPLUS 1
2.2 V 2.8 4.2 6.2
MHz
f(DCO=2) FN_8=1, FN_4=FN_3=FN_2=x; DCOPLUS = 1 3 V 4.2 6.3 9.2 MHz
f
FN 8 1 FN 4 FN 3 FN 2 x; DCOPLUS 1
2.2 V 21 32 46
MHz
f(DCO=27) FN_8=1,FN_4=FN_3=FN_2=x; DCOPLUS = 1 3 V 30 46 70 MHz
S
Step size between adjacent DCO taps: 1 < TAP ≤ 20 1.06 1.11
Sn
Step
size
between
adjacent
DCO
taps:
Sn = fDCO(Tap n+1) / fDCO(Tap n) (see Figure 16 for taps 21 to 27) TAP = 27 1.07 1.17
D
Temperature drift, N
(
D
CO)
= 01Eh, FN_8=FN_4=FN_3=FN_2=0 2.2 V –0.2 –0.3 –0.4
%/_C
Dt
Temperature
drift
,
N(DCO)
=
01Eh
,
FN
_
8=FN
_
4=FN
_
3=FN
_
2=0
D = 2; DCOPLUS = 0 3 V –0.2 –0.3 –0.4 %/_C
DVDrift with VCC variation, N(DCO) = 01Eh, FN_8=FN_4=FN_3=FN_2=0
D = 2; DCOPLUS = 0 0 5 15 %/V
TA − °CVCC − V
f(DCO)
f(DCO205C)
f(DCO)
f(DCO3V)
1.8 3.02.4 3.6
1.0
20 6040 85
1.0
0−20−400
Figure 15. DCO Frequency vs Supply Voltage VCC and vs Ambient Temperature
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
43
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
12720
1.11
1.17
DCO Tap
Sn - Stepsize Ratio between DCO Taps
Min
Max
1.07
1.06
Figure 16. DCO Tap Step Size
DCO Frequency
Adjusted by Bits
29 to 25 in SCFI1 {N{DCO}}
FN_2=0
FN_3=0
FN_4=0
FN_8=0
FN_2=1
FN_3=0
FN_4=0
FN_8=0
FN_2=x
FN_3=1
FN_4=0
FN_8=0
FN_2=x
FN_3=x
FN_4=1
FN_8=0
FN_2=x
FN_3=x
FN_4=x
FN_8=1
Legend
Tolerance at Tap 27
Tolerance at Tap 2
Overlapping DCO Ranges:
Uninterrupted Frequency Range
f(DCO)
Figure 17. Five Overlapping DCO Ranges Controlled by FN_x Bits
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
44 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
crystal oscillator, LFXT1 oscillator (see Notes 1 and 2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OSCCAPx = 0h, VCC = 2.2 V / 3 V 0
C
Inte
g
rated input capacitance OSCCAPx = 1h, VCC = 2.2 V / 3 V 10
pF
CXIN
Integrated
input
capacitance
(see Note 4) OSCCAPx = 2h, VCC = 2.2 V / 3 V 14 pF
OSCCAPx = 3h, VCC = 2.2 V / 3 V 18
OSCCAPx = 0h, VCC = 2.2 V / 3 V 0
C
Inte
g
rated output capacitance OSCCAPx = 1h, VCC = 2.2 V / 3 V 10
pF
CXOUT
Integrated
output
capacitance
(see Note 4) OSCCAPx = 2h, VCC = 2.2 V / 3 V 14 pF
OSCCAPx = 3h, VCC = 2.2 V / 3 V 18
VIL
Input levels at XIN
V2 2 V/3 V (see Note 3)
VSS 0.2×VCC
V
VIH Input levels at XIN VCC = 2.2 V/3 V (see Note 3) 0.8×VCC VCC V
NOTES: 1. The parasitic capacitance from the package and board may be estimated to be 2 pF. The effective load capacitor for the crystal is
(CXIN xC
XOUT) / (CXIN + CXOUT). This is independent of XTS_FLL.
2. To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines should be observed.
− Keep the trace between the device and the crystal as short as possible.
− Design a good ground plane around the oscillator pins.
− Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
− Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
− Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
− If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
− Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
3. Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or resonator .
4. External capacitance is recommended for precision real-time clock applications; OSCCAPx = 0h.
crystal oscillator, XT2 oscillator (see Note 1)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
CXT2IN Integrated input capacitance VCC = 2.2 V/3 V 2 pF
CXT2OUT Integrated output capacitance VCC = 2.2 V/3 V 2 pF
VIL
Input levels at XT2IN
VCC = 2 2 V/3 V (see Note 2)
VSS 0.2 × VCC V
VIH Input levels at XT2IN VCC = 2.2 V/3 V (see Note 2) 0.8 × VCC VCC V
NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
45
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (UART mode)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fUSCI USCI input clock frequency Internal: SMCLK, ACLK
External: UCLK
Duty Cycle = 50% ± 10% fSYSTEM MHz
fBITCLK BITCLK clock frequency
(equals Baudrate in MBaud) 2.2V /3 V 1 MHz
t
UART receive de
g
litch time 2.2 V 50 150 600
ns
tτ
UART
receive
deglitch
time
(see Note 1) 3 V 50 100 600 ns
NOTE 1: Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
USCI (SPI master mode) (see Figure 18 and Figure 19)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fUSCI USCI input clock frequency SMCLK, ACLK
Duty Cycle = 50% ± 10% fSYSTEM MHz
t
SOMI input data setup time
2.2 V 110
ns
tSU,MI SOMI input data setup time 3 V 75 ns
t
SOMI input data hold time
2.2 V 0
ns
tHD,MI SOMI input data hold time 3 V 0ns
t
SIMO output data valid time
UCLK ed
g
e to SIMO valid; 2.2 V 30
ns
tVALID,MO SIMO output data valid time
UCLK
edge
to
SIMO
valid;
CL = 20 pF 3 V 20 ns
USCI (SPI slave mode) (see Figure 20 and Figure 21)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
tSTE,LEAD STE lead time
STE low to clock 2.2 V/3 V 50 ns
tSTE,LAG STE lag time
Last clock to STE high 2.2 V/3 V 10 ns
tSTE,ACC STE access time
STE low to SOMI data out 2.2 V/3 V 50 ns
tSTE,DIS STE disable time
STE high to SOMI high impedance 2.2 V/3 V 50 ns
t
SIMO input data setup time
2.2 V 20
ns
tSU,SI SIMO input data setup time 3 V 15 ns
t
SIMO input data hold time
2.2 V 10
ns
tHD,SI SIMO input data hold time 3 V 10 ns
t
SOMI output data valid time
UCLK ed
g
e to SOMI valid; 2.2 V 75 110
ns
tVALID,SO SOMI output data valid time
UCLK
edge
to
SOMI
valid;
CL = 20 pF 3 V 50 75 ns
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
46 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
UCLK
CKPL = 0
CKPL = 1
SIMO
1/fUCxCLK
tLOW/HIGH tLOW/HIGH
SOMI
tSU,MI
tHD,MI
tVALID,MO
Figure 18. SPI Master Mode, CKPH = 0
UCLK
CKPL = 0
CKPL = 1
SIMO
1/fUCxCLK
tLOW/HIGH tLOW/HIGH
SOMI
tSU,MI tHD,MI
tVALID,MO
Figure 19. SPI Master Mode, CKPH = 1
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
47
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
STE
UCLK
CKPL = 0
CKPL = 1
SOMI
tACC tDIS
1/fUCxCLK
tLOW/HIGH tLOW/HIGH
SIMO
tSU,SIMO
tHD,SIMO
tVALID,SOMI
tSTE,LEAD tSTE,LAG
Figure 20. SPI Slave Mode, CKPH = 0
STE
UCLK
CKPL=0
CKPL=1
tSTE,LEAD tSTE,LAG
tACC tDIS
tLOW/HIGH tLOW/HIGH
tSU,SI tHD,SI
tVALID,SO
SOMI
SIMO
1/fUCxCLK
Figure 21. SPI Slave Mode, CKPH = 1
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
48 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (I2C mode) (see Figure 22)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fUSCI USCI input clock frequency Internal: SMCLK, ACLK
External: UCLK
Duty Cycle = 50% ± 10% fSYSTEM MHz
fSCL SCL clock frequency 2.2 V/3 V 0 400 kHz
t
Hold time (repeated) START
fSCL ≤ 100kHz 2.2 V/3 V 4.0
s
tHD,STA Hold time (repeated) START fSCL > 100kHz 2.2 V/3 V 0.6 μs
t
Set up time for a repeated START
fSCL ≤ 100kHz 2.2 V/3 V 4.7
s
tSU,STA Set−up time for a repeated START fSCL > 100kHz 2.2 V/3 V 0.6 μs
tHD,DAT Data hold time 2.2 V/3 V 0 ns
tSU,DAT Data set−up time 2.2 V/3 V 250 ns
tSU,STO Set−up time for STOP 2.2 V/3 V 4.0 μs
t
Pulse width of spikes suppressed b
y
2.2 V 50 150 600
ns
tSP
Pulse
width
of
spikes
suppressed
by
input filter 3 V 50 100 600 ns
SDA
SCL
tLOW
tHD ,DAT
tSU ,DAT
tHD ,STA tSU ,STA tHD ,STA
tHIGH
tSU ,STO
tSP
tBUF
Figure 22. I2C Mode Timing
USART1 (see Note 1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
USART1 deglitch time
VCC = 2.2 V, SYNC = 0, UART mode 200 430 800
ns
t(τ)USART1 deglitch time VCC = 3 V, SYNC = 0, UART mode 150 280 500 ns
NOTE 1: The signal applied to the USART1 receive signal/terminal (URXD1) should meet the timing requirements of t(τ) to ensure that the URXS
flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(τ). The operating conditions to
set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the
URXD1 line.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
49
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, power supply and input range conditions (see Note 1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AVCC Analog supply voltage AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V 2.2 3.6 V
V(P6.x/Ax) Analog input voltage
range (see Note 2)
All external Ax terminals. Analog inputs
selected in ADC12MCTLx register and P6Sel.x=1,
V(AVSS) ≤ VAx ≤ V(AVCC) 0 VAVCC V
I
Operating supply current
into AV terminal
fADC12CLK = 5.0 MHz,
ADC12ON 1 REFON 0
VCC = 2.2 V 0.65 1.3
mA
IADC12 into AVCC terminal
(see Note 3) ADC12ON = 1, REFON = 0,
SHT0=0, SHT1=0, ADC12DIV=0 VCC = 3 V 0.8 1.6 mA
I
Operating supply current
it AV til
fADC12CLK = 5.0 MHz,
ADC12ON = 0,
REFON = 1, REF2_5V = 1 VCC = 3 V 0.5 0.8 mA
IREF+ into AVCC terminal
(see Note 4) fADC12CLK = 5.0 MHz,
ADC12ON 0
VCC = 2.2 V 0.5 0.8
mA
(see
Note
4)
ADC12ON = 0,
REFON = 1, REF2_5V = 0 VCC = 3 V 0.5 0.8 mA
CIInput capacitance Only one terminal can be selected
at one time, Ax VCC = 2.2 V 40 pF
RIInput MUX ON resistance 0V ≤ VAx ≤ VAVCC VCC = 3 V 2000 Ω
NOTES: 1. The leakage current is defined in the leakage current table with Ax parameter.
2. The analog input voltage range must be within the selected reference voltage range VR+ to VR− for valid conversion results.
3. The internal reference supply current is not included in current consumption parameter IADC12.
4. The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
12-bit ADC, external reference (see Note 1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VeREF+ Positive external
reference voltage input VeREF+ > VREF−/VeREF−, (see Note 2) 1.4 VAVCC V
VREF− /VeREF− Negative external
reference voltage input VeREF+ > VREF−/VeREF−, (see Note 3) 0 1.2 V
(VeREF+ −
VREF−/VeREF−)Differential external
reference voltage input VeREF+ > VREF−/VeREF−, (see Note 4) 1.4 VAVCC V
IVeREF+ Input leakage current 0V ≤VeREF+ ≤ VAVCC VCC = 2.2 V/3 V ±1μA
IVREF−/VeREF− Input leakage current 0V ≤ VeREF− ≤ VAVCC VCC = 2.2 V/3 V ±1μA
NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
3. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
4. The accuracy limits minimum external dif ferential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
50 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, built-in reference
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
V
Positive built-in reference REF2_5V = 1 for 2.5 V,
IVREF+max ≤IVREF+≤IVREF+min VCC = 3 V 2.4 2.5 2.6
V
VREF+
Positive
built in
reference
voltage output REF2_5V = 0 for 1.5 V,
IVREF+max ≤IVREF+≤IVREF+min VCC =
2.2 V/3 V 1.44 1.5 1.56 V
AVCC minimum voltage,
REF2_5V = 0, IVREF+max ≤IVREF+ ≤IVREF+min 2.2
AVCC
(
min
)
AV
CC
minimum
voltage
,
Positive built-in reference REF2_5V = 1, IVREF+min ≥IVREF+ ≥−0.5mA 2.8 V
AVCC(min)
Positive
built in
reference
active REF2_5V = 1, IVREF+min ≥IVREF+ ≥ −1mA 2.9
V
I
Load current out of VREF+ VCC = 2.2 V 0.01 −0.5
mA
IVREF+
Load
current
out
of
VREF
+
terminal VCC = 3 V 0.01 −1 mA
IVREF+ = 500 μA +/− 100 μA,
Analog input voltage 0 75 V;
VCC = 2.2 V ±2
LSB
I
Load-current re
g
ulation Analog input voltage ~0.75 V;
REF2_5V = 0 VCC = 3 V ±2LSB
IL(VREF)+
Load current
regulation
VREF+ terminal IVREF+ = 500 μA ± 100 μA,
Analog input voltage ~1.25 V,
REF2_5V = 1 VCC = 3 V ±2 LSB
I
Load current re
g
ulation IVREF+ =100 μA → 900 μA,
C 5 μFax 05xV
V3V
20
ns
IDL(VREF) +
Load
current
regulation
VREF+ terminal CVREF+=5 μF, ax ~0.5 x VREF+,
Error of conversion result ≤ 1 LSB VCC = 3 V 20 ns
CVREF+ Capacitance at pin VREF+
(see Note 1) REFON =1,
0 mA ≤ IVREF+ ≤IVREF+max VCC =
2.2 V/3 V 5 10 μF
TREF+ Temperature coefficient of
built-in reference IVREF+ is a constant in the range of
0 mA ≤ IVREF+ ≤ 1 mA VCC =
2.2 V/3 V ±100 ppm/°C
tREFON
Settle time of internal
reference voltage (see
Figure 23 and Note 2)
IVREF+ = 0.5 mA, CVREF+ = 10 μF,
VREF+ = 1.5 V, V AVCC = 2.2 V 17 ms
NOTES: 1. The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses
two capacitors between pins VREF+ and AVSS and VREF−/VeREF− and AVSS: 10 μF tantalum and 100 nF ceramic.
2. The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load.
CVREF+
1 μF
01 ms 10 ms 100 ms tREFON
tREFON ≈.66 x CVREF+ [ms] with CVREF+ in μF
100 μF
10 μF
Figure 23. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
51
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
+
−
10 μF 100 nF AVSS
MSP430FG461x
+
−
+
−
10 μF 100 nF
10 μF 100 nF
AVCC
10 μF 100 nF DVSS1/2
DVCC1/2
From
Power
Supply
Apply
External
Reference
+
−
Apply External Reference [VeREF+]
or Use Internal Reference [VREF+]VREF+ or VeREF+
VREF−/VeREF−
Figure 24. Supply Voltage and Reference Voltage Design VREF−/VeREF− External Supply
+
−
10 μF 100 nF AVSS
MSP430FG461x
+
−
10 μF 100 nF
AVCC
10 μF 100 nF DVSS1/2
DVCC1/2
From
Power
Supply +
−
Apply External Reference [VeREF+]
or Use Internal Reference [VREF+]VREF+ or VeREF+
VREF−/VeREF−
Reference Is Internally
Switched to AVSS
Figure 25. Supply Voltage and Reference Voltage Design VREF−/VeREF− = AVSS, Internally Connected
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
52 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, timing parameters
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
fADC12CLK For specified performance of
ADC12 linearity parameters VCC = 2.2V/3 V 0.45 5 6.3 MHz
fADC12OSC Internal ADC12
oscillator ADC12DIV=0,
fADC12CLK=fADC12OSC VCC = 2.2 V/ 3 V 3.7 5 6.3 MHz
t
Conversion time
CVREF+ ≥ 5 μF, Internal oscillator,
fADC12OSC = 3.7 MHz to 6.3 MHz VCC = 2.2 V/ 3 V 2.06 3.51 μs
tCONVERT Conversion time External fADC12CLK from ACLK, MCLK, or SMCLK,
ADC12SSEL ≠ 0 13×ADC12DIV×
1/fADC12CLK μs
tADC12ON Turn on settling time
of the ADC (see Note 1) 100 ns
t
Sampling time
RS = 400 Ω, RI = 1000 Ω,
C30 pF τ[R +R]xC
VCC = 3 V 1220
ns
tSample Sampling time CI = 30 pF, τ = [RS + RI] x CI,
(see Note 2) VCC = 2.2 V 1400 ns
NOTES: 1. The condition is that the error in a conversion started after t ADC12ON is less than ±0.5 LSB. The reference and input signal are already
settled.
2. Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) x (RS + RI) x CI+ 800 ns where n = ADC resolution = 12, RS = external source resistance.
12-bit ADC, linearity parameters
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
E
Integral linearity error
1.4 V ≤ (VeREF+ − VREF−/VeREF−) min ≤ 1.6 V V
CC
= ±2
LSB
EIIntegral linearity error 1.6 V < (V eREF+ − VREF−/VeREF−) min ≤ [VAVCC]
VCC
=
2.2 V/3 V ±1.7 LSB
EDDifferential linearity
error (VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−),
CVREF+ = 10 μF (tantalum) and 100 nF (ceramic) VCC =
2.2 V/3 V ±1 LSB
EOOffset error (VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−),
Internal impedance of source RS < 100 Ω,
CVREF+ = 10 μF (tantalum) and 100 nF (ceramic)
VCC =
2.2 V/3 V ±2±4 LSB
EGGain error (VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−),
CVREF+ = 10 μF (tantalum) and 100 nF (ceramic) VCC =
2.2 V/3 V ±1.1 ±2 LSB
ETTotal unadjusted
error (VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−),
CVREF+ = 10 μF (tantalum) and 100 nF (ceramic) VCC =
2.2 V/3 V ±2±5 LSB
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
53
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, temperature sensor and built-in VMID
PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT
I
Operatin
g
suppl
y
current into REFON = 0, INCH = 0Ah, 2.2 V 40 120
A
ISENSOR
Operating
supply
current
into
AVCC terminal (see Note 1)
REFON
=
0
,
INCH
=
0Ah
,
ADC12ON=NA, TA = 25_C3 V 60 160 μA
V
(see Note 2)
ADC12ON = 1, INCH = 0Ah, 2.2 V/
986
mV
VSENSOR (see Note 2)
ADC12ON
=
1
,
INCH
=
0Ah
,
TA = 0°C
2
.
2
V/
3 V 986 mV
TC
ADC12ON 1 INCH 0Ah
2.2 V/
355±3%
mV/°C
TCSENSOR ADC12ON = 1, INCH = 0Ah
2
.
2
V/
3 V 3.55±3% mV/°C
t
Sample time required if
channel 10 is selected
ADC12ON = 1, INCH = 0Ah, 2.2 V 30
s
tSENSOR(sample) channel 10 is selected
(see Note 3)
ADC12ON
=
1
,
INCH
=
0Ah
,
Error of conversion result ≤1 LSB 3 V 30 μs
I
Current into divider at
ADC12ON 1 INCH 0Bh
2.2 V NA
A
IVMID
Current
into
divider
at
channel 11 (see Note 4) ADC12ON = 1, INCH = 0Bh 3 V NA μA
V
AV divider at channel 11
ADC12ON = 1, INCH = 0Bh, 2.2 V 1.1 1.1±0.04
V
VMID AVCC divider at channel 11
ADC12ON
=
1
,
INCH
=
0Bh
,
VMID is ~0.5 x VAVCC 3 V 1.5 1.50±0.04 V
t
Sample time required if
channel 11 is selected
ADC12ON = 1, INCH = 0Bh, 2.2 V 1400
ns
tVMID(sample) channel 11 is selected
(see Note 5)
ADC12ON
=
1
,
INCH
=
0Bh
,
Error of conversion result ≤ 1 LSB 3 V 1220 ns
NOTES: 1. The sensor current ISENSOR is consumed if (ADC12ON = 1 and REFON=1), or (ADC12ON=1 AND INCH=0Ah and sample signal
is high). When REFON = 1, ISENSOR is already included in IREF+.
2. The temperature sensor of fset can be as much as ±20_C. A single-point calibration is recommended in order to minimize the offset
error of the built-in temperature sensor.
3. The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on)
4. No additional current is needed. The VMID is used during sampling.
5. The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
12-bit DAC, supply specifications
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
AVCC Analog supply voltage AVCC = DVCC,
AVSS = DVSS =0 V 2.20 3.60 V
DAC12AMPx=2, DAC12IR=0,
DAC12_xDAT=0800h 50 110
I
Supply current:
Single DAC Channel
DAC12AMPx=2, DAC12IR=1,
DAC12_xDAT=0800h , VeREF+=VREF+= AVCC
2 2 V/3 V
50 110
A
IDD Single DAC Channel
(see Notes 1 and 2) DAC12AMPx=5, DAC12IR=1,
DAC12_xDAT=0800h, VeREF+=VREF+= AVCC
2.2 V/3 V 200 440
μA
DAC12AMPx=7, DAC12IR=1,
DAC12_xDAT=0800h, VeREF+=VREF+= AVCC 700 1500
PSRR
Power-supply
rejection ratio
DAC12_xDAT = 800h, VREF = 1.5 V,
ΔAVCC = 100mV 2.2 V
70
dB
PSRR rejection ratio
(see Notes 3 and 4) DAC12_xDAT = 800h, VREF = 1.5 V or 2.5 V,
ΔAVCC = 100mV 3 V 70 dB
NOTES: 1. No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly.
2. Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input
specifications.
3. PSRR = 20*log{ΔAVCC/ΔVDAC12_xOUT}.
4. VREF is applied externally. The internal reference is not used.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
54 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, linearity specifications (see Figure 26)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Resolution (12-bit Monotonic) 12 bits
INL
Integral nonlinearity Vref = 1.5 V,
DAC12AMPx = 7, DAC12IR = 1 2.2 V
±20
±80
LSB
INL
Integral
nonlinearity
(see Note 1) Vref = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1 3 V
±2.0 ±8.0 LSB
DNL
Differential nonlinearity Vref = 1.5 V,
DAC12AMPx = 7, DAC12IR = 1 2.2 V
±04
±10
LSB
DNL
Differential
nonlinearity
(see Note 1) Vref = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1 3 V
±0.4 ±1.0 LSB
Offset voltage without
calibration
Vref = 1.5 V,
DAC12AMPx = 7, DAC12IR = 1 2.2 V
±21
EO
calibration
(see Notes 1, 2) Vref = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1 3 V
±21
mV
Offset voltage with
calibration
Vref = 1.5 V,
DAC12AMPx = 7, DAC12IR = 1 2.2 V
±25
mV
calibration
(see Notes 1, 2) Vref = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1 3 V ±2.5
dE(O)/dTOffset error
temperature coefficient
(see Note 1) 2.2 V/3 V ±30 μV/°C
E
Gain error (see Note 1)
VREF = 1.5 V 2.2 V
±350
% FSR
EGGain error (see Note 1) VREF = 2.5 V 3 V ±3.50 % FSR
dE(G)/dTGain temperature
coefficient (see Note 1) 2.2 V/3 V 10 ppm of
FSR/°C
Time for offset calibration
DAC12AMPx = 2 100
tOffset_Cal Time for offset calibration
(see Note 3)
DAC12AMPx = 3,5 2.2 V/3 V 32 ms
tOffset
_
Cal
(see Note 3) DAC12AMPx = 4,6,7
2.2
V/3
V
6
ms
NOTES: 1. Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coeffici ents “a” and
“b” of the first order equation: y = a + b*x. VDAC12_xOUT = EO + (1 + EG) * (VeREF+/4095) * DAC12_xDAT, DAC12IR = 1.
2. The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON
3. The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with
DAC12AMPx = {0, 1}. It is recommended that the DAC12 module be configured prior to initiating calibration. Port activity during
calibration may effect accuracy and is not recommended.
Positive
Negative
VR+
Gain Error
Offset Error
DAC Code
DAC VOUT
Ideal transfer
function
RLoad =
AVCC
CLoad = 100pF
2
DAC Output
Figure 26. Linearity Test Load Conditions and Gain/Offset Definition
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
55
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, linearity specifications (continued)
DAC12_xDAT − Digital Code
−4
−3
−2
−1
0
1
2
3
4
0 512 1024 1536 2048 2560 3072 3584
VCC = 2.2 V, VREF = 1.5V
DAC12AMPx = 7
DAC12IR = 1
TYPICAL INL ERROR
vs
DIGITAL INPUT DATA
4095
INL − Integral Nonlinearity Error − LSB
DAC12_xDAT − Digital Code
−2.0
−1.5
−1.0
−0.5
0.0
0.5
1.0
1.5
2.0
0 512 1024 1536 2048 2560 3072 3584
VCC = 2.2 V, VREF = 1.5V
DAC12AMPx = 7
DAC12IR = 1
TYPICAL DNL ERROR
vs
DIGITAL INPUT DATA
4095
DNL − Differential Nonlinearity Error − LSB
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
56 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, output specifications
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
No Load, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7 0 0.005
V
Output voltage
ran
g
e
No Load, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
2 2 V/3 V
AVCC−0.05 AVCC
V
VO
range
(see Note 1,
Figure 29) RLoad= 3 kΩ, V eREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
2.2 V/3 V
0 0.1
V
RLoad= 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7 AVCC−0.13 AVCC
CL(DAC12)
Max DAC12
load
capacitance 2.2V/3V 100 pF
I
Max DAC12 2.2V −0.5 +0.5
mA
IL(DAC12)
Max
DAC12
load current 3V −1.0 +1.0 mA
RLoad= 3 kΩ, VO/P(DAC12) < 0.3 V,
DAC12AMPx = 2, DAC12_xDAT = 0h 150 250
RO/P(DAC12) Output
resistance
(see Figure 29)
RLoad= 3 kΩ,
VO/P(DAC12) > AVCC−0.3 V
DAC12_xDAT = 0FFFh 2.2 V/3 V 150 250 Ω
(g)
RLoad= 3 kΩ,
0.3V ≤ VO/P(DAC12) ≤ AVCC − 0.3V 1 4
NOTE 1: Data is valid after the offset calibration of the output amplifier.
RO/P(DAC12_x)
Max
0.3
AVCC
AVCC
−0.3V VOUT
Min
RLoad
AVCC
CLoad
= 100pF
2
ILoad
DAC12
O/P(DAC12_x)
Figure 29. DAC12_x Output Resistance Tests
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
57
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
12-bit DAC, reference input specifications
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Ve
Reference input DAC12IR=0 (see Notes 1 and 2)
2 2 V/3 V
AVCC/3 AVCC+0.2
V
VeREF+
Reference
input
voltage range DAC12IR=1 (see Notes 3 and 4) 2.2 V/3 V A Vcc AVcc+0.2 V
DAC12_0 IR=DAC12_1 IR =0 20 MΩ
DAC12_0 IR=1, DAC12_1 IR = 0
40
48
56
Ri(VREF+),Reference input DAC12_0 IR=0, DAC12_1 IR = 1
2 2 V/3 V
40 48 56
(VREF+),
Ri(VeREF+)
p
resistance DAC12_0 IR=DAC12_1 IR =1,
DAC12_0 SREFx = DAC12_1 SREFx
(see Note 5)
2
.
2
V/3
V
20 24 28 kΩ
NOTES: 1. For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
2. The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC − VE(O)] / [3*(1 + EG)].
3. For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
4. The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC − VE(O)] / (1 + EG).
5. When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel
reducing the reference input resistance.
12-bit DAC, dynamic specifications; Vref = VCC, DAC12IR = 1 (see Figure 30 and Figure 31)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
DAC12
DAC12_xDAT = 800h, DAC12AMPx = 0 → {2, 3, 4} 60 120
tON DAC12
on time
DAC12
_
xDAT
=
800h
,
ErrorV(O) < ±0.5 LSB DAC12AMPx = 0 → {5, 6} 2.2 V/3 V 15 30 μs
tON
on-time
ErrorV(O)
<
±0.5
LSB
(see Note 1,Figure 30) DAC12AMPx = 0 → 7
2.2
V/3
V
6 12
μs
Settling time
DAC12 xDAT
DAC12AMPx = 2 100 200
tS
(
FS
)
Settling time,
full scale
DAC12_xDAT =
80h→F7Fh→80h
DAC12AMPx = 3,5 2.2 V/3 V 40 80 μs
tS(FS)
full-scale 80h→ F7Fh→ 80h DAC12AMPx = 4,6,7
2.2
V/3
V
15 30
μs
Settling time
DAC12_xDAT = DAC12AMPx = 2 5
tS
(
C-C
)
Settling time,
code to code
DAC12
_
xDAT
=
3F8h→ 408h→ 3F8h DAC12AMPx = 3,5 2.2 V/3 V 2μs
tS(C
-
C)
code to code
3F8h→
408h→
3F8h
BF8h→ C08h→ BF8h DAC12AMPx = 4,6,7
2.2
V/3
V
1
μs
DAC12_xDAT = DAC12AMPx = 2 0.05 0.12
SR Slew rate
DAC12
_
xDAT
=
80h→ F7Fh→ 80h DAC12AMPx = 3,5 2.2 V/3 V 0.35 0.7 V/μs
SR
Slew
rate
80h→
F7Fh→
80h
(see Note 2) DAC12AMPx = 4,6,7
2.2
V/3
V
1.5 2.7
V/μs
DAC12 xDAT
DAC12AMPx = 2 600
Glitch energy, full-scale DAC12_xDAT =
80h→F7Fh→80h
DAC12AMPx = 3,5 2.2 V/3 V 150 nV-s
Glitch
energy,
full scale
80h→ F7Fh→ 80h DAC12AMPx = 4,6,7
2.2
V/3
V
30
nV s
NOTES: 1. RLoad and CLoad connected to AVSS (not AVCC/2) in Figure 30.
2. Slew rate applies to output voltage steps >= 200mV.
RLoad
AVCC
CLoad = 100pF
2
DAC Output
RO/P(DAC12.x)
ILoad
Conversion 1 Conversion 2
VOUT
Conversion 3
Glitch
Energy +/− 1/2 LSB
+/− 1/2 LSB
tsettleLH tsettleHL
= 3 kΩ
Figure 30. Settling Time and Glitch Energy Testing
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
58 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
Conversion 1 Conversion 2
VOUT
Conversion 3
10%
tSRLH tSRHL
90%
10%
90%
Figure 31. Slew Rate Testing
12-bit DAC, dynamic specifications continued (TA = 25°C unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
3 dB b d idth
DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h 40
BW−3dB
3-dB bandwidth,
VDC=1.5V, VAC=0.1VPP
(see Figure 32)
DAC12AMPx = {5, 6}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h 2.2 V/3 V 180 kHz
(see Figure 32) DAC12AMPx = 7, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h 550
DAC12_0DAT = 800h, No Load,
DAC12_1DAT = 80h<−>F7Fh, RLoad = 3kΩ
fDAC12_1OUT = 10kHz @ 50/50 duty cycle
2 2 V/3 V
−80
dB
Channel-to-channel crosstalk
(see Note 1 and Figure 33) DAC12_0DAT = 80h<−>F7Fh, RLoad = 3kΩ,
DAC12_1DAT = 800h, No Load,
fDAC12_0OUT = 10kHz @ 50/50 duty cycle
2.2 V/3 V
−80
dB
NOTE 1: RLOAD = 3 kΩ, CLOAD = 100 pF
VeREF+
AC
DC
RLoad
AVCC
CLoad = 100pF
2
ILoad
DAC12_x DACx
= 3 kΩ
Figure 32. Test Conditions for 3-dB Bandwidth Specification
DAC12_xDAT 080h
VOUT
fToggle
7F7h
VDAC12_yOUT
080h 7F7h 080h
VDAC12_xOUT
e
REF+ RLoad
AVCC
CLoad
= 100pF
2
ILoad
DAC12_1
RLoad
AVCC
CLoad
= 100pF
2
ILoad
DAC12_0 DAC0
DAC1
V
Figure 33. Crosstalk Test Conditions
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
59
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
operational amplifier OA, supply specifications
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VCC Supply voltage — 2.2 3.6 V
Fast Mode,
180
290
Fast
Mode
,
OARRIP = 1 (rail-to-rail mode off) 180 290
Medium Mode,
110
190
Medium
Mode
,
OARRIP = 1 (rail-to-rail mode off) 110 190
I
Su
pp
l
y
current Slow Mode,
OARRIP = 1 (rail-to-rail mode off)
2 2 V/3 V
50 80
A
ICC
Supply
current
(see Note 1) Fast Mode, 2.2 V/3 V
300
490
μA
(see
Note
1)
Fast
Mode
,
OARRIP = 0 (rail-to-rail mode on) 300 490
Medium Mode,
190
350
Medium
Mode
,
OARRIP = 0 (rail-to-rail mode on) 190 350
Slow Mode,
90
190
Slow
Mode
,
OARRIP = 0 (rail-to-rail mode on) 90 190
PSRR Power supply rejection ratio Non-inverting 2.2 V/3 V 70 dB
NOTE 1: P6SEL.x = 1 for each corresponding pin when used in OA input or OA output mode.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
60 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operational amplifier OA, input/output specifications
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
V
Voltage supply I/P
OARRIP = 1 (rail-to-rail mode off) −0.1 VCC−1.2
V
VI/P Voltage supply, I/P OARRIP = 0 (rail-to-rail mode on) —−0.1 VCC+0.1 V
I
Input leaka
g
e current, I/P TA = −40 to +55_C −5 ±0.5 5
nA
IIkg
Input
leakage
current
,
I/P
(see Notes 1 and 2) TA = +55 to +85_C—−20 ±5 20 nA
Fast Mode 50
Medium Mode fV
(
I/P
)
= 1 kHz 80
V
Voltage noise density I/P
Slow Mode
fV(I/P)
1
kHz
140
nV/√Hz
VnVoltage noise density, I/P Fast Mode —30 nV/√Hz
Medium Mode fV
(
I/P
)
= 10 kHz 50
Slow Mode
fV(I/P)
10
kHz
65
V
Offset voltage I/P
2 2 V/3 V
±10
mV
VIO Offset voltage, I/P 2.2 V/3 V ±10 mV
Offset temperature drift, I/P see Note 3 2.2 V/3 V ±10 μV/°C
Offset voltage drift
with supply, I/P 0.3V ≤ VIN ≤ VCC−0.3V
ΔVCC≤ ± 10%, TA = 25°C2.2 V/3 V ±1.5 mV/V
V
High level output voltage O/P
Fast Mode, ISOURCE ≤ −500μA2.2 V VCC−0.2 VCC
V
VOH High-level output voltage, O/P Slow Mode,ISOURCE ≤ −150μA3 V VCC−0.1 VCC V
V
Low level output voltage O/P
Fast Mode, ISOURCE ≤ +500μA2.2 V VSS 0.2
V
VOL Low-level output voltage, O/P Slow Mode,ISOURCE ≤ +150μA3 V VSS 0.1 V
RLoad= 3 kΩ, CLoad = 50pF,
OARRIP = 0 (rail-to-rail mode on),
VO/P(OAx) < 0.2 V 150 250
RO/P
(OAx)
Output
Resistance
(see Figure 34 and Note 4)
RLoad= 3 kΩ, CLoad = 50pF,
OARRIP = 0 (rail-to-rail mode on),
VO/P(OAx) > AVCC − 0.2 V 2.2 V/3 V 150 250 Ω
RLoad= 3 kΩ, CLoad = 50pF,
OARRIP = 0 (rail-to-rail mode on),
0.2 V ≤ VO/P(OAx) ≤ AVCC − 0.2 V 0.1 4
CMRR Common-mode rejection ratio Non-inverting 2.2 V/3 V 70 dB
NOTES: 1. ESD damage can degrade input current leakage.
2. The input bias current is overridden by the input leakage current.
3. Calculated using the box method.
4. Specification valid for voltage-follower OAx configuration.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
61
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) RO/P(OAx)
Max
0.2V AVCC
AVCC
−0.2V VOUT
Min
RLoad
AVCC
CLoad
2
ILoad
OAx
O/P(OAx)
Figure 34. OAx Output Resistance Tests
operational amplifier OA, dynamic specifications
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Fast Mode — 1.2
SR Slew rate Medium Mode — 0.8 V/μs
SR
Slew
rate
Slow Mode — 0.3
V/μs
Open-loop voltage gain — 100 dB
φmPhase margin CL = 50 pF — 60 deg
Gain margin CL = 50 pF — 20 dB
Non inverting Fast Mode R 47kΩC50pF
22
Gain
-
bandwidth product
Non−inverting, Fast Mode, RL = 47kΩ, CL = 50pF 2.2
GBW
Gain
-
bandwidth
product
(see Figure 35
Non inverting Medium Mode R 300kΩC50pF
2 2 V/3 V
14
MHz
GBW (see Figure 35 Non−inverting, Medium Mode, RL =300kΩ, CL = 50pF 2.2 V/3 V 1.4 MHz
GBW
(see
Figure
35
a
n
d
Fi
gu
r
e
36)
Non inverting Slow Mode R 300kΩC50pF
2.2
V/3
V
05
MHz
and
Figure
36)
Non−inverting, Slow Mode, RL =300kΩ, CL = 50pF 0.5
ten(on) Enable time on ton, non-inverting, Gain = 1 2.2 V/3 V 10 20 μs
ten(off) Enable time off 2.2 V/3 V 1μs
Figure 35
Input Frequency − kHz
−80
−60
−40
−20
0
20
40
60
80
100
120
140 TYPICAL OPEN-LOOP GAIN vs FREQUENCY
Slow Mode
Fast Mode
Gain − dB
Medium Mode
0.001 0.01 0.1 1 10 100 1000 10000
Figure 36
Input Frequency − kHz
−250
−200
−150
−100
−50
0
1 10 100 1000 10000
TYPICAL PHASE vs FREQUENCY
Phase − degrees
Slow Mode
Fast Mode
Medium Mode
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
62 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
operational amplifier OA feedback network, noninverting amplifier mode (OAFCx = 4)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
OAFBRx = 0 0.996 1.00 1.002
OAFBRx = 1 1.329 1.334 1.340
OAFBRx = 2 1.987 2.001 2.016
G
Gain
OAFBRx = 3
22V/3V
2.64 2.667 2.70
G Gain OAFBRx = 4 2.2 V/ 3 V 3.93 4.00 4.06
OAFBRx = 5 5.22 5.33 5.43
OAFBRx = 6 7.76 7.97 8.18
OAFBRx = 7 15.0 15.8 16.6
THD
Total harmonic distortion/
All gains
2.2 V −60
dB
THD
Total
harmonic
distortion/
nonlinearity All gains 3 V −70 dB
tSettle Settling time (see Note 1) All power modes 2.2 V/3 V 7 12 μs
NOTES: 1. The settling time specifies the time until an ADC result is stable. This includes the minimum required sampling time of the ADC. The
settling time of the amplifier itself might be faster.
operational amplifier OA feedback network, inverting amplifier mode (OAFCx = 6) (see Note 1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
OAFBRx = 1 −0.371 −0.335 −0.298
OAFBRx = 2 −1.031 −1.002 −0.972
OAFBRx = 3 −1.727 −1.668 −1.609
G
Gain
OAFBRx = 4
22V/3V
−3.142 −3.00 −2.856
G
G
a
i
nOAFBRx = 5
2
.
2
V/
3
V
−4.581 −4.33 −4.073
OAFBRx = 6 −7.529 −6.97 −6.379
OAFBRx = 7 −17.04
0−14.8 −12.27
9
THD
Total harmonic distortion/
All gains
2.2 V −60
dB
THD
Total
harmonic
distortion/
nonlinearity All gains 3 V −70 dB
tSettle Settling time (see Note 2) All power modes 2.2 V/3 V 7 12 μs
NOTES: 1. This includes the 2 OA configuration “inverting amplifier with input buf fer”. Both OA needs to be set to the same power mode OAPMx.
2. The settling time specifies the time until an ADC result is stable. This includes the minimum required sampling time of the ADC. The
settling time of the amplifier itself might be faster.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
63
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
flash memory (MSP430FG461x devices only)
PARAMETER TEST
CONDITIONS VCC MIN TYP MAX UNIT
VCC(PGM/
ERASE) Program and Erase supply voltage 2.7 3.6 V
fFTG Flash Timing Generator frequency 257 476 kHz
IPGM Supply current from DVCC during program 2.7 V/ 3.6 V 3 5 mA
IERASE Supply current from DVCC during erase See Note 3 2.7 V/ 3.6 V 3 7 mA
IGMERASE Supply current from DVCC during global
mass erase See Note 4 2.7 V/ 3.6 V 6 14 mA
tCPT Cumulative program time See Note 1 2.7 V/ 3.6 V 10 ms
tCMErase Cumulative mass erase time 2.7 V/ 3.6 V 20 ms
Program/Erase endurance 104105cycles
tRetention Data retention duration TJ = 25°C 100 years
tWord Word or byte program time 30
tBlock, 0Block program time for 1st byte or word 25
tBlock, 1-63 Block program time for each additional byte
or word
SNt2
18
t
tBlock, End Block program end-sequence wait time See Note 2 6tFTG
tMass Erase Mass erase time 10593
tGlobal Mass Erase Global mass erase time 10593
tSeg Erase Segment erase time 4819
NOTES: 1. The cumulative program time must not be exceeded during a block-write operation. This parameter is only relevant if the block write
feature is used.
2. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG).
3. Lower 64-KB or upper 64-KB Flash memory erased.
4. All Flash memory erased.
JTAG interface
PARAMETER TEST
CONDITIONS VCC MIN TYP MAX UNIT
f
TCK input frequency
See Note 1
2.2 V 0 5 MHz
fTCK TCK input frequency See Note 1 3 V 0 10 MHz
RInternal Internal pull-up resistance on TMS, TCK, TDI/TCLK See Note 2 2.2 V/ 3 V 25 60 90 kΩ
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected.
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG fuse (see Note 1)
PARAMETER TEST
CONDITIONS VCC MIN TYP MAX UNIT
VCC(FB) Supply voltage during fuse-blow condition TA = 25°C 2.5 V
VFB Voltage level on TDI/TCLK for fuse-blow: F versions 6 7 V
IFB Supply current into TDI/TCLK during fuse blow 100 mA
tFB Time to blow fuse 1 ms
NOTE 1: Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
64 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematics
Port P1, P1.0 to P1.5, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P1SEL.x
1
0
P1DIR.x
P1IN.x
DVSS
DVSS
Pad Logic
DVSS
P1IRQ.x
D
EN
Module X IN
1
0
Module X OUT
P1OUT.x
Note: x = 0,1,2,3,4,5
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
Interrupt
Edge
Select
QEN
Set
P1SEL.x
P1IES.x
P1IFG.x
P1IE.x
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
65
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P1 (P1.0 to P1.5) pin functions
PIN NAME (P1 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P1.X) X FUNCTION P1DIR.x P1SEL.x
P1.0/TA0 0 P1.0 (I/O) I: 0; O: 1 0
Timer_A3.CCI0A 0 1
Timer_A3.TA0 1 1
P1.1/TA0/MCLK 1 P1.1 (I/O) I: 0; O: 1 0
Timer_A3.CCI0B 0 1
MCLK 1 1
P1.2/TA1 2 P1.2 (I/O) I: 0; O: 1 0
Timer_A3.CCI1A 0 1
Timer_A3.TA1 1 1
P1.3/TBOUTH/SVSOUT 3 P1.3 (I/O) I: 0; O: 1 0
Timer_B7.TBOUTH 0 1
SVSOUT 1 1
P1.4/TBCLK/SMCLK 4 P1.4 (I/O) I: 0; O: 1 0
Timer_B7.TBCLK 0 1
SMCLK 1 1
P1.5/TACLK/ACLK 5 P1.5 (I/O) I: 0; O: 1 0
Timer_A3.TACLK 0 1
ACLK 1 1
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
66 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P1, P1.6, P1.7, input/output with Schmitt trigger
−
+
Comp_A
Bus
Keeper
EN
Direction
0: Input
1: Output
P1SEL.x
1
0
P1DIR.x
P1IN.x
DVSS
DVSS
Pad Logic
CAPD.x
P1IRQ.x
D
EN
Module X IN
1
0
Module X OUT
P1OUT.x
Note: x = 6,7
P1.6/CA0
P1.7/CA1
Interrupt
Edge
Select
QEN
Set
P1SEL.x
P1IES.x
P1IFG.x
P1IE.x P2CA0
CA0
CA1
P2CA1
1
0
1
0
Port P1 (P1.6 and P1.7) pin functions
PIN NAME (P1 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P1.X) X FUNCTION CAPD.x P1DIR.x P1SEL.x
P1.6/CA0 6 P1.6 (I/O) 0I: 0; O: 1 0
CA0 1 X X
P1.7/CA1 7 P1.7 (I/O) 0I: 0; O: 1 0
CA1 1 X X
NOTE 1: X: Don’t care
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
67
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P2, P2.0 to P2.3, P2.6 to P2.7, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P2SEL.x
1
0
P2DIR.x
P2IN.x
DVSS
DVSS
Pad Logic
TBOUTH
P2IRQ.x
D
EN
Module X IN
1
0
Module X OUT
P2OUT.x
Note: x = 0,1,2,3,6,7
P2.0/TA2
P2.1/TB0
P2.2/TB1
P2.3/TB2
P2.6/CAOUT
P2.7/ADC12CLK/DMAE0
Interrupt
Edge
Select
QEN
Set
P2SEL.x
P2IES.x
P2IFG.x
P2IE.x
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
68 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P2 (P2.0, P2.1, P2.2, P2.3, P2.6 and P2.7) pin functions
PIN NAME (P2 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P2.X) X FUNCTION P2DIR.x P2SEL.x
P2.0/TA2 0 P2.0 (I/O) I: 0; O: 1 0
Timer_A3.CCI2A 0 1
Timer_A3.TA2 1 1
P2.1/TB0 1 P2.1 (I/O) I: 0; O: 1 0
Timer_B7.CCI0A and Timer_B7.CCI0B 0 1
Timer_B7.TB0 (see Note 1) 1 1
P2.2/TB1 2 P2.2 (I/O) I: 0; O: 1 0
Timer_B7.CCI1A and Timer_B7.CCI1B 0 1
Timer_B7.TB1 (see Note 1) 1 1
P2.3/TB3 3 P2.3 (I/O) I: 0; O: 1 0
Timer_B7.CCI2A and Timer_B7.CCI2B 0 1
Timer_B7.TB3 (see Note 1) 1 1
P2.6/CAOUT 6 P2.6 (I/O) I: 0; O: 1 0
CAOUT 1 1
P2.7/ADC12CLK/DMAE0 7 P2.7 (I/O) I: 0; O: 1 0
ADC12CLK 1 1
DMAE0 0 1
NOTE 1: Setting TBOUTH causes all Timer_B outputs to be set to high impedance.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
69
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P2, P2.4 to P2.5, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P2SEL.x
1
0
P2DIR.x
P2IN.x
DVSS
DVSS
Pad Logic
DVSS
P2IRQ.x
D
EN
Module X IN
1
0
Module X OUT
P2OUT.x
Note: x = 4,5
P2.4/UCA0TXD
P2.5/UCA0RXD
Interrupt
Edge
Select
QEN
Set
P2SEL.x
P2IES.x
P2IFG.x
P2IE.x
Direction control
from Module X
Port P2 (P2.4 and P2.5) pin functions
PIN NAME (P2 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P2.X) X FUNCTION P2DIR.x P2SEL.x
P2.4/UCA0TXD 4 P2.4 (I/O) I: 0; O: 1 0
USCI_A0.UCA0TXD (see Note 1, 2) X 1
P2.5/UCA0RXD 5 P2.5 (I/O) I: 0; O: 1 0
USCI_A0.UCA0RXD (see Note 1, 2) X 1
NOTES: 1. X: Don’t care
2. When in USCI mode, P2.4 is set to output, P2.5 is set to input.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
70 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P3, P3.0 to P3.3, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P3SEL.x
1
0
P3DIR.x
P3IN.x
DVSS
DVSS
Pad Logic
DVSS
D
EN
Module X IN
1
0
Module X OUT
P3OUT.x
Note: x = 0,1,2,3
P3.0/UCB0STE
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK
Port P3 (P3.0 to P3.3) pin functions
PIN NAME (P3 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P3.X) X FUNCTION P3DIR.x P3SEL.x
P3.0/UCB0STE 0 P3.0 (I/O) I: 0; O: 1 0
UCB0STE (see Notes 1, 2) X 1
P3.1/UCB0SIMO/ 1 P3.1 (I/O) I: 0; O: 1 0
UCB0SDA UCB0SIMO/UCB0SDA (see Notes 1, 2, 3) X 1
P3.2/UCB0SOMI/ 2 P3.2 (I/O) I: 0; O: 1 0
UCB0SCL UCB0SOMI/UCB0SCL (see Notes 1, 2, 3) X 1
P3.3/UCB0CLK 3 P3.3 (I/O) I: 0; O: 1 0
UCB0CLK (see Notes 1, 2) X 1
NOTES: 1. X: Don’t care
2. The pin direction is controlled by the USCI module.
3. In case the I2C functionality is selected the output drives only the logical 0 to VSS level.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
71
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P3, P3.4 to P3.7, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P3SEL.x
1
0
P3DIR.x
P3IN.x
DVSS
DVSS
Pad Logic
TBOUTH
D
EN
Module X IN
1
0
Module X OUT
P3OUT.x
Note: x = 4,5,6,7
P3.4/TB3
P3.5/TB4
P3.6/TB5
P3.7/TB6
Port P3 (P3.4 to P3.7) pin functions
PIN NAME (P3 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P3.X) X FUNCTION P3DIR.x P3SEL.x
P3.4/TB3 4 P3.4 (I/O) I: 0; O: 1 0
Timer_B7.CCI3A and Timer_B7.CCI3B 0 1
Timer_B7.TB3 (see Note 1) 1 1
P3.5/TB4 5 P3.5 (I/O) I: 0; O: 1 0
Timer_B7.CCI4A and Timer_B7.CCI4B 0 1
Timer_B7.TB4 (see Note 1) 1 1
P3.6/TB5 6 P3.6 (I/O) I: 0; O: 1 0
Timer_B7.CCI5A and Timer_B7.CCI5B 0 1
Timer_B7.TB5 (see Note 1) 1 1
P3.7/TB6 7 P3.7 (I/O) I: 0; O: 1 0
Timer_B7.CCI6A and Timer_B7.CCI6B 0 1
Timer_B7.TB6 (see Note 1) 1 1
NOTE 1: Setting TBOUTH causes all Timer_B outputs to be set to high impedance.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
72 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P4, P4.0 to P4.1, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P4SEL.x
1
0
P4DIR.x
P4IN.x
DVSS
DVSS
Pad Logic
DVSS
D
EN
Module X IN
1
0
Module X OUT
P4OUT.x
Note: x = 0,1
P4.1/URXD1
P4.0/UTXD1
Direction control
from Module X
Port P4 (P4.0 to P4.1) pin functions
PIN NAME (P4 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P4.X) X FUNCTION P4DIR.x P4SEL.x
P4.0/UTXD1 0 P4.0 (I/O) I: 0; O: 1 0
USART1.UTXD1 (see Notes 1, 2) X 1
P4.1/URXD1 1 P4.1 (I/O) I: 0; O: 1 0
USART1.URXD1 (see Notes 1, 2) X 1
NOTES: 1. X: Don’t care
2. When in USART1 mode, P4.0 is set to output, P4.1 is set to input.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
73
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P4, P4.2 to P4.7, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P4SEL.x
1
0
P4DIR.x
P4IN.x
LCDS32/36
Segment Sy
Pad Logic
DVSS
D
EN
Module X IN
1
0
Module X OUT
P4OUT.x
Note:x = 2,3,4,5,6,7
y = 34,35,36,37,38,39
P4.7/UCA0RXD/S34
P4.6/UCA0TXD/S35
P4.5/UCLK1/S36
P4.4/SOMI1/S37
P4.3/SIMO1/S38
P4.2/STE1/S39
Direction control
from Module X
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
74 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P4 (P4.2 to P4.5) pin functions
PIN NAME (P4 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P4.X) X FUNCTION P4DIR.x P4SEL.x LCDS36
P4.2/STE1/S39 2 P4.2 (I/O) I: 0; O: 1 0 0
USART1.STE1 X 1 0
S39 (see Note 1) X X 1
P4.3/SIMO/S38 3 P4.3 (I/O) I: 0; O: 1 0 0
USART1.SIMO1 (see Notes 1, 2) X 1 0
S38 (see Note 1) X X 1
P4.4/SOMI/S37 4 P4.4 (I/O) I: 0; O: 1 0 0
USART1.SOMI1 (see Notes 1, 2) X 1 0
S37 (see Note 1) X X 1
P4.5/SOMI/S36 5 P4.5 (I/O) I: 0; O: 1 0 0
USART1.UCLK1 (see Notes 1, 2) X 1 0
S36 (see Note 1) X X 1
P4.6/UCA0TXD/S35 6 P4.6 (I/O) I: 0; O: 1 0 0
USCI_A0.UCA0TXD (see Notes 1, 3) X 1 0
S35 (see Note 1) X X 1
P4.7/UCA0RXD/S34 7 P4.7 (I/O) I: 0; O: 1 0 0
USCI_A0.UCA0RXD (see Notes 1, 3) X 1 0
S34 (see Note 1) X X 1
NOTES: 1. X: Don’t care
2. The pin direction is controlled by the USART1 module.
3. When in USCI mode, P4.6 is set to output, P4.7 is set to input.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
75
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P5, P5.0, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P5SEL.x
1
0
P5DIR.x
P5IN.x
LCDS0
Segment Sy
1
0
P5OUT.x
P5.0/S1/A13/OA1I1
DVSS
INCH=13#
A13#
Pad Logic
−
+
OA1
Note:x = 0
y = 1
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
76 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P5 (P5.0) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P5.X) X FUNCTION P5DIR.x P5SEL.x INCHx OAPx(OA1)
OANx(OA1) LCDS0
P5.0/S1/A13/OA1I1 0 P5.0 (I/O) (see Note 1) I: 0; O: 1 0 X X 0
OAI11 (see Note 1) 0 X X 1 0
A13 (see Notes 1, 3) X 1 13 X X
S1 enabled (see Note 1) X 0 X X 1
S1 disabled (see Note 1) X 1 X X 1
NOTES: 1. X: Don’t care
2. N/A: Not available or not applicable.
3. Setting the P5SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
77
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P5, P5.1, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P5SEL.x
1
0
P5DIR.x
P5IN.x
LCDS0
Segment Sy
1
0
P5OUT.x
P5.1/S0/A12/DAC1
DVSS
INCH=12#
A12#
Pad Logic
DAC12.1OPS
DAC1 1
0
2
DVSS
0 if DAC12.1AMPx= 0 and DAC12.1 OPS= 1
1 if DAC12.1AMPx= 1 and DAC12.1 OPS= 1
2 if DAC12.1AMPx> 1 and DAC12.1 OPS= 1
Note:x = 1
y = 0
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
78 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P5 (P5.1) pin functions
PIN NAME (P5 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P5.X) X FUNCTION P5DIR.x P5SEL.x INCHx DAC12.1OPS DAC12.1AMPx LCDS0
P5.1/S0/A12/DAC1 1 P5.1 (I/O) (see Note 1) I: 0; O: 1 0 X 0 X 0
DAC1 high impedance
(see Note 1) X X X 1 0 X
DVSS (see Note 1) X X X 1 1 X
DAC1 output
(see Note 1) X X X 1 > 1 X
A12 (see Notes 1, 2) X 1 12 0 X 0
S0 enabled (see Note 1) X 0 X 0 X 1
S0 disabled
(see Note 1) X 1 X 0 X 1
NOTES: 1. X: Don’t care
2. Setting the P5SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
79
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P5, P5.2 to P5.4, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P5SEL.x
1
0
P5DIR.x
P5IN.x
LCD Signal
Pad Logic
DVSS
1
0
P5OUT.x
Note:x = 2,3,4
P5.2/COM1
P5.3/COM2
P5.4/COM3
DVSS
Port P5 (P5.2 to P5.4) pin functions
PIN NAME (P5 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P5.X) X FUNCTION P5DIR.x P5SEL.x
P5.2/COM1 2 P5.2 (I/O) I: 0; O: 1 0
COM1 (see Note 1) X 1
P5.3/COM2 3 P5.3 (I/O) I: 0; O: 1 0
COM2 (see Note 1) X 1
P5.4/COM3 4 P5.4 (I/O) I: 0; O: 1 0
COM3 (see Note 1) X 1
NOTE 1: X: Don’t care
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
80 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P5, P5.5 to P5.7, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P5SEL.x
1
0
P5DIR.x
P5IN.x
LCD Signal
Pad Logic
DVSS
1
0
P5OUT.x
Note:x = 5,6,7
P5.5/R03
P5.6/LCDREF/R13
P5.7/R03
DVSS
Port P5 (P5.5 to P5.7) pin functions
PIN NAME (P5 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P5.X) X FUNCTION P5DIR.x P5SEL.x
P5.5/R03 5 P5.5 (I/O) I: 0; O: 1 0
R03 (see Note 1) X 1
P5.6/LCDREF/R13 6 P5.6 (I/O) I: 0; O: 1 0
R13 or LCDREF (see Notes 1, 2) X 1
P5.7/R03 7 P5.7 (I/O) I: 0; O: 1 0
R03 (see Note 1) X 1
NOTES: 1. X: Don’t care
2. External reference for the LCD_A charge pump is applied when VLCDREFx = 01. Otherwise R13 is selected.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
81
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P6, P6.0, P6.2, and P6.4, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P6SEL.x
1
0
P6DIR.x
P6IN.x
INCH=0/2/4#
Ay#
Pad Logic
1
0
DVSS
P6OUT.x
P6.0/A0/OA0I0
P6.2/A2/OA0I1
P6.4/A4/OA1I0
−
+
OA0/1
Note:x = 0, 2, 4
y = 0, 1
# = Signal from or to ADC12
Port P6 (P6.0, P6.2, and P6.4) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P6.X) X FUNCTION P6DIR.x P6SEL.x OAPx (OA0)
OANx (OA0) OAPx (OA1)
OANx(OA1) INCHx
P6.0/A0/OA0I0 0 P6.0 (I/O) (see Note 1) I: 0; O: 1 0 X X X
OA0I0 (see Note 1) 0 X 0 X X
A0 (see Notes 1, 3) X 1 X X 0
P6.2/A2/OA0I1 2 P6.2 (I/O) (see Note 1) I: 0; O: 1 0 X X X
OA0I1 (see Note 1) 0 X 1 X X
A2 (see Notes 1, 3) X 1 X X 2
P6.4/A4/OA1I0 4 P6.4 (I/O) (see Note 1) I: 0; O: 1 0 X X X
OA1I0 (see Note 1) 0 X X 0 X
A4 (see Notes 1, 3) X 1 X X 4
NOTES: 1. X: Don’t care
2. N/A: Not available or not applicable.
3. Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
82 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P6, P6.1, P6.3, and P6.5 input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0:Input
1:Output
P6SEL.x
1
0
P6DIR.x
P6IN.x
INCH=1/3/5#
Ay#
Pad Logic
1
0
DVSS
P6OUT.x
P6.1/A1/OA0O
P6.3/A3/OA1O
P6.5/A5/OA2O
−
+
OAy
OAPMx> 0
OAADC1
Note:x = 1, 3, 5
y = 0, 1, 2
# = Signal from or to ADC12
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
83
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P6 (P6.1, P6.3, and P6.5) pin functions
PIN NAME (P6 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P6.X) X FUNCTION P6DIR.x P6SEL.x OAADC1 OAPMx INCHx
P6.1/A1/OA0O 1 P6.1 (I/O) (see Note 1) I: 0; O: 1 0 X 0 X
OA0O (see Notes 1, 4) X X 1 > 0 X
A1 (see Notes 1, 3) X 1 X 0 1
P6.3/A3/OA1O 3 P6.3 (I/O) (see Note 1) I: 0; O: 1 0 X 0 X
OA1O (see Notes 1, 4) X X 1 > 0 X
A3 (see Notes 1, 3) X 1 X 0 3
P6.5/A5/OA2O 5 P6.5 (I/O) (see Note 1) I: 0; O: 1 0 X 0 X
OA2O (see Notes 1, 4) X X 1 > 0 X
A5 (see Notes 1, 3) X 1 X 0 5
NOTES: 1. X: Don’t care
2. N/A: Not available or not applicable.
3. Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
4. Setting the OAADC1 bit or setting OAFCx = 00 will cause the operational amplifier to be present at the pin as well as internally
connected to the corresponding ADC12 input.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
84 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P6, P6.6, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P6SEL.x
1
0
P6DIR.x
P6IN.x
INCH=6#
A6#
Pad Logic
1
0
DVSS
P6OUT.x P6.6/A6/DAC0/OA2I0
−
+
OA2
DAC0
DAC12.0OPS
DAC12.0AMP> 0
1
0
2
0 if DAC12.0AMPx= 0 and DAC12. 0OPS = 0
1 if DAC12.0AMPx= 1 and DAC12. 0OPS = 0
2 if DAC12.0AMPx> 1 and DAC12. 0OPS = 0
DVSS
Note:x = 6
# = Signal from or to ADC12
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
85
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P6 (P6.6) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P6.X) X FUNCTION P6DIR.x P6SEL.x INCHx DAC12.0OPS DAC12.0AMPx OAPx (OA2)
OANx (OA2)
P6.6/A6/DAC0/OA2I0 6 P6.6 (I/O) (see Note 1) I: 0; O: 1 0 X 1 X X
DAC0 high impedance
(see Note 1) X X X 0 0 X
DVSS (see Note 1) X X X 0 1 X
DAC0 output
(see Note 1) X X X 0 >1 X
A6 (see Notes 1, 2) X 1 6 X X X
OA2I0 (see Note 1) 0 X 0 X X 0
NOTES: 1. X: Don’t care
2. Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
86 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P6, P6.7, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P6SEL.x
1
0
P6DIR.x
P6IN.x
INCH=7#
A7#
Pad Logic
1
0
DVSS
P6OUT.x
P6.7/A7/DAC1/SVSIN
DAC1
DAC12.1OPS
DAC12.1AMP> 0
1
0
2
0 if DAC12.1AMPx=0 and DAC12.1OPS= 0
1 if DAC12.1AMPx=1 and DAC12.1OPS= 0
2 if DAC12.1AMPx>1 and DAC12.1OPS= 0
To SVS Mux
VLD=15
DVSS
Note:x = 7
# = Signal from or to ADC12
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
87
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P6 (P6.7) pin functions
PIN NAME (P6 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P6.X) X FUNCTION P6DIR.x P6SEL.x INCHx DAC12.1OPS DAC12.1AMPx
P6.7/A7/DAC1/SVSIN 7 P6.7 (I/O) (see Note 1) I: 0; O: 1 0 X 1 X
DAC1 high impedance
(see Note 1) X X X 0 0
DVSS (see Note 1) X X X 0 1
DAC1 output
(see Note 1) X X X 0 > 1
A7 (see Notes 1, 2) X 1 7 X X
SVSIN (see Notes 1,3) 0 1 0 1 X
NOTES: 1. X: Don’t care
2. Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
3. Setting VLDx = 15 will also cause the external SVSIN to be used. In this case, the P6SEL.x bit is a do not care.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
88 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P7, P7.0 to P7.3, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P7SEL.x
1
0
P7DIR.x
P7IN.x
LCDS28/32
Segment Sy
Pad Logic
DVSS
D
EN
Module X IN
1
0
Module X OUT
P7OUT.x
P7.3/UCA0CLK/S30
P7.2/UCA0SOMI/S31
P7.1/UCA0SIMO/S32
P7.0/UCA0STE/S33
Direction control
from Module X
Note:x = 0, 1, 2, 3
y = 30, 31, 32, 33
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
89
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P7 (P7.0 to P7.1) pin functions
PIN NAME (P7 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P7.X) X FUNCTION P7DIR.x P7SEL.x LCDS32
P7.0/UCA0STE/S33 0 P7.0 (I/O) I: 0; O: 1 0 0
USCI_A0.UCA0STE (see Notes 1, 2) X 1 0
S33 (see Note 1) X X 1
P7.1/UCA0SIMO/S32 1 P7.1 (I/O) I: 0; O: 1 0 0
USCI_A0.UCA0SIMO (see Notes 1, 2) X 1 0
S32 (see Note 1) X X 1
P7.2/UCA0SOMI/S31 2 P7.2 (I/O) I: 0; O: 1 0 0
USCI_A0.UCA0SOMI (see Notes 1, 3) X 1 0
S31 (see Note 1) X X 1
P7.3/UCA0CLK/S30 3 P7.3 (I/O) I: 0; O: 1 0 0
USCI_A0.UCA0CLK (see Notes 1, 3) X 1 0
S30 (see Note 1) X X 1
NOTES: 1. X: Don’t care
2. The pin direction is controlled by the USCI module.
3. The pin direction is controlled by the USCI module.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
90 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P7, P7.4 to P7.7, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P7SEL.x
1
0
P7DIR.x
P7IN.x
LCDS24/28
Segment Sy
Pad Logic
DVSS
1
0
P7OUT.x
P7.7/S26
P7.6/S27
P7.5/S28
P7.4/S29
DVSS
Note:x = 4, 5, 6, 7
y = 26, 27, 28, 29
Port P7 (P7.4 to P7.5) pin functions
PIN NAME (P7 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P7.X) X FUNCTION P7DIR.x P7SEL.x LCDS28
P7.4/S29 4 P7.4 (I/O) I: 0; O: 1 0 0
S29 (see Note 1) X X 1
P7.5/S28 5 P7.5 (I/O) I: 0; O: 1 0 0
S28 (see Note 1) X X 1
P7.6/S27 6 P7.6 (I/O) I: 0; O: 1 0 0
S27 (see Note 1) X X 1
P7.7/S26 7 P7.7 (I/O) I: 0; O: 1 0 0
S26 (see Note 1) X X 1
NOTE 1: X: Don’t care
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
91
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P8, P8.0 to P8.7, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P8SEL.x
1
0
P8DIR.x
P8IN.x
LCDS16/20/24
Segment Sy
Pad Logic
DVSS
1
0
P8OUT.x
Note: x = 0,1,2,3,4,5,6,7
y= 25,24,23,22,21,20,19,18
P8.7/S18
P8.6/S19
P8.5/S20
P8.4/S21
P8.3/S22
P8.2/S23
P8.1/S24
P8.0/S25
DVSS
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
92 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P8 (P8.0 to P8.1) pin functions
PIN NAME (P8 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P8.X) X FUNCTION P8DIR.x P8SEL.x LCDS16
P8.0/S18 0 P8.0 (I/O) I: 0; O: 1 0 0
S18 (see Note 1) X X 1
P8.1/S19 0 P8.0 (I/O) I: 0; O: 1 0 0
S19 (see Note 1) X X 1
P8.2/S20 2 P8.2 (I/O) I: 0; O: 1 0 0
S20 (see Note 1) X X 1
P8.3/S21 3 P8.3 (I/O) I: 0; O: 1 0 0
S21 (see Note 1) X X 1
P8.4/S22 4 P8.4 (I/O) I: 0; O: 1 0 0
S22 (see Note 1) X X 1
P8.5/S23 5 P8.5 (I/O) I: 0; O: 1 0 0
S23 (see Note 1) X X 1
NOTE 1: X: Don’t care
Port P8 (P8.6 to P8.7) pin functions
PIN NAME (P8 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P8.X) X FUNCTION P8DIR.x P8SEL.x LCDS24
P8.6/S24 6 P8.6 (I/O) I: 0; O: 1 0 0
S24 (see Note 1) X X 1
P8.7/S25 7 P8.7 (I/O) I: 0; O: 1 0 0
S25 (see Note 1) X X 1
NOTE 1: X: Don’t care
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
93
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P9, P9.0 to P9.7, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0:Input
1:Output
P9SEL.x
1
0
P9DIR.x
P9IN.x
LCDS8/12/16
Segment Sy
Pad Logic
DVSS
1
0
P9OUT.x
Note:x = 0,1,2,3,4,5,6,7
y= 17,16,15,14,13,12,11,10
P9.7/S10
P9.6/S11
P9.5/S12
P9.4/S13
P9.3/S14
P9.2/S15
P9.1/S16
P9.0/S17
DVSS
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
94 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P9 (P9.0 to P9.1) pin functions
PIN NAME (P9 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P9.X) X FUNCTION P9DIR.x P9SEL.x LCDS16
P9.0/S17 0 P9.0 (I/O) I: 0; O: 1 0 0
S17 (see Note 1) X X 1
P9.1/S16 1 P9.1 (I/O) I: 0; O: 1 0 0
S16 (see Note 1) X X 1
P9.2/S20 2 P9.2 (I/O) I: 0; O: 1 0 0
S15 (see Note 1) X X 1
P9.3/S21 3 P9.3 (I/O) I: 0; O: 1 0 0
S14 (see Note 1) X X 1
P9.4/S22 4 P9.4 (I/O) I: 0; O: 1 0 0
S13 (see Note 1) X X 1
P9.5/S23 5 P9.5 (I/O) I: 0; O: 1 0 0
S12 (see Note 1) X X 1
P9.6/S24 6 P9.6 (I/O) I: 0; O: 1 0 0
S11 (see Note 1) X X 1
P9.7/S25 7 P9.7 (I/O) I: 0; O: 1 0 0
S10 (see Note 1) X X 1
NOTE 1: X: Don’t care
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
95
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P10, P10.0 to P10.5, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P10SEL.x
1
0
P10DIR.x
P10IN.x
LCDS4/8
Segment Sy
Pad Logic
DVSS
1
0
P10OUT.x
Note:x = 0,1,2,3,4,5
y= 9,8,7,6,5,4
P10.5/S4
P10.4/S5
P10.3/S6
P10.2/S7
P10.1/S8
P10.0/S9
DVSS
Port P10 (P10.0 to P10.1) pin functions
PIN NAME (P10 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P10.X) X FUNCTION P10DIR.x P10SEL.x LCDS8
P10.0/S8 0 P10.0 (I/O) I: 0; O: 1 0 0
S8 (see Note 1) X X 1
P10.1/S7 1 P10.1 (I/O) I: 0; O: 1 0 0
S7 (see Note 1) X X 1
P10.2/S7 2 P10.2 (I/O) I: 0; O: 1 0 0
S7 (see Note 1) X X 1
P10.3/S6 3 P10.3 (I/O) I: 0; O: 1 0 0
S6 (see Note 1) X X 1
P10.4/S5 4 P10.4 (I/O) I: 0; O: 1 0 0
S5 (see Note 1) X X 1
P10.5/S4 5 P10.5 (I/O) I: 0; O: 1 0 0
S4 (see Note 1) X X 1
NOTE 1: X: Don’t care
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
96 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P10, P10.6, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P10SEL.x
1
0
P10DIR.x
P10IN.x
LCDS0
Segment Sy
1
0
P10OUT.x
Note: x = 6
y =3
P10.6/S3/A15
DVSS
INCH=15#
A15#
Pad Logic
Port P10 (P10.6) pin functions
PIN NAME (P10 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P10.X) X FUNCTION P10DIR.x P10SEL.x INCHx LCDS0
P10.6/S3/A15 6 P5.0 (I/O) (see Note 1) I: 0; O: 1 0 X 0
A15 (see Notes 1, 3) X 1 15 0
S3 enabled (see Note 1) X 0 X 1
S3 disabled (see Note 1) X 1 X 1
NOTES: 1. X: Don’t care
2. N/A: Not available or not applicable.
3. Setting the P10SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
97
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P10, P10.7, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P10SEL.x
1
0
P10DIR.x
P10IN.x
LCDS0
Segment Sy
1
0
P10OUT.x
Note: x = 7
y= 2
P10.7/S2/A14/OA2I1
DVSS
INCH=14#
A14#
Pad Logic
−
+
OA2
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
98 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P10 (P10.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P10.X) X FUNCTION P10DIR.x P10SEL.x INCHx OAPx (OA1)
OANx (OA1) LCDS0
P10.7/S2/A14/OA2I1 7 P10.7 (I/O) (see Note 1) I: 0; O: 1 0 X X 0
A14 (see Notes 1, 3) X 1 14 X 0
OA2I1 (see Notes 1, 3) 0 X X 1 0
S2 enabled (see Note 1) X 0 X X 1
S2 disabled (see Note 1) X 1 X X 1
NOTES: 1. X: Don’t care
2. N/A: Not available or not applicable.
3. Setting the P10SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
99
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VeREF+/DAC0
VeREF+ /DAC0
#
Reference Voltage to ADC12
1
0
’0’, if DAC12CALON = 0
DAC12AMPx>1 AND DAC12OPS=1
’1’, if DAC12AMPx=1
’1’, if DAC12AMPx>1
+
−
DAC12OPS
Reference Voltage to DAC1
Reference Voltage to DAC0
If the reference of DAC0 is taken from pin VeREF+ /DAC0, unpredictable voltage levels will be on pin.
In this situation, the DAC0 output is fed back to its own reference input.
#
DAC0_2_OA
DAC12.0OPS
1
0
P6.6/A6/DAC0/OA2I0
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
100 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger or output
TDI
TDO
TMS
TDI/TCLK
TDO/TDI
Controlled
by JTAG
TCK
TMS
TCK
DVCC
Controlled by JTAG
Test
JTAG
and
Emulation
Module
DVCC
DVCC
Burn and Test
Fuse
RST/NMI
GD
S
U
GD
S
U
TCK
Tau ~ 50 ns
Brownout
Controlled by JTAG
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
101
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity
of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current (I(TF)) of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be
taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see
Figure 37). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition). The JTAG pins are terminated internally and therefore do not require external termination.
Time TMS Goes Low After POR
TMS
I(TF)
ITDI/TCLK
Figure 37. Fuse Check Mode Current
MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
102 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Data Sheet Revision History
Literature
Number Summary
SLAS508 Preliminary Product Preview datasheet release
SLAS508A Production Data data sheet release
SLAS508B Changed power consumption values in features (page 1)
SLAS508C Changed tVALID,MO, tHD,SI, and tVALID,SO values (page 43)
SLAS508D Changed I(AM) values for CG461x (page 29)
SLAS508E
Added ZQW package information
Changed power consumption values for Standby and Off Modes in features (page 1)
Corrected description of P7.3/UCA0CLK/S30 terminal (page 7)
Clarified test conditions in recommended operating conditions table (page 30)
Changed I(AM) values for CG461x and all TYP values for I(LPM3) in supply current into AVCC + DVCC table (page 31)
Clarified test conditions in DCO table (page 42)
Clarified test conditions in USART table (page 48)
Clarified test conditions in operational amplifier OA, supply specifications table (page 59)
Clarified test conditions in operational amplifier OA, input/output specifications table (page 60)
SLAS508F Removed preview notice for MSP430CG461x in PZ package.
SLAS508G Removed preview notice for all devices in ZQW package.
SLAS508H Added “operational amplifier OA feedback network, noninverting amplifier mode (OAFCx = 4)” table
and “operational amplifier OA feedback network, inverting amplifier mode (OAFCx = 6)” table (page 62)
SLAS508I Changed limits on td(SVSon) parameter (page 40)
NOTE: Page and figure numbers refer to the respective document revision.
PACKAGE OPTION ADDENDUM
www.ti.com 9-May-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
MSP430FG4616IPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430FG4616IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430FG4616IZQW ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 113 250 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
MSP430FG4616IZQWR ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 113 2500 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
MSP430FG4616IZQWT ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 113 250 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
MSP430FG4617IPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430FG4617IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430FG4617IZQW ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 113 250 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
MSP430FG4617IZQWR ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 113 2500 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
MSP430FG4617IZQWT ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 113 250 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
MSP430FG4618IPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430FG4618IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430FG4618IZQW ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 113 250 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
PACKAGE OPTION ADDENDUM
www.ti.com 9-May-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
MSP430FG4618IZQWR ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 113 2500 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
MSP430FG4618IZQWT ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 113 250 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
MSP430FG4619IPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430FG4619IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430FG4619IZQW ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 113 250 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
MSP430FG4619IZQWR ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 113 2500 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
MSP430FG4619IZQWT ACTIVE BGA
MICROSTAR
JUNIOR
ZQW 113 250 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 9-May-2012
Addendum-Page 3
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
MSP430FG4616IZQWR BGA MI
CROSTA
R JUNI
OR
ZQW 113 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1
MSP430FG4616IZQWT BGA MI
CROSTA
R JUNI
OR
ZQW 113 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1
MSP430FG4617IZQWR BGA MI
CROSTA
R JUNI
OR
ZQW 113 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1
MSP430FG4617IZQWT BGA MI
CROSTA
R JUNI
OR
ZQW 113 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1
MSP430FG4618IZQWR BGA MI
CROSTA
R JUNI
OR
ZQW 113 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1
MSP430FG4618IZQWT BGA MI
CROSTA
R JUNI
ZQW 113 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Feb-2012
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
OR
MSP430FG4619IZQWR BGA MI
CROSTA
R JUNI
OR
ZQW 113 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1
MSP430FG4619IZQWT BGA MI
CROSTA
R JUNI
OR
ZQW 113 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
MSP430FG4616IZQWR BGA MICROSTAR
JUNIOR ZQW 113 2500 336.6 336.6 28.6
MSP430FG4616IZQWT BGA MICROSTAR
JUNIOR ZQW 113 250 336.6 336.6 28.6
MSP430FG4617IZQWR BGA MICROSTAR
JUNIOR ZQW 113 2500 336.6 336.6 28.6
MSP430FG4617IZQWT BGA MICROSTAR
JUNIOR ZQW 113 250 336.6 336.6 28.6
MSP430FG4618IZQWR BGA MICROSTAR
JUNIOR ZQW 113 2500 336.6 336.6 28.6
MSP430FG4618IZQWT BGA MICROSTAR ZQW 113 250 336.6 336.6 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Feb-2012
Pack Materials-Page 2
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
JUNIOR
MSP430FG4619IZQWR BGA MICROSTAR
JUNIOR ZQW 113 2500 336.6 336.6 28.6
MSP430FG4619IZQWT BGA MICROSTAR
JUNIOR ZQW 113 250 336.6 336.6 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Feb-2012
Pack Materials-Page 3
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK
4040149/B 11/96
50
26 0,13 NOM
Gage Plane
0,25
0,45
0,75
0,05 MIN
0,27
51
25
75
1
12,00 TYP
0,17
76
100
SQ
SQ
15,80
16,20
13,80
1,35
1,45
1,60 MAX
14,20
0°–7°
Seating Plane
0,08
0,50 M
0,08
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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