Rev.2.10 Dec 05, 2007 Page 1 of 57
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R8C/2C Group, R8C/2D Group
RENESAS MCU
1. Overview
1.1 Features
The R8C/2C Group and R8C/2D Group of single-chip MCUs incorporates the R8C/Tiny Series CPU core,
employing sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, and it is capable
of executing instructions at high speed. In addition, the CPU core boasts a multiplier for high-speed operation
processing.
Power consumption is low, and the supported operating modes allow additional power control. These MCUs also
use an anti-noise configuration to reduce emissions of electromagnetic noise and are designed to withstand EMI.
Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of
system components.
Furthermore, the R8C/2D Group has on-chip data flash (1 KB × 2 blocks).
The difference between the R8C/2C Group and R8C/2D Group is only the presence or absence of dat a flash. Their
peripheral functions are the same.
1.1.1 Applications
Electronic household appli a nces, office equipment, audio equipment, consumer equipment, etc.
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1.1.2 Specifications
Tables 1.1 and 1.2 outlines the Specifications for R8C/2C Group and Tables 1.3 and 1.4 outlines the
Specification s for R8C/2D Group.
Table 1.1 Specific ations for R8C/2C Group (1)
Item Function Specification
CPU Central processing
unit R8C/Tiny series core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operation mode: Single-chip mode (address space: 1 Mbyte)
Memory ROM, RAM Refer to Table 1.5 Product List for R8C/2C Group.
Power Supply
Voltage
Detection
Volt age detection
circuit • Power-on reset
• Voltage detection 3
I/O Ports Programmable I/O
ports • Input-only: 2 pins
• CMOS I/O ports: 71, selectable pull-up resistor
• High current drive port s: 8
Clock Clock generation
circuits 3 circuits: XIN clock oscillation circuit (with on-chip feedback resistor),
On-chip oscillator (high-speed, low-speed)
(high-speed on-chip oscillator has a frequency adjustment function),
XCIN clock oscillation circuit (32 kHz)
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16
• Low power consumption modes:
Standard operating mode (high-speed clock, low-speed clock, high-speed
on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode
Real-time clock (timer RE)
Interrupts • External: 5 so urces, Internal: 23 sources, Software: 4 sources
• Priority levels: 7 levels
Watchdog Timer 15 bits × 1 (with prescaler), reset start selectable
Timer Timer RA 8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), pulse output mode (output le vel inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
Timer RB 8 bits × 1 (with 8-bit prescaler)
T imer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programma ble wait one-
shot generation mode
Timer RC 16 bits × 1 (w it h 4 capt ure/comp a r e reg i ste r s)
Timer mode (input capture function, output compare function), PWM mode
(output 3 pins), PWM2 mode (PWM output pin)
Timer RD 16 bits × 2 (w it h 4 capt ure/comp a r e reg i ste r s)
Timer mode (input capture function, output compare function), PWM mode
(output 6 pins), reset synchronous PWM mode (output three-phase
waveforms (6 pins), sawtooth wave modulation), complementary PWM mode
(output three-phase waveforms (6 pins), triangular wave modulation), PWM3
mode (PWM output 2 pins with fixed period)
Timer RE 8 bits × 1
Real-time clock mode (count seconds, minutes, hours, days of week), output
compare mode
Timer RF 16 bits × 1 (with capture/compare register pin and compare register pin)
Input capture mode, output compare mode
R8C/2C Group, R8C/2D Group 1. Overview
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NOTES:
1. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
2. Specify the D version if D version functions are to be used.
3. Please contact Renesas Technology sales offices for the Y version.
Table 1.2 Specific ations for R8C/2C Group (2)
Item Function Specification
Serial
Interface UART0, UART1,
UART2 Clock synchronous serial I/O/UART × 3
Clock Synchronous Serial I/O with
Chip Select (SSU) 1 (shared with I2C-bus)
I2C bus(1) 1 (shared with SSU)
LIN Module Hardware LIN: 1 (timer RA, UART0)
A/D Converter 10-bit resolution × 20 channels, includes sample and hold function, with sweep
mode
D/A Converter 8-bit resolution × 2 circuits
Flash Memory • Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 100 times
• Program security: ROM code protect, ID code check
• Debug functions: On-chip deb ug, on-board flash rewrite function
Operating Frequency/Supply
Voltage f(XIN) = 20 MHz (VCC = 3.0 to 5.5 V)
f(XIN) = 10 MHz (VCC = 2.7 to 5.5 V)
f(XIN) = 5 MHz (VCC = 2.2 to 5.5 V)
Current consumption 12 mA (VCC = 5.0 V, f(XIN) = 20 MHz)
5.5 mA (VCC = 3.0 V, f(XIN) = 10 MHz)
2.1 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz))
0.65 µA (VCC = 3.0 V, stop mode)
Operating Ambient Temperature -20 to 85°C (N version)
-40 to 85°C (D version)(2)
-20 to 105°C (Y version)(3)
Package 80-pin LQFP
Package code: PLQP0080KB-A (previous code: 80P6Q-A)
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Table 1.3 Specific ations for R8C/2D Group (1)
Item Function Specification
CPU Central processing
unit R8C/Tiny series core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operation mode: Single-chip mode (address space: 1 Mbyte)
Memory ROM, RAM Refer to Table 1.6 Product List for R8C/2D Group.
Power Supply
Voltage
Detection
Volt age detection
circuit • Power-on reset
• Voltage detection 3
I/O Ports Programmable I/O
ports • Input-only: 2 pins
• CMOS I/O ports: 71, selectable pull-up resistor
• High current drive port s: 8
Clock Clock generation
circuits 3 circuits: XIN clock oscillation circuit (with on-chip feedback resistor),
On-chip oscillator (high-speed, low-speed)
(high-speed on-chip oscillator has a frequency adjustment function),
XCIN clock oscillation circuit (32 kHz)
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16
• Low power consumption modes:
Standard operating mode (high-speed clock, low-speed clock, high-speed
on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode
Real-time clock (timer RE)
Interrupts • External: 5 so urces, Internal: 23 sources, Software: 4 sources
• Priority levels: 7 levels
Watchdog Timer 15 bits × 1 (with prescaler), reset start selectable
Timer Timer RA 8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), pulse output mode (output le vel inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
Timer RB 8 bits × 1 (with 8-bit prescaler)
T imer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programma ble wait one-
shot generation mode
Timer RC 16 bits × 1 (w it h 4 capt ure/comp a r e reg i ste r s)
Timer mode (input capture function, output compare function), PWM mode
(output 3 pins), PWM2 mode (PWM output pin)
Timer RD 16 bits × 2 (w it h 4 capt ure/comp a r e reg i ste r s)
Timer mode (input capture function, output compare function), PWM mode
(output 6 pins), reset synchronous PWM mode (output three-phase
waveforms (6 pins), sawtooth wave modulation), complementary PWM mode
(output three-phase waveforms (6 pins), triangular wave modulation), PWM3
mode (PWM output 2 pins with fixed period)
Timer RE 8 bits × 1
Real-time clock mode (count seconds, minutes, hours, days of week), output
compare mode
Timer RF 16 bits × 1 (with capture/compare register pin and compare register pin)
Input capture mode, output compare mode
R8C/2C Group, R8C/2D Group 1. Overview
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NOTES:
1. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
2. Specify the D version if D version functions are to be used.
3. Please contact Renesas Technology sales offices for the Y version.
Table 1.4 Specific ations for R8C/2D Group (2)
Item Function Specification
Serial
Interface UART0, UART1,
UART2 Clock synchronous serial I/O/UART × 3
Clock Synchronous Serial I/O with
Chip Select (SSU) 1 (shared with I2C-bus)
I2C bus(1) 1 (shared with SSU)
LIN Module Hardware LIN: 1 (timer RA, UART0)
A/D Converter 10-bit resolution × 20 channels, includes sample and hold function, with sweep
mode
D/A Converter 8-bit resolution × 2 circuits
Flash Memory • Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 10,000 times (data flash)
1,000 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip deb ug, on-board flash rewrite function
Operating Frequency/Supply
Voltage f(XIN) = 20 MHz (VCC = 3.0 to 5.5 V)
f(XIN) = 10 MHz (VCC = 2.7 to 5.5 V)
f(XIN) = 5 MHz (VCC = 2.2 to 5.5 V)
Current consumption 12 mA (VCC = 5.0 V, f(XIN) = 20 MHz)
5.5 mA (VCC = 3.0 V, f(XIN) = 10 MHz)
2.1 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz))
0.65 µA (VCC = 3.0 V, stop mode)
Operating Ambient Temperature -20 to 85°C (N version)
-40 to 85°C (D version)(2)
-20 to 105°C (Y version)(3)
Package 80-pin LQFP
Package code: PLQP0080KB-A (previous code: 80P6Q-A)
R8C/2C Group, R8C/2D Group 1. Overview
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1.2 Product List
Table 1.5 lists Product List for R8C/2C Group, Figure 1.1 shows a Part Number, Memory Size, and Package of
R8C/2C Group, T able 1.6 lists Product List for R8C/2D Group, and Figure 1.2 shows a Part Number, Memory Size,
and Package of R8C/2D Group.
NOTE:
1. The user ROM is programmed before shipment.
Table 1.5 Product List for R8C/2C Group Current of Dec. 2007
Part No. ROM Capacity RAM Capacity Package Type Remarks
R5F212C7SNFP 48 Kbytes 2.5 Kbytes PLQP0080KB-A N version
R5F212C8SNFP 64 Kbytes 3 Kbytes PLQP0080KB-A
R5F212CASNFP 96 Kbytes 7 Kbytes PLQP0080KB-A
R5F212CCSNFP 128 Kbytes 7.5 Kbytes PLQP0080KB-A
R5F212C7SDFP 48 Kbytes 2.5 Kbytes PLQP0080KB-A D version
R5F212C8SDFP 64 Kbytes 3 Kbytes PLQP0080KB-A
R5F212CASDFP 96 Kbytes 7 Kbytes PLQP0080KB-A
R5F212CCSDFP 128 Kbytes 7.5 Kbytes PLQP0080KB-A
R5F212C7SNXXXF P 48 Kbytes 2. 5 Kby tes PLQP0080KB-A N version Factory
programming
product(1)
R5F212C8SNXXXFP 64 Kbytes 3 Kbytes PLQP0080KB-A
R5F212CASNXXXFP 96 Kbytes 7 Kbytes PLQP0080KB-A
R5F212CCSNXXXFP 128 Kbytes 7.5 Kbytes PLQP0080KB-A
R5F212C7SDXXXF P 48 Kby tes 2.5 Kbytes PLQP0080KB-A D version
R5F212C8SDXXXFP 64 Kbytes 3 Kbytes PLQP0080KB-A
R5F212CASDXXXFP 96 Kbytes 7 Kbytes PLQP0080KB-A
R5F212CCSDXXXFP 128 Kbytes 7.5 Kbytes PLQP0080KB-A
R8C/2C Group, R8C/2D Group 1. Overview
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Figure 1.1 Part Number, Memory Size, and Package of R8C/2C Group
Part No. R 5 F 21 2C 7 S N XXX FP
Package type:
FP: PLQP0080KB-A (0.5 mm pin-pitch, 12 mm square body)
ROM number
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
Y: Operating ambient temperature -20°C to 105°C (1)
S: Low-voltage version
ROM capacity
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/2C Group
R8C/Tiny Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
NOTE:
1. Please contact Renesas Technology sales offices for the Y version.
R8C/2C Group, R8C/2D Group 1. Overview
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NOTE:
1. The user ROM is programmed before shipment.
Figure 1.2 Part Number, Memory Size, and Package of R8C/2D Group
Table 1.6 Product List for R8C/2D Group Current of Dec. 2007
Part No. ROM Capacity RAM
Capacity Package Type Remarks
Program ROM Data flash
R5F212D7SNFP 48 Kbytes 1 Kbyte × 2 2.5 Kbytes PLQP0080KB-A N version
R5F212D8SNFP 64 Kbytes 1 Kbyte × 2 3 Kbytes PLQP0080KB-A
R5F212DASNFP 96 Kbytes 1 Kbyte × 2 7 Kbytes PLQP0080KB-A
R5F212DCSNFP 128 Kbytes 1 Kbyte × 2 7.5 Kbytes PLQP0080KB-A
R5F212D7SDFP 48 Kbytes 1 Kbyte × 2 2.5 Kbytes PLQP0080KB-A D version
R5F212D8SDFP 64 Kbytes 1 Kbyte × 2 3 Kbytes PLQP0080KB-A
R5F212DASDFP 96 Kbytes 1 Kbyte × 2 7 Kbytes PLQP0080KB-A
R5F212DCSDFP 128 Kbytes 1 Kbyte × 2 7.5 Kbytes PLQP0080KB-A
R5F212D7SNXXXFP 48 Kbytes 1 Kbyte × 2 2.5 Kbytes PLQP0080KB-A N version Factory
programming
product(1)
R5F212D8SNXXXFP 64 Kbytes 1 Kbyte × 2 3 Kbytes PLQP0080KB-A
R5F212DASNXXXFP 96 Kbytes 1 Kbyte × 2 7 Kbytes PLQP0080KB-A
R5F212DCSNXXXFP 128 Kbytes 1 Kbyte × 2 7.5 Kbytes PLQP0080KB-A
R5F212D7SDXXXFP 48 Kbytes 1 Kbyte × 2 2.5 Kbytes PLQP0080KB-A D version
R5F212D8SDXXXFP 64 Kbytes 1 Kbyte × 2 3 Kbytes PLQP0080KB-A
R5F212DASDXXXFP 96 Kbytes 1 Kbyte × 2 7 Kbytes PLQP0080KB-A
R5F212DCSDXXXFP 128 Kbytes 1 Kbyte × 2 7.5 Kbytes PLQP0080KB-A
Part No. R 5 F 21 2D 7 S N XXX FP
Package type:
FP: PLQP0080KB-A (0.5 mm pin-pitch, 12 mm square body)
ROM number
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
Y: Operating ambient temperature -20°C to 105°C (1)
S: Low-voltage version
ROM capacity
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/2D Group
R8C/Tiny Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
NOTE:
1. Please contact Renesas Technology sales offices for the Y version.
R8C/2C Group, R8C/2D Group 1. Overview
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1.3 Block Diagram
Figure 1.3 shows a Block Diagram.
Figure 1.3 Block Diagra m
D/A converter
(8 bits × 2) R8C/Tiny Series CPU core
System clock generation
circuit
XIN-XOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
XCIN-XCOUT
Memory
ROM(1)
RAM(2)
Multiplier
R0H R0L
R1H R2
R3
R1L
A0
A1
FB
SB
USP
ISP
INTB
PC
FLG
I/O ports
NOTES:
1. ROM size varies with MCU ty pe.
2. RAM size v aries wit h MCU t y pe.
8
Port P1
8
Port P3
3 2
Port P4
8
Port P0
8
Port P2
8
Port P5
Timers
Timer RA (8 bits × 1)
Timer RB (8 bits × 1)
Timer RC (16 bits × 1)
Timer RD (16 bits × 2)
Timer RE (8 bi t s × 1)
Timer RF (16 bits × 1)
UART or
clock synchronous serial I/O
(8 bits × 3)
I2C bus or SSU
(8 bits × 1)
Peripheral functions
Watchdog timer
(15 bits)
A/D converter
(10 bits × 20 channels)
LIN module
8
Port P6
8
Port P7
8
Port P8
4
Port P9
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1.4 Pin Assignment
Figure 1.4 shows Pin Assignment (Top View). Tables 1.7 and 1.8 outlines the Pin Name Information by Pin
Number.
Figure 1.4 Pin Assignment (Top View)
48 47 46 45 44 43 42 4160 59 58 57 56 55 54 53
33
34
35
36
21
22
23
24
25
26
27
28
29
30
31
32
1 3456789101112131415162
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
P7_0/AN12
P3_5/SCL/SSCK
P3_7/SSO
VCC/AVCC
VREF
P0_7/AN0/DA1
VSS/AVSS
P0_6/AN1/DA0
P0_5/AN2/CLK1
P6_1
P6_2
P0_3/AN4
P0_2/AN5
P0_0/AN7
P0_1/AN6
P0_4/AN3
P8_2/TRFO02
P2_6/TRDIOC1
P2_5/TRDIOB1
P2_4/TRDIOA1
P2_3/TRDIOD0
P2_2/TRDIOC0
P2_1/TRDIOB0
P2_0/TRDIOA0/TRDCLK
P1_7/TRAIO/INT1
P1_6/CLK0
P1_5/RXD0/(TRAIO)/(INT1)(2)
P8_6
P8_5/TRFO12
P8_3/TRFO10/TRFI
P8_4/TRFO11
P1_4/TXD0
P7_5/AN17
P6_6/INT2/TXD1
P6_7/INT3/RXD1
P6_5/(CLK1)/CLK2(2)
P6_4/RXD2
P6_3/TXD2
P3_1/TRBO
P3_0/TRAO
P3_6/(INT1)(2)
P3_2/(INT2)(2)
P1_3/Kl3/AN11
P1_1/Kl1/AN9
P1_0/Kl0/AN8
P7_6/AN18
P7_7/AN19
P1_2/Kl2/AN10
P3_3/SSI
P9_2
P5_0/TRCCLK
P5_1/TRCIOA/TRCTRG
P5_2/TRCIOB
P5_3/TRCIOC
P5_4/TRCIOD
VCC/AVCC
P4_6/XIN
VSS/AVSS
P4_7/XOUT(1)
P4_4/XCOUT
P4_3/XCIN
P3_4/SDA/SCS
MODE
RESET
17 18 19 20
37
38
39
40
52 51 50 49
64
63
62
61
P8_1/TRFO01
P8_0/TRFO00
P6_0/TREO
P4_5/INT0
P9_1
P9_0
P2_7/TRDIOD1
P8_7
P9_3
P5_7
P5_6
P5_5
P7_4/AN16
P7_1/AN13
P7_3/AN15
P7_2/AN14
R8C/2C Group
R8C/2D Group
PLQP0080KB-A(80P6Q-A)
(top view)
NOTES:
1. P4_7/XOUT are an input-only port.
2. Can be assigned t o the pin in pa rentheses by a program.
3. Confirm the pin 1 position on the packag e by referring to the package dimensions.
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NOTE:
1. Can be assigned to the pin in parentheses by a program.
Table 1.7 Pin Name Information by Pin Number (1)
Pin
Number Control Pin Port I/O Pin Functions for of Peripheral Modules
Interrupt Timer Serial
Interface SSU I2C bus
A/D Converter,
D/A Converter
1 P3_3 SSI
2 P3_4 SCS SDA
3 P5_7
4 P5_6
5 P5_5
6MODE
7 XCIN P4_3
8 XCOUT P4_4
9RESET
10 XOUT P4_7
11 VSS/AVSS
12 XIN P4_6
13 VCC/AVCC
14 P5_4 TRCIOD
15 P5_3 TRCIOC
16 P5_2 TRCIOB
17 P5_1 TRCIOA/TRCTRG
18 P5_0 TRCCLK
19 P9_3
20 P9_2
21 P9_1
22 P9_0
23 P2_7 TRDIOD1
24 P2_6 TRDIOC1
25 P2_5 TRDIOB1
26 P2_4 TRDIOA1
27 P2_3 TRDIOD0
28 P2_2 TRDIOC0
29 P2_1 TRDIOB0
30 P2_0 TRDIOA0/ TRDCLK
31 P1_7 INT1 TRAIO
32 P1_6 CLK0
33 P1_5 (INT1)(1) (TRAIO)(1) RXD0
34 P1_4 TXD0
35 P8_7
36 P8_6
37 P8_5 TRFO12
38 P8_4 TRFO11
39 P8_3 TRFO10/TRFI
40 P8_2 TRFO02
41 P8_1 TRFO01
42 P8_0 TRFO00
43 P6_0 TREO
44 P4_5 INT0 INT0
45 P6_6 INT2 TXD1
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NOTE:
1. Can be assigned to the pin in parentheses by a program.
Table 1.8 Pin Name Information by Pin Number (2)
Pin
Number Control Pin Port I/O Pin Functions for of Peripheral Modules
Interrupt Timer Serial
Interface SSU I2C bus
A/D Converter,
D/A Converter
46 P6_7 INT3 RXD1
47 P6_5 (CLK1)(1)
/CLK2
48 P6_4 RXD2
49 P6_3 TXD2
50 P3_1 TRBO
51 P3_0 TRAO
52 P3_6 (INT1)(1)
53 P3_2 (INT2)(1)
54 P1_3 KI3 AN11
55 P1_2 KI2 AN10
56 P1_1 KI1 AN9
57 P1_0 KI0 AN8
58 P7_7 AN19
59 P7_6 AN18
60 P7_5 AN17
61 P7_4 AN16
62 P7_3 AN15
63 P7_2 AN14
64 P7_1 AN13
65 P7_0 AN12
66 P0_0 AN7
67 P0_1 AN6
68 P0_2 AN5
69 P0_3 AN4
70 P0_4 AN3
71 P6_2
72 P6_1
73 P0_5 CLK1 AN2
74 P0_6 AN1/DA0
75 VSS/AVSS
76 P0_7 AN0/DA1
77 VREF
78 VCC/AVCC
79 P3_7 SSO
80 P3_5 SSCK SCL
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1.5 Pin Functions
Tables 1.9 and 1.10 list Pin Functions.
I: Input O: Output I/O: Input and output
NOTE:
1. Refer to the oscillator manufacturer for oscillation characteristics.
Table 1.9 Pin Functions (1)
Item Pin Name
I/O Type
Description
Power supply input VCC, VSS −Apply 2.2 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin.
Analog power
supply input AVCC, AVSS −Power supply for the A/D converter.
Connect a capacitor between AVCC and AVSS.
Reset input RESET I Input “L” on this pin resets the MCU.
MODE MODE I Connect this pin to VCC via a resistor.
XIN clock input XIN I These pins are provided for XIN clock generation circuit I/O.
Connect a ceramic resonator or a crystal oscillator between
the XIN and XOUT pins(1). To use an external clock, input it to
the XIN pin and leave the XOUT pin open.
XIN clock output XOUT O
XCIN clock input XCIN I These pins are provided for XCIN clock generation circuit I/O.
Connect a crystal oscillator between the XCIN and XCOUT
pins(1). To use an external clock, input it to the XCIN pin and
leave the XCOUT pin open.
XCIN clock output XCOUT O
INT interrupt input INT0 to INT3 IINT interrupt input pins.
INT0 is timer RD input pin. INT1 is timer RA input pin.
Key input interrupt KI0 to KI3 I Key input interrupt input pins
Timer RA TRAIO I/O Timer RA I/O pin
TRAO O Timer RA output pin
Timer RB TRBO O Timer RB output pin
Timer RC TRCCLK I External clock input pin
TRCTRG I External trigger input pin
TRCIOA, TRCIOB,
TRCIOC, TRCIOD I/O Timer RC I/O pins
Timer RD TRDIOA0, TRDIOA1,
TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1,
TRDIOD0, TRDIOD1
I/O Timer RD I/O pins
TRDCLK I External clock input pin
Timer RE TREO O Divided clock output pin
Timer RF TRFI I Timer RF input pin
TRFO00 to TRFO02,
TRFO10 to TRFO12 O Timer RF output pins
Serial interface CLK0, CLK1, CLK2 I/O Transfer clock I/O pins
RXD0, RXD1, RXD2 I Serial da ta input pins
TXD0, TXD1, TXD2 O Serial data output pins
I2C bus SCL I/O Clock I/O pin
SDA I/O Data I/O pin
SSU SSI I/O Data I/O pin
SCS I/O Chip-select signal I/O pin
SSCK I/O Clock I/O pin
SSO I/O Data I/O pin
Reference voltage
input VREF I Reference voltage input pin to A/D converter and D/A
converter
R8C/2C Group, R8C/2D Group 1. Overview
Rev.2.10 Dec 05, 2007 Page 14 of 57
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I: Input O: Output I/O: Input and output
Table 1.10 Pin Functions (2)
Item Pin Name
I/O Type
Description
A/D converter AN0 to AN19 I Analo g input pins to A/D converter
D/A converter DA0 to DA1 O D/A converter output pins
I/O port P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_7,
P3_0 to P3_7,
P4_3 to P4_5,
P5_0 to P5_7,
P6_0 to P6_7,
P7_0 to P7_7,
P8_0 to P8_7,
P9_0 to P9_3
I/O CMOS I/O ports. Each port has an I/O select direction
register, allowing each pin in the port to be directed for input
or output individually.
Any port set to input can be set to use a pull-up resistor or not
by a program.
P2_0 to P2_7 also function as LED drive ports.
Input port P4_6, P4_7 I Input-only ports
R8C/2C Group, R8C/2D Group 2. Central Processing Unit (CPU)
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2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register bank.
Figure 2.1 CPU Registers
R2
b31 b15 b8b7 b0
Data registers(1)
Address registers(1)
R3 R0H (high-order of R0)
R2
R3
A0
A1
INTBHb15b19 b0
INTBL
FB Frame base register(1)
The 4 high order bits of INTB are INTBH and
the 16 low order bits of INTB are INTBL.
Interrupt table register
b19 b0
USP
Program counter
ISP
SB
User stack pointer
Interrupt stack pointer
Static base register
PC
FLG Flag register
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bi t
Processor interrupt priority level
Reserved bi t
C
IPL DZSBOIU
b15 b0
b15 b0
b15 b0
b8 b7
NOTE:
1. These registers comprise a register bank. There are two register banks.
R1H (high-order of R1)
R0L (low-order of R0)
R1L (low-order of R1)
R8C/2C Group, R8C/2D Group 2. Central Processing Unit (CPU)
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2.1 Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R 0H) and low-order bit s (R0L) to be used sep aratel y as 8-bit data regist ers. R1H and R 1L are
analogous to R0H and R0L. R2 can be combined with R0 and used a s a 32-bit data regi ster (R2R0). R3R1 is
analogous to R2R0.
2.2 Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer , arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32-
bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7 Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8 Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1 Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2 Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3 Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4 Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative valu e; otherwise to 0.
2.8.5 Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6 Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
R8C/2C Group, R8C/2D Group 2. Central Processing Unit (CPU)
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2.8.7 Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor inte rrupt priorit y levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
If necessary, set to 0. When read, the content is undefined.
R8C/2C Group, R8C/2D Group 3. Memory
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3. Memory
3.1 R8C/2C Group
Figure 3.1 is a Memory Map of R8C/2C Group. The R8C/2C group has 1 Mbyte of address space from addresses
00000h to FFFFFh.
The internal ROM is allocated lower addresses, beginning with address 0 FFFFh. For exam ple, a 48 -Kbyte i nternal
ROM area is allocated addresses 04000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 2.5-Kbyte internal
RAM area is allocated addresses 00400h to 00DFFh. The internal RAM is used not only for storing data but also
for calling subroutines and as stacks when interrupt requests are acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control
registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use
and cannot be accessed by users.
Figure 3.1 Memory Map of R8C/2 C Group
Undefined inst ruction
Overflow
BRK instruct ion
Address match
Single step
Watchdog timer, oscillation stop detection, voltage monitor
(Reserved)
(Reserved)
Reset
Internal ROM Internal RAM
Size Address 0YYYYh
48 Kbytes
64 Kbytes
96 Kbytes
128 Kby t e s
−
13FFFh
1BFFFh
23FFFh
00DFFh
00FFFh
011FFh
011FFh
00400h
002FFh
00000h
Internal RAM
SFR
(Refer to 4. Special
Function Registers
(SFRs))
0FFFFh
0FFDCh
Address 0XXXXh
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Address ZZZZZh Size
2.5 Kbytes
3 Kbyt e s
7 Kbyt e s
7.5 Kbytes
04000h
04000h
04000h
04000h
FFFFFh
0FFFFh
0YYYYh Internal ROM
(program ROM)
Expanded area
Internal ROM
(program ROM)
ZZZZZh
0XXXXh
03000h Internal RAM
0WWWWh
−
−
03DFFh
03FFFh
Address 0WWWWh
R8C/2C Group, R8C/2D Group 3. Memory
Rev.2.10 Dec 05, 2007 Page 19 of 57
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3.2 R8C/2D Group
Figure 3.2 is a Memory Map of R8C/2D Group. The R8C/2D group has 1 Mbyte of address space from addresses
00000h to FFFFFh.
The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a
48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal ROM (data flash) is allocated addresses 02400h to 02BFFh.
The internal RAM area is allocated higher addresses, beginning with address 00400h. For example, a 2.5-Kbyte
internal RAM is allocated addresses 00400h to 00DFFh. The internal RAM is used not only for storing data but
also for calling subroutines and as stacks when interrupt requests are acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control
registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use
and cannot be accessed by users.
Figure 3.2 Memory Map of R8C/2 D Group
Undefined instruc tion
Overflow
BRK instruct ion
Address match
Single step
Watchdog timer, oscillation stop detection, voltage monitor
(Reserved)
(Reserved)
Reset
Internal ROM Internal RAM
Size Address 0YYYYh
48 Kbytes
64 Kbytes
96 Kbytes
128 Kby t e s
00DFFh
00FFFh
011FFh
011FFh
FFFFFh
0FFFFh
0YYYYh
00400h
002FFh
00000h
Internal ROM
(program ROM)
Expanded area
Internal RAM
SFR
(Refer to 4. Special
Function Registers
(SFRs))
0FFFFh
0FFDCh
Address 0XXXXhAddress ZZZZZh Size
2.5 Kbytes
3 Kbytes
7 Kbytes
7.5 Kbytes
Internal ROM
(data fl a s h)(1)
NOTES:
1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown.
2. The blank regions are reserved. Do not access locations in these regions.
0XXXXh
02400h
02BFFh
Internal ROM
(program ROM)
ZZZZZh
−
13FFFh
1BFFFh
23FFFh
04000h
04000h
04000h
04000h
03000h Internal RAM
0WWWWh
−
−
03DFFh
03FFFh
Address 0WWWWh
R8C/2C Group, R8C/2D Group 4. S pecial Function Registers (SFRs)
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4. Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.12 list the special
function registers.
Table 4.1 SFR Information (1)(1)
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Software reset, wat chdog timer reset, voltage monit or 1 reset, or voltage monitor 2 reset do not affect this register.
3. The LVD0ON bit in the OFS register is set to 1 and hardware reset.
4. Power-on reset, voltage monitor 0 rese t, or the LVD0ON bit in the OFS register is set to 0 and hardware reset.
5. Software reset, wat chdog timer reset, voltage monit or 1 reset, or voltage monitor 2 reset do not affect b2 and b3.
6. The CSPROINI bit in the OFS register is set to 0.
Address Register Symbol After reset
0000h
0001h
0002h
0003h
0004h Processor Mode Register 0 PM0 00h
0005h Processor Mode Register 1 PM1 00h
0006h System Clock Control Register 0 CM0 01101000b
0007h System Clock Control Register 1 CM1 00100000b
0008h Module Operation Ena ble Register MSTCR 00h
0009h
000Ah Protect Register PRCR 00h
000Bh
000Ch Oscillation S top Detection Register OCD 00000100b
000Dh Watchdog Timer Reset Register WDTR XXh
000Eh Watchdog Timer Start Register WDTS XXh
000Fh Watchdog Timer Control Regi ster WDC 00X11111b
0010h Address Match Interrupt Register 0 RMAD0 00h
0011h 00h
0012h 00h
0013h Address Match Interrupt Enable Register AIER 00h
0014h Address Match Interrupt Register 1 RMAD1 00h
0015h 00h
0016h 00h
0017h
0018h
0019h
001Ah
001Bh
001Ch Count Source Protection Mode Register CSPR 00h
10000000b(6)
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h High-Speed On-Chip Oscillator Control Register 0 FRA0 00h
0024h High-Speed On-Chip Oscillator Control Register 1 FRA1 When shipping
0025h High-Speed On-Chip Oscillator Control Register 2 FRA2 00h
0026h
0027h
0028h Clock Prescaler Reset Flag CPSRF 00h
0029h
002Ah
002Bh High-Speed On-Chip Oscillator Control Register 6 FRA6 When Shipping
002Ch High-Speed On-Chip Oscillator Control Register 7 FRA7 When Shipping
0030h
0031h Voltage Detection Register 1 (2) VCA1 00001000b
0032h Voltage Detection Register 2 (2) VCA2 00h(3)
00100000b(4)
0033h
0034h
0035h
0036h Voltage Monitor 1 Circuit Control Register(5) VW1C 00001000b
0037h Voltage Monitor 2 Circuit Control Register(5) VW2C 00h
0038h Voltage Monitor 0 Circuit Control Register(2) VW0C 0000X000b(3)
0100X001b(4)
0039h
003Ah
003Eh
003Fh
R8C/2C Group, R8C/2D Group 4. S pecial Function Registers (SFRs)
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Table 4.2 SFR Information (2)(1)
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Selected by the IICSEL bi t in the PMR register.
Address Register Symbol After reset
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h Timer RC Interrupt Control Register TRCIC XXXXX000b
0048h Timer RD0 Interrupt Control Register TRD0IC XXXXX000b
0049h Timer RD1 Interrupt Control Register TRD1IC XXXXX000b
004Ah Timer RE Interrupt Control Register TREIC XXXXX000b
004Bh UART2 Transmi t Interrupt Control Register S2TIC XXXXX000b
004Ch UART2 Receive Interrupt Control Register S2RIC XXXXX000b
004Dh Key Input Interrupt Control Register KUPIC XXXXX000b
004Eh
004Fh SSU/IIC Interrupt Control Register(2) S SUIC / IICIC XXXXX000b
0050h Compare 1 Interrupt Control Register CMP1IC XXXXX000b
0051h UART0 Transmit Interrupt Control Regist er S0TIC XXXXX000b
0052h UART0 Receive In terrupt Control Register S0RIC XXXXX000b
0053h UART1 Transmit Interrupt Control Register S1TIC XXXXX000b
0054h UART1 Receive In terrupt Control Register S1RIC XXXXX000b
0055h INT2 Interrupt Control Register INT2IC XX00X000b
0056h Timer RA Interrupt Control Register TRAIC XXXXX000b
0057h
0058h Timer RB Interrupt Control Register TRBIC XXXXX000b
0059h INT1 Interrupt Control Register INT1IC XX00X000b
005Ah INT3 Interrupt Control Register INT3IC XX00X000b
005Bh Timer RF Interrupt Control Register TRFIC XXXXX000b
005Ch Compare 0 Interrupt Control Register CMP0IC XXXXX000b
005Dh INT0 Interrupt Control Register INT0IC XX00X000b
005Eh A/D Conversion Interrupt Control Register ADIC XXXXX000b
005Fh Capture Interrupt Control Register CAPIC XXXXX000b
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
R8C/2C Group, R8C/2D Group 4. S pecial Function Registers (SFRs)
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Table 4.3 SFR Information (3)(1)
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Selected by the IICSEL bi t in the PMR register.
Address Register Symbol After reset
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h UART0 Transmit/Receive Mode Register U0MR 00h
00A1h UART0 Bit Ra te Register U0BRG XXh
00A2h UART0 Transmi t Buffer Register U0TB XXh
00A3h XXh
00A4h UART0 Transmit/ R eceive Control Register 0 U0C0 00001000b
00A5h UART0 Transmit/ R eceive Control Register 1 U0C1 00000010b
00A6h UART0 Receive Buffer Register U0RB XXh
00A7h XXh
00A8h UART1 Transmit/Receive Mode Register U1MR 00h
00A9h UART1 Bit Ra te Register U1BRG XXh
00AAh UART1 Transmi t Buffer Register U1TB XXh
00ABh XXh
00ACh UART1 Transmit/Receive Control Register 0 U1C0 00001000b
00ADh UART1 Transmit/Receive Control Register 1 U1C1 00000010b
00AEh UART1 Receive Buffer Register U1RB XXh
00AFh XXh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h SS Control Register H / IIC bus Control Register 1(2) SSCRH / ICCR1 00h
00B9h SS Control Register L / IIC bus Control Register 2(2) SSCRL / ICCR2 01111101b
00BAh SS Mode Register / IIC bus Mode Regist er(2) SSMR / ICMR 00011000b
00BBh SS Enable Register / IIC bus Interrupt Enable Register(2) SSER / ICIER 00h
00BCh SS Sta tus Regist er / IIC bus Status Register(2) SSSR / ICSR 00h / 0000X000b
00BDh SS Mode Register 2 / Slave Address Register(2) SSMR2 / SAR 00h
00BEh SS Transmit Data Register / IIC bus Transmit Data Register(2) SSTDR / ICDRT FFh
00BFh SS Receive Data Register / IIC bus Receive Data Register(2) SSRDR / ICDRR FFh
R8C/2C Group, R8C/2D Group 4. S pecial Function Registers (SFRs)
Rev.2.10 Dec 05, 2007 Page 23 of 57
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Table 4.4 SFR Information (4)(1)
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Address Register Symbol After reset
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h D/A Register 0 DA0 00h
00D9h
00DAh D/A Register 1 DA1 00h
00DBh
00DCh D/A Control Register DACON 00h
00DDh
00DEh
00DFh
00E0h Port P0 Register P0 XXh
00E1h Port P1 Register P1 XXh
00E2h Port P0 Direction Register PD0 00h
00E3h Port P1 Direction Register PD1 00h
00E4h Port P2 Register P2 XXh
00E5h Port P3 Register P3 XXh
00E6h Port P2 Direction Register PD2 00h
00E7h Port P3 Direction Register PD3 00h
00E8h Port P4 Register P4 XXh
00E9h Port P5 Register P5 XXh
00EAh Port P4 Direction Register PD4 00h
00EBh Port P5 Direction Register PD5 00h
00ECh Port P6 Register P6 XXh
00EDh
00EEh Port P6 Direction Register PD6 00h
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h Port P2 Drive Capacity Control Register P2DRR 00h
00F5h UART1 Function Select Register U1SR 000000XXb
00F6h
00F7h
00F8h Port Mode Register PMR 00h
00F9h External Input Enable Register INTEN 00h
00FAh INT Input Filter Select Regi ster INTF 00h
00FBh Key Input Enable Register KIEN 00h
00FCh Pull-Up Control Register 0 PUR0 00h
00FDh Pull-Up Control Register 1 PUR1 XX000000b
00FEh
00FFh
R8C/2C Group, R8C/2D Group 4. S pecial Function Registers (SFRs)
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Table 4.5 SFR Information (5)(1)
NOTE:
1. The blank regions are reserved. Do not access locations in these regions
Address Register Symbol After reset
0100h Timer RA Control Register TRACR 00h
0101h Timer RA I/O Control Register TRAIOC 00h
0102h Timer RA Mode Register TRAMR 00h
0103h Timer RA Prescaler Register TRAPRE FFh
0104h Timer RA Register TRA FFh
0105h LIN Control Register 2 LINCR2 00h
0106h LIN Control Register LINCR 00h
0107h LIN Status Register LINST 00h
0108h Timer RB Control Register TRBCR 00h
0109h Timer RB One-Shot Control Register TRBOCR 00h
010Ah Timer RB I/O Control Register TRBIOC 00h
010Bh Timer RB Mode Register TRBMR 00h
010Ch Timer RB Prescaler Register TRBPRE FFh
010Dh Timer RB Secondary Register TRBSC FFh
010Eh Timer RB Primary Register TRBPR FFh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h Timer RE Second Data Register / Counter Data Register TRESEC 00h
0119h Timer RE Minute Data Register / Compare Data Register TREMIN 00h
011Ah Timer RE Hour Data Register TREHR 00h
011Bh Timer RE Day of Week Data Register TREWK 00h
011Ch Timer RE Control Register 1 TRECR1 00h
011Dh Timer RE Control Register 2 TRECR2 00h
011Eh Timer RE Clock Source Select Register TRECSR 00001000b
011Fh
0120h Timer RC Mode Register TRCMR 01001000b
0121h Timer RC Control Register 1 TRCCR1 00h
0122h Timer RC Interrupt Enable Register TRCIER 01110000b
0123h Timer RC Status Register TRCSR 01110000b
0124h Timer RC I/O Control Register 0 TRCIOR0 10001000b
0125h Timer RC I/O Control Register 1 TRCIOR1 10001000b
0126h Timer RC Counter TRC 00h
0127h 00h
0128h Timer RC General Register A TRCGRA FFh
0129h FFh
012Ah Timer RC General Register B TRCGRB FFh
012Bh FFh
012Ch Timer RC General Register C TRCGRC FFh
012Dh FFh
012Eh Timer RC General Register D TRCGRD FFh
012Fh FFh
0130h Timer RC Control Register 2 TRCCR2 00011111b
0131h Timer RC Digital Filter Function Select Register TRCDF 00h
0132h Timer RC Output Master Enable Register TRCOER 01111111b
0133h
0134h
0135h
0136h
0137h Timer RD Start Register TRDSTR 11111100b
0138h Timer RD Mode Register TRDMR 00001110b
0139h Timer RD PWM Mode Register TRDPMR 10001000b
013Ah Timer RD Function Control Register TRDFCR 10000000b
013Bh Timer RD Output Master Enable Register 1 TRDOER1 FFh
013Ch Timer RD Output Master Enable Register 2 TRDOER2 01111111b
013Dh Timer RD Output Control Register TRDOCR 00h
013Eh Timer RD Digital Filter Function Select Register 0 TRDDF0 00h
013Fh Timer RD Digital Filter Function Select Register 1 TRDDF1 00h
R8C/2C Group, R8C/2D Group 4. S pecial Function Registers (SFRs)
Rev.2.10 Dec 05, 2007 Page 25 of 57
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Table 4.6 SFR Information (6)(1)
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Address Register Symbol After reset
0140h Timer RD Control Register 0 TRDCR0 00h
0141h Timer RD I/O Control Register A0 TRDIORA0 10001000b
0142h Timer RD I/O Control Register C0 TRDIORC0 10001000b
0143h Timer RD Status Register 0 TRDSR0 11000000b
0144h Timer RD Interrupt Enable Register 0 TRDIER0 11100000b
0145h Timer RD PWM Mode Output Level Control Register 0 TRDPOCR0 11111000b
0146h Timer RD Counter 0 TRD0 00h
0147h 00h
0148h Timer RD General Register A0 TRDGRA0 FFh
0149h FFh
014Ah Timer RD General Register B0 TRDGRB0 FFh
014Bh FFh
014Ch Timer RD General Register C0 TRDGRC0 FFh
014Dh FFh
014Eh Timer RD General Register D0 TRDGRD0 FFh
014Fh FFh
0150h Timer RD Control Register 1 TRDCR1 00h
0151h Timer RD I/O Control Register A1 TRDIORA1 10001000b
0152h Timer RD I/O Control Register C1 TRDIORC1 10001000b
0153h Timer RD Status Register 1 TRDSR1 11000000b
0154h Timer RD Interrupt Enable Register 1 TRDIER1 11100000b
0155h Timer RD PWM Mode Output Level Control Register 1 TRDPOCR1 11111000b
0156h Timer RD Counter 1 TRD1 00h
0157h 00h
0158h Timer RD General Register A1 TRDGRA1 FFh
0159h FFh
015Ah Timer RD General Register B1 TRDGRB1 FFh
015Bh FFh
015Ch Timer RD General Register C1 TRDGRC1 FFh
015Dh FFh
015Eh Timer RD General Register D1 TRDGRD1 FFh
015Fh FFh
0160h UART2 Transmit/Receive Mode Register U2MR 00h
0161h UART2 Bit Rate Register U2BRG XXh
0162h UART2 Transmit Buffer Register U2TB XXh
0163h XXh
0164h UART2 Transmit/Receive Control Register 0 U2C0 00001000b
0165h UART2 Transmit/Receive Control Register 1 U2C1 00000010b
0166h UART2 Receive Buffer Register U2RB XXh
0167h XXh
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
R8C/2C Group, R8C/2D Group 4. S pecial Function Registers (SFRs)
Rev.2.10 Dec 05, 2007 Page 26 of 57
REJ03B0183-0210
Table 4.7 SFR Information (7)(1)
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Address Register Symbol After reset
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
01B3h Flash Memory Control Register 4 FMR4 01000000b
01B4h
01B5h Flash Memory Control Register 1 FMR1 1000000Xb
01B6h
01B7h Flash Memory Control Register 0 FMR0 00000001b
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
R8C/2C Group, R8C/2D Group 4. S pecial Function Registers (SFRs)
Rev.2.10 Dec 05, 2007 Page 27 of 57
REJ03B0183-0210
Table 4.8 SFR Information (8)(1)
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Address Register Symbol After reset
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
01C6h
01C7h
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
R8C/2C Group, R8C/2D Group 4. S pecial Function Registers (SFRs)
Rev.2.10 Dec 05, 2007 Page 28 of 57
REJ03B0183-0210
Table 4.9 SFR Information (9)(1)
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Address Register Symbol After reset
0200h
0201h
0202h
0203h
0204h
0205h
0206h
0207h
0208h
0209h
020Ah
020Bh
020Ch
020Dh
020Eh
020Fh
0210h
0211h
0212h
0213h
0214h
0215h
0216h
0217h
0218h
0219h
021Ah
021Bh
021Ch
021Dh
021Eh
021Fh
0220h
0221h
0222h
0223h
0224h
0225h
0226h
0227h
0228h
0229h
022Ah
022Bh
022Ch
022Dh
022Eh
022Fh
0230h
0231h
0232h
0233h
0234h
0235h
0236h
0237h
0238h
0239h
023Ah
023Bh
023Ch
023Dh
023Eh
023Fh
R8C/2C Group, R8C/2D Group 4. S pecial Function Registers (SFRs)
Rev.2.10 Dec 05, 2007 Page 29 of 57
REJ03B0183-0210
Table 4.10 SFR In forma tio n (10)(1)
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Address Register Symbol After reset
0240h
0241h
0242h
0243h
0244h
0245h
0246h
0247h
0248h
0249h
024Ah
024Bh
024Ch
024Dh
024Eh
024Fh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh
025Fh
0260h
0261h
0262h
0263h
0264h
0265h
0266h
0267h
0268h
0269h
026Ah
026Bh
026Ch
026Dh
026Eh
026Fh
0270h
0271h
0272h
0273h
0274h
0275h
0276h
0277h
0278h
0279h
027Ah
027Bh
027Ch
027Dh
027Eh
027Fh
R8C/2C Group, R8C/2D Group 4. S pecial Function Registers (SFRs)
Rev.2.10 Dec 05, 2007 Page 30 of 57
REJ03B0183-0210
Table 4.11 SFR Information (11)(1)
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. After input capture mode.
3. After output compare mode.
Address Register Symbol After reset
0280h
0281h
0282h
0283h
0284h
0285h
0286h
0287h
0288h
0289h
028Ah
028Bh
028Ch
028Dh
028Eh
028Fh
0290h Timer RF Register TRF 00h
0291h 00h
0292h
0293h
0294h
0295h
0296h
0297h
0298h
0299h
029Ah Timer RF Control Register 0 TRFCR0 00h
029Bh Timer RF Control Register 1 TRFCR1 00h
029Ch Capture / Compare 0 Register TRFM0 0000h(2)
029Dh FFFFh(3)
029Eh Compare 1 Register TRFM1 FFh
029Fh FFh
02A0h
02A1h
02A2h
02A3h
02A4h
02A5h
02A6h
02A7h
02A8h
02A9h
02AAh
02ABh
02ACh
02ADh
02AEh
02AFh
02B0h
02B1h
02B2h
02B3h
02B4h
02B5h
02B6h
02B7h
02B8h
02B9h
02BAh
02BBh
02BCh
02BDh
02BEh
02BFh
R8C/2C Group, R8C/2D Group 4. S pecial Function Registers (SFRs)
Rev.2.10 Dec 05, 2007 Page 31 of 57
REJ03B0183-0210
Table 4.12 SFR In forma tio n (12)(1)
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. The OFS register cannot be changed by a pr ogram. Use a flash programmer to write to it.
Address Register Symbol After reset
02C0h A/D Register 0 AD0 XXh
02C1h XXh
02C2h A/D Register 1 AD1 XXh
02C3h XXh
02C4h A/D Register 2 AD2 XXh
02C5h XXh
02C6h A/D Register 3 AD3 XXh
02C7h XXh
02C8h
02C9h
02CAh
02CBh
02CCh
02CDh
02CEh
02CFh
02D0h
02D1h
02D2h
02D3h
02D4h A/D Control Register 2 ADCON2 00001000b
02D5h
02D6h A/D Control Register 0 ADCON0 00000011b
02D7h A/D Control Register 1 ADCON1 00h
02D8h
02D9h
02DAh
02DBh
02DCh
02DDh
02DEh
02DFh
02E0h Port P7 Direction Register PD7 00h
02E1h
02E2h Port P7 Register P7 XXh
02E3h
02E4h Port P8 Direction Register PD8 00h
02E5h Port P9 Direction Register PD9 X0h
02E6h Port P8 Register P8 XXh
02E7h Port P9 Register P9 XXh
02E8h
02E9h
02EAh
02EBh
02ECh
02EDh
02EEh
02EFh
02F0h
02F1h
02F2h
02F3h
02F4h
02F5h
02F6h
02F7h
02F8h
02F9h
02FAh
02FBh
02FCh Pull-Up Control Register 2 PUR2 XXX00000b
02FDh
02FEh
02FFh Timer RF Output Control Register TRFOUT 00h
FFFFh Option Function Select Register OFS (Note 2)
R8C/2C Group, R8C/2D Group 5. Electrical Characteristics
Rev.2.10 Dec 05, 2007 Page 32 of 57
REJ03B0183-0210
5. Electrical Characteristics
Table 5.1 Absolute Maximum Rat ings
Symbol Parameter Condition Rated Value Unit
VCC/AVCC Supply voltage −0.3 to 6.5 V
VIInput voltage −0.3 to VCC + 0.3 V
VOOutput voltage −0.3 to VCC + 0.3 V
PdPower dissipation Topr = 25°C700mW
Topr Operating ambient temperature −20 to 85 (N version) /
−40 to 85 (D version) °C
Tstg Storage temperature −65 to 150 °C
The electrical ch aracteristics of N ver sion (Topr = –20°C to 85°C) and D version (Topr = –40°C to 85°C) are
listed below.
Please contact Renesas Technology sales offices for the electrical characteristics in the Y version (Topr =
–20°C to 105°C).
R8C/2C Group, R8C/2D Group 5. Electrical Characteristics
Rev.2.10 Dec 05, 2007 Page 33 of 57
REJ03B0183-0210
NOTES:
1. VCC = 2.2 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. The average output current indicates the average value of current measured during 100 ms.
Table 5.2 Recommended Operating Conditions
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
VCC/AVCC Supply voltage 2.2 −5.5 V
VSS/AVSS Supply voltage −0−V
VIH Input “H” voltage 0.8 VCC −VCC V
VIL Input “L” voltage 0 −0.2 VCC V
IOH(sum) Peak sum output
“H” current Sum of all pins IOH(peak) −−−240 mA
IOH(sum) Average sum
output “H” current Sum of all pins IOH(avg) −−−120 mA
IOH(peak) Peak output “H”
current Except P2_0 to P2_7 −−−10 mA
P2_0 to P2_7 −−−40 mA
IOH(avg) Average output
“H” current Except P2_0 to P2_7 −−−5mA
P2_0 to P2_7 −−−20 mA
IOL(sum) Peak sum output
“L” current Sum of all pins IOL(peak) −−240 mA
IOL(sum) Average sum
output “L” current Sum of all pins IOL(avg) −−120 mA
IOL(peak) Peak output “L”
current Except P2_0 to P2_7 −−10 mA
P2_0 to P2_7 −−40 mA
IOL(avg) Average output
“L” current Except P2_0 to P2_7 −−5mA
P2_0 to P2_7 −−20 mA
f(XIN) XIN clock input oscillation frequency 3.0 V ≤ VCC ≤ 5.5 V 0 −20 MHz
2.7 V ≤ VCC < 3.0 V 0 −10 MHz
2.2 V ≤ VCC < 2.7 V 0 −5MHz
f(XCIN) XCIN clock input oscillation frequency 2.2 V ≤ VCC ≤ 5.5 V 0 −70 kHz
−System clock OCD2 = 0
XlN clock selected 3.0 V ≤ VCC ≤ 5.5 V 0 −20 MHz
2.7 V ≤ VCC < 3.0 V 0 −10 MHz
2.2 V ≤ VCC < 2.7 V 0 −5MHz
OCD2 = 1
On-chip oscillator clock
selected
FRA01 = 0
Low-speed on-chip
oscillator clock selected
−125 −kHz
FRA01 = 1
High-speed on-chip
oscillator clock selected
3.0 V ≤ VCC ≤ 5.5 V
−−20 MHz
FRA01 = 1
High-speed on-chip
oscillator clock selected
2.7 V ≤ VCC ≤ 5.5 V
−−10 MHz
FRA01 = 1
High-speed on-chip
oscillator clock selected
2.2 V ≤ VCC ≤ 5.5 V
−−5MHz
R8C/2C Group, R8C/2D Group 5. Electrical Characteristics
Rev.2.10 Dec 05, 2007 Page 34 of 57
REJ03B0183-0210
Figure 5.1 Ports P0 to P9 Timing Measurement Circuit
NOTES:
1. VCC/AVCC = Vref = 2.2 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in
8-bit mode.
NOTES:
1. VCC/AVCC = Vref = 2.7 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. This applies when one D/A converter is used and the value of the DAi register (i = 0 or 1) for the unused D/A converter is 00h.
The resistor ladder of the A/D converter is not included. Also, even if the VCUT bit in the ADCON1 register is set to 0 (VREF
not connected), IVref flows into the D/A converters.
Table 5.3 A/D Converter Characteristics(1)
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
−Resolution Vref = AVCC −−10 Bit
−Absolute
accuracy 10-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V −−±3 LSB
8-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V −−±2 LSB
10-bit mode φAD = 10 MHz, Vref = AVCC = 3.3 V −−±5 LSB
8-bit mode φAD = 10 MHz, Vref = AVCC = 3.3 V −−±2 LSB
10-bit mode φAD = 5 MHz, Vref = AVCC = 2.2 V −−±5 LSB
8-bit mode φAD = 5 MHz, Vref = AVCC = 2.2 V −−±2 LSB
Rladder Resistor ladder Vref = AVCC 10 −40 kΩ
tconv Conversion time 10-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V 3.3 −−µs
8-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V 2.8 −−µs
Vref Reference voltage 2.2 −AVCC V
VIA Analog input voltage(2) 0−AVCC V
−A/D operating
clock frequency Without sample and hold Vref = AVCC = 2.7 to 5.5 V 0.25 −10 MHz
With sample and hold Vref = AVCC = 2.7 to 5.5 V 1 −10 MHz
Without sample and hold Vref = AVCC = 2.2 to 5.5 V 0.25 −5MHz
With sample and hold Vref = AVCC = 2.2 to 5.5 V 1 −5MHz
Table 5.4 D/A Converter Characteristics(1)
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
−Resolution −−8Bit
−Absolute accuracy −−1.0 %
tsu Setup time −−3µs
ROOutput resistor 4 10 20 kΩ
IVref Reference power input current (NOTE 2) −−1.5 mA
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
30pF
R8C/2C Group, R8C/2D Group 5. Electrical Characteristics
Rev.2.10 Dec 05, 2007 Page 35 of 57
REJ03B0183-0210
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance
still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as p ossible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the
number of erase operations to a certain number.
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
Table 5.5 Flash Memory (Program ROM) Electrical Characteristics
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
−Program/erase endurance(2) R8C/2C Group 100(3) −−times
R8C/2D Group 1,000(3) −−times
−Byte program time −50 400 µs
−Block erase time −0.4 9 s
td(SR-SUS) Time delay from suspend request until
suspend −−97+CPU clock
× 6 cycles µs
−Interval from erase start/restart until
following suspend request 650 −−µs
−Interval from program start/restart until
following suspend request 0−−ns
−T ime from suspend until program/erase
restart −−3+CPU clo c k
× 4 cycles µs
−Program, erase voltage 2.7 −5.5 V
−Read voltage 2.2 −5.5 V
−Program, erase temperature 0 −60 °C
−Data hold time(7) Ambient temperature = 55°C20 −−year
R8C/2C Group, R8C/2D Group 5. Electrical Characteristics
Rev.2.10 Dec 05, 2007 Page 36 of 57
REJ03B0183-0210
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance
still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. S tandard of block A and block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times
is the same as that in program ROM.
5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as p ossible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the
number of erase operations to a certain number.
6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
7. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
8. −40°C for D version.
9. The data hold time includes time that the power supply is off or the clock is not supplied.
Table 5.6 Flash Memory (Data flash Block A, Block B) Electrical Characteristics(4)
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
−Program/erase endurance(2) 10,000(3) −−times
−Byte program time
(program/erase endurance ≤ 1,000 times) −50 400 µs
−Byte program time
(program/erase endurance > 1,000 times) −65 −µs
−Block erase time
(program/erase endurance ≤ 1,000 times) −0.2 9 s
−Block erase time
(program/erase endurance > 1,000 times) −0.3 −s
td(SR-SUS) Time delay from suspend request until
suspend −−97+CPU clock
× 6 cycles µs
−Interval from erase start/restart until
following suspend request 650 −−µs
−Interval from program start/restart until
following suspend request 0−−ns
−Time from suspend until program/erase
restart −−3+CPU clock
× 4 cycles µs
−Program, erase voltage 2.7 −5.5 V
−Read voltage 2.2 −5.5 V
−Program, erase temperature −20(8) −85 °C
−Data hold time(9) Ambient temperature = 55 °C20 −−year
R8C/2C Group, R8C/2D Group 5. Electrical Characteristics
Rev.2.10 Dec 05, 2007 Page 37 of 57
REJ03B0183-0210
Figure 5.2 Time delay until Suspend
NOTES:
1. The measurement condition is VCC = 2.2 V to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).
2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2
register to 0.
NOTES:
1. The measurement condition is VCC = 2.2 V to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).
2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.
NOTES:
1. The measurement condition is VCC = 2.2 V to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).
2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.
3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
Table 5.7 Voltage Detection 0 Circui t Elect ri ca l Ch ara cteris ti cs
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
Vdet0 Voltage detection level 2.2 2.3 2.4 V
−Voltage detection circuit self power consumption VCA25 = 1, VCC = 5.0 V −0.9 −µA
td(E-A) Waiting time until voltage detection circuit operation
starts(2) −−300 µs
Vccmin MCU operating voltage minimum value 2.2 −−V
Table 5.8 Voltage Detection 1 Circui t Elect ri ca l Ch ara cteris ti cs
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
Vdet1 Voltage detection level 2.70 2.85 3.00 V
−Voltage monitor 1 interrupt request generation time(2) −40 −µs
−Voltage detection circuit self power consumption VCA26 = 1, VCC = 5.0 V −0.6 −µA
td(E-A) Waiting time until voltage detection circuit operation
starts(3) −−100 µs
Table 5.9 Voltage Detection 2 Circui t Elect ri ca l Ch ara cteris ti cs
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
Vdet2 Voltage detection level 3.3 3.6 3.9 V
−Voltage monitor 2 interrupt request generation time(2) −40 −µs
−Voltage detection circuit self power consumption VCA27 = 1, VCC = 5.0 V −0.6 −µA
td(E-A) Waiting time until voltage detection circuit operation
starts(3) −−100 µs
FMR46
Suspend request
(maskable in terrupt request)
Fixed time
td(SR-SUS)
Clock-dependent
time Access restart
R8C/2C Group, R8C/2D Group 5. Electrical Characteristics
Rev.2.10 Dec 05, 2007 Page 38 of 57
REJ03B0183-0210
NOTES:
1. The measurement condition is Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. This condition (external power VCC rise gradient) does not apply if VCC ≥ 1.0 V.
3. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the
VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1.
4. tw(por1) indicates the duration the externa l power VCC must be held below the effective voltage (Vpor1) to enable a power on
reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if −20°C ≤ Topr ≤ 85°C, maintain tw(por1) for
3,000 s or more if −40°C ≤ Topr < −20°C.
Figure 5.3 Power-on Reset Circuit Electrical Characteristics
Table 5.10 Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics(3)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
Vpor1 Power-on reset valid voltage(4) −−0.1 V
Vpor2 Power-on reset or voltage monitor 0 reset valid
voltage 0−Vdet0 V
trth External power VCC rise gradient(2) 20 −−mV/msec
NOTES:
1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage
range (2.2 V or above) during the sampling time.
2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit of Hardware Manual for details.
3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detectio n
Circuit of Hardware Manual for details.
Vdet0(3)
Vpor1
Internal
reset signal
(“L” valid)
tw(por1) Sampling time(1, 2)
Vdet0(3)
1
fOCO-S × 32 1
fOCO-S × 32
Vpor2
2.2V
External
Power VCC trth trth
R8C/2C Group, R8C/2D Group 5. Electrical Characteristics
Rev.2.10 Dec 05, 2007 Page 39 of 57
REJ03B0183-0210
NOTES:
1. VCC = 2.2 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. These standard values show when the FRA1 register value after reset is assumed.
3. These standard values show when the correction value in the FRA6 register is written to the FRA1 register.
NOTE:
1. VCC = 2.2 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = 25°C.
2. Waiting time until the internal power supply generation circuit stabilizes during power-on.
3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode.
Table 5.11 High-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
fOCO40M High-speed on-chip oscillator frequency
temperature • supply voltage dependence VCC = 2.7 V to 5.5 V
−20°C ≤ Topr ≤ 85°C(2) 39.2 40 40.8 MHz
VCC = 2.7 V to 5.5 V
−40°C ≤ Topr ≤ 85°C(2) 39.0 40 41.0 MHz
VCC = 2.2 V to 5.5 V
−20°C ≤ Topr ≤ 85°C(3) 35.2 40 44.8 MHz
VCC = 2.2 V to 5.5 V
−40°C ≤ Topr ≤ 85°C(3) 34.0 40 46.0 MHz
High-speed on-chip oscillator frequency when
correction value in FRA7 register is written to
FRA1 register
VCC = 5.0 V, Topr = 25°C−36.864 −MHz
VCC = 2.7 V to 5.5 V
−20°C ≤ Topr ≤ 85°C−3% −3% %
−Value in FRA1 register after reset 08h −F7h −
−Oscillation frequency adjustment unit of high-
speed on-chip oscillator Adjust FRA1 register
(value after reset) to −1−+0.3 −MHz
−Oscillation stability time VCC = 5.0 V, Topr = 25°C−10 100 µs
−Self power consumption at oscillation VCC = 5.0 V, Topr = 25°C−550 −µA
Table 5.12 Low-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
fOCO-S Low-speed on-chip oscillator frequency 30 125 250 kHz
−Oscillation stability time VCC = 5.0 V, Topr = 25°C−10 100 µs
−Self power consumption at oscillation VCC = 5.0 V, Topr = 25°C−15 −µA
Table 5.13 Power Supply Circuit Timing Characteristics
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
td(P-R) Time for internal power supply stabilization during
power-on(2) 1−2000 µs
td(R-S) STOP exit time(3) −−150 µs
R8C/2C Group, R8C/2D Group 5. Electrical Characteristics
Rev.2.10 Dec 05, 2007 Page 40 of 57
REJ03B0183-0210
NOTES:
1. VCC = 2.2 to 5.5 V, VSS = 0 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
Table 5.14 Timing Requirements of Clock Synchronous Serial I/O with Chip Select(1)
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
tSUCYC SSCK clock cycle time 4 −−
tCYC(2)
tHI SSCK clock “H” width 0.4 −0.6 tSUCYC
tLO SSCK clock “L” width 0.4 −0.6 tSUCYC
tRISE SSCK clock rising
time Master −− 1tCYC(2)
Slave −− 1µs
tFALL SSCK clock falling
time Master −− 1tCYC(2)
Slave −− 1µs
tSU SSO, SSI data input setup time 100 −− ns
tHSSO, SSI data input hold time 1 −−
tCYC(2)
tLEAD SCS setup time Slave 1tCYC + 50 −− ns
tLAG SCS hold time Slave 1tCYC + 50 −− ns
tOD SSO, SSI data output delay time −− 1tCYC(2)
tSA SSI slave access time 2.7 V ≤ VCC ≤ 5.5 V −−1.5tCYC + 100 ns
2.2 V ≤ VCC < 2.7 V −−1.5tCYC + 200 ns
tOR SSI slave out open time 2.7 V ≤ VCC ≤ 5.5 V −−1.5tCYC + 100 ns
2.2 V ≤ VCC < 2.7 V −−1.5tCYC + 200 ns
R8C/2C Group, R8C/2D Group 5. Electrical Characteristics
Rev.2.10 Dec 05, 2007 Page 41 of 57
REJ03B0183-0210
Figure 5.4 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Master)
VIH or VOH
VIH or VOH
tHI
tLO
tHI
tFALL tRISE
tLO tSUCYC
tOD
tH
tSU
SCS (output)
SSCK (output)
(CPOS = 1)
SSCK (output)
(CPOS = 0)
SSO (output)
SSI (input)
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
VIH or VOH
tHI
tLO
tHI
tFALL tRISE
tLO tSUCYC
tOD
tH
tSU
SCS (output)
SSCK (output)
(CPOS = 1)
SSCK (output)
(CPOS = 0)
SSO (output)
SSI (input)
4-Wire Bus Communication Mode, Master, CPHS = 0
CPHS, CPOS: Bits in SSMR register
R8C/2C Group, R8C/2D Group 5. Electrical Characteristics
Rev.2.10 Dec 05, 2007 Page 42 of 57
REJ03B0183-0210
Figure 5.5 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Slave)
VIH or VOH
VIH or VOH
SCS (input)
SSCK (input)
(CPOS = 1)
SSCK (input)
(CPOS = 0)
SSO (input)
SSI (output)
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
VIH or VOH
tHI
tLO
tHI
tFALL tRISE
tLO tSUCYC
tH
tSU
SCS (input)
SSCK (input)
(CPOS = 1)
SSCK (input)
(CPOS = 0)
SSO (input)
SSI (output)
4-Wire Bus Communication Mode, Slave, CPHS = 0
tOD
tLEAD
tSA
tLAG
tOR
tHI
tLO
tHI
tFALL tRISE
tLO tSUCYC
tH
tSU
tOD
tLEAD
tSA
tLAG
tOR
CPHS, CPOS: Bits in SSMR register
R8C/2C Group, R8C/2D Group 5. Electrical Characteristics
Rev.2.10 Dec 05, 2007 Page 43 of 57
REJ03B0183-0210
Figure 5.6 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Clock Synchronous
Communication Mode)
VIH or VOH
tHI
tLO tSUCYC
tOD
tH
tSU
SSCK
SSO (output)
SSI (input)
VIH or VOH
R8C/2C Group, R8C/2D Group 5. Electrical Characteristics
Rev.2.10 Dec 05, 2007 Page 44 of 57
REJ03B0183-0210
NOTES:
1. VCC = 2.2 to 5.5 V, VSS = 0 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
Figure 5.7 I/O Timing of I2C bus Interface
Table 5.15 Timing Require m ents of I2C bus Interface (1)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
tSCL SCL input cycle time 12tCYC + 600(2) −−ns
tSCLH SCL input “H” width 3tCYC + 300(2) −−ns
tSCLL SCL input “L” width 5tCYC + 500(2) −−ns
tsf SCL, SDA input fall time −−300 ns
tSP SCL, SDA input spike pulse rejection time −−
1tCYC(2) ns
tBUF SDA input bus-free time 5tCYC(2) −−ns
tSTAH Start condition input hold time 3tCYC(2) −−ns
tSTAS Retransmit start condition input setup time 3tCYC(2) −−ns
tSTOP Stop condition input setup time 3tCYC(2) −−ns
tSDAS Data input setup time 1tCYC + 20(2) −−ns
tSDAH Data input hold time 0 −−ns
SDA
tSTAH
tSCLL
tBUF
VIH
VIL
tSCLH
SCL
tsr
tsf
tSDAH
tSCL
tSTAS tSP tSTOP
tSDAS
P(2) S(1) Sr(3) P(2)
NOTES:
1. Start condition
2. Stop condition
3. Retransmit start condition
R8C/2C Group, R8C/2D Group 5. Electrical Characteristics
Rev.2.10 Dec 05, 2007 Page 45 of 57
REJ03B0183-0210
NOTE:
1. VCC = 4.2 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), f(XIN) = 20 MHz, unless otherwise specified.
Table 5.16 Electrical Characteristics (1) [VCC = 5 V]
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
VOH Output “H” volt age Except P2_0 to P2_7,
XOUT IOH = −5 mA VCC − 2.0 −VCC V
IOH = −200 µAVCC − 0.5 −VCC V
P2_0 to P2_7 Drive capacity HIGH IOH = −20 mA VCC − 2.0 −VCC V
Drive capacity LOW IOH = −5 mA VCC − 2.0 −VCC V
XOUT Drive capacity HIGH IOH = −1 mA VCC − 2.0 −VCC V
Drive capacity LOW IOH = −500 µAVCC − 2.0 −VCC V
VOL Output “L” voltage Except P2_0 to P2_7,
XOUT IOL = 5 mA −−2.0 V
IOL = 200 µA−−0.45 V
P2_0 to P2_7 Drive capacity HIGH IOL = 20 mA −−2.0 V
Drive capacity LOW IOL = 5 mA −−2.0 V
XOUT Drive capacity HIGH IOL = 1 mA −−2.0 V
Drive capacity LOW IOL = 500 µA−−2.0 V
VT+-VT- Hysteresis INT0, INT1, INT2,
INT3, KI0, KI1, KI2,
KI3, TRAIO, TRFI,
RXD0, RXD1, CLK0,
CLK1, CLK2, SSI,
SCL, SDA, SSO
0.1 0.5 −V
RESET 0.1 1.0 −V
IIH Input “H” current VI = 5 V −−5.0 µA
IIL Input “L” current VI = 0 V −−−5.0 µA
RPULLUP Pull-up resistance VI = 0 V 30 50 167 kΩ
RfXIN Feedback
resistance XIN −1.0 −MΩ
RfXCIN Feedback
resistance XCIN −18 −MΩ
VRAM RAM hold voltage During stop mode 1.8 −−V
R8C/2C Group, R8C/2D Group 5. Electrical Characteristics
Rev.2.10 Dec 05, 2007 Page 46 of 57
REJ03B0183-0210
Table 5.17 Electrical Characteristics (2) [Vcc = 5 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
ICC Power supply
current
(V
CC
= 3.3 to 5.5 V)
Single-chip mode,
output pins are
open, other pins
are VSS
High-speed
clock mode XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−12 20 mA
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−10 16 mA
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−7−mA
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−5.5 −mA
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−4.5 −mA
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−3−mA
High-speed
on-chip
oscillator mode
XIN clock off
High-speed on-chip oscillator on fO CO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
−612mA
XIN clock off
High-speed on-chip oscillator on fO CO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−2.5 −mA
Low-speed
on-chip
oscillator mode
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
−150 400 µA
Low-speed
clock mode XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
FMR47 = 1
−150 400 µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
Program operation on RAM
Flash memory off, FMSTP = 1
−35 −µA
Wait mode XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−30 90 µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Periphe r al clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−18 55 µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−3.5 −µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−2.3 −µA
Stop mode XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Periphe r al clock off
VCA27 = VCA26 = VCA25 = 0
−0.7 3.0 µA
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Periphe r al clock off
VCA27 = VCA26 = VCA25 = 0
−1.7 −µA
R8C/2C Group, R8C/2D Group 5. Electrical Characteristics
Rev.2.10 Dec 05, 2007 Page 47 of 57
REJ03B0183-0210
Timing Requirements
(Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25°C) [VCC = 5 V]
Figure 5.8 XIN Input and XCIN Input Timing Diagram when VCC = 5 V
Figure 5.9 TRAIO Input and INT1 Input Timing Diagram when VCC = 5 V
NOTES:
1. When using timer RF input capture mode, adjust the cycle time to (1/timer RF count source frequency × 3) or above.
2. When using timer RF input capture mode, adjust the pulse width to (1/timer RF count source frequency × 1.5) or above.
Figure 5.10 TRFI Input Timing Diagram when VCC = 5 V
Table 5.18 XI N Input, XCIN Input
Symbol Parameter Standard Unit
Min. Max.
tc(XIN) XIN input cycle time 50 −ns
tWH(XIN) XIN input “H” width 25 −ns
tWL(XIN) XIN input “L” width 25 −ns
tc(XCIN) XCIN input cycle time 14 −µs
tWH(XCIN) XCIN input “H” width 7 −µs
tWL(XCIN) XCIN input “L” width 7 −µs
Table 5.19 TRAIO Input, INT1 Input
Symbol Parameter Standard Unit
Min. Max.
tc(TRAIO) TRAIO input cycle time 100 −ns
tWH(TRAIO) TRAIO input “H” width 40 −ns
tWL(TRAIO) TRAIO input “L” width 40 −ns
Table 5.20 TRFI Input
Symbol Parameter Standard Unit
Min. Max.
tc(TRFI) TRFI input cycle time 400(1) −ns
tWH(TRFI) TRFI input “H” width 200(2) −ns
tWL(TRFI) TRFI input “L” width 200(2) −ns
XIN input
tWH(XIN)
tC(XIN)
tWL(XIN)
VCC = 5 V
TRAIO input
VCC = 5 V
tC(TRAIO)
tWL(TRAIO)
tWH(TRAIO)
tWH(TRFI)
tc(TRFI)
tWL(TRFI)
TRFI input
VCC = 5 V
R8C/2C Group, R8C/2D Group 5. Electrical Characteristics
Rev.2.10 Dec 05, 2007 Page 48 of 57
REJ03B0183-0210
i = 0 to 2
Figure 5.11 Serial Interface Timing Diagram when VCC = 5 V
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
Figure 5.12 External Interrupt INTi Input Timing Diagram when VCC = 5 V
Table 5.21 Se ria l Int e rf ac e
Symbol Parameter Standard Unit
Min. Max.
tc(CK) CLKi input cycle time 200 −ns
tW(CKH) CLKi input “H” width 100 −ns
tW(CKL) CLKi input “L” width 100 −ns
td(C-Q) TXDi output delay time −50 ns
th(C-Q) TXDi hold time 0 −ns
tsu(D-C) RXDi input setup time 50 −ns
th(C-D) RXDi input hold time 90 −ns
Table 5.22 External Interrupt INTi (i = 0, 2, 3) Input
Symbol Parameter Standard Unit
Min. Max.
tW(INH) INT0 input “H” width 250(1) −ns
tW(INL) INT0 input “L” width 250(2) −ns
tW(CKH)
tC(CK)
tW(CKL) th(C-Q)
th(C-D)
tsu(D-C)td(C-Q)
CLKi
TXDi
RXDi
i = 0 to 2
VCC = 5 V
INTi input
tW(INL)
tW(INH)
i = 0, 2, 3
VCC = 5 V
R8C/2C Group, R8C/2D Group 5. Electrical Characteristics
Rev.2.10 Dec 05, 2007 Page 49 of 57
REJ03B0183-0210
NOTE:
1. VCC =2.7 to 3.3 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), f(XIN) = 10 MHz, unless otherwise specified.
Table 5.23 Electrical Characteristics (3) [VCC = 3 V]
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
VOH Output “H” voltage Except P2_0 to P2_7,
XOUT IOH = −1 mA VCC − 0.5 −VCC V
P2_0 to P2_7 Drive capacity
HIGH IOH = −5 mA VCC − 0.5 −VCC V
Drive capacity
LOW IOH = −1 mA VCC − 0.5 −VCC V
XOUT Drive capacity
HIGH IOH = −0.1 mA VCC − 0.5 −VCC V
Drive capacity
LOW IOH = −50 µAVCC − 0.5 −VCC V
VOL Output “L” voltage Except P2_0 to P2_7,
XOUT IOL = 1 mA −−0.5 V
P2_0 to P2_7 Drive capacity
HIGH IOL = 5 mA −−0.5 V
Drive capacity
LOW IOL = 1 mA −−0.5 V
XOUT Drive capacity
HIGH IOL = 0.1 mA −−0.5 V
Drive capacity
LOW IOL = 50 µA−−0.5 V
VT+-VT- Hysteresis INT0, INT1, INT2,
INT3, KI0, KI1, KI2,
KI3, TRAIO, TRFI,
RXD0, RXD1, CLK0,
CLK1, CLK2, SSI,
SCL, SDA, SSO
0.1 0.3 −V
RESET 0.1 0.4 −V
IIH Input “H” current VI = 3 V −−4.0 µA
IIL Input “L” current VI = 0 V −−−4.0 µA
RPULLUP Pull-up resistance VI = 0 V 66 160 500 kΩ
RfXIN Feedback resistance XIN −3.0 −MΩ
RfXCIN Feedback resistance XCIN −18 −MΩ
VRAM RAM hold voltage During stop mode 1.8 −−V
R8C/2C Group, R8C/2D Group 5. Electrical Characteristics
Rev.2.10 Dec 05, 2007 Page 50 of 57
REJ03B0183-0210
Table 5.24 Electrical Characteristics (4) [Vcc = 3 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
ICC Power supply current
(VCC = 2.7 to 3.3 V)
Single-chip mode,
output pins are open,
other pins are VSS
High-speed
clock mode XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−5.5 −mA
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−2−mA
High-speed
on-chip
oscillator
mode
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
−5.5 11 mA
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−2.2 −mA
Low-speed
on-chip
oscillator
mode
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
−145 400 µA
Low-speed
clock mode XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
FMR47 = 1
−145 400 µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
Program operation on RAM
Flash memory off, FMSTP = 1
−30 −µA
Wait mode XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−28 85 µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−17 50 µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−3.3 −µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−2.1 −µA
Stop mode XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
−0.65 3.0 µA
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
−1.65 −µA
R8C/2C Group, R8C/2D Group 5. Electrical Characteristics
Rev.2.10 Dec 05, 2007 Page 51 of 57
REJ03B0183-0210
Timing requirements
(Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25°C) [VCC = 3 V]
Figure 5.13 XIN Input and XCIN Input Timing Diagram when VCC = 3 V
Figure 5.14 TRAIO Input and INT1 Input Timing Diagram when VCC = 3 V
NOTES:
1. When using timer RF input capture mode, adjust the cycle time to (1/timer RF count source frequency × 3) or above.
2. When using timer RF input capture mode, adjust the pulse width to (1/timer RF count source frequency × 1.5) or above.
Figure 5.15 TRFI Input Timing Diagram when VCC = 3 V
Table 5.25 XI N Input, XCIN Input
Symbol Parameter Standard Unit
Min. Max.
tc(XIN) XIN input cycle time 100 −ns
tWH(XIN) XIN input “H” width 40 −ns
tWL(XIN) XIN input “L” width 40 −ns
tc(XCIN) XCIN input cycle time 14 −µs
tWH(XCIN) XCIN input “H” width 7 −µs
tWL(XCIN) XCIN input “L” width 7 −µs
Table 5.26 TRAIO Input, INT1 Input
Symbol Parameter Standard Unit
Min. Max.
tc(TRAIO) TRAIO input cycle time 300 −ns
tWH(TRAIO) TRAIO input “H” width 120 −ns
tWL(TRAIO) TRAIO input “L” width 120 −ns
Table 5.27 TRFI Input
Symbol Parameter Standard Unit
Min. Max.
tc(TRFI) TRFI input cycle time 1200(1) −ns
tWH(TRFI) TRFI input “H” width 600(2) −ns
tWL(TRFI) TRFI input “L” width 600(2) −ns
XIN input
tWH(XIN)
tC(XIN)
tWL(XIN)
VCC = 3 V
TRAIO in pu t
VCC = 3 V
tC(TRAIO)
tWL(TRAIO)
tWH(TRAIO)
TRFI input
tWH(TRFI)
tc(TRFI)
tWL(TRFI)
VCC = 3 V
R8C/2C Group, R8C/2D Group 5. Electrical Characteristics
Rev.2.10 Dec 05, 2007 Page 52 of 57
REJ03B0183-0210
i = 0 to 2
Figure 5.16 Serial Interface Timing Diagram when VCC = 3 V
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
Figure 5.17 External Interrupt INTi Input Timing Diagram when VCC = 3 V
Table 5.28 Se ria l Int e rf ac e
Symbol Parameter Standard Unit
Min. Max.
tc(CK) CLKi input cycle time 300 −ns
tW(CKH) CLKi input “H” width 150 −ns
tW(CKL) CLKi Input “L” width 150 −ns
td(C-Q) TXDi output delay time −80 ns
th(C-Q) TXDi hold time 0 −ns
tsu(D-C) RXDi input setup time 70 −ns
th(C-D) RXDi input hold time 90 −ns
Table 5.29 External Interrupt INTi (i = 0, 2, 3) Input
Symbol Parameter Standard Unit
Min. Max.
tW(INH) INT0 input “H” width 380(1) −ns
tW(INL) INT0 input “L” width 380(2) −ns
tW(CKH)
tC(CK)
tW(CKL) th(C-Q)
th(C-D)
tsu(D-C)td(C-Q)
CLKi
TXDi
RXDi
VCC = 3 V
i = 0 to 2
INTi input
tW(INL)
tW(INH)
VCC = 3 V
i = 0, 2, 3
R8C/2C Group, R8C/2D Group 5. Electrical Characteristics
Rev.2.10 Dec 05, 2007 Page 53 of 57
REJ03B0183-0210
NOTE:
1. VCC = 2.2 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), f(XIN) = 5 MHz, unless otherwise specified.
Table 5.30 Electrical Characteristics (5) [VCC = 2.2 V]
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
VOH Output “H” voltage Except P2_0 to P2_7,
XOUT IOH = −1 mA VCC − 0.5 −VCC V
P2_0 to P2_7 Drive capacity
HIGH IOH = −2 mA VCC − 0.5 −VCC V
Drive capacity
LOW IOH = −1 mA VCC − 0.5 −VCC V
XOUT Drive capacity
HIGH IOH = −0.1 mA VCC − 0.5 −VCC V
Drive capacity
LOW IOH = −50 µAVCC − 0.5 −VCC V
VOL Output “L” voltage Except P2_0 to P2_7,
XOUT IOL = 1 mA −−0.5 V
P2_0 to P2_7 Drive capacity
HIGH IOL = 2 mA −−0.5 V
Drive capacity
LOW IOL = 1 mA −−0.5 V
XOUT Drive capacity
HIGH IOL = 0.1 mA −−0.5 V
Drive capacity
LOW IOL = 50 µA−−0.5 V
VT+-VT- Hysteresis INT0, INT1, INT2,
INT3, KI0, KI1, KI2,
KI3, TRAIO, TRFI,
RXD0, RXD1, CLK0,
CLK1, CLK2, SSI,
SCL, SDA, SSO
0.05 0.3 −V
RESET 0.05 0.15 −V
IIH Input “H” current VI = 2.2 V −−4.0 µA
IIL Input “L” current VI = 0 V −−−4.0 µA
RPULLUP Pull-up resistance VI = 0 V 100 200 600 kΩ
RfXIN Feedback resistance XIN −5−MΩ
RfXCIN Feedback resistance XCIN −35 −MΩ
VRAM RAM hold voltage During stop mode 1.8 −−V
R8C/2C Group, R8C/2D Group 5. Electrical Characteristics
Rev.2.10 Dec 05, 2007 Page 54 of 57
REJ03B0183-0210
Table 5.31 Electrical Characteristics (6) [Vcc = 2.2 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
ICC Power supply current
(VCC = 2.2 to 2.7 V)
Single-chip mode,
output pins are open,
other pins are VSS
High-speed
clock mode XIN = 5 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−2.5 −mA
XIN = 5 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−1−mA
High-speed
on-chip
oscillator
mode
XIN clock off
High-speed on-chip oscillator on fOCO = 5 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
−4−mA
XIN clock off
High-speed on-chip oscillator on fOCO = 5 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−1.7 −mA
Low-speed on-
chip oscillator
mode
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
−110 300 µA
Low-speed
clock mode XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
FMR47 = 1
−125 350 µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
Program operation on RAM
Flash memory off, FMSTP = 1
−27 −µA
Wait mode XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−20 60 µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−12 40 µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−2.8 −µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−1.9 −µA
Stop mode XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
−0.6 3.0 µA
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
−1.60 −µA
R8C/2C Group, R8C/2D Group 5. Electrical Characteristics
Rev.2.10 Dec 05, 2007 Page 55 of 57
REJ03B0183-0210
Timing requirements
(Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V at Topr = 25°C) [VCC = 2.2 V]
Figure 5.18 XIN Input and XCIN Input Timing Diagram when VCC = 2.2 V
Figure 5.19 TRAIO Input and INT1 Input Timing Diagram when VCC = 2.2 V
NOTES:
1. When using timer RF input capture mode, adjust the cycle time to (1/timer RF count source frequency × 3) or above.
2. When using timer RF input capture mode, adjust the pulse width to (1/timer RF count source frequency × 1.5) or above.
Figure 5.20 TRFI Input Timing Diagram when VCC = 2.2 V
Table 5.32 XI N Input, XCIN Input
Symbol Parameter Standard Unit
Min. Max.
tc(XIN) XIN input cycle time 200 −ns
tWH(XIN) XIN input “H” width 90 −ns
tWL(XIN) XIN input “L” width 90 −ns
tc(XCIN) XCIN input cycle time 14 −µs
tWH(XCIN) XCIN input “H” width 7 −µs
tWL(XCIN) XCIN input “L” width 7 −µs
Table 5.33 TRAIO Input, INT1 Input
Symbol Parameter Standard Unit
Min. Max.
tc(TRAIO) TRAIO input cycle time 500 −ns
tWH(TRAIO) TRAIO input “H” width 200 −ns
tWL(TRAIO) TRAIO input “L” width 200 −ns
Table 5.34 TRFI Input
Symbol Parameter Standard Unit
Min. Max.
tc(TRFI) TRFI input cycle time 2000(1) −ns
tWH(TRFI) TRFI input “H” width 1000(2) −ns
tWL(TRFI) TRFI input “L” width 1000(2) −ns
XIN input
tWH(XIN)
tC(XIN)
tWL(XIN)
VCC = 2.2 V
TRAIO input
tC(TRAIO)
tWL(TRAIO)
tWH(TRAIO)
VCC = 2.2 V
TRFI input
tWH(TRFI)
tc(TRFI)
tWL(TRFI)
VCC = 2.2 V
R8C/2C Group, R8C/2D Group 5. Electrical Characteristics
Rev.2.10 Dec 05, 2007 Page 56 of 57
REJ03B0183-0210
i = 0 to 2
Figure 5.21 Serial Interface Timing Diagram when VCC = 2.2 V
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
Figure 5.22 External Interrupt INTi Input Timing Diagram when VCC = 2.2 V
Table 5.35 Se ria l Int e rf ac e
Symbol Parameter Standard Unit
Min. Max.
tc(CK) CLKi input cycle time 800 −ns
tW(CKH) CLKi input “H” width 400 −ns
tW(CKL) CLKi input “L” width 400 −ns
td(C-Q) TXDi output delay time −200 ns
th(C-Q) TXDi hold time 0 −ns
tsu(D-C) RXDi input setup time 150 −ns
th(C-D) RXDi input hold time 90 −ns
Table 5.36 External Interrupt INTi (i = 0, 2, 3) Input
Symbol Parameter Standard Unit
Min. Max.
tW(INH) INT0 input “H” width 1000(1) −ns
tW(INL) INT0 input “L” width 1000(2) −ns
tW(CKH)
tC(CK)
tW(CKL) th(C-Q)
th(C-D)
tsu(D-C)td(C-Q)
CLKi
TXDi
RXDi
VCC = 2.2 V
i = 0 to 2
INTi input
tW(INL)
tW(INH)
VCC = 2.2 V
i = 0, 2, 3
Rev.2.10 Dec 05, 2007 Page 57 of 57
REJ03B0183-0210
R8C/2C Group, R8C/2D Group Package Dimensions
Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of
the Renesas Technology website.
Detail F
c
A
L
1
L
A
1
A
2
Index mark
y
*2
*1
*3
F
80
61
60 41
40
21
20
1
x
Z
E
Z
D
E
H
E
D
H
D
eb
p
2.
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
NOTE)
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
Previous CodeJEITA Package Code RENESAS Code
PLQP0080KB-A 80P6Q-A
MASS[Typ.]
0.5gP-LQFP80-12x12-0.50
1.0
0.125
0.18
1.25
1.25
0.08
0.200.1450.09
0.250.200.15
MaxNomMin
Dimension in Millimeters
Symbol
Reference
12.112.011.9
D
12.112.011.9
E
1.4
A
2
14.214.013.8
14.214.013.8
1.7
A
0.20.1
0
0.70.50.3
L
x
10°0°
c
0.5
e
0.08
y
H
D
H
E
A
1
b
p
b
1
c
1
Z
D
Z
E
L
1
Terminal cross section
c
bp
c
1
b
1
A - 1
REVISION HISTORY R8C/2C Group, R8C/2D Group Datasheet
Rev. Date Description
Page Summary
0.01 Apr 03, 2006 −First Edition issued
0.10 Jun 26, 2006 All pages Pin name revised
CMP0_0 → TRFO00, CMP0_1 → TRFO01, CMP0_2 → TRFO02,
CMP1_0 → TRFO10, CMP1_1 → TRFO11, CMP1_2 → TRFO12,
TRFIN → TRFI
2, 4 Table 1.1 Specifi cations for R8C/2C Group (1) and Table 1.3
Specifications for R8C/2D Group (1);
I/O Ports: • Input-only: 3 pins → 2 pins revised
Interrupts: • Internal: 17 sources → 23 sources revised
3, 5 Table 1.2 Specifi cations for R8C/2C Group (2) and Table 1.4
Specifications for R8C/2D Group (2);
ROM Correction Function deleted
8 Figure 1.3 Block Diagram revised
9 Figure 1.4 Pin Assignment (Top View) revised
10, 11 Table 1.7 Pin Name Information by Pin Number (1) and Table 1.8 Pin
Name Information by Pin Number (2) revised
12, 13 Table 1.9 Pin Functions (1) and Table 1.10 Pin Functions (2) revised
19 Table 4.1 SFR Information (1 );
• 0008h: Module Standby Control Register, MSTCR, 00h added
• 001Ch: “00h” → “00h, 10000000b” revised
• NOTE6 added
20 Table 4.2 SFR Information (2 );
• 005Fh: Capture Interrupt Control Register, CAPIC, XXXXX000b added
22 Table 4.4 SFR Information (4 );
• 00DCh: “00DDh” → “00DCh” revised
• 00F5h: “XXXX00XXb” → “00h” revised
23 Table 4.5 SFR Information (5 );
• 0105h: LIN Special Function Register, LINCR2, 00h added
31 Package Dimensions;
“Diagrams showing th e latest package dimensions ... in the
“Packages” section of the Renesas Technology website.” added
0.20 Sep 15, 2006 31 to 54 5. Electrical Characteristics added
0.30 Dec 22 , 2006 6 Table 1.5 and Figure 1.1 revised
7 Tab le 1.6 and Figure 1.2 revised
17 Fi gure 3.1 revised
18 Fi gure 3.2 revised
19 Table 4.1;
• 000Ah: “00XXX000b” → “00h” revised
• 0008h:
“Module Standby Control Register”
→
“Module Operation Enable Register” revised
• 000Fh: “00011111b” → “00X11111b” revised
37 Table 5.11 revised
R8C/2C Group, R8C/2D Group Datasheet
REVISION HISTORY
A - 2
REVISION HISTORY R8C/2C Group, R8C/2D Group Datasheet
1.00 Feb 09, 2007 All pages “Preliminary” deleted
3 Table 1.2 revised
5 Table 1.4 revised
6 Tab le 1.5 and Figure 1.1 revised
7 Tab le 1.6 and Figure 1.2 revised
17 Fi gure 3.1 revised
18 Fi gure 3.2 revised
19 Table 4.1;
• 0008h:
“Module Standby Control Register”
→
“Module Operation Enable Register” revised
• 000Ah: “00XXX000b” → “00h” revised
• 000Fh: “00011111b” → “00X11111b” revised
• 002Bh: “High-Speed On-Chip Oscillator Control Register 6” added
23 Table 4.5;
0105h: “LIN Control Register 2” register name revised
31 Table 5.2 revised
32 Table 5.3 and Table 5.4; NOTE1 revised
37 Table 5.11 revised
44 Table 5.17 revi sed
46 Table 5.21 and Figur e 5.11; “i = 0 to 2” revised
48 Table 5.24 revi sed
50 Table 5.28 revised, Figure 5.16; “i = 0 to 2” revised
52 Table 5.31 revi sed
53 Table 5.34 revi sed
54 Table 5.35 and Figure 5.21; “i = 0 to 2” revised
2.00 Oct 17, 2007 all pages Y version added
6, 7 Table 1.5, Table 1.6 (D) mark is deleted
31 Table 5.1 Rated Value : “T BD” → “700”
2.10 Dec 05 , 20 07 2, 4 Table 1.1, Table 1.3 Clock: “Real-time clock (timer RE)” added
6, 7 Table 1.5 and Figure 1.1 revised
8 Table 1.6 and Figure 1.2 revised
18, 19 Figure 3.1 and Figure 3.2 revised
20 Table 4.1 002Ch: High-Speed On-Chip Oscillator Control Register 7
added
23 Table 4.4 00F5h: After reset “00h” → “000000XXb” revised
33 Table 5.2 NOTE2 revised
39 Table 5.11 revised
Rev. Date Description
Page Summary
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