High Performance, SPI Digital Output, Angular Rate Sensor ADXRS810 Data Sheet FEATURES GENERAL DESCRIPTION Excellent null offset stability over temperature High vibration rejection over a wide frequency range 2000 g powered shock survivability SPI digital output with 16-bit data-word Low noise Continuous self-test Fail-safe functions Temperature sensor 3.3 V and 5 V operation -40C to +105C operation Small, low profile, industry standard SOIC package provides yaw rate (Z-axis) response Qualified for automotive applications The ADXRS810 is an angular rate sensor (gyroscope) intended for automotive navigation applications. An advanced, differential, quad-sensor design rejects the influence of linear acceleration, enabling the ADXRS810 to operate in exceedingly harsh environments where shock and vibration are present. The ADXRS810 uses an internal, continuous self-test architecture. The integrity of the electromechanical system is checked by applying a high frequency electrostatic force to the sense structure to generate a rate signal that can be differentiated from the baseband rate data and internally analyzed. The ADXRS810 is capable of sensing an angular rate of up to 300/sec. Angular rate data is presented as a 16-bit word, as part of a 32-bit SPI message. APPLICATIONS The ADXRS810 is available in a cavity plastic 16-lead SOIC and is capable of operating across both a wide voltage range (3.3 V to 5 V) and temperature range (-40C to 105C). Car navigation FUNCTIONAL BLOCK DIAGRAM VX HIGH VOLTAGE GENERATION PDD ADXRS810 LDO REGULATOR HV DRIVE CLOCK PHASEDIVIDER LOCKED LOOP AMPLITUDE DETECT Z-AXIS ANGULAR RATE SENSOR Q DAQ P DAQ 12-BIT ADC ALU DECIMATION FILTER DEMOD TEMPERATURE CALIBRATION FAULT DETECTION Q FILTER REGISTERS/MEMORY BAND-PASS FILTER DVDD AVDD SPI INTERFACE MOSI MISO SCLK CS DVSS ST CONTROL PSS EEPROM AVSS 11034-001 CP5 Figure 1. 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ADXRS810 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 SPI Communication Protocol--Bit Definitions ......................... 15 Applications ....................................................................................... 1 Command/Response Bit Descriptions .................................... 15 General Description ......................................................................... 1 ADXRS810 Fault Register Bit Definitions .............................. 17 Functional Block Diagram .............................................................. 1 CHK Bit Assertion: Recommended Start-Up Routine ......... 19 Revision History ............................................................................... 2 SPI Rate Data Format..................................................................... 20 Specifications..................................................................................... 3 ADXRS810 Memory Map ............................................................. 21 Absolute Maximum Ratings ............................................................ 5 Memory Register Definitions ....................................................... 22 Thermal Resistance ...................................................................... 5 0x00 RATE1, 0x01 RATE0 ........................................................ 22 Rate Sensitive Axis ....................................................................... 5 0x02 TEM1, 0x03 TEM0 ........................................................... 22 ESD Caution .................................................................................. 5 0x04 LOCST1, 0x05 LOCST0 ................................................... 22 Pin Configurations and Function Descriptions ........................... 6 0x06 HICST1, 0x07 HICST0 .................................................... 22 Typical Performance Characteristics ............................................. 7 0x08 QUAD1, 0x09 QUAD0 ..................................................... 22 Theory of Operation ........................................................................ 9 0x0A FAULT1, 0x0B FAULT0 .................................................. 23 Continuous Self-Test .................................................................... 9 0x0C PID1, 0x0D PID0 ............................................................. 23 Applications Information .............................................................. 10 0x0E SN3, 0x0F SN2, 0x10 SN1, 0x11 SN0 ............................. 23 Calibrated Performance ............................................................. 10 Suggested PCB Layout ................................................................... 24 Mechanical Considerations for Mounting .............................. 10 Solder Profile............................................................................... 25 Application Circuit ..................................................................... 10 Package Marking Codes ............................................................ 26 ADXRS810 Signal Chain Timing ............................................. 11 Outline Dimensions ....................................................................... 27 SPI Communications Characteristics .......................................... 12 Ordering Guide .......................................................................... 27 SPI Communication Protocol--Applications ............................. 13 Automotive Products ................................................................. 27 Device Data Latching ................................................................. 13 Command/Response .................................................................. 14 REVISION HISTORY 10/12--Revision 0: Initial Version Rev. 0 | Page 2 of 28 Data Sheet ADXRS810 SPECIFICATIONS Specification conditions at TA = 25C, PDD = 5 V, angular rate = 0/sec, bandwidth = f0/200, 1 g, continuous self-test on. Table 1. Parameter MEASUREMENT RANGE SENSITIVITY Nominal Sensitivity Sensitivity Tolerance Sensitivity Temperature Drift Nonlinearity 1 Cross-Axis Sensitivity 2 NULL Null Accuracy Null Temperature Drift Overall Null Accuracy1 Null Drift Gradient NOISE PERFORMANCE Rate Noise Density LOW-PASS FILTER Cut-Off (-3 dB) Frequency Group Delay 3 SENSOR RESONANT FREQUENCY SHOCK AND VIBRATION IMMUNITY Sensitivity-to-Linear Acceleration SELF-TEST Magnitude Fault Register Threshold Sensor Data Status Threshold Frequency ST Low-Pass Filter -3 dB Frequency ST Low-Pass Filter Group Delay3 SPI COMMUNICATIONS Clock Frequency Voltage Input High Voltage Input Low Output Voltage Low Output Voltage High Input/Output Leakage Current Internal Pull-Up Current Test Conditions/Comments Full-scale range See Figure 2 Symbol FSR Min 300 Typ Max 80 1 At 25C From -40C to +25C or 25C to 85C Best fit straight line -3 +3 0.05 3 At 25C -40C to +25C or 25C to 85C -40C to +85C -40C to +85C 2 -4 -8 -0.1 TA = 25C TA = -40C to 105C +4 +8 +0.1 0.015 0.020 f0/200, see Figure 10 Frequency = 0 Hz fLP tLP f0 3.25 13 DC to 5 kHz See the Continuous Self-Test section 77.5 4 15.5 4.75 19 0.03 MOSI, CS, SCLK MOSI, CS, SCLK MISO, current = 3 mA MISO, current = -2 mA MISO, MOSI, SCLK, VOL = 0 V MISO, MOSI, SCLK, VOL = PDD CS, PDD = 3.3 V, CS = 0.15 x PDD CS, PDD = 5 V, CS = 0.15 x PDD TEMPERATURE SENSOR Value at 45C Scale Factor 2239 1279 fST fOP VIH VIL VOL VOH IIL IIH IPU 485 1.95 64 8.08 PDD + 0.3 PDD x 0.15 0.5 PDD - 0.5 -0.1 0 60 80 0 5 Rev. 0 | Page 3 of 28 /sec /sec /sec /s/C Hz ms kHz /sec/g 2879 3839 0.85 x PDD -0.3 LSB//sec % % % FSR rms % /sec/Hz /sec/Hz 2559 Compared to LOCST data Compared to LOCST data f0/32 f0/8000 Unit /sec 0 0.1 200 300 LSBs LSBs LSBs Hz Hz ms MHz V V V V A A A A LSB LSB/C ADXRS810 Parameter POWER SUPPLY Supply Voltage Quiescent Supply Current Turn-On Time SWITCHING REGULATOR Required CP5 Supply Current Internal Operating Voltage Internal Resistance 5 V Supply 3.3 V Supply Required Current Data Sheet Test Conditions/Comments 2 3 Min PDD IDD 3.15 ICP5 VCP5 Ron 0.1 22 Power on to 1/2/sec of final or within 1% of final value (whichever comes first) See the Application Circuit section Current requirement for external inductor 5 V Supply 3.3 V Supply TEMPERATURE RANGE 1 Symbol Rev. 0 | Page 4 of 28 Max Unit 6 100 5.25 10 500 V mA ms 1 25 mA V 50 75 35 20 mA mA C Ityp TMIN, TMAX Minimum/maximum limit is at least 4 sigma based on characterization. Cross-axis sensitivity specification does not include effects due to device mounting on a PCB. Minimum/maximum limits are guaranteed by design. Typ -40 +105 Data Sheet ADXRS810 ABSOLUTE MAXIMUM RATINGS Table 2. RATE SENSITIVE AXIS Rating 2000 g The ADXRS810 is available in a SOIC package. The device transmits a positive-going LSB count for clockwise rotation about the axis normal to the package top. Conversely, a negative-going LSB count is transmitted for counterclockwise rotation about the Z-axis. 2000 g -0.3 V to +6.0 V Indefinite RATE AXIS -40C to +125C -40C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. + 16 9 SOIC PACKAGE Figure 2. RATEOUT Signal Increases with Clockwise Rotation ESD CAUTION THERMAL RESISTANCE JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance Package Type 16-Lead SOIC JA 191.5 JC 25 11034-002 Parameter Acceleration (Any Axis, Unpowered, 0.5 ms) Acceleration (Any Axis, Powered, 0.5 ms) Supply Voltage (PDD) Output Short-Circuit Duration (Any Pin to Common) Operating Temperature Range Storage Temperature Unit C/W Rev. 0 | Page 5 of 28 ADXRS810 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS DVDD 1 16 SCLK RSVD 2 15 MOSI RSVD 3 CS 4 MISO 5 PDD 6 11 AVSS PSS 7 10 RSVD VX 8 TOP VIEW (Not to Scale) 14 AVDD 13 DVSS 12 RSVD 9 CP5 11034-003 ADXRS810 Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2, 3, 10, 12 4 5 6 7 8 9 11 13 14 15 16 1 Mnemonic DVDD RSVD CS MISO PDD PSS VX CP5 AVSS DVSS AVDD MOSI SCLK Description Digital Regulated Voltage Output. See the Application Circuit section. Reserved for Analog Devices, Inc., Use Only. Connect to GND. 1 Chip Select. Master In/Slave Out. Supply Voltage. Switching Regulator Ground (GND). High Voltage Switching Node. See the Application Circuit section. High Voltage Supply. See the Application Circuit section. Analog Ground (GND). Digital Signal Ground (GND). Analog Regulated Voltage Output. See the Application Circuit section. Master Out/Slave In. SPI Clock. The RSVD pins must be connected to PCB ground. For enhanced product diagnosis, make this connection through a trace and not directly through the package footprint. See the Suggested PCB Layout section for proper connection to the PCB. Rev. 0 | Page 6 of 28 Data Sheet ADXRS810 TYPICAL PERFORMANCE CHARACTERISTICS N > 1000, unless otherwise noted. 0.50 +105C -40C PERCENTAGE OF POPULATION (%) 0.30 0.25 0.20 0.15 0.10 0.05 0 -2.0 -1.5 -1.0 -0.5 0 0.5 RATE OUT(/sec) 1.0 1.5 2.0 0.40 0.30 0.20 0.10 0 78 79 80 SENSITIVITY (LSB//sec) Figure 4. Initial Null Output 83 3 82 SENSITIVITY (LSB//sec) 1 0 -1 -2 81 80 79 78 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 TEMPERATURE (C) 76 11034-010 -4 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 TEMPERATURE (C) 11034-012 77 -3 Figure 8. Sensitivity over Temperature (N > 100) Figure 5. Typical Null Output Response over Temperature (N > 100) 1 Figure 9. Typical Root Allan Variance at -40C Figure 6. Typical Root Allan Variance at 105C Rev. 0 | Page 7 of 28 1000 11034-013 AVERAGING TIME (Hours) 100 10 1 0.1 0.01 0.001 0.0001 1000 0.01 0.001 11034-016 AVERAGING TIME (Hours) 100 10 1 0.1 0.01 0.001 0.0001 0.00001 0.000001 0.0000001 0.01 0.1 0.00001 0.1 0.0000001 ROOT ALLAN VARIANCE (/sec) 1 0.000001 NULL OUTPUT (/sec) 2 ROOT ALLAN VARIANCE (/sec) 82 Figure 7. Sensitivity 4 0.001 81 11034-007 +105C -40C 0.35 11034-008 PERCENTAGE OF POPULATION (%) 0.40 Data Sheet GYRO OUTPUT (/s) GYRO OUTPUT (/s/Hz) 0.1 0.01 0.001 5 10 100 FREQUENCY (Hz) 300 60 30 50 20 40 10 30 0 20 -10 10 -20 0 -30 -10 -40 0.10 11034-022 0.0001 DUT RESPONSE (/s) REF 0.15 0.20 0.25 0.30 0.35 -20 0.40 TIME (sec) Figure 10. DUT Typical Response to Random Vibration (5 Hz to 5 kHz at 15 g RMS) Rev. 0 | Page 8 of 28 Figure 11. DUT Typical Response to 50 g, 10 ms Half-Sine Shock Test INPUT ACCELERATION (g) 40 1 11034-021 ADXRS810 Data Sheet ADXRS810 THEORY OF OPERATION The ADXRS810 operates on the principle of a resonator gyro. Figure 12 presents a simplified illustration of one of four polysilicon sensing structures. Each sensing structure contains a dither frame that is electrostatically driven to resonance. This produces the necessary velocity element to produce a Coriolis force when experiencing angular rate. The ADXRS810 is designed to sense Z-axis (yaw) angular rate. When the sensing structure is exposed to angular rate, the resulting Coriolis force is coupled into an outer sense frame, which contains movable fingers that are placed between fixed pickoff fingers. This forms a capacitive pickoff structure that senses Coriolis motion. The resulting signal is fed to a series of gain and demodulation stages that produce the electrical rate signal output. The quad-sensor design rejects linear and angular acceleration, including external g-forces and vibration. This is achieved by mechanically coupling the four sensing structures such that external g-forces appear as common-mode signals that can be removed by the fully differential architecture implemented in the ADXRS810. CONTINUOUS SELF-TEST The ADXRS810 gyroscope uses a complete electromechanical self-test. An electrostatic force is applied to the gyroscope frame, resulting in a deflection of the capacitive sense fingers. This deflection is exactly equivalent to deflection that occurs as a result of the external rate input. The output from the beam structure is processed by the same signal chain as a true rate output signal, providing complete coverage of both the electrical and mechanical components. The electromechanical self-test is performed continuously during operation at a rate higher than the output bandwidth of the device. The self-test routine generates equivalent positive and negative rate deflections. This information can then be filtered such that there is no overall effect on the demodulated rate output. RATE SIGNAL WITH CONTINUOUS SELF-TEST SIGNAL SELF-TEST AMPLITUDE, INTERNALLY COMPARED TO THE SPECIFICATION TABLE LIMITS Y Z LOW FREQUENCY RATE INFORMATION 11034-023 Figure 13. Continuous Self-Test Demodulation Figure 12. Simplified Gyro Sense Structure The resonator requires 22.5 V (typical) for operation. Because only 5 V is typically available in most applications, a switching regulator is included on-chip. If an external high voltage supply is available, the inductor and diode can be omitted, and this supply can be connected to CP5. See the Application Circuit section. The difference amplitude between the positive and negative self-test deflections is filtered to f0/8000 (~1.95 Hz) and continuously monitored and compared to hardcoded self-test limits. If the measured amplitude exceeds these limits (listed in the Specifications table), one of two error conditions is asserted, depending on the magnitude of self-test error. For less severe self-test error magnitudes, the CST bit of the fault register is asserted; however, the status bits (ST[1:0]) in the sensor data response remain set to 0b01 for valid sensor data. For more severe self-test errors, the CST bit of the fault register is asserted, and the status bits (ST[1:0]) in the sensor data response are set to 0b00 for invalid sensor data. The thresholds for both failure conditions are listed in the Specifications table. The user can access the self-test information by issuing a read command to the self-test memory register (Address 0x04). See the SPI Communication Protocol--Applications section for more information about error reporting. Rev. 0 | Page 9 of 28 11034-024 X ADXRS810 Data Sheet APPLICATIONS INFORMATION CALIBRATED PERFORMANCE Each ADXRS810 gyroscope uses internal EEPROM memory to store its temperature calibration information. The calibration information is encoded into the device during factory testing. The calibration data is used to perform offset, gain, and selftest corrections over temperature. Storing this information internally removes the burden from the customer of performing system level temperature calibration. MECHANICAL CONSIDERATIONS FOR MOUNTING Mount the ADXRS810 in a location close to a hard mounting point of the printed circuit board (PCB) to the case. Mounting the ADXRS810 at an unsupported PCB location (that is, at the end of a lever or in the middle of a trampoline), as shown in Figure 14, may result in apparent measurement errors because the gyroscope is subject to the resonant vibration of the PCB. Locating the gyroscope near a hard mounting point helps ensure that any PCB resonances at the gyroscope are above the frequency at which harmful aliasing with the internal electronics can occur. To ensure that aliased signals do not couple into the baseband measurement range, it is recommended that the module be designed such that the first system level resonance occurs at a frequency higher than 800 Hz. supply do not result in the current exceeding the 0.1 mA to 1 mA limits. See the Specifications table for a complete description of the parameters related to the shunt regulator. Table 5. Component Inductor Diode Capacitor Capacitor Qty 1 1 3 1 Description 470 H (560 H) >24 V breakdown voltage 1 F 100 nF Note the following schematic recommendations: * Leakage current on the CP5 pin should be kept to a minimum. All sources of leakage, including reverse leakage current through the diode and PCB surface leakage, should account for not more than 70 A. For most applications, the diode is the primary source of leakage current. Applications that operate at 3.3 V should use an inductor value of 560 H to ensure proper operation of the internal boost regulator. For all applications, the inductor must be capable for 50 mA of peak current. * TO C 1 DVDD SCLK 16 1F TO C GYROSCOPE PCB GND RSVD MOSI RSVD AVDD CS DVSS MISO RSVD 1F 3.3V TO 5V Figure 14. Where Not to Mount a Gyroscope TO C PDD AVSS PSS RSVD VX CP5 1F APPLICATION CIRCUIT 100nF Figure 15 and Figure 16 show the recommended application circuits for the ADXRS810 gyroscope. These application circuits provide a connection reference for the SOIC package. Note that DVDD, AVDD, and PDD are all individually connected to ground through 1 F capacitors. Do not connect these supplies together. Additionally, an external diode and inductor must be connected for proper operation of the internal shunt regulator. These components allow for the internal resonator drive voltage to reach its required level, as listed in the Specifications table. Figure 16 presents an alternate method of operation for the ADXRS810 gyroscope. If the user has access to a power source that is capable of supplying a current of between 0.1 mA and 1 mA to the CP5 pin, this alternate source can be used to drive the internal regulator. In this application circuit, the external diode and inductor can be omitted and VX left as a no connect. 470H GND 11034-026 GND DIODE >24V BREAKDOWN Figure 15. Recommended ADXRS810 Application Circuit TO C 1 DVDD SCLK 16 1F TO C GND RSVD MOSI RSVD AVDD CS DVSS MISO RSVD 1F TO C TO C 3.3V TO 5V The required supply current to the CP5 pin can be met in one of two ways. Either a current source can be connected to CP5, such that the stated current requirement is satisfied, or a high voltage supply can be connected to CP5 through a resistor. For both methods, take precautions such that variations to the Rev. 0 | Page 10 of 28 PDD AVSS PSS RSVD VX CP5 1F 100nF GND 0.1mA TO 1mA GND HIGH VOLTAGE SUPPLY Figure 16. ADXRS810 Alternate Application Circuit 11034-027 MOUNTING POINTS 11034-025 TO C Data Sheet ADXRS810 ADXRS810 SIGNAL CHAIN TIMING The ADXRS810 primary signal chain is in Figure 17. It is the series of necessary functional circuit blocks through which the rate data is generated and processed. This sequence of electromechanical elements determines how quickly the device is capable of translating an external rate input stimulus into an SPI word to be sent to the master device. The group delay, which is a function of the filter characteristic, is the time required for the output of the low-pass filter to be within 10% of the external rate input and is seen to be ~4 ms. Additional delay can be observed due to the timing of SPI transactions and the population of the rate data into the internal device registers. This delay is broken down in Figure 17 such that the delay through each element of the signal chain is presented. The transfer function for the rate data low-pass filter (LPF) is given as 1 Z 64 1 1 Z 2 where: T 1 1 f 0 15.2 kHz (typ) And the transfer function for the continuous self-test LPF is given as 1 64 63 Z 1 where: T 16 16 (typ) f 0 15.2 kHz PRIMARY SIGNAL CHAIN <5s DELAY BAND-PASS FILTER ARITHMETIC LOGIC UNIT <5s DELAY 12-BIT ADC DEMOD RATE DATA LPF CONTINUOUS SELF-TEST LPF Z-AXIS ANGULAR RATE SENSOR <64ms GROUP DELAY Figure 17. ADXRS810 Primary Signal Chain and Associated Delays Rev. 0 | Page 11 of 28 <2.2ms DELAY SPI TRANSACTION 11034-030 <5s DELAY REGISTERS/MEMORY 4ms GROUP DELAY ADXRS810 Data Sheet SPI COMMUNICATIONS CHARACTERISTICS The following conditions apply to the SPI command and response timing characteristics in Table 6: * * * * * * All timing parameters are guaranteed through characterization. All timing is shown with respect to 10% of PDD and 90% of the actual delivered voltage waveform. Parameters are valid for 3.0 V PDD 5.5 V. Capacitive load for all signals is assumed to be 80 pF. Ambient temperature is -40C TA +105C. The MISO pull-up load is 47 k or 110 A. CS tTD tSCLK tLEAD tSCLKhi tSCLKlo tR tCSlag tF SCLK tMISOlag tA tV MISO tDIS MSB LSB tHIGH tSU MSB LSB 11034-032 MOSI Figure 18. SPI Timings Drawing Table 6. SPI Command/Response Timing Characteristics Symbol fOP tSCLKLhi tSCLKIo tSCLK tF tR tSU tHIGH tA tV tMISOlag tDIS tLEAD tCSlag tTD Function SPI operating frequency Clock (SCLK) high time Clock (SCLK) low time SCLK period Clock (SCLK) fall time Clock (SCLK) rise time Data input (MOSI) setup time Data input (MOSI) hold time Data output (MISO) access time Data output (MISO) valid after SCLK Data output (MISO) lag time Data output (MISO) disable time Enable (CS) lead time Enable (CS) lag time Sequential transfer delay Min 1/2 tSCLK - 13 1/2 tSCLK - 13 123.7 5.5 5.5 37 49 Max 8.08 13 13 20 32.5 0 40 1/2 tSCLK 1/2 tSCLK 0.1 Rev. 0 | Page 12 of 28 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns s Data Sheet ADXRS810 SPI COMMUNICATION PROTOCOL--APPLICATIONS DEVICE DATA LATCHING fast sequential transfer delay of 0.1 s (see Table 6). As a design precaution, it should be noted that the transmitted data is only as recent as the sequential transmission delay implemented by the system. Conditions that result in a sequential transfer delay of several seconds cause the next sequential device response to contain data that is several seconds old. To allow for rapid acquisition of data from the ADXRS810, device data latching is implemented as shown in Figure 19. Upon assertion of chip select, the data in the device is latched into memory. When the full MOSI command is received, and chip select deasserted, the appropriate data is shifted into the SPI port registers in preparation for the next sequential command/response exchange. This allows for an exceedingly DEVICE DATA IS LATCHED AFTER THE ASSERTION OF CS. LATCHED DATA IS TRANSMITTED DURING THE NEXT SEQUENTIAL COMMAND/RESPONSE EXCHANGE. CS 32 CLOCK CYCLES 32 CLOCK CYCLES MOSI COMMAND N 0x... COMMAND N + 1 0x... MISO RESPONSE N - 1 0x00000001 RESPONSE N 0x... Figure 19. Device Data Latching Rev. 0 | Page 13 of 28 32 CLOCK CYCLES COMMAND N + 2 0x... RESPONSE N + 1 0x... 11034-033 SCLK ADXRS810 Data Sheet COMMAND/RESPONSE Input/output is handled through a 32-bit command/response SPI interface. The command/response SPI interface is structured such that the response to a command is issued during the next sequential SPI exchange. As shown in Figure 20, the response (Response N) to a specific command (Command N) is issued upon receipt of the next command (Command N + 1). For the ADXRS810, the clock phase = clock polarity = 0. Additionally, the device response to the initial command is 0x00000001. This prevents the transmission of random data to the master device upon the initial command/response exchange. CS SCLK 32 CLOCK CYCLES 32 CLOCK CYCLES COMMAND N COMMAND N + 1 MISO RESPONSE N - 1 RESPONSE N Figure 20. SPI Protocol Rev. 0 | Page 14 of 28 11034-031 MOSI Data Sheet ADXRS810 SPI COMMUNICATION PROTOCOL--BIT DEFINITIONS Table 7. SPI Signals Signal Serial Clock Chip Select Master Out/Slave In Master In/Slave Out Symbol SCLK CS MOSI MISO Description Exactly 32 clock cycles when CS is active Active low Data sent to the gyro device from the main controller Data sent to the main controller from the gyro Table 8. SPI Commands Command 31 30 29 28 27 Sensor SQ1 SQ0 1 SQ2 Data 26 25 24 23 22 21 20 19 18 17 16 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHK P Read 1 0 0 SM2 SM1 SM0 A8 A7 A6 A5 A4 A3 A2 A1 A0 P Write 0 1 0 SM2 SM1 SM0 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P Table 9. SPI Responses Bit Command 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Sensor SQ2 SQ1 SQ0 P0 ST1 ST0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PLL Q NVM POR PWR CST CHK P1 Data Read 0 1 0 P0 1 1 1 0 SM2 SM1 SM0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P1 Write 0 0 1 P0 1 1 1 0 SM2 SM1 SM0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P1 R/W Error 0 0 0 P0 1 1 1 0 SM2 SM1 SM0 0 0 SPI RE DU COMMAND/RESPONSE BIT DESCRIPTIONS Table 10. Quick Guide--Bit Definitions for the SPI Interface Bit [SQ2:SQ0] [A8:A0] [D15:D0] P SPI RE [SM2:SM0] DU [ST1:ST0] P0 P1 Description Sequence bits (from master) Register address Data Command odd parity SPI command/response Request error Sensor module bits (from master) Data unavailable Status bits Response, odd parity, Bits[31:16] Response, odd parity, Bits[31:0] Rev. 0 | Page 15 of 28 PLL Q NVM POR PWR CST CHK P1 ADXRS810 Data Sheet SQ2:SQ0 Table 11. This field provides the system with a means of synchronizing the data samples received from multiple sensors. To facilitate correct synchronization, the ADXRS810 gyroscope includes the SQ[2:0] field in the response as it was received in the request. ST[1:0] 00 01 10 11 SM2:SM0 Sensor module bits from the master device. These bits are not implemented in the ADXRS810 but are hardcoded to 000 for all occurrences. There are two independent conditions that can result in the ST bits being set to 0b00 during a sensor data response. * A8:A0 These bits represent the memory address from which device data is read or to which information is written. These bits should be supplied by the master only when the memory registers are being accessed and are ignored for all sensor data requests. See the Memory Register Definitions section for a complete description of the available memory registers. Content in Bits[D15:D0] Error data for sensor data response Valid sensor data Sensor self-test data Read/write response * The self-test response is sufficiently different from its nominal value. See the Specifications table for the appropriate limits. A PLL fault is active. P D15:D0 Parity bit required for all master-to-slave data transmissions. Communications protocol requires one parity bit to achieve odd parity for the entire 32-bit command. Bits that are in don't care positions are still factored into the parity calculation. These 16 bits of device data can contain any of the following: P0 * Parity bit that establishes odd parity for Bits[31:16] of the device response. * * * Master: data to be written to a memory register as specified in A8:A0. Slave: sensor rate output data. Slave: device data read from the memory register specified in A8:A0, as well as data from the next sequential register. Slave: for a write command, the 16-bit data that is written to the specified memory register is reflected back to the master device for correlation. SPI The SPI bit is set when any of the following occurs: * * Too many/too few bits are transmitted A message from the control module contains a parity error The occurrence of a SPI error results in the device issuing a R/W error response (see Table 9), regardless of the SPI command type (see Table 8) issued by the master device. ST1:ST0 The ST1 and ST0 status bits are used to signal to the master device the type of data contained in the response message. The status bits are decoded as shown in Table 11. P1 Parity bit that establishes odd parity for the entire 32-bit device response. RE Communications error bit transmitted from the ADXRS810 device to the control module. Request errors can occur when * * * An invalid command is sent from the control module A read/write command specifies an invalid memory register A write command attempted to write to a nonwritable memory register DU Once the chip select pin (CS) is deasserted, wait 0.1 s before reasserting the chip select pin (CS) and initiating another command/response frame with the device. Failure to adhere to this timing specification may result in a data unavailable (DU) error. Rev. 0 | Page 16 of 28 Data Sheet ADXRS810 ADXRS810 FAULT REGISTER BIT DEFINITIONS Table 12 describes the bits available for signaling faults to the user. Table 12. Quick Guide--Fault Register Bit Definitions Bit PLL Q NVM POR UV AMP PWR CST CHK OV FAIL Description PLL failure Quadrature error NVM memory fault Power-on/reset failed to initialize Regulator undervoltage Amplitude detection failure Power regulation failed: overvoltage/undervoltage Continuous self-test failure Check; generate faults Regulator overvoltage Failure that sets the ST[1:0] bits to 0b00 The individual bits of the fault register are updated asynchronously, depending on their respective detection criteria; however, it is recommended that the fault register be read at a rate of at least 100 Hz. Once asserted, individual status bits are not deasserted until they are read by the master device. If the error persists after a fault register read, the status bit immediately reasserts and remains asserted until the next sequential command/response exchange. The FAULT0 register is appended to every sensor data request. The remaining fault information can be accessed by issuing a read command to Address 0x0A. PLL This bit indicates that the device had a failure in the phase lock loop functional circuit block, which occurs when the PLL fails to achieve sync with the resonator structure. If the PLL status flag is active, the ST bits of the sensor data response are set to 0b00, indicating that the response contains potentially invalid rate data. Q A Q fault can be asserted based on two independent quadrature calculations. Located in the QUAD1 memory register (Address 0x08) is a value corresponding to the total instantaneous quadrature present in the device. If this value exceeds 4096 LSBs, a Q fault is issued. Separately, an internal quadrature accumulator records the amount of quadrature correction performed by the ADXRS810. A Q fault is issued after the quadrature error present in the device contributes to an equivalent of 4/sec (typical) of rate offset. NVM An NVM error is transmitted to the control module if the internal NVM data fails a checksum calculation. This check is performed once every 50 s and does not include the PID memory register. POR An internal check is performed on device startup to ensure that the volatile memory of the device is functional. This is accomplished by programming a known value from the device's ROM into a volatile memory register. This value is continuously compared to the known value in ROM every 1 s for the duration of the device operation. If the value stored in the volatile memory changes, or does not match the value stored in ROM, the POR error flag is asserted. The value stored in ROM is rewritten to the volatile memory upon a device power cycle. PWR The device performs a continuous check of the internal 3 V regulated voltage level. If either an overvoltage (OV) or undervoltage (UV) fault is asserted, the PWR bit is asserted as well. These conditions occur when the regulated voltage is observed to be either more than 3.3 V or less than 2.77 V. An internal low-pass filter removes high frequency glitching effects so that the PWR bit is not asserted unnecessarily. To determine if the fault is a result of an overvoltage or undervoltage condition, the OV and UV fault bits must be analyzed. CST The ADXRS810 is designed with continuous self-test functionality. Measured self-test amplitudes are compared against the limits presented in the Specifications table. Deviation from this value results in a reported self-test error. There are two thresholds for a self-test failure. * * Rev. 0 | Page 17 of 28 A self-test value > 320 LSBs from nominal results in an assertion of the self-test flag in the fault register. A self-test value > 1280 LSBs from nominal results in both an assertion of the self-test flag in the fault register and setting of the ST[1:0] bits to 0b00, indicating that the rate data contained in the sensor data response is potentially invalid. ADXRS810 Data Sheet CHK UV The CHK bit is transmitted by the control module to the ADXRS810 as a method of generating faults. By asserting the CHK bit, the device creates conditions that result in the generation of all faults represented through the fault register. For example, the self-test amplitude is deliberately altered so that it exceeds the fault detection threshold, resulting in a selftest error. In this way, the device is capable of checking both its ability to detect a fault condition and its ability to report that fault to the control module. The UV fault bit asserts when the internally regulated voltage (nominally 3 V) is observed to be less than 2.77 V. This measurement is low pass filtered to prevent artifacts such as noise spikes from asserting a fault condition. When a UV fault occurs, the PWR fault bit is asserted simultaneously. Because the UV fault bit is not transmitted as part of a sensor data request, it is recommended that the user read back the FAULT1 and FAULT0 memory registers upon the assertion of a PWR error. This allows the user to determine the specific error condition. The fault conditions are initiated nearly simultaneously; however, the timing for receiving fault codes when the CHK bit is asserted is dependent upon the time required to generate each unique fault. It takes not more than 50 ms for all of the internal faults to be generated and the fault register to be updated to reflect the condition of the device. Until the CHK bit is cleared, the ST[1:0] status bits are set to 0b10, indicating that the data should be interpreted by the control module as self-test data. After the CHK bit is deasserted, the fault conditions require an additional 50 ms to decay and the device to return to normal operation. See Figure 21 for the proper methodology for asserting the CHK bit. OV The OV fault bit asserts when the internally regulated voltage (nominally 3 V) is observed to exceed 3.3 V. This measurement is low pass filtered to prevent artifacts such as noise spikes from asserting a fault condition. When an OV fault occurs, the PWR fault bit is asserted simultaneously. Because the OV fault bit is not transmitted as part of a sensor data request, it is recommended that the user read back the FAULT1 and FAULT0 memory registers upon the assertion of a PWR error. This allows the user to determine the specific error condition. FAIL The fail flag is asserted when a condition arises such that the ST[0:1] bits are set to 0b00. This indicates that the device has experienced a gross failure and that the sensor data could potentially be invalid. AMP The AMP fault bit is asserted when the measured amplitude of the silicon resonator has been significantly reduced. This condition can occur if the voltage supplied to CP5 has fallen below the requirements of the internal voltage regulator. This fault bit is OR'ed with the CST fault such that during a sensor data request the CST bit position represents either an AMP failure or a CST failure. The full fault status register, FAULT0, can then be read from memory to validate the specific failure. Rev. 0 | Page 18 of 28 Data Sheet ADXRS810 used in the next sequential command/response exchange. This results in an apparent one transaction delay before the data resulting from the assertion of the CHK bit is reported by the device. For all other read/write interactions with the device, no such delay exists, and the MOSI command is serviced during the next sequential command/ response exchange. Note that when the CHK bit is deasserted, if the user tries to obtain data from the device before the CST fault flag has cleared, the device reports the data as error data. Figure 21 illustrates a recommended start-up routine that can be implemented by the user. Alternate start-up sequences can be employed; however, take care that the response from the ADXRS810 is handled correctly. If implemented immediately after power is applied to the device, the total time to implement the following fault detection routine is approximately 200 ms. As described in the Device Data Latching section, the data present in the device upon the assertion of the CS signal is MOSI: SENSOR DATA REQUEST; CLEARS THE CHK BIT MOSI: SENSOR DATA REQUEST CHK COMMAND ASSERTED MISO: STANDARD INITIAL RESPONSE MISO: SENSOR DATA RESPONSE DATA LATCH POINT CS X 32 CLOCK CYCLES SCLK MOSI 0x2000 0003 MISO 0x0000001 t = 100ms POWER IS APPLIED TO THE DEVICE. WAIT 100ms TO ALLOW FOR THE INTERNAL CIRCUITRY TO BE INITIALIZED. 0x2000 0000 MISO: CHK RESPONSE ST[1:0] = 0b10 MISO: CHK RESPONSE ST[1:0] = 0b10 X 32 CLOCK CYCLES 32 CLOCK CYCLES 0x2000 0000 0x2000 0000 0x...FF OR 0x...FE (PARITY DEPENDENT) 0x... ONCE THE 100ms START-UP TIME HAS OCCURRED, THE MASTER DEVICE IS FREE TO ASSERT THE CHK BIT AND START THE PROCESS OF INTERNAL ERROR CHECKING. DURING THE FIRST COMMAND/ RESPONSE EXCHANGE AFTER POWER-ON, THE ADXRS800 IS DESIGNED TO ISSUE A PREDEFINED RESPONSE. MOSI: SENSOR DATA REQUEST X 32 CLOCK CYCLES t = 150ms MOSI: SENSOR DATA REQUEST t = 200ms A 50ms DELAY IS REQUIRED SO THAT THE GENERATION OF FAULTS WITHIN THE DEVICE IS ALLOWED TO COMPLETE. HOWEVER, BECAUSE THE DEVICE DATA IS LATCHED BEFORE THE CHK BIT IS ASSERTED, THE DEVICE RESPONSE DURING THIS COMMAND/RESPONSE EXCHANGE DOES NOT CONTAIN FAULT INFORMATION. THIS RESPONSE CAN BE DISCARDED. 0x...FF OR 0x...FE (PARITY DEPENDENT) t = 200ms + tTD ANOTHER 50ms DELAY MUST BE OBSERVED TO ALLOW THE FAULT CONDITIONS TO CLEAR. IF THE DEVICE IS FUNCTIONING PROPERLY, THE MISO RESPONSE CONTAINS ALL ACTIVE FAULTS, AS WELL AS HAVING SET THE MESSAGE FORMAT TO SELF-TEST DATA. THIS IS INDICATED THROUGH THE ST BITS BEING SET TO 0b10. Figure 21. Recommended Start-Up Sequence Rev. 0 | Page 19 of 28 t = 200ms + 2tTD THE FAULT BITS OF THE ADXRS800 REMAIN ACTIVE UNTIL CLEARED. DUE TO THE REQUIRED DECAY PERIOD FOR EACH FAULT CONDITION, FAULT CONDITIONS REMAIN PRESENT UPON THE IMMEDIATE DEASSERTION OF THE CHK BIT. THIS RESULTS IN A SECOND SEQUENTIAL RESPONSE IN WHICH THE FAULT BITS ARE ASSERTED. AGAIN, THE RESPONSE IS FORMATTED AS SELF-TEST DATA INDICATING THAT THE FAULT BITS HAVE BEEN SET INTENTIONALLY. ALL FAULT CONDITIONS ARE CLEARED, AND ALL SUBSEQUENT DATA EXCHANGES NEED ONLY OBSERVE THE SEQUENTIAL TRANSFER DELAY TIMING PARAMETER. 11034-034 CHK BIT ASSERTION: RECOMMENDED START-UP ROUTINE ADXRS810 Data Sheet SPI RATE DATA FORMAT The ADXRS810 gyroscope transmits rate data in a 16-bit format as part of a 32-bit SPI data frame. See Table 9 for the full 32-bit format of the sensor data request response. The rate data is transmitted MSB first, from D15 to D0. The data is formatted as a twos complement number, with a scale factor of 80 LSBs//sec. Therefore, the highest obtainable value for positive (clockwise) rotation is 0x7FFF (decimal +32,767) and for counterclockwise rotation is 0x8000 (decimal -32,768). Performance of the device is not guaranteed above 24,000 LSBs (300/sec). Table 13. ADXRS810 Rate Data Table 14-Bit Rate Data Decimal (LSBs) Hex (D15:D0) 32,767 0x7FFF ... ... 24,000 0x5DC0 ... ... 10,000 0x2710 ... ... 1000 0x03E8 ... ... 100 0x0064 ... ... 12 0x000C 11 0x000B 10 0x000A ... ... 3 0x0003 2 0x0002 1 0x0001 0 0x0000 -1 0xFFFF -2 0xFFFE -3 0xFFFD ... ... -10 0xFFF6 -11 0xFFF5 -12 0xFFF4 ... ... -100 0xFF9C ... ... -1000 0xFC18 ... ... -10, 000 0xD8F0 ... ... -24,000 0xA240 ... ... -32,768 0x8000 Data Type Rate data (not guaranteed) ... Rate data ... Rate data ... Rate data ... Rate data ... Rate data Rate data Rate data ... Rate data Rate data Rate data Rate data Rate data Rate data Rate data ... Rate data Rate data Rate data ... Rate data ... Rate data ... Rate data ... Rate data ... Rate data (not guaranteed) Rev. 0 | Page 20 of 28 Description Maximum possible positive data value ... 300/sec rotation (positive FSR) ... 125/sec rotation ... 12.5/sec rotation ... 1.25/sec rotation ... 0.15/sec rotation 0.1375/sec rotation 0.125/sec rotation ... 0.015/sec rotation 0.01375/sec rotation 0.0125/sec rotation 0 rotation value -0.0125/sec rotation -0.01375/sec rotation -0.015/sec rotation ... -0.125/sec rotation -0.1375/sec rotation -0.15/sec rotation ... -1.25/sec rotation ... -12.5/sec rotation ... -125/sec rotation ... -300/sec rotation (negative FSR) ... Maximum possible negative data value Data Sheet ADXRS810 ADXRS810 MEMORY MAP Table 14 contains a list of the memory registers that are available to be read by the user. See the Command/Response section for the proper input sequence to read a specific memory register. Each memory register comprises eight bits of data; however, when a read request is performed, the data is always returned as a 16-bit message. This is accomplished by appending the data from the next sequential register to the memory address that is specified. Data is transmitted MSB first. For proper acquisition of data from the memory register, the read request should be made to the even numbered register address only. The memory map registers are described in the Memory Register Definitions section. Table 14. ADXRS810 Memory Map 1 Addr Name MSB 0x00 RATE1 RTE15 RTE14 RTE13 RTE12 RTE11 RTE10 RTE9 RTE8 0x01 RATE0 RTE7 RTE6 RTE5 RTE4 RTE3 RTE2 RTE1 RTE0 0x02 TEM1 TEM9 TEM8 TEM7 TEM6 TEM5 TEM4 TEM3 TEM2 0x03 TEM0 TEM1 TEM0 X X X X X X 0x04 LOCST1 LCST15 LCST14 LCST13 LCST12 LCST11 LCST10 LCST9 LCST8 0x05 LOCST0 LCST7 LCST6 LCST5 LCST4 LCST3 LCST2 LCST1 LCST0 0x06 HICST1 HCST15 HCST14 HCST13 HCST12 HCST11 HCST10 HCST9 HCST8 0x07 HICST0 HCST7 HCST6 HCST5 HCST4 HCST3 HCST2 HCST1 HCST0 0x08 QUAD1 QAD15 QAD14 QAD13 QAD12 QAD11 QAD10 QAD9 QAD8 0x09 QUAD0 QAD7 QAD6 QAD5 QAD4 QAD3 QAD2 QAD1 QAD0 0x0A FAULT1 X X X X FAIL AMP OV UV 0x0B FAULT0 PLL Q NVM POR PWR CST CHK 0 0x0C PID1 PIDB15 PIDB14 PIDB13 PIDB12 PIDB11 PIDB10 PIDB9 PIDB8 0x0D PID0 PIDB7 PIDB6 PIDB5 PIDB4 PIDB3 PIDB2 PIDB1 PIDB0 0x0E SN3 SNB31 SNB30 SNB29 SNB28 SNB27 SNB26 SNB25 SNB24 0x0F SN2 SNB23 SNB22 SNB21 SNB20 SNB19 SNB18 SNB17 SNB16 0x10 SN1 SNB15 SNB14 SNB13 SNB12 SNB11 SNB10 SNB9 SNB8 0x11 SN0 SNB7 SNB6 SNB5 SNB4 SNB3 SNB2 SNB1 SNB0 1 LSB X = don't care. Rev. 0 | Page 21 of 28 ADXRS810 Data Sheet MEMORY REGISTER DEFINITIONS The SPI-accessible memory registers are described in this section. As described in the previous section, when requesting data from a memory register, only the first sequential memory address need be addressed. The data returned by the device contains 16 bits of memory register information. Bits[15:8] contain the MSB of the requested information, and Bits[7:0] contain the LSB. In each of the following register sections, the update rate and scale factors are called out for convenience. 0x00 RATE1, 0x01 RATE0 MSB D15 D7 D14 D6 D13 D5 D12 D4 D11 D3 D10 D2 D9 D1 LSB D8 D0 Register Update Rate: f0/32 (~485 Hz) Scale Factor: 80 LSBs//sec The rate registers contain the temperature compensated rate output of the device filtered to f0/200 (~77.5Hz). This data can also be accessed by issuing a sensor data read request to the device. The data is presented as a 16-bit, twos complement number. 0x02 TEM1, 0x03 TEM0 MSB1 D9 D1 1 D8 D0 D7 X D6 X D5 X D4 X D3 X LSB D2 X X = don't care. Register Update Rate: f0/32 (~485 Hz) Scale Factor: 5 LSBs/C The TEMx registers contain a value corresponding to the temperature of the device. The data is presented as a 10-bit, twos complement number. 0 LSBs corresponds to a temperature of approximately 45C. Table 15. Temperature 45C 85C 0C 1 X = don't care. Value of TEM1:TEM01 0000 0000 00XX XXXX 0011 0010 00XX XXXX 1100 0111 11XX XXXX 0x04 LOCST1, 0x05 LOCST0 MSB D15 D7 D14 D6 D13 D5 D12 D4 D11 D3 D10 D2 D9 D1 LSB D8 D0 Register Update Rate: f0/16 (~970 Hz) Scale Factor: 80 LSBs//sec The LOCSTx memory registers contain the value of the temperature compensated and low pass filtered continuous self-test delta. This value is a measure of the difference between the positive and negative self-test deflections and corresponds to the values presented in the Specifications table. The device issues a CST error when the value of the self-test exceeds the established self-test limits. The self-test data is filtered to f0/8000 (~1.95 Hz) to prevent false triggering of the CST fault bit. The data is presented as a 16-bit, twos complement number, with a scale factor of 80 LSBs//sec. 0x06 HICST1, 0x07 HICST0 MSB D15 D7 D14 D6 D13 D5 D12 D4 D11 D3 D10 D2 D9 D1 LSB D8 D0 Register Update Rate: f0/16 (~970 Hz) Scale Factor: 80 LSBs//sec The HICSTx registers contain the unfiltered self-test information. The HICSTx data can be used to supplement fault diagnosis in safety critical applications as sudden shifts in the self-test response are detected. However, the CST bit of the fault register is not set when the HICSTx data is observed to exceed the self-test limits. Only the LOCSTx memory register, which is designed to filter noise and the effects of sudden, temporary self-test spiking due to external disturbances, controls the assertion of the CST fault bit. The data is presented as a 16-bit, twos complement number. 0x08 QUAD1, 0x09 QUAD0 MSB D15 D7 D14 D6 D13 D5 D12 D4 D11 D3 D10 D2 D9 D1 LSB D8 D0 Register Update Rate: f0/64 (~240 Hz) Scale Factor: 80 LSBs//sec equivalent The QUADx memory registers contain a value corresponding to the amount of quadrature error present in the device at a given time. Quadrature can be likened to a measurement of the error of the motion of the resonator structure and can be caused by stresses and aging effects. The quadrature data is filtered to f0/200 (~77.5Hz) and can be read frequently to detect sudden shifts in the level of quadrature. The data is presented as a 16-bit, twos complement number. Rev. 0 | Page 22 of 28 Data Sheet ADXRS810 0x0A FAULT1, 0x0B FAULT0 MSB1 X PLL 1 X Q X NVM X POR FAIL PWR 0x0E SN3, 0x0F SN2, 0x10 SN1, 0x11 SN0 AMP CST OV CHK LSB UV 0 X = don't care. Register Update Rate: N/A Scale Factor: N/A The FAULTx registers contain the state of the error flags in the device. The FAULT0 register is appended to the end of every device data transmission (see Table 12); however, this register can also be accessed independently through its memory location. The individual fault bits are updated asynchronously, requiring <5 s to activate, once the fault condition exists onchip. Once toggled, each fault bit remains active until the fault register is read or a sensor data command is received. If the fault is still active after the bit is read, the fault bit immediately reasserts itself. MSB D31 D23 D15 D7 D14 D6 D13 D5 D12 D4 D11 D3 D10 D2 D9 D1 D29 D21 D13 D5 D28 D20 D12 D4 D27 D19 D11 D3 D26 D18 D10 D2 D25 D17 D9 D1 LSB D24 D16 D8 D0 Register Update Rate: N/A Scale Factor: N/A The SNx (serial number) registers contain a 32-bit identification number that uniquely identifies the device. To read the entire serial number, two memory read requests must be initiated. The first read request to Address 0x0E returns the upper 16 bits of the serial number, and the second read request to Address 0x10 returns the lower 16 bits of the serial number. 0X0C PID1, 0X0D PID0 MSB D15 D7 D30 D22 D14 D6 LSB D8 D0 Register Update Rate: N/A Scale Factor: N/A The PIDx (part ID) registers contain a 16-bit number identifying the version of the ADXRS810. Combined with the serial number, this information allows for a higher degree of device individualization and tracking. The initial product ID is 0x5201. 0x52 can be interpreted as the ASCII value for the R character, with 0x01 signifying the first revision. Subsequent versions of silicon can increment this value to R02 (0x5202), R03 (0x5203), and so on. Rev. 0 | Page 23 of 28 ADXRS810 Data Sheet SUGGESTED PCB LAYOUT * Figure 22 and Figure 23 show a suggested board layout for the SOIC package, and Figure 24 shows a sample solder pad layout. The board layout is intended for a 2-layer PCB design. While this exact layout need not be followed, the user should adhere to the following guidelines: * * 11034-051 * Locate C1, C2, and C3 as close as possible to their respective package pin. Connect all Analog Devices reserved pins to GND through a trace and not directly through the pad itself. Keep the trace from the VX package pin to L1/D1 as short as possible. It is acceptable to locate either L1 or D1 on the back side of the PCB to shorten this trace. Figure 23. SOIC PCB Layout Bottom Layer Metal (Silkscreen Is shown as a Reference Only and Is Not Present on the Back Side of the PCB.) Figure 22. SOIC PCB Layout Top Layer Metal 11.232 1.270 9.462 0.572 1.691 Figure 24. Sample SOIC Solder Pad Layout (Land Pattern); Dimensions Shown in Millimeters Rev. 0 | Page 24 of 28 11034-037 * * 11034-049 * Figure 22 and Figure 23 show the use of a top-layer metal GND plane for all GND connections. The use of a power plane is not recommended. For the SOIC package, it is not recommended to route the SPI interface traces under the device without proper shielding, such as a filled ground plane (used in Figure 22 and Figure 23). The PDD trace is widened compared to other signal traces for improved noise performance. Note that the L1 and D1 footprints change according to the user's selection of inductor and diode component. Data Sheet ADXRS810 SOLDER PROFILE SUPPLIER TP TC USER TP TC TC TC - 5C SUPPLIER tP USER tP TP tP MAXIMUM RAMP-UP RATE = 3C/sec MAXIMUM RAMP-DOWN RATE = 6C/sec TC - 5C TL TEMPERATURE TSMAX PREHEAT AREA tL TSMIN tS 11034-040 25 TIME 25C TO PEAK TIME Figure 25. Recommended Soldering Profile Table 16. Soldering Profile Characteristics Profile Feature Average Ramp Rate (TL to TP) Preheat Minimum Temperature (TSMIN) Maximum Temperature (TSMAX) Time (TSMIN to TSMAX) (tS) TSMAX to TL Ramp-Up Rate Time Maintained Above Liquidous (TL) Liquidous Temperature (TL) Time (tL) Classification Temperature (TC)1 Peak Temperature (TP) Time Within 5C of Actual Peak Temperature (tP) Ramp-Down Rate Time from 25C to Peak Temperature 1 Sn63/Pb37 Conditions Pb-Free 3C/sec maximum 100C 150C 60 sec to 120 sec 150C 200C 60 sec to 120 sec 3C/sec maximum 183C 60 sec to 150 sec 220C TC + 0C/-5C 10 sec to 30 sec 217C 60 sec to 150 sec 250C TC + 0C/-5C 20 sec to 40 sec 6C/sec maximum 6 minutes maximum 8 minutes maximum Based on IPC/JEDEC J-STD-020D.1 for SnPb and Pb-free processes. Package volume < 350 mm3, and package thickness > 2.5 mm. Rev. 0 | Page 25 of 28 ADXRS810 Data Sheet XRS810 BRGZ n #YYWW LLLLLLLLL 11034-041 PACKAGE MARKING CODES Figure 26. Package Marking Codes for the 16-Lead SOIC Table 17. Package Code Designations Marking XRS 810 B RG Z n # YYWW LLLLLLLLL Significance Angular rate sensor Series number Temperature grade (-40C to +105C) Package designator (SOIC package) RoHs compliant Revision number Pb-free designation Assembly date code Assembly lot code (up to nine characters) Rev. 0 | Page 26 of 28 Data Sheet ADXRS810 OUTLINE DIMENSIONS 10.30 BSC 9 DETAIL A 10.42 BSC 7.80 BSC 1 8 PIN 1 INDICATOR 0.25 GAGE PLANE 8 4 0 1.27 BSC 9.59 BSC 3.73 3.58 3.43 1.50 1.35 1.20 0.28 0.18 0.08 COPLANARITY 0.10 0.50 0.45 0.40 0.75 0.70 0.65 0.58 0.48 0.38 0.87 0.77 0.67 DETAIL A 072409-B 16 Figure 27. 16-Lead Small Outline, Plastic Cavity Package [SOIC_CAV] (RG-16-1) Dimensions shown in millimeters ORDERING GUIDE Model1, 2 ADXRS810WBRGZ-RL 1 2 Temperature Range -40C to +105C Package Description 16-Lead Small Outline, Plastic Cavity Package [SOIC_CAV] Package Option RG-16-1 Z = RoHS Compliant Part. W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The ADXRS810 model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for this model. Rev. 0 | Page 27 of 28 ADXRS810 Data Sheet NOTES (c)2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11034-0-10/12(0) Rev. 0 | Page 28 of 28