To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
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1. All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
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and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by
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(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
User’s Manual
µ
PD789304
µ
PD789306
µ
PD789314
µ
PD789316
µ
PD78F9306
µ
PD78F9316
µ
PD789306, 789316 Subseries
8-Bit Single-Chip Microcontrollers
Printed in Japan
Document No. U14800EJ3V0UD00 (3rd edition)
Date Published May 2005 NS CP(K)
2000, 2004
2 User’s Manual U14800EJ3V0UD
[MEMO]
User’s Manual U14800EJ3V0UD 3
1
2
3
4
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between V
IL
(MAX) and V
IH
(MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
IL
(MAX) and
V
IH
(MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
DD
or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dr y, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
NOTES FOR CMOS DEVICES
5
6
4 User’s Manual U14800EJ3V0UD
EEPROM and FIP are trademarks of NEC Electronics Corporation.
Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
User’s Manual U14800EJ3V0UD 5
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
The information in this document is current as of May, 2005. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
•
•
•
•
•
•
M8E 02. 11-1
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
"Standard":
"Special":
"Specific":
6 User’s Manual U14800EJ3V0UD
Regional Information
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
[GLOBAL SUPPORT]
http://www.necel.com/en/support/support.html
NEC Electronics America, Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-558-3737
NEC Electronics Shanghai Ltd.
Shanghai, P.R. China
Tel: 021-5888-5400
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 6253-8311
J04.1
N
EC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: 0211-65030
• Sucursal en España
Madrid, Spain
Tel: 091-504 27 87
Vélizy-Villacoublay, France
Tel: 01-30-67 58 00
• Succursale Française
• Filiale Italiana
Milano, Italy
Tel: 02-66 75 41
• Branch The Netherlands
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Tel: 040-244 58 45
• Tyskland Filial
Taeby, Sweden
Tel: 08-63 80 820
• United Kingdom Branch
Milton Keynes, UK
Tel: 01908-691-133
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
User’s Manual U14800EJ3V0UD
7
INTRODUCTION
Target Readers This manual is intended to give user engineers an understanding of the functions of
the
µ
PD789306 and
µ
PD789316 Subseries to design and develop its application
systems and programs.
Target products:
•
µ
PD789306 Subseries:
µ
PD789304, 789306, 78F9306
•
µ
PD789316 Subseries:
µ
PD789314, 789316, 78F9316
For the main system clock frequency, fX is applied to ceramic/crystal oscillation
(
µ
PD789306 Subseries) and fCC is applied to RC oscillation (
µ
PD789316 Subseries).
Purpose This manual is designed to deepen your understanding of the following functions
using the following organization.
Organization Two manuals are available for the
µ
PD789306 and
µ
PD789316 Subseries:
This manual and the instruction manual (common to the 78K/0S Series).
µ
PD789306, 789316
Subseries
User’s Manual
78K/0S Series
User’s Manual
Instructions
• Pin functions
• Internal block functions
• Interrupts
• Other internal peripheral functions
• Electrical specifications
• CPU function
• Instruction set
• Instruction description
How to Use This Manual It is assumed that the readers of this manual have general knowledge of electrical
engineering, logic circuits, and microcontrollers.
• To understand the overall functions of the
µ
PD789306 and
µ
PD789316 Subseries
→ Read this manual in the order of the CONTENTS.
The mark shows major revised points.
• How to read register formats
→ The name of a bit whose number is enclosed with < > is reserved in the
assembler and is defined as an sfr variable by the #pragma sfr directive in the C
compiler.
• To learn the detailed functions of a register whose register name is known
→ See APPENDIX C.
• To learn the details of the instruction functions of the 78K/0S series
→ Refer to 78K/0S Series Instructions User’s Manual (U11047E) separately
available.
• To learn the electrical specifications of the
µ
PD789306 and
µ
PD789316 Subseries
→ Refer to CHAPTER 22 ELECTRICAL SPECIFICATIONS.
User’s Manual U14800EJ3V0UD
8
Conventions Data significance: Higher digits on the left and lower digits on the right
Active low representation: xxx (overscore over pin or signal name)
Note: Footnote for item marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information
Numerical representation: Binary ... xxxx or xxxxB
Decimal ... xxxx
Hexadecimal ... xxxxH
Related Documents The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name Document No.
µ
PD789306, 789316 Subseries User’s Manual This manual
78K/0S Series Instructions User’s Manual U11047E
Documents Related to Development Software Tools (User’s Manuals)
Document Name Document No.
Operation U17391E
Language U17390E
RA78K0S Assembler Package
Structured Assembly Language U17389E
Operation U16654E CC78K0S C Compiler
Language U16655E
Operation U17246E SM+ System Simulator
User Open Interface U17247E
Operation U16768E SM78K Series Ver. 2.52 System Simulator
External Part User Open Interface Specification U15802E
ID78K0S-NS Ver. 2.52 Integrated Debugger Operation U16584E
PM plus Ver.5.20 U16934E
Documents Related to Development Hardware Tools (User’s Manuals)
Document Name Document No.
IE-78K0S-NS In-Circuit Emulator U13549E
IE-78K0S-NS-A In-Circuit Emulator U15207E
IE-789306-NS-EM1 Emulation Board U16115E
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
User’s Manual U14800EJ3V0UD
9
Documents Related to Flash Memory Writing
Document Name Document No.
PG-FP3 Flash Memory Programmer User’s Manual U13502E
PG-FP4 Flash Memory Programmer User’s Manual U15260E
Other Related Documents
Document Name Document No.
SEMICONDUCTOR SELECTION GUIDE - Products and Packages - X13769X
Semiconductor Device Mount Manual Note
Quality Grades on NEC Semiconductor Devices C11531E
NEC Semiconductor Device Reliability/Quality Control System C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E
Note See the “Semiconductor Device Mount Manual” webpage (http://www.necel.com/pkg/en/mount/index.html)
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
User’s Manual U14800EJ3V0UD
10
CONTENTS
CHAPTER 1 GENERAL (
µ
PD789306 SUBSERIES)............................................................................16
1.1 Features ......................................................................................................................................16
1.2 Applications................................................................................................................................16
1.3 Ordering Information .................................................................................................................17
1.4 Pin Configuration (Top View)....................................................................................................18
1.5 78K/0S Series Lineup.................................................................................................................20
1.6 Block Diagram ............................................................................................................................23
1.7 Overview of Functions...............................................................................................................24
CHAPTER 2 GENERAL (
µ
PD789316 SUBSERIES)............................................................................26
2.1 Features ......................................................................................................................................26
2.2 Applications................................................................................................................................26
2.3 Ordering Information .................................................................................................................27
2.4 Pin Configuration (Top View)....................................................................................................28
2.5 78K/0S Series Lineup.................................................................................................................30
2.6 Block Diagram ............................................................................................................................33
2.7 Overview of Functions...............................................................................................................34
CHAPTER 3 PIN FUNCTIONS (
µ
PD789306 SUBSERIES) ................................................................36
3.1 List of Pin Functions..................................................................................................................36
3.2 Description of Pin Functions ....................................................................................................38
3.2.1 P00 to P03 (Port 0) .......................................................................................................................38
3.2.2 P10 to P13 (Port 1) .......................................................................................................................38
3.2.3 P20 to P26 (Port 2) .......................................................................................................................38
3.2.4 P30 to P33 (Port 3) .......................................................................................................................39
3.2.5 P50 to P53 (Port 5) .......................................................................................................................39
3.2.6 S0 to S23 ......................................................................................................................................39
3.2.7 COM0 to COM3 ............................................................................................................................ 39
3.2.8 VLC0 to VLC2 ...................................................................................................................................39
3.2.9 CAPH, CAPL.................................................................................................................................39
3.2.10 RESET ..........................................................................................................................................40
3.2.11 X1, X2 ........................................................................................................................................... 40
3.2.12 XT1, XT2.......................................................................................................................................40
3.2.13 VDD ................................................................................................................................................40
3.2.14 VSS ................................................................................................................................................40
3.2.15 VPP (
µ
PD78F9306 only) ................................................................................................................40
3.2.16 IC (mask ROM version only) .........................................................................................................40
3.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins........................41
CHAPTER 4 PIN FUNCTIONS (
µ
PD789316 SUBSERIES) ................................................................43
4.1 List of Pin Functions..................................................................................................................43
User’s Manual U14800EJ3V0UD
11
4.2 Description of Pin Functions.................................................................................................... 45
4.2.1 P00 to P03 (Port 0) ....................................................................................................................... 45
4.2.2 P10 to P13 (Port 1) ....................................................................................................................... 45
4.2.3 P20 to P26 (Port 2) ....................................................................................................................... 45
4.2.4 P30 to P33 (Port 3) ....................................................................................................................... 46
4.2.5 P50 to P53 (Port 5) ....................................................................................................................... 46
4.2.6 S0 to S23 ...................................................................................................................................... 46
4.2.7 COM0 to COM3 ............................................................................................................................ 46
4.2.8 VLC0 to VLC2 ................................................................................................................................... 46
4.2.9 CAPH, CAPL................................................................................................................................. 47
4.2.10 RESET.......................................................................................................................................... 47
4.2.11 CL1, CL2....................................................................................................................................... 48
4.2.12 XT1, XT2....................................................................................................................................... 48
4.2.13 VDD ................................................................................................................................................ 48
4.2.14 VSS ................................................................................................................................................ 48
4.2.15 VPP (
µ
PD78F9316 only) ................................................................................................................ 48
4.2.16 IC (mask ROM version only) ......................................................................................................... 49
4.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins .......................49
CHAPTER 5 CPU ARCHITECTURE......................................................................................................51
5.1 Memory Space............................................................................................................................ 51
5.1.1 Internal program memory space ................................................................................................... 55
5.1.2 Internal data memory (internal high-speed RAM) space ............................................................... 55
5.1.3 Special function register (SFR) area ............................................................................................. 55
5.1.4 Data memory addressing .............................................................................................................. 56
5.2 Processor Registers .................................................................................................................. 59
5.2.1 Control registers............................................................................................................................ 59
5.2.2 General-purpose registers ............................................................................................................ 62
5.2.3 Special function registers (SFRs).................................................................................................. 63
5.3 Instruction Address Addressing .............................................................................................. 66
5.3.1 Relative addressing....................................................................................................................... 66
5.3.2 Immediate addressing................................................................................................................... 67
5.3.3 Table indirect addressing .............................................................................................................. 68
5.3.4 Register addressing ...................................................................................................................... 68
5.4 Operand Address Addressing..................................................................................................69
5.4.1 Direct addressing .......................................................................................................................... 69
5.4.2 Short direct addressing ................................................................................................................. 70
5.4.3 Special function register (SFR) addressing................................................................................... 71
5.4.4 Register addressing ...................................................................................................................... 72
5.4.5 Register indirect addressing.......................................................................................................... 73
5.4.6 Based addressing ......................................................................................................................... 74
5.4.7 Stack addressing .......................................................................................................................... 74
User’s Manual U14800EJ3V0UD
12
CHAPTER 6 PORT FUNCTIONS ...........................................................................................................75
6.1 Port Functions............................................................................................................................75
6.2 Port Configuration .....................................................................................................................77
6.2.1 Port 0 ............................................................................................................................................78
6.2.2 Port 1 ............................................................................................................................................79
6.2.3 Port 2 ............................................................................................................................................80
6.2.4 Port 3 ............................................................................................................................................85
6.2.5 Port 5 ............................................................................................................................................86
6.3 Registers Controlling Port Function ........................................................................................87
6.4 Port Function Operation............................................................................................................91
6.4.1 Writing to I/O port..........................................................................................................................91
6.4.2 Reading from I/O port.................................................................................................................... 91
6.4.3 Arithmetic operation of I/O port ..................................................................................................... 91
CHAPTER 7 CLOCK GENERATOR (
µ
PD789306 SUBSERIES) .......................................................92
7.1 Clock Generator Functions.......................................................................................................92
7.2 Clock Generator Configuration ................................................................................................92
7.3 Registers Controlling Clock Generator ...................................................................................94
7.4 System Clock Oscillators..........................................................................................................97
7.4.1 Main system clock oscillator..........................................................................................................97
7.4.2 Subsystem clock oscillator ............................................................................................................98
7.4.3 Examples of incorrect resonator connection .................................................................................99
7.4.4 Divider circuit............................................................................................................................... 100
7.4.5 When no subsystem clock is used .............................................................................................. 100
7.5 Clock Generator Operation .....................................................................................................101
7.6 Changing Setting of System Clock and CPU Clock .............................................................102
7.6.1 Time required for switching between system clock and CPU clock............................................. 102
7.6.2 Switching between system clock and CPU clock ........................................................................ 103
CHAPTER 8 CLOCK GENERATOR (
µ
PD789316 SUBSERIES) .....................................................104
8.1 Clock Generator Functions.....................................................................................................105
8.2 Clock Generator Configuration ..............................................................................................105
8.3 Registers Controlling Clock Generator .................................................................................106
8.4 System Clock Oscillators........................................................................................................109
8.4.1 Main system clock oscillator........................................................................................................ 109
8.4.2 Subsystem clock oscillator ..........................................................................................................110
8.4.3 Examples of incorrect resonator connection ............................................................................... 111
8.4.4 Divider circuit............................................................................................................................... 114
8.4.5 When no subsystem clock is used .............................................................................................. 114
8.5 Clock Generator Operation .....................................................................................................115
8.6 Changing Setting of System Clock and CPU Clock .............................................................116
8.6.1 Time required for switching between system clock and CPU clock............................................. 116
8.6.2 Switching between system clock and CPU clock ........................................................................ 117
User’s Manual U14800EJ3V0UD
13
CHAPTER 9 16-BIT TIMER 20............................................................................................................. 118
9.1 16-Bit Timer 20 Functions.......................................................................................................118
9.2 16-Bit Timer 20 Configuration ................................................................................................119
9.3 Registers Controlling 16-Bit Timer 20 ...................................................................................121
9.4 16-Bit Timer 20 Operation .......................................................................................................124
9.4.1 Operation as timer interrupt ........................................................................................................ 124
9.4.2 Operation as timer output............................................................................................................ 126
9.4.3 Capture operation ....................................................................................................................... 127
9.4.4 16-bit timer counter 20 readout ................................................................................................... 128
9.5 Cautions on Using 16-Bit Timer 20 ........................................................................................129
9.5.1 Restrictions when rewriting 16-bit compare register 20............................................................... 129
CHAPTER 10 8-BIT TIMER 30, 40.......................................................................................................131
10.1 8-Bit Timer 30, 40 Functions...................................................................................................131
10.2 8-Bit Timer 30, 40 Configuration ............................................................................................ 132
10.3 Registers Controlling 8-Bit Timer 30, 40 ...............................................................................137
10.4 8-Bit Timer 30, 40 Operation ...................................................................................................142
10.4.1 Operation as 8-bit timer counter.................................................................................................. 142
10.4.2 Operation as 16-bit timer counter................................................................................................ 152
10.4.3 Operation as carrier generator .................................................................................................... 159
10.4.4 Operation as PWM output (timer 40 only) ................................................................................... 164
10.5 Notes on Using 8-Bit Timer 30, 40..........................................................................................166
CHAPTER 11 WATCH TIMER .............................................................................................................168
11.1 Watch Timer Functions ...........................................................................................................168
11.2 Watch Timer Configuration..................................................................................................... 170
11.3 Register Controlling Watch Timer..........................................................................................171
11.4 Watch Timer Operation ...........................................................................................................172
11.4.1 Operation as watch timer ............................................................................................................ 172
11.4.2 Operation as interval timer .......................................................................................................... 172
CHAPTER 12 WATCHDOG TIMER ..................................................................................................... 174
12.1 Watchdog Timer Functions ....................................................................................................174
12.2 Watchdog Timer Configuration ..............................................................................................175
12.3 Registers Controlling Watchdog Timer.................................................................................176
12.4 Watchdog Timer Operation.....................................................................................................178
12.4.1 Operation as watchdog timer ...................................................................................................... 178
12.4.2 Operation as interval timer .......................................................................................................... 179
CHAPTER 13 SERIAL INTERFACE 10 ..............................................................................................180
13.1 Serial Interface 10 Functions..................................................................................................180
13.2 Serial Interface 10 Configuration ...........................................................................................181
13.3 Register Controlling Serial Interface 10 ................................................................................183
User’s Manual U14800EJ3V0UD
14
13.4 Serial Interface 10 Operation ..................................................................................................185
13.4.1 Operation stop mode................................................................................................................... 185
13.4.2 3-wire serial I/O mode ................................................................................................................. 186
CHAPTER 14 SERIAL INTERFACE 20 ..............................................................................................188
14.1 Serial Interface 20 Functions ..................................................................................................188
14.2 Serial Interface 20 Configuration............................................................................................189
14.3 Registers Controlling Serial Interface 20 ..............................................................................193
14.4 Serial Interface 20 Operation ..................................................................................................200
14.4.1 Operation stop mode................................................................................................................... 200
14.4.2 Asynchronous serial interface (UART) mode .............................................................................. 202
14.4.3 3-wire serial I/O mode ................................................................................................................. 215
CHAPTER 15 LCD CONTROLLER/DRIVER.......................................................................................220
15.1 LCD Controller/Driver Functions............................................................................................220
15.2 LCD Controller/Driver Configuration .....................................................................................220
15.3 Registers Controlling LCD Controller/Driver ........................................................................223
15.4 Setting LCD Controller/Driver.................................................................................................227
15.5 LCD Display Data Memory ......................................................................................................227
15.6 Common and Segment Signals ..............................................................................................228
15.7 Display Modes ..........................................................................................................................230
15.7.1 Three-time slot display example.................................................................................................. 230
15.7.2 Four-time slot display example.................................................................................................... 233
15.8 Supplying LCD Drive Voltages VLC0, VLC1, and VLC2 .............................................................236
CHAPTER 16 INTERRUPT FUNCTIONS ............................................................................................237
16.1 Interrupt Function Types.........................................................................................................237
16.2 Interrupt Sources and Configuration.....................................................................................237
16.3 Registers Controlling Interrupt Function ..............................................................................240
16.4 Interrupt Servicing Operation .................................................................................................246
16.4.1 Non-maskable interrupt request acknowledgment operation ......................................................246
16.4.2 Maskable interrupt request acknowledgment operation .............................................................. 248
16.4.3 Multiple interrupt servicing........................................................................................................... 249
16.4.4 Putting interrupt requests on hold ............................................................................................... 251
CHAPTER 17 STANDBY FUNCTION ..................................................................................................252
17.1 Standby Function and Configuration.....................................................................................252
17.1.1 Standby function ......................................................................................................................... 252
17.1.2 Register controlling standby function...........................................................................................253
17.2 Standby Function Operation...................................................................................................254
17.2.1 HALT mode................................................................................................................................. 254
17.2.2 STOP mode ................................................................................................................................ 257
CHAPTER 18 RESET FUNCTION .......................................................................................................260
User’s Manual U14800EJ3V0UD
15
CHAPTER 19 FLASH MEMORY...........................................................................................................263
19.1 Flash Memory Characteristics................................................................................................264
19.1.1 Programming environment.......................................................................................................... 264
19.1.2 Communication mode ................................................................................................................. 265
19.1.3 On-board pin connections ........................................................................................................... 268
19.1.4 Connection when using flash memory writing adapter ................................................................ 271
CHAPTER 20 MASK OPTIONS ...........................................................................................................275
CHAPTER 21 INSTRUCTION SET ......................................................................................................276
21.1 Operation ..................................................................................................................................276
21.1.1 Operand identifiers and description methods.............................................................................. 276
21.1.2 Description of “Operation” column............................................................................................... 277
21.1.3 Description of “Flag” column ....................................................................................................... 277
21.2 Operation List...........................................................................................................................278
21.3 Instructions Listed by Addressing Type ...............................................................................283
CHAPTER 22 ELECTRICAL SPECIFICATIONS..................................................................................286
CHAPTER 23 CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER
(REFERENCE VALUES) ...............................................................................................305
CHAPTER 24 PACKAGE DRAWINGS.................................................................................................307
CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS ............................................................310
APPENDIX A DEVELOPMENT TOOLS ..............................................................................................313
A.1 Software Package ....................................................................................................................315
A.2 Language Processing Software ............................................................................................. 315
A.3 Control Software ......................................................................................................................316
A.4 Flash Memory Writing Tools...................................................................................................316
A.5 Debugging Tools (Hardware)..................................................................................................317
A.6 Debugging Tools (Software)...................................................................................................318
APPENDIX B CAUTIONS ON DESIGNING TARGET SYSTEM..........................................................319
APPENDIX C REGISTER INDEX.........................................................................................................323
C.1 Register Index (Alphabetic Order of Register Name) ..........................................................323
C.2 Register Index (Alphabetic Order of Register Symbol) .......................................................325
APPENDIX D REVISION HISTORY ......................................................................................................327
D.1 Major Revisions in This Edition .............................................................................................327
D.2 Revision History of Previous Editions...................................................................................328
16 User’s Manual U14800EJ3V0UD
CHAPTER 1 GENERAL (
µ
PD789306 SUBSERIES)
1.1 Features
• Main system clock: Ceramic/crystal oscillation
• Minimum instruction execution time can be changed from high-speed (0.4
µ
s: @ 5.0 MHz operation with main
system clock) to ultra-low-speed (122
µ
s: @ 32.768 kHz operation with subsystem clock)
• ROM and RAM capacities
Item Data Memory
Part Number
Program Memory
(ROM) Internal High-Speed
RAM
LCD Display RAM
µ
PD789304 8 KB
µ
PD789306
Mask ROM
16 KB
µ
PD78F9306 Flash memory 16 KB
512 bytes 24 × 4 bits
• I/O ports: 23
• Serial interface: 2 channels
Switchable between 3-wire serial I/O mode and UART mode: 1 channel
3-wire serial I/O mode: 1 channel
• Timer: 5 channels
• 16-bit timer: 1 channel
• 8-bit timer/event counter: 2 channels
• Watch timer: 1 channel
• Watchdog timer: 1 channel
• LCD controller/driver
Segment signals: 24, common signals: 4
• Vectored interrupt sources: 15
• Power supply voltage: VDD = 1.8 to 5.5 V
• Operating ambient temperature: TA = –40 to +85°C
1.2 Applications
Remote controllers, healthcare equipment, etc.
CHAPTER 1 GENERAL (
µ
PD789306 SUBSERIES)
User’s Manual U14800EJ3V0UD
17
1.3 Ordering Information
Part Number Package Internal ROM
µ
PD789304GC-×××-AB8 64-pin plastic QFP (14 × 14 mm) Mask ROM
µ
PD789304GK-×××-9ET 64-pin plastic TQFP (12 × 12 mm) Mask ROM
µ
PD789304GK-×××-9ET-A 64-pin plastic TQFP (12 × 12 mm) Mask ROM
µ
PD789304GC-×××-8BS-A Note 64-pin plastic LQFP (14 × 14 mm) Mask ROM
µ
PD789306GC-×××-AB8 64-pin plastic QFP (14 × 14 mm) Mask ROM
µ
PD789306GK-×××-9ET 64-pin plastic TQFP (12 × 12 mm) Mask ROM
µ
PD789306GK-×××-9ET-A 64-pin plastic TQFP (12 × 12 mm) Mask ROM
µ
PD789306GC-×××-8BS-A Note 64-pin plastic LQFP (14 × 14 mm) Mask ROM
µ
PD78F9306GC-AB8 64-pin plastic QFP (14 × 14 mm) Flash memory
µ
PD78F9306GK-9ET 64-pin plastic TQFP (12 × 12 mm) Flash memory
µ
PD78F9306GK-9ET-A 64-pin plastic TQFP (12 × 12 mm) Flash memory
µ
PD78F9306GC-8BS-A Note 64-pin plastic LQFP (14 × 14 mm) Flash memory
Note To be development.
Remarks 1. ××× indicates ROM code suffix.
2. Products that have the part numbers suffixed by "-A" are lead-free products.
CHAPTER 1 GENERAL (
µ
PD789306 SUBSERIES)
User’s Manual U14800EJ3V0UD
18
1.4 Pin Configuration (Top View)
• 64-pin plastic QFP (14 × 14 mm) • 64-pin plastic TQFP (12 × 12 mm)
µ
PD789304GC-×××-AB8
µ
PD789304GK-×××-9ET
µ
PD789306GC-×××-AB8
µ
PD789306GK-×××-9ET
µ
PD78F9306GC-AB8
µ
PD78F9306GK-9ET
• 64-pin plastic LQFP (14 × 14 mm)
µ
PD789304GK-×××-9ET-A
µ
PD789304GC-×××-8BS-A Note
µ
PD789306GK-×××-9ET-A
µ
PD789306GC-×××-8BS-A Note
µ
PD78F9306GK-9ET-A
µ
PD78F9306GC-8BS-A Note
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P50
P51
P52
P53
IC (V
PP
)
XT1
XT2
V
DD
V
SS
X1
X2
RESET
P00/KR0
P01/KR1
P02/KR2
P03/KR3 32
CAPH
CAPL
V
LC0
V
LC1
V
LC2
COM0
COM1
COM2
COM3
S0
S1
S2
S3
S4
S5
S6
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
P20/SCK10
P21/SO10
P22/SI10
P23/SCK20/ASCK20
P24/SO20/TxD20
P25/SI20/RxD20
P26/TO20
P30/INTP0/CPT20
P31/INTP1/TO30/TMI40
P32/INTP2/TO40
P33/INTP3
P10
P11
P12
P13
S23
Caution Connect the IC (Internally Connected) pin directly to VSS.
Note To be development.
Remarks 1. The parenthesized values apply to
µ
PD78F9306.
2. Products that have the part numbers suffixed by "-A" are lead-free products.
CHAPTER 1 GENERAL (
µ
PD789306 SUBSERIES)
User’s Manual U14800EJ3V0UD
19
ASCK20: Asynchronous Serial Input S0 to S23: Segment Output
CAPH, CAPL: LCD Power Supply Capacitance Control SCK10, SCK20: Serial Clock
COM0 to COM3: Common Output SI10, SI20: Serial Input
CPT20: Capture Trigger Input SO10, SO20: Serial Output
IC: Internally Connected TMI40: Timer Input
INTP0 to INTP3: External interrupt Input TO20, TO30, TO40: Timer Output
KR0 to KR3: Key Return TxD20: Transmit Data
P00 to P03: Port 0 VDD: Power Supply
P10 to P13: Port 1 VLC0 to VLC2: LCD Power Supply
P20 to P26: Port 2 VPP: Programming Power Supply
P30 to P33: Port 3 VSS: Ground
P50 to P53: Port 5 X1, X2: Crystal/ceramic Oscillator
RESET: Reset XT1, XT2: Crystal Oscillator
RxD20: Receive Data
CHAPTER 1 GENERAL (
µ
PD789306 SUBSERIES)
User’s Manual U14800EJ3V0UD
20
1.5 78K/0S Series Lineup
The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.
80-pin SIO, 8-bit A/D converter, and resistance division type LCD (28 × 4)
52-pin
52-pin
SIO and resistance division type LCD (24 × 4)
8-bit A/D and on-chip voltage booster type LCD (23 × 4)
PD789327
PD789467
PD789446
PD789436
PD789426
PD789306
PD789316
PD789426 with enhanced A/D converter (10 bits)
PD789446 with enhanced A/D converter (10 bits)
SIO, 8-bit A/D, and on-chip voltage booster type LCD (15 × 4)
SIO, 8-bit A/D, and on-chip voltage booster type LCD (5 × 4)
RC oscillation version of the PD789306
SIO and on-chip voltage booster type LCD (24 × 4)
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
PD789407A
PD789456
LCD drive
80-pin PD789417A PD789407A with enhanced A/D converter (10 bits)
SIO, 10-bit A/D converter, and on-chip voltage booster type LCD (28 × 4)
80-pin
SIO, 8-bit A/D converter, and resistance division type LCD (28 × 4)
80-pin PD789479
PD789489
PD789881
64-pin UART and resistance division type LCD (26 × 4)
Products under development
Products in mass production
Small-scale package, general-purpose applications
78K/0S
Series
On-chip UART and capable of low voltage (1.8 V) operation
PD789074 with added subsystem clock
44-pin
Small-scale package, general-purpose applications and A/D converter
44-pin
30-pin
30-pin
30-pin
30-pin
PD789124A
PD789134A
PD789177
PD789167
PD789104A
PD789114A
PD789167 with enhanced A/D converter (10 bits)
PD789104A with enhanced timer
PD789124A with enhanced A/D converter (10 bits)
RC oscillation version of the PD789104A
PD789104A with enhanced A/D converter (10 bits)
PD789026 with added 8-bit A/D converter and multiplier
PD789177Y
PD789167Y
Y Subseries products support SMB.
88-pin PD789830
PD789835B
144-pin
UART and dot LCD (40 × 16)
UART, 8-bit A/D, and dot LCD (Total display output pins: 96)
42-/44-pin
44-pin
PD789074
30-pin PD789026 with enhanced timer
30-pin PD789074 with enhanced timer and increased ROM, RAM capacity
PD789088
PD789046
PD789026
USB
44-pin PD789800 For PC keyboard and on-chip USB function
Inverter control
44-pin PD789842 On-chip inverter controller and UART
VFD drive
52-pin PD789871 On-chip VFD controller (Total display output pins: 25)
Keyless entry
20-pin PD789860
PD789861
20-pin
On-chip POC and key return circuit
RC oscillation version of the PD789860
On-chip bus controller
30-pin PD789850A On-chip CAN controller
Meter control
PD789052
20-pin PD789860 without EEPROM, POC, and LVI
PD789062
20-pin RC oscillation version of the PD789052
PD789862
30-pin PD789860 with enhanced timer, added SIO, and increased ROM, RAM capacity
44-pin PD789852 PD789850A with enhanced functions such as timer and A/D converter
Sensor
20-pin PD789863
On-chip analog macro for sensor
20-pin
RC oscillation version of the PD789864
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µµ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
PD789864
µ
Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some
documents, but the functions of the two are the same.
CHAPTER 1 GENERAL (
µ
PD789306 SUBSERIES)
User’s Manual U14800EJ3V0UD
21
The major functional differences between the subseries are listed below.
Series for General-purpose applications and LCD drive
Timer VDD Function
Subseries Name
ROM
Capacity 8-Bit 16-Bit Watch WDT
8-Bit
A/D
10-Bit
A/D
Serial
Interface
I/O
MIN.
Value
Remarks
µ
PD789046 16 KB 1 ch
µ
PD789026 4 KB to 16 KB
1 ch 34
µ
PD789088 16 KB to
32 KB
3 ch
µ
PD789074 2 KB to 8 KB 1 ch
1 ch 1 ch
(UART: 1 ch)
24
−
µ
PD789062 RC oscillation
version
Small-scale
package,
general-
purpose
applications
µ
PD789052
4 KB 2 ch −
−
1 ch − −
− 14
1.8 V
−
µ
PD789177 − 8 ch
µ
PD789167
16 KB to
24 KB
3 ch 1 ch
8 ch −
31 −
µ
PD789134A − 4 ch
µ
PD789124A 4 ch −
RC oscillation
version
µ
PD789114A − 4 ch
Small-scale
package,
general-
purpose
applications
and A/D
converter
µ
PD789104A
2 KB to 8 KB 1 ch
1 ch
−
1 ch
4 ch −
1 ch
(UART: 1 ch)
20
1.8 V
−
µ
PD789835B 24 KB to
60 KB
6 ch − 3 ch 37 1.8 VNote
µ
PD789830 24 KB 1 ch
− 1 ch
(UART: 1 ch)
30 2.7 V
Dot LCD
supported
µ
PD789489 32 KB to
48 KB
−
8 ch
µ
PD789479 24 KB to
48 KB
8 ch −
2 ch
(UART: 1 ch)
45
µ
PD789417A − 7 ch
µ
PD789407A
12 KB to
24 KB
3 ch
7 ch −
43
µ
PD789456 − 6 ch
µ
PD789446 6 ch −
30
µ
PD789436 − 6 ch
µ
PD789426
12 KB to
16 KB
6 ch
1 ch
(UART: 1 ch)
40
−
µ
PD789316 RC oscillation
version
µ
PD789306
8 KB to 16 KB
1 ch
− 2 ch
(UART: 1 ch)
23
µ
PD789467 1 ch − 18
LCD drive
µ
PD789327
4 KB to 24 KB
2 ch
−
1 ch 1 ch
−
−
1 ch 21
1.8 V
−
Note Flash memory version: 3.0 V
CHAPTER 1 GENERAL (
µ
PD789306 SUBSERIES)
User’s Manual U14800EJ3V0UD
22
Series for ASSP
Timer VDD Function
Subseries Name
ROM
Capacity 8-Bit 16-Bit Watch WDT
8-Bit
A/D
10-Bit
A/D
Serial
Interface
I/O
MIN.
Value
Remarks
USB
µ
PD789800
8 KB 2 ch − − 1 ch − − 2 ch
(USB: 1 ch)
31 4.0 V −
Inverter
control
µ
PD789842
8 KB to 16 KB 3 ch Note 1 1 ch 1 ch 8 ch − 1 ch
(UART: 1 ch)
30 4.0 V −
µ
PD789852
24 KB to
32 KB
3 ch − 8 ch 3 ch
(UART: 2 ch)
31 On-chip bus
controller
µ
PD789850A
16 KB 1 ch
1 ch − 1 ch
4 ch − 2 ch
(UART: 1 ch)
18
4.0 V −
µ
PD789861
RC oscillation
version, on-
chip EEPROM
µ
PD789860
4 KB 2 ch − − 14 Keyless
entry
µ
PD789862
16 KB 1 ch 2 ch
− 1 ch − −
1 ch
(UART: 1 ch)
22
1.8 V
On-chip
EEPROM
µ
PD789864
On-chip
EEPROM
Sensor
µ
PD789863
4 KB 1 ch Note 2 − 1 ch − 4 ch − 5 1.9 V
RC oscillation
version, on-
chip EEPROM
VFD drive
µ
PD789871
4 KB to 8 KB 3 ch − 1 ch 1 ch − − 1 ch 33 2.7 V −
Meter
control
µ
PD789881
16 KB 2 ch 1 ch − 1 ch − − 1 ch
(UART: 1 ch)
28 2.7 VNote 3 −
Notes 1. 10-bit timer: 1 channel
2. 12-bit timer: 1 channel
3. Flash memory version: 3.0 V
CHAPTER 1 GENERAL (
µ
PD789306 SUBSERIES)
User’s Manual U14800EJ3V0UD
23
1.6 Block Diagram
V
DD
V
SS
IC
(V
PP
)
78K/0S
CPU core
ROM
(flash
memory)
TO30/TMI40
/INTP1/P31 8-bit
timer 30
P00 to P03
Port 0
P10 to P13
Port 1
P20 to P26
Port 2
P30 to P33
Port 3
P50 to P53
Port 5
TMI40/TO30
/INTP1/P31
TO20/P26 16-bit timer 20
Watch timer
Watchdog timer
Serial
interface 20
SCK20/ASCK20/P23
SI20/RxD20/P25
SO20/TxD20/P24
S0 to S23
COM0 to COM3
RAM
RAM space
for LCD
data
8-bit
tmer/event
counter 40
Cascaded
16-bit
timer/
event
counter
TO40/INTP2/P32
CPT20/INTP0
/P30
Serial
interface 10
SCK10/P20
SI10/P22
SO10/P21
V
LC0
to V
LC2
CAPH
CAPL
LCD controller
driver
System control
RESET
CL1
CL2
XT1
XT2
Interrupt control
INTP0/CPT20/
P30
INTP1/TO30/
TMI40/P31
INTP2/TO40/
P32
INTP3/P33
KR0/P00 to
KR3/P03
Remarks 1. The internal ROM capacity varies depending on the product.
2. The parenthesized values apply to
µ
PD78F9306.
CHAPTER 1 GENERAL (
µ
PD789306 SUBSERIES)
User’s Manual U14800EJ3V0UD
24
1.7 Overview of Functions
Part Number
Item
µ
PD789304
µ
PD789306
µ
PD78F9306
Internal memory ROM Mask ROM Flash memory
8 KB 16 KB 16 KB
High-speed RAM 512 bytes
LCD display RAM 24 × 4 bits
System clock Ceramic/crystal oscillation
Minimum instruction execution time • 0.4
µ
s/1.6
µ
s (@ 5.0 MHz operation with main system clock)
• 122
µ
s (@ 32.768 kHz operation with subsystem clock)
General-purpose registers 8 bits × 8 registers
Instruction set • 16-bit operations
• Bit manipulations (such as set, reset, and test)
Multiplier 8 bits × 8 bits = 16 bits
I/O ports Total: 23
• CMOS I/O: 19
• N-ch open-drain: 4
Serial interfaces • Switchable between 3-wire serial I/O mode and UART mode: 1 channel
• 3-wire serial I/O mode: 1 channel
Timers • 16-bit timer: 1 channel
• 8-bit timer/event counter: 2 channels
• Watch timer: 1 channel
• Watchdog timer: 1 channel
Timer outputs 3
LCD controller/driver • Segment signal outputs: 24 max.
• Common signal outputs: 4 max.
Maskable Internal: 9, external: 5 Vectored interrupt
sources Non-maskable Internal: 1
Power supply voltage VDD = 1.8 to 5.5 V
Operating ambient temperature TA = −40 to +85°C
Package • 64-pin plastic QFP (14 × 14 mm)
• 64-pin plastic TQFP (12 × 12 mm)
• 64-pin plastic LQFP (14 × 14 mm) (To be development)
CHAPTER 1 GENERAL (
µ
PD789306 SUBSERIES)
User’s Manual U14800EJ3V0UD 25
An outline of the timer is shown below.
16-Bit
Timer 20
8–Bit
Timer 30
8-Bit
Timer/Event
Counter 40
Watch Timer Watchdog
Timer
Interval timer – 1 channel 1 channel 1 channelNote 1 1 channelNote 2 Operation
mode External event
counter
– – 1 channel – –
Timer outputs 1 1 1 – –
Square-wave
outputs
– 1 1 – –
Capture 1 input – – – –
Function
Interrupt
sources
1 1 1 2 2
Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time.
2. The watchdog timer has the watchdog timer and interval timer functions. However, use the watchdog
timer by selecting either the watchdog timer function or interval timer function.
26 User’s Manual U14800EJ3V0UD
CHAPTER 2 GENERAL (
µ
PD789316 SUBSERIES)
2.1 Features
• Main system clock: RC oscillation
• Minimum instruction execution time can be changed from high-speed (0.5
µ
s: @ 4.0 MHz operation with main
system clock) to ultra-low-speed (122
µ
s: @ 32.768 kHz operation with subsystem clock)
• ROM and RAM capacities
Item Data Memory
Part Number
Program Memory
(ROM) Internal High-Speed
RAM
LCD Display RAM
µ
PD789314 Mask ROM 8 KB
µ
PD789316 16 KB
µ
PD78F9316 Flash memory 16 KB
512 bytes 24 × 4 bits
• I/O ports: 23
• Serial interface: 2 channels
Switchable between 3-wire serial I/O mode and UART mode: 1 channel
3-wire serial I/O mode: 1 channel
• Timer: 5 channels
• 16-bit timer: 1 channel
• 8-bit timer/event counter: 2 channels
• Watch timer: 1 channel
• Watchdog timer: 1 channel
• LCD controller/driver
Segment signals: 24, common signals: 4
• Vectored interrupt sources: 15
• Power supply voltage: VDD = 1.8 to 5.5 V
• Operating ambient temperature: TA = –40 to +85°C
2.2 Applications
Remote controllers, healthcare equipment, etc.
CHAPTER 2 GENERAL (
µ
PD789316 SUBSERIES)
User’s Manual U14800EJ3V0UD
27
2.3 Ordering Information
Part Number Package Internal ROM
µ
PD789314GC-×××-AB8 64-pin plastic QFP (14 × 14 mm) Mask ROM
µ
PD789314GK-×××-9ET 64-pin plastic TQFP (12 × 12 mm) Mask ROM
µ
PD789314GK-×××-9ET-A 64-pin plastic TQFP (12 × 12 mm) Mask ROM
µ
PD789314GC-×××-8BS-A Note 64-pin plastic LQFP (14 × 14 mm) Mask ROM
µ
PD789316GC-×××-AB8 64-pin plastic QFP (14 × 14 mm) Mask ROM
µ
PD789316GK-×××-9ET 64-pin plastic TQFP (12 × 12 mm) Mask ROM
µ
PD789316GK-×××-9ET-A 64-pin plastic TQFP (12 × 12 mm) Mask ROM
µ
PD789316GC-×××-8BS-A Note 64-pin plastic LQFP (14 × 14 mm) Mask ROM
µ
PD78F9316GC-AB8 64-pin plastic QFP (14 × 14 mm) Flash memory
µ
PD78F9316GK-9ET 64-pin plastic TQFP (12 × 12 mm) Flash memory
µ
PD78F9316GK-9ET-A 64-pin plastic TQFP (12 × 12 mm) Flash memory
µ
PD78F9316GC-8BS-A Note 64-pin plastic LQFP (14 × 14 mm) Flash memory
Note To be development.
Remarks 1. ××× indicates ROM code suffix.
2. Products that have the part numbers suffixed by "-A" are lead-free products.
CHAPTER 2 GENERAL (
µ
PD789316 SUBSERIES)
User’s Manual U14800EJ3V0UD
28
2.4 Pin Configuration (Top View)
• 64-pin plastic QFP (14 × 14 mm) • 64-pin plastic TQFP (12 × 12 mm)
µ
PD789314GC-×××-AB8
µ
PD789314GK-×××-9ET
µ
PD789316GC-×××-AB8
µ
PD789316GK-×××-9ET
µ
PD78F9316GC-AB8
µ
PD78F9316GK-9ET
• 64-pin plastic LQFP (14 × 14 mm)
µ
PD789314GK-×××-9ET-A
µ
PD789314GC-×××-8BS-A Note
µ
PD789316GK-×××-9ET-A
µ
PD789316GC-×××-8BS-A Note
µ
PD78F9316GK-9ET-A
µ
PD78F9316GC-8BS-A Note
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P50
P51
P52
P53
IC (V
PP
)
XT1
XT2
V
DD
V
SS
X1
X2
RESET
P00/KR0
P01/KR1
P02/KR2
P03/KR3 32
CAPH
CAPL
V
LC0
V
LC1
V
LC2
COM0
COM1
COM2
COM3
S0
S1
S2
S3
S4
S5
S6
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
P20/SCK10
P21/SO10
P22/SI10
P23/SCK20/ASCK20
P24/SO20/TxD20
P25/SI20/RxD20
P26/TO20
P30/INTP0/CPT20
P31/INTP1/TO30/TMI40
P32/INTP2/TO40
P33/INTP3
P10
P11
P12
P13
S23
Caution Connect the IC (Internally Connected) pin directly to VSS.
Note To be development.
Remark The parenthesized values apply to
µ
PD78F9316.
CHAPTER 2 GENERAL (
µ
PD789316 SUBSERIES)
User’s Manual U14800EJ3V0UD
29
ASCK20: Asynchronous Serial Input RxD20: Receive Data
CAPH, CAPL: LCD Power Supply Capacitance Control S0 to S23: Segment Output
CL1, CL2: RC Oscillator SCK10, SCK20: Serial Clock
COM0 to COM3: Common Output SI10, SI20: Serial Input
CPT20: Capture Trigger Input SO10, SO20: Serial Output
IC: Internally Connected TMI40: Timer Input
INTP0 to INTP3: External interrupt Input TO20, TO30, TO40: Timer Output
KR0 to KR3: Key Return TxD20: Transmit Data
P00 to P03: Port 0 VDD: Power Supply
P10 to P13: Port 1 VLC0 to VLC2: LCD Power Supply
P20 to P26: Port 2 VPP: Programming Power Supply
P30 to P33: Port 3 VSS: Ground
P50 to P53: Port 5 XT1, XT2: Crystal Oscillator
RESET: Reset
CHAPTER 2 GENERAL (
µ
PD789316 SUBSERIES)
User’s Manual U14800EJ3V0UD
30
2.5 78K/0S Series Lineup
The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.
80-pin SIO, 8-bit A/D converter, and resistance division type LCD (28 × 4)
52-pin
52-pin SIO and resistance division type LCD (24 × 4)
8-bit A/D and on-chip voltage booster type LCD (23 × 4)
PD789327
PD789467
PD789446
PD789436
PD789426
PD789306
PD789316
PD789426 with enhanced A/D converter (10 bits)
PD789446 with enhanced A/D converter (10 bits)
SIO, 8-bit A/D, and on-chip voltage booster type LCD (15 × 4)
SIO, 8-bit A/D, and on-chip voltage booster type LCD (5 × 4)
RC oscillation version of the PD789306
SIO and on-chip voltage booster type LCD (24 × 4)
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
PD789407A
PD789456
LCD drive
80-pin PD789417A PD789407A with enhanced A/D converter (10 bits)
SIO, 10-bit A/D converter, and on-chip voltage booster type LCD (28 × 4)
80-pin SIO, 8-bit A/D converter, and resistance division type LCD (28 × 4)
80-pin PD789479
PD789489
PD789881
64-pin UART and resistance division type LCD (26 × 4)
Products under development
Products in mass production
Small-scale package, general-purpose applications
78K/0S
Series
On-chip UART and capable of low voltage (1.8 V) operation
PD789074 with added subsystem clock
44-pin
Small-scale package, general-purpose applications and A/D converter
44-pin
30-pin
30-pin
30-pin
30-pin
PD789124A
PD789134A
PD789177
PD789167
PD789104A
PD789114A
PD789167 with enhanced A/D converter (10 bits)
PD789104A with enhanced timer
PD789124A with enhanced A/D converter (10 bits)
RC oscillation version of the PD789104A
PD789104A with enhanced A/D converter (10 bits)
PD789026 with added 8-bit A/D converter and multiplier
PD789177Y
PD789167Y
Y Subseries products support SMB.
88-pin PD789830
PD789835B
144-pin
UART and dot LCD (40 × 16)
UART, 8-bit A/D, and dot LCD (Total display output pins: 96)
42-/44-pin
44-pin
PD789074
30-pin PD789026 with enhanced timer
30-pin PD789074 with enhanced timer and increased ROM, RAM capacity
PD789088
PD789046
PD789026
USB
44-pin PD789800 For PC keyboard and on-chip USB function
Inverter control
44-pin PD789842 On-chip inverter controller and UART
VFD drive
52-pin PD789871 On-chip VFD controller (Total display output pins: 25)
Keyless entry
20-pin PD789860
PD789861
20-pin
On-chip POC and key return circuit
RC oscillation version of the PD789860
On-chip bus controller
30-pin PD789850A On-chip CAN controller
Meter control
PD789052
20-pin PD789860 without EEPROM, POC, and LVI
PD789062
20-pin RC oscillation version of the PD789052
PD789862
30-pin PD789860 with enhanced timer, added SIO, and increased ROM, RAM capacity
44-pin PD789852 PD789850A with enhanced functions such as timer and A/D converter
Sensor
20-pin PD789863
On-chip analog macro for sensor
20-pin RC oscillation version of the PD789864
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µµ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
PD789864
µ
Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some
documents, but the functions of the two are the same.
CHAPTER 2 GENERAL (
µ
PD789316 SUBSERIES)
User’s Manual U14800EJ3V0UD
31
The major functional differences between the subseries are listed below.
Series for General-purpose applications and LCD drive
Timer VDD Function
Subseries Name
ROM
Capacity 8-Bit 16-Bit Watc
h
WDT
8-Bit
A/D
10-Bit
A/D
Serial
Interface
I/O
MIN.
Value
Remarks
µ
PD789046 16 KB 1 ch
µ
PD789026 4 KB to 16 KB
1 ch 34
µ
PD789088 16 KB to
32 KB
3 ch
µ
PD789074 2 KB to 8 KB 1 ch
1 ch 1 ch
(UART: 1 ch)
24
−
µ
PD789062 RC oscillation
version
Small-scale
package,
general-
purpose
applications
µ
PD789052
4 KB 2 ch −
−
1 ch − −
− 14
1.8 V
−
µ
PD789177 − 8 ch
µ
PD789167
16 KB to
24 KB
3 ch 1 ch
8 ch −
31 −
µ
PD789134A − 4 ch
µ
PD789124A 4 ch −
RC oscillation
version
µ
PD789114A − 4 ch
Small-scale
package,
general-
purpose
applications
and A/D
converter
µ
PD789104A
2 KB to 8 KB 1 ch
1 ch
−
1 ch
4 ch −
1 ch
(UART: 1 ch)
20
1.8 V
−
µ
PD789835B 24 KB to
60 KB
6 ch − 3 ch 37 1.8 VNote
µ
PD789830 24 KB 1 ch
− 1 ch
(UART: 1 ch)
30 2.7 V
Dot LCD
supported
µ
PD789489 32 KB to
48 KB
−
8 ch
µ
PD789479 24 KB to
48 KB
8 ch −
2 ch
(UART: 1 ch)
45
µ
PD789417A − 7 ch
µ
PD789407A
12 KB to
24 KB
3 ch
7 ch −
43
µ
PD789456 − 6 ch
µ
PD789446 6 ch −
30
µ
PD789436 − 6 ch
µ
PD789426
12 KB to
16 KB
6 ch
1 ch
(UART: 1 ch)
40
−
µ
PD789316 RC oscillation
version
µ
PD789306
8 KB to 16 KB
1 ch
− 2 ch
(UART: 1 ch)
23
µ
PD789467 1 ch − 18
LCD drive
µ
PD789327
4 KB to 24 KB
2 ch
−
1 ch 1 ch
−
−
1 ch 21
1.8 V
−
Note Flash memory version: 3.0 V
CHAPTER 2 GENERAL (
µ
PD789316 SUBSERIES)
User’s Manual U14800EJ3V0UD
32
Series for ASSP
Timer VDD Function
Subseries Name
ROM
Capacity 8-Bit 16-Bit Watc
h
WDT
8-Bit
A/D
10-Bit
A/D
Serial
Interface
I/O
MIN.
Value
Remarks
USB
µ
PD789800
8 KB 2 ch − − 1 ch − − 2 ch
(USB: 1 ch)
31 4.0 V −
Inverter
control
µ
PD789842
8 KB to 16 KB 3 ch Note 1 1 ch 1 ch 8 ch − 1 ch
(UART: 1 ch)
30 4.0 V −
µ
PD789852
24 KB to
32 KB
3 ch − 8 ch 3 ch
(UART: 2 ch)
31 On-chip bus
controller
µ
PD789850A
16 KB 1 ch
1 ch − 1 ch
4 ch − 2 ch
(UART: 1 ch)
18
4.0 V −
µ
PD789861
RC oscillation
version, on-
chip EEPROM
µ
PD789860
4 KB 2 ch − − 14 Keyless
entry
µ
PD789862
16 KB 1 ch 2 ch
− 1 ch − −
1 ch
(UART: 1 ch)
22
1.8 V
On-chip
EEPROM
µ
PD789864
On-chip
EEPROM
Sensor
µ
PD789863
4 KB 1 ch Note 2 − 1 ch − 4 ch − 5 1.9 V
RC oscillation
version, on-
chip EEPROM
VFD drive
µ
PD789871
4 KB to 8 KB 3 ch − 1 ch 1 ch − − 1 ch 33 2.7 V −
Meter
control
µ
PD789881
16 KB 2 ch 1 ch − 1 ch − − 1 ch
(UART: 1 ch)
28 2.7 VNote
3
−
Notes 1. 10-bit timer: 1 channel
2. 12-bit timer: 1 channel
3. Flash memory version: 3.0 V
CHAPTER 2 GENERAL (
µ
PD789316 SUBSERIES)
User’s Manual U14800EJ3V0UD
33
2.6 Block Diagram
V
DD
V
SS
IC
(V
PP
)
78K/0S
CPU core
ROM
(flash
memory)
TO30/TMI40
/INTP1/P31 8-bit
timer 30 P00 to P03
Port 0
P10 to P13
Port 1
P20 to P26
Port 2
P30 to P33
Port 3
P50 to P53
Port 5
TMI40/TO30
/INTP1/P31
TO20/P26 16-bit timer 20
Watch timer
Watchdog timer
Serial
interface 20
SCK20/ASCK20/P23
SI20/RxD20/P25
SO20/TxD20/P24
S0 to S23
COM0 to COM3
RAM
RAM space
for LCD
data
8-bit
timer/event
counter 40
Cascaded
16-bit
tmer/
event
counter
TO40/INTP2/P32
CPT20/INTP0
/P30
Serial
interface 10
SCK10/P20
SI10/P22
SO10/P21
V
LC0
to V
LC2
CAPH
CAPL
LCD controller
driver
System control
RESET
CL1
CL2
XT1
XT2
Interrupt control
INTP0/CPT20/
P30
INTP1/TO30/
TMI40/P31
INTP2/TO40/
P32
INTP3/P33
KR0/P00 to
KR3/P03
Remarks 1. The internal ROM capacity varies depending on the product.
2. The parenthesized values apply to
µ
PD78F9316.
CHAPTER 2 GENERAL (
µ
PD789316 SUBSERIES)
User’s Manual U14800EJ3V0UD
34
2.7 Overview of Functions
Part Number
Item
µ
PD789314
µ
PD789316
µ
PD78F9316
Internal memory ROM Mask ROM Flash memory
8 KB 16 KB 16 KB
High-speed RAM 512 bytes
LCD display RAM 24 × 4 bits
System clock RC oscillation
Minimum instruction execution time • 0.5
µ
s/2.0
µ
s (@ 4.0 MHz operation with main system clock)
• 122
µ
s (@ 32.768 kHz operation with subsystem clock)
General-purpose registers 8 bits × 8 registers
Instruction set • 16-bit operations
• Bit manipulations (such as set, reset, and test)
Multiplier 8 bits × 8 bits = 16 bits
I/O ports Total: 23
• CMOS I/O: 19
• N-ch open-drain: 4
Serial interfaces • Switchable between 3-wire serial I/O mode and UART mode: 1 channel
• 3-wire serial I/O mode: 1 channel
Timers • 16-bit timer: 1 channel
• 8-bit timer/event counter: 2 channels
• Watch timer: 1 channel
• Watchdog timer: 1 channel
Timer outputs 3
LCD controller/driver • Segment signal outputs: 24 max.
• Common signal outputs: 4 max.
Maskable Internal: 9, external: 5 Vectored interrupt
sources Non-maskable Internal: 1
Power supply voltage VDD = 1.8 to 5.5 V
Operating ambient temperature TA = −40 to +85°C
Package • 64-pin plastic QFP (14 × 14 mm)
• 64-pin plastic TQFP (12 × 12 mm)
• 64-pin plastic LQFP (14 × 14 mm) (To be development)
CHAPTER 2 GENERAL (
µ
PD789316 SUBSERIES)
User’s Manual U14800EJ3V0UD 35
An outline of the timer is shown below.
16-Bit
Timer 20
8–Bit
Timer 30
8-Bit
Timer/Event
Counter 40
Watch Timer Watchdog
Timer
Interval timer – 1 channel 1 channel 1 channelNote 1 1 channelNote 2 Operation
mode External event
counter
– – 1 channel – –
Timer outputs 1 1 1 – –
Square-wave
outputs
– 1 1 – –
Capture 1 input – – – –
Function
Interrupt
sources
1 1 1 2 2
Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time.
2. The watchdog timer has the watchdog timer and interval timer functions. However, use the watchdog
timer by selecting either the watchdog timer function or interval timer function.
36 User’s Manual U14800EJ3V0UD
CHAPTER 3 PIN FUNCTIONS (
µ
PD789306 SUBSERIES)
3.1 List of Pin Functions
(1) Port pins
Pin Name I/O Function After Reset Alternate Function
P00 to P03 I/O Port 0.
4-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be
specified by means of pull-up resistor option register 0 (PU0) or
key return mode register 00 (KRM00) in port units.
Input KR0 to KR3
P10 to P13 I/O Port 1.
4-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be
specified by means of pull-up resistor option register 0 (PU0) in
port units.
Input –
P20 SCK10
P21 SO10
P22 SI10
P23 SCK20/ASCK20
P24 SO20/TxD20
P25 SI20/RxD20
P26
I/O Port 2.
7-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be
specified by means of pull-up resistor option register B2 (PUB2)
in 1-bit units.
Input
TO20
P30 INTP0/CPT20
P31 INTP1/TO30/
TMI40
P32 INTP2/TO40
P33
I/O Port 3.
4-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be
specified by means of pull-up resistor option register B3 (PUB3)
in 1-bit units.
Input
INTP3
P50 to P53 I/O Port 5.
4-bit N-ch open-drain I/O port.
Input/output can be specified in 1-bit units.
For a mask ROM version, an on-chip pull-up resistor can be
specified by the mask option in 1-bit units.
Input −
CHAPTER 3 PIN FUNCTIONS (
µ
PD789306 SUBSERIES)
User’s Manual U14800EJ3V0UD 37
(2) Non-port pins
Pin Name I/O Function After Reset Alternate Function
INTP0 P30/CPT20
INTP1 P31/TO30/TMI40
INTP2 P32/TO40
INTP3
Input External interrupt input for which the valid edge (rising edge,
falling edge, or both rising and falling edges) can be specified
Input
P33
KR0 to KR3 Input Key return signal detection Input P00 to P03
SCK10 Serial interface 10 serial clock input/output P20
SCK20
I/O
Serial interface 20 serial clock input/output
Input
P23/ASCK20
SI10 Serial interface 10 serial data input P22
SI20
Input
Serial interface 20 serial data input
Input
P25/RxD20
SO10 Serial interface 10 serial data output P21
SO20
Output
Serial interface 20 serial data output
Input
P24/TxD20
ASCK20 Input Serial clock input for asynchronous serial interface Input P23/SCK20
RxD20 Input Serial data input for asynchronous serial interface Input P25/SI20
TxD20 Output Serial data output for asynchronous serial interface Input P24/SO20
TO20 Output 16-bit timer 20 output Input P26
CPT20 Input Capture edge input Input P30/INTP0
TO30 Output Timer 30 output Input P31/INTP1/TMI40
TO40 Output Timer 40 output Input P32/INTP2
TMI40 Input External count clock input to timer 40 Input P31/INTP1/TO30
S0 to S23 Output LCD controller/driver segment signal output Output low
level
•−•
COM0 to COM3 Output LCD controller/driver common signal output Output low
level
−
VLC0 to VLC2 − LCD driving voltage − •−•
CAPH − − •−•
CAPL −
Capacitor connection pin for LCD drive
− •−•
X1 Input − •−•
X2 −
Connecting crystal resonator for main system clock oscillation
− •−•
XT1 Input − •−•
XT2 −
Connecting crystal resonator for subsystem clock oscillation
− •−•
RESET Input System reset input Input •−•
VDD − Positive power supply − •−•
VSS − Ground potential − •−•
IC − Internally connected. Connect directly to VSS. − •−•
VPP − Sets flash memory programming mode. Applies high voltage
when a program is written or verified.
− •−•
CHAPTER 3 PIN FUNCTIONS (
µ
PD789306 SUBSERIES)
User’s Manual U14800EJ3V0UD
38
3.2 Description of Pin Functions
3.2.1 P00 to P03 (Port 0)
These pins constitute a 4-bit I/O port. In addition, these pins enable key return signal detection.
Port 0 can be specified in the following operation modes in 1-bit units.
(1) Port mode
These pins constitute a 4-bit I/O port and can be set in the input or output port mode in 1-bit units by port
mode register 0 (PM0). When used as an input port, use of an on-chip pull-up resistor can be specified by
pull-up resistor option register 0 (PU0) in port units.
(2) Control mode
In this mode, P00 to P03 function as key return signal detection pins (KR0 to KR3).
3.2.2 P10 to P13 (Port 1)
These pins constitute a 4-bit I/O port and can be set in the input or output port mode in 1-bit units by port mode
register 1 (PM1). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor
option register 0 (PU0) in port units.
3.2.3 P20 to P26 (Port 2)
These pins constitute a 7-bit I/O port. In addition, these pins enable timer output, serial interface data I/O, and
clock I/O.
Port 2 can be specified in the following operation modes in 1-bit units.
(1) Port mode
In this mode, P20 to P26 function as a 7-bit I/O port. Port 2 can be set in the input or output port mode in 1-
bit units by port mode register 2 (PM2). When used as an input port, use of an on-chip pull-up resistor can
be specified by pull-up resistor option register B2 (PUB2) in 1-bit units.
(2) Control mode
In this mode, P20 to P26 function as the timer output, serial interface data I/O, and clock I/O.
(a) TO20
This is the timer output pin of 16-bit timer 20.
(b) SI10, SI20, SO10, SO20
These are the serial data I/O pins of the serial interface.
(c) SCK10, SCK20
These are the serial clock I/O pins of the serial interface.
(d) RxD20, TxD20
These are the serial data I/O pins of the asynchronous serial interface.
(e) ASCK20
This is the serial clock input pin of the asynchronous serial interface.
CHAPTER 3 PIN FUNCTIONS (
µ
PD789306 SUBSERIES)
User’s Manual U14800EJ3V0UD 39
Caution When using P20 to P26 as serial interface pins, the I/O mode and output latch must be set
according to the functions to be used. For the details of the setting, refer to Table 13-2 Settings
of Serial Interface 10 Operating Mode and Table 14-2 Settings of Serial Interface 20 Operating
Mode.
3.2.4 P30 to P33 (Port 3)
These pins constitute a 4-bit I/O port. In addition, they also function as timer I/O and external interrupt input.
Port 3 can be specified in the following operation mode in 1-bit units.
(1) Port mode
In this mode, port 3 functions as a 4-bit I/O port. Port 3 can be set in the input or output port mode in 1-bit
units by port mode register 3 (PM3). When used as an input port, use of an on-chip pull-up resistor can be
specified by pull-up resistor option register B3 (PUB3) in 1-bit units.
(2) Control mode
In this mode, the pins function as timer I/O and external interrupt input.
(a) TMI40
This is the external clock input pin to timer 40.
(b) TO30, TO40
These are the timer output pins of timer 30 and timer 40
(c) INTP0 to INTP3
These are external interrupt input pins for which valid edges (rising edge, falling edge, or both rising and
falling edges) can be specified.
3.2.5 P50 to P53 (Port 5)
These pins function as a 4-bit N-ch open-drain I/O port. Port 5 can be set in the input or output port mode in 1-bit
units by port mode register 5 (PM5). In the mask ROM version, use of an on-chip pull-up resistor can be specified by
a mask option.
3.2.6 S0 to S23
These pins are segment signal output pins for the LCD controller/driver.
3.2.7 COM0 to COM3
These pins are common signal output pins for the LCD controller/driver.
3.2.8 VLC0 to VLC2
These pins are power supply voltage pins to drive the LCD.
3.2.9 CAPH, CAPL
These pins are capacitor connection pins to drive the LCD.
CHAPTER 3 PIN FUNCTIONS (
µ
PD789306 SUBSERIES)
User’s Manual U14800EJ3V0UD
40
3.2.10 RESET
This pin inputs an active-low system reset signal.
3.2.11 X1, X2
These pins are used to connect a crystal resonator for main system clock oscillation.
To supply an external clock, input the clock to X1 and input the inverted signal to X2.
3.2.12 XT1, XT2
These pins are used to connect a crystal resonator for subsystem clock oscillation.
To supply an external clock, input the clock to XT1 and input the inverted signal to XT2.
3.2.13 VDD
This is the positive power supply pin.
3.2.14 VSS
This is the ground pin.
3.2.15 VPP (
µ
PD78F9306 only)
A high voltage should be applied to this pin when the flash memory programming mode is set and when the
program is written or verified.
Handle the pins in either of the following ways.
• Independently connect a 10 kΩ pull-down resistor.
• Switch this pin to be directly connected to the dedicated flash programmer in programming mode or to VSS in
normal operation mode using a jumper on the board.
If the wiring between the VPP pin and VSS pin is long, or external noise is superimposed on the VPP pin, the user
program may not run correctly.
3.2.16 IC (mask ROM version only)
The IC (Internally Connected) pin is used to set the
µ
PD789304 and
µ
PD789306 in the test mode before
shipment. In the normal operation mode, directly connect this pin to the VSS pin with as short a wiring length as
possible.
If a potential difference is generated between the IC pin and VSS pin due to a long wiring length, or an external
noise superimposed on the IC pin, the user program may not run correctly.
• Directly connect the IC pin to the VSS pin.
VSS IC
Keep short
CHAPTER 3 PIN FUNCTIONS (
µ
PD789306 SUBSERIES)
User’s Manual U14800EJ3V0UD 41
3.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.
For the input/output circuit configuration of each type, see Figure 3-1.
Table 3-1. Types of Pin Input/Output Circuits
Pin Name I/O Circuit
Type
I/O Recommended Connection of Unused Pins
P00/KR0 to P03/KR3 8-A
P10 to P13 5-A
P20/SCK10
P21/SO10
P22/SI10
P23/SCK20/ASCK20
P24/SO20/TxD20
P25/SI20/RxD20
P26/TO20
Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P30/INPT0/CPT20
P31/INPT1/TO30/TMI40
P32/INPT2/TO40
P33/INPT3
8-A
Input: Independently connect to VSS via a resistor.
Output: Leave open.
P50 to P53
(Mask ROM version)
13-W
P50 to P53 (
µ
PD78F9306) 13-V
I/O
Input: Independently connect to VSS via a resistor.
Output: Leave this pin open at low-level output after clearing the output
latch of the port to 0.
S0 to S23 17
COM0 to COM3 18
Output
VLC0 to VLC2 −
CAPH, CAPL −
•−•
Leave open.
XT1 Input Connect to VSS.
XT2
−
− Leave open.
RESET 2 Input −
IC (Mask ROM version) Connect directly to VSS.
VPP (
µ
PD78F9306)
− •−•
Independently connect to a 10 kΩ pull-down resistor or connect directly
to VSS.
CHAPTER 3 PIN FUNCTIONS (
µ
PD789306 SUBSERIES)
User’s Manual U14800EJ3V0UD
42
Figure 3-1. Pin Input/Output Circuits
Type 2 Type 13-W
Schmitt-triggered input with hysteresis characteristics
IN
V
SS
Output data
Output disable
IN/OUT
V
DD
N-ch
Middle-voltage
input buffer
Input enable
Pull-up resistor
(mask option)
Type 5-A Type 17
Pull-up
enable
Data
Output
disable
Input
enable
VDD
P-ch
VDD
P-ch
IN/OUT
N-ch
VSS
P-ch
P-ch
V
LC0
V
LC1
N-ch
P-ch
N-ch
V
LC2
SEG
data
P-ch
OUT
N-ch
N-ch
Type 8-A Type 18
Pull-up
enable
Data
Output
disable
V
DD
P-ch
V
DD
P-ch
IN/OUT
N-ch
V
SS
COM
data
OUT
P-ch
P-ch
V
LC0
V
LC1
N-ch
V
LC2
P-ch
N-ch
N-ch
P-ch
N-ch
N-ch
P-ch
Type 13-V
VSS
Output data
Output disable
IN/OUT
N-ch
Middle-voltage
input buffer
Input enable
User’s Manual U14800EJ3V0UD 43
CHAPTER 4 PIN FUNCTIONS (
µ
PD789316 SUBSERIES)
4.1 List of Pin Functions
(1) Port pins
Pin Name I/O Function After Reset Alternate Function
P00 to P03 I/O Port 0.
4-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be
specified by means of pull-up resistor option register 0 (PU0) or
key return mode register 00 (KRM00) in port units.
Input KR0 to KR3
P10 to P13 I/O Port 1.
4-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be
specified by means of pull-up resistor option register 0 (PU0) in
port units.
Input –
P20 SCK10
P21 SO10
P22 SI10
P23 SCK20/ASCK20
P24 SO20/TxD20
P25 SI20/RxD20
P26
I/O Port 2.
7-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be
specified by means of pull-up resistor option register B2 (PUB2)
in 1-bit units.
Input
TO20
P30 INTP0/CPT20
P31 INTP1/TO30/
TMI40
P32 INTP2/TO40
P33
I/O Port 3.
4-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be
specified by means of pull-up resistor option register B3 (PUB3).
Input
INTP3
P50 to P53 I/O Port 5.
4-bit N-ch open-drain I/O port.
Input/output can be specified in 1-bit units.
For a mask ROM version, an on-chip pull-up resistor can be
specified by the mask option in 1-bit units.
Input −
CHAPTER 4 PIN FUNCTIONS (
µ
PD789316 SUBSERIES)
User’s Manual U14800EJ3V0UD
44
(2) Non-port pins
Pin Name I/O Function After Reset Alternate Function
INTP0 P30/CPT20
INTP1 P31/TO30/TMI40
INTP2 P32/TO40
INTP3
Input External interrupt input for which the valid edge (rising edge,
falling edge, or both rising and falling edges) can be specified
Input
P33
KR0 to KR3 Input Key return signal detection Input P00 to P03
SCK10 Serial interface 10 serial clock input/output P20
SCK20
I/O
Serial interface 20 serial clock input/output
Input
P23/ASCK20
SI10 Serial interface 10 serial data input P22
SI20
Input
Serial interface 20 serial data input
Input
P25/RxD20
SO10 Serial interface 10 serial data output P21
SO20
Output
Serial interface 20 serial data output
Input
P24/TxD20
ASCK20 Input Serial clock input for asynchronous serial interface Input P23/SCK20
RxD20 Input Serial data input for asynchronous serial interface Input P25/SI20
TxD20 Output Serial data output for asynchronous serial interface Input P24/SO20
TO20 Output 16-bit timer 20 output Input P26
CPT20 Input Capture edge input Input P30/INTP0
TO30 Output Timer 30 output Input P31/INTP1/TMI40
TO40 Output Timer 40 output Input P32/INTP2
TMI40 Input External count clock input to timer 40 Input P31/INTP1/TO30
S0 to S23 Output LCD controller/driver segment signal output Output low
level
•−•
COM0 to COM3 Output LCD controller/driver common signal output Output low
level
−
VLC0 to VLC2 − LCD driving voltage − •−•
CAPH − − •−•
CAPL −
Capacitor connection pin for LCD drive
− •−•
CL1 Input − •−•
CL2 −
Connecting resistor (R) and capacitor (C) for main system clock
oscillation − •−•
XT1 Input − •−•
XT2 −
Connecting crystal resonator for subsystem clock oscillation
− •−•
RESET Input System reset input Input •−•
VDD − Positive power supply − •−•
VSS − Ground potential − •−•
IC − Internally connected. Connect directly to VSS. − •−•
VPP − Sets flash memory programming mode. Applies high voltage
when a program is written or verified.
− •−•
CHAPTER 4 PIN FUNCTIONS (
µ
PD789316 SUBSERIES)
User’s Manual U14800EJ3V0UD 45
4.2 Description of Pin Functions
4.2.1 P00 to P03 (Port 0)
These pins constitute a 4-bit I/O port. In addition, these pins enable key return signal detection.
Port 0 can be specified in the following operation modes in 1-bit units.
(1) Port mode
These pins constitute a 4-bit I/O port and can be set in the input or output port mode in 1-bit units by port
mode register 0 (PM0). When used as an input port, use of an on-chip pull-up resistor can be specified by
pull-up resistor option register 0 (PU0) in port units.
(2) Control mode
In this mode, P00 to P03 function as key return signal detection pins (KR0 to KR3). These pins constitute a
4-bit I/O port and can be set in the input or output port mode in 1-bit units by port mode register 0 (PM0).
When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option
register 0 (PU0).
4.2.2 P10 to P13 (Port 1)
These pins constitute a 4-bit I/O port and can be set in the input or output port mode in 1-bit units by port mode
register 1 (PM1). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor
option register 0 (PU0) in port units.
4.2.3 P20 to P26 (Port 2)
These pins constitute a 7-bit I/O port. In addition, these pins enable timer output, serial interface data I/O, and
clock I/O.
Port 2 can be specified in the following operation modes in 1-bit units.
(1) Port mode
In this mode, P20 to P26 function as a 7-bit I/O port. Port 2 can be set in the input or output port mode in 1-
bit units by port mode register 2 (PM2). When used as an input port, use of an on-chip pull-up resistor can
be specified by pull-up resistor option register B2 (PUB2) in 1-bit units.
(2) Control mode
In this mode, P20 to P26 function as the timer output, serial interface data I/O, and clock I/O.
(a) TO20
This is the timer output pin of 16-bit timer 20.
(b) SI10, SI20, SO10, SO20
These are the serial data I/O pins of the serial interface.
(c) SCK10, SCK20
These are the serial clock I/O pins of the serial interface.
(d) RxD20, TxD20
These are the serial data I/O pins of the asynchronous serial interface.
CHAPTER 4 PIN FUNCTIONS (
µ
PD789316 SUBSERIES)
User’s Manual U14800EJ3V0UD
46
(e) ASCK20
This is the serial clock input pin of the asynchronous serial interface.
Caution When using P20 to P26 as serial interface pins, the I/O mode and output latch must be set
according to the functions to be used. For the details of the setting, refer to Table 13-2 Settings
of Serial Interface 10 Operating Mode and Table 14-2 Settings of Serial Interface 20 Operating
Mode.
4.2.4 P30 to P33 (Port 3)
These pins constitute a 4-bit I/O port. In addition, they also function as timer I/O and external interrupt input.
Port 3 can be specified in the following operation modes in 1-bit units.
(1) Port mode
In this mode, port 3 functions as a 4-bit I/O port. Port 3 can be set in the input or output port mode in 1-bit
units by port mode register 3 (PM3). When used as an input port, use of an on-chip pull-up resistor can be
specified by pull-up resistor option register B3 (PUB3) in 1-bit units.
(2) Control mode
In this mode, the pins function as timer I/O and external interrupt input.
(a) TMI40
This is the external clock input pin to timer 40.
(b) TO30, TO40
These are the timer output pins of timer 30 and timer 40
(c) CPT20
This is the capture edge input pin for 16-bit timer 20.
(d) INTP0 to INTP3
These are external interrupt input pins for which valid edges (rising edge, falling edge, or both rising and
falling edges) can be specified.
4.2.5 P50 to P53 (Port 5)
These pins function as a 4-bit N-ch open-drain I/O port. Port 5 can be set in the input or output port mode in 1-bit
units by port mode register 5 (PM5). In the mask ROM version, use of an on-chip pull-up resistor can be specified by
a mask option.
4.2.6 S0 to S23
These pins are segment signal output pins for the LCD controller/driver.
4.2.7 COM0 to COM3
These pins are common signal output pins for the LCD controller/driver.
4.2.8 VLC0 to VLC2
These pins are power supply voltage pins to drive the LCD.
CHAPTER 4 PIN FUNCTIONS (
µ
PD789316 SUBSERIES)
User’s Manual U14800EJ3V0UD 47
4.2.9 CAPH, CAPL
These pins are capacitor connection pins to drive the LCD.
4.2.10 RESET
This pin inputs an active-low system reset signal.
4.2.11 CL1, CL2
These pins are used to connect a resistor (R) and capacitor (C) for main system clock oscillation.
To supply an external clock, input the clock to CL1 and input the inverted signal to CL2.
4.2.12 XT1, XT2
These pins are used to connect a crystal resonator for subsystem clock oscillation.
To supply an external clock, input the clock to XT1 and input the inverted signal to XT2.
4.2.13 VDD
This is the positive power supply pin.
4.2.14 VSS
This is the ground pin.
4.2.15 VPP (
µ
PD78F9316 only)
A high voltage should be applied to this pin when the flash memory programming mode is set and when the
program is written or verified.
Handle the pins in either of the following ways.
• Independently connect a 10 kΩ pull-down resistor.
• Switch this pin to be directly connected to the dedicated flash programmer in programming mode or to VSS in
normal operation mode using a jumper on the board.
If the wiring between the VPP pin and VSS pin is long, or external noise is superimposed on the VPP pin, the user
program may not run correctly.
CHAPTER 4 PIN FUNCTIONS (
µ
PD789316 SUBSERIES)
User’s Manual U14800EJ3V0UD
48
4.2.16 IC (mask ROM version only)
The IC (Internally Connected) pin is used to set the
µ
PD789314 and
µ
PD789316 in the test mode before
shipment. In the normal operation mode, directly connect this pin to the VSS pin with as short a wiring length as
possible.
If a potential difference is generated between the IC pin and VSS pin due to a long wiring length, or an external
noise superimposed on the IC pin, the user program may not run correctly.
• Directly connect the IC pin to the VSS pin.
VSS IC
Keep short
CHAPTER 4 PIN FUNCTIONS (
µ
PD789316 SUBSERIES)
User’s Manual U14800EJ3V0UD 49
4.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 4-1.
For the input/output circuit configuration of each type, see Figure 4-1.
Table 4-1. Types of Pin Input/Output Circuits
Pin Name I/O Circuit
Type
I/O Recommended Connection of Unused Pins
P00/KR0 to P03/KR3 8-A
P10 to P13 5-A
P20/SCK10
P21/SO10
P22/SI10
P23/SCK20/ASCK20
P24/SO20/TxD20
P25/SI20/RxD20
P26/TO20
Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P30/INTP0/CPT20
P31/INTP1/TO30/TMI40
P32/INTP2/TO40
P33/INTP3
8-A
Input: Independently connect to VSS via a resistor.
Output: Leave open.
P50 to P53
(Mask ROM version)
13-W
P50 to P53 (
µ
PD78F9316) 13-V
I/O
Input: Independently connect to VSS via a resistor.
Output: Leave this pin open at low-level output after clearing the output
latch of the port to 0.
S0 to S23 17
COM0 to COM3 18
Output
VLC0 to VLC2 −
CAPH, CAPL −
•−•
Leave open.
XT1 Input Connect to VSS.
XT2
−
− Leave open.
RESET 2 Input −
IC (Mask ROM version) Connect directly to VSS.
VPP (
µ
PD78F9316)
− •−•
Independently connect to a 10 kΩ pull-down resistor or connect directly
to VSS.
CHAPTER 4 PIN FUNCTIONS (
µ
PD789316 SUBSERIES)
User’s Manual U14800EJ3V0UD
50
Figure 4-1. Pin Input/Output Circuits
Type 2 Type 13-W
Schmitt-triggered input with hysteresis characteristics
IN
V
SS
Output data
Output disable
IN/OUT
V
DD
N-ch
Middle-voltage
input buffer
Input enable
Pull-up resistor
(mask option)
Type 5-A Type 17
Pull-up
enable
Data
Output
disable
Input
enable
VDD
P-ch
VDD
P-ch
IN/OUT
N-ch
VSS
P-ch
P-ch
V
LC0
V
LC1
N-ch
P-ch
N-ch
V
LC2
SEG
data
P-ch
OUT
N-ch
N-ch
Type 8-A Type 18
Pull-up
enable
Data
Output
disable
V
DD
P-ch
V
DD
P-ch
IN/OUT
N-ch
V
SS
COM
data
OUT
P-ch
P-ch
V
LC0
V
LC1
N-ch
V
LC2
P-ch
N-ch
N-ch
P-ch
N-ch
N-ch
P-ch
Type 13-V
VSS
Output data
Output disable
IN/OUT
N-ch
Middle-voltage
input buffer
Input enable
User’s Manual U14800EJ3V0UD 51
CHAPTER 5 CPU ARCHITECTURE
5.1 Memory Space
The
µ
PD789306 and
µ
PD789316 Subseries can access 64 KB of memory space. Figures 5-1 through 5-3 show
the memory maps.
Figure 5-1. Memory Map (
µ
PD789304, 789314)
Special function registers
256 × 8 bits
Internal high-speed RAM
512 × 8 bits
LCD display RAM
24 × 4 bits
Reserved
Reserved
Internal ROM
8192 × 8 bits
FFFFH
FF00H
FEFFH
FD00H
FCFFH
FA00H
F9FFH
0000H
Program
memory space
Data
memory space
1FFFH
0000H
Program area
0080H
007FH
Program area
0040H
003FH
CALLT table area
0022H
0021H
Vector table area
FA18H
FA17H
2000H
1FFFH
CHAPTER 5 CPU ARCHITECTURE
User’s Manual U14800EJ3V0UD
52
Figure 5-2. Memory Map (
µ
PD789306, 789316)
Special function registers
256 × 8 bits
Internal high-speed RAM
512 × 8 bits
Internal ROM
16384 × 8 bits
FFFFH
FF00H
FEFFH
0000H
Program
memory space
Data
memory space
3FFFH
0000H
Program area
0080H
007FH
Program area
0040H
003FH
CALLT table area
0022H
0021H
Vector table area
LCD display RAM
24 × 4 bits
Reserved
Reserved
FD00H
FCFFH
FA00H
F9FFH
FA18H
FA17H
4000H
3FFFH
CHAPTER 5 CPU ARCHITECTURE
User’s Manual U14800EJ3V0UD
53
Figure 5-3. Memory Map (
µ
PD78F9306, 78F9316)
Special function registers
256 × 8 bits
Internal high-speed RAM
512 × 8 bits
Internal flash memory
16384 × 8 bits
FFFFH
FF00H
FEFFH
0000H
Program
memory space
Data
memory space
3FFFH
0000H
Program area
0080H
007FH
Program area
0040H
003FH
CALLT table area
0022H
0021H
Vector table area
LCD display RAM
24 × 4 bits
Reserved
Reserved
FD00H
FCFFH
FA00H
F9FFH
FA18H
FA17H
4000H
3FFFH
CHAPTER 5 CPU ARCHITECTURE
User’s Manual U14800EJ3V0UD
54
5.1.1 Internal program memory space
The internal program memory space stores programs and table data. This space is usually addressed by the
program counter (PC).
The
µ
PD789306 and
µ
PD789316 Subseries provide internal ROM (or flash memory) with the following capacity for
each product.
Table 5-1. Internal ROM Capacity
Part Number Internal ROM
Structure Capacity
µ
PD789304, 789314 8192 × 8 bits
µ
PD789306, 789316
Mask ROM
16384 × 8 bits
µ
PD78F9306, 78F9316 Flash memory 16384 × 8 bits
The following areas are allocated to the internal program memory space.
(1) Vector table area
The 34-byte area of addresses 0000H to 0021H is reserved as a vector table area. This area stores program
start addresses to be used when branching by the RESET input or an interrupt request generation. Of a 16-
bit program address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an
odd address.
Table 5-2. Vector Table
(2) CALLT instruction table area
The subroutine entry address of a 1-byte call instruction (CALLT) can be stored in the 64-byte area of
addresses 0040H to 007FH.
Vector Table Address Interrupt Request Vector Table Address Interrupt Request
0000H RESET input 0012H INTST20
0004H INTWDT 0014H INTWTI
0006H INTP0 0016H INTTM20
0008H INTP1 0018H INTTM30
000AH INTP2 001AH INTTM40
000CH INTP3 001EH INTWT
000EH INTSR20/INTCSI20 0020H INTKR00
0010H INTCSI10
CHAPTER 5 CPU ARCHITECTURE
User’s Manual U14800EJ3V0UD
55
5.1.2 Internal data memory (internal high-speed RAM) space
The
µ
PD789306 and
µ
PD789316 Subseries products incorporate the following RAM.
(1) Internal high-speed RAM
Internal high-speed RAM is incorporated in the area between FD00H and FEFFH.
The internal high-speed RAM is also used as a stack.
(2) LCD display RAM
LCD display RAM is allocated in the area between FA00H and FA17H. The LCD display RAM can also be
used as ordinary RAM.
5.1.3 Special function register (SFR) area
Special function registers (SFRs) of on-chip peripheral hardware are allocated in the area between FF00H to
FFFFH (see Table 5-3).
CHAPTER 5 CPU ARCHITECTURE
User’s Manual U14800EJ3V0UD
56
5.1.4 Data memory addressing
The
µ
PD789306 and
µ
PD789316 Subseries are provided with a variety of addressing modes to make memory
manipulation as efficient as possible. At the addresses corresponding to data memory area (FD00H to FFFFH)
especially, specific addressing modes that correspond to the particular function an area, such as the special function
registers are available. Figures 5-4 through 5-6 show the data memory addressing modes.
Figure 5-4. Data Memory Addressing (
µ
PD789304, 789314)
Special function registers (SFRs)
256 × 8 bits
Internal high-speed RAM
512 × 8 bits
Internal ROM
8192 × 8 bits
FFFFH
0000H
Direct adressing
Register indirect
addressing
Based addressing
FF00H
FEFFH
FF20H
FF1FH
FE20H
FE1FH
SFR addressing
Short direct
addressing
LCD display RAM
24 × 4 bits
Reserved
Reserved
FD00H
FCFFH
FA00H
F9FFH
2000H
1FFFH
FA18H
FA17H
CHAPTER 5 CPU ARCHITECTURE
User’s Manual U14800EJ3V0UD
57
Figure 5-5. Data Memory Addressing (
µ
PD789306, 789316)
Special function registers (SFRs)
256 × 8 bits
Internal high-speed RAM
512 × 8 bits
Internal ROM
16384 × 8 bits
FFFFH
0000H
Direct addressing
Register indirect
addressing
Based addressing
FF00H
FEFFH
FF20H
FF1FH
FE20H
FE1FH
SFR addressing
Short direct
addressing
LCD display RAM
24 × 4 bits
Reserved
Reserved
FD00H
FCFFH
FA00H
F9FFH
4000H
3FFFH
FA18H
FA17H
CHAPTER 5 CPU ARCHITECTURE
User’s Manual U14800EJ3V0UD
58
Figure 5-6. Data Memory Addressing (
µ
PD78F9306, 78F9316)
Special function registers (SFRs)
256 × 8 bits
Internal high-speed RAM
512 × 8 bits
Internal flash memory
16384 × 8 bits
FFFFH
0000H
Direct addressing
Register indirect
addressing
Based addressing
FF00H
FEFFH
FF20H
FF1FH
FE20H
FE1FH
SFR addressing
Short direct
addressing
LCD display RAM
24 × 4 bits
Reserved
Reserved
FD00H
FCFFH
FA00H
F9FFH
4000H
3FFFH
FA18H
FA17H
CHAPTER 5 CPU ARCHITECTURE
User’s Manual U14800EJ3V0UD
59
5.2 Processor Registers
The
µ
PD789306 and
µ
PD789316 Subseries provide the following on-chip processor registers.
5.2.1 Control registers
The control registers contain special functions to control the program sequence statuses and stack memory. The
program counter, program status word, and stack pointer are control registers.
(1) Program counter (PC)
The program counter is a 16-bit register that holds the address information of the next program to be
executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction
to be fetched. When a branch instruction is executed, immediate data or register contents are set.
RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 5-7. Program Counter Configuration
015
PC14PC15PC PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags to be set/reset by instruction
execution.
The program status word contents are automatically stacked upon interrupt request generation or PUSH
PSW instruction execution and are automatically restored upon execution of the RETI and POP PSW
instructions.
RESET input sets PSW to 02H.
Figure 5-8. Program Status Word Configuration
70
IE Z 0 AC 0 0 1 CY
PSW
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(a) Interrupt enable flag (IE)
This flag controls interrupt request acknowledgement operations of the CPU.
When 0, IE is set to the interrupt disable status (DI), and interrupt requests other than non-maskable
interrupt are all disabled.
When 1, IE is set to the interrupt enable status (EI). Interrupt request acknowledgement enable is
controlled with an interrupt mask flag for various interrupt sources.
IE is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI
instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
(c) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all
other cases.
(d) Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out
value upon rotate instruction execution and functions as a bit accumulator during bit manipulation
instruction execution.
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(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed
RAM area can be set as the stack area.
Figure 5-9. Stack Pointer Configuration
015
SP14SP15SP SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore)
from the stack memory.
Each stack operation saves/restores data as shown in Figures 5-10 and 5-11.
Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before
instruction execution.
Figure 5-10. Data to Be Saved to Stack Memory
Interrupt
PSW
PC15 to PC8
PC15 to PC8
PC7 to PC0
Lower
register pairs
SP SP _ 2
SP _ 2
CALL, CALLT
instructions
PUSH rp
instruction
SP _ 1
SP
SP SP _ 2
SP _ 2
SP _ 1
SP
PC7 to PC0
SP _ 3
SP _ 2
SP _ 1
SP
SP SP _ 3
Higher
register pairs
Figure 5-11. Data to Be Restored from Stack Memory
RETI instruction
PSW
PC15 to PC8
PC15 to PC8
PC7 to PC0
Lower
register pairs
RET instructionPOP rp
instruction
SP PC7 to PC0
Higher
register pairs
SP + 1
SP SP + 2
SP
SP + 1
SP SP + 2
SP
SP + 1
SP + 2
SP SP + 3
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5.2.2 General-purpose registers
The general-purpose registers consist of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can be used as an 8-bit register, or two 8-bit registers in pairs can be used as a 16-bit register (AX,
BC, DE, and HL).
General-purpose registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, or HL)
or absolute names (R0 to R7 and RP0 to RP3).
Figure 5-12. General-Purpose Register Configuration
(a) Absolute names
R0
15 0 7 0
16-bit processing 8-bit processing
RP3
RP2
RP1
RP0
R1
R2
R3
R4
R5
R6
R7
(b) Function names
X
15 0 7 0
16-bit processing 8-bit processing
HL
DE
BC
AX
A
C
B
E
D
L
H
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5.2.3 Special function registers (SFRs)
Unlike a general-purpose register, each special function register has a special function.
The special function registers are allocated in the 256-byte area of FF00H to FFFFH.
Special function registers can be manipulated, like general-purpose registers, by operation, transfer, and bit
manipulation instructions. The manipulatable bit units (1, 8, and 16) differ depending on the special function register
type.
The manipulatable bits can be specified as follows.
• 1-bit manipulation
Describes a symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This
manipulation can also be specified with an address.
• 8-bit manipulation
Describes a symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This
manipulation can also be specified with an address.
• 16-bit manipulation
Describes a symbol reserved by the assembler for the 16-bit manipulation instruction operand. When
addressing an address, describe an even address.
Table 5-3 lists the special function registers. The meanings of the symbols in this table are as follows:
• Symbol
Indicates the addresses of the implemented special function registers. The symbols are reserved for the
assembler and are defined as an sfr variable by the #pragma sfr directive for the C compiler. Therefore, these
symbols can be used as instruction operands if an assembler or integrated debugger is used.
• R/W
Indicates whether the special function register in question can be read or written.
R/W: Read/write
R: Read only
W: Write only
• Bit manipulation unit
Indicates the bit units (1, 8, 16) in which the special function register in question can be manipulated.
• After reset
Indicates the status of the special function register when the RESET signal is input.
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Table 5-3. Special Function Register List (1/2)
Bit Manipulation Unit Address Special Function Register (SFR) Name Symbol R/W
1 Bit 8 Bits 16 Bits
After Reset
FF00H Port 0 P0 √ √ −
FF01H Port 1 P1 √ √ −
FF02H Port 2 P2 √ √ −
FF03H Port 3 P3 √ √ −
FF05H Port 5 P5
R/W
√ √ −
00H
FF0CH 8-bit compare register 40 CR40 − √
FF0DH 8-bit compare register 30 CR30
CR4
Note1
W
− √
√Notes 2, 3 Undefined
FF0EH 8-bit timer counter 40 TM40 − √
FF0FH 8-bit timer counter 30 TM30
TM4
Note1
R
− √
√Notes 2, 3 00H
FF10H Transmit shift register 20 TXS20 W − √ − FFH
Receive buffer register 20 RXB20
SIO20
R − √ −
FF11H Serial shift register 10 SIO10 R/W − √ −
Undefined
FF16H
FF17H
16-bit compare register 20 CR20Note 1 W
− − √Notes 2, 3 FFFFH
FF18H
FF19H
16-bit timer counter 20 TM20Note 1 − − √Notes 2, 3 0000H
FF1AH 16-bit capture register 20
FF1BH
TCP20Note 1
R
− − √Notes 2, 3 Undefined
FF20H Port mode register 0 PM0 √ √ −
FF21H Port mode register 1 PM1 √ √ −
FF22H Port mode register 2 PM2 √ √ −
FF23H Port mode register 3 PM3 √ √ −
FF25H Port mode register 5 PM5 √ √ −
FFH
FF32H Pull-up resistor option register B2 PUB2 √ √ −
FF33H Pull-up resistor option register B3 PUB3 √ √ −
FF42H Watchdog timer clock select register WDCS − √ −
FF48H 16-bit timer mode control register 20 TMC20 √ √ −
FF4AH Watch timer mode control register WTM
R/W
√ √ −
00H
FF4CH 8-bit compare register H40 CRH40 W − √ − Undefined
Notes 1. Name of SFR dedicated for 16-bit access.
2. Only in short direct addressing, 16-bit access is possible.
3. These are 16-bit access dedicated registers, however, 8-bit access is possible. When performing 8-bit
access, access using direct addressing.
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Table 5-3. Special Function Register List (2/2)
Bit Manipulation Unit Address Special Function Register (SFR) Name Symbol R/W
1 Bit 8 Bits 16 Bits
After Reset
FF4DH 8-bit timer mode control register 30 TMC30 √ √ −
FF4EH 8-bit timer mode control register 40 TMC40
R/W
√ √ −
FF4FH Carrier generator output control register 40 TCA40 W − √ −
FF70H Asynchronous serial interface mode register 20 ASIM20 R/W √ √ −
FF71H Asynchronous serial interface status register 20 ASIS20 R √ √ −
FF72H Serial operation mode register 20 CSIM20 √ √ −
FF73H Baud rate generator control register 20 BRGC20 − √ −
FF78H Serial operation mode register 10 CSIM10 √ √ −
FFB0H LCD display mode register 0 LCDM0 √ √ −
FFB2H LCD clock control register 0 LCDC0 √ √ −
FFB3H LCD voltage amplification control register 0 LCDVA0 √ √ −
FFE0H Interrupt request flag register 0 IF0 √ √ −
FFE1H Interrupt request flag register 1 IF1 √ √ −
00H
FFE4H Interrupt mask flag register 0 MK0 √ √ −
FFE5H Interrupt mask flag register 1 MK1 √ √ −
FFH
FFECH External interrupt mode register 0 INTM0 − √ −
FFEDH External interrupt mode register 1 INTM1 − √ −
FFF0H Suboscillation mode register SCKM √ √ −
FFF2H Subclock control register CSS √ √ −
FFF5H Key return mode register 00 KRM00 √ √ −
FFF7H Pull-up resistor option register 0 PU0 √ √ −
FFF9H Watchdog timer mode register WDTM √ √ −
00H
FFFAH Oscillation stabilization time select registerNote OSTS − √ − 04H
FFFBH Processor clock control register PCC
R/W
√ √ − 02H
Note
µ
PD789306 Subseries only.
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5.3 Instruction Address Addressing
An instruction address is determined by the program counter (PC) contents. The PC contents are normally
incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each
time another instruction is executed. When a branch instruction is executed, the branch destination information is set
to the PC and branched by the following addressing (for details of each instruction, refer to 78K/0S Series
Instructions User’s Manual (U11047E)).
5.3.1 Relative addressing
[Function]
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the
start address of the following instruction is transferred to the program counter (PC) and branched. The
displacement value is treated as signed two’s complement data (–128 to +127) and bit 7 becomes a sign bit.
This means that information is relatively branched to a location between –128 and +127, from the start address
of the next instruction when relative addressing is used.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.
[Illustration]
15 0
PC
15 0
S
15 0
PC
+
876
α
jdisp8
When S = 0, α indicates all bits 0.
... PC is the start address of
the next instruction of
a BR instruction.
When S = 1, α indicates all bits 1.
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5.3.2 Immediate addressing
[Function]
Immediate data in the instruction word is transferred to the program counter (PC) and branched.
This function is carried out when the CALL !addr16 or BR !addr16 instruction is executed.
CALL !addr16 and BR !addr16 instructions can be branched to any location in the memory space.
[Illustration]
In case of CALL !addr16 and BR !addr16 instructions
15 0
PC
87
70
CALL or BR
Low Addr.
High Addr.
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5.3.3 Table indirect addressing
[Function]
Table contents (branch destination address) of the particular location to be addressed by the lower 5-bit
immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and
branched.
This function is carried out when the CALLT [addr5] instruction is executed. The instruction enables a branch
to any location in the memory space by referring to the addresses stored in the memory table at 40H to 7FH.
[Illustration]
15 1
15 0
PC
70
Low Addr.
High Addr.
Memory (Table)
Effective address + 1
Effective address 01
00000000
87
87
65 0
0
001
765 10
ta4–0
Instruction code
5.3.4 Register addressing
[Function]
The register pair (AX) contents to be specified with an instruction word are transferred to the program counter
(PC) and branched.
This function is carried out when the BR AX instruction is executed.
[Illustration]
70
rp
07
AX
15 0
PC
87
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5.4 Operand Address Addressing
The following various methods are available to specify the register and memory (addressing) which undergo
manipulation during instruction execution.
5.4.1 Direct addressing
[Function]
The memory indicated with immediate data in an instruction word is directly addressed.
[Operand format]
Identifier Description
addr16 Label or 16-bit immediate data
[Description example]
MOV A, !FE00H; When setting !addr16 to FE00H
Instruction code 00101001OP code
00000000
11111110
00H
FEH
[Illustration]
70
OP code
addr16 (Lower)
addr16 (Higher)
Memory
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5.4.2 Short direct addressing
[Function]
The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.
The fixed space is the 256-byte space FE20H to FF1FH where the addressing is applied. Internal high-speed
RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH,
respectively.
The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the whole SFR area.
Ports that are frequently accessed in a program and the compare register of the timer/event counter are
mapped in this area, and these SFRs can be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH,
bit 8 is set to 1. See [Illustration] below.
[Operand format]
Identifier Description
saddr Label or FE20H to FF1FH immediate data
saddrp Label or FE20H to FF1FH immediate data (even address only)
[Description example]
MOV FE90H, #50H; When setting saddr to FE90H and the immediate data to 50H
Instruction code 1 1110101
10010000
01010000
OP code
90H (saddr-offset)
50H (Immediate data)
[Illustration]
15 0
Short direct memory
Effective
address 1111111
8
07
OP code
saddr-offset
α
When 8-bit immediate data is 20H to FFH, α = 0.
When 8-bit immediate data is 00H to 1FH, α = 1.
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5.4.3 Special function register (SFR) addressing
[Function]
The memory-mapped special function registers (SFRs) are addressed with 8-bit immediate data in an
instruction word.
This addressing is applied to the 256-byte space FF00H to FFFFH. However, the SFRs mapped at FF00H to
FF1FH can also be accessed with short direct addressing.
[Operand format]
Identifier Description
sfr Special function register name
[Description example]
MOV PM0, A; When selecting PM0 for sfr
Instruction code 11100111
00100000
[Illustration]
15 0
SFR
Effective
Address 1111111
87
07
OP code
sfr-offset
1
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5.4.4 Register addressing
[Function]
In the register addressing mode, general-purpose registers are accessed as operands. The general-purpose
register to be accessed is specified by a register specification code or functional name in the instruction code.
Register addressing is carried out when an instruction with the following operand format is executed. When an
8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.
[Operand format]
Identifier Description
r X, A, C, B, E, D, L, H
rp AX, BC, DE, HL
r and rp can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C,
B, E, D, L, H, AX, BC, DE, and HL).
[Description example]
MOV A, C; When selecting the C register for r
Instruction code 0 0001010
00100101
Register specification code
INCW DE; When selecting the DE register pair for rp
Instruction code 10001000
Register specification code
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5.4.5 Register indirect addressing
[Function]
In the register indirect addressing mode, memory is manipulated according to the contents of a register pair
specified as an operand. The register pair to be accessed is specified by the register pair specification code in
an instruction code.
This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier Description
− [DE], [HL]
[Description example]
MOV A, [DE]; When selecting register pair [DE]
Instruction code 00101011
[Illustration]
15 08
D
7
E
07
7 0
A
DE
Addressed memory
contents are
transferred.
Memory address
specified with
register pair DE.
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5.4.6 Based addressing
[Function]
8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is
used to address the memory. Addition is performed by expanding the offset data as a positive number to 16
bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier Description
− [HL+byte]
[Description example]
MOV A, [HL+10H]; When setting byte to 10H
Instruction code 00101101
00010000
5.4.7 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing method is automatically employed when the PUSH, POP, subroutine call, and return
instructions are executed or the register is saved/restored upon generation of an interrupt request.
Only the internal high-speed RAM area can be addressed using stack addressing.
[Description example]
In the case of PUSH DE
Instruction code 10101010
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CHAPTER 6 PORT FUNCTIONS
6.1 Port Functions
The
µ
PD789306 and
µ
PD789316 Subseries provide the ports shown in Figure 6-1, enabling various methods of
control.
Numerous other functions are provided that can be used in addition to the digital I/O port functions. For more
information on these additional functions, see CHAPTER 3 PIN FUNCTIONS (
µ
PD789306 SUBSERIES) and
CHAPTER 4 PIN FUNCTIONS (
µ
PD789316 SUBSERIES).
Figure 6-1. Port Types
P30
P33
P00
P03
P50
P53
P20
P26
Port 3
Port 5
Port 2
P10
P13
Port 1
Port 0
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Table 6-1. Port Functions
Pin Name I/O Function After Reset Alternate Function
P00 to P03 I/O Port 0.
4-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor
can be specified by means of pull-up resistor option
register 0 (PU0) or key return mode register 00
(KRM00) in port units.
Input KR0 to KR3
P10 to P13 I/O Port 1.
4-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor
can be specified by pull-up resistor option register 0
(PU0) in port units.
Input −
P20 SCK10
P21 SO10
P22 SI10
P23 SCK20/ASCK20
P24 SO20/TxD20
P25 SI20/RxD20
P26
I/O Port 2.
7-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor
can be specified by means of pull-up resistor option
register B2 (PUB2) in 1-bit units.
Input
TO20
P30 INTP0/CPT20
P31 INTP1/TO30/TMI40
P32 INTP2/TO40
P33
I/O Port 3.
4-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor
can be specified by means of pull-up resistor option
register B3 (PUB3) in 1-bit units.
Input
INTP3
P50 to P53 I/O Port 5.
4-bit N-ch open-drain I/O port.
Input/output can be specified in 1-bit units.
For a mask ROM version, an on-chip pull-up resistor
can be specified by a mask option in 1 bit units.
Input −
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6.2 Port Configuration
Ports have the following hardware configuration.
Table 6-2. Configuration of Port
Item Configuration
Control registers Port mode register (PMm: m = 0 to 3, 5)
Pull-up resistor option register 0 (PU0)
Pull-up resistor option register B2, B3 (PUB2, PUB3)
Ports Total: 23 (CMOS I/O: 19, N-ch open-drain I/O: 4)
Pull-up resistors • Mask ROM version
Total: 23 (software control: 19, mask option control: 4)
• Flash memory version
Total: 19 (software control only)
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6.2.1 Port 0
This is a 4-bit I/O port with an output latch. Port 0 can be specified in the input or output mode in 1-bit units by
using the port mode register 0 (PM0). When the P00 to P03 pins are used as input port pins, on-chip pull-up resistors
can be connected in 4-bit units by using pull-up resistor option register 0 (PU0).
Port 0 is set in the input mode when the RESET signal is input.
Figure 6-2 shows a block diagram of port 0.
Figure 6-2. Block Diagram of P00 to P03
WRKRM00
VDD
P00/KR0 to
P03/KR3
WRPUO
RD
WRPORT
WRPM
PU00
PM00 to PM03
KRM000
P-ch
Internal bus
Selector
Output latch
(P00 to P03)
Alternate function
KRM00: Key return mode register 00
PU0: Pull-up resistor option register 0
PM: Port mode register
RD: Port 0 read signal
WR: Port 0 write signal
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6.2.2 Port 1
This is a 4-bit I/O port with an output latch. Port 1 can be specified in the input or output mode in 1-bit units by
using port mode register 1 (PM1). When using the P10 to P13 pins as input port pins, on-chip pull-up resistors can be
connected in 4-bit units by using pull-up resistor option register 0 (PU0).
This port is set in the input mode when the RESET signal is input.
Figure 6-3 shows a block diagram of port 1.
Figure 6-3. Block Diagram of P10 to P13
WRPU0
RD
WRPORT
WRPM
PU01
PM10 to PM13
VDD
P-ch
P10 to P13
Internal bus
Selector
Output latch
(P10 to P13)
PU0: Pull-up resistor option register 0
PM: Port mode register
RD: Port 1 read signal
WR: Port 1 write signal
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6.2.3 Port 2
This is a 7-bit I/O port with an output latch. Port 2 can be specified in the input or output mode in 1-bit units by
using port mode register 2 (PM2). When using the P20 to P26 pins as input port pins, on-chip pull-up resistors can be
connected in 1-bit units by using pull-up resistor option register B2 (PUB2).
The port is also used as a data I/O and clock I/O to and from the serial interface and for timer output.
This port is set in the input mode when the RESET signal is input.
Figures 6-4 to 6-7 show block diagrams of port 2.
Caution When using the pins of port 2 as the serial interface pin, the I/O or output latch must be set
according to the function to be used. For how to set the latches, see Table 13-2 Settings of
Serial Interface 10 Operating Mode and Figure 14-2 Settings of Serial Interface 20 Operating
Mode.
Figure 6-4. Block Diagram of P20 and P23
Internal bus
VDD
P-ch
P20/SCK10,
P23/ASCK20/
SCK20
WRPUB2
RD
WRPORT
WRPM
PUB20, PUB23
Alternate
function
Output latch
(P20, P23)
PM20, PM23
Alternate
function
Selector
PUB2: Pull-up resistor option register B2
PM: Port mode register
RD: Port 2 read signal
WR: Port 2 write signal
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Figure 6-5. Block Diagram of P21 and P24
Internal bus
V
DD
P-ch
P21/SO10,
P24/SO20/TxD20
WR
PUB2
RD
WR
PORT
WR
PM
PUB21, PUB24
Output latch
(P21, P24)
PM21, PM24
Alternate
function
Selector
PUB2: Pull-up resistor option register B2
PM: Port mode register
RD: Port 2 read signal
WR: Port 2 write signal
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Figure 6-6. Block Diagram of P22 and P25
Internal bus
VDD
P-ch
P22/SI10,
P25/SI20/RxD20
WRPUB2
RD
WRPORT
WRPM
PUB22, PUB25
Alternate
function
Output latch
(P22, P25)
PM22, PM25
Selector
PUB2: Pull-up resistor option register B2
PM: Port mode register
RD: Port 2 read signal
WR: Port 2 write signal
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Figure 6-7. Block Diagram of P26
Internal bus
V
DD
P26/TO20
WR
PUB2
RD
WR
PORT
WR
PM
PUB26
Alternate
function
Output latch
(P26)
PM26
Selector
P-ch
PUB2: Pull-up resistor option register B2
PM: Port mode register
RD: Port 2 read signal
WR: Port 2 write signal
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6.2.4 Port 3
This is a 4-bit I/O port with an output latch. Port 3 can be specified in the input or output mode in 1-bit units by
using port mode register 3 (PM3). When using the P30 to P33 pins as input port pins, on-chip pull-up resistors can be
connected in 1-bit units by using pull-up resistor option register B3 (PUB3).
This port is also used as an external interrupt input, capture input, and timer I/O.
This port is set in the input mode when the RESET signal is input.
Figures 6-8 and 6-9 show block diagrams of port 3.
Figure 6-8. Block Diagram of P30 and P33
P30/INTP0/CPT20,
P33/INTP3
WR
PUB2
RD
WR
PORT
WR
PM
PUB30, PUB33
PM30, PM33
V
DD
P-ch
Internal bus
Alternate
function
Selector
Output latch
(P30, P33)
PUB3: Pull-up resistor option register B3
PM: Port mode register
RD: Port 3 read signal
WR: Port 3 write signal
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Figure 6-9. Block Diagram of P31 and P32
P31/INTP1/TO30/
TMI40,
P32/INTP2/TO40
WR
PUB2
RD
WR
PORT
WR
PM
PUB31, PUB32
PM31, PM32
V
DD
P-ch
Internal bus
Alternate
function
Selector
Output latch
(P31, P32)
Alternate
function
PUB3: Pull-up resistor option register B3
PM: Port mode register
RD: Port 3 read signal
WR: Port 3 write signal
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6.2.5 Port 5
This is a 4-bit N-ch open-drain I/O port with an output latch. Port 5 can be specified in the input or output mode in
1-bit units by using port mode register 5 (PM5). For a mask ROM version, use of an on-chip pull-up resistor can be
specified by a mask option.
This port is set in the input mode when the RESET signal is input.
Figure 6-10 shows a block diagram of port 5.
Figure 6-10. Block Diagram of P50 to P53
Internal bus
Selector
RD
PM50 to PM53
P50 to P53
N-ch
WR
PORT
Output latch
(P50 to P53)
WR
PM
V
DD
Mask option resistor
Mask ROM version only.
For flash memory version,
a pull-up resistor is not
incorporated.
PM: Port mode register
RD: Port 5 read signal
WR: Port 5 write signal
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6.3 Registers Controlling Port Function
The ports are controlled by the following two types of registers.
• Port mode registers (PM0 to PM3, PM5)
• Pull-up resistor option registers (PU0, PUB2, PUB3)
(1) Port mode registers (PM0 to PM3, PM5)
These registers are used to set port input/output in 1-bit units.
The port mode registers are independently set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets the registers to FFH.
When port pins are used as alternate-function pins, set the port mode register and output latch according to
Table 6-3.
Caution As port 3 has an alternate function as external interrupt input, when the port function
output mode is specified and the output level is changed, the interrupt request flag is set.
When the output mode is used, therefore, the interrupt mask flag should be preset to 1.
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Figure 6-11. Format of Port Mode Register
PMmn
0 Output mode (output buffer ON)
Input mode (output buffer OFF) 1
1
1
1
1
1
1
1
1
1
1
1
1
PM03
PM13
PM53
PM02
PM12
PM52
PM01
PM11
PM51
PM00
PM10
PM50
PM0
PM1
PM5
7
Symbol Address After reset
6543210 R/W
FF20H
FF21H
FF25H
FFH
FFH
FFH
R/W
R/W
R/W
1
1
PM26
1
PM25
1
PM24
1
PM23
PM33
PM22
PM32
PM21
PM31
PM20
PM30
PM2
PM3
FF22H
FF23H
FFH
FFH
R/W
R/W
Pmn pin input/output mode selection
(m = 0 to 3, 5, n = 0 to 6)
Table 6-3. Port Mode Register and Output Latch Settings When Using Alternate Functions
Alternate Function
Pin Name
Name I/O
PMxx Pxx
P00 to P03 KR0 to KR3 Input 1 x
P26 TO20 Output 0 0
INTP0 Input 1 x P30
CPT20 Input 1 x
INTP1 Input 1 x
TO30 Output 0 0
P31
TMI40 Input 1 x
INTP2 Input 1 x P32
TO40 Output 0 0
P33 INTP3 Input 1 x
Caution When port 2 is used as a serial interface pin, the I/O latch or output latch must be set according
to its function. For the setting method, see Table 13-2 Settings of Serial Interface 10 Operating
Mode and Table 14-2 Settings of Serial Interface 20 Operating Mode.
Remark x: don’t care
PMxx: Port mode register
Pxx: Port output latch
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(2) Pull-up resistor option register 0 (PU0)
Pull-up resistor option register 0 (PU0) sets whether an on-chip pull-up resistor on each port is used or not.
On the port specified to use an on-chip pull-up resistor by PU0, the pull-up resistor can be internally used
only for the bits set in the input mode. No on-chip pull-up resistors can be used for the bits set in the output
mode regardless of the setting of PU0. This also applies to cases when the pins are used for alternate
functions.
PU0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears PU0 to 00H.
Figure 6-12. Format of Pull-Up Resistor Option Register 0
Pm on-chip pull-up resistor selection
(m = 0, 1)
000000PU01 PU00PU0
Address After reset R/W
FFF7H 00H R/W
765432<1><0>
PU0m
0
1
On-chip pull-up resistor not used
On-chip pull-up resistor used
Symbol
Caution Bits 2 to 7 must be set to 0.
(3) Pull-up resistor option register B2 (PUB2)
Pull-up resistor option register B2 (PUB2) sets whether on-chip pull-up resistors on P20 to P26 are used or
not.
On the port specified to use an on-chip pull-up resistor by PUB2, the pull-up resistor can be internally used
only for the bits set in the input mode. No on-chip pull-up resistors can be used for the bits set in the output
mode regardless of the setting of PUB2. This also applies to cases when the pins are used for alternate
functions.
PUB2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears PUB2 to 00H.
Figure 6-13. Format of Pull-Up Resistor Option Register B2
P2n on-chip pull-up resistor selection
(n = 0 to 6)
0 PUB26 PUB25 PUB24 PUB23 PUB22 PUB21 PUB20
PUB2
Address After reset R/W
FF32H 00H R/W
7 <6> <5> <4> <3> <2> <1> <0>
PUB2n
0
1
On-chip pull-up resistor not used
On-chip pull-up resistor used
Symbol
Caution Bit 7 must be set to 0.
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(4) Pull-up resistor option register B3 (PUB3)
Pull-up resistor option register B3 (PUB3) sets whether on-chip pull-up resistors on P30 to P33 are used or
not.
On the port specified to use an on-chip pull-up resistor by PUB3, the pull-up resistor can be internally used
only for the bits set in the input mode. No on-chip pull-up resistors can be used for the bits set in the output
mode regardless of the setting of PUB3. This also applies to cases when the pins are used for alternate
functions.
PUB3 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears PUB3 to 00H.
Figure 6-14. Format of Pull-Up Resistor Option Register B3
P3n on-chip pull-up resistor selection
(n = 0 to 3)
00
0 0 PUB33 PUB32 PUB31 PUB30
PUB3
Address After reset R/W
FF33H 00H R/W
7654<3><2><1><0>
PUB3n
0
1
On-chip pull-up resistor not used
On-chip pull-up resistor used
Symbol
Caution Bits 4 to 7 must be set to 0.
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6.4 Port Function Operation
The operation of a port differs depending on whether the port is set in the input or output mode, as described
below.
6.4.1 Writing to I/O port
(1) In output mode
A value can be written to the output latch of a port by using a transfer instruction. The contents of the output
latch can be output from the pins of the port.
Data once written to the output latch is retained until new data is written to the output latch.
(2) In input mode
A value can be written to the output latch by using a transfer instruction. However, the status of the port pin
is not changed because the output buffer is OFF.
Data once written to the output latch is retained until new data is written to the output latch.
Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port.
However, this instruction accesses the port in 8-bit units. When this instruction is
executed to manipulate a bit of an input/output port, therefore, the contents of the output
latch of the pin that is set in the input mode and not subject to manipulation become
undefined.
6.4.2 Reading from I/O port
(1) In output mode
The status of an output latch can be read by using a transfer instruction. The contents of the output latch are
not changed.
(2) In input mode
The status of a pin can be read by using a transfer instruction. The contents of the output latch are not
changed.
6.4.3 Arithmetic operation of I/O port
(1) In output mode
An arithmetic operation can be performed with the contents of the output latch. The result of the operation is
written to the output latch. The contents of the output latch are output from the port pins.
Data once written to the output latch is retained until new data is written to the output latch.
(2) In input mode
The contents of the output latch become undefined. However, the status of the pin is not changed because
the output buffer is OFF.
Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port.
However, this instruction accesses the port in 8-bit units. When this instruction is
executed to manipulate a bit of an input/output port, therefore, the contents of the output
latch of the pin that is set in the input mode and not subject to manipulation become
undefined.
92 User’s Manual U14800EJ3V0UD
CHAPTER 7 CLOCK GENERATOR (
µ
PD789306 SUBSERIES)
7.1 Clock Generator Functions
The clock generator generates the clock to be supplied to the CPU and peripheral hardware.
The following two types of system clock oscillators are used.
• Main system clock (ceramic/crystal) oscillator
This circuit oscillates at 1.0 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting
the processor clock control register (PCC).
• Subsystem clock oscillator
This circuit oscillates at 32.768 kHz. Oscillation can be stopped by the suboscillation mode register (SCKM).
7.2 Clock Generator Configuration
The clock generator includes the following hardware.
Table 7-1. Configuration of Clock Generator
Item Configuration
Control registers Processor clock control register (PCC)
Suboscillation mode register (SCKM)
Subclock control register (CSS)
Oscillators Main system clock oscillator
Subsystem clock oscillator
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Figure 7-1. Block Diagram of Clock Generator
f
XT
f
X
Prescaler
f
X
2
2
f
XT
2
1/2
Prescaler
Watch timer
LCD controller
/driver
Clock to
peripheral
hardware
CPU clock
(f
CPU
)
Standby
controller
Wait
controller
Selector
STOP MCC PCC1 CLS CSS0
Internal bus
Suboscillation mode register
(SCKM)
FRC SCC
Internal bus
Subclock control
register (CSS)
Processor clock
control register
(PCC)
Subsystem
clock
oscillator
X1
X2
XT1
XT2
Main system
clock
oscillator
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µ
PD789306 SUBSERIES)
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7.3 Registers Controlling Clock Generator
The clock generator is controlled by the following registers.
• Processor clock control register (PCC)
• Suboscillation mode register (SCKM)
• Subclock control register (CSS)
(1) Processor clock control register (PCC)
PCC sets CPU clock selection and the division ratio.
PCC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PCC to 02H.
Figure 7-2. Format of Processor Clock Control Register
Control of main system clock oscillator operation
MCC00000PCC1 0PCC
Symbol Address After reset R/W
FFFBH 02H R/W
<7>6543210
MCC
0
1
Operation enabled
Operation disabled
0.4 s
1.6 s
122 s
Selection of CPU clock (f
CPU
)
Note
CSS0
0
0
1
1
PCC1
0
1
0
1
f
X
f
X
/2
2
f
XT
/2
µ
µ
µ
Minimum instruction execution time: 2/f
CPU
f
X
= 5.0 MHz or f
XT
= 32.768 kHz operation
Note The CPU clock is selected according to a combination of the PCC1 flag in the processor clock control
register (PCC) and the CSS0 flag in the subclock control register (CSS) (Refer to 7.3 (3) Subclock control
register (CSS)).
Cautions 1. Bits 0 and 2 to 6 must be set to 0.
2. The MCC can be set only when the subsystem clock has been selected as the CPU clock.
Remarks 1. fX: Main system clock oscillation frequency
2. f
XT: Subsystem clock oscillation frequency
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(2) Suboscillation mode register (SCKM)
SCKM selects a feedback resistor for the subsystem clock, and controls the oscillation of the clock.
SCKM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SCKM to 00H.
Figure 7-3. Format of Suboscillation Mode Register
Feedback resistor selection
Note
000000FRCSCCSCKM
Symbol Address After reset R/W
FFF0H 00H R/W
76543210
FRC
0
1
On-chip feedback resistor used
On-chip feedback resistor not used
Control of subsystem clock oscillator operationSCC
0
1
Operation enabled
Operation disabled
Note The feedback resistor is necessary to adjust the bias point of the oscillation waveform to close to the mid
point of the supply voltage. Only when the subclock is not used, the power consumption in STOP mode
can be further reduced by setting FRC = 1.
Caution Bits 2 to 7 must be set to 0.
CHAPTER 7 CLOCK GENERATOR (
µ
PD789306 SUBSERIES)
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(3) Subclock control register (CSS)
CSS specifies whether the main system or subsystem clock oscillator is to be selected. It also specifies the
CPU clock operation status.
CSS is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSS to 00H.
Figure 7-4. Format of Subclock Control Register
CPU clock operation status
0 0 CLS CSS0 0000CSS
Address After reset R/W
FFF2H 00H R/W
76543210
CLS
0
1
Operation based on the output of the divided main system clock
Operation based on the subsystem clock
Selection of the main system or subsystem clock oscillatorCSS0
0
1
Divided output from the main system clock oscillator
Output from the subsystem clock oscillator
Symbol
Note
Note Bit 5 is read only.
Caution Bits 0 to 3, 6, and 7 must be set to 0.
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7.4 System Clock Oscillators
7.4.1 Main system clock oscillator
The main system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 MHz TYP.) connected
across the X1 and X2 pins.
An external clock can also be input to the circuit. In this case, input the clock signal to the X1 pin, and input the
inverted signal to the X2 pin.
Figure 7-5 shows the external circuit of the main system clock oscillator.
Figure 7-5. External Circuit of Main System Clock Oscillator
(a) Crystal or ceramic oscillation (b) External clock
Crystal
or
ceramic resonator
V
SS
X2
X1
External
clock X1
X2
Caution When using the main system or subsystem clock oscillator, wire as follows in the area enclosed
by the broken lines in Figures 7-5 and 7-6 to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
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7.4.2 Subsystem clock oscillator
The subsystem clock oscillator is oscillated by the crystal resonator (32.768 kHz TYP.) connected across the XT1
and XT2 pins.
An external clock can also be input to the circuit. In this case, input the clock signal to the XT1 pin, and input the
inverted signal to the XT2 pin.
Figure 7-6 shows the external circuit of the subsystem clock oscillator.
Figure 7-6. External Circuit of Subsystem Clock Oscillator
(a) Crystal oscillation (b) External clock
XT2
V
SS
XT1
32.768
kHz
Crystal resonator
External
clock XT1
XT2
Caution When using the main system or subsystem clock oscillator, wire as follows in the area enclosed
by the broken lines in Figures 7-5 and 7-6 to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
When using the subsystem clock, particular care is required because the subsystem clock
oscillator is designed as a low-amplitude circuit for reducing current consumption.
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7.4.3 Examples of incorrect resonator connection
Figure 7-7 shows examples of incorrect resonator connection.
Figure 7-7. Examples of Incorrect Resonator Connection (1/2)
(a) Too long wiring (b) Crossed signal line
V
SS
X1 X2
V
SS
X1 X2
PORTn
(n = 0 to 3, 5)
(c) Wiring near high fluctuating current (d) Current flowing through ground line of oscillator
(potential at points A, B, and C fluctuates)
V
SS
X1 X2
High current
V
SS
X1
AB C
P
mn
V
DD
High current
X2
Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a resistor
to the XT2 in series.
CHAPTER 7 CLOCK GENERATOR (
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Figure 7-7. Examples of Incorrect Resonator Connection (2/2)
(e) Signal is fetched (f) Parallel and near signal lines of main system clock
and subsystem clock
V
SS
X1 X2
V
SS
X2
XT2 is wired parallel to X1.
X1 XT2 XT1
Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a resistor
to the XT2 in series.
Caution If the X1 wire is in parallel with the XT2 wire, crosstalk noise may occur between the X1 and XT2,
resulting in a malfunction.
To avoid this, do not lay the X1 and XT2 wires in parallel.
7.4.4 Divider circuit
The divider circuit divides the output of the main system clock oscillator (fX) to generate various clocks.
7.4.5 When no subsystem clock is used
If a subsystem clock is not necessary, for example, for low-power consumption operation or clock operation,
handle the XT1 and XT2 pins as follows:
XT1: Connect to VSS
XT2: Leave open
In this case, however, a small current leaks via the on-chip feedback resistor in the subsystem clock oscillator
when the main system clock is stopped. To avoid this, set bit 1 (FRC) of the suboscillation mode register (SCKM) so
that the on-chip feedback resistor will not be used. Also in this case, handle the XT1 and XT2 pins as stated above.
CHAPTER 7 CLOCK GENERATOR (
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7.5 Clock Generator Operation
The clock generator generates the following clocks and controls the operation modes of the CPU, such as the
standby mode.
• Main system clock fX
• Subsystem clock fXT
• CPU clock fCPU
• Clock to peripheral hardware
The operation and function of the clock generator is determined by the processor clock control register (PCC),
suboscillation mode register (SCKM), and subclock control register (CSS), as follows.
(a) The low-speed mode (1.6
µ
s: at 5.0 MHz operation) of the main system clock is selected when the
RESET signal is generated (PCC = 02H). While a low level is input to the RESET pin, oscillation of the
main system clock is stopped.
(b) Three types of Minimum instruction execution time (0.4
µ
s and 1.6
µ
s: main system clock (at 5.0 MHz
operation), 122
µ
s: subsystem clock (at 32.768 kHz operation)) can be selected by the PCC, SCKM,
and CSS settings.
(c) Two standby modes, STOP and HALT, can be used with the main system clock selected. In a system
where no subsystem clock is used, setting bit 1 (FRC) of the SCKM so that the on-chip feedback
resistor cannot be used reduces current consumption in STOP mode. In a system where a subsystem
clock is used, setting SCKM bit 0 to 1 can cause the subsystem clock to stop oscillation.
(d) CSS bit 4 (CSS0) can be used to select the subsystem clock so that low current consumption operation
is used (122
µ
s: at 32.768 kHz operation).
(e) With the subsystem clock selected, it is possible to cause the main system clock to stop oscillating
using bit 7 (MCC) of PCC. The HALT mode can be used, but the STOP mode cannot.
(f) The clock pulse for the peripheral hardware is generated by dividing the frequency of the main system
clock, but the subsystem clock pulse is only supplied to the watch timer and LCD controller/driver. The
watch timer and LCD controller/driver can therefore keep running even during standby. The other
hardware stops when the main system clock stops because it runs based on the main system clock
(except for external input clock operations).
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µ
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7.6 Changing Setting of System Clock and CPU Clock
7.6.1 Time required for switching between system clock and CPU clock
The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC) and bit 4
(CSS0) of the subclock control register (CSS).
Actually, the specified clock is not selected immediately after the setting of PCC has been changed, and the old
clock is used for the duration of several instructions after that (see Table 7-2).
Table 7-2. Maximum Time Required for Switching CPU Clock
Set Value Before Switching Set Value After Switching
CSS0 PCC1 CSS0 PCC1 CSS0 PCC1 CSS0 PCC1
0 0 0 1 1 x
0 0 4 clocks 2fX/fXT clocks
(306 clocks)
1 2 clocks fX/2fXT clocks
(76 clocks)
1 x 2 clocks 2 clocks
Remarks 1. Two clocks are the minimum instruction execution time of the CPU clock before switching.
2. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
3. x: don’t care
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7.6.2 Switching between system clock and CPU clock
The following figure illustrates how the CPU clock and system clock switch.
Figure 7-8. Switching Between System Clock and CPU Clock
System clock
CPU clock
Interrupt request signal
RESET
VDD
fXfXfXT fX
Low-speed
operation
High-speed
operation
Subsystem clock
operation
High-speed operation
Wait (6.55 ms: at 5.0 MHz operation)
Internal reset operation
<1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released
when the RESET pin is later made high, and the main system clock starts oscillating. At this time, the
oscillation stabilization time (215/fX) is automatically secured.
After that, the CPU starts instruction execution at the slow speed of the main system clock (1.6
µ
s: at
5.0 MHz operation).
<2> After the time required for the VDD voltage to rise to the level at which the CPU can operate at high speed
has elapsed, bit 1 (PCC1) of the processor clock control register (PCC) and bit 4 (CSS0) of the subclock
control register (CSS) are rewritten so that high-speed operation can be selected.
<3> A drop of the VDD voltage is detected with an interrupt request signal. The clock is switched to the
subsystem clock (at this moment, the subsystem clock must be in the oscillation stabilization status).
<4> A recover of the VDD voltage is detected with an interrupt request signal. Bit 7 (MCC) of PCC is set to 0, and
then the main system clock starts oscillating. After the time required for the oscillation to stabilize has
elapsed, PCC1 and CSS0 are rewritten so that high-speed operation can be selected again.
Caution When the main system clock is stopped and the device is operating on the subsystem
clock, wait until the oscillation stabilization time has been secured by the program before
switching back to the main system clock.
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CHAPTER 8 CLOCK GENERATOR (
µ
PD789316 SUBSERIES)
8.1 Clock Generator Functions
The clock generator generates the clock to be supplied to the CPU and peripheral hardware.
The following two types of system clock oscillators are used.
• Main system clock (RC) oscillator
This circuit oscillates at 2.0 to 4.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting
the processor clock control register (PCC).
• Subsystem clock oscillator
This circuit oscillates at 32.768 kHz. Oscillation can be stopped by the suboscillation mode register (SCKM).
8.2 Clock Generator Configuration
The clock generator includes the following hardware.
Table 8-1. Configuration of Clock Generator
Item Configuration
Control registers Processor clock control register (PCC)
Suboscillation mode register (SCKM)
Subclock control register (CSS)
Oscillators Main system clock oscillator
Subsystem clock oscillator
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Figure 8-1. Block Diagram of Clock Generator
f
XT
f
CC
Prescaler
f
CC
2
2
f
XT
2
1/2
Prescaler
Watch timer
LCD controller
/driver
Clock to
peripheral
hardware
CPU clock
(f
CPU
)
Standby
controller
Wait
controller
Selector
STOP MCC PCC1 CLS CSS0
Internal bus
Suboscillation mode register
(SCKM)
FRC SCC
Internal bus
Subclock control
register (CSS)
Processor clock
control register
(PCC)
Subsystem
clock
oscillator
CL1
CL2
XT1
XT2
Main system
clock
oscillator
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8.3 Registers Controlling Clock Generator
The clock generator is controlled by the following registers.
• Processor clock control register (PCC)
• Suboscillation mode register (SCKM)
• Subclock control register (CSS)
(1) Processor clock control register (PCC)
PCC sets CPU clock selection and the division ratio.
PCC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PCC to 02H.
Figure 8-2. Format of Processor Clock Control Register
Control of main system clock oscillator operation
MCC00000PCC1 0PCC
Symbol Address After reset R/W
FFFBH 02H R/W
<7>6543210
MCC
0
1
Operation enabled
Operation disabled
0.5 s
2.0 s
122 s
Selection of CPU clock (f
CPU
)
Note
CSS0
0
0
1
1
PCC1
0
1
0
1
f
CC
f
CC
/2
2
f
XT
/2
µ
µ
µ
Minimum instruction execution time: 2/f
CPU
f
CC
= 4.0 MHz or f
XT
= 32.768 kHz operation
Note The CPU clock is selected according to a combination of the PCC1 flag in the processor clock control
register (PCC) and the CSS0 flag in the subclock control register (CSS) (Refer to 8.3 (3) Subclock control
register (CSS)).
Cautions 1. Bits 0 and 2 to 6 must be set to 0.
2. The MCC can be set only when the subsystem clock has been selected as the CPU clock.
Remarks 1. fCC: Main system clock oscillation frequency
2. f
XT: Subsystem clock oscillation frequency
CHAPTER 8 CLOCK GENERATOR (
µ
PD789316 SUBSERIES)
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(2) Suboscillation mode register (SCKM)
SCKM selects a feedback resistor for the subsystem clock, and controls the oscillation of the clock.
SCKM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SCKM to 00H.
Figure 8-3. Format of Suboscillation Mode Register
Feedback resistor selection
Note
000000FRCSCCSCKM
Symbol Address After reset R/W
FFF0H 00H R/W
76543210
FRC
0
1
On-chip feedback resistor used
On-chip feedback resistor not used
Control of subsystem clock oscillator operationSCC
0
1
Operation enabled
Operation disabled
Note The feedback resistor is necessary to adjust the bias point of the oscillation waveform to close to the mid
point of the supply voltage. Only when the subclock is not used, the power consumption in STOP mode
can be further reduced by setting FRC = 1.
Caution Bits 2 to 7 must be set to 0.
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µ
PD789316 SUBSERIES)
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(3) Subclock control register (CSS)
CSS specifies whether the main system or subsystem clock oscillator is to be selected. It also specifies the
CPU clock operation status.
CSS is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSS to 00H.
Figure 8-4. Format of Subclock Control Register
CPU clock operation status
0 0 CLS CSS0 0000CSS
Address After reset R/W
FFF2H 00H R/W
76543210
CLS
0
1
Operation based on the output of the divided main system clock
Operation based on the subsystem clock
Selection of the main system or subsystem clock oscillatorCSS0
0
1
Divided output from the main system clock oscillator
Output from the subsystem clock oscillator
Symbol
Note
Note Bit 5 is read only.
Caution Bits 0 to 3, 6, and 7 must be set to 0.
CHAPTER 8 CLOCK GENERATOR (
µ
PD789316 SUBSERIES)
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8.4 System Clock Oscillators
8.4.1 Main system clock oscillator
The main system clock oscillator is oscillated by the resistor (R) and capacitor (C) (4.0 MHz: TYP.) connected
across the CL1 and CL2 pins.
An external clock can also be input to the circuit. In this case, input the clock signal to the CL1 pin, and input the
inverted signal to the CL2 pin.
Figure 8-5 shows the external circuit of the main system clock oscillator.
Figure 8-5. External Circuit of Main System Clock Oscillator
(a) RC oscillation (b) External clock
V
SS
CL1
RC
CL2
External
clock CL1
CL2
Caution When using the main system or subsystem clock oscillator, wire as follows in the area enclosed
by the broken lines in Figures 8-5 and 8-6 to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
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µ
PD789316 SUBSERIES)
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8.4.2 Subsystem clock oscillator
The subsystem clock oscillator is oscillated by the crystal resonator (32.768 kHz TYP.) connected across the XT1
and XT2 pins.
An external clock can also be input to the circuit. In this case, input the clock signal to the XT1 pin, and input the
inverted signal to the XT2 pin.
Figure 8-6 shows the external circuit of the subsystem clock oscillator.
Figure 8-6. External Circuit of Subsystem Clock Oscillator
(a) Crystal oscillation (b) External clock
XT2
V
SS
XT1
32.768
kHz
Crystal resonator
External
clock XT1
XT2
Caution When using the main system or subsystem clock oscillator, wire as follows in the area enclosed
by the broken lines in Figures 8-5 and 8-6 to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
When using the subsystem clock, particular care is required because the subsystem clock
oscillator is designed as a low-amplitude circuit for reducing current consumption.
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µ
PD789316 SUBSERIES)
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8.4.3 Examples of incorrect resonator connection
Figure 8-7 shows examples of incorrect resonator connection.
Figure 8-7. Examples of Incorrect Resonator Connection (1/3)
(a) Too long wiring
• Main system clock
• Subsystem clock
VSSCL2CL1
XT1 XT2 VSS
(b) Crossed signal line
• Main system clock
• Subsystem clock
V
SS
CL2
PORTn
(n = 0 to 3, 5)
CL1
PORTn
(n = 0 to 3, 5)
XT1 XT2 V
SS
CHAPTER 8 CLOCK GENERATOR (
µ
PD789316 SUBSERIES)
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Figure 8-7. Examples of Incorrect Resonator Connection (2/3)
(c) Wiring near high fluctuating current
• Main system clock
• Subsystem clock
V
SS
CL2CL1
High current
XT1 XT2 V
SS
High current
(d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates)
• Main system clock • Subsystem clock
VSS
VDD
CL2CL1
PORTn
(n = 0 to 3, 5)
AB
High current
VDD
PORTn
(n = 0 to 3, 5)
XT1 XT2 VSS
ABC
High current
CHAPTER 8 CLOCK GENERATOR (
µ
PD789316 SUBSERIES)
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Figure 8-7. Examples of Incorrect Resonator Connection (3/3)
(e) Signal is fetched
• Main system clock
• Subsystem clock
V
SS
CL2CL1
XT1 XT2 V
SS
(f) Parallel and near signal lines of main system clock
and subsystem clock
VSS XT1
XT2 is wired parallel to CL1.
XT2 CL1 CL2
CHAPTER 8 CLOCK GENERATOR (
µ
PD789316 SUBSERIES)
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8.4.4 Divider circuit
The divider circuit divides the output of the main system clock oscillator (fCC) to generate various clocks.
8.4.5 When no subsystem clock is used
If a subsystem clock is not necessary, for example, for low-power consumption operation or clock operation,
handle the XT1 and XT2 pins as follows:
XT1: Connect to VSS
XT2: Leave open
In this case, however, a small current leaks via the on-chip feedback resistor in the subsystem clock oscillator
when the main system clock is stopped. To avoid this, set bit 1 (FRC) of the suboscillation mode register (SCKM) so
that the on-chip feedback resistor will not be used. Also in this case, handle the XT1 and XT2 pins as stated above.
CHAPTER 8 CLOCK GENERATOR (
µ
PD789316 SUBSERIES)
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8.5 Clock Generator Operation
The clock generator generates the following clocks and controls the operation modes of the CPU, such as the
standby mode.
• Main system clock fCC
• Subsystem clock fXT
• CPU clock fCPU
• Clock to peripheral hardware
The operation and function of the clock generator is determined by the processor clock control register (PCC),
suboscillation mode register (SCKM), and subclock control register (CSS), as follows.
(a) The low-speed mode (2.0
µ
s: at 4.0 MHz operation) of the main system clock is selected when the
RESET signal is generated (PCC = 02H). While a low level is input to the RESET pin, oscillation of the
main system clock is stopped.
(b) Three types of Minimum instruction execution time (0.5
µ
s and 2.0
µ
s: main system clock (at 4.0 MHz
operation), 122
µ
s: subsystem clock (at 32.768 kHz operation)) can be selected by the PCC, SCKM,
and CSS settings.
(c) Two standby modes, STOP and HALT, can be used with the main system clock selected. In a system
where no subsystem clock is used, setting bit 1 (FRC) of the SCKM so that the on-chip feedback
resistor cannot be used reduces current consumption in STOP mode. In a system where a subsystem
clock is used, setting SCKM bit 0 to 1 can cause the subsystem clock to stop oscillation.
(d) CSS bit 4 (CSS0) can be used to select the subsystem clock so that low current consumption operation
is used (122
µ
s: at 32.768 kHz operation).
(e) With the subsystem clock selected, it is possible to cause the main system clock to stop oscillating
using bit 7 (MCC) of PCC. The HALT mode can be used, but the STOP mode cannot.
(f) The clock pulse for the peripheral hardware is generated by dividing the frequency of the main system
clock, but the subsystem clock pulse is only supplied to the watch timer and LCD controller/driver. The
watch timer and LCD controller/driver can therefore keep running even during standby. The other
hardware stops when the main system clock stops because it runs based on the main system clock
(except for external input clock operations).
CHAPTER 8 CLOCK GENERATOR (
µ
PD789316 SUBSERIES)
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8.6 Changing Setting of System Clock and CPU Clock
8.6.1 Time required for switching between system clock and CPU clock
The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC) and bit 4
(CSS0) of the subclock control register (CSS).
Actually, the specified clock is not selected immediately after the setting of PCC has been changed, and the old
clock is used for the duration of several instructions after that (see Table 8-2).
Table 8-2. Maximum Time Required for Switching CPU Clock
Set Value Before Switching Set Value After Switching
CSS0 PCC1 CSS0 PCC1 CSS0 PCC1 CSS0 PCC1
0 0 0 1 1 x
0 0 4 clocks 2fCC/fXT clocks
(244 clocks)
1 2 clocks fCC/2fXT clocks
(61 clocks)
1 x 2 clocks 2 clocks
Remarks 1. Two clocks are the minimum instruction execution time of the CPU clock before switching.
2. The parenthesized values apply to operation at fCC = 4.0 MHz or fXT = 32.768 kHz.
3. x: don’t care
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µ
PD789316 SUBSERIES)
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8.6.2 Switching between system clock and CPU clock
The following figure illustrates how the CPU clock and system clock switch.
Figure 8-8. Switching Between System Clock and CPU Clock
System clock
CPU clock
Interrupt request signal
RESET
VDD
fCC fCC fXT fCC
Low-speed
operation
High-speed
operation
Subsystem clock
operation
High-speed operation
Wait (32 s: at 4.0 MHz operation)
Internal reset operation
µ
<1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released
when the RESET pin is later made high, and the main system clock starts oscillating. At this time, the
oscillation stabilization time (27/fCC) is automatically secured.
After that, the CPU starts instruction execution at the slow speed of the main system clock (2.0
µ
s: at
4.0 MHz operation).
<2> After the time required for the VDD voltage to rise to the level at which the CPU can operate at high speed
has elapsed, bit 1 (PCC1) of the processor clock control register (PCC) and bit 4 (CSS0) of the subclock
control register (CSS) are rewritten so that high-speed operation can be selected.
<3> A drop of the VDD voltage is detected with an interrupt request signal. The clock is switched to the
subsystem clock (at this moment, the subsystem clock must be in the oscillation stabilization status).
<4> A recover of the VDD voltage is detected with an interrupt request signal. Bit 7 (MCC) of PCC is set to 0, and
then the main system clock starts oscillating. After the time required for the oscillation to stabilize has
elapsed, PCC1 and CSS0 are rewritten so that high-speed operation can be selected again.
Caution When the main system clock is stopped and the device is operating on the subsystem
clock, wait until the oscillation stabilization time has been secured by the program before
switching back to the main system clock.
118 User’s Manual U14800EJ3V0UD
CHAPTER 9 16-BIT TIMER 20
16-bit timer 20 references the free running counter and provides the functions such as timer interrupt and timer
output. In addition, the count value can be captured by a capture trigger pin.
9.1 16-Bit Timer 20 Functions
16-bit timer 20 has the following functions.
• Timer interrupt
• Timer output
• Count value capture
(1) Timer interrupt
An interrupt is generated when a count value and compare value matches.
(2) Timer output
Timer output control is possible when a count value and compare value matches.
(3) Count value capture
The 16-bit timer counter 20 (TM20) count value is latched to capture register in synchronization with the
capture trigger and retained.
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9.2 16-Bit Timer 20 Configuration
16-bit timer 20 includes in the following hardware.
Table 9-1. Configuration of 16-Bit Timer 20
Item Configuration
Timer counter 16 bits × 1 (TM20)
Registers Compare register: 16 bits × 1 (CR20)
Capture register: 16 bits × 1 (TCP20)
Timer outputs 1 (TO20)
Control registers 16-bit timer mode control register 20 (TMC20)
Port mode register 2 (PM2)
Port mode register 3 (PM3)
Port 2 (P2)
Figure 9-1. Block Diagram of 16-Bit Timer 20
CPT20/P30
/INTP0
Internal bus
Internal bus
16-bit timer mode
control register 20
(TMC20)
16-bit timer mode
control register 20 (TMC20)
TOF20
CPT201 CPT200
TOC20
TCL201 TCL200
TOE20
f
CLK
f
CLK
/2
5
f
CLK
/2
2
f
CLK
/2
7
Edge
detector
16-bit capture
register 20 (TCP20)
16-bit counter
read buffer
16-bit timer counter 20 (TM20)
16-bit compare register 20 (CR20)
Match
Selector
OVF
F/F
TOD20
TO20/P26
INTTM20
P26
output latch
PM26
Remark f
CLK: fX or fCC
CHAPTER 9 16-BIT TIMER 20
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(1) 16-bit compare register 20 (CR20)
This register compares the value set to CR20 with the count value of 16-bit timer counter 20 (TM20), and
when they match, generates an interrupt request (INTTM20).
CR20 is set with a 16-bit memory manipulation instruction. The values 0000H to FFFFH can be set. RESET
input sets CR20 to FFFFH.
Cautions 1. This register is manipulated with a 16-bit memory manipulation instruction, however an
8-bit memory manipulation instruction can also be used. When manipulated with an 8-
bit memory manipulation instruction, the accessing method should be direct
addressing.
2. When rewriting CR20 during a count operation, preset CR20 to interrupt disabled using
interrupt mask flag register 0 (MK0). Also set the timer output data to inversion
disabled using 16-bit timer mode control register 20 (TMC20).
If CR20 is rewritten while interrupts are enabled, an interrupt request may be generated
at that time.
(2) 16-bit timer counter 20 (TM20)
This is a 16-bit register that counts count pulses.
TM20 is read with a 16-bit memory manipulation instruction.
This register is in free running mode during count clock input.
RESET input sets TM20 to 0000H and then to free running mode again.
Cautions 1. The count value after releasing stop becomes undefined because the count operation is
executed during the oscillation stabilization time.
2. This register is manipulated with a 16-bit memory manipulation instruction, however an
8-bit memory manipulation instruction can also be used. When manipulated with an 8-
bit memory manipulation instruction, the accessing method should be direct
addressing.
3. When manipulated with an 8-bit memory manipulation instruction, readout should be
performed in the order from lower byte to higher byte and must be in pairs.
(3) 16-bit capture register 20 (TCP20)
This is a 16-bit register that captures the contents of 16-bit timer counter 20 (TM20).
The TCP20 is set with a 16-bit memory manipulation instruction.
RESET input sets TCP20 undefined.
Caution This register is manipulated with a 16-bit memory manipulation instruction, however an 8-
bit memory manipulation instruction can also be used. When manipulated with an 8-bit
memory manipulation instruction, the accessing method should be direct addressing.
(4) 16-bit counter read buffer
This buffer latches a counter value and retains the count value of 16-bit timer counter 20 (TM20).
CHAPTER 9 16-BIT TIMER 20
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9.3 Registers Controlling 16-Bit Timer 20
The following four registers control 16-bit timer 20.
• 16-bit timer mode control register 20 (TMC20)
• Port mode register 2 (PM2)
• Port mode register 3 (PM3)
• Port 2 (P2)
(1) 16-bit timer mode control register 20 (TMC20)
16-bit timer mode control register 20 (TMC20) controls the setting of the count clock, capture edge, etc.
TMC20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMC20 to 00H.
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Figure 9-2. Format of 16-Bit Timer Mode Control Register 20
TOC20
0
1
TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20
TMC20
R/W
FF48H 00H R/W
<6>54321
CPT201
0
0
1
1
CPT200
0
1
0
1
Capture operation disabled
Rising edge of CPT20
Falling edge of CPT20
Both edges of CPT20
TOF20
0
1
<7> <0>
Set by overflow of 16-bit timer
Symbol Address After reset
Timer output data inversion control
Inversion disabled
Inversion enabled
Capture edge selection
During f
X
= 5.0 MHz operation During f
CC
= 4.0 MHz operation
TOE20
0
1
TCL201
0
0
TCL200
0
1
f
X
(5.0 MHz)
f
X
/2
2
(1.25 MHz)
f
X
/2
5
(156.3 kHz)
f
X
/2
7
(39.1 kHz)
f
CC
(4.0 MHz)
f
CC
/2
2
(1.0 MHz)
f
CC
/2
5
(125 kHz)
f
CC
/2
7
(31.3 kHz)
1
1
0
1
16-bit timer counter 20 output control
Output disabled (port mode)
Output enabled
16-bit timer counter 20 count clock selection
Overflow flag set
Cleared by reset and software
0
1Timer output data is 1
Timer output data is 0
TOD20
Timer output data
Note
Note Bit 7 is read-only.
Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. f
CC: Main system clock oscillation frequency (RC oscillation)
CHAPTER 9 16-BIT TIMER 20
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(2) Port mode register 2, 3 (PM2, PM3)
This register sets the input/output of port 2, 3 in 1-bit units.
To use the P26/TO20 pin for timer output, set the output latch of PM26 and P26 to 0.
To use the P30/INTP0/CPT20 pin for capture input, set the PM30 to 1.
PM2, PM3 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM2 to FFH.
Figure 9-3. Format of Port Mode Register 2, 3
1 PM26
PM25 PM24
PM23 PM22 PM21 PM20PM2
R/W
FF22H FFH R/W
65432170
Symbol Address After reset
11
11
PM33 PM32 PM31 PM30PM3 FF23H FFH R/W
PMmn
0
1Input mode (output buffer OFF)
Pmn pin input/output mode selection (mn = 20-26, 30-33)
Output mode (output buffer ON)
CHAPTER 9 16-BIT TIMER 20
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9.4 16-Bit Timer 20 Operation
9.4.1 Operation as timer interrupt
16-bit timer 20 can generate interrupts repeatedly each time the free-running counter value reaches the value set
to CR20. Since this counter is not cleared and holds the count even after an interrupt is generated, the interval time is
equal to one cycle of the count clock set in TCL201 and TCL200.
To operate 16-bit timer 20 as a timer interrupt, the following settings are required.
• Set count values to CR20
• Set 16-bit timer mode control register 20 (TMC20) as shown in Figure 9-4.
Figure 9-4. Settings of 16-Bit Timer Mode Control Register 20 at Timer Interrupt Operation
– 0/1 0/1 0/1 0/1 0/1 0/1 0/1
TOD20 TOF20
CPT201 CPT200
TOC20
TCL201 TCL200
TOE20
TMC20
Setting of count clock (see Table 9-2)
Caution If both the CPT201 flag and CPT200 flag are set to 0, the capture edge becomes operation
disabled.
When the count value of 16-bit timer counter 20 (TM20) matches the value set to CR20, counting of TM20
continues and an interrupt request signal (INTTM20) is generated.
Table 9-2 shows the interval time, and Figure 9-5 shows the timing of the timer interrupt operation.
Caution Process as follows when rewriting CR20 during a count operation.
<1> Set the interrupt to disabled (TMMK20 (bit 1of interrupt mask flag register 1(MK1) = 1)
<2> Set the inversion control of timer output data to disabled (TOC20 = 0)
If CR20 is rewritten while interrupts are enabled, an interrupt request may be generated at
that time.
Table 9-2. Interval Time of 16-Bit Timer 20
Count Clock Interval Time TCL201 TCL200
During fX = 5.0
MHz Operation
During fCC = 4.0
MHz Operation
During fX = 5.0
MHz Operation
During fCC = 4.0
MHz Operation
0 0
1/fX (0.2
µ
s) 1/fCC (0.25
µ
s) 216/fX (13.1 ms) 216/fCC (16.4 ms)
0 1
22/fX (0.8
µ
s) 22/fCC (1.0
µ
s) 218/fX (52.4 ms) 218/fCC (65.5 ms)
1 0
25/fX (6.4
µ
s) 25/fCC (8.0
µ
s) 221/fX (419.4 ms) 221/fCC (524.2 ms)
1 1
27/fX (25.6
µ
s) 27/fCC (32
µ
s) 223/fX (1.68 s) 223/fCC (2.10 ms)
Remarks 1. f
X: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. f
CC: Main system clock oscillation frequency (RC oscillation)
CHAPTER 9 16-BIT TIMER 20
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Figure 9-5. Timing of Timer Interrupt Operation
Count clock
TM20 count value
CR20
INTTM20
TO20
TOF20
0000H
0001H
N
FFFFH 0000H 0001H
N
FFFFH
NN N NN
Interrupt acknowledgement
Interrupt acknowledgement
Overflow flag set
Remark N = 0000H to FFFFH
CHAPTER 9 16-BIT TIMER 20
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9.4.2 Operation as timer output
16-bit timer 20 can invert the timer output repeatedly each time the free-running counter value reaches the value
set to CR20. Since this counter is not cleared and holds the count even after the timer output is inverted, the interval
time is equal to one cycle of the count clock set in TCL201 and TCL200.
To operate 16-bit timer 20 as a timer output, the following settings are required.
• Set P26 to output mode (PM26 = 0)
• Set the output latch of P26 to 0
• Set the count value to CR20
• Set 16-bit timer mode control register 20 (TMC20) as shown in Figure 9-6
Figure 9-6. Settings of 16-Bit Timer Mode Control Register 20 at Timer Output Operation
– 0/1 0/1 0/1 1 0/1 0/1 1
TOD20 TOF20
CPT201 CPT200
TOC20
TCL201 TCL200
TOE20
TMC20
Setting of count clock (see Table 9-2)
Inversion enable of timer output data
TO20 output enable
Caution If both the CPT201 flag and CPT200 flag are set to 0, the capture edge becomes operation
disabled.
When the count value of 16-bit timer counter 20 (TM20) matches the value set in CR20, the output status of the
TO20/P26 pin is inverted. This enables timer output. At that time, TM20 continues counting and an interrupt request
signal (INTTM20) is generated.
Figure 9-7 shows the timing of timer output (see Table 9-2 for the interval time of the 16-bit timer 20).
Figure 9-7. Timer Output Timing
Count clock
TM20 count value
CR20
INTTM20
TO20
Note
TOF20
0000H
0001H
N
FFFFH 0000H 0001H
N
FFFFH
NN N NN
Interrupt acknowledgement
Interrupt acknowledgement
Overflow flag set
Note The TO20 initial value becomes low level during output enable (TOE20 = 1).
Remark N = 0000H to FFFFH
CHAPTER 9 16-BIT TIMER 20
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9.4.3 Capture operation
The capture operation functions to capture and latch the count value of 16-bit timer counter 20 (TM20) to the
capture register in synchronization with a capture trigger.
Set as shown in Figure 9-8 to allow 16-bit timer 20 to start the capture operation.
Figure 9-8. Settings of 16-Bit Timer Mode Control Register 20 at Capture Operation
– 0/1 0/1 0/1 0/1 0/1 0/1 0/1
TOD
20
TOF
20
CPT201 CPT200
TOC
20
TCL201 TCL200
TOE
20
TMC20
Count clock selection
Capture edge selection (see Table 9-3)
16-bit capture register 20 (TCP20) starts a capture operation after the CPT20 capture trigger edge has been
detected, and latches and retains the count value of 16-bit timer counter 20 (TM20). TCP20 fetches count value
within 2 clocks and retains the count value until the next capture edge detection.
Table 9-3 and Figure 9-9 show the setting contents of the capture edge and capture operation timing, respectively.
Table 9-3. Setting Contents of Capture Edge
CPT201 CPT200 Capture Edge Selection
0 0 Capture operation disabled
0 1 Rising edge of CPT20 pin
1 0 Falling edge of CPT20 pin
1 1 Both edges of CPT20 pin
Caution Because TCP20 is rewritten when a capture trigger edge is detected during a TCP20 read,
disable capture trigger edge detection during a TCP20 read.
Figure 9-9. Capture Operation Timing (With Both Edges of CPT20 Pin Specified)
Count clock
TM20
Counter read buffer
TCP20
CPT20
0000H
0000H
0001H
0001H
Undefined
N
N
N
M – 1 M
M
M
Capture start Capture start
Capture edge detection Capture edge detection
CHAPTER 9 16-BIT TIMER 20
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9.4.4 16-bit timer counter 20 readout
The count value of 16-bit timer counter 20 (TM20) is read out by a 16-bit manipulation instruction.
TM20 readout is performed through a counter read buffer. The counter read buffer latches the TM20 count value,
and buffer operation is held pending at the CPU clock falling edge after the read signal of the TM20 lower byte rises
and the count value is retained. The counter read buffer value in the retention state can be read out as the count
value.
Cancellation of pending is performed at the CPU clock falling edge after the read signal of the TM20 higher byte
falls.
RESET input sets TM20 to 0000H and starts it free running.
Figure 9-10 shows the timing of 16-bit timer counter 20 readout.
Cautions 1. The count value after releasing stop becomes undefined because the count operation is
executed during oscillation stabilization time.
2. Although TM20 is a register dedicated for a 16-bit transfer instruction, an 8-bit transfer
instruction can also be used.
When using an 8-bit transfer instruction, execute it using direct addressing.
3. When using an 8-bit transfer instruction, execute in the order from lower byte to higher byte
in pairs. If only the lower byte is read, the pending state of the counter read buffer is not
canceled, and if only the higher byte is read, an undefined count value is read.
Figure 9-10. 16-Bit Timer Counter 20 Readout Timing
CPU clock
Count clock
TM20
Counter read buffer
TM20 read signal
0000H
0000H
0001H
0001H
N
N
N + 1
Read signal latch
dosabled period
Remark N = 0000H to FFFFH
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9.5 Cautions on Using 16-Bit Timer 20
9.5.1 Restrictions when rewriting 16-bit compare register 20
(1) Disable interrupts (TMMK20 = 1) and the inversion control of timer output (TOC20 = 0) before rewriting the
compare register (CR20).
If CR20 is rewritten with interrupts enabled, an interrupt request may be generated immediately.
(2) Depending on the timing of rewriting the compare register (CR20), the interval time may become twice as
long as the intended time. Similarly, a shorter waveform or twice-longer waveform than the intended timer
output waveform may be output.
To avoid this problem, rewrite the compare register using either of the following procedures A or B.
<Countermeasure A> When rewriting using 8-bit access
<1> Disable interrupts (TMMK20 = 1) and the inversion control of timer output (TOC20 = 0).
<2> First rewrite the higher 1 byte of CR20 (16 bits).
<3> Then rewrite the lower 1 byte of CR20 (16 bits).
<4> Clear the interrupt request flag (TMIF20).
<5> Enable timer interrupts/timer output inversion after half a cycle or more of the count clock has elapsed from
the beginning of the interrupt.
<Program example A> (count clock = 32/fX, CPU clock = fX)
TM20_VCT: SET1 TMMK20 ; Disable timer interrupts (6 clocks)
CLR1 TMC20.3 ; Disable timer output inversion (6 clocks)
MOV A,#xxH ; Set the rewrite value of higher byte (6 clocks)
MOV !0FF17H,A ; Rewrite CR20 higher byte (8 clocks)
MOV A,#yyH ; Set the rewrite value of lower byte (6 clocks)
MOV !0FF16H,A ; Rewrite CR20 lower byte (8 clocks)
CLR1 TMIF20 ; Clear interrupt request flag (6 clocks)
CLR1 TMMK20 ; Enable timer interrupts (6 clocks)
SET1 TMC20.3 ; Enable timer output inversion
Note Because the INTTM20 signal becomes high level for half a cycle of the count clock after an interrupt is
generated, the output is inverted if TOC20 is set to 1 during this period.
Total: 16 clocks or
moreNote
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<Countermeasure B> When rewriting using 16-bit access
<1> Disable interrupts (TMMK20 = 1) and the inversion control of timer output (TOC20 = 0).
<2> Rewrite CR20 (16 bits).
<3> Wait for one cycle or more of the count clock.
<4> Clear the interrupt request flag (TMIF20).
<5> Enable timer interrupts/timer output inversion.
<Program example B> (count clock = 32/fX, CPU clock = fX)
TM20_VCT SET1 TMMK20 ; Disable timer interrupts
CLR1 TMC20.3 ; Disable timer output inversion
MOVW AX,#xxyyH ; Set the rewrite value of CR20
MOVW CR20,AX ; Rewrite CR20
NOP
NOP
: ; 16 NOP instructions (wait for 32/fX)Note
NOP
NOP
CLR1 TMIF20 ; Clear interrupt request flag
CLR1 TMMK20 ; Enable timer interrupts
SET1 TMC20.3 ; Enable timer output inversion
Note Clear the interrupt request flag (TMIF20) after waiting for one cycle or more of the count clock from the
instruction rewriting CR20 (MOVW CR20, AX).
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CHAPTER 10 8-BIT TIMER 30, 40
10.1 8-Bit Timer 30, 40 Functions
An 8-bit timer (one channel, timer 30) and an 8-bit timer/event counter (one channel, timer 40) are incorporated in
the µPD789306, 789316 Subseries. The operation modes listed in the following table can be set via mode register
settings.
Table 10-1. Operation Modes
Channel
Mode
Timer 30 Timer 40
8-bit timer counter mode
(Discrete mode)
Available Available
16-bit timer counter mode
(Cascade connection mode)
Available
Carrier generator mode Available
PWM output mode Not available Available
(1) 8-bit timer counter mode (discrete mode)
The following functions can be used in this mode.
• Interval timer with 8-bit resolution
• External event counter with 8-bit resolution (timer 40 only)
• Square wave output with 8-bit resolution
(2) 16-bit timer counter mode (cascade connection mode)
Operation as a 16-bit timer/event counter is enabled during cascade connection mode.
The following functions can be used in this mode.
• Interval timer with 16-bit resolution
• External event counter with 16-bit resolution
• Square wave output with 16-bit resolution
(3) Carrier generator mode
The carrier clock generated by timer 40 is output in cycles set by timer 30.
(4) PWM output mode (timer 40 only)
Pulses are output using any duty factor set by timer 40.
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10.2 8-Bit Timer 30, 40 Configuration
The 8-bit timer 30, 40 includes the following hardware.
Table 10-2. 8-Bit Timer 30, 40 Configuration
Item Configuration
Timer counters 8 bits × 2 (TM30, TM40)
Registers Compare registers: 8 bits × 3 (CR30, CR40, CRH40)
Timer outputs 2 (TO30, TO40)
Control registers 8-bit timer mode control register 30 (TMC30)
8-bit timer mode control register 40 (TMC40)
Carrier generator output control register 40 (TCA40)
Port mode register 3 (PM3)
Port 3 (P3)
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TCE30
TCL300
TMD300
TCL301
8-bit timer mode
control register 30
(TMC30)
Selector
Decoder
Selector
Selector
8-bit compare
register 30 (CR30)
8-bit timer counter 30
(TM30)
Selector
Internal reset signal
Timer 40 match signal
(during cascade connection mode)
Timer 30 match signal
(during cascade connection mode)
From Figure 10-2 (D)
Count operation start signal
(during cascade connection mode) INTTM30
fCLK/24
fCLK/28
Timer 40 interrupt request signal
(from Figure 10-2 (B))
Carrier clock
(from Figure 10-2 (C))
Clear
Cascade connection mode
Match
From Figure 10-2 (E)
To Figure 10-2 (F)
To Figure 10-2 (G)
Internal bus
OVF
Timer 30 match signal
(during carrier generator mode)
Bit 7 of TM40
(from Figure 10-2 (A))
(A)
(C)
(D)
(E)
(F)
(G)
(B)
TOE30
PM31
P31
output latch
TO30/P31/
INTP1/TMI40
Figure 10-1. Block Diagram of Timer 30
Remark f
CLK: fX or fCC
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TCE40
TCL402 TCL401 TCL400
TMD401
TMD400
TOE40
8-bit timer mode control
register 40 (TMC40)
Decoder
8-bit timer counter 40 (TM40)
F/F
TM30 match signal
(during cascade connection mode)
Count operation start signal to timer 30
(during cascade connection mode) TM40 timer counter match signal
(during cascade connection mode)
Clear
8-bit compare
register 40 (CR40)
Selector
Output control lerNote
RMC40
NRZB40
NRZ40
Carrier generator output
control register 40 (TCA40)
To Figure 10-1 (D)
(D)
(F)
(E) (B)
(A)
(C)
(G)
count clock input
signal to TM30
Internal reset signal
INTTM40
To Figure 10-1 (A)
Bit 7 of TM40
(during cascade connection mode)
From Figure 10-1 (F)
To Figure 10-1 (E)
Match TO40/P32/INTP2
To Figure
10-1
(C)
Carrier clock
Reset
Carrier generator mode
PWM mode
Cascade connection mode
8-bit compare
register H40 (CRH40)
Internal bus
Selector
OVF
To Figure 10-1 (B)
Timer 40 interrupt request signal
From Figure 10-1 (G)
Timer counter match signal from timer 30
(during carrier generator mode)
f
CLK
/2
3
f
CLK
/2
7
TMI40/P31/
INTP1/TO30 TMI/2
TMI/2
2
TMI/2
3
Prescaler
Figure 10-2. Block Diagram of Timer 40
Note For details, see Figure 10-3.
Remark f
CLK: fX or fCC
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Figure 10-3. Block Diagram of Output Controller (Timer 40)
F/F
RMC40 NRZ40
TOE40
PM32
P32
output latch
Selector
TO40/P32/
INTP2
Carrier generator mode
Carrier clock
(1) 8-bit compare register 30 (CR30)
This 8-bit register is used to continually compare the value set to CR30 with the count value in 8-bit timer
counter 30 (TM30) and to generate an interrupt request (INTTM30) when a match occurs.
CR30 is set with an 8-bit memory manipulation instruction.
RESET input makes CR30 undefined.
Caution CR30 cannot be used during PWM output mode.
(2) 8-bit compare register 40 (CR40)
This 8-bit register is used to continually compare the value set to CR40 with the count value in 8-bit timer
counter 40 (TM40) and to generate an interrupt request (INTTM40) when a match occurs. When connected
to TM30 via a cascade connection and used as a 16-bit timer/event counter, the interrupt request (INTTM40)
occurs only when matches occur simultaneously between CR30 and TM30 and between CR40 and TM40
(INTTM30 does not occur).
In carrier generator mode and PWM output mode, this registers is used for low-level width setting.
CR40 is set with an 8-bit memory manipulation instruction.
RESET input makes CR40 undefined.
(3) 8-bit compare register H40 (CRH40)
During carrier generator mode or PWM output mode, the high-level width of timer output is set by writing a
value to CRH40.
The value set in CRH40 is constantly compared with TM40 count value, and an interrupt request (INTTM40)
is generated if they match.
CRH40 is set with an 8-bit memory manipulation instruction.
RESET input makes CRH40 undefined.
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(4) 8-bit timer counters 30 and 40 (TM30 and TM40)
These are 8-bit registers that are used to count the count pulse.
TM30 and TM40 are read with an 8-bit memory manipulation instruction.
RESET input clears TM30 and TM40 to 00H.
TM30 and TM40 are cleared to 00H under the following conditions.
(a) Discrete mode
(i) TM30
• After reset
• When TCE30 (bit 7 of 8-bit timer mode control register 30 (TMC30)) is cleared to 0
• When a match occurs between TM30 and CR30
• When the TM30 count value overflows
(ii) TM40
• After reset
• When TCE40 (bit 7 of 8-bit timer mode control register 40 (TMC40)) is cleared to 0
• When a match occurs between TM40 and CR40
• When the TM40 count value overflows
(b) Cascade connection mode (TM30 and TM40 are simultaneously cleared to 00H)
• After reset
• When the TCE40 flag is cleared to 0
• When matches occur simultaneously between TM30 and CR30 and between TM40 and CR40
• When the TM30 and TM40 count values overflow simultaneously
(c) Carrier generator mode/PWM output mode (TM40 only)
• After reset
• When the TCE40 flag is cleared to 0
• When a match occurs between TM40 and CR40
• When a match occurs between TM40 and CRH40
• When the TM40 count value overflows
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10.3 Registers Controlling 8-Bit Timer 30, 40
The 8-bit timer 30, 40 is controlled by the following five registers.
• 8-bit timer mode control register 30 (TMC30)
• 8-bit timer mode control register 40 (TMC40)
• Carrier generator output control register 40 (TCA40)
• Port mode register 3 (PM3)
• Port 3 (P3)
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(1) 8-bit timer mode control register 30 (TMC30)
8-bit timer mode control register 30 (TMC30) is used to control the timer 30 count clock setting and the
operation mode setting.
TMC30 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMC30 to 00H.
Figure 10-4. Format of 8-Bit Timer Mode Control Register 30
Symbol <7> 6 5 4 3 2 1 <0> Address After reset R/W
TMC30 TCE30 0 0 TCL301 TCL300 0 TMD300 TOE30 FF4DH 00H R/W
TCE30 Control of TM30 count operationNote 1
0 Clears TM30 count value and stops operation
1 Starts count operation
Selection of timer 30 count clock
TCL301 TCL300
During fX = 5.0 MHz operation During fCC = 4.0 MHz operation
0 0
fX/24 (312.5 kHz) fCC/24 (250 kHz)
0 1
fX/28 (19.5 kHz) fCC/28 (15.6 kHz)
1 0 Timer 40 match signal
1 1 Carrier clock (during carrier generator mode) or timer 40 output signal (during a mode other than
carrier generator mode)
TMD300 TMD401 TMD400 Selection of operation mode for timer 30 and timer 40Note 2
0 0 0 8-bit timer counter mode (discrete mode)
1 0 1 16-bit timer counter mode (cascade connection mode)
0 1 1 Carrier generator mode
0 1 0 Timer 40: PWM output mode
Timer 30: 8-bit timer counter mode
Other than above Setting prohibited
TOE30 Control of timer output
0 Output disabled (port mode)
1 Output enabled
Notes 1. Since the count operation is controlled by TCE40 (bit 7 of TMC40) in cascade connection mode, any
setting for TCE30 is ignored.
2. The operation mode selection is set to both the TMC30 register and TMC40 register.
Caution In cascade connection mode, the timer 40 output signal is forcibly selected for the count clock.
Remarks 1. f
X: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. f
CC: Main system clock oscillation frequency (RC oscillation)
CHAPTER 10 8-BIT TIMER 30, 40
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(2) 8-bit timer mode control register 40 (TMC40)
8-bit timer mode control register 40 (TMC40) is used to control the timer 40 count clock setting and the
operation mode setting.
TMC40 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMC40 to 00H.
Figure 10-5. Format of 8-Bit Timer Mode Control Register 40
Symbol <7> 6 5 4 3 2 1 <0> Address After reset R/W
TMC40 TCE40 0 TCL402 TCL401 TCL400 TMD401 TMD400 TOE40 FF4EH 00H R/W
TCE40 Control of TM40 count operationNote 1
0 Clears TM40 count value and stops operation (the count value is also cleared for TM30 during cascade
connection mode)
1 Starts count operation (the count operation is also started for TM30 during cascade connection mode)
Selection of timer 40 count clock
TCL402 TCL401 TCL400
During fX = 5.0 MHz operation During fCC = 4.0 MHz operation
0 0 0
fX/23 (625 kHz) fCC/23 (500 kHz)
0 0 1
fX/27 (39.1 kHz) fCC/27 (31.3 kHz)
0 1 0 fTMI
0 1 1 fTMI/2
1 0 0
fTMI/22
1 0 1
fTMI/23
TMD300 TMD401 TMD400 Selection of operation mode for timer 30 and timer 40Note 2
0 0 0 8-bit timer counter mode (discrete mode)
1 0 1 16-bit timer counter mode (cascade connection mode)
0 1 1 Carrier generator mode
0 1 0 Timer 40: PWM output mode
Timer 30: 8-bit timer counter mode
Other than above Setting prohibited
TOE40 Control of timer output
0 Output disabled (port mode)
1 Output enabled
Notes 1. Since the count operation is controlled by TCE40 (bit 7 of TMC40) in cascade connection mode, any
setting for TCE30 is ignored.
2. The operation mode selection is set to both the TMC30 register and TMC40 register.
Remarks 1. f
X: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. f
CC: Main system clock oscillation frequency (RC oscillation)
3. f
TMI: External clock input from the TMI40 pin
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(3) Carrier generator output control register 40 (TCA40)
This register is used to set the timer output data during carrier generator mode.
TCA40 is set with an 8-bit memory manipulation instruction.
RESET input clears TCA40 to 00H.
Figure 10-6. Format of Carrier Generator Output Control Register 40
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
TCA40 0 0 0 0 0 RMC40 NRZB40 NRZ40 FF4FH 00H W
RMC40 Control of remote control output
0 When NRZ40 = 1, a carrier pulse is output to TO40/INTP2/P32 pin
1 When NRZ40 = 1, high-level signal is output to TO40/INTP2/P32 pin
NRZB40 This is the bit that stores the next data to be output to NRZ40. Data is transferred to NRZ40 at the rising edge
of the timer 30 match signal.
NRZ40 No return zero data
0 Outputs low-level signal (carrier clock is stopped)
1 Outputs carrier pulse or high-level signal
Cautions 1. Bits 3 to 7 must be set to 0.
2. TCA40 cannot be set with a 1-bit memory manipulation instruction. Be sure to use an 8-
bit memory manipulation instruction to set TCA40.
3. The NRZ40 flag can be written only when carrier generator output is stopped (TOE40 =
0). The data cannot be overwritten when TOE40 = 1.
4. When the carrier generator is stopped once and then started again, NRZB40 does not
hold the previous data. Re-set data to NRZB40. At this time, a 1-bit memory
manipulation instruction must not be used. Be sure to use an 8-bit memory
manipulation instruction.
5. To enable operation in the carrier generator mode, set a value to the compare registers
(CR30, CR40, and CRH40), and input the necessary value to the NRZB40 and NRZ40
flags in advance. Otherwise, the signal of the timer match circuit will become unstable
and the NRZ40 flag will be undefined.
6. While INTTM30 (interrupt generated by the match signal of timer 30) is being output,
accessing TCA40 is prohibited.
Accessing TCA40 is prohibited while 8-bit timer counter 30 (TM30) is 00H.
To access TCA40 while TM30 = 00H, wait for more than half a period of the TM30 count
clock and then rewrite TCA40.
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(4) Port mode register 3 (PM3)
This register is used to set the I/O mode of port 3 in 1-bit units.
When using the P31/TO30/INTP1/TMI40 pin as a timer output, set the PM31 and P31 output latch to 0.
When using the P31/TO30/INTP1/TMI40 pin as a timer input, set the PM31 to 1.
When using the P32/TO40/INTP2 pin as a timer output, set the PM32 and P32 output latch to 0.
PM3 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM3 to FFH.
Figure 10-7. Format of Port Mode Register 3
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
PM3 1 1 1 1 PM33 PM32 PM31 PM30 FF23H FFH R/W
PM3n I/O mode of P3n pin
(n = 0 to 3)
0 Output mode (output buffer is ON)
1 Input mode (output buffer is OFF)
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10.4 8-Bit Timer 30, 40 Operation
10.4.1 Operation as 8-bit timer counter
Timer 30 and timer 40 can independently be used as an 8-bit timer counter.
The following modes can be used for the 8-bit timer counter.
• Interval timer with 8-bit resolution
• External event counter with 8-bit resolution (timer 40 only)
• Square wave output with 8-bit resolution
(1) Operation as interval timer with 8-bit resolution
The interval timer with 8-bit resolution repeatedly generates an interrupt at a time interval specified by the
count value preset in 8-bit compare register n0 (CRn0).
To operate 8-bit timer n0 as an interval timer, settings must be made in the following sequence.
<1> Disable operation of 8-bit timer counter n0 (TMn0) (TCEn0 = 0).
<2> Disable timer output of TOn0 (TOEn0 = 0).
<3> Set a count value in CRn0.
<4> Set the operation mode of timer n0 to 8-bit timer counter mode (see Figures 10-4 and 10-5).
<5> Set the count clock for timer n0 (see Tables 10-3 to 10-6).
<6> Enable the operation of TMn0 (TCEn0 = 1).
When the count value of 8-bit timer counter n0 (TMn0) matches the value set in CRn0, TMn0 is cleared to
00H and continues counting. At the same time, an interrupt request signal (INTTMn0) is generated.
Tables 10-3 to 10-6 show interval time, and Figures 10-8 to 10-12 show the timing of the interval timer
operation.
Caution Be sure to stop the timer operation before overwriting the count clock with different data.
Remark n = 3, 4
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Table 10-3. Interval Time of Timer 30 (During fX = 5.0 MHz Operation)
TCL301 TCL300 Minimum Interval Time Maximum Interval Time Resolution
0 0 24/fX (3.2
µ
s) 212/fX (0.82 ms) 24/fX (3.2
µ
s)
0 1 28/fX (51.2
µ
s) 216/fX (13.1 ms) 28/fX (51.2
µ
s)
1 0 Input cycle of timer 40
match signal
Input cycle of timer 40
match signal × 28
Input cycle of timer 40
match signal
1 1 Input cycle of timer 40
output
Input cycle of timer 40
output × 28
Input cycle of timer 40
Remark fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
Table 10-4. Interval Time of Timer 30 (During fCC = 4.0 MHz Operation)
TCL301 TCL300 Minimum Interval Time Maximum Interval Time Resolution
0 0 24/fCC (4.0
µ
s) 212/fCC (1.02 ms) 24/fCC (4.0
µ
s)
0 1 28/fCC (64
µ
s) 216/fCC (16.4 ms) 28/fCC (64
µ
s)
1 0 Input cycle of timer 40
match signal
Input cycle of timer 40
match signal × 28
Input cycle of timer 40
match signal
1 1 Input cycle of timer 40
output
Input cycle of timer 40
output × 28
Input cycle of timer 40
Remark fCC: Main system clock oscillation frequency (RC oscillation)
Table 10-5. Interval Time of Timer 40 (During fX = 5.0 MHz Operation)
TCL402 TCL401 TCL400 Minimum Interval Time Maximum Interval Time Resolution
0 0 0 23/fX (1.6
µ
s) 211/fX (0.41 ms) 23/fX (1.6
µ
s)
0 0 1 27/fX (25.6
µ
s) 215/fX (6.55 ms) 27/fX (25.6
µ
s)
0 1 0 fTMI input cycle fTMI input cycle × 28 fTMI input cycle
0 1 1 fTMI/2 input cycle fTMI/2 input cycle × 28 fTMI/2 input cycle
1 0 0 fTMI/22 input cycle fTMI/22 input cycle × 28 fTMI/22 input cycle
1 0 1 fTMI/23 input cycle fTMI/23 input cycle × 28 fTMI/23 input cycle
Remark fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
Table 10-6. Interval Time of Timer 40 (During fCC = 4.0 MHz Operation)
TCL402 TCL401 TCL400 Minimum Interval Time Maximum Interval Time Resolution
0 0 0 23/fCC (2.0
µ
s) 211/fCC (0.51 ms) 23/fCC (2.0
µ
s)
0 0 1 27/fCC (32
µ
s) 215/fCC (8.19 ms) 27/fCC (32
µ
s)
0 1 0 fTMI input cycle fTMI input cycle × 28 fTMI input cycle
0 1 1 fTMI/2 input cycle fTMI/2 input cycle × 28 fTMI/2 input cycle
1 0 0 fTMI/22 input cycle fTMI/22 input cycle × 28 fTMI/22 input cycle
1 0 1 fTMI/23 input cycle fTMI/23 input cycle × 28 fTMI/23 input cycle
Remark fCC: Main system clock oscillation frequency (RC oscillation)
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Figure 10-8. Timing of Interval Timer Operation with 8-Bit Resolution (Basic Operation)
Count stop
count clock
TMn0
CRn0
TCEn0
INTTMn0
TOn0
N
t
TMn0 N00H 01H N00H 01H N00H 00H
01H
00H 01H
Clear Clear Clear
Count start
Interrupt acknowledgement Interrupt acknowledgement
Interrupt acknowledgement
Interval time Interval time
Remarks 1. Interval time = (N + 1) × t: N = 00H to FFH
2. n = 3, 4
Figure 10-9. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Cleared to 00H)
count clock
CRn0
TCEn0
INTTMn0
TOn0
00H
TMn0 00H
Count start
TMn0
Remark n = 3, 4
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Figure 10-10. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to FFH)
count clock
CRn0
TCEn0
INTTMn0
TOn0
FFH
TMn0 FFH 00H 01H 00H 01H 00H
00H 01H FFH FFH FFH 00H
Clear Clear Clear
Count start
TMn0
Remark n = 3, 4
Figure 10-11. Timing of Interval Timer Operation with 8-Bit Resolution
(When CRn0 Changes from N to M (N < M))
count clock
CRn0
TCEn0
INTTMn0
TOn0
TMn0
TMn0
N00H 00H N00H 01H
00H 01H MNM
NM
Clear Clear Clear
Count start
Interrupt acknowledgement Interrupt acknowledgement
CRn0 overwritten
Remark n = 3, 4
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Figure 10-12. Timing of Interval Timer Operation with 8-Bit Resolution
(When CRn0 Changes from N to M (N > M))
count clock
CRn0
TCEn0
INTTMn0
TOn0
TMn0
TMn0
00H 00H 00H
N − 1 NMN M
NM
00H FFH M
H
Clear Clear Clear
TMn0 overflows
because M < N
CRn0 overwritten
Remark n = 3, 4
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Figure 10-13. Timing of Interval Timer Operation with 8-Bit Resolution
(When Timer 40 Match Signal Is Selected for Timer 30 Count Clock)
Timer 40
count clock
CR40
TCE40
INTTM40
TO40
TM40 N00H M00H
00H 01H M
NM
00H M00H
00H 02H Y
01H 00H Y00H
Y
TO30
INTTM30
TCE30
CR30
TM30
Input clock to timer 30
(timer 40 match signal)
Clear Clear Clear Clear
Count start
Count start
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(2) Operation as external event counter with 8-bit resolution (timer 40 only)
The external event counter counts the number of external clock pulses input to the TMI40/P31/INTP1/TO30
pin by using 8-bit timer counter 40 (TM40).
To operate timer 40 as an external event counter, settings must be made in the following sequence.
<1> Disable operation of 8-bit timer counter 40 (TM40) (TCE40 = 0).
<2> Disable timer output of TO40 (TOE40 = 0).
<3> Set P31 to input mode (PM31 = 1).
<4> Select the external input clock for timer 40 (see Tables 10-5 and 10-6).
<5> Set the operation mode of timer 40 to 8-bit timer counter mode (see Figure 10-5).
<6> Set a count value in CR40.
<7> Enable the operation of TM40 (TCE40 = 1).
Note This operation only applies to timer 40.
Each time the valid edge is input, the value of TM40 is incremented.
When the count value of TM40 matches the value set in CR40, TM40 is cleared to 00H and continues
counting. At the same time, an interrupt request signal (INTTM40) is generated.
Figure 10-14 shows the timing of the external event counter operation.
Caution Be sure to stop the timer operation before overwriting the count clock with different data.
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Figure 10-14. Timing of Operation of External Event Counter with 8-Bit Resolution
TMI40 pin input
TM40 count value
CR40
TCE40
INTTM40
00H 01H 02H 03H 04H 05H N − 1 N 00H 01H 02H 03H
N
Remark N = 00H to FFH
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(3) Operation as square-wave output with 8-bit resolution
Square waves of any frequency can be output at an interval specified by the value preset in 8-bit compare
register n0 (CRn0).
To operate timer n0 for square-wave output, settings must be made in the following sequence.
<1> When using timer 30, set P31 to output mode (PM31 = 0).
When using timer 40, set P32 to output mode (PM32 = 0).
<2> Set the output latches of P31 and P32 to 0.
<3> Disable operation of timer counter n0 (TMn0) (TCEn0 = 0).
<4> Set a count clock for timer n0 and enable output of TOn0 (TOEn0 = 1).
<5> Set a count value in CRn0.
<6> Enable the operation of TMn0 (TCEn0 = 1).
When the count value of TMn0 matches the value set in CRn0, the TOn0 pin output will be inverted. Through
application of this mechanism, square waves of any frequency can be output. As soon as a match occurs,
TMn0 is cleared to 00H and continues counting. At the same time, an interrupt request signal (INTTMn0) is
generated.
The square-wave output is cleared to 0 by setting TCEn0 to 0.
Tables 10-7 to 10-10 show the square-wave output range, and Figure 10-15 shows the timing of square-wave
output.
Caution Be sure to stop the timer operation before overwriting the count clock with different data.
Remark n = 3, 4
Table 10-7. Square-Wave Output Range of Timer 30 (During fX = 5.0 MHz Operation)
TCL301 TCL300 Minimum Pulse Width Maximum Pulse Width Resolution
0 0
24/fX (3.2
µ
s) 212/fX (0.82 ms) 24/fX (3.2
µ
s)
0 1
28/fX (51.2
µ
s) 216/fX (13.1 ms) 28/fX (51.2
µ
s)
Remark fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
Table 10-8. Square-Wave Output Range of Timer 30 (During fCC = 4.0 MHz Operation)
TCL301 TCL300 Minimum Pulse Width Maximum Pulse Width Resolution
0 0
24/fCC (4.0
µ
s) 212/fCC (1.02 ms) 24/fCC (4.0
µ
s)
0 1
28/fCC (64
µ
s) 216/fCC (16.4 ms) 28/fCC (64
µ
s)
Remark fCC: Main system clock oscillation frequency (RC oscillation)
Table 10-9. Square-Wave Output Range of Timer 40 (During fX = 5.0 MHz Operation)
TCL402 TCL401 TCL400 Minimum Pulse Width Maximum Pulse Width Resolution
0 0 0
23/fX (1.6
µ
s) 211/fX (0.41 ms) 23/fX (1.6
µ
s)
0 0 1
27/fX (25.6
µ
s) 215/fX (6.55 ms) 27/fX (25.6
µ
s)
Remark fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
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Table 10-10. Square-Wave Output Range of Timer 40 (During fCC = 4.0 MHz Operation)
TCL402 TCL401 TCL400 Minimum Pulse Width Maximum Pulse Width Resolution
0 0 0
23/fCC (2.0
µ
s) 211/fCC (0.51 ms) 23/fCC (2.0
µ
s)
0 0 1
27/fCC (32
µ
s) 215/fCC (8.19 ms) 27/fCC (32
µ
s)
Remark fCC: Main system clock oscillation frequency (RC oscillation)
Figure 10-15. Timing of Square-Wave Output with 8-Bit Resolution
count clock
CRn0
TCEn0
INTTMn0
TOn0
Note
N
TMn0
TMn0
N00H 01H N00H 01H N00H 01H
00H 01H
Clear Clear Clear
Count start
Interrupt acknowledgement Interrupt acknowledgement
Interrupt acknowledgement
Note The initial value of TOn0 is low level when output is enabled (TOEn0 = 1).
Remark n = 3, 4
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10.4.2 Operation as 16-bit timer counter
Timer 30 and timer 40 can be used as a 16-bit timer counter using cascade connection. In this case, 8-bit timer
counter 30 (TM30) is the higher 8 bits and 8-bit timer counter 40 (TM40) is the lower 8 bits. 8-bit timer 40 controls
reset and clear.
The following modes can be used for the 16-bit timer counter.
• Interval timer with 16-bit resolution
• External event counter with 16-bit resolution
• Square-wave output with 16-bit resolution
(1) Operation as interval timer with 16-bit resolution
The interval timer with 16-bit resolution repeatedly generates an interrupt at a time interval specified by the
count value preset in 8-bit compare register 30 (CR30) and 8-bit compare register 40 (CR40).
To operate as an interval timer with 16-bit resolution, settings must be made in the following sequence.
<1> Disable operation of 8-bit timer counter 30 (TM30) and 8-bit timer counter 40 (TM40) (TCE30 = 0,
TCE40 = 0).
<2> Disable timer output of TO40 (TOE40 = 0).
<3> Set the count clock for timer 40 (see Tables 10-5 and 10-6).
<4> Set the operation mode of timer 30 and 8-bit timer 40 to 16-bit timer counter mode (see Figures 10-4
and 10-5).
<5> Set a count value in CR30 and CR40.
<6> Enable the operation of TM30 and TM40 (TCE40 = 1Note).
Note Start and clear of the timer in the 16-bit timer counter mode are controlled by TCE40 (the value of
TCE30 is invalid).
When the count values of TM30 and TM40 match the values set in CR30 and CR40 respectively, both TM30 and
TM40 are simultaneously cleared to 00H and counting continues. At the same time, an interrupt request signal
(INTTM40) is generated (INTTM30 is not generated).
Tables 10-11 and 10-12 show interval time, and Figure 10-16 shows the timing of the interval timer operation.
Cautions 1. Be sure to stop the timer operation before overwriting the count clock with different data.
2. In the 16-bit timer counter mode, TO30 cannot be used. Be sure to set TOE30 = 0 to disable
TO30 output.
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Table 10-11. Interval Time with 16-Bit Resolution (During fX = 5.0 MHz Operation)
TCL402 TCL401 TCL400 Minimum Interval Time Maximum Interval Time Resolution
0 0 0 23/fX (1.6
µ
s) 219/fX (0.10 s) 23/fX (1.6
µ
s)
0 0 1 27/fX (25.6
µ
s) 223/fX (1.68 s) 27/fX (25.6
µ
s)
0 1 0 fTMI input cycle fTMI input cycle × 216 fTMI input cycle
0 1 1 fTMI/2 input cycle fTMI/2 input cycle × 216 fTMI/2 input cycle
1 0 0 fTMI/22 input cycle fTMI/22 input cycle × 216 fTMI/22 input cycle
1 0 1 fTMI/23 input cycle fTMI/23 input cycle × 216 fTMI/23 input cycle
Remark fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
Table 10-12. Interval Time with 16-Bit Resolution (During fCC = 4.0 MHz Operation)
TCL402 TCL401 TCL400 Minimum Interval Time Maximum Interval Time Resolution
0 0 0 23/fCC (2.0
µ
s) 219/fCC (0.13 s) 23/fCC (2.0
µ
s)
0 0 1 27/fCC (32
µ
s) 223/fCC (2.10 s) 27/fCC (32
µ
s)
0 1 0 fTMI input cycle fTMI input cycle × 216 fTMI input cycle
0 1 1 fTMI/2 input cycle fTMI/2 input cycle × 216 fTMI/2 input cycle
1 0 0 fTMI/22 input cycle fTMI/22 input cycle × 216 fTMI/22 input cycle
1 0 1 fTMI/23 input cycle fTMI/23 input cycle × 216 fTMI/23 input cycle
Remark fCC: Main system clock oscillation frequency (RC oscillation)
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Interval time
count clock
TM40
CR40
TCE40
INTTM40
TO40
FFH 00H7FH
00H
N00H
NN N N
80H 7FH 80H FFH 00H N00H
NNN
TM30
TM40
count clock
TM30
00H X
X − 1
01H
CR30 XXX
7FH 80H FFH 00H N00H
NNN
X
X − 1 00H
t
Not cleared because TM30 does not match Cleared because TM30 and TM40 match simultaneously
Count start
Interrupt not generated because
TM30 does not match Interrupt acknowledgement Interrupt acknowledgement
Remark Interval time = (256X + N + 1) × t: X = 00H to FFH, N = 00H to FFH
Figure 10-16. Timing of Interval Timer Operation with 16-Bit Resolution
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(2) Operation as external event counter with 16-bit resolution
The external event counter counts the number of external clock pulses input to the TMI40/P31/INTP1/TO30
pin by TM30 and TM40.
To operate as an external event counter with 16-bit resolution, settings must be made in the following
sequence.
<1> Disable operation of TM30 and TM40 (TCE30 = 0, TCE40 = 0).
<2> Disable timer output of TO40 (TOE40 = 0).
<3> Set P31 to input mode (PM31 = 1).
<4> Select the external input clock for timer 40 (see Tables 10-5 and 10-6).
<5> Set the operation mode of timer 30 and 8-bit timer 40 to 16-bit timer counter mode (see Figures 10-4
and 10-5).
<6> Set a count value in CR30 and CR40.
<7> Enable the operation of TM30 and TM40 (TCE40 = 1Note).
Note Start and clear of the timer in the 16-bit timer counter mode are controlled by TCE40 (the value of
TCE30 is invalid).
Each time the valid edge is input, the values of TM30 and TM40 are incremented.
When the count values of TM30 and TM40 simultaneously match the values set in CR30 and CR40
respectively, both TM30 and TM40 are cleared to 00H and counting continues. At the same time, an interrupt
request signal (INTTM40) is generated (INTTM30 is not generated).
Figure 10-17 shows the timing of the external event counter operation.
Caution Be sure to stop the timer operation before overwriting the count clock with different data.
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TMI40 pin input
TM40
CR40
TCE40
INTTM40
FFH 00H7FH
00H
N00H
NN N N
80H 7FH 80H FFH 00H N00H
NNN
TM30 count clock
TM30 00H X
01H
CR30 XXX
7FH 80H FFH 00H N00H
NNN
X
X − 1 00H
X − 1
Not cleared because TM30 does not match Cleared because TM30 and TM40 match simultaneously
Count start
Interrupt not generated because
TM30 does not match Interrupt acknowledgement Interrupt
acknowledgement
Remark X = 00H to FFH, N = 00H to FFH
Figure 10-17. Timing of External Event Counter Operation with 16-Bit Resolution
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(3) Operation as square-wave output with 16-bit resolution
Square waves of any frequency can be output at an interval specified by the count value preset in CR30 and
CR40.
To operate as a square-wave output with 16-bit resolution, settings must be made in the following sequence.
<1> Disable operation of TM30 and TM40 (TCE30 = 0, TCE40 = 0).
<2> Disable output of TO30 and TO40 (TOE30 = 0, TOE40 = 0).
<3> Set a count clock for timer 40.
<4> Set P32 to output mode (PM32 = 0) and P32 output latch to 0 and enable TO40 output (TOE40 = 1)
(TO30 cannot be used).
<5> Set count values in CR30 and CR40.
<6> Enable the operation of TM40 (TCE40 = 1Note).
Note Start and clear of the timer in the 16-bit timer counter mode are controlled by TCE40 (the value of
TCE30 is invalid).
When the count values of TM30 and TM40 simultaneously match the values set in CR30 and CR40
respectively, the TO40 pin output will be inverted. Through application of this mechanism, square waves of
any frequency can be output. As soon as a match occurs, TM30 and TM40 are cleared to 00H and counting
continues. At the same time, an interrupt request signal (INTTM40) is generated (INTTM30 is not generated).
The square-wave output is cleared to 0 by setting TCE40 to 0.
Tables 10-13 and 10-14 show the square wave output range, and Figure 10-18 shows timing of square wave
output.
Cautions 1. Be sure to stop the timer operation before overwriting the count clock with different
data.
2. In the 16-bit timer counter mode, TO30 cannot be used. Be sure to set TOE30 = 0 to
disable TO30 output.
Table 10-13. Square-Wave Output Range with 16-Bit Resolution (During fX = 5.0 MHz Operation)
TCL402 TCL401 TCL400 Minimum Pulse Width Maximum Pulse Width Resolution
0 0 0
23/fX (1.6
µ
s) 219/fX (0.10 s) 23/fX (1.6
µ
s)
0 0 1
27/fX (25.6
µ
s) 223/fX (1.68 s) 27/fX (25.6
µ
s)
Remark fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
Table 10-14. Square-Wave Output Range with 16-Bit Resolution (During fCC = 4.0 MHz Operation)
TCL402 TCL401 TCL400 Minimum Pulse Width Maximum Pulse Width Resolution
0 0 0
23/fCC (2.0
µ
s) 219/fCC (0.13 s) 23/fCC (2.0
µ
s)
0 0 1
27/fCC (32
µ
s) 223/fCC (2.10 s) 27/fCC (32
µ
s)
Remark fCC: Main system clock oscillation frequency (RC oscillation)
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Count clock
Count value
CR40
TCE40
INTTM40
TO40
Note
FFH 00H7FH
00H
N00H
NN N N
80H 7FH 80H FFH 00H N00H
NNN
Count clock
TM40
TM40
Count value
TM30
TM30
00H X
X − 1
01H
CR30 XXX
7FH 80H FFH 00H N00H
NNN
X
X − 1 00H
Not cleared because TM30 does not match Cleared because TM30 and TM40 match simultaneously
Count start
Interrupt not generated because
TM30 does not match Interrupt acknowledgement
Interrupt acknowledgement
Figure 10-18. Timing of Square-Wave Output with 16-Bit Resolution
Note The initial value of TO40 is low level when output is enabled (TOE40 = 1).
Remark X = 00H to FFH, N = 00H to FFH
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10.4.3 Operation as carrier generator
An arbitrary carrier clock generated by TM40 can be output in the cycle set in TM30.
To operate timer 30 and timer 40 as carrier generators, settings must be made in the following sequence.
<1> Disable operation of TM30 and TM40 (TCE30 = 0, TCE40 = 0).
<2> Disable timer output of TO30 and TO40 (TOE30 = 0, TOE40 = 0).
<3> Set count values in CR30, CR40, and CRH40.
<4> Set the operation mode of timer 30 and timer 40 to carrier generator mode (see Figures 10-4 and 10-5).
<5> Set the count clock for timer 30 and timer 40.
<6> Set remote control output to carrier pulse (RMC40 (bit 2 of carrier generator output control register 40
(TCA40)) = 0).
Input the required value to NRZB40 (bit 1 of TCA40) by program.
Input a value to NRZ40 (bit 0 of TCA40) before it is reloaded from NRZB40.
<7> Set P32 to output mode (PM32 = 0) and the P32 output latch to 0 and enable TO40 output by setting TOE40
to 1.
<8> Enable the operation of TM30 and TM40 (TCE30 = 1, TCE40 = 1).
<9> Save the value of NRZB40 to a general-purpose register.
<10> When INTTM30 rises, the value of NRZB40 is transferred to NRZ40. After that, rewrite TCA40 with an 8-bit
memory manipulation instruction. Input the value to be transferred to NRZ40 next time to NRZB40, and input
the value saved in <9> to NRZ40.
<11> Generate the desired carrier signal by repeating <9> and <10>.
The operation of the carrier generator is as follows.
<1> When the count value of TM40 matches the value set in CR40, an interrupt request signal (INTTM40) is
generated and output of timer 40 is inverted, which makes the compare register switch from CR40 to CRH40.
<2> After that, when the count value of TM40 matches the value set in CRH40, an interrupt request signal
(INTTM40) is generated and output of timer 40 is inverted again, which makes the compare register switch
from CRH40 to CR40.
<3> The carrier clock is generated by repeating <1> and <2> above.
<4> When the count value of TM30 matches the value set in CR30, an interrupt request signal (INTTM30) is
generated. The rising edge of INTTM30 is the data reload signal of NRZB40 and is transferred to NRZ40.
<5> When NRZ40 is 1, a carrier clock is output from TO40 pin.
Cautions 1. TCA40 cannot be set with a 1-bit memory manipulation instruction. Be sure to use an 8-bit
memory manipulation instruction.
2. The NRZ40 flag can be rewritten only when the carrier generator output is stopped (TOE40
= 0). The data of the flag is not changed even if a write instruction is executed while TOE40
= 1.
3. When setting the carrier generator operation again after stopping it once, reset NRZB40
because the previous value is not retained. In this case also a 1-bit memory manipulation
instruction cannot be used. Be sure to use an 8-bit memory manipulation instruction.
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Cautions 4. To enable operation in the carrier generator mode, set a value to the compare registers
(CR30, CR40, and CRH40), and input the necessary value to the NRZB40 and NRZ40 flags in
advance. Otherwise, the signal of the timer match circuit will become unstable and the
NRZ40 flag will be undefined.
5. While INTTM30 (interrupt generated by the match signal of timer 30) is being output,
accessing TCA40 is prohibited.
Accessing TCA40 is prohibited while 8-bit timer counter 30 (TM30) is 00H.
To access TCA40 while TM30 = 00H, wait for more than half a period of the TM30 count
clock and then rewrite TCA40.
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Figures 10-19 to 10-21 show the operation timing of the carrier generator.
Figure 10-19. Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M > N))
TM40
count clock
TM40
count value
CR40
TCE40
INTTM40
M
00HN00H 01H
N
CRH40 M
N00H
Carrier clock
N00H 00H N M
00H 01H X00H 01H X 00H 01H X00H X00H 01H
TM30
count value
CR30
TCE30
INTTM30
TM30
count clock
01010
0101
0
NRZB40
NRZ40
TO40
Carrier clock
X
Count start
Clear Clear Clear Clear
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Figure 10-20. Timing of Carrier Generator Operation
(When CR40 = N, CRH40 = M (M < N))
TM40
count clock
TM40
count value
CR40
TCE40
INTTM40
N
00H
N
CRH40 M
Carrier clock
N
00H
00H 01H X00H 01H X00H 01H X00H X 00H 01H
TM30
count value
CR30
TCE30
INTTM30
TM30
count clock
01010
0101
0
NRZB40
NRZ40
TO40
Carrier clock
M00H MM00H M00H
X
Count start
Clear Clear Clear Clear
Remark This timing chart shows an example in which the value of NRZ40 is changed while the carrier clock is
high.
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Figure 10-21. Timing of Carrier Generator Operation (When CR40 = CRH40 = N)
Count clock
TM40
count value
CR40
TM40
TM30
TCE40
INTTM40
N
00H00H 00H
N
X
CRH40 N
N
Carrier clock
00H 00H N N
00H 01H X00H 01H X00H 01H X00H X00H 01H
TM30
CR30
TCE30
INTTM30
Count clock
01010
0101
0
NRZB40
NRZ40
TO40
Carrier clock
NN00H
Clear Clear Clear Clear Clear
Count start
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10.4.4 Operation as PWM output (timer 40 only)
In the PWM output mode, a pulse of any duty ratio can be output by setting a low-level width using CR40 and a
high-level width using CRH40.
To operate timer 40 in PWM output mode, settings must be made in the following sequence.
<1> Disable operation of TM40 (TCE40 = 0).
<2> Disable timer output of TO40 (TOE40 = 0).
<3> Set count values in CR40 and CRH40.
<4> Set the operation mode of timer 40 to carrier generator mode (see Figure 10-5).
<5> Set the count clock for timer 40.
<6> Set P32 to output mode (PM32 = 0) and the P32 output latch to 0 and enable timer output of TO40 (TOE40 =
1).
<7> Enable the operation of TM40 (TCE40 = 1).
The operation in the PWM output mode is as follows.
<1> When the count value of TM40 matches the value set in CR40, an interrupt request signal (INTTM40) is
generated and output of timer 40 is inverted, which makes the compare register switch from CR40 to CRH40.
<2> A match between TM40 and CR40 clears the TM40 value to 00H and then counting starts again.
<3> After that, when the count value of TM40 matches the value set in CRH40, an interrupt request signal
(INTTM40) is generated and output of timer 40 is inverted again, which makes the compare register switch
from CRH40 to CR40.
<4> A match between TM40 and CRH40 clears the TM40 value to 00H and then counting starts again.
A pulse of any duty ratio is output by repeating <1> to <4> above. Figures 10-22 and 10-23 show the operation
timing in the PWM output mode.
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Figure 10-22. PWM Output Mode Timing (Basic Operation)
count clock
TM40
count value
CR40
TCE40
TM40
INTTM40
00H
N
00H 01H
N
CRH40 M
N
TO40
Note
00H 00H
01H M01H 01H M00H
Clear Clear Clear Clear
Count start
Note The initial value of TO40 is low level when output is enabled (TOE40 = 1).
Figure 10-23. PWM Output Mode Timing (When CR40 and CRH40 Are Overwritten)
Count clock
TM40
count value
CR40
TCE40
TM40
INTTM40
00H
N
00H 01H
N
CRH40 M
N
TO40
Note
M
X
Y00H 00H X
00H
X
YM
Clear Clear Clear Clear
Count start
Note The initial value of TO40 is low level when output is enabled (TOE40 = 1).
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10.5 Notes on Using 8-Bit Timer 30, 40
(1) Error on starting timer
An error of up to 1.5 clocks is included in the time between when the timer is started and a match signal is
generated. This is because the counter may be incremented by detecting a rising edge at the timing at which
the timer starts while the count clock is high level (see Figure 10-24).
Figure 10-24. Case in Which Error of 1.5 Clocks (Max.) Occurs
TCEn0
TCEn0
00H 01H 02H 03H
If delay A > delay B when the timer starts while the selected
clock is high level, an error of 1.5 clocks (max.) occurs.
TMn0 count value
Count pulse
Clear signal
Selected clock
Clear signal
8-bit timer counter n0
(TMn0)
Count
pulse
Delay A
Delay A
Delay B
Delay B
Selected clock
Remark n = 3, 4
(2) Count value if external clock input from TMI40 pin is selected
When the external clock signal input from the TMI40 pin is selected as the count clock, the count value may
start from 01H if the timer is enabled (TCE40 = 0 → 1) while the TMI40 pin is high. This is because the input
signal of the TMI40 pin is internally ANDed with the TCE40 signal. Consequently, the counter is incremented
because the rising edge of the count clock is input to the timer immediately when the TCE40 pin is set.
Depending on the delay timing, the count value is incremented by one if the rising edge is input after the
counter is cleared. Counting is not affected if the rising edge is input before the counter is cleared (the
counter operates normally).
Use the timer being aware that it has an error of one count, or take either of the following actions A or B.
<Action A> Always start the timer when the TMI40 pin is low.
<Action B> Save the count value to a control register when the timer is started, subtract the count value from
the count value saved to the control register when reading the count value, and take the result as
the true count value.
CHAPTER 10 8-BIT TIMER 30, 40
User’s Manual U14800EJ3V0UD
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Figure 10-25. Counting Operation if Timer Is Started When TMI40 Is High
TCE40 flag
TMI40
H
Rising edge
detector Counter
Clear
Increment
Remark n = 0, 1
(3) Setting of 8-bit compare register n0
8-bit compare register n0 (CRn0) can be cleared to 00H.
Therefore, one pulse can be counted when the 8-bit timer operates as an event counter.
Figure 10-26. Timing of Operation as External Event Counter (8-Bit Resolution)
TMI40 input
CR40 00H
TM40
count value 00H 00H 00H 00H
Interrupt request flag
Remark n = 3, 4
168 User’s Manual U14800EJ3V0UD
CHAPTER 11 WATCH TIMER
11.1 Watch Timer Functions
The watch timer has the following functions.
• Watch timer
• Interval timer
The watch and interval timers can be used at the same time.
Figure 11-1 is a block diagram of the watch timer.
Figure 11-1. Watch Timer Block Diagram
f
CLK
/2
7
f
XT
f
W
f
W
2
4
f
W
2
5
f
W
2
6
f
W
2
7
f
W
2
8
f
W
2
9
Clear
9-bit prescaler
Selecter
Clear
5-bit counter INTWT
INTWTI
WTM7 WTM6 WTM5 WTM4 WTM1 WTM0
Watch timer mode
control register (WTM)
Internal bus
Selecter
Remark fCLK: fX or fCC
CHAPTER 11 WATCH TIMER
User’s Manual U14800EJ3V0UD 169
(1) Watch timer
The 4.19 MHz main system clock or 32.768 kHz subsystem clock is used to generate an interrupt request
(INTWT) at 0.5-second intervals.
Caution When the main system clock is operating at 5.0 MHz (ceramic/crystal oscillation) or 4.0 MHz
(RC oscillation), it cannot be used to generate a 0.5-second interval. In this case, the
subsystem clock, which operates at 32.768 kHz, should be used instead.
(2) Interval timer
The interval timer is used to generate an interrupt request (INTWT) at specified intervals.
Table 11-1. Interval Time of Interval Timer (Ceramic/Crystal Oscillation)
Interval During fX = 5.0 MHz Operation During fX = 4.19 MHz Operation During fXT = 32.768 kHz Operation
24 × 1/fW 409.6
µ
s 488
µ
s 488
µ
s
25 × 1/fW 819.2
µ
s 977
µ
s 977
µ
s
26 × 1/fW 1.64 ms 1.95 ms 1.95 ms
27 × 1/fW 3.28 ms 3.91 ms 3.91 ms
28 × 1/fW 6.55 ms 7.81 ms 7.81 ms
29 × 1/fW 13.1 ms 15.6 ms 15.6 ms
Remarks 1. f
W: Watch timer clock frequency (fX/27 or fXT)
2. f
X: Main system clock oscillation frequency (ceramic/crystal oscillation)
3. f
XT: Subsystem clock oscillation frequency
Table 11-2. Interval Time of Interval Timer (RC Oscillation)
Interval During fCC = 4.0 MHz Operation During fXT = 32.768 kHz Operation
24 × 1/fW 512
µ
s 488
µ
s
25 × 1/fW 1.02 ms 977
µ
s
26 × 1/fW 2.05 ms 1.95 ms
27 × 1/fW 4.10 ms 3.91 ms
28 × 1/fW 8.19 ms 7.81 ms
29 × 1/fW 16.4 ms 15.6 ms
Remarks 1. f
W: Watch timer clock frequency (fCC/27 or fXT)
2. f
CC: Main system clock oscillation frequency (RC oscillation)
3. f
XT: Subsystem clock oscillation frequency
CHAPTER 11 WATCH TIMER
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11.2 Watch Timer Configuration
The watch timer includes the following hardware.
Table 11-3. Watch Timer Configuration
Item Configuration
Counter 5 bits × 1
Prescaler 9 bits × 1
Control register Watch timer mode control register (WTM)
CHAPTER 11 WATCH TIMER
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11.3 Register Controlling Watch Timer
The watch timer mode control register (WTM) is used to control the watch timer.
• Watch timer mode control register (WTM)
WTM selects a count clock for the watch timer and specifies whether to enable clocking of the timer. It also
specifies the prescaler interval and how the 5-bit counter is controlled.
WTM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears WTM to 00H.
Figure 11-2. Format of Watch Timer Mode Control Register
Watch timer count clock selection
During f
X
= 5.0 MHz, f
XT
= 32.768 kHz operation During f
CC
= 4.0 MHz, f
XT
= 32.768 kHz operation
WTM7 WTM6 WTM5 WTM4 0 0 WTM1 WTM0WTM
Symbol Address After reset R/W
FF4AH 00H R/W
765432<1><0>
WTM7
0
1
Prescaler interval selectionWTM6
0
0
0
0
1
1
2
4
/f
W
2
5
/f
W
2
6
/f
W
2
7
/f
W
2
8
/f
W
2
9
/f
W
WTM5
0
0
1
1
0
0
WTM4
0
1
0
1
0
1
Control of 5-bit counter operation
WTM1
0
1
Cleared after stop
Started
Watch timer operationWTM0
0
1
Operation stopped (both prescaler and timer cleared)
Operation enabled
Other than above
f
X
/2
7
f
XT
(39.1 kHz)
(32.768 kHz)
f
CC
/2
7
(31.3 kHz)
Setting prohibited
Remarks 1. fW: Watch timer clock frequency (fX/27, fCC/27, or fXT)
2. f
X: Main system clock oscillation frequency (ceramic/crystal oscillation)
3. f
CC: Main system clock oscillation frequency (RC oscillation)
4. f
XT: Subsystem clock oscillation frequency
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11.4 Watch Timer Operation
11.4.1 Operation as watch timer
The main system clock (4.19 MHz) or subsystem clock (32.768 kHz) is used as a watch timer which generates
0.5-second intervals.
The watch timer is used to generate an interrupt request at specified intervals.
By setting bits 0 and 1 (WTM0 and WTM1) of the watch timer mode control register (WTM) to 1, the watch timer
starts counting. By setting them to 0, the 5-bit counter is cleared and the watch timer stops counting.
When the interval timer also operates at the same time, only the watch timer can be started from 0 seconds by
setting WTM1 to 0. However, an error of up to 29 × 1/fW seconds may occur for the first overflow of the watch timer
(INTWT) after a 0-second start because the 9-bit prescaler is not cleared in this case.
11.4.2 Operation as interval timer
The interval timer is used to repeatedly generate an interrupt request at the interval specified by a preset count
value.
The interval time can be selected by bits 4 to 6 (WTM4 to WTM6) of the watch timer mode control register (WTM).
Table 11-4. Interval Time of Interval Timer (Ceramic/Crystal Oscillation)
Interval During fX = 5.0 MHz Operation During fX = 4.19 MHz Operation During fXT = 32.768 kHz Operation
24 × 1/fW 409.6
µ
s 488
µ
s 488
µ
s
25 × 1/fW 819.2
µ
s 977
µ
s 977
µ
s
26 × 1/fW 1.64 ms 1.95 ms 1.95 ms
27 × 1/fW 3.28 ms 3.91 ms 3.91 ms
28 × 1/fW 6.55 ms 7.81 ms 7.81 ms
29 × 1/fW 13.1 ms 15.6 ms 15.6 ms
Remarks 1. f
W: Watch timer clock frequency (fX/27 or fXT)
2. f
X: Main system clock oscillation frequency (ceramic/crystal oscillation)
3. f
XT: Subsystem clock oscillation frequency
Table 11-5. Interval Time of Interval Timer (RC Oscillation)
Interval During fCC = 4.0 MHz Operation During fXT = 32.768 kHz Operation
24 × 1/fW 512
µ
s 488
µ
s
25 × 1/fW 1.02 ms 977
µ
s
26 × 1/fW 2.05 ms 1.95 ms
27 × 1/fW 4.10 ms 3.91 ms
28 × 1/fW 8.19 ms 7.81 ms
29 × 1/fW 16.4 ms 15.6 ms
Remarks 1. f
W: Watch timer clock frequency (fCC/27 or fXT)
2. f
CC: Main system clock oscillation frequency (RC oscillation)
3. f
XT: Subsystem clock oscillation frequency
CHAPTER 11 WATCH TIMER
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Figure 11-3. Watch Timer/Interval Timer Operation Timing
0H
Start Overflow Overflow
5-bit counter
Count clock
f
W
/2
9
Watch timer
interrupt
INTWT
Interval timer
interrupt
INTWTI
Watch timer interrupt time (0.5 s) Watch timer interrupt time (0.5 s)
Interval
timer (T)
T
Caution When operation of the watch timer and 5-bit counter has been enabled by setting the watch
timer mode control register (WTM) (setting WTM0 (bit 0 of WTM) to 1), the time until the first
interrupt request after this setting will not be exactly the same as the time set by watch timer
interrupt time (0.5 s). This is because the 5-bit counter starts counting one cycle after the
output of the 9-bit prescaler. The INTWT signal will be generated at the set time from its second
generation.
Remarks 1. f
W: Watch timer clock frequency
2. The parenthesized values apply to operation at fW = 32.768 kHz.
174 User’s Manual U14800EJ3V0UD
CHAPTER 12 WATCHDOG TIMER
12.1 Watchdog Timer Functions
The watchdog timer has the following functions.
• Watchdog timer
• Interval timer
Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode
register (WDTM).
(1) Watchdog timer
The watchdog timer is used to detect program runaway. When the runaway is detected, a non-maskable
interrupt or the RESET signal can be generated.
Table 12-1. Runaway Detection Time of Watchdog Timer
Runaway Detection Time During fX = 5.0 MHz Operation During fCC = 4.0 MHz Operation
211 × 1/fCLK 2
11/fX (410
µ
s) 211/fCC (512
µ
s)
213 × 1/fCLK 213/fX (1.64 ms) 213/fCC (2.05 ms)
215 × 1/fCLK 215/fX (6.55 ms) 215/fCC (8.19 ms)
217 × 1/fCLK 217/fX (26.2 ms) 217/fCC (32.8 ms)
Remarks 1. f
CLK: fX or fCC
2. f
X: Main system clock oscillation frequency (ceramic/crystal oscillation)
3. f
CC: Main system clock oscillation frequency (RC oscillation)
(2) Interval timer
The interval timer generates an interrupt at any preset intervals.
Table 12-2. Interval Time of Watchdog Timer
Interval Time During fX = 5.0 MHz Operation During fCC = 4.0 MHz Operation
211 × 1/fCLK 2
11/fX (410
µ
s) 211/fCC (512
µ
s)
213 × 1/fCLK 213/fX (1.64 ms) 213/fCC (2.05 ms)
215 × 1/fCLK 215/fX (6.55 ms) 215/fCC (8.19 ms)
217 × 1/fCLK 217/fX (26.2 ms) 217/fCC (32.8 ms)
Remarks 1. f
CLK: fX or fCC
2. f
X: Main system clock oscillation frequency (ceramic/crystal oscillation)
3. f
CC: Main system clock oscillation frequency (RC oscillation)
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12.2 Watchdog Timer Configuration
The watchdog timer includes the following hardware.
Table 12-3. Watchdog Timer Configuration
Item Configuration
Control registers Watchdog timer clock select register (WDCS)
Watchdog timer mode register (WDTM)
Figure 12-1. Watchdog Timer Block Diagram
Internal bus
Internal bus
Prescaler
Selector
Controller
f
CLK
2
6
f
CLK
2
8
f
CLK
2
10
3
7-bit counter
Clear
WDTIF
WDTMK
WDCS2 WDCS1 WDCS0
Watchdog timer clock select
register (WDCS)
Watchdog timer mode register
(WDTM)
WDTM4
RUN
WDTM3
INTWDT
Maskable
interrupt request
RESET
INTWDT
Non-maskable
interrupt request
f
CLK
2
4
Remark f
CLK: fX or fCC
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12.3 Registers Controlling Watchdog Timer
The following two registers are used to control the watchdog timer.
• Watchdog timer clock select register (WDCS)
• Watchdog timer mode register (WDTM)
(1) Watchdog timer clock select register (WDCS)
This register sets the watchdog timer count clock.
WDCS is set with an 8-bit memory manipulation instruction.
RESET input clears WDCS to 00H.
Figure 12-2. Format of Watchdog Timer Clock Select Register
WDCS2
0
0
1
1
00000
WDCS2 WDCS1
0WDCS
R/W
R/W
76543210
WDCS1
0
1
0
1
f
X
/2
4
f
X
/2
6
f
X
/2
8
f
X
/2
10
Setting prohibited
Symbol Address
FF42H 00H
After reset
Other than above
During f
X
= 5.0 MHz operation
Count clock selection
During f
CC
= 4.0 MHz operation
(313 kHz)
(78.1 kHz)
(19.5 kHz)
(4.88 kHz)
f
CC
/2
4
f
CC
/2
6
f
CC
/2
8
f
CC
/2
10
(250 kHz)
(62.5 kHz)
(15.6 kHz)
(3.91 kHz)
Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. f
CC: Main system clock oscillation frequency (RC oscillation)
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(2) Watchdog timer mode register (WDTM)
This register sets an operation mode of the watchdog timer, and enables/disables counting of the watchdog
timer.
WDTM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears WDTM to 00H.
Figure 12-3. Format of Watchdog Timer Mode Register
RUN
0
1
Selection of operation of watchdog timer
Note 1
RUN 0 0
WDTM4 WDTM3
000WDTM
Symbol Address After reset R/W
FFF9H 00H R/W
<7>6543210
Stops counting
Clears counter and starts counting
WDTM4
Selection of operation mode of watchdog timer
Note 2
WDTM3
01
10
11
Operation stopped
Interval timer mode (when overflow occurs, a maskable interrupt occur)
Note 3
Watchdog timer mode 1 (when overflow occurs, a non-maskable interrupt occurs)
Watchdog timer mode 2 (when overflow occurs, reset operation starts)
00
Notes 1. Once RUN has been set (1), it cannot be cleared (0) by software. Therefore, when counting is started,
it cannot be stopped by any means other than RESET input.
2. Once WDTM3 and WDTM4 have been set (1), they cannot be cleared (0) by software.
3. The watchdog timer starts operations as an interval timer when RUN is set to 1.
Cautions 1. When the watchdog timer is cleared by setting RUN to 1, the actual overflow time is up to
0.8% shorter than the time set by the watchdog timer clock select register (WDCS).
2. In watchdog timer mode 1 or 2, set WDTM4 to 1 after confirming that the WDTIF (bit 0 of
interrupt request flag register 0 (IF0)) is set to 0. While WDTIF is 1, a non-maskable interrupt
is generated upon write completion if watchdog timer mode 1 or 2 is selected.
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12.4 Watchdog Timer Operation
12.4.1 Operation as watchdog timer
The watchdog timer detects a program runaway when bit 4 (WDTM4) of the watchdog timer mode register
(WDTM) is set to 1.
The count clock (runaway detection time interval) of the watchdog timer can be selected by bits 0 to 2 (WDCS0 to
WDCS2) of the watchdog timer clock select register (WDCS). By setting bit 7 (RUN) of WDTM to 1, the watchdog
timer is started. Set RUN to 1 within the set runaway detection time interval after the watchdog timer has been started.
By setting RUN to 1, the watchdog timer can be cleared and start counting. If RUN is not set to 1, and the runaway
detection time is exceeded, the system is reset or a non-maskable interrupt is generated by the value of bit 3
(WDTM3) of WDTM.
The watchdog timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1
before entering the STOP mode to clear the watchdog timer, and then execute the STOP instruction.
Cautions 1. The actual runaway detection time may be up to 0.8% shorter than the set time.
2. When the subsystem clock is selected as the CPU clock, the watchdog timer stops counting.
In this case, therefore, the watchdog timer stops operation even though the main system
clock is oscillating.
Table 12-4. Runaway Detection Time of Watchdog Timer
WDCS2 WDCS1 During fX = 5.0 MHz Operation During fCC = 4.0 MHz Operation
0 0
211/fX (410
µ
s) 211/fCC (512
µ
s)
0 1 213/fX (1.64 ms) 213/fCC (2.05 ms)
1 0 215 /fX (6.55 ms) 215/fCC (8.19 ms)
1 1 217/fX (26.2 ms) 217/fCC (32.8 ms)
Other than above Setting prohibited
Remarks 1. f
X: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. f
CC: Main system clock oscillation frequency (RC oscillation)
CHAPTER 12 WATCHDOG TIMER
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12.4.2 Operation as interval timer
When bit 4 (WDTM4) and bit 3 (WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1,
respectively, the watchdog timer also operates as an interval timer that repeatedly generates an interrupt at time
intervals specified by a preset count value.
Select a count clock (or interval time) by setting bits 0 to 2 (WDCS0 to WDCS2) of the watchdog timer clock select
register (WDCS). The watchdog timer starts operation as an interval timer when the RUN bit (bit 7 of WDTM) is set to
1.
In the interval timer mode, the interrupt mask flag (WDTMK) is valid, and a maskable interrupt (INTWDT) can be
generated. The priority of INTWDT is set as the highest of all the maskable interrupts.
The interval timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1
before entering the STOP mode to clear the interval timer, and then execute the STOP instruction.
Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when the watchdog timer mode is selected), the
interval timer mode is not set, unless the RESET signal is input.
2. The interval time immediately after the setting by WDTM may be up to 0.8% shorter than the
set time.
Table 12-5. Interval Time of Watchdog Timer
WDCS2 WDCS1 During fX = 5.0 MHz Operation During fCC = 4.0 MHz Operation
0 0
211/fX (410
µ
s) 211/fCC (512
µ
s)
0 1 213/fX (1.64 ms) 213/fCC (2.05 ms)
1 0 215 /fX (6.55 ms) 215/fCC (8.19 ms)
1 1 217/fX (26.2 ms) 217/fCC (32.8 ms)
Other than above Setting prohibited
Remarks 1. f
X: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. f
CC: Main system clock oscillation frequency (RC oscillation)
180 User’s Manual U14800EJ3V0UD
CHAPTER 13 SERIAL INTERFACE 10
13.1 Serial Interface 10 Functions
Serial interface 10 has the following two modes.
• Operation stop mode
• 3-wire serial I/O mode
(1) Operation stop mode
This mode is used when serial transfer is not carried out. It enables a reduction in power consumption.
(2) 3-wire serial I/O mode (MSB/LSB-first switchable)
In this mode, 8-bit data transfer is carried out-first with three lines, one for the serial clock (SCK10) and two
for serial data (SI10 and SO10).
The 3-wire serial I/O mode supports simultaneous transmit and receive operations, reducing data transfer
processing time.
It is possible to switch the start bit of 8-bit data to be transmitted between the MSB and the LSB, thus
allowing connection to devices with either start bit.
The 3-wire serial I/O mode is effective for connecting display controllers and peripheral I/O such as the 75XL
Series, 78K Series, and 17K Series, which have internal conventional clocked serial interfaces.
CHAPTER 13 SERIAL INTERFACE 10
User’s Manual U14800EJ3V0UD 181
13.2 Serial Interface 10 Configuration
Serial interface 10 includes the following hardware.
Table 13-1. Configuration of Serial Interface 10
Item Configuration
Register Serial shift register 10 (SIO10)
Control register Serial operation mode register 10 (CSIM10)
Port mode register 2 (PM2)
Port 2 (P2)
(1) Serial shift register 10 (SIO10)
This is an 8-bit register used for parallel-to-serial conversion and to perform serial data
transmission/reception in synchronization with serial clocks.
SIO10 is set with an 8-bit memory manipulation instruction.
RESET input makes SIO10 undefined.
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Internal Bus
SI10/P22
Serial operation mode
register 10 (CSIM10)
CSIE10
TPS101
TPS100
DIR10
CSCK10
Serial shift register 10
(SIO10)
SO10/P21
PM21
PM20
SCK10/P20
Serial clock counter Interrupt request
generator
Clock controller
Selector
Selector
INTCSI10
F/F
f
CLK
/2
2
f
CLK
/2
3
f
CLK
/2
4
f
CLK
/2
5
Output latch
(P20)
Output latch
(P21)
2
Remark fCLK: fX or fCC
Figure 13-1. Block Diagram of Serial Interface 10
CHAPTER 13 SERIAL INTERFACE 10
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13.3 Register Controlling Serial Interface 10
The following three registers are used to control serial interface 10.
• Serial operation mode register 10 (CSIM10)
• Port mode register 2 (PM2)
• Port 2 (P2)
(1) Serial operation mode register 10 (CSIM10)
This register is used to control serial interface 10 and set the serial clock and start bit.
CSIM10 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM10 to 00H.
Figure 13-2. Format of Serial Operation Mode Register 10
CSIE10
0
1
Operation control in 3-wire serial I/O mode
CSIE10
0
TPS101 TPS100
0 DIR10
CSCK10
0CSIM10
Symbol Address After reset R/W
FF78H 00H R/W
<7>6543210
Operation stopped
Operation enabled
DIR10
0
1
Start bit specification
MSB
LSB
CSCK10
0
1
SIO10 clock selection
Input clock to SCK10 pin from external
Internal clock selected by TPS100, TPS101
During fX = 5.0 MHz operation During fCC = 4.0 MHz operation
TPS101
0
0
TPS100
0
1f
X/23 (625 kHz)
fX/22 (1.25 MHz)
fX/24 (313 kHz)
fX/25 (156 kHz)
fCC/23 (500 kHz)
fCC/22 (1.0 MHz)
fCC/24 (250 kHz)
fCC/25 (125 kHz)
1
1
0
1
Count clock selection when internal clock is selected
Cautions 1. Bits 0, 3, and 6 must be set to 0.
2. Switch operation mode after stopping the serial transmit/receive operation.
Remarks 1. f
X: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. f
CC: Main system clock oscillation frequency (RC oscillation)
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Table 13-2. Settings of Serial Interface 10 Operating Mode
(1) Operation stop mode
CSIM10 PM22 P22 PM21 P21 PM20 P20 Start Shift P22/SI10 P21/SO10 P20/SCK10
CSIE10 DIR10 CSCK10 Bit Clock Pin Function Pin Function Pin Function
0 × × ×Note 1 ×Note 1 ×Note 1 ×Note 1 ×Note 1 ×Note 1 — — P22 P21 P20
Other than above Setting prohibited
(2) 3-wire serial I/O mode
CSIM10 PM22 P22 PM21 P21 PM20 P20 Start Shift P22/SI10 P21/SO10 P20/SCK10
CSIE10 DIR10 CSCK10 Bit Clock Pin Function Pin Function Pin Function
1 0 0
1Note 2 ×Note 2 0 1 1 × MSB External
clock
SI10Note 2 SO10
(CMOS output)
SCK10 input
1 0 1 Internal
clock
SCK10 output
1 1 0 1
× LSB External
clock
SCK10 input
1 0 1 Internal
clock
SCK10 output
Other than above Setting prohibited
Notes 1. Can be used as port function.
2. If used only for transmission, can be used as P22 (CMOS I/O).
Remark ×: don’t care
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13.4 Serial Interface 10 Operation
Serial interface 10 provides the following two types of modes.
• Operation stop mode
• 3-wire serial I/O mode
13.4.1 Operation stop mode
In the operation stop mode, serial transfer is not executed, therefore enabling a reduction in the power
consumption.
The P20/SCK10, P21/SO10, and P22/SI10 pins can be used as normal I/O ports.
(1) Register setting
Operation stop mode is set by serial operation mode register 10 (CSIM10).
Serial operation mode register 10 (CSIM10)
CSIM10 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM10 to 00H.
CSIE10
0
1
Operation control in 3-wire serial I/O mode
CSIE10
0
TPS101 TPS100
0 DIR10
CSCK10
0CSIM10
Symbol Address After reset R/W
FF78H 00H R/W
<7>6543210
Operation stopped
Operation enabled
Caution Bits 0, 3, and 6 must be set to 0.
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13.4.2 3-wire serial I/O mode
The 3-wire serial I/O mode is useful for connection of peripheral I/O and display controllers, etc., which incorporate
a conventional clocked serial interface, such as the 75X/XL Series, 78K Series, 17K Series.
Communication is performed using three lines: a serial clock line (SCK10), serial output line (SO10), and serial
input line (SI10).
(1) Register setting
3-wire serial I/O mode settings are performed using serial operation mode register 10 (CSIM10), port mode
register 2 (PM2), and port 2 (P2).
(a) Serial operation mode register 10 (CSIM10)
CSIM10 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM10 to 00H.
CSIE10
0
1
Operation control in 3-wire serial I/O mode
CSIE10
0
TPS101
TPS100
0 DIR10
CSCK10
0CSIM10
Symbol Address After reset R/W
FF78H 00H R/W
<7>6543210
Operation stopped
Operation enabled
DIR10
0
1
Start bit specification
MSB
LSB
CSCK10
0
1
SIO10 clock selection
Input clock to SCK10 pin from external
Internal clock selected by TPS100, TPS101
During f
X
= 5.0 MHz operation During f
CC
= 4.0 MHz operation
TPS101
0
0
TPS100
0
1f
X
/2
3
(625 kHz)
f
X
/2
2
(1.25 MHz)
f
X
/2
4
(313 kHz)
f
X
/2
5
(156 kHz)
f
CC
/2
3
(500 kHz)
f
CC
/2
2
(1.0 MHz)
f
CC
/2
4
(250 kHz)
f
CC
/2
5
(125 kHz)
1
1
0
1
Count clock selection when internal clock is selected
Cautions 1. Bits 0, 3, and 6 must be set to 0.
2. Switch operation mode after stopping the serial transmit/receive operation.
Remarks 1. f
X: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. f
CC: Main system clock oscillation frequency (RC oscillation)
CHAPTER 13 SERIAL INTERFACE 10
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(2) Communication operation
In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is
transmitted/received bit by bit in synchronization with the serial clock.
Transmit shift register 10 (SIO10) shift operations are performed in synchronization with the fall of the serial
clock (SCK10). Transmit data is then held in the SO10 latch and output from the SO10 pin. Also, receive
data input to the SI10 pin is latched in the input bits of SIO10 on the rise of SCK10.
At the end of an 8-bit transfer, the operation of SIO10 stops automatically, and the interrupt request signal
(INTCSI10) is generated.
Figure 13-3. 3-Wire Serial I/O Mode Timing
12345678
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
End of transfer
Transfer starts at the falling edge of SCK10
SCK10
SI10
SO10
INTCSI10
Cautions 1. When data is written to SIO10 in the serial operation disabled status (CSIE10 = 0), the
data cannot be transmitted or received.
2. When data is written to SIO10 in the serial operation disabled status (CSIE10 = 0) and
then serial operation is enabled (CSIE10 = 1), the data cannot be transmitted or
received.
3. Once data has been written to SIO10 with the serial clock selected (CSCK10 = 0),
overwriting the data does not update the contents of SIO10.
4. When CSIM10 is operated during data transmission/reception, data cannot be
transmitted or received normally.
5. When SIO10 is operated during data transmission/reception, the data cannot be
transmitted or received normally.
(3) Transfer start
Serial transfer is started by setting transfer data to the transmit shift register 10 (SIO10) when the following
two conditions are satisfied.
• Bit 7 (CSIE10) of serial operation mode register 10 (CSIM10) = 1
• Internal serial clock is stopped or SCK10 is a high level after 8-bit serial transfer.
Termination of 8-bit transfer stops the serial transfer automatically and generates the interrupt request signal
(INTCSI10).
188 User’s Manual U14800EJ3V0UD
CHAPTER 14 SERIAL INTERFACE 20
14.1 Serial Interface 20 Functions
Serial interface 20 has the following three modes.
• Operation stop mode
• Asynchronous serial interface (UART) mode
• 3-wire serial I/O mode
(1) Operation stop mode
This mode is used when serial transfer is not carried out. It can reduce power consumption.
(2) Asynchronous serial interface (UART) mode
In this mode, one byte of data following the start bit is transmitted/received, and full-duplex operation is
possible.
A dedicated UART baud rate generator is incorporated, allowing communication over a wide range of baud
rates. In addition, the baud rate can be defined by scaling the input clock to the ASCK20 pin.
Caution Use the main system clock with ceramic/crystal oscillation in the UART mode. With RC
oscillation, the frequency varies so much that transmission and reception may be affected
when the internal clock is selected for the source clock of the baud rate generator.
(3) 3-wire serial I/O mode (MSB/LSB-first switchable)
In this mode, 8-bit data transfer is carried out with three lines, one for the serial clock (SCK20) and two for
serial data (SI20, SO20).
The 3-wire serial I/O mode supports simultaneous transmit and receive operations, reducing data transfer
processing time.
It is possible to switch the start bit of 8-bit data to be transmitted between the MSB and the LSB, thus
allowing connection to devices with either start bit.
The 3-wire serial I/O mode is effective for connecting display controllers and peripheral I/O such as the 75XL
Series, 78K Series, and 17K Series, which have internal conventional clocked serial interfaces.
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14.2 Serial Interface 20 Configuration
Serial interface 20 includes the following hardware configuration.
Table 14-1. Configuration of Serial Interface 20
Item Configuration
Registers Transmit shift register 20 (TXS20)
Receive shift register 20 (RXS20)
Receive buffer register 20 (RXB20)
Control registers Serial operation mode register 20 (CSIM20)
Asynchronous serial interface mode register 20 (ASIM20)
Asynchronous serial interface status register 20 (ASIS20)
Baud rate generator control register 20 (BRGC20)
Port mode register 2 (PM2)
Port 2 (P2)
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Internal bus
Receive buffer
register 20 (RXB20)
Switching start bit
Asynchronous serial
interface status register 20
(ASIS20)
Serial operation mode
register 20 (CSIM20)
Receive shift register
20 (RXS20)
CSIE20
DIR20
CSCK20
PE20 FE20
OVE20 TXE20 RXE20 PS201 PS200
CL20 SL20
Asynchronous serial interface
mode register 20 (ASIM20)
Transmit shift register
20 (TXS20)
Transmit shift clock
Selector
CSIE20
Data phases
control
Receive shift
clock
SI20/P25
/RxD20
SO20/P24
/TxD20
4
Parity detection
Detection of stop bit
Receive data counter
Parity operation
Addition of stop bit
Transmit data counter
SL20, CL20, PS200, PS201
Receive enabl
Receive clock
Detection clock
Detection
of start bit
PM24
CSIE20
CSCK20
SCK20/P23
/ASCK20
Clock phases
control
Receive detection
Internal clock
output
External clock input
Transmit/receive
clock
control
Baud rate
generator
Note
4
TPS203 TPS202 TPS201 TPS200
CSIE20
CSCK20
f
CLK
/2-f
CLK
/2
8
Baud rate generator
control register 20
(BRGC20)
INTST20
INTSR20/INTCSI20
Internal bus
Output latch
(P24)
Output latch
(P23)
PM23
Note For the baud rate generator configuration, see Figure 14-2.
Remark f
CLK:
f
X
or f
CC
Figure 14-1. Block Diagram of Serial Interface 20
CHAPTER 14 SERIAL INTERFACE 20
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Receive detection clock
Transmit shift clock
Receive shift clock
Receive detection
TXE20
RXE20
CSIE20
1/2
1/2
Transmit clock
counter (3 bits)
Receive clock
counter (3 bits)
4
f
CLK
/2
f
CLK
/2
3
f
CLK
/2
4
f
CLK
/2
5
f
CLK
/2
6
f
CLK
/2
7
f
CLK
/2
8
f
CLK
/2
2
ASCK20/SCK20/P23
TPS203 TPS202 TPS201 TPS200
Baud rate generator
control register 20
(BRGC20)
Remark f
CLK
: f
X
or f
CC
Selector
Selector
Selector
Internal bus
Figure 14-2. Block Diagram of Baud Rate Generator
CHAPTER 14 SERIAL INTERFACE 20
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(1) Transmit shift register 20 (TXS20)
This register is used to specify data to be transmitted. Data written to TXS20 is transmitted as serial data.
If the data length is specified as 7 bits, bits 0 to 6 of the data written to TXS20 are transferred as the transmit
data. The transmit operation is started by writing data to TXS20.
TXS20 is written to with an 8-bit memory manipulation instruction. It cannot be read.
RESET input sets TXS20 to FFH.
Caution During a transmit operation, do not write to TXS20.
TXS20 and receive buffer register 20 (RXB20) are allocated to the same address, so when
reading is performed, RXB20 values are read.
(2) Receive shift register 20 (RXS20)
This register is used to convert serial data input to the RxD20 pin into parallel data. Each time one byte of
data is received, it is transferred to receive buffer register 20 (RXB20).
The RXS20 cannot be manipulated directly by program.
(3) Receive buffer register 20 (RXB20)
This register is used to hold received data. Each time one byte of data is received, a new byte of data is
transferred from receive shift register 20 (RXS20).
If the data length is specified as 7 bits, receive data is transferred to bits 0 to 6 of RXB20, and the MSB of
RXB20 always becomes 0.
RXB20 can be read with an 8-bit memory manipulation instruction. It cannot be written to.
RESET input makes RXB20 undefined.
Caution RXB20 and transmit shift register 20 (TXS20) are allocated to the same address, so when
writing is performed, the values are written to TXS20.
(4) Transmit controller
This circuit controls transmit operations by adding a start bit, parity bit, and stop bit to data written to transmit
shift register 20 (TXS20), according to the data set to asynchronous serial interface mode register 20
(ASIM20).
(5) Receive controller
This circuit controls receive operations according to the data set to asynchronous serial interface mode
register 20 (ASIM20). It performs also parity error check, etc., during receive operations, and when an error is
detected, it sets the value to asynchronous serial interface status register 20 (ASIS20) depending on the
nature of the error.
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14.3 Registers Controlling Serial Interface 20
The following six registers are used to control serial interface 20.
• Serial operation mode register 20 (CSIM20)
• Asynchronous serial interface mode register 20 (ASIM20)
• Asynchronous serial interface status register 20 (ASIS20)
• Baud rate generator control register 20 (BRGC20)
• Port mode register 2 (PM2)
• Port 2 (P2)
(1) Serial operation mode register 20 (CSIM20)
This register is set when using serial interface 20 in the 3-wire serial I/O mode.
CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM20 to 00H.
Figure 14-3. Format of Serial Operation Mode Register 20
CSIE20
0
1
Operation control in 3-wire serial I/O mode
CSIE20
0000DIR20
CSCK20
0CSIM20
Symbol Address After reset R/W
FF72H 00H R/W
<7>6543210
Operation stopped
Operation enabled
DIR20
0
1
Start bit specification
MSB
LSB
CSCK20
0
1
Clock selection in 3-wire serial I/O mode
Input clock to SCK20 pin from external
Dedicated baud rate generator output
Cautions 1. Bits 0, and 3 to 6 must be set to 0.
2. Clear CSIM20 to 00H in the UART mode.
3. When the external input clock is selected in 3-wire serial I/O mode, set input mode by setting
bit 3 of port mode register 2 (PM2) to 1.
4. Switching operation modes must be performed after the serial transmit/receive operation is
stopped.
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(2) Asynchronous serial interface mode register 20 (ASIM20)
This register is set when using the serial interface 20 in the asynchronous serial interface mode.
ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM20 to 00H.
Figure 14-4. Format of Asynchronous Serial Interface Mode Register 20
TXE20
0
1
Transmit operation control
TXE20 RXE20 PS201 PS200
CL20 SL20 0 0ASIM20
Symbol Address After reset R/W
FF70H 00H R/W
<7><6>543210
Transmit operation stopped
Transmit operation enabled
Receive operation stopped
Receive operation enabled
RXE20
0
1
0
1
0
0
0
1
0
1
1
1
No parity
Always add 0 parity at transmission
Parity check is not performed at reception (No parity error is generated)
Odd parity
Even parity
Receive operation control
PS201
Parity bit specification
PS200
CL20
0
1
SL20
Character length specification of transmit data
7 bits
8 bits
1 bit
2 bits
Transmit data stop bit length specification
Cautions 1. Bits 0 and 1 must be set to 0.
2. Clear ASIM20 to 00H in the 3-wire serial I/O mode.
3. Switching operation modes must be performed after the serial transmit/receive operation is
stopped.
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Table 14-2. Settings of Serial Interface 20 Operating Mode
(1) Operation stop mode
P25/SI20/RxD20 P24/SO20/TxD20
P23/SCK20/ASCK20
P25 P24 P23
ASIM20
TXE20
0
RXE20
0
CSIE20
0
CSIM20
DIR20
x
CSCK20
x
PM25
x
Note 1
P25
x
Note 1
PM24
x
Note 1
P24
x
Note 1
PM23
x
Note 1
P23
x
Note 1
—
—
Other than above Setting prohibited
Start
Bit
Shift
Clock Pin Function Pin Function Pin Function
(2) 3-wire serial I/O mode
MSB
LSB
SI20Note 2 SO20
(CMOS output)
SCK20 input
SCK20 output
0 0 1
1
0
1
0
1
0
1
1
Note 2
x
Note 2
0 1 1
0
1
0
x
1
x
1
External
clock
External
clock
Internal
clock
Internal
clock
Other than above Setting prohibited
P25/SI20/RxD20 P24/SO20/TxD20
P23/SCK20/ASCK20
ASIM20
TXE20 RXE20 CSIE20
CSIM20
DIR20
CSCK20
PM25
P25
PM24
P24
PM23
P23 Start
Bit
Shift
Clock Pin Function Pin Function Pin Function
SCK20 input
SCK20 output
(3) Asynchronous serial interface mode
P25/SI20/RxD20 P24/SO20/TxD20
P23/SCK20/ASCK20
LSB P25
RxD20
TxD20
(CMOS output)
P24
TxD20
(CMOS output)
ASCK20 input
P23
ASCK20 input
P23
ASCK20 input
P23
ASIM20
TXE20
1
0
1
RXE20
0
1
1
CSIE20
0
0
0
CSIM20
DIR20
0
0
0
CSCK20
0
0
0
PM25
x
Note 1
1
1
P25
x
Note 1
x
x
PM24
0
x
Note 1
0
P24
1
x
Note 1
1
PM23
1
x
Note 1
1
x
Note 1
1
x
Note 1
P23
x
x
Note 1
x
x
Note 1
x
x
Note 1
Other than above
Start
Bit
Shift
Clock Pin Function Pin Function Pin Function
External
clock
External
clock
External
clock
Internal
clock
Internal
clock
Internal
clock
Setting prohibited
Notes 1. Can be used as port function.
2. If used only for transmission, can be used as P25 (CMOS I/O).
Remark x: don’t care
CHAPTER 14 SERIAL INTERFACE 20
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(3) Asynchronous serial interface status register 20 (ASIS20)
This register indicates types of error when a reception error is generated in the asynchronous interface mode.
ASIS20 is read with a 1-bit or 8-bit memory manipulation instruction.
The contents of ASIS20 become undefined in the 3-wire serial I/O mode.
RESET input clears ASIS20 to 00H.
Figure 14-5. Format of Asynchronous Serial Interface Status Register 20
PE20
0
1
Parity error flag
00000PE20 FE20
OVE20
ASIS20
Symbol Address After reset R/W
FF71H 00H R
76543<2><1><0>
Parity error not generated
Parity error generated (when the transmit parity and receive parity did not match)
Flaming error not generated
Flaming error generated
Note 1
(when stop bit is not detected.)
Overrun error not generated
Overrun error generated
Note 2
(when the next receive operation is completed before the data is read from the receive buffer register 20.)
FE20
0
1
0
1
Flaming error flag
Overrun error flag
OVE20
Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL20) of asynchronous serial interface
mode register 20 (ASIM20), the stop bit detection in the case of reception is performed with 1 bit.
2. Be sure to read receive buffer register 20 (RXB20) when an overrun error occurs. If not, every time the
data is received an overrun error occurs.
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(4) Baud rate generator control register 20 (BRGC20)
This register is used to set the serial clock of serial interface 20.
BRGC20 is set with an 8-bit memory manipulation instruction.
RESET input clears BRGC20 to 00H.
Figure 14-6. Format of Baud Rate Generator Control Register 20
TPS203
0
0
0
0
0
0
0
0
1
TPS203 TPS202 TPS201 TPS200
0000BRGC20
R/W
FF73H 00H R/W
76543210
TPS202
0
0
0
0
1
1
1
1
0
f
X
/2
f
X
/2
2
f
X
/2
3
f
X
/2
4
f
X
/2
5
f
X
/2
6
f
X
/2
7
f
X
/2
8
(2.5 MHz)
(1.25 MHz)
(625 kHz)
(313 kHz)
(156 kHz)
(78.1 kHz)
(39.1 kHz)
(19.5 kHz)
f
CC
/2
f
CC
/2
2
f
CC
/2
3
f
f
CC
/2
4
CC
/2
5
f
CC
/2
6
f
CC
/2
7
f
CC
/2
8
(2.0 MHz)
(1.0 MHz)
(500 kHz)
(250 kHz)
(125 kHz)
(62.5 kHz)
(31.3 kHz)
(15.6 kHz)
TPS201
0
0
1
1
0
0
1
1
0
TPS200
0
1
0
1
0
1
0
1
0
n
1
2
3
4
5
6
7
8
–
Setting prohibited
Symbol Address After reset
Selection of baud rate generator source clock
During f
X
= 5.0 MHz operation During f
CC
= 4.0 MHz operation
Input clock from external to ASCK20 pin
Note
Other than above
Note Only used in the UART mode.
Cautions 1. When writing to BRGC20 is performed during a communication operation, the output of the
baud rate generator is disrupted and communications cannot be performed normally. Be
sure not to write to BRGC20 during a communication operation.
2. Use the main system clock with ceramic/crystal oscillation in the UART mode. With RC
oscillation, the frequency varies so much that transmission and reception may be affected
when the internal clock is selected for the source clock of the baud rate generator.
3. Be sure not to select n = 1 during operation at fX > 2.5 MHz in UART mode because the
resulting baud rate exceeds the rated range.
4. When the external input clock is selected in 3-wire serial I/O mode, set input mode by setting
bit 3 of port mode register 2 (PM2) to 1.
Remarks 1. f
X: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. f
CC: Main system clock oscillation frequency (RC oscillation)
3. n: Value determined in the settings of TPS200 to TPS203 (1 ≤ n ≤ 8)
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The baud rate transmit/receive clock to be generated is either a signal divided from the system clock, or a
signal divided from the clock input from the ASCK20 pin.
(a) Generation of UART baud rate transmit/receive clock by means of system clock
The transmit/receive clock is generated by dividing the system clock. The baud rate generated from the
system clock is estimated by using the following expression.
[Baud rate] = [bps]
fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
n: Value in Figure 14-6 that is determined by the settings of TPS200 to TPS203 (2 ≤ n ≤ 8)
Table 14-3. Example of Relationship Between System Clock and Baud Rate
Error (%) Baud Rate
(bps)
n BRGC00 Set Value
fX = 5.0 MHz fX = 4.9152 MHz
1200 8 70H
2400 7 60H
4800 6 50H
9600 5 40H
19200 4 30H
38400 3 20H
76800 2 10H
1.73 0
Caution Be sure not to select n = 1 during operation at fX > 2.5 MHz because the resulting baud rate
exceeds the rated range.
fX
2n + 1 × 8
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(b) Generation of UART baud rate transmit/receive clock by means of external clock from ASCK20
pin
The transmit/receive clock is generated by dividing the clock input from the ASCK20 pin. The baud rate
generated from the clock input from the ASCK20 pin is estimated by using the following expression.
[Baud rate] = [bps]
fASCK: Frequency of clock input to the ASCK20 pin
Table 14-4. Relationship Between ASCK20 Pin Input Frequency
and Baud Rate (When BRGC20 Is Set to 80H)
Baud Rate (bps) ASCK20 Pin Input Frequency (kHz)
75 1.2
150 2.4
300 4.8
600 9.6
1200 19.2
2400 38.4
4800 76.8
9600 153.6
19200 307.2
31250 500.0
38400 614.4
(c) Generation of serial clock from system clock in 3-wire serial I/O
The serial clock is generated by dividing the system clock. The frequency of the serial clock can be
obtained by the following expression. If the serial clock is externally input to the SCK20 pin, it is
unnecessary to set BRGC20.
[Serial clock frequency] = [Hz]
fCLK: fX or fCC
fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
fCC: Main system clock oscillation frequency (RC oscillation)
n: Values in Figure 14-6 determined by the settings of TPS200 to TPS203 (1 ≤ n ≤ 8)
fASCK
16
fCLK
2n+1
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14.4 Serial Interface 20 Operation
Serial interface 20 has the following three modes.
• Operation stop mode
• Asynchronous serial interface (UART) mode
• 3-wire serial I/O mode
14.4.1 Operation stop mode
In the operation stop mode, serial transfer is not executed, therefore enabling a reduction in the power
consumption.
The P23/SCK20/ASCK20, P24/SO20/TxD20, and P25/SI20/RxD20 pins can be used as normal I/O ports.
(1) Register setting
Operation stop mode is set by serial operation mode register 20 (CSIM20) and asynchronous serial interface
mode register 20 (ASIM20).
(a) Serial operation mode register 20 (CSIM20)
CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM20 to 00H.
CSIE20
0
1
Operation control in 3-wire serial I/O mode
CSIE20
0000DIR20
CSCK20
0CSIM20
Symbol Address After reset R/W
FF72H 00H R/W
<7>6543210
Operation stopped
Operation enabled
Caution Bits 0 and 3 to 6 must be set to 0.
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(b) Asynchronous serial interface mode register 20 (ASIM20)
ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM20 to 00H.
TXE20
0
1
Transmit operation control
TXE20 RXE20
PS201 PS200 CL20 SL20 0 0ASIM20
Symbol Address After reset R/W
FF70H 00H R/W
<7><6>543210
Transmit operation stopped
Transmit operation enabled
Receive operation stopped
Receive operation enabled
RXE20
0
1
Receive operation control
Caution Bits 0 and 1 must be set to 0.
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14.4.2 Asynchronous serial interface (UART) mode
In this mode, the one-byte data following the start bit is transmitted/received and thus full-duplex communications
are possible.
This device incorporates a UART-dedicated baud rate generator that enables communications at a desired
transfer rate from many options. In addition, the baud rate can be also defined by dividing the clock input to the
ASCK20 pin.
The UART-dedicated baud rate generator also can output the 31.25 kbps baud rate which complies with the MIDI
standard.
Caution Use the main system clock with ceramic/crystal oscillation in the UART mode. With RC
oscillation, the frequency varies so much that transmission and reception may be affected when
the internal clock is selected for the source clock of the baud rate generator.
(1) Register setting
UART mode is set by serial operation mode register 20 (CSIM20), asynchronous serial interface mode
register 20 (ASIM20), asynchronous serial interface status register 20 (ASIS20), baud rate generator control
register 20 (BRGC20), port mode register 2 (PM2), and port 2 (P2).
(a) Serial operation mode register 20 (CSIM20)
CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM20 to 00H.
Clear CSIM20 to 00H in the UART mode.
CSIE20
0
1
Operation control in 3-wire serial I/O mode
CSIE20
0000DIR20
CSCK20
0CSIM20
Symbol Address After reset R/W
FF72H 00H R/W
<7>6543210
Operation stopped
Operation enabled
DIR20
0
1
Start bit specification
MSB
LSB
CSCK20
0
1
Clock selection in 3-wire serial I/O mode
Input clock to SCK20 pin from external
Dedicated baud rate generator output
Caution 1. Bits 0 and 3 to 6 must be set to 0.
2. Switching operation modes must be performed after the serial transmit/receive
operation is stopped.
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(b) Asynchronous serial interface mode register 20 (ASIM20)
ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM20 to 00H.
TXE20
0
1
Transmit operation control
TXE20 RXE20
PS201 PS200
CL20 SL20 0 0ASIM20
Symbol Address After reset R/W
FF70H 00H R/W
<7><6>543210
Transmit operation stopped
Transmit operation enabled
Receive operation stopped
Receive operation enabled
RXE20
0
1
0
1
0
0
0
1
0
1
1
1
No parity
Always add 0 parity at transmission
Parity check is not performed at reception (No parity error is generated)
Odd parity
Even parity
Receive operation control
PS201
Parity bit specification
PS200
CL20
0
1
SL20
Character length specification
7 bits
8 bits
1 bit
2 bits
Transmit data stop bit length specification
Cautions 1. Bits 0 and 1 must be set to 0.
2. Switching operation modes must be performed after the serial transmit/receive
operation is stopped.
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(c) Asynchronous serial interface status register 20 (ASIS20)
ASIS20 is read with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIS20 to 00H.
PE20
0
1
Parity error flag
00000PE20 FE20
OVE20
ASIS20
Symbol Address After reset R/W
FF71H 00H R
76543210
Parity error not generated
Parity error generated (when the transmit parity and receive parity did not match)
Flaming error not generated
Flaming error generated (when stop bit is not detected.)
Note 1
Overrun error not generated
Overrun error generated
(when the next receive operation is completed before the data is read from the receive buffer register.)
Note 2
FE20
0
1
0
1
Flaming error flag
Overrun error flag
OVE20
Notes 1. Even when the stop bit length is set to 2 bits by setting bit 2 (SL20) of asynchronous serial
interface mode register 20 (ASIM20), the stop bit detection in the case of reception is
performed with 1 bit.
2. Be sure to read receive buffer register 20 (RXB20) when an overrun error occurs. If not,
every time the data is received an overrun error occurs.
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(d) Baud rate generator control register 20 (BRGC20)
BRGC20 is set with an 8-bit memory manipulation instruction.
RESET input clears BRGC20 to 00H.
TPS203
0
0
0
0
0
0
0
0
1
TPS203 TPS202 TPS201 TPS200
0000BRGC20
R/W
FF73H 00H R/W
76543210
TPS202
0
0
0
0
1
1
1
1
0
f
X
/2
f
X
/2
2
f
X
/2
3
f
X
/2
4
f
X
/2
5
f
X
/2
6
f
X
/2
7
f
X
/2
8
(2.5 MHz)
(1.25 MHz)
(625 kHz)
(313 kHz)
(156 kHz)
(78.1 kHz)
(39.1 kHz)
(19.5 kHz)
TPS201
0
0
1
1
0
0
1
1
0
TPS200
0
1
0
1
0
1
0
1
0
n
1
2
3
4
5
6
7
8
Setting prohibited
Symbol Address After reset
Selection of baud rate generator source clock
Input clock to ASCK20 pin from external
Note
Other than above
Note Only used in the UART mode.
Cautions 1. When writing to BRGC20 is performed during a communication operation, the
output of the baud rate generator is disrupted and communications cannot be
performed normally. Be sure not to write to BRGC20 during a communication
operation.
2. Use the main system clock with ceramic/crystal oscillation in the UART mode.
With RC oscillation, the frequency varies so much that transmission and reception
may be affected when the internal clock is selected for the source clock of the
baud rate generator.
3. Be sure not to select n = 1 during operation at fX > 2.5 MHz because the resulting
baud rate exceeds the rated range.
4. When external input clock is selected, set bit 3 of port mode register 2 (PM2) to
input mode.
Remarks 1. f
X: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. The parenthesized values apply to operation at fX = 5.0 MHz.
3. n: Value determined in the settings of TPS200 to TPS203 (1 ≤ n ≤ 8)
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The baud rate transmit/receive clock to be generated is either a signal divided from the main system
clock, or a signal divided from the clock input from the ASCK20 pin.
(i) Generation of UART baud rate transmit/receive clock by means of system clock
The transmit/receive clock is generated by dividing the system clock. The baud rate generated
from the system clock is estimated by using the following expression.
[Baud rate] = [bps]
fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
n: Value in the above table that is determined by the settings of TPS200 to TPS203 (2 ≤ n ≤
8)
Table 14-5. Example of Relationship Between Main System Clock and Baud Rate
Error (%) Baud Rate
(bps)
n BRGC20 Set Value
fX = 5.0 MHz fX = 4.9152 MHz
1200 8 70H
2400 7 60H
4800 6 50H
9600 5 40H
19200 4 30H
38400 3 20H
76800 2 10H
1.73 0
Caution Be sure not to select n = 1 during operation at fX > 2.5 MHz because the resulting baud rate
exceeds the rated range.
fX
2n + 1 ×8
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(ii) Generation of UART baud rate transmit/receive clock by means of external clock from
ASCK20 pin
The transmit/receive clock is generated by dividing the clock input from the ASCK20 pin. The
baud rate generated from the clock input from the ASCK20 pin is estimated by using the following
expression.
[Baud rate] = [bps]
fASCK: Frequency of clock input to the ASCK20 pin
Table 14-6. Relationship Between ASCK20 Pin Input Frequency
and Baud Rate (When BRGC20 Is Set to 80H)
Baud Rate (bps) ASCK20 Pin Input Frequency (kHz)
75 1.2
150 2.4
300 4.8
600 9.6
1200 19.2
2400 38.4
4800 76.8
9600 153.6
19200 307.2
31250 500.0
38400 614.4
fASCK
16
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(2) Communication operation
(a) Data format
The transmit/receive data format is as shown in Figure 14-7. One data frame consists of a start bit,
character bits, parity bit and stop bit(s).
The specification of character bit length, parity selection, and specification of stop bit length for each
data frame is carried out by asynchronous serial interface mode register 20 (ASIM20).
Figure 14-7. Format of Asynchronous Serial Interface Transmit/Receive Data
D0 D1 D2 D3 D4 D5 D6 D7
Parity
bit Stop bit
Start
bit
One data frame
• Start bit ...................... 1 bit
• Character bits............. 7 bits/8 bits
• Parity bits ................... Even parity/odd parity/0 parity/no parity
• Stop bit(s)................... 1 bit/2 bits
When 7 bits are selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in
transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit (bit 7) is
always 0.
The serial transfer rate is selected by means of baud rate generator control register 20 (BRGC20).
If a serial data receive error is generated, the receive error contents can be determined by reading the
status of asynchronous serial interface status register 20 (ASIS20).
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(b) Parity types and operation
The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity
bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit
(odd number) error can be detected. With 0 parity and no parity, an error cannot be detected.
(i) Even parity
• At transmission
The transmission operation is controlled so that the number of bits with a value of 1 in the
transmit data including parity bit may be even. The parity bit value should be as follows.
The number of bits with a value of 1 is an odd number in transmit data: 1
The number of bits with a value of 1 is an even number in transmit data: 0
• At reception
The number of bits with a value of 1 in the receive data including parity bit is counted, and if the
number is odd, a parity error is generated.
(ii) Odd parity
• At transmission
Conversely to the even parity, the transmission operation is controlled so that the number of bits
with a value of 1 in the transmit data including parity bit may be odd. The parity bit value should
be as follows.
The number of bits with a value of 1 is an odd number in transmit data: 0
The number of bits with a value of 1 is an even number in transmit data: 1
• At reception
The number of bits with a value of 1 in the receive data including parity bit is counted, and if the
number is even, a parity error is generated.
(iii) 0 Parity
When transmitting, the parity bit is set to 0 irrespective of the transmit data.
At reception, a parity bit check is not performed. Therefore, a parity error is not generated,
irrespective of whether the parity bit is set to 0 or 1.
(iv) No parity
A parity bit is not added to the transmit data. At reception, data is received assuming that there is
no parity bit. Since there is no parity bit, a parity error is not generated.
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(c) Transmission
A transmit operation is started by writing transmit data to transmit shift register 20 (TXS20). The start
bit, parity bit, and stop bit(s) are added automatically.
When the transmit operation starts, the data in TXS20 is shifted out, and when TXS20 is empty, a
transmission completion interrupt (INTST20) is generated.
Figure 14-8. Asynchronous Serial Interface Transmission Completion Interrupt Timing
(a) Stop bit length: 1
Stop
ParityD7D6D2D1D0
Start
TxD20 (Output)
INTST20
(b) Stop bit length: 2
Stop
ParityD7D6D2D1D0
Start
TxD20 (Output)
INTST20
Caution Do not overwrite asynchronous serial interface mode register 20 (ASIM20) during a
transmit operation. If the ASIM20 register is overwritten during transmission,
subsequent transmission may not operate (the normal state is restored by RESET
input).
It is possible to determine whether transmission is in progress by software by using a
transmission completion interrupt (INTST20) or the interrupt request flag (STIF20) set
by the INTST20.
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(d) Reception
When bit 6 (RXE20) of asynchronous serial interface mode register 20 (ASIM20) is set (1), a receive
operation is enabled and sampling of the RxD20 pin input is performed.
RxD20 pin input sampling is performed using the serial clock specified by ASIM20.
When the RxD20 pin input becomes low, the 3-bit counter starts counting, and at the time when half the
time determined by specified baud rate has passed, the data sampling start timing signal is output. If
the RxD20 pin input sampled again as a result of this start timing signal is low, it is identified as a start
bit, the 3-bit counter is initialized and starts counting, and data sampling is performed. When character
data, a parity bit, and one stop bit are detected after the start bit, reception of one frame of data ends.
When one frame of data has been received, the receive data in the shift register is transferred to
receive buffer register 20 (RXB20), and a reception completion interrupt (INTSR20) is generated.
If an error is generated, the receive data in which the error was generated is still transferred to RXB20,
and INTSR20 is generated.
If the RXE20 bit is reset (0) during the receive operation, the receive operation is stopped immediately.
In this case, the contents of RXB20 and asynchronous serial interface status register 20 (ASIS20) are
not changed, and INTSR20 is not generated.
Figure 14-9. Asynchronous Serial Interface Reception Completion Interrupt Timing
Stop
ParityD7D6D2D1D0
Start
RxD20 (Input)
INTSR20
Caution Be sure to read receive buffer register 20 (RXB20) even if a receive error occurs. If
RXB20 is not read, an overrun error will be occurred when the next data is received,
and the receive error state will continue indefinitely.
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(e) Receive errors
The following three errors may occur during a receive operation: a parity error, framing error, or overrun
error. An error flag is set in asynchronous serial interface status register 20 (ASIS20) as the result of
data reception. Receive error causes are shown in Table 14-7.
It is possible to determine what kind of error was generated during reception by reading the contents of
ASIS20 in the reception error interrupt servicing (see Figures 14-9 and 14-10).
The contents of ASIS20 are reset (0) by reading receive buffer register 20 (RXB20) or receiving the next
data (if there is an error in the next data, the corresponding error flag is set).
Table 14-7. Receive Error Causes
Receive Errors Cause Value of ASIS20
Parity error Parity specified at transmission and reception data parity do not match. 04H
Framing error Stop bit is not detected. 02H
Overrun error Reception of next data is completed before data is read from receive buffer
register.
01H
Figure 14-10. Receive Error Timing
(a) Parity error generated
Stop
ParityD7D6D2D1D0
Start
RxD20 (Input)
INTSR20
(b) Flaming error or overrun error generated
Stop
ParityD7D6D2D1D0
Start
RxD20 (Input)
INTSR20
Cautions 1. The contents of the ASIS20 register are reset (0) by reading receive buffer register
20 (RXB20) or receiving the next data. To ascertain the error contents, read ASIS20
before reading RXB20.
2. Be sure to read receive buffer register 20 (RXB20) even if a receive error occurs. If
RXB20 is not read, an overrun error will be occurred when the next data is received,
and the receive error state will continue indefinitely.
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(f) Reading receive data
When the reception completion interrupt (INTSR20) is generated, receive data can be read by reading
the value of receive buffer register 20 (RXB20).
To read the receive data stored in receive buffer register 20 (RXB20), read while reception is enabled
(RXE20 = 1).
Remark However, if it is necessary to read receive data after reception has stopped (RXE20 = 0),
read using either of the following methods.
(a) Read after setting RXE20 = 0 after waiting for one cycle or more of the source clock
selected by BRGC20.
(b) Read after bit 2 (DIR20) of serial operation mode register 20 (CSIM20) is set (1).
Program example of (a) (BRGC20 = 00H (source clock = fx/2))
INTRXE: ;<Reception completion interrupt routine>
NOP ;2 clocks
CLR1 RXE20 ;Reception stopped
MOV A, RXB20 ;Read receive data
Program example of (b)
INTRXE: ;<Reception completion interrupt routine>
SET1 CSIM20.2 ;DIR20 flag is set to LSB first
CLR1 RXE20 ;Reception stopped
MOV A, RXB20 ;Read receive data
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(3) UART mode cautions
(a) When bit 7 (TXE20) of asynchronous serial interface mode register 20 (ASIM20) is cleared during
transmission, be sure to set transmit shift register 20 (TXS20) to FFH, then set TXE20 to 1 before
executing the next transmission.
(b) When bit 6 (RXE20) of asynchronous serial interface mode register 20 (ASIM20) is cleared during
reception, receive buffer register 20 (RXB20) and the receive completion interrupt (INTSR20) are as
follows.
ParityRxD20 pin
RXB20
INTSR20
<3><1>
<2>
When RXE20 is set to 0 at a time indicated by <1>, RXB20 holds the previous data and does not generate
INTSR20.
When RXE20 is set to 0 at a time indicated by <2>, RXB20 updates the data and does not generate
INTSR20.
When RXE20 is set to 0 at a time indicated by <3>, RXB20 updates the data and generates INTSR20.
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14.4.3 3-wire serial I/O mode
The 3-wire serial I/O mode is useful for connection of peripheral I/O and display controllers, etc., which incorporate
a conventional clocked serial interface, such as the 75XL Series, 78K Series, 17K Series.
Communication is performed using three lines: a serial clock line (SCK20), serial output line (SO20), and serial
input line (SI20).
(1) Register setting
3-wire serial I/O mode settings are performed using serial operation mode register 20 (CSIM20),
asynchronous serial interface mode register 20 (ASIM20), baud rate generator control register 20 (BRGC20),
port mode register 2 (PM2), and port 2 (P2).
(a) Serial operation mode register 20 (CSIM20)
CSIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM20 to 00H.
CSIE20
0
1
Operation control in 3-wire serial I/O mode
CSIE20
0000DIR20
CSCK20
0CSIM20
Symbol Address After reset R/W
FF72H 00H R/W
<7>6543210
Operation stopped
Operation enabled
DIR20
0
1
Start bit specification
MSB
LSB
CSCK20
0
1
Clock selection in 3-wire serial I/O mode
Input clock to SCK20 pin from external
Dedicated baud rate generator output
Caution 1. Bits 0 and 3 to 6 must be set to 0.
2. When the external input clock is selected in 3-wire serial I/O mode, set input mode
by setting bit 3 of port mode register 2 (PM2) to 1.
3. Switching operation modes must be performed after the serial transmit/receive
operation is stopped.
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(b) Asynchronous serial interface mode register 20 (ASIM20)
ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM20 to 00H.
When the 3-wire serial I/O mode is selected, ASIM20 must be cleared to 00H.
TXE20
0
1
Transmit operation control
TXE20 RXE20
PS201 PS200
CL20 SL20 0 0ASIM20
Symbol Address After reset R/W
FF70H 00H R/W
<7><6>543210
Transmit operation stopped
Transmit operation enabled
Receive operation stopped
Receive operation enabled
RXE20
0
1
0
1
0
0
0
1
0
1
1
1
No parity
Always add 0 parity at transmission
Parity check is not performed at reception (No parity error is generated.)
Odd parity
Even parity
Receive operation control
PS201
Parity bit specification
PS200
CL20
0
1
SL20
Character length specification
7 bits
8 bits
1 bit
2 bits
Transmit data stop bit length specification
Cautions 1. Bits 0 and 1 must be set to 0.
2. Switching operation modes must be performed after the serial transmit/receive
operation is stopped.
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(c) Baud rate generator control register 20 (BRGC20)
BRGC20 is set with an 8-bit memory manipulation instruction.
RESET input clears BRGC20 to 00H.
TPS203
0
0
0
0
0
0
0
0
1
TPS203 TPS202 TPS201 TPS200
0000BRGC20
R/W
FF73H 00H R/W
76543210
TPS202
0
0
0
0
1
1
1
1
0
f
X
/2
f
X
/2
2
f
X
/2
3
f
X
/2
4
f
X
/2
5
f
X
/2
6
f
X
/2
7
f
X
/2
8
(2.5 MHz)
(1.25 MHz)
(625 kHz)
(313 kHz)
(156 kHz)
(78.1 kHz)
(39.1 kHz)
(19.5 kHz)
f
CC
/2
f
CC
/2
2
f
CC
/2
3
f
f
CC
/2
4
CC
/2
5
f
CC
/2
6
f
CC
/2
7
f
CC
/2
8
(2.0 MHz)
(1.0 MHz)
(500 kHz)
(250 kHz)
(125 kHz)
(62.5 kHz)
(31.3 kHz)
(15.6 kHz)
TPS201
0
0
1
1
0
0
1
1
0
TPS200
0
1
0
1
0
1
0
1
0
n
1
2
3
4
5
6
7
8
–
Setting prohibited
Symbol Address After reset
Selection of baud rate generator source clock
During f
X
= 5.0 MHz operation During f
CC
= 4.0 MHz operation
Input clock to ASCK20 pin from external
Note
Other than above
Note In 3-wire serial I/O mode, it is setting prohibited.
Caution When writing to BRGC20 is performed during a communication operation, the output
of the baud rate generator is disrupted and communications cannot be performed
normally. Be sure not to write to BRGC20 during a communication operation.
Remarks 1. f
X: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. f
CC: Main system clock oscillation frequency (RC oscillation)
3. n: Value in the above table that is determined in the settings of TPS200 to TPS203
(1 ≤ n ≤ 8)
If the internal clock is used as the serial clock for the 3-wire serial I/O mode, set the TPS200 to TPS203
bits to set the frequency of the serial clock. To obtain the frequency to be set, use the following formula.
When the serial clock is input from external, setting BRGC20 is unnecessary.
Serial clock frequency = [Hz]
fCLK: fX or fCC
fX: Main system clock oscillation frequency (ceramic/crystal oscillation)
fCC: Main system clock oscillation frequency (RC oscillation)
n: Value in the above table that is determined in the settings of TPS200 to TPS203 (1 ≤ n ≤ 8)
fCLK
2n + 1
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(2) Communication operation
In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is
transmitted/received bit by bit in synchronization with the serial clock.
Transmit shift register 20 (TXS20/SIO20) and receive shift register 20 (RXS20) shift operations are
performed in synchronization with the fall of the serial clock (SCK20). Transmit data is then held in the SO20
latch and output from the SO20 pin. Also, receive data input to the SI20 pin is latched in receive buffer
register 20 (RXB20/SIO20) on the rise of SCK20.
At the end of an 8-bit transfer, the operation of TXS20/SIO20 or RXS20 stops automatically, and the interrupt
request signal (INTCSI20) is generated.
Figure 14-11. 3-Wire Serial I/O Mode Timing
(i) Master operation
12345678
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SCK20
SO20 Note
SI20
Writing to SIO20
INTCSI20
(ii) Slave operation
12345678
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
SCK20
SI20
NoteSO20
Writing to SIO20
INTCSI20
Note The value of the last bit previously output is output.
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(3) Transfer start
Serial transfer is started by setting transfer data to transmit shift register 20 (TXS20/SIO20) when the
following two conditions are satisfied.
• Bit 7 (CSIE20) of serial operation mode register 20 (CSIM20) = 1
• Internal serial clock is stopped or SCK20 is a high level after 8-bit serial transfer.
Caution If CSIE20 is set to 1 after data write to TXS20/SIO20, transfer does not start.
Termination of 8-bit transfer stops the serial transfer automatically and generates the interrupt request signal
(INTCSI20).
220 User’s Manual U14800EJ3V0UD
CHAPTER 15 LCD CONTROLLER/DRIVER
15.1 LCD Controller/Driver Functions
The functions of the LCD controller/driver of the
µ
PD789306 and
µ
PD789316 Subseries are as follows.
(1) Automatic output of segment and common signals based on automatic display data memory read
(2) Two different display modes:
• 1/3 duty (1/3 bias)
• 1/4 duty (1/3 bias)
(3) Four different frame frequencies, selectable in each display mode
(4) Up to 24 segment signal outputs (S0 to S23) and four common signal outputs (COM0 to COM3)
(5) Operation with a subsystem clock
(6) On-chip voltage boosting circuit
Table 15-1 lists the maximum number of pixels that can be displayed in each display mode.
Table 15-1. Maximum Number of Pixels
Bias Mode Number of Time Slices Common Signals
Used
Maximum Number of Pixels
3 COM0 to COM2 72 (24 segments × 3 commons)Note 1
1/3
4 COM0 to COM3 96 (24 segments × 4 commons)Note 2
Notes 1. 8-digit LCD panel, each digit having a 3-segment
configuration.
2. 12-digit LCD panel, each digit having a 2-segment configuration.
15.2 LCD Controller/Driver Configuration
The LCD controller/driver includes the following hardware.
Table 15-2. Configuration of LCD Controller/Driver
Item Configuration
Display outputs Segment signals: 24
Common signals: 4
Control registers LCD display mode register 0 (LCDM0)
LCD clock control register 0 (LCDC0)
LCD voltage amplification control register 0 (LCDVA0)
CHAPTER 15 LCD CONTROLLER/DRIVER
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The correspondence with the LCD display RAM is shown in Figure 15-1 below.
Figure 15-1. Correspondence with LCD Display RAM
Address Bit Segment
7 6 5 4 3 2 1 0
FA17H 0 0 0 0
→ S23
FA16H 0 0 0 0
→ S22
FA15H 0 0 0 0
→ S21
FA14H 0 0 0 0
→ S20
FA13H 0 0 0 0
→ S19
FA12H 0 0 0 0
→ S18
FA11H 0 0 0 0
→ S17
FA10H 0 0 0 0
→ S16
FA0FH 0 0 0 0
→ S15
FA0EH 0 0 0 0
→ S14
FA0DH 0 0 0 0
→ S13
FA0CH 0 0 0 0
→ S12
FA0BH 0 0 0 0
→ S11
FA0AH 0 0 0 0
→ S10
FA09H 0 0 0 0
→ S9
FA08H 0 0 0 0
→ S8
FA07H 0 0 0 0
→ S7
FA06H 0 0 0 0
→ S6
FA05H 0 0 0 0
→ S5
FA04H 0 0 0 0
→ S4
FA03H 0 0 0 0
→ S3
FA02H 0 0 0 0
→ S2
FA01H 0 0 0 0
→ S1
FA00H 0 0 0 0
→ S0
Common
↑
COM3
↑
COM2
↑
COM1
↑
COM0
Remark Bit 4 to 7 are fixed to 0.
CHAPTER 15 LCD CONTROLLER/DRIVER
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Internal bus
LCDC03 LCDC02
LCDC01
LCDC00
2
2
Selector
Prescaler
LCD
clock
selector
Selector
fLCD
26
fLCD
27
fLCD
28
fLCD
29
LCD clock control
register 0 (LCDC0)
LCDON0
VAON0
LCD display mode
register 0 (LCDM0)
VLC0
Segment
driver
Common driver
COM0 COM1 COM2 COM3
3210
32106574
FA00H
Display data
memory
LCDON0
Selector
Segment
driver
3210
32106574
FA17H
LCDON0
S23
fCLK/25
fCLK/26
fCLK/27
fXT
S0
............... ...............
fLCD
Selector
Segment
driver
3210
32106574
FA0FH
LCDON0
S15
LCDCL
LIPS0 GAIN
LCD voltage amplification
control register 0 (LCDVA0)
VLC2
CAPH CAPL VLC1
..........
...........
............
...........
...........
...........
Booster circuit
Common voltage
controller
Clock
generator for
boosting
Timing
controller
VAON0
Segment voltage
controller
Selector
Segment
driver
3210
32106574
FA10H
LCDON0
S16
.............
...........
...........
............
............
...........
............
..........
LCDM00
Remark fCLK: fX or fCC
...........
...........
Figure 15-2. Block Diagram of LCD Controller/Driver
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15.3 Registers Controlling LCD Controller/Driver
The following three registers control the LCD controller/driver.
• LCD display mode register 0 (LCDM0)
• LCD clock control register 0 (LCDC0)
• LCD voltage amplification control register 0 (LCDVA0)
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(1) LCD display mode register 0 (LCDM0)
LCDM0 is used to control the LCD display enable/disable status, booster circuit operation enable/disable
status, segment pin/common pin output, and the display mode.
LCDM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears LCDM0 to 00H.
Figure 15-3. Format of LCD Display Mode Register 0
LCDON0
VAON0
0 LIPS0 0 0 0
LCDM00
LCDM0
Symbol Address After reset R/W
FFB0H 00H R/W
<7><6>5<4>3210
LCD controller/driver display mode selection
LCDM00
0
1
4
3
LCD display enable/disable
LCDON0
0
1
Display off (all segment signals are deselected.)
Display on
Operation control of segment pin/common pin outputNote
LIPS0
0
1
Booster circuit operation enable/disableNote
VAON0
0
1
Booster circuit stopped
Booster circuit enabled
Output ground level to segment/common pin
Output deselect level to segment pin and LCD waveform to common pin
Number of time slices Bias mode
1/3
1/3
Note When the LCD display panel is not used, the VAON0 and LIPS0 must be set to 0 to reduce power
consumption.
Cautions 1. Bits 1 to 3 and 5 must be set to 0.
2. When operating VAON0, follow the procedure described below.
A. To stop voltage amplification after switching display status from on to off:
1) Set to display off status by setting LCDON0 = 0.
2) Disable outputs of all the segment buffers and common buffers by setting LIPS0 = 0.
3) Stop voltage amplification by setting VAON0= 0.
B. To stop voltage amplification during display on status:
Setting prohibited. Be sure to stop voltage amplification after setting display off.
C. To set display on from voltage amplification stop status:
1) Start voltage amplification by setting VAON0 = 1, then wait for voltage boost wait time
(tVAWAIT) (See CHAPTER 22 ELECTRICAL SPECIFICATIONS).
2) Set all the segment buffers and common buffers to non-display output status by
setting LIPS0 = 1.
3) Set display on by setting LCDON0 = 1.
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(2) LCD clock control register 0 (LCDC0)
LCDC0 specifies the LCD source clock and LCD clock. The frame frequency is determined according to the
LCD clock and the number of time slices.
LCDC0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears LCDC0 to 00H.
Figure 15-4. Format of LCD Clock Control Register 0
LCDC03 LCDC02 LCDC01 LCDC00
LCDC0
Symbol Address After reset R/W
FFB2H 00H R/W
76543210
LCD source clock (f
LCD
) selection
Note
During f
X
= 5.0 MHz or f
XT
= 32.768 kHz operation During f
CC
= 4.0 MHz or f
XT
= 32.768 kHz operation
LCDC03
0
0
1
1
LCDC02
0
1
0
1
LCD clock (LCDCL) selection
LCDC01
0
0
1
1
LCDC00
0
1
0
1
0000
f
LCD
/2
6
f
LCD
/2
7
f
LCD
/2
8
f
LCD
/2
9
f
XT
(32.768 kHz)
f
X
/2
5
(156.3 kHz)
f
X
/2
6
(78.1 kHz)
f
X
/2
7
(39.1 kHz)
f
CC
/2
5
(125 kHz)
f
CC
/2
6
(62.5 kHz)
f
CC
/2
7
(31.3 kHz)
Note Specify an LCD source clock (fLCD) frequency of at least 32 kHz.
Remarks 1. f
X: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. f
CC: Main system clock oscillation frequency (RC oscillation)
3. f
XT: Subsystem clock oscillation frequency
As an example, Table 15-3 lists the frame frequencies used when fXT (32.768 kHz) is supplied as the LCD
source clock (fLCD).
Caution Set the frame frequency to 128 Hz or lower.
Table 15-3. Frame Frequencies (Hz)
LCD Clock (LCDCL)
Number of time slices
fXT/29
(64 Hz)
fXT/28
(128 Hz)
fXT/27
(256 Hz)
fXT/26
(512 Hz)
3 21 43 85 171Note
4 16 32 64 128
Note This setting is prohibited because it causes the frame frequency to exceed 128 Hz.
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(3) LCD voltage amplification control register 0 (LCDVA0)
LCDVA0 controls the voltage amplification level during the voltage amplifier operation.
LCDVA0 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input clears LCDVA0 to 00H.
Figure 15-5. Format of LCD Voltage Boost Control Register 0
0 GAINLCDVA0
Symbol Address After reset R/W
FFB3H 00H R/W
7654321<0>
GAIN
0
1
1.5 V (specification of the LCD panel used is 4.5 V.)
1.0 V (specification of the LCD panel used is 3 V.)
000000
Reference voltage (VLC2) level selectionNote
Note Select the settings according to the specifications of the LCD panel that is used.
Caution Before changing the LCDVA0 setting, be sure to stop voltage boosting (VAON0 = 0).
Remark The TYP. value is indicated as the reference voltage (VLC2) value.
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15.4 Setting LCD Controller/Driver
Set the LCD controller/driver using the following procedure.
<1> Set the frame frequency using LCD clock control register 0 (LCDC0).
<2> Set the voltage amplification level using LCD voltage amplification control register 0 (LCDVA0).
GAIN = 0: VLC0 = 4.5 V, VLC1 = 3 V, VLC2 = 1. 5 V
GAIN = 1: VLC0 = 3 V, VLC1 = 2 V, VLC2 = 1 V
<3> Set the time division using LCDM00 (bit 0 of LCD display mode register 0 (LCDM0)).
<4> Enable voltage amplification by setting VAON0 (bit 6 of LCDM0) (VAON0 = 1).
<5> Wait for voltage boost wait time (tVAWAIT) after setting VAON0 (See CHAPTER 22 ELECTRICAL
SPECIFICATIONS).
<6> Set LIPS0 (bit 4 of LCDM0) (LIPS0 = 1) and output the deselect potential.
<7> Start output corresponding to each data memory by setting LCDON0 (bit 7 of LCDM0) (LCDON0 =1).
15.5 LCD Display Data Memory
The LCD display data memory is mapped at addresses FA00H to FA17H. Data in the LCD display data memory
can be displayed on the LCD panel using the LCD controller/driver.
Figure 15-6 shows the relationship between the contents of the LCD display data memory and the
segment/common outputs.
That part of the display data memory which is not used for display can be used as ordinary RAM.
Figure 15-6. Relationship Between LCD Display Data Memory Contents and Segment/Common Outputs
S23FA17H
S22FA16H
S21FA15H
S20
S2FA02H
S1FA01H
S0FA00H
COM3 COM2 COM1 COM0
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
Address
Caution No memory has been installed as the higher 4 bits of the LCD display data memory. Be sure to
set 0 to them.
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15.6 Common and Segment Signals
Each pixel of the LCD panel turns on when the potential difference between the corresponding common and
segment signals becomes higher than a specific voltage (LCD drive voltage, VLCD). It turns off when the potential
difference becomes lower than VLCD.
Applying DC voltage to the common and segment signals for an LCD panel would deteriorate it. To avoid this
problem, this LCD panel is driven with AC voltage.
(1) Common signals
Each common signal is selected sequentially according to a specified number of time slots at the timing listed
in Table 15-4. In the static display mode, the same signal is output to COM0 to COM3 in common.
In the three-time slot mode, keep the COM3 pin open.
Table 15-4. COM Signals
COM Signal
Number of Time Slots
COM0 COM1 COM2 COM3
Three-time slot mode Open
Four-time slot mode
(2) Segment signals
The segment signals correspond to 24 bytes of LCD display data memory (FA00H to FA17H). Bits 0, 1, 2,
and 3 of each byte are read in synchronization with COM0, COM1, COM2, and COM3, respectively. If the
contents of each bit are 1, it is converted to the select voltage, and if 0, it is converted to the deselect voltage.
The conversion results are output to the segment pins (S0 to S23).
Check, with the information given above, what combination of the front-surface electrodes (corresponding to
the segment signals) and the rear-surface electrodes (corresponding to the common signals) forms display
patterns in the LCD display data memory, and write the bit data that corresponds to the desired display
pattern on a one-to-one basis.
Bit 3 of the LCD display data memory is not used for LCD display in the three-time slot mode. So this bit can
be used for purposes other than display.
LCD display data memory bits 4 to 7 are fixed to 0.
(3) Output waveforms of common and segment signals
When both common and segment signals are at the select voltage, a display-on voltage of ±VLCD is obtained.
The other combinations of the signals correspond to the display-off voltage.
Figure 15-7 shows the common signal waveforms, and Figure 15-8 shows the voltages and phases of the
common and segment signals.
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Figure 15-7. Common Signal Waveforms
COMn
(Three-time slot mode)
T
F
= 3 × T
V
LC0
V
SS
V
LCD
V
LC1
V
LC2
T
F
= 4 × T
COMn
(Four-time slot mode)
V
LC0
V
LCD
V
LC1
V
LC2
V
SS
T: One LCD clock period TF: Frame frequency
Figure 15-8. Voltages and Phases of Common and Segment Signals
Select Deselect
Common signal
Segment signal
V
LC0
V
SS
V
LCD
V
LC0
V
SS
V
LCD
TT
V
LC2
V
LC2
V
LC1
V
LC1
T: One LCD clock period
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15.7 Display Modes
15.7.1 Three-time slot display example
Figure 15-10 shows how the 8-digit LCD panel having the display pattern shown in Figure 15-9 is connected to the
segment signals (S0 to S23) and the common signals (COM0 to COM2) of the
µ
PD789306 or
µ
PD789316 Subseries
chip. This example displays data “123456.78” in the LCD panel. The contents of the display data memory (addresses
FA00H to FA17H) correspond to this display.
The following description focuses on numeral “6.” ( ) displayed in the third digit. To display “6.” in the LCD panel,
it is necessary to apply the select or deselect voltage to the S6 to S8 pins according to Table 15-5 at the timing of the
common signals COM0 to COM2; see Figure 15-9 for the relationship between the segment signals and LCD
segments.
Table 15-5. Select and Deselect Voltages (COM0 to COM2)
Segment
Common
S6 S7 S8
COM0 Deselect Select Select
COM1 Select Select Select
COM2 Select Select
−
According to Table 15-5, it is determined that the display data memory location (FA06H) that corresponds to S6
must contain x110.
Figure 15-11 shows examples of LCD drive waveforms between the S6 signal and each common signal. When
the select voltage is applied to S6 at the timing of COM1 or COM2, an alternate rectangle waveform, +VLCD/–VLCD, is
generated to turn on the corresponding LCD segment.
Figure 15-9. Three-Time Slot LCD Display Pattern and Electrode Connections
;;
;;
;;
;;
;
;
;;;
;;;
;;
;;
;;
;;
;;
;;
;;
S3n+2 S3n
COM0
COM2
S3n+1
COM1
Remark n = 0 to 7
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Figure 15-10. Example of Connecting Three-Time Slot LCD Panel
001011011101110110111111
001110011011011111001111
×××××××××××××××××××××××× Bit 3
Bit 2
Bit 1
Bit 0
Timing strobe
Data memory address
LCD panel
FA00H
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
FA10H
1
2
3
4
5
6
7
S 0
S 1
S 2
S 3
S 4
S 5
S 6
S 7
S 8
S 9
S 10
S 11
S 12
S 13
S 14
S 15
S 16
S 17
S 18
S 19
S 20
S 21
S 22
S 23
COM 3
COM 2
COM 1
COM 0
Open
00 10 10 00 10 11 00 10
x’ x’ x’ x’ x’ x’ x’ x’
x’: Can be used to store any data because there is no corresponding segment in the LCD panel.
×: Can always be used to store any data because of the three-time slot mode being used.
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Figure 15-11. Three-Time Slot LCD Drive Waveform Examples
V
LC0
V
LC2
COM0
+V
LCD
0
COM0-S9
−V
LCD
V
LC1
+1/3V
LCD
−1/3V
LCD
V
SS0
V
LC0
V
LC2
COM1 V
LC1
V
SS0
V
LC0
V
LC2
COM2 V
LC1
V
SS0
V
LC0
V
LC2
S9 V
LC1
V
SS0
+V
LCD
0
COM1-S9
−V
LCD
+1/3V
LCD
−1/3V
LCD
+V
LCD
0
COM2-S9
−V
LCD
+1/3V
LCD
−1/3V
LCD
T
F
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15.7.2 Four-time slot display example
Figure 15-13 shows how the 12-digit LCD panel having the display pattern shown in Figure 15-12 is connected to
the segment signals (S0 to S23) and the common signals (COM0 to COM3) of the
µ
PD789306 or
µ
PD789316
Subseries chip. This example displays data “123456.789012” in the LCD panel. The contents of the display data
memory (addresses FA00H to FA17H) correspond to this display.
The following description focuses on numeral “6.” ( ) displayed in the seventh digit. To display “6.” in the LCD
panel, it is necessary to apply the select or deselect voltage to the S12 and S13 pins according to Table 15-6 at the
timing of the common signals COM0 to COM3; see Figure 15-12 for the relationship between the segment signals and
LCD segments.
Table 15-6. Select and Deselect Voltages (COM0 to COM3)
Segment
Common
S12 S13
COM0 Select Select
COM1 Deselect Select
COM2 Select Select
COM3 Select Select
According to Table 15-6, it is determined that the display data memory location (FA0CH) that corresponds to S12
must contain 1101.
Figure 15-14 shows examples of LCD drive waveforms between the S12 signal and each common signal. When
the select voltage is applied to S12 at the timing of COM0, an alternate rectangle waveform, +VLCD/–VLCD, is
generated to turn on the corresponding LCD segment.
Figure 15-12. Four-Time Slot LCD Display Pattern and Electrode Connections
Remark n = 0 to 11
;;
;;
;;
;;
;
;
;;
;;
COM0
S
2n
COM1
S
2n+1
COM2
COM3
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Figure 15-13. Example of Connecting Four-Time Slot LCD Panel
000101101111111111110001
011111111010011111010111
011001010111011101110110
001010001011001000100010 Bit 3
Bit 2
Bit 1
Bit 0
Timing strobe
Data memory address
LCD panel
FA00H
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
FA10H
1
2
3
4
5
6
7
S 0
S 1
S 2
S 3
S 4
S 5
S 6
S 7
S 8
S 9
S 10
S 11
S 12
S 13
S 14
S 15
S 16
S 17
S 18
S 19
S 20
S 21
S 22
S 23
COM 3
COM 2
COM 1
COM 0
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Figure 15-14. Four-Time Slot LCD Drive Waveform Examples
T
F
V
LC0
V
LC2
COM0
+V
LCD
0
COM0-S16
−V
LCD
V
LC1
+1/3V
LCD
−1/3V
LCD
V
SS
V
LC0
V
LC2
COM1 V
LC1
V
SS
V
LC0
V
LC2
COM2 V
LC1
V
SS
V
LC0
V
LC2
COM3 V
LC1
V
SS
+V
LCD
0
COM1-S16
−V
LCD
+1/3V
LCD
−1/3V
LCD
V
LC0
V
LC2
S16 V
LC1
V
SS
Remark The waveforms for COM2 to S16 and COM3 to S16 are omitted.
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15.8 Supplying LCD Drive Voltages VLC0, VLC1, and VLC2
The
µ
PD789306, 789316 Subseries contains a booster circuit (×3 only) to generate a supply voltage to drive the
LCD. The internal LCD reference voltage is output from the VLC2 pin. A voltage two times higher than that on VLC2 is
output from the VLC1 pin and a voltage three times higher than that on VLC2 is output from the VLC0 pin.
The LCD reference voltage (VLC2) can be specified by setting LCD boost control register 0 (LCDVA0).
The
µ
PD789306, 789316 Subseries requires an external capacitor (recommended value: 0.47
µ
F) because it
employs a capacitance division method to generate a supply voltage to drive the LCD.
Table 15-7. Output Voltages of VLC0 to VLC2 Pins
LCDVA0 GAIN = 0 GAIN = 1
LCD drive power supply pin
VLC0 4.5 V 3.0 V
VLC1 3.0 V 2.0 V
VLC2 (LCD reference voltage) 1.5 V 1.0 V
Cautions 1. When using the LCD function, do not leave the VLC0, VLC1, and VLC2 pins open. Refer to Figure
15-15 for connection.
2. Since the LCD drive voltage is separate from the main power supply, a constant voltage can
be supplied regardless of VDD fluctuation.
Figure 15-15. Example of Connecting Pins for LCD Driver
V
LC0
V
LC1
V
LC2
C2 C3 C4
CAPH
C1
External pin
C1 = C2 = C3 = C4 = 0.47 F
CAPL
µ
Remark Use a capacitor with as little leakage as possible.
In addition, make C1 a nonpolar capacitor.
User’s Manual U14800EJ3V0UD 237
CHAPTER 16 INTERRUPT FUNCTIONS
16.1 Interrupt Function Types
The following two types of interrupt functions are used.
(1) Non-maskable interrupt
This interrupt is acknowledged unconditionally. It does not undergo interrupt priority control and is given top
priority over all other interrupt requests.
A standby release signal is generated.
One interrupt source from the watchdog timer is incorporated as a non-maskable interrupt.
(2) Maskable interrupt
This interrupt undergoes mask control. If two or more interrupts with the same priority are simultaneously
generated, each interrupt has a predetermined priority as shown in Table 16-1.
A standby release signal is generated.
5 external and 9 internal interrupt sources are incorporated as maskable interrupts.
16.2 Interrupt Sources and Configuration
A total of 15 non-maskable and maskable interrupts are incorporated as interrupt sources (see Table
16-1).
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Table 16-1. Interrupt Source List
Interrupt Source Interrupt Type PriorityNote 1
Name Trigger
Internal/
External
Vector
Table
Address
Basic
Configuration
TypeNote 2
Non-maskable − INTWDT Watchdog timer overflow (with
watchdog timer mode 1 selected)
(A)
0 INTWDT Watchdog timer overflow (with interval
timer mode selected)
Internal 0004H
(B)
1 INTP0 0006H
2 INTP1 0008H
3 INTP2 000AH
4 INTP3
Pin input edge detection External
000CH
(C)
INTSR20 End of serial interface 20 UART
reception
5
INTCSI20 End of serial interface 20 3-wire SIO
transfer reception
000EH
6 INTCSI10 End of serial interface 10 3-wire SIO
transfer reception
0010H
7 INTST20 End of serial interface 20 UART
transmission
0012H
8 INTWTI Interval timer interrupt 0014H
9 INTTM20 Generation of match signal of 16-bit
timer 20
0016H
10 INTTM30 Generation of match signal of 8-bit
timer 30
0018H
11 INTTM40 Generation of match signal of 8-bit
timer/event counter 40
001AH
12 INTWT Watch timer interrupt
Internal
001EH
(B)
Maskable
13 INTKR00 Key return signal detection External 0020H (C)
Notes 1. Priority is the priority order when several maskable interrupts are generated at the same time. 0 is the
highest order and 13 is the lowest order.
2. Basic configuration types (A) to (C) correspond to (A) to (C) in Figure 16-1.
Remark There are two interrupt sources for the watchdog timer (INTWDT): non-maskable and maskable
interrupts (internal). Either one (but not both) should be selected for actual use.
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User’s Manual U14800EJ3V0UD 239
Figure 16-1. Basic Configuration of Interrupt Function
(A) Internal non-maskable interrupt
Internal bus
Interrupt request Vector table
address generator
Standby release signal
(B) Internal maskable interrupt
MK
IF
IE
Internal bus
Interrupt request
Vector table
address generator
Standby release signal
(C) External maskable interrupt
MK
IF
IE
Internal bus
INTM0, INTM1, KRM00
Interrupt
request
Edge
detector
Vector table
address generator
Standby
release signal
INTP0: External interrupt mode register 0
INTP1: External interrupt mode register 1
KRM00: Key return mode register 00
IF: Interrupt request flag
IE: Interrupt enable flag
MK: Interrupt mask flag
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16.3 Registers Controlling Interrupt Function
The following five types of registers are used to control the interrupt functions.
• Interrupt request flag registers 0, 1 (IF0 and IF1)
• Interrupt mask flag registers 0, 1 (MK0 and MK1)
• External interrupt mode registers 0, 1 (INTM0 and INTM1)
• Program status word (PSW)
• Key return mode register 00 (KRM00)
Table 16-2 gives a listing of interrupt request flag and interrupt mask flag names corresponding to interrupt
requests.
Table 16-2. Flags Corresponding to Interrupt Request Signal Name
Interrupt Request Signal Name Interrupt Request Flag Interrupt Mask Flag
INTWDT
INTP0
INTP1
INTP2
INTP3
INTSR20/INTCSI20
INTCSI10
INTST20
INTWTI
INTTM20
INTTM30
INTTM40
INTWT
INTKR00
WDTIF
PIF0
PIF1
PIF2
PIF3
SRIF20
CSIIF10
STIF20
WTIIF
TMIF20
TMIF30
TMIF40
WTIF
KRIF00
WDTMK
PMK0
PMK1
PMK2
PMK3
SRMK20
CSIMK10
STMK20
WTIMK
TMMK20
TMMK30
TMMK40
WTMK
KRMK00
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(1) Interrupt request flag registers 0, 1 (IF0 and IF1)
The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction
is executed. It is cleared to 0 when an instruction is executed upon acknowledgement of an interrupt request
or upon RESET input.
IF0 and IF1 are set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears IF0 and IF1 to 00H.
Figure 16-2. Format of Interrupt Request Flag Registers
0
1
0
KRIF00
WTIF 0
TMIF40 TMIF30 TMIF20
WTIIFIF1 FFE1H 00H R/W
Interrupt request flag
No interrupt request signal is generated
Interrupt request signal is generated; Interrupt request state
XXIFX
<6> <5> 4 <3> <2> <1>7 <0>
STIF20
CSIIF10
SRIF20
PIF3 PIF2 PIF1 PIF0
WDTIF
IF0
R/W
FFE0H 00H R/W
Symbol Address After reset
<6> <5> <4> <3> <2> <1><7> <0>
Cautions 1. Bits 4 and 7 of IF1 must be set to 0.
2. The WDTIF flag is R/W enabled only when a watchdog timer is used as an interval timer. If
the watchdog timer mode 1 or 2 is used, set the WDTIF flag to 0.
3. Because port 3 has an alternate function as the external interrupt input, when the output
level is changed by specifying the output mode of the port function, an interrupt request flag
is set. Therefore, the interrupt mask flag should be set to 1 before using the output mode.
4. If an interrupt is acknowledged, the interrupt request flag is automatically cleared before the
interrupt routine is entered.
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(2) Interrupt mask flag registers 0, 1 (MK0 and MK1)
The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service.
MK0 and MK1 are set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets MK0 and MK1 to FFH.
Figure 16-3. Format of Interrupt Mask Flag Registers
0
1
1
KRMK00
WTMK
1
TMMK40 TMMK30 TMMK20
WTIMK
MK1 FFE5H FFH R/W
Interrupt servicing control
Interrupt servicing enabled
Interrupt servicing disabled
<6> <5> 4 <3> <2> <1>7 <0>
XXMK
STMK20
CSIMK10
SRMK20
PMK3 PMK2 PMK1 PMK0
WDTMK
MK0
R/W
FFE4H FFH R/W
Symbol Address After reset
<6> <5> <4> <3> <2> <1><7> <0>
Cautions 1. Bits 4 and 7 of MK1 must be set to 1.
2. If the WDTMK flag is read when the watchdog timer is used in watchdog timer mode 1 or 2,
its value becomes undefined.
3. Because port 3 has an alternate function as the external interrupt input, when the output
level is changed by specifying the output mode of the port function, an interrupt request flag
is set. Therefore, the interrupt mask flag should be set to 1 before using the output mode.
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(3) External interrupt mode register 0 (INTM0)
This register is used to specify a valid edge for INTP0 to INTP2.
INTM0 is set with an 8-bit memory manipulation instruction.
RESET input clears INTM0 to 00H.
Figure 16-4. Format of External Interrupt Mode Register 0
0
0
1
1
ES21 ES20 ES11 ES10 ES01 ES00 0 0INTM0
R/W
FFECH 00H R/W
76543210
0
1
0
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
Symbol Address After reset
INTP0 valid edge selection
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
INTP1 valid edge selection
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
INTP2 valid edge selection
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
ES00
ES01
ES11 ES10
ES20ES21
Cautions 1. Bits 0 and 1 must be set to 0.
2. Before setting the INTM0 register, be sure to set the relevant interrupt mask flag to 1 to
disable interrupts.
After that, clear (0) the interrupt request flag, then set the interrupt mask flag to 0 to enable
interrupts.
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(4) External interrupt mode register 1 (INTM1)
INTM1 is used to specify a valid edge for INTP3.
INTM1 is set with an 8-bit memory manipulation instruction.
RESET input clears INTM1 to 00H.
Figure 16-5. Format of External Interrupt Mode Register 1
0 0 0 0 0 0 ES31 ES30INTM1
76543210
ES31
0
0
1
1
INTP3 valid edge selectionES30
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
Symbol Address After reset R/W
FFEDH 00H R/W
Cautions 1. Bits 2 to 7 must be set to 0.
2. Before setting INTM1, set PMK3 to 1 to disable interrupts.
After that, clear (0) PIF3, then set PMK3 to 0 to enable interrupts.
(5) Program status word (PSW)
The program status word is a register used to hold the instruction execution result and the current status for
interrupt requests. The IE flag to set maskable interrupt enable/disable is mapped.
Besides 8-bit unit read/write, this register can carry out operations with a bit manipulation instruction and
dedicated instructions (EI, DI). When a vectored interrupt is acknowledged, the PSW is automatically saved
into a stack, and the IE flag is reset to 0.
RESET input sets PSW to 02H.
Figure 16-6. Configuration of Program Status Word
IE Z 0 AC 0 0 1 CYPSW
76543210
IE
0
1
02H
Symbol After reset
Used when normal instruction is executed
Interrupt acknowledgement enabled/disabled
Disabled
Enabled
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(6) Key return mode register 00 (KRM00)
This register sets the pin that detects a key return signal (falling edge of port 0).
KRM00 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears KRM00 to 00H.
Figure 16-7. Format of Key Return Mode Register 00
0
1
00
00000
KRM000
KRM00 FFF5H 00H R/W
Address After reset R/W
Key return signal detection control
No detection
Detection (detecting falling edge of port 0)
65432170
KRM000
Symbol
Cautions 1. Bits 1 to 7 must be set to 0.
2. Before setting KRM00, always set bit 6 of MK1 (KRMK00 = 1) to disable interrupts. After
setting KRM00, clear KRMK00 after clearing bit 6 of IF1 (KRIF00 = 0) to enable interrupts.
3. When P00 to P03 are in input mode, on-chip pull-up resistors are connected to P00 to P03 by
the setting of KRM000. After switching to output mode, the on-chip pull-up resistors are cut
off. However, key return signal detection continues.
4. The key return signal cannot be detected while even one of the pins that specify detection of
the key return signal is low, even if a falling edge is generated at other key return pins.
Figure 16-8. Block Diagram of Falling Edge Detector
P00/KR0
P01/KR1
P02/KR2
P03/KR3
Falling edge detector
KRMK00
KRIF00 set signal
Standby release
signal
Key return mode register 00 (KRM00)
Note
Selector
Note Selector that selects the pin used for falling edge input
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16.4 Interrupt Servicing Operation
16.4.1 Non-maskable interrupt request acknowledgment operation
The non-maskable interrupt request is unconditionally acknowledged even when interrupts are disabled. It is not
subject to interrupt priority control and takes precedence over all other interrupts.
When the non-maskable interrupt request is acknowledged, PSW and PC are saved to the stack in that order, the
IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches.
Figure 16-9 shows the flow from non-maskable interrupt request generation to acknowledgement, Figure 16-10
shows the timing of non-maskable interrupt acknowledgement, and Figure 16-11 shows the acknowledgement
operation when a number of non-maskable interrupts are generated.
Caution During non-maskable interrupt service program execution, do not input another non-maskable
interrupt request; if it is input, the service program will be interrupted and the new non-
maskable interrupt request will be acknowledged.
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Figure 16-9. Flow from Generation of Non-Maskable Interrupt Request to Acknowledgment
Start
WDTM4 = 1
(watchdog timer mode
is selected)
Interval timer
No
WDT
overflows
No
Yes
Reset processing
No
Yes
Yes
Interrupt request is generated
Interrupt servicing starts
WDTM3 = 0
(non-maskable interrupt
is selected)
WDTM: Watchdog timer mode register
WDT: Watchdog timer
Figure 16-10. Timing of Non-Maskable Interrupt Request Acknowledgment
Instruction Instruction
Saving PSW and PC, and
jump to interrupt servicing Interrupt servicing program
CPU processing
WDTIF
Figure 16-11. Non-Maskable Interrupt Request Acknowledgment
Second interrupt servicing
First interrupt servicing
NMI request
(second)
NMI request
(first)
Main routine
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16.4.2 Maskable interrupt request acknowledgment operation
A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the
corresponding interrupt mask flag is cleared to 0. A vectored interrupt is acknowledged in the interrupt enabled status
(when the IE flag is set to 1).
The time required to start the interrupt servicing after a maskable interrupt request has been generated is shown in
Table 16-3.
Refer to Figures 16-13 and 16-14 for the timing of interrupt request acknowledgement.
Table 16-3. Time from Generation of Maskable Interrupt Request to Servicing
Minimum Time Maximum TimeNote
9 clocks 19 clocks
Note The wait time is maximum when an interrupt request is generated immediately before
BT or BF instruction.
Remark 1 clock: (fCPU: CPU clock)
When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting
from the one assigned the highest priority by the priority specification flag.
A pending interrupt is acknowledged when the status where it can be acknowledged is set.
Figure 16-12 shows the algorithm of interrupt request acknowledgement.
When a maskable interrupt request is acknowledged, the PSW and PC are saved to the stack in that order, the IE
flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to the PC, and
execution branches.
To return from interrupt servicing, use the RETI instruction.
Figure 16-12. Interrupt Request Acknowledgment Program Algorithm
Start
xxIF = 1 ?
xxMK = 0 ?
IE = 1 ?
Vectored interrupt
servicing
Yes (Interrupt request generated)
Yes
Yes
No
No
No
Interrupt request pending
Interrupt request pending
xxIF: Interrupt request flag
xxMK: Interrupt mask flag
IE: Flag to control maskable interrupt request acknowledgement (1 = enable, 0 = disable)
1
fCPU
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Figure 16-13. Interrupt Request Acknowledgment Timing (Example: MOV A, r)
Clock
CPU MOV A, r
Saving PSW and PC, and
jump to interrupt servicing
8 clocks
Interrupt servicing program
Interrupt
If the interrupt request has generated an interrupt request flag (XXIF) by the time the instruction clocks under
execution, n clocks (n = 4 to 10), are n − 1, interrupt request acknowledgment processing will start following the
completion of the instruction under execution. Figure 16-13 shows an example using the 8-bit data transfer instruction
MOV A, r. Because this instruction is executed in 4 clocks, if an interrupt request is generated between the start of
execution and the 3rd clock, interrupt request acknowledgment processing will take place following the completion of
MOV A, r.
Figure 16-14. Interrupt Request Acknowledgment Timing
(When Interrupt Request Flag Is Generated in Final Clock Under Execution)
Clock
CPU NOP MOV A, r Saving PSW and PC, and
jump to interrupt servicing
Interrupt servicing
program
Interrupt
8 clocks
If the interrupt request flag (XXIF) is generated in the final clock of the instruction, interrupt request
acknowledgment processing will begin after execution of the next instruction is complete.
Figure 16-14 shows an example whereby an interrupt request was generated in the 2nd clock of NOP (a 2-clock
instruction). In this case, the interrupt request will be processed after execution of MOV A, r, which follows NOP, is
complete.
Caution When interrupt request flag registers 0 and 1 (IF0 and IF1), or interrupt mask flag registers 0 and
1 (MK0 and MK1) are being accessed, interrupt requests will be held pending.
16.4.3 Multiple interrupt servicing
Multiple interrupts, in which another interrupt request is acknowledged while an interrupt request being serviced,
can be serviced using the priority order. If multiple interrupts are generated at the same time, they are serviced in the
order according to the priority assigned to each interrupt request in advance (refer to Table 16-1).
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Figure 16-15. Example of Multiple Interrupts
Example 1. Acknowledging multiple interrupts
INTyy
EI
Main servicing
EI
INTyy servicingINTxx servicing
RETI
IE = 0
INTxx
RETI
IE = 0
The interrupt request INTyy is acknowledged during the servicing of interrupt INTxx and multiple interrupts are
performed. Before each interrupt request is acknowledged, the EI instruction is issued and the interrupt request is
enabled.
Example 2. Multiple interrupts are not performed because interrupts are disabled
INTyy
EI
Main servicing
RETI
INTyy servicingINTxx servicing
IE = 0
INTxx
RETI
INTyy is held pending
IE = 0
Because interrupt requests are disabled (the EI instruction has not been issued) in the interrupt INTxx servicing,
the interrupt request INTyy is not acknowledged and multiple interrupts are not performed. INTyy is held pending and
is acknowledged after INTxx servicing is completed.
IE = 0: Interrupt requests disabled
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16.4.4 Putting interrupt requests on hold
If an interrupt request (such as a maskable, non-maskable, or external interrupt) is generated when a certain type
of instruction is being executed, the interrupt request will not be acknowledged until the instruction is completed. Such
instructions (interrupt request pending instructions) are as follows.
• Instructions that manipulate interrupt request flag registers 0, 1 (IF0 and IF1)
• Instructions that manipulate interrupt mask flag registers 0, 1 (MK0 and MK1)
252 User’s Manual U14800EJ3V0UD
CHAPTER 17 STANDBY FUNCTION
17.1 Standby Function and Configuration
17.1.1 Standby function
The standby function is to reduce the power consumption of the system and can be effected in the following two
modes:
(1) HALT mode
This mode is set when the HALT instruction is executed. The HALT mode stops the operation clock of the
CPU. The system clock oscillator continues oscillating. This mode does not reduce the power consumption
as much as the STOP mode, but is useful for resuming processing immediately when an interrupt request is
generated, or for intermittent operations.
(2) STOP mode
This mode is set when the STOP instruction is executed. The STOP mode stops the main system clock
oscillator and stops the entire system. The power consumption of the CPU can be substantially reduced in
this mode.
The data memory can be retained at the low voltage (VDD = 1.8 V). Therefore, this mode is useful for
retaining the contents of the data memory at an extremely low current.
The STOP mode can be released by an interrupt request, so that this mode can be used for intermittent
operation. However, some time is required until the system clock oscillator stabilizes after the STOP mode
has been released. If processing must be resumed immediately by using an interrupt request, therefore, use
the HALT mode.
In both modes, the previous contents of the registers, flags, and data memory before setting the standby mode are
all retained. In addition, the statuses of the output latch of the I/O ports and output buffer are also retained.
Caution To set the STOP mode, be sure to stop the operations of the peripheral hardware, and then
execute the STOP instruction.
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17.1.2 Register controlling standby function
The wait time after the STOP mode is released upon interrupt request until oscillation stabilizes is controlled with
the oscillation stabilization time select register (OSTS)Note.
OSTS is set with an 8-bit memory manipulation instruction.
RESET input sets OSTS to 04H. However, it takes 215/fX, not 217/fX, after RESET input.
Note The
µ
PD789306 Subseries only.
The
µ
PD789316 Subseries does not have an oscillation stabilization time select register. The oscillation
stabilization time for the
µ
PD789316 Subseries is fixed at 27/fCC.
Figure 17-1. Format of Oscillation Stabilization Time Select Register
OSTS2
0
0
1
00000
OSTS2 OSTS1 OSTS0
OSTS
R/W
FFFAH 04H R/W
76543210
OSTS1
0
1
0
2
12
/f
X
2
15
/f
X
2
17
/f
X
(819 s)
(6.55 ms)
(26.2 ms)
OSTS0
0
0
0
Setting prohibited
Symbol Address After reset
Oscillation stabilization time selection
Other than above
µ
Caution The wait time after the STOP mode is released does not include the time from STOP mode
release to clock oscillation start (“a” in the figure below), regardless of whether STOP mode is
released by RESET input or by interrupt generation.
V
SS
a
STOP mode release
X1 pin voltage
waveform
Remarks 1. f
X: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. The parenthesized values apply to operation at fX = 5.0 MHz.
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17.2 Standby Function Operation
17.2.1 HALT mode
(1) HALT mode
The HALT mode is set by executing the HALT instruction.
The operation status in the HALT mode is shown in the following table.
Table 17-1. HALT Mode Operating Status
HALT Mode Operation Status While The Main
System Clock Is Running
HALT Mode Operation Status While The
Subsystem Clock Is Running
Item
While the subsystem
clock is running
While the subsystem
clock is not running
While the main system
clock is running
While the main system
clock is not running
Main system clock Oscillation enabled Oscillation stopped
CPU Operation stopped
Port (output latch) Remains in the state existing before the selection of HALT mode.
16-bit timer 20 Operation enabled Operation stopped
8-bit timer 30 Operation enabledNote 1
8-bit timer 40
Operation enabled
Operation enabledNote 2
Watch timer Operation enabled Operation enabledNote 3 Operation enabled Operation enabledNote 4
Watchdog timer Operation enabled Operation stopped
Serial interface 10
Serial interface 20
Operation enabled Operation enabledNote 5
LCD controller/driver Operation enabled Operation enabledNote 3 Operation enabled Operation enabledNote 4
External interrupt Operation enabledNote 6
Notes 1. Operation is enabled only when input signal from timer 40 (timer 40 operation is enabled) is selected as
the count clock.
2. Operation is enabled when TMI40 is selected as the count clock.
3. Operation is enabled while the main system clock is selected.
4. Operation is enabled while the subsystem clock is selected.
5. Operation is enabled only when external clock is selected.
6. Maskable interrupt that is not masked
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(2) Releasing HALT mode
The HALT mode can be released by the following three types of sources:
(a) Releasing by unmasked interrupt request
The HALT mode is released by an unmasked interrupt request. In this case, if the interrupt is enabled
to be acknowledged, vectored interrupt processing is performed. If the interrupt is disabled, the
instruction at the next address is executed.
Figure 17-2. Releasing HALT Mode by Interrupt
HALT
instruction
Standby
release signal
Wait
WaitHALT mode
Operation
mode Operation mode
Clock Oscillation
Remarks 1. The broken line indicates the case where the interrupt request that has released the standby mode
is acknowledged.
2. The wait time is as follows:
• When vectored interrupt processing is performed: 9 to 10 clocks
• When vectored interrupt processing is not performed: 1 to 2 clocks
(b) Releasing by non-maskable interrupt request
The HALT mode is released regardless of whether the interrupt is enabled or disabled, and vectored
interrupt processing is performed.
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(c) Releasing by RESET input
When the HALT mode is released by the RESET signal, execution branches to the reset vector address
in the same manner as the ordinary reset operation, and program execution is started.
Figure 17-3. Releasing HALT Mode by RESET Input
HALT
instruction
RESET
signal
Wait
Note
Reset
period
HALT mode
Operation
mode
Oscillation
stabilization
wait status
Clock
Operation
mode
Oscillation
stops
Oscillation Oscillation
Note For the
µ
PD789306 Subseries, 215/fX: 6.55 ms (@ fX = 5.0 MHz operation)
For the
µ
PD789316 Subseries, 27/fCC: 32
µ
s (@ fCC = 4.0 MHz operation)
Remarks 1. f
X: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. f
CC: Main system clock oscillation frequency (RC oscillation)
Table 17-2. Operation After Releasing HALT Mode
Releasing Source MKxx IE Operation
0 0 Executes next address instruction
0 1 Executes interrupt servicing
Maskable interrupt request
1 x Retains HALT mode
Non-maskable interrupt request − x Executes interrupt servicing
RESET input -−- − Reset processing
x: don’t care
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17.2.2 STOP mode
(1) Setting and operation status of STOP mode
The STOP mode is set by executing the STOP instruction.
Caution Because the standby mode can be released by an interrupt request signal, the standby
mode is released as soon as it is set if there is an interrupt source whose interrupt request
flag is set and interrupt mask flag is reset. When the STOP mode is set, therefore, the
HALT mode is set immediately after the STOP instruction has been executed, the wait time
set by the oscillation stabilization time select register (OSTS) elapses, and then an
operation mode is set.
The operation status in the STOP mode is shown in the following table.
Table 17-3. STOP Mode Operating Status
STOP Mode Operation Status While The Main System Clock Is Running
Item
While the subsystem clock is running While the subsystem clock is not running
Main system clock Oscillation stopped
CPU Operation stopped
Port (output latch) Remains in the state existing before the selection of STOP mode.
16-bit timer 20 Operation stopped
8-bit timer 30 Operation enabledNote 1
8-bit timer 40 Operation enabledNote 2
Watch timer Operation enabledNote 3 Operation stopped
Watchdog timer Operation stopped
Serial interface 10
Serial interface 20
Operation enabledNote 4
LCD controller/driver Operation enabledNote 3 Operation stopped
External interrupt Operation enabledNote 5
Notes 1. Operation is enabled only when input signal from timer 40 (timer 40 operation is enabled) is selected as
the count clock.
2. Operation is enabled when TMI40 is selected as the count clock.
3. Operation is enabled while the subsystem clock is selected.
4. Operation is enabled only when external clock is selected.
5. Maskable interrupt that is not masked
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(2) Releasing STOP mode
The STOP mode can be released by the following two types of sources:
(a) Releasing by unmasked interrupt request
The STOP mode can be released by an unmasked interrupt request. In this case, if the interrupt is
enabled to be acknowledged, vectored interrupt processing is performed, after the oscillation
stabilization time has elapsed. If the interrupt is disabled, the instruction at the next address is executed.
Figure 17-4. Releasing STOP Mode by Interrupt
STOP
instruction
Standby
release signal
Wait
Note
(set time by OSTS)
STOP mode
Operation
mode
Oscillation stabilization
wait status
Clock
Operation
mode
Oscillation
stops Oscillation
Oscillation
Note The
µ
PD789316 Subseries does not have OSTS and wait is fixed at 27/fCC.
Remark The broken line indicates the case where the interrupt request that has released the standby mode is
acknowledged.
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(b) Releasing by RESET input
When the STOP mode is released by the RESET signal, the reset operation is performed after the
oscillation stabilization time has elapsed.
Figure 17-5. Releasing STOP Mode by RESET Input
STOP
instruction
RESET
signal
WaitNote
STOP mode
Operation
mode
Oscillation
stabilization
wait status
Clock
Operation
mode
Oscillation
stops Oscillation
Oscillation
Reset
period
Note For the
µ
PD789306 Subseries, 215/fX: 6.55 ms (@ fX = 5.0 MHz operation)
For the
µ
PD789316 Subseries, 27/fCC: 32
µ
s (@ fCC = 4.0 MHz operation)
Remarks 1. f
X: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. f
CC: Main system clock oscillation frequency (RC oscillation)
Table 17-4. Operation After Releasing STOP Mode
Releasing Source MKxx IE Operation
Maskable interrupt request 0 0 Executes next address instruction
0 1 Executes interrupt servicing
1 x Retains STOP mode
RESET input − -−- Reset processing
x: don’t care
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CHAPTER 18 RESET FUNCTION
The following two operations are available to generate reset signals.
(1) External reset input by RESET pin
(2) Internal reset by watchdog timer runaway time detection
External and internal reset have no functional differences. In both cases, program execution starts at the address
at 0000H and 0001H by RESET input.
When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each hardware
is set to the status shown in Table 18-1. Each pin has a high impedance during reset input or during oscillation
stabilization time just after reset clear.
When a high level is input to the RESET pin, the reset is cleared and program execution is started after the
oscillation stabilization time has elapsed. The reset applied by the watchdog timer overflow is automatically cleared
after reset, and program execution is started after the oscillation stabilization time has elapsed (see Figures 18-2 to
18-4.)
Cautions 1. For an external reset, input a low level for 10
µ
s or more to the RESET pin.
2. When the STOP mode is cleared by reset, the STOP mode contents are held during reset
input. However, the port pins become high impedance.
Figure 18-1. Block Diagram of Reset Function
RESET
Interrupt function
Count clock
Reset controller
Watchdog timer
Over-
flow
Reset signal
Stop
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Figure 18-2. Reset Timing by RESET Input
X1, CL1
RESET
Internal
reset signal
Port pin
During normal
operation
Delay Delay
Hi-Z
Reset period
(oscillation stops)
Normal operation
(reset processing)
Oscillation
stabilization
time wait
Figure 18-3. Reset Timing by Overflow in Watchdog Timer
X1, CL1
Overflow in
watchdog timer
Internal
reset signal
Port pin Hi-Z
During normal
operation
Reset period
(oscillation
continues)
Normal operation
(reset processing)
Oscillation
stabilization
time wait
Figure 18-4. Reset Timing by RESET Input in STOP Mode
X1, CL1
RESET
Internal
reset signal
Port pin
Delay Delay
Hi-Z
STOP instruction execution
During normal
operation
Reset period
(oscillation stops)
Stop status
(oscillation stops)
Normal operation
(reset processing)
Oscillation
stabilization
time wait
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Table 18-1. Hardware Status After Reset
Hardware Status After Reset
Program counter (PC)Note 1 The contents of reset
vector tables (0000H
and 0001H) are set.
Stack pointer (SP) Undefined
Program status word (PSW) 02H
Data memory UndefinedNote 2 RAM
General-purpose register UndefinedNote 2
Port (P0 to P3, P5) (Output latch) 00H
Port mode register (PM0 to PM3, PM5) FFH
Pull-up resistor option register (PU0, PUB2, PUB3) 00H
Processor clock control register (PCC) 02H
Suboscillation mode register (SCKM) 00H
Subclock control register (CSS) 00H
Oscillation stabilization time select register (OSTS)Note 3 04H
Timer counter (TM20) 0000H
Compare register (CR20) FFFFH
Control register (TMC20) 00H
16-bit timer 20
Capture register (TCP20) Undefined
Timer counter (TM30, TM40) 00H
Compare register (CR30, CR40, CRH40) Undefined
8-bit timer 30, 40
Mode control register (TMC30, TMC40) 00H
Watch timer Mode control register (WTM) 00H
Clock select register (WDCS) 00H Watchdog timer
Mode register (WDTM) 00H
Serial operation mode register (CSIM10, CSIM20) 00H
Asynchronous serial interface mode register (ASIM20) 00H
Asynchronous serial interface status register (ASIS20) 00H
Baud rate generator control register (BRGC20) 00H
Transmit shift register (TXS20) FFH
Serial interface 20
Receive buffer register (RXB20) Undefined
Display mode register (LCDM0) 00H
Clock control register (LCDC0) 00H
LCD controller/driver
Voltage amplification control register (LCDVA0) 00H
Request flag register (IF0, IF1) 00H
Mask flag register (MK0, MK1) FFH
External interrupt mode register (INTM0, INTM1) 00H
Interrupt
Key return mode register (KRM00) 00H
Notes 1. During reset input and oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined. All other hardware remains unchanged after reset.
2. The post-reset values are retained in the standby mode.
3.
µ
PD789306 Subseries only
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CHAPTER 19 FLASH MEMORY
The
µ
PD78F9306, 78F9316 are available as the flash memory versions of the
µ
PD789306, 789316 Subseries.
The
µ
PD78F9306 is a version with the internal ROM of the
µ
PD789304, 789306 replaced with flash memory and
the
µ
PD78F9316 is a version with the internal ROM of the
µ
PD789314, 789316 replaced with flash memory. The
differences between the
µ
PD78F9306, 78F9316 and the mask ROM versions are shown in Table 19-1.
Table 19-1. Differences Between
µ
PD78F9306, 78F9316 and Mask ROM Versions
Flash Memory Version Mask ROM Version Part Number
Item
µ
PD78F9306
µ
PD78F9316
µ
PD789304
µ
PD789306
µ
PD789314
µ
PD789316
ROM 16 KB 8 KB 16 KB 8 KB 16 KB
High-speed RAM 512 bytes
Internal
memory
LCD display RAM 24 × 4 bits
System clock Ceramic/
crystal
oscillation
RC
oscillation
Ceramic/crystal oscillation RC oscillation
IC pin Not provided Provided
VPP pin Provided Not provided
Pull-up resistor 19 (software control: 19) 23 (software control: 19, mask option control: 4)
Electrical specifications Refer to CHAPTER 22 ELECTRICAL SPECIFICATIONS.
Caution There are differences in noise immunity and noise radiation between the flash memory and mask
ROM versions. When pre-producing an application set with the flash memory version and then
mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the
commercial samples (not engineering samples) of the mask ROM version.
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19.1 Flash Memory Characteristics
Flash memory programming is performed by connecting a dedicated flash programmer (Flashpro III (part no. FL-
PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)) to the target system with the
µ
PD78F9306, 78F9316 mounted
on the target system (on-board). A flash memory program adapter (FA adapter), which is a target board used
exclusively for programming, is also provided.
Remark FL-PR3, FL-PR4, and the program adapter are products made by Naito Densei Machida Mfg. Co., Ltd.
(TEL +81-45-475-4191).
Programming using flash memory has the following advantages.
• Software can be modified after the microcontroller is solder-mounted on the target system.
• Distinguishing software facilities small-quantity, varied model production
• Easy data adjustment when starting mass production
19.1.1 Programming environment
The following shows the environment required for
µ
PD78F9306, 78F9316 flash memory programming.
When Flashpro III (part no. FL-PR3, PG-FP3) or Flashpro IV (part no. FL-PR4, PG-FP4) is used as a dedicated
flash programmer, a host machine is required to control the dedicated flash programmer. Communication between the
host machine and flash programmer is performed via RS-232C/USB (Rev. 1.1).
For details, refer to the manuals for Flashpro III/Flashpro IV.
Remark USB is supported by Flashpro IV only.
Figure 19-1. Environment for Writing Program to Flash Memory
Host machine
RS-232C
USB
Dedicated flash
programmer
PD78F9306
PD78F9316
V
PP
V
DD
V
SS
RESET
3-wire serial I/O
or UART
µ
µ
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19.1.2 Communication mode
Use the communication mode shown in Table 19-2 to perform communication between the dedicated flash
programmer and
µ
PD78F9306, 78F9316.
Table 19-2. Communication Mode List
TYPE SettingNote 1
CPU Clock
Communication
Mode COMM PORT SIO Clock
In Flashpro On Target Board
Multiple
Rate
Pins Used Number of VPP
Pulses
3-wire serial
I/O
SIO ch-0
(3-wire, sync.)
100 Hz to
1.25 MHzNote 2
1, 2, 4, 5
MHzNotes 2, 3
1 to 5 MHzNote 2 1.0 SI10/P22
SO10/P21
SCK10/P20
0
UART UART ch-0
(Async.)
4,800 to
76,800 bps
Notes 2, 4
5 MHzNote 5 4.91 or
5 MHzNote 2
1.0 RxD20/SI20/P25
TxD20/SO20/P24
8
Notes 1. Selection items for TYPE settings on the dedicated flash programmer (Flashpro III (part no. FL-PR3,
PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)).
2. The possible setting range differs depending on the voltage. For details, refer to CHAPTER 22
ELECTRICAL SPECIFICATIONS.
3. 2 or 4 MHz only for Flashpro III
4. Because signal wave slew also affects UART communication, in addition to the baud rate error,
thoroughly evaluate the slew and baud rate error.
5. Only for Flashpro IV. However, when using Flashpro III, be sure to select the clock of the resonator on
the board. UART cannot be used with the clock supplied by Flashpro III.
Figure 19-2. Communication Mode Selection Format
10 V
V
SS
V
DD
V
PP
V
DD
V
SS
RESET
12 n
V
PP
pulses
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Figure 19-3. Example of Connection with Dedicated Flash Programmer
(a) 3-wire serial I/O
Dedicated flash programmer
VPP1
VDD
RESET
SCK
SO
SI
CLK
Note 1
GND
V
PP
V
DD
RESET
SCK10
SI10
SO10
X1 (P03)
V
SS
PD78F9306, 78F9316
µ
(b) UART
Dedicated flash programmer
VPP1
VDD
RESET
SO
SI
CLK
Notes 1, 2
GND
VPP
VDD
RESET
RXD20
TXD20
X1 (P30)
VSS
PD78F9306, 78F9316
µ
Notes 1. When the system clock is supplied from the dedicated flash programmer to the
µ
PD78F9306, connect
the CLK pin with X1 pin and disconnect the on-board resonator. When using the clock of the on-board
resonator, do not connect the CLK pin.
When using the
µ
PD78F9316, be sure to connect the CLK pin with P03 pin and the system clock is
supplied from the dedicated flash programmer.
2. When using UART with Flashpro III, the clock of the resonator connected to the X1 pin must be used,
so do not connect to the CLK pin.
Caution The VDD pin, if already connected to the power supply, must be connected to the VDD pin of the
dedicated flash programmer. When using the power supply connected to the VDD pin, supply
voltage before starting programming.
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If Flashpro III/Flashpro IV is used as a dedicated flash programmer, the following signals are generated for the
µ
PD78F9306, 78F9316. For details, refer to the manual of Flashpro III/Flashpro IV.
Table 19-3. Pin Connection List
Signal Name I/O Pin Function Pin Name 3-Wire Serial I/O UART
VPP1 Output Write voltage VPP
VPP2 − − − × ×
VDD I/O VDD voltage generation/
voltage monitoring
VDD Note Note
GND − Ground VSS
X1 (
µ
PD78F9316)
CLK Output Clock output
P03 (
µ
PD78F9316)
RESET Output Reset signal RESET
SI Input Receive signal SO10/TxD20
SO Output Transmit signal SI10/RxD20
SCK Output Transfer clock SCK10 ×
HS Input Handshake signal − × ×
Note VDD voltage must be supplied before programming is started.
Remark : Pin must be connected.
: If the signal is supplied on the target board, pin does not need to be connected.
×: Pin does not need to be connected.
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19.1.3 On-board pin connections
When programming on the target system, provide a connector on the target system to connect to the dedicated
flash programmer.
There may be cases in which an on-board function that switches from the normal operation mode to flash memory
programming mode is required.
<VPP pin>
Input 0 V to the VPP pin in the normal operation mode. A write voltage of 10.0 V (TYP.) is supplied to the VPP
pin in the flash memory programming mode. Therefore, connect the VPP pin using method (1) or (2) below.
(1) Connect a pull-down resistor of RVPP = 10 kΩ to the VPP pin.
(2) Set the jumper on the board to switch the input of VPP pin to the programmer side or directly to GND.
The following shows an example of VPP pin connection.
Figure 19-4. VPP Pin Connection Example
PD78F9306,
PD78F9316
V
PP
µ
µ
Pull-down resistor (RV
PP
)
Connection pin of dedicated flash programmer
<Serial interface pins>
The following shows the pins used by each serial interface.
Serial Interface Pins Used
3-wire serial I/O SI10, SO10, SCK10
UART RxD20, TxD20
Note that signal conflict or malfunction of other devices may occur when an on-board serial interface pin that is
connected to another device is connected to the dedicated flash programmer.
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(1) Signal conflict
A signal conflict occurs if the dedicated flash programmer (output) is connected to a serial interface pin
(input) connected to another device (output). To prevent this signal conflict, isolate the connection with the
other device or put the other device in the output high impedance status.
Figure 19-5. Signal Conflict (Serial Interface Input Pin)
PD78F9306,
PD78F9316
Signal conflict
Output pin
In the flash memory programming mode, the signal
output by another device and the signal sent by the
dedicated flash programmer conflict. To prevent this,
isolate the signal on the device side.
Connection pin of dedicated flash
programmer
Other device
Input pin
µ
µ
(2) Malfunction of another device
When the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output)
connected to another device (input), a signal may be output to the device, causing a malfunction. To prevent
such malfunction, isolate the connection with other device or set so that the input signal to the device is
ignored.
Figure 19-6. Malfunction of Another Device
PD78F9306,
PD78F9316
Input pin
Input pin
Pin
Pin
Other device
Other device
Connection pin of dedicated flash
programmer
Connection pin of dedicated flash
programmer
If the signal output by the PD78F9306, 78F9316 affects another device in the
flash memory programming mode, isolate the signal on the device side.
If the signal output by the dedicated flash programmer affects another
device, isolate the signal on the device side.
PD78F9306,
PD78F9316
µ
µ
µ
µ
µ
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<RESET pin>
When the reset signal of the dedicated flash programmer is connected to the RESET pin connected to the reset
signal generator on the board, a signal conflict occurs. To prevent this signal conflict, isolate the connection with
the reset signal generator.
If a reset signal is input from the user system in the flash memory programming mode, a normal programming
operation will not be performed. Do not input signals other than reset signals from the dedicated flash programmer
during this period.
Figure 19-7. Signal Conflict (RESET Pin)
RESET
PD78F9306,
PD78F9316
Signal conflict
Output pin
Reset signal generator
In the flash memory programming mode, the signal output
by the reset signal generator and the signal output by the
dedicated flash programmer conflict, therefore, isolate the
signal on the reset signal generator side.
Connection pin of dedicated
flash programmer
µ
µ
<Port pins>
Shifting to the flash memory programming mode sets all the pins except those used for flash memory
programming communication to the status immediately after reset.
Therefore, if the external device does not acknowledge an initial status such as the output high impedance
status, connect the external device to VDD or VSS via a resistor.
<Oscillation pins>
• In the case of
µ
PD78F9306
When using an on-board clock, connection of X1, X2, XT1, and XT2 must conform to the methods in the
normal operation mode.
When using the clock output of the flash programmer, directly connect it to the X1 pin with the on-board main
oscillator disconnected, and leave the X2 pin open. For the subclock, connection conforms to that in the
normal operation mode.
• In the case of
µ
PD78F9316
Connect CL1, CL2, XT1, and XT2 as required in the normal operation mode, and connect the clock output of
the flash programmer to the P03 pin.
<Power supply>
To use the power output of the flash programmer, connect the VDD0 pins to VDD of the flash programmer, and
the VSS pins to GND of the flash programmer.
To use the on-board power supply, connection must conform to that in the normal operation mode. However,
because the voltage is monitored by the flash programmer, therefore, VDD of the flash programmer must be
connected.
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<Other pins>
Handle the other pins (S0 to S23, COM0 to COM3, VLC0 to VLC2, CAPH, CAPL) in the same way as in the
normal operation mode.
19.1.4 Connection when using flash memory writing adapter
The following shows an example of the recommended connection when using the flash memory writing adapter.
Figure 19-8. Example of Flash Memory Writing Adapter Connection When Using 3-Wire Serial I/O Mode
(
µ
PD78F9306)
GND
VDD
LVDD (VPP2)
SI SO SCK CLKOUT RESET VPP RESERVE/HS
WRITER INTERFACE
VDD (2.7 to 5.5 V)
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
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Figure 19-9. Example of Flash Memory Writing Adapter Connection When Using 3-Wire Serial I/O Mode
(
µ
PD78F9316)
GND
VDD
LVDD (VPP2)
SI SO SCK CLKOUT RESET VPP RESERVE/HS
WRITER INTERFACE
VDD (2.7 to 5.5 V)
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
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Figure 19-10. Example of Flash Memory Writing Adapter Connection When Using UART Mode
(
µ
PD78F9306)
GND
VDD
LVDD (VPP2)
SI SO SCK CLKOUT RESET VPP RESERVE/HS
WRITER INTERFACE
VDD (2.7 to 5.5 V)
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
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Figure 19-11. Example of Flash Memory Writing Adapter Connection When Using UART Mode
(
µ
PD78F9316)
GND
VDD
LVDD (VPP2)
SI SO SCK CLKOUT RESET VPP RESERVE/HS
WRITER INTERFACE
VDD (2.7 to 5.5 V)
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
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CHAPTER 20 MASK OPTIONS
Table 20-1. Selection of Mask Option for Pins
Pin Mask Option
P50 to P53 Whether a pull-up resistor is to be incorporated can be specified in 1-bit units.
For P50 to P53 (port 5), a mask option is used to specify whether a pull-up resistor is to be incorporated. The
mask option is selectable in 1-bit units.
Caution Flash memory versions do not have a mask option-based on-chip pull-up resistor function.
276 User’s Manual U14800EJ3V0UD
CHAPTER 21 INSTRUCTION SET
This chapter lists the instruction set of the
µ
PD789306 and
µ
PD789316 Subseries. For the details of the operation
and machine language (instruction code) of each instruction, refer to 78K/0S Series Instructions User’s Manual
(U11047E).
21.1 Operation
21.1.1 Operand identifiers and description methods
Operands are described in “Operand” column of each instruction in accordance with the description method of the
instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description
methods, select one of them. Alphabetic letters in capitals and symbols, #, !, $, and [ ] are key words and are
described as they are. Each symbol has the following meaning.
• #: Immediate data specification • $: Relative address specification
• !: Absolute address specification • [ ]: Indirect address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to
describe the #, !, $ and [ ] symbols.
For operand register identifiers, r and rp, either functional names (X, A, C, etc.) or absolute names (names in
parenthesis in the table below, R0, R1, R2, etc.) can be used for description.
Table 21-1. Operand Identifiers and Description Methods
Identifier Description Method
r
rp
sfr
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
Special-function register symbol
saddr
saddrp
FE20H to FF1FH Immediate data or labels
FE20H to FF1FH Immediate data or labels (even addresses only)
addr16
addr5
0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions)
0040H to 007FH Immediate data or labels (even addresses only)
word
byte
bit
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
Remark See Table 5-3 Special Function Register List for symbols of special function registers.
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21.1.2 Description of “Operation” column
A: A register; 8-bit accumulator
X: X register
B: B register
C: C register
D: D register
E: E register
H: H register
L: L register
AX: AX register pair; 16-bit accumulator
BC: BC register pair
DE: DE register pair
HL: HL register pair
PC: Program counter
SP: Stack pointer
PSW: Program status word
CY: Carry flag
AC: Auxiliary carry flag
Z: Zero flag
IE: Interrupt request enable flag
NMIS: Flag indicating non-maskable interrupt servicing in progress
( ): Memory contents indicated by address or register contents in parenthesis
XH, XL: Higher 8 bits and lower 8 bits of 16-bit register
∧: Logical product (AND)
∨: Logical sum (OR)
V: Exclusive logical sum (exclusive OR)
−: Inverted data
addr16: 16-bit immediate data or label
jdisp8: Signed 8-bit data (displacement value)
21.1.3 Description of “Flag” column
(Blank): Unchanged
0: Cleared to 0
1: Set to 1
x: Set/cleared according to the result
R: Previously saved value is restored
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21.2 Operation List
Mnemonic Operands Byte Clock Operation Flag
Z AC CY
MOV r, #byte 3 6
r ← byte
saddr, #byte 3 6
(saddr) ← byte
sfr, #byte 3 6
sfr ← byte
A, r Note 1 2 4 A ← r
r, A Note 1 2 4 r ← A
A, saddr 2 4
A ← (saddr)
saddr, A 2 4
(saddr) ← A
A, sfr 2 4
A ← sfr
sfr, A 2 4
sfr ← A
A, !addr16 3 8
A ← (addr16)
!addr16, A 3 8
(addr16) ← A
PSW, #byte 3 6
PSW ← byte x x x
A, PSW 2 4
A ← PSW
PSW, A 2 4
PSW ← A x x x
A, [DE] 1 6
A ← (DE)
[DE], A 1 6
(DE) ← A
A, [HL] 1 6
A ← (HL)
[HL], A 1 6
(HL) ← A
A, [HL+byte] 2 6
A ← (HL + byte)
[HL+byte], A 2 6
(HL + byte) ← A
XCH A, X 1 4
A ↔ X
A, r Note 2 2 6 A ↔ r
A, saddr 2 6
A ↔ (saddr)
A, sfr 2 6
A ↔ sfr
A, [DE] 1 8
A ↔ (DE)
A, [HL] 1 8
A ↔ (HL)
A, [HL+byte] 2 8
A ↔ (HL + byte)
Notes 1. Except r = A.
2. Except r = A, X.
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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Mnemonic Operands Byte Clock Operation Flag
Z AC CY
MOVW rp, #word 3 6
rp ← word
AX, saddrp 2 6
AX ← (saddrp)
saddrp, AX 2 8
(saddrp) ← AX
AX, rp
Note 1 4
AX ← rp
rp, AX
Note 1 4
rp ← AX
XCHW AX, rp Note 1 8
AX ↔ rp
ADD A, #byte 2 4
A, CY ← A + byte x x x
saddr, #byte 3 6
(saddr), CY ← (saddr) + byte x x x
A, r 2 4
A, CY ← A + r x x x
A, saddr 2 4
A, CY ← A + (saddr) x x x
A, !addr16 3 8
A, CY ← A + (addr16) x x x
A, [HL] 1 6
A, CY ← A + (HL) x x x
A, [HL+byte] 2 6
A, CY ← A + (HL + byte) x x x
ADDC A, #byte 2 4
A, CY ← A + byte + CY x x x
saddr, #byte 3 6
(saddr), CY ← (saddr) + byte + CY x x x
A, r 2 4
A, CY ← A + r + CY x x x
A, saddr 2 4
A, CY ← A + (saddr) + CY x x x
A, !addr16 3 8
A, CY ← A + (addr16) + CY x x x
A, [HL] 1 6
A, CY ← A + (HL) + CY x x x
A, [HL+byte] 2 6
A, CY ← A + (HL + byte) + CY x x x
SUB A, #byte 2 4
A, CY ← A − byte x x x
saddr, #byte 3 6
(saddr), CY ← (saddr) − byte x x x
A, r 2 4
A, CY ← A − r x x x
A, saddr 2 4
A, CY ← A − (saddr) x x x
A, !addr16 3 8
A, CY ← A − (addr16) x x x
A, [HL] 1 6
A, CY ← A − (HL) x x x
A, [HL+byte] 2 6
A, CY ← A − (HL + byte) x x x
Note Only when rp = BC, DE, or HL.
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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Mnemonic Operands Byte Clock Operation Flag
Z AC CY
SUBC A, #byte 2 4
A, CY ← A − byte − CY x x x
saddr, #byte 3 6
(saddr), CY ← (saddr) − byte − CY x x x
A, r 2 4
A, CY ← A − r − CY x x x
A, saddr 2 4
A, CY ← A − (saddr) − CY x x x
A, !addr16 3 8
A, CY ← A − (addr16) − CY x x x
A, [HL] 1 6
A, CY ← A − (HL) − CY x x x
A, [HL+byte] 2 6
A, CY ← A − (HL + byte) − CY x x x
AND A, #byte 2 4
A ← A ∧ byte x
saddr, #byte 3 6
(saddr) ← (saddr) ∧ byte x
A, r 2 4
A ← A ∧ r x
A, saddr 2 4
A ← A ∧ (saddr) x
A, !addr16 3 8
A ← A ∧ (addr16) x
A, [HL] 1 6
A ← A ∧ (HL) x
A, [HL+byte] 2 6
A ← A ∧ (HL + byte) x
OR A, #byte 2 4
A ← A ∨ byte x
saddr, #byte 3 6
(saddr) ← (saddr) ∨ byte x
A, r 2 4
A ← A ∨ r x
A, saddr 2 4
A ← A ∨ (saddr) x
A, !addr16 3 8
A ← A ∨ (addr16) x
A, [HL] 1 6
A ← A ∨ (HL) x
A, [HL+byte] 2 6
A ← A ∨ (HL + byte) x
XOR A, #byte 2 4
A ← A V byte x
saddr, #byte 3 6
(saddr) ← (saddr) V byte x
A, r 2 4
A ← A V r x
A, saddr 2 4
A ← A V (saddr) x
A, !addr16 3 8
A ← A V (addr16) x
A, [HL] 1 6
A ← A V (HL) x
A, [HL+byte] 2 6
A ← A V (HL + byte) x
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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Mnemonic Operands Byte Clock Operation Flag
Z AC CY
CMP A, #byte 2 4
A − byte x x x
saddr, #byte 3 6
(saddr) − byte x x x
A, r 2 4
A − r x x x
A, saddr 2 4
A − (saddr) x x x
A, !addr16 3 8
A − (addr16) x x x
A, [HL] 1 6
A − (HL) x x x
A, [HL+byte] 2 6
A − (HL + byte) x x x
ADDW AX, #word 3 6
AX, CY ← AX + word x x x
SUBW AX, #word 3 6
AX, CY ← AX − word x x x
CMPW AX, #word 3 6
AX − word x x x
INC r 2 4
r ← r + 1 x x
saddr 2 4
(saddr) ← (saddr) + 1 x x
DEC r 2 4
r ← r − 1 x x
saddr 2 4
(saddr) ← (saddr) − 1 x x
INCW rp 1 4
rp ← rp + 1
DECW rp 1 4
rp ← rp − 1
ROR A, 1 1 2
(CY, A7 ← A0, Am−1 ← Am) × 1 x
ROL A, 1 1 2
(CY, A0 ← A7, Am+1 ← Am) × 1 x
RORC A, 1 1 2
(CY ← A0, A7 ← CY, Am−1 ← Am) × 1 x
ROLC A, 1 1 2
(CY ← A7, A0 ← CY, Am+1 ← Am) × 1 x
SET1 saddr.bit 3 6
(saddr.bit) ← 1
sfr.bit 3 6
sfr.bit ← 1
A.bit 2 4
A.bit ← 1
PSW.bit 3 6
PSW.bit ← 1 x x x
[HL].bit 2 10
(HL).bit ← 1
CLR1 saddr.bit 3 6
(saddr.bit) ← 0
sfr.bit 3 6
sfr.bit ← 0
A.bit 2 4
A.bit ← 0
PSW.bit 3 6
PSW.bit ← 0 x x x
[HL].bit 2 10
(HL).bit ← 0
SET1 CY 1 2
CY ← 1 1
CLR1 CY 1 2
CY ← 0 0
NOT1 CY 1 2
CY ← CY x
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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Mnemonic Operands Byte Clock Operation Flag
Z AC CY
CALL !addr16 3 6
(SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L,
PC ← addr16, SP ← SP − 2
CALLT [addr5] 1 8
(SP − 1) ← (PC + 1)H, (SP − 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1),
PCL ← (00000000, addr5), SP ← SP − 2
RET 1 6
PCH ← (SP + 1), PCL ← (SP), SP ← SP + 2
RETI 1 8
PCH ← (SP + 1), PCL ← (SP),
PSW ← (SP + 2), SP ← SP + 3, NMIS ← 0
RRR
PUSH PSW 1 2
(SP − 1) ← PSW, SP ← SP − 1
rp 1 4
(SP − 1) ← rpH, (SP − 2) ← rpL, SP ← SP − 2
POP PSW 1 4
PSW ← (SP), SP ← SP + 1 RRR
rp 1 6
rpH ← (SP + 1), rpL ← (SP), SP ← SP + 2
MOVW SP, AX 2 8
SP ← AX
AX, SP 2 6
AX ← SP
BR !addr16 3 6
PC ← addr16
$addr16 2 6
PC ← PC + 2 + jdisp8
AX 1 6
PCH ← A, PCL ← X
BC $saddr16 2 6
PC ← PC + 2 + jdisp8 if CY = 1
BNC $saddr16 2 6
PC ← PC + 2 + jdisp8 if CY = 0
BZ $saddr16 2 6
PC ← PC + 2 + jdisp8 if Z = 1
BNZ $saddr16 2 6
PC ← PC + 2 + jdisp8 if Z = 0
BT saddr.bit, $addr16 4 10
PC ← PC + 4 + jdisp8 if (saddr.bit) = 1
sfr.bit, $addr16 4 10
PC ← PC + 4 + jdisp8 if sfr.bit = 1
A.bit, $addr16 3 8
PC ← PC + 3 + jdisp8 if A.bit = 1
PSW.bit, $addr16 4 10
PC ← PC + 4 + jdisp8 if PSW.bit = 1
BF saddr.bit, $addr16 4 10
PC ← PC + 4 + jdisp8 if (saddr.bit) = 0
sfr.bit, $addr16 4 10
PC ← PC + 4 + jdisp8 if sfr.bit = 0
A.bit, $addr16 3 8
PC ← PC + 3 + jdisp8 if A.bit = 0
PSW.bit, $addr16 4 10
PC ← PC + 4 + jdisp8 if PSW.bit = 0
DBNZ B, $addr16 2 6
B ← B − 1, then PC ← PC + 2 + jdisp8 if B ≠ 0
C, $addr16 2 6
C ← C − 1, then PC ← PC + 2 + jdisp8 if C ≠ 0
saddr, $addr16 3 8
(saddr) ← (saddr) − 1, then
PC ← PC + 3 + jdisp8 if (saddr) ≠ 0
NOP 1 2 No Operation
EI 3 6
IE ← 1 (Enable interrupt)
DI 3 6
IE ← 0 (Disable interrupt)
HALT 1 2 Set HALT mode
STOP 1 2 Set STOP mode
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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21.3 Instructions Listed by Addressing Type
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH,
POP, DBNZ
2nd Operand
1st Operand
#byte A r sfr saddr
!addr16 PSW [DE] [HL]
[HL+byte]
$addr1
6
1 None
A ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOVNote
XCHNote
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
ROR
ROL
RORC
ROLC
r MOV
MOV INC
DEC
B, C DBNZ
sfr MOV MOV
saddr MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV DBNZ INC
DEC
!addr16 MOV
PSW MOV MOV PUSH
POP
[DE] MOV
[HL] MOV
[HL+byte] MOV
Note Except r = A.
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(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand
1st Operand
#word AX rpNote saddrp SP None
AX ADDW
SUBW
CMPW
MOVW
XCHW
MOVW MOVW
rp MOVW MOVWNote INCW
DECW
PUSH
POP
saddrp MOVW
SP MOVW
Note Only when rp = BC, DE, or HL.
(3) Bit manipulation instructions
SET1, CLR1, NOT1, BT, BF
2nd Operand
1st Operand
$addr16 None
A.bit BT
BF
SET1
CLR1
sfr.bit BT
BF
SET1
CLR1
saddr.bit BT
BF
SET1
CLR1
PSW.bit BT
BF
SET1
CLR1
[HL].bit SET1
CLR1
CY SET1
CLR1
NOT1
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(4) Call instructions/branch instructions
CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ
2nd Operand
1st Operand
AX !addr16 [addr5] $addr16
Basic Instructions BR CALL
BR
CALLT BR
BC
BNC
BZ
BNZ
Compound Instructions DBNZ
(5) Other instructions
RET, RETI, NOP, EI, DI, HALT, STOP
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CHAPTER 22 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter Symbol Conditions Ratings Unit
VDD –0.3 to +6.5 V Power supply voltage
VPP
µ
PD78F9306, 78F9316 only Note 1 –0.3 to +10.5 V
VI1 P00 to P03, P10 to P13, P20 to P26, P30 to
P33, X1 [CL1], X2 [CL2], XT1, XT2, RESET
–0.3 to VDD + 0.3Note 2 V
N-ch open drain –0.3 to +13 V
Input voltage
VI2 P50 to P53
On-chip pull-up resistor –0.3 to VDD + 0.3Note 2 V
Output voltage VO –0.3 to VDD + 0.3Note 2 V
1 pin –10 mA Output current, high IOH
Total for all pins –30 mA
1 pin 30 mA Output current, low IOL
Total for all pins 160 mA
In normal operation –40 to +85 °C Operating ambient temperature TA
During flash memory programming 10 to 40 °C
Mask ROM version –65 to +150 °C Storage temperature Tstg
µ
PD78F9306, 78F9316 –40 to +125 °C
Notes 1. Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash
memory is written.
• When supply voltage rises
VPP must exceed VDD 10
µ
s or more after VDD has reached the lower-limit value (1.8 V) of the
operating voltage range (see a in the figure below).
• When supply voltage drops
VDD must be lowered 10
µ
s or more after VPP falls below the lower-limit value (1.8 V) of the operating
voltage range of VDD (see b in the figure below).
1.8 V
VDD
0 V
0 V
VPP
1.8 V
a b
2. 6.5 V or less
CHAPTER 22 ELECTRICAL SPECIFICATIONS
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Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product is
on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remarks 1. Pin names enclosed in brackets [ ] apply when using the
µ
PD789316 Subseries.
2. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of
port pins.
CHAPTER 22 ELECTRICAL SPECIFICATIONS
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Main System Clock Oscillator Characteristics
Ceramic/crystal oscillation (
µ
PD789306 Subseries) (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit
Oscillation frequency (fX)Note 1 1.0 5.0 MHz Ceramic
resonator
X1X2V
SS
C1C2
Oscillation stabilization
timeNote 2
After VDD reaches
oscillation voltage
range MIN.
4 ms
Oscillation frequencyNote 1 1.0 5.0 MHz
VDD = 4.5 to 5.5 V 10 ms
Crystal
resonator
X1X2V
SS
C1C2
Oscillation stabilization
timeNote 2 VDD = 1.8 to 5.5 V 30 ms
X1 input frequency (fX)Note 1 1.0 5.0 MHz
X2 X1
X1 input high-/low-level width
(tXH, tXL)
85 500 ns
X1 input frequency (fX)Note 1 VDD = 2.7 to 5.5 V 1.0 5.0 MHz
External
clock
X2
OPEN
X1
X1 input high-/low-level width
(tXH, tXL)
VDD = 2.7 to 5.5 V 85 500 ns
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release. Use a resonator whose
oscillation stabilizes within the oscillation stabilization wait time.
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the device is operating on the subsystem
clock, wait until the oscillation stabilization time has been secured by the program before
switching back to the main system clock.
Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
CHAPTER 22 ELECTRICAL SPECIFICATIONS
User’s Manual U14800EJ3V0UD 289
RC oscillation (
µ
PD789316 Subseries) (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit
Oscillation frequency (fCC)Note 1 2.0 4.0 MHz
VDD = 2.7 to 5.5 V 32
µ
s
RC
resonator
CL2CL1
Oscillation stabilization
timeNote 2 VDD = 1.8 to 5.5 V 128
µ
s
CL1 input frequency (fCC)Note 1 1.0 4.0 MHz
CL1 CL2
CL1 input high-/low-level
width (tXH, tXL)
100 500 ns
CL1 input frequency (fCC)Note 1 VDD = 2.7 to 5.5 V 1.0 4.0 MHz
External
clock
CL1
OPEN
CL2
CL1 input high-/low-level
width (tXH, tXL)
VDD = 2.7 to 5.5 V 100 500 ns
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
The error of capacitor (C) and resistor (R) is not included.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figure to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the device is operating on the subsystem
clock, wait until the oscillation stabilization time has been secured by the program before
switching back to the main system clock.
CHAPTER 22 ELECTRICAL SPECIFICATIONS
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RC Oscillation Frequency Characteristics (TA = –40 to +85°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
fCC1 VDD = 2.7 to 5.5 V 1.5 2.0 2.5 MHz
fCC2 VDD = 1.8 to 3.6 V 0.5 2.0 2.5 MHz
fCC3
R = 11.0 kΩ,
C = 22 pF
Target: 2 MHz VDD = 1.8 to 5.5 V 0.5 2.0 2.5 MHz
fCC4 VDD = 2.7 to 5.5 V 2.5 3.0 3.5 MHz
fCC5 VDD = 1.8 to 3.6 V 0.75 3.0 3.5 MHz
fCC6
R = 6.8 kΩ,
C = 22 pF
Target: 3 MHz VDD = 1.8 to 5.5 V 0.75 3.0 3.5 MHz
fCC7 VDD = 2.7 to 5.5 V 3.5 4.0 4.7 MHz
fCC8 VDD = 1.8 to 3.6 V 1.0 4.0 4.7 MHz
Oscillation
frequency
fCC9
R = 4.7 kΩ,
C = 22 pF
Target: 4 MHz VDD = 1.8 to 5.5 V 1.0 4.0 4.7 MHz
Remarks 1. Set RC to one of the above nine values so that the typical value of the oscillation frequency is within
2.0 to 4.0 MHz.
2. The resistor (R) and capacitor (C) error is not included.
Subsystem Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit
Oscillation frequency
(fXT)Note 1
32 32.768 35 kHz
VDD = 4.5 to 5.5 V 1.2 2
Crystal
resonator
XT2XT1VSS
C4
C3
R
Oscillation stabilization
timeNote 2 VDD = 1.8 to 5.5 V 10
s
XT1 input frequency
(fXT)Note 1
32 35 kHz
External
clock
XT1 XT2
XT1 input high-/low-level
width (tXTH, tXTL)
14.3 15.6
µ
s
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN.
Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figure to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current
consumption, and is more prone to malfunction due to noise than the main system clock
oscillator. Particular care is therefore required with the wiring method when the
subsystem clock is used.
Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
CHAPTER 22 ELECTRICAL SPECIFICATIONS
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DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (1/6)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
1 pin 10 mA Output current, low IOL
All pins 80 mA
1 pin –1 mA Output current, high IOH
All pins –15 mA
VDD = 2.7 to 5.5 V 0.7VDD VDD V VIH1 P10 to P13
VDD = 1.8 to 5.5 V 0.9VDD VDD V
VDD = 2.7 to 5.5 V 0.7VDD 12 V N-ch open drain
VDD = 1.8 to 5.5 V 0.9VDD 12 V
VDD = 2.7 to 5.5 V 0.7VDD VDD V
VIH2 P50 to
P53
On-chip pull-up
resistor VDD = 1.8 to 5.5 V 0.9VDD VDD V
VDD = 2.7 to 5.5 V 0.8VDD VDD V VIH3 RESET, P00 to P03,
P20 to P26, P30 to P33 VDD = 1.8 to 5.5 V 0.9VDD VDD V
VDD = 4.5 to 5.5 V VDD – 0.5 VDD V
Input voltage, high
VIH4 X1 [CL1], X2 [CL2], XT1,
XT2 VDD = 1.8 to 5.5 V VDD – 0.1 VDD V
VDD = 2.7 to 5.5 V 0 0.3VDD V VIL1 P10 to P13
VDD = 1.8 to 5.5 V 0 0.1VDD V
VDD = 2.7 to 5.5 V 0 0.3VDD V VIL2 P50 to P53
VDD = 1.8 to 5.5 V 0 0.1VDD V
VDD = 2.7 to 5.5 V 0 0.2VDD V VIL3 RESET, P00 to P03,
P20 to P26, P30 to P33 VDD = 1.8 to 5.5 V 0 0.1VDD V
VDD = 4.5 to 5.5 V 0 0.4 V
Input voltage, low
VIL4 X1 [CL1], X2 [CL2], XT1,
XT2 VDD = 1.8 to 5.5 V 0 0.1 V
IOH = –1 mA VDD = 4.5 to 5.5 V VDD – 1.0 V Output voltage, high VOH
IOH = –100
µ
A VDD = 1.8 to 5.5 V VDD – 0.5 V
4.5 ≤ VDD ≤ 5.5 V,
IOL = 10 mA
1.0 V
VOL1 P00 to P03, P10 to P13,
P20 to P26, P30 to P33
1.8 ≤ VDD < 4.5 V,
IOL = 400
µ
A
0.5 V
4.5 ≤ VDD < 5.5 V,
IOL = 10 mA
1.0 V
Output voltage, low
VOL2 P50 to P53
1.8 ≤ VDD < 4.5 V,
IOL = 1.6 mA
0.4 V
Remarks 1. Pin names enclosed in brackets [ ] apply when using the
µ
PD789316 Subseries.
2. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of
port pins.
CHAPTER 22 ELECTRICAL SPECIFICATIONS
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DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (2/6)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
ILIH1 P00 to P03, P10 to
P13, P20 to P26, P30
to P33, RESET
3
µ
A
ILIH2
VI = VDD
X1 [CL1], X2 [CL2],
XT1, XT2
20
µ
A
Input leakage current,
high
ILIH3 VI = 12 V P50 to P53
(N-ch open drain)
20
µ
A
ILIL1 P00 to P03, P10 to
P13, P20 to P26, P30
to P33, RESET
–3
µ
A
ILIL2 X1 [CL1], X2 [CL2],
XT1, XT2
–20
µ
A
Input leakage current,
low
ILIL3
VI = 0 V
P50 to P53
(N-ch open drain)
–3Note
µ
A
Output leakage current,
high
ILOH VO = VDD 3
µ
A
Output leakage current,
low
ILOL VO = 0 V –3
µ
A
Software pull-up
resistor
R1 VI = 0 V P00 to P03, P10 to
P13, P20 to P26,
P30 to P33
50 100 200 kΩ
Mask option pullup
resistorNote 2
R2 VI = 0 V P50 to P53 10 30 60 kΩ
Notes 1. If P50 to P53 have been set to input mode when a read instruction is executed to read from P50 to P53,
a low-level input leakage current of up to –30
µ
A flows during only one cycle. At all other times, the
maximum leakage current is –3
µ
A.
2. Mask ROM version only
Remarks 1. Pin names enclosed in brackets [ ] apply when using the
µ
PD789316 Subseries.
2. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of
port pins.
CHAPTER 22 ELECTRICAL SPECIFICATIONS
User’s Manual U14800EJ3V0UD 293
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (3/6)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 5.0 V ±10%Note 2 1.8 2.9 mA
VDD = 3.0 V ±10%Note 3 0.36 0.9 mA
IDD1 5.0 MHz crystal oscillation
operation mode
(C1 = C2 = 22 pF)
VDD = 2.0 V ±10%Note 3 0.16 0.45 mA
VDD = 5.0 V ±10%Note 2 0.96 1.92 mA
VDD = 3.0 V ±10%Note 3 0.26 0.76 mA
IDD2 5.0 MHz crystal oscillation
HALT modeNote 4
(C1 = C2 = 22 pF)
VDD = 2.0 V ±10%Note 3 0.1 0.34 mA
VDD = 5.0 V ±10% 30 58
µ
A
VDD = 3.0 V ±10% 9 26
µ
A
IDD3 32.768 kHz crystal
oscillation operation
modeNote 5
(C3 = C4 = 22 pF,
R1 = 220 kΩ)
VDD = 2.0 V ±10% 4 12
µ
A
VDD = 5.0 V ±10% 25 48
µ
A
VDD = 3.0 V ±10% 7 20
µ
A
LCD not
operatingNote 4
VDD = 2.0 V ±10% 4 10
µ
A
VDD = 5.0 V ±10% 28 57
µ
A
VDD = 3.0 V ±10% 9.6 27.8
µ
A
IDD4 32.768 kHz
crystal
oscillation
HALT
modeNote 5
(C3 = C4 =
22 pF, R1 =
220 kΩ)
LCD
operatingNote 7
VDD = 2.0 V ±10% 6 16
µ
A
VDD = 5.0 V ±10% 0.1 10
µ
A
VDD = 3.0 V ±10% 0.05 5.0
µ
A
Power supply
currentNote 1
(
µ
PD789304,
789306)
IDD5 STOP modeNote 6
VDD = 2.0 V ±10% 0.05 3.0
µ
A
Notes 1. The port current (including the current that flows to the on-chip pull-up resistors) is not included.
2. High-speed mode operation (when processor clock control register (PCC) is cleared to 00H)
3. Low-speed mode operation (when PCC is set to 02H)
4. When the LCD is not operating and the booster circuit is operating (LCDON0 = 0, VAON0 = 1, LIPS0 =
1).
5. When the main system clock is stopped
6. When the LCD is not operating (LCDON0 = 0, VAON0 = 0, LIPS0 = 0)
7. Then the LCD is operating (LCDON0 = 1, VAON0 = 1, LIPS0 = 1)
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 22 ELECTRICAL SPECIFICATIONS
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DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (4/6)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 5.0 V ±10%Note 2 4.5 9 mA
VDD = 3.0 V ±10%Note 3 1 2 mA
IDD1 5.0 MHz crystal oscillation
operation mode
(C1 = C2 = 22 pF)
VDD = 2.0 V ±10%Note 3 0.65 1.5 mA
VDD = 5.0 V ±10%Note 2 1.4 2 mA
VDD = 3.0 V ±10%Note 3 0.4 0.8 mA
IDD2 5.0 MHz crystal oscillation
HALT modeNote 4
(C1 = C2 = 22 pF)
VDD = 2.0 V ±10%Note 3 0.19 0.42 mA
VDD = 5.0 V ±10% 100 230
µ
A
VDD = 3.0 V ±10% 70 160
µ
A
IDD3 32.768 kHz crystal
oscillation operation
modeNote 5
(C3 = C4 = 22 pF,
R1 = 220 kΩ)
VDD = 2.0 V ±10% 58 120
µ
A
VDD = 5.0 V ±10% 25 65
µ
A
VDD = 3.0 V ±10% 7 29
µ
A
LCD not
operatingNote 4
VDD = 2.0 V ±10% 4 20
µ
A
VDD = 5.0 V ±10% 28 70
µ
A
VDD = 3.0 V ±10% 9.6 34
µ
A
IDD4 32.768 kHz
crystal
oscillation
HALT
modeNote 5
(C3 = C4 =
22 pF, R1 =
220 kΩ)
LCD
operatingNote 7
VDD = 2.0 V ±10% 6 25
µ
A
VDD = 5.0 V ±10% 0.1 17
µ
A
VDD = 3.0 V ±10% 0.05 5.5
µ
A
Power supply
currentNote 1
(
µ
PD78F9306)
IDD5 STOP modeNote 6
VDD = 2.0 V ±10% 0.05 3.5
µ
A
Notes 1. The port current (including the current that flows to the on-chip pull-up resistors) is not included.
2. High-speed mode operation (when processor clock control register (PCC) is cleared to 00H)
3. Low-speed mode operation (when PCC is set to 02H)
4. When the LCD is not operating and the booster circuit is operating (LCDON0 = 0, VAON0 = 1, LIPS0 =
1).
5. When the main system clock is stopped
6. When the LCD is not operating (LCDON0 = 0, VAON0 = 0, LIPS0 = 0)
7. Then the LCD is operating (LCDON0 = 1, VAON0 = 1, LIPS0 = 1)
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 22 ELECTRICAL SPECIFICATIONS
User’s Manual U14800EJ3V0UD 295
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (5/6)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 5.0 V ±10%Note 2 1.65 3.0 mA
VDD = 3.0 V ±10%Note 3 0.65 1.44 mA
IDD1 4.0 MHz RC oscillation
operation mode
(R = 4.7 kΩ, C = 22 pF) VDD = 2.0 V ±10%Note 3 0.38 1.05 mA
VDD = 5.0 V ±10%Note 2 1.1 2.29 mA
VDD = 3.0 V ±10%Note 3 0.6 1.28 mA
IDD2 4.0 MHz RC oscillation
HALT modeNote 4
(R = 4.7 kΩ, C = 22 pF) VDD = 2.0 V ±10%Note 3 0.35 0.82 mA
VDD = 5.0 V ±10% 30 58
µ
A
VDD = 3.0 V ±10% 9 26
µ
A
IDD3 32.768 kHz crystal
oscillation operation
modeNote 5
(C3 = C4 = 22 pF, R1 = 220
kΩ)
VDD = 2.0 V ±10% 4 12
µ
A
VDD = 5.0 V ±10% 25 48
µ
A
VDD = 3.0 V ±10% 7 20
µ
A
LCD not
operatingNote 4
VDD = 2.0 V ±10% 4 10
µ
A
VDD = 5.0 V ±10% 28 57
µ
A
VDD = 3.0 V ±10% 9.6 27.8
µ
A
IDD4 32.768 kHz
crystal
oscillation
HALT
modeNote 5
(C3 = C4 =
22 pF, R1 =
220 kΩ)
LCD
operatingNote 7
VDD = 2.0 V ±10% 6 16
µ
A
VDD = 5.0 V ±10% 0.1 10
µ
A
VDD = 3.0 V ±10% 0.05 5.0
µ
A
Power supply
currentNote 1
(
µ
PD789314,
789316)
IDD5 STOP modeNote 6
VDD = 2.0 V ±10% 0.05 3.0
µ
A
Notes 1. The port current (including the current that flows to the on-chip pull-up resistors) is not included.
2. High-speed mode operation (when processor clock control register (PCC) is cleared to 00H)
3. Low-speed mode operation (when PCC is set to 02H)
4. When the LCD is not operating and the booster circuit is operating (LCDON0 = 0, VAON0 = 1, LIPS0 =
1).
5. When the main system clock is stopped
6. When the LCD is not operating (LCDON0 = 0, VAON0 = 0, LIPS0 = 0)
7. Then the LCD is operating (LCDON0 = 1, VAON0 = 1, LIPS0 = 1)
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 22 ELECTRICAL SPECIFICATIONS
User’s Manual U14800EJ3V0UD
296
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (6/6)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 5.0 V ±10%Note 2 6 9 mA
VDD = 3.0 V ±10%Note 3 2.0 2.5 mA
IDD1 4.0 MHz RC oscillation
operation mode
(R = 4.7 kΩ, C = 22 pF) VDD = 2.0 V ±10%Note 3 1.2 1.6 mA
VDD = 5.0 V ±10%Note 2 2.5 3.5 mA
VDD = 3.0 V ±10%Note 3 1.5 2 mA
IDD2 4.0 MHz RC oscillation
HALT modeNote 4
(R = 4.7 kΩ, C = 22 pF) VDD = 2.0 V ±10%Note 3 0.8 1.5 mA
VDD = 5.0 V ±10% 100 230
µ
A
VDD = 3.0 V ±10% 70 160
µ
A
IDD3 32.768 kHz crystal
oscillation operation
modeNote 5
(C3 = C4 = 22 pF, R1 = 220
kΩ)
VDD = 2.0 V ±10% 58 120
µ
A
VDD = 5.0 V ±10% 25 65
µ
A
VDD = 3.0 V ±10% 7 29
µ
A
LCD not
operatingNote 4
VDD = 2.0 V ±10% 4 20
µ
A
VDD = 5.0 V ±10% 28 70
µ
A
VDD = 3.0 V ±10% 9.6 34
µ
A
IDD4 32.768 kHz
crystal
oscillation
HALT
modeNote 5
(C3 = C4 =
22 pF, R1 =
220 kΩ)
LCD
operatingNote 7
VDD = 2.0 V ±10% 6 25
µ
A
VDD = 5.0 V ±10% 0.1 17
µ
A
VDD = 3.0 V ±10% 0.05 5.5
µ
A
Power supply
currentNote 1
(
µ
PD78F9316)
IDD5 STOP modeNote 6
VDD = 2.0 V ±10% 0.05 3.5
µ
A
Notes 1. The port current (including the current that flows to the on-chip pull-up resistors) is not included.
2. High-speed mode operation (when processor clock control register (PCC) is cleared to 00H)
3. Low-speed mode operation (when PCC is set to 02H)
4. When the LCD is not operating and the booster circuit is operating (LCDON0 = 0, VAON0 = 1, LIPS0 =
1).
5. When the main system clock is stopped
6. When the LCD is not operating (LCDON0 = 0, VAON0 = 0, LIPS0 = 0)
7. Then the LCD is operating (LCDON0 = 1, VAON0 = 1, LIPS0 = 1)
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
CHAPTER 22 ELECTRICAL SPECIFICATIONS
User’s Manual U14800EJ3V0UD 297
AC Characteristics
(1) Basic operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 0.4 8.0
µ
s
Operating with main
system clock VDD = 1.8 to 5.5 V 1.6 8.0
µ
s
Cycle time (minimum
instruction execution
time)
TCY
Operating with subsystem clock 114 122 125
µ
s
CPT20 input high-/low-
level width
tCPTH,
tCPTL
10
µ
s
VDD = 2.7 to 5.5 V 0 4 MHz TMI40 input frequency fTI
VDD = 1.8 to 5.5 V 0 275 kHz
VDD = 2.7 to 5.5 V 0.1
µ
s
TMI40 input high-/low-
level width
tTIH,
tTIL VDD = 1.8 to 5.5 V 1.8
µ
s
Interrupt input high-
/low-level width
tINTH,
tINTL
INTP0 to INTP3 10
µ
s
Key return input low-
level width
tKRL KR0 to KR3 10
µ
s
RESET low-level width tRSL 10
µ
s
TCY vs VDD (main system clock)
Power supply voltage V
DD
(V)
123456
0.1
0.4
0.5
1.0
2.0
10
20
60
Cycle time T
CY
[ s]
Guaranteed
operation range
µ
CHAPTER 22 ELECTRICAL SPECIFICATIONS
User’s Manual U14800EJ3V0UD
298
(2) Serial interface 10, 20 (SIO10, SIO20) (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(a) 3-wire serial I/O mode (internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 800 ns SCKn0 cycle time tKCY1
VDD = 1.8 to 5.5 V 3200 ns
VDD = 2.7 to 5.5 V tKCY1/2–50 ns SCKn0 high-/low-level
width
tKH1,
tKL1 VDD = 1.8 to 5.5 V tKCY1/2–150 ns
VDD = 2.7 to 5.5 V 150 ns SIn0 setup time
(to SCKn0↑)
tSIK1
VDD = 1.8 to 5.5 V 500 ns
VDD = 2.7 to 5.5 V 400 ns SIn0 hold time
(from SCKn0↑)
tKSI1
VDD = 1.8 to 5.5 V 600 ns
VDD = 2.7 to 5.5 V 0 250 ns Delay time from
SCKn0↓ to SOn0
output
tKSO1 R = 1 kΩ, C = 100 pFNote
VDD = 1.8 to 5.5 V 0 1000 ns
Note R and C are the load resistance and load capacitance of the SOn0 output lines.
Remark n = 1, 2
(b) 3-wire serial I/O mode (external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 800 ns SCKn0 cycle time tKCY2
VDD = 1.8 to 5.5 V 3200 ns
VDD = 2.7 to 5.5 V 400 ns SCKn0 high-/low-level
width
tKH2,
tKL2 VDD = 1.8 to 5.5 V 1600 ns
VDD = 2.7 to 5.5 V 100 ns SIn0 setup time
(to SCKn0↑)
tSIK2
VDD = 1.8 to 5.5 V 150 ns
VDD = 2.7 to 5.5 V 400 ns SIn0 hold time
(from SCKn0↑)
tKSI2
VDD = 1.8 to 5.5 V 600 ns
VDD = 2.7 to 5.5 V 0 300 ns Delay time from
SCKn0↓ to SOn0
output
tKSO2 R = 1 kΩ, C = 100 pFNote
VDD = 1.8 to 5.5 V 0 1000 ns
Note R and C are the load resistance and load capacitance of the SOn0 output lines.
Remark n = 1, 2
CHAPTER 22 ELECTRICAL SPECIFICATIONS
User’s Manual U14800EJ3V0UD 299
(c) UART mode (SIO20 only) (dedicated baud rate generator output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 78125 bps Transfer rate
VDD = 1.8 to 5.5 V 19531 bps
(d) UART mode (SIO20 only) (external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 800 ns ASCK20 cycle time tKCY3
VDD = 1.8 to 5.5 V 3200 ns
VDD = 2.7 to 5.5 V 400 ns ASCK20 high-/low-
level width
tKH3,
tKL3 VDD = 1.8 to 5.5 V 1600 ns
VDD = 2.7 to 5.5 V 39063 bps Transfer rate
VDD = 1.8 to 5.5 V 9766 bps
ASCK20 rise/fall time tR,
tF
1
µ
s
CHAPTER 22 ELECTRICAL SPECIFICATIONS
User’s Manual U14800EJ3V0UD
300
AC Timing Test Points (excluding X1 (CL1) and XT1 inputs)
0.8V
DD
0.2V
DD
Test points 0.8V
DD
0.2V
DD
Clock Timing
1/f
CLK
t
XL
t
XH
X1 (CL1) input V
IH4
(MIN.)
V
IL4
(MAX.)
1/fXT
tXTL tXTH
XT1 input VIH4 (MIN.)
VIL4 (MAX.)
Remark fCLK: fX or fCC
Capture Input Timing
CPT20
t
CPTL
t
CPTH
TMI Timing
1/fTI
tTIL tTIH
TMI40 input
Interrupt Input Timing
INTP0 to INTP3
t
INTL
t
INTH
CHAPTER 22 ELECTRICAL SPECIFICATIONS
User’s Manual U14800EJ3V0UD 301
Key Return Input Timing
KR00 to KR03
t
KRL
RESET Input Timing
RESET
t
RSL
Serial Transfer Timing
3-wire serial I/O mode:
t
KCYm
t
KLm
t
KHm
SCK10, SCK20
t
SIKm
t
KSIm
t
KSOm
Input data
Output data
SI10, SI20
SO10, SO20
Remark m = 1, 2
UART mode (external clock input):
t
KCY3
t
KL3
t
KH3
ASCK20
t
R
t
F
CHAPTER 22 ELECTRICAL SPECIFICATIONS
User’s Manual U14800EJ3V0UD
302
LCD Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
GAIN = 1 0.84 1.0 1.165 V LCD output voltage
variation range
VLCD2 C1 to C4Note 1
= 0.47
µ
F GAIN = 0 1.26 1.5 1.74 V
Doubler output VLCD1 C1 to C4Note 1 = 0.47
µ
F 2 VLCD2– 0.1 2.0 VLCD2 2.0 VLCD2 V
Tripler output VLCD0 C1 to C4Note 1 = 0.47
µ
F 3 VLCD2– 0.15 3.0 VLCD2 3.0 VLCD2 V
GAIN = 0 1.8 ≤ VDD ≤ 5.5 V 0.5 s
5.0 ≤ VDD ≤ 5.5 V 2.0 s
4.5 ≤ VDD < 5.0 V 1.0 s
Voltage boost wait timeNote 2 tVAWAIT
GAIN = 1
1.8 ≤ VDD < 4.5 V 0.5 s
LCD output voltage
differentialNote 3 (common)
VODC IO = ±5
µ
A 0
±0.2 V
LCD output voltage
differentialNote 3 (segment)
VODS IO = ±1
µ
A 0
±0.2 V
Notes 1. This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: Capacitor connected between CAPH and CAPL
C2: Capacitor connected between VLC0 and VSS
C3: Capacitor connected between VLC1 and VSS
C4: Capacitor connected between VLC2 and VSS
2. This is the wait time from when voltage boost is started (VAON0 = 1) until display is enabled (LCDON0
= 1).
3. The voltage differential is the difference between the segment and common signal output’s actual and
ideal output voltages.
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention power supply voltage VDDDR 1.8 5.5 V
Release signal set time tSREL 0
µ
s
Oscillation Stabilization Wait Time (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Release by RESET 215/fX s
Oscillation stabilization wait
timeNote 1 (ceramic/crystal
oscillation)
tWAIT
Release by interrupt Note 2 s
Release by RESET 27/fCC s
Oscillation stabilization wait
time (RC oscillation)
tWAIT
Release by interrupt 27/fCC s
Notes 1. Use a resonator whose oscillation stabilizes within the oscillation stabilization wait time.
2. Selection of 212/fX, 215/fX, or 217/fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register (OSTS).
Remarks 1. f
X: Main system clock oscillation frequency (ceramic/crystal oscillation)
2. f
CC: Main system clock oscillation frequency (RC oscillation)
CHAPTER 22 ELECTRICAL SPECIFICATIONS
User’s Manual U14800EJ3V0UD 303
Data Retention Timing (STOP Mode Release by RESET)
V
DD
Data retention mode
STOP mode
HALT mode
Internal reset operation
Operation mode
t
SREL
t
WAIT
STOP instruction execution
V
DDDR
RESET
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
VDD
Data retention mode
STOP mode
HALT mode
Operation mode
tSREL
tWAIT
STOP instruction execution
VDDDR
Standby release signal
(interrupt request)
CHAPTER 22 ELECTRICAL SPECIFICATIONS
User’s Manual U14800EJ3V0UD
304
Flash Memory Write/Erase Characteristics (TA = 10 to 40°C, VDD = 1.8 to 5.5 V) (
µ
PD78F9306, 78F9316)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 1.0 5 MHz Operating frequency fX, fCC
VDD = 1.8 to 5.5 V 1.0 1.25 MHz
Ceramic oscillation
During fX = 5.0 MHz
operation
7 mA
Write currentNote 1
(VDD pin)
IDDW When VPP supply
voltage = VPP1
RC oscillation
During fCC = 4.0 MHz
operationNote 2
9 mA
Write currentNote 1
(VPP pin)
IPPW When VPP supply voltage = VPP1 12 mA
Ceramic oscillation
During fX = 5.0 MHz
operation
7 mA
Erase currentNote 1
(VDD pin)
IDDE When VPP supply
voltage = VPP1
RC oscillation
During fCC = 4.0 MHz
operationNote 2
9 mA
Erase currentNote 1
(VPP pin)
IPPE When VPP supply voltage = VPP1
100 mA
Unit erase time ter 0.5 1 1 s
Total erase time tera 20 s
Write count Erase/write are regarded as 1 cycle 20 Times
VPP0 In normal operation 0 0.2VDD V VPP supply voltage
VPP1 During flash memory programming 9.7 10.0 10.3 V
Notes 1. The port current (including the current that flows to the on-chip pull-up resistors) is not included.
2. When an external clock is input
User’s Manual U14800EJ3V0UD 305
CHAPTER 23 CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER
(REFERENCE VALUES)
(1) Characteristics curves of voltage boost stabilization time
The following shows the characteristics curves of the time from the start of voltage boost (VAON0 = 1) and
the changes in the LCD output voltage (when GAIN is set as 1 (using the 3 V display panel)).
LCD Output Voltage/Voltage Boost Time
VDD = 4.5 V
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
VDD = 5 V VDD = 5.5 V
0 500 1000 1500 2000
Voltage boost time [ms]
LCD output voltage [V]
2500 3000 3500 4000
VLCD0
VLCD1
VLCD2
CHAPTER 23 RECOMMENDED SOLDERING CONDITIONS
User’s Manual U14800EJ3V0UD
306
(2) Temperature characteristics of LCD output voltage
The following shows the temperature characteristics curves of LCD output voltage.
LCD Output Voltage/Temperature (When GAIN = 1)
LCD Output Voltage/Temperature (When GAIN = 0)
V
LCD2
−40
5
4
3
2
1
0−30 −20 −10 0 10 20
Temperature [˚C]
LCD output voltage [V]
30 40 50 60 70 80
V
LCD1
V
LCD0
V
LCD2
−40
5
4
3
2
1
0−30 −20 −10 0 10 20
Temperature [˚C]
LCD output voltage [V]
30 40 50 60 70 80
V
LCD1
V
LCD0
User’s Manual U14800EJ3V0UD
307
CHAPTER 24 PACKAGE DRAWINGS
64-PIN PLASTIC LQFP (14x14)
NOTE
Each lead centerline is located within 0.20 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
D
G
17.2±0.2
14.0±0.2
0.8 (T.P.)
1.0
J
17.2±0.2
K
C 14.0±0.2
I 0.20
1.6±0.2
L0.8
F 1.0
N
P
Q
0.10
1.4±0.1
0.127±0.075
U 0.886±0.15
R
S
3°
1.7 MAX.
T 0.25
P64GC-80-8BS
H 0.37+0.08
−0.07
M 0.17+0.03
−0.06
SN
J
T
detail of lead end
C D
A
B
K
M
I
S
P
RL
U
Q
G
F
M
H
+4°
−3°
1
64
49
17
32
16
48 33
S
CHAPTER 24 PACKAGE DRAWINGS
User’s Manual U14800EJ3V0UD
308
48
49 32
64
117
16
33
64-PIN PLASTIC QFP (14x14)
NOTE
Each lead centerline is located within 0.15 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
D
G
17.6±0.4
14.0±0.2
0.8 (T.P.)
1.0
J
17.6±0.4
K
P64GC-80-AB8-5
C 14.0±0.2
I 0.15
1.8±0.2
L0.8±0.2
F 1.0
N
P
Q
0.10
2.55±0.1
0.1±0.1
R
S
5°±5°
2.85 MAX.
H 0.37+0.08
−0.07
M 0.17+0.08
−0.07
S
SN
J
detail of lead end
C D
A
B
R
K
M
L
P
I
S
Q
G
F
M
H
CHAPTER 24 PACKAGE DRAWINGS
User’s Manual U14800EJ3V0UD
309
48
32
33
64
1
17
16
49
S
S
64-PIN PLASTIC TQFP (12x12)
ITEM MILLIMETERS
G 1.125
A 14.0±0.2
C 12.0±0.2
D
F 1.125
14.0±0.2
B 12.0±0.2
N 0.10
P
Q 0.1±0.05
1.0
S
R3°+4°
−3°
R
H
K
J
Q
G
I
S
P
detail of lead end
NOTE
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
M
H0.32+0.06
−0.10
I 0.13
J
K 1.0±0.2
0.65 (T.P.)
L 0.5
M0.17+0.03
−0.07
P64GK-65-9ET-3
T
U 0.6±0.15
0.25
F
M
A
B
CD
N
T
L
U
1.1±0.1
310 User’s Manual U14800EJ3V0UD
CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS
The
µ
PD789306 and
µ
PD789316 Subseries should be soldered and mounted under the following recommended
conditions.
For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales
representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Table 25-1. Surface Mounting Type Soldering Conditions (1/3)
µ
PD789304GC-×××-AB8: 64-pin plastic QFP (14 × 14)
µ
PD789306GC-×××-AB8: 64-pin plastic QFP (14 × 14)
µ
PD789314GC-×××-AB8: 64-pin plastic QFP (14 × 14)
µ
PD789316GC-×××-AB8: 64-pin plastic QFP (14 × 14)
µ
PD78F9306GC-AB8: 64-pin plastic QFP (14 × 14)
µ
PD78F9316GC-AB8: 64-pin plastic QFP (14 × 14)
Soldering Method Soldering Conditions Recommended Condition
Symbol
Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C
or higher), Count: three times or less
IR35-00-3
VPS Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C
or higher), Count: three times or less
VP15-00-3
Wave soldering Soldering bath temperature: 260°C max., Time: 10 seconds max.,
Count: 1, Preheating temperature: 120°C max. (package surface
temperature)
WS60-00-1
Partial heating Pin temperature: 350°C max., Time: 3 seconds max. (per pin row) −
Caution Do not use different soldering methods together (except for partial heating).
CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS
User’s Manual U14800EJ3V0UD
311
Table 25-1. Surface Mounting Type Soldering Conditions (2/3)
µ
PD789304GK-×××-9ET: 64-pin plastic TQFP (fine pitch) (12 × 12)
µ
PD789306GK-×××-9ET: 64-pin plastic TQFP (fine pitch) (12 × 12)
µ
PD789314GK-×××-9ET: 64-pin plastic TQFP (fine pitch) (12 × 12)
µ
PD789316GK-×××-9ET: 64-pin plastic TQFP (fine pitch) (12 × 12)
µ
PD78F9306GK-9ET: 64-pin plastic TQFP (fine pitch) (12 × 12)
µ
PD78F9316GK-9ET: 64-pin plastic TQFP (fine pitch) (12 × 12)
Soldering Method Soldering Conditions Recommended Condition
Symbol
Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C
or higher), Count: Twice or less, Exposure limit: 7 daysNote (after that,
prebake at 125°C for 10 to 72 hours)
IR35-107-2
VPS Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C
or higher), Count: Twice or less, Exposure limit: 7 daysNote (after that,
prebake at 125°C for 10 to 72 hours)
VP15-107-2
Wave soldering Soldering bath temperature: 260°C max., Time: 10 seconds max.,
Count: 1, Preheating temperature: 120°C max. (package surface
temperature), Exposure limit: 7 daysNote (after that, prebake at 125°C for
10 to 72 hours)
WS60-107-1
Partial heating Pin temperature: 350°C max., Time: 3 seconds max. (per pin row) −
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS
User’s Manual U14800EJ3V0UD
312
Table 25-1. Surface Mounting Type Soldering Conditions (3/3)
µ
PD789304GK-×××-9ET-A: 64-pin plastic TQFP (fine pitch) (12 × 12)
µ
PD789306GK-×××-9ET-A: 64-pin plastic TQFP (fine pitch) (12 × 12)
µ
PD789314GK-×××-9ET-A: 64-pin plastic TQFP (fine pitch) (12 × 12)
µ
PD789316GK-×××-9ET-A: 64-pin plastic TQFP (fine pitch) (12 × 12)
µ
PD78F9306GK-9ET-A: 64-pin plastic TQFP (fine pitch) (12 × 12)
µ
PD78F9316GK-9ET-A: 64-pin plastic TQFP (fine pitch) (12 × 12)
Soldering Method Soldering Conditions Recommended Condition
Symbol
Infrared reflow Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C
or higher), Count: Three times or less, Exposure limit: 7 daysNote (after
that, prebake at 125°C for 20 to 72 hours)
IR60-207-3
Wave soldering When the pin pitch of the package is 0.65 mm or more, wave soldering
can also be performed.
For details, contact an NEC Electronics sales representative.
−
Partial heating Pin temperature: 350°C max., Time: 3 seconds max. (per pin row) −
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
Remarks 1. Products that have the part numbers suffixed by "-A" are lead-free products.
2. For soldering methods and conditions other than those recommended above, contact an NEC
Electronics sales representative.
User’s Manual U14800EJ3V0UD
313
APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for development of systems using the
µ
PD789306 and
µ
PD789316
Subseries.
Figure A-1 shows development tools.
• Support of PC98-NX series
Unless specified otherwise, the products supported by IBM PC/AT™ compatibles can be used in the PC98-NX
series. When using the PC98-NX series, refer to the explanation of IBM PC/AT compatibles.
• WindowsTM
Unless specified otherwise, “Windows” indicates the following operating systems.
• Windows 3.1
• Windows 95
• Windows 98
• Windows 2000
• Windows NTTM Ver. 4.0
• Windows XP
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U14800EJ3V0UD
314
Figure A-1. Development Tools
Language processing software
· Assembler package
· C compiler package
· Device file
· C library source file
Note 1
Debugging software
· Integrated debugger
· System simulator
Host machine
(PC or EWS)
Interface adapter
In-circuit emulator
Emulation board
Emulation probe
Conversion socket or
conversion adapter
Target system
Flash programmer
Flash memory
writing adapter
Flash memory
Power supply unit
· Software package
Control software
· Project Manager
(Windows version only)
Note 2
Software package
Flash memory writing environment
Notes 1. C library source file is not included in the software package.
2. Project Manager is included in the assembler package.
Project Manager is used only in the Windows environment.
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U14800EJ3V0UD
315
A.1 Software Package
Software tools for development of the 78K/0S Series are combined in this package.
The following tools are included.
RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S, and device files
SP78K0S
Software package
Part number:
µ
S××××SP78K0S
Remark ×××× in the part number differs depending on the operating system to be used.
µ
S××××SP78K0S
×××× Host Machine OS Supply Medium
AB17 Japanese Windows CD-ROM
BB17
PC-9800 series, IBM PC/AT
compatibles English Windows
A.2 Language Processing Software
Program that converts program written in mnemonic into object codes that can be executed
by microcontroller.
In addition, automatic functions to generate a symbol table and optimize branch instructions
are also provided.
Used in combination with a device file (DF789306) (sold separately).
<Caution when used in PC environment>
The assembler package is a DOS-based application but may be used in the Windows
environment by using the Project Manager of Windows (included in the assembler package).
RA78K0S
Assembler package
Part number:
µ
S××××RA78K0S
Program that converts program written in C language into object codes that can be executed
by microcontroller.
Used in combination with an assembler package (RA78K0S) and device file (DF789306)
(both sold separately).
<Caution when used in PC environment>
The C compiler package is a DOS-based application but may be used in the Windows
environment by using the Project Manager of Windows (included in the assembler package).
CC78K0S
C compiler package
Part number:
µ
S××××CC78K0S
File containing the information inherent to the device.
Used in combination with the RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S (all sold
separately).
DF789306Note 1
Device file
Part number:
µ
S××××DF789306
Source file of functions for generating object library included in C compiler package.
Necessary for changing object library included in C compiler package according to
customer’s specifications. Since this is a source file, its working environment does not
depend on any particular operating system.
CC78K0S-LNote 2
C library source file
Part number:
µ
S××××CC78K0S-L
Notes 1. DF789306 is a common file that can be used with RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S.
2. CC78K0S-L is not included in the software package (SP78K0S).
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U14800EJ3V0UD
316
Remark ×××× in the part number differs depending on the host machine and operating system to be used.
µ
S××××RA78K0S
µ
S××××CC78K0S
×××× Host Machine OS Supply Medium
AB13 Japanese Windows
BB13 English Windows
3.5-inch 2HD FD
AB17 Japanese Windows
BB17
PC-9800 series,
IBM PC/AT compatibles
English Windows
3P17 HP9000 series 700TM HP-UXTM (Rel. 10.10)
3K17 SPARCstationTM SunOSTM (Rel. 4.1.4),
SolarisTM (Rel. 2.5.1)
CD-ROM
µ
S××××DF789306
µ
S××××CC78K0S-L
×××× Host Machine OS Supply Medium
AB13 Japanese Windows 3.5-inch 2HD FD
BB13
PC-9800 series,
IBM PC/AT compatibles English Windows
3P16 HP9000 series 700 HP-UX (Rel. 10.10) DAT
3K13 3.5-inch 2HD FD
3K15
SPARCstation SunOS (Rel. 4.1.4),
Solaris (Rel. 2.5.1) 1/4-inch CGMT
A.3 Control Software
Project Manager Control software created for efficient development of the user program in the Windows
environment. User program development operations such as editor startup, build, and
debugger startup can be performed from the Project Manager.
<Caution>
The Project Manager is included in the assembler package (RA78K0S).
The Project Manager is used only in the Windows environment.
A.4 Flash Memory Writing Tools
Flashpro III (FL-PR3, PG-FP3)
Flashpro IV (FL-PR4, PG-FP4)
Flash programmer
Dedicated flash programmer for microcontrollers incorporating flash memory
FA-64GC
FA-64GK-9ET
Flash memory writing adapter
Adapter for writing to flash memory and connected to Flashpro III or Flashpro IV.
• FA-64GC: For 64-pin plastic QFP (GC-AB8 type)
• FA-64GK-9ET: For 64-pin plastic TQFP (GK-9ET type)
Remark The FL-PR3, FL-PR4, FA-64GC, and FA-64GK-9ET are products made by Naito Densei Machida Mfg.
Co., Ltd. (TEL +81-45-475-4191).
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U14800EJ3V0UD
317
A.5 Debugging Tools (Hardware)
IE-78K0S-NS
In-circuit emulator
In-circuit emulator for debugging a hardware and software of application system using the
78K/0S Series. Supports an integrated debugger (ID78K0S-NS). Used in combination with an
AC adapter, emulation probe, and interface adapter for connecting the host machine.
IE-78K0S-NS-A
In-circuit emulator
The IE-78K0S-NS-A provides a coverage function in addition to the IE-78K0S-NS functions,
thus enhancing the debug functions, including the tracer and timer functions.
IE-70000-MC-PS-B
AC adapter
Adapter for supplying power from AC 100 to 240 V outlet.
IE-70000-98-IF-C
Interface adapter
Adapter necessary when using a PC-9800 series PC (except notebook type) as the host
machine (C bus supported)
IE-70000-CD-IF-A
PC card interface
PC card and interface cable necessary when using a notebook PC as the host machine
(PCMCIA socket supported)
IE-70000-PC-IF-C
Interface adapter
Adapter necessary when using an IBM PC/AT compatible as the host machine of the (ISA bus
supported)
IE-70000-PCI-IF-A
Interface adapter
Adapter necessary when using a personal computer incorporating the PCI bus as the host
machine
IE-789306-NS-EM1
Emulation board
Board for emulating the peripheral hardware specific to the device. Used in combination with
an in-circuit emulator.
NP-64GC
Emulation probe
Cable to connect an in-circuit emulator to the target system. Used in combination with the
EV-9200G-64.
EV-9200G-64
Conversion socket
Conversion socket to connect the NP-64GC to a target system board on which an 64-pin plastic
QFP (GC-AB8 type) can be mounted.
NP-64GC-TQ
NP-H64GC-TQ
Emulation probe
Cable to connect an in-circuit emulator to the target system. Used in combination with the TGB-
064SAP.
TGB-064SAP
Conversion adapter
Conversion adapter to connect the NP-64GC-TQ or NP-H64GC-TQ to a target system board on
which an 64-pin plastic QFP (GC-AB8 type) can be mounted.
NP-64GK
NP-H64GK-TQ
Emulation probe
Cable to connect an in-circuit emulator to the target system. Used in combination with the TGK-
064SBW.
TGK-064SBW
Conversion adapter
Conversion adapter to connect the NP-64GK or NP-H64GK-TQ to a target system board on
which an 64-pin plastic TQFP (fine pitch) (GK-9ET type) can be mounted.
Remarks 1. The NP-64GC, NP-64GC-TQ, NP-H64GC-TQ, NP-64GK, and NP-H64GK-TQ are products made by
Naito Densei Machida Mfg. Co., Ltd. (TEL +81-45-475-4191).
2. The TGC-064SAP and TGK-064SBW are products made by TOKYO ELETECH CORPORATION.
For further information, contact: Daimaru Kogyo, Ltd.
Tokyo Electronics Department (TEL +81-3-3820-7112)
Osaka Electronics Department (TEL +81-6-6244-6672)
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U14800EJ3V0UD
318
A.6 Debugging Tools (Software)
This debugger supports the in-circuit emulators IE-78K0S-NS and IE-78K0S-NS-A for the
78K/0S Series. The ID78K0S-NS is Windows-based software.
It has improved C-compatible debugging functions and can display the results of tracing with
the source program using an integrating window function that associates the source
program, disassemble display, and memory display with the trace result.
Used in combination with a device file (DF789306) (sold separately).
ID78K0S-NS
Integrated debugger
Part number:
µ
S××××ID78K0S-NS
This is a system simulator for the 78K/0S Series. The SM78K0S is Windows-based
software.
It can be used to debug the target system at C source level or assembler level while
simulating the operation of the target system on the host machine.
Using SM78K0S, the logic and performance of the application can be verified independently
of hardware development. Therefore, the development efficiency can be enhanced and the
software quality can be improved.
Used in combination with a device file (DF789306) (sold separately).
SM78K0S
System simulator
Part number:
µ
S××××SM78K0S
File containing the information inherent to the device.
Used in combination with the RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S (all sold
separately).
DF789306Note
Device file
Part number:
µ
S××××DF789306
Note DF789306 is a common file that can be used with RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S.
Remark ×××× in the part number differs depending on the operating system and supply medium to be used.
µ
S××××ID78K0S-NS
µ
S××××SM78K0S
×××× Host Machine OS Supply Medium
AB13 Japanese Windows
BB13 English Windows
3.5-inch 2HD FD
AB17 Japanese Windows
BB17
PC-9800 series,
IBM PC/AT compatibles
English Windows
CD-ROM
User’s Manual U14800EJ3V0UD 319
APPENDIX B CAUTIONS ON DESIGNING TARGET SYSTEM
The following shows the conditions when connecting the emulation probe to the conversion adapter. Follow the
configuration below and consider the shape of parts to be mounted on the target system when designing a system.
Among the products described in this appendix, NP-64GC-TQ, NP-H64GC-TQ, NP-64GK, and NP-H64GK-TQ are
products of Naito Densei Machida Mfg. Co., Ltd, and TGC-064SAP and TGK-064SBW are products of TOKYO
ELETECH CORPORATION.
Table B-1. Distance Between IE System and Conversion Adapter
Emulation Probe Conversion Adapter Distance Between IE System and Conversion Adapter
NP-64GC-TQ 170 mm
NP-H64GC-TQ
TGC-064SAP
370 mm
NP-64GK 170 mm
NP-H64GK-TQ
TGK-064SBW
370 mm
Figure B-1. Distance Between In-Circuit Emulator and Conversion Adapter
(When 64GC Is Used)
170 mm
Note
In-circuit emulator
IE-78K0S-NS or IE-78K0S-NS-A
Emulation board
IE-789306-NS-EM1
Conversion adapter: TGC-064SAP
Target system
CN1
Emulation probe
NP-64GC-TQ
NP-H64GC-TQ
Note Distance when NP-64GC-TQ is used. When NP-H64GC-TQ is used, the distance is 370 mm.
APPENDIX B CAUTIONS ON DESIGNING TARGET SYSTEM
User’s Manual U14800EJ3V0UD
320
Figure B-2. Connection Conditions of Target System (When NP-64GC-TQ Is Used)
Figure B-3. Connection Conditions of Target System (When NP-H64GC-TQ Is Used)
Emulation probe
NP-64GC-TQ
Emulation board
IE-789306-NS-EM1
23 mm
25 mm
40 mm 34 mm
Target system
20.65 mm Pin 1
11 mm
20.65 mm
Conversion adapter
TGC-064SAP
Emulation probe
NP-H64GC-TQ
Emulation board
IE-789306-NS-EM1
23 mm
23 mm
42 mm 45 mm
Target system
20.65 mm Pin 1
11 mm
Conversion adapter
TGC-064SAP
20.65 mm
APPENDIX B CAUTIONS ON DESIGNING TARGET SYSTEM
User’s Manual U14800EJ3V0UD 321
Figure B-4. Distance Between In-Circuit Emulator and Conversion Adapter
(When 64GK Is Used)
170 mmNote
In-circuit emulator
IE-78K0S-NS or IE-78K0S-NS-A
Emulation board
IE-789306-NS-EM1
Conversion adapter
TGK-064SBW
Target system
CN1
Emulation probe
NP-64GK, NP-H64GK-TQ
Note Distance when NP-64GK is used. When NP-H64GK-TQ is used, the distance is 370 mm.
Figure B-5. Connection Conditions of Target System (When NP-64GK Is Used)
Emulation probe
NP-64GK
Emulation board
IE-789306-NS-EM1
21.95 mm
40 mm 34 mm
Target system
18.4 mm Pin 1
11 mm
25 mm
18.4 mm
Conversion adapter
TGK-064SBW
APPENDIX B CAUTIONS ON DESIGNING TARGET SYSTEM
User’s Manual U14800EJ3V0UD
322
Figure B-6. Connection Conditions of Target System (When NP-H64GK-TQ Is Used)
Emulation probe
NP-H64GK-TQ
Emulation board
IE-789306-NS-EM1
42 mm 45 mm
18.4 mm
Target system
18.4 mm
Pin 1
21.95 mm
23 mm
Conversion adapter
TGK-064SBW 11 mm
User’s Manual U14800EJ3V0UD 323
APPENDIX C REGISTER INDEX
C.1 Register Index (Alphabetic Order of Register Name)
[A]
Asynchronous serial interface mode register 20 (ASIM20) .................................................................................. 194
Asynchronous serial interface status register 20 (ASIS20) .................................................................................. 196
[B]
Baud rate generator control register 20 (BRGC20) .............................................................................................. 197
[C]
Carrier generator output control register 40 (TCA40) ........................................................................................... 140
[E]
8-bit compare register 30 (CR30)......................................................................................................................... 135
8-bit compare register 40 (CR40)......................................................................................................................... 135
8-bit compare register H40 (CRH40).................................................................................................................... 135
8-bit timer counter 30 (TM30)............................................................................................................................... 136
8-bit timer counter 40 (TM40)............................................................................................................................... 136
8-bit timer mode control register 30 (TMC30)....................................................................................................... 138
8-bit timer mode control register 40 (TMC40)....................................................................................................... 139
External interrupt mode register 0 (INTM0) .......................................................................................................... 243
External interrupt mode register 1 (INTM1) .......................................................................................................... 244
[ I ]
Interrupt mask flag register 0, 1 (MK0, MK1)........................................................................................................ 242
Interrupt request flag register 0, 1 (IF0, IF1)......................................................................................................... 241
[K]
Key return mode register 00 (KRM00).................................................................................................................. 245
[L]
LCD clock control register 0 (LCDC0) .................................................................................................................. 225
LCD display mode register 0 (LCDM0)................................................................................................................. 224
LCD voltage amplification control register 0 (LCDVA0)........................................................................................ 226
[O]
Oscillation stabilization time select register (OSTS)............................................................................................. 253
[P]
Port 0 (P0).............................................................................................................................................................. 78
Port 1 (P1).............................................................................................................................................................. 79
Port 2 (P2).............................................................................................................................................................. 80
Port 3 (P3).............................................................................................................................................................. 84
Port 5 (P5).............................................................................................................................................................. 87
APPENDIX C REGISTER INDEX
User’s Manual U14800EJ3V0UD
324
Port mode register 0 (PM0) ....................................................................................................................................87
Port mode register 1 (PM1) ....................................................................................................................................87
Port mode register 2 (PM2) ....................................................................................................................................87
Port mode register 3 (PM3) ....................................................................................................................................87
Port mode register 5 (PM5) ....................................................................................................................................87
Processor clock control register (PCC)...........................................................................................................94, 106
Pull-up resistor option register 0 (PU0)...................................................................................................................89
Pull-up resistor option register B2 (PUB2)..............................................................................................................89
Pull-up resistor option register B3 (PUB3)..............................................................................................................90
[R]
Receive buffer register 20 (RXB20)......................................................................................................................192
[S]
Subclock control register (CSS)......................................................................................................................96, 108
Suboscillation mode register (SCKM).............................................................................................................95, 107
Serial operation mode register 10 (CSIM10) ........................................................................................................183
Serial operation mode register 20 (CSIM20) ........................................................................................................193
Serial shift register 10 (SIO10) .............................................................................................................................181
16-bit capture register 20 (TCP20) .......................................................................................................................120
16-bit compare register 20 (CR20) .......................................................................................................................120
16-bit timer counter 20 (TM20) .............................................................................................................................120
16-bit timer mode control register 20 (TMC20) .....................................................................................................121
[T]
Transmit shift register 20 (TXS20)........................................................................................................................192
[W]
Watch timer mode control register (WTM)............................................................................................................171
Watchdog timer clock select register (WDCS)......................................................................................................176
Watchdog timer mode register (WDTM) ...............................................................................................................177
APPENDIX C REGISTER INDEX
User’s Manual U14800EJ3V0UD 325
C.2 Register Index (Alphabetic Order of Register Symbol)
[A]
ASIM20: Asynchronous serial interface mode register 20.................................................................................. 194
ASIS20: Asynchronous serial interface status register 20 ................................................................................. 196
[B]
BRGC20: Baud rate generator control register 20............................................................................................... 197
[C]
CR20: 16-bit compare register 20................................................................................................................... 120
CR30: 8-bit compare register 30..................................................................................................................... 135
CR40: 8-bit compare register 40..................................................................................................................... 135
CRH40: 8-bit compare register H40 .................................................................................................................. 135
CSIM10: Serial operation mode register 10 ....................................................................................................... 183
CSIM20: Serial operation mode register 20 ....................................................................................................... 193
CSS: Subclock control register ............................................................................................................... 96, 108
[ I ]
IF0: Interrupt request flag register 0 ...........................................................................................................241
IF1: Interrupt request flag register 1 ...........................................................................................................241
INTM0: External interrupt mode register 0 ....................................................................................................... 243
INTM1: External interrupt mode register 1 ....................................................................................................... 244
[K]
KRM00: Key return mode register 00 ................................................................................................................245
[L]
LCDC0: LCD clock control register 0 ................................................................................................................245
LCDM0: LCD display mode register 0 ............................................................................................................... 234
LCDVA0: LCD voltage amplification control register 0 ........................................................................................ 226
[M]
MK0: Interrupt mask flag register 0............................................................................................................... 242
MK1: Interrupt mask flag register 1............................................................................................................... 242
[O]
OSTS: Oscillation stabilization time select register ......................................................................................... 253
[P]
P0: Port 0..................................................................................................................................................... 78
P1: Port 1..................................................................................................................................................... 79
P2: Port 2..................................................................................................................................................... 80
P3: Port 3..................................................................................................................................................... 84
P5: Port 5..................................................................................................................................................... 86
PCC: Processor clock control register .................................................................................................... 94, 106
PM0: Port mode register 0.............................................................................................................................. 87
APPENDIX C REGISTER INDEX
User’s Manual U14800EJ3V0UD
326
PM1: Port mode register 1 ..............................................................................................................................87
PM2: Port mode register 2 ..............................................................................................................................87
PM3: Port mode register 3 ..............................................................................................................................87
PM5: Port mode register 5 ..............................................................................................................................87
PU0: Pull-up resistor option register 0 ............................................................................................................89
PUB2: Pull-up resistor option register B2..........................................................................................................89
PUB3: Pull-up resistor option register B3..........................................................................................................90
[R]
RXB20: Receive buffer register 20....................................................................................................................192
[S]
SCKM: Suboscillation mode register..........................................................................................................95, 107
SIO10: Serial sift register 10 ............................................................................................................................181
[T]
TCA40: Carrier generator output control register 40.........................................................................................140
TCP20: 16-bit capture register 20.....................................................................................................................120
TM20: 16-bit timer counter 20.........................................................................................................................120
TM30: 8-bit timer counter 30...........................................................................................................................136
TM40: 8-bit timer counter 40...........................................................................................................................136
TMC20: 16-bit timer mode control register 20 ...................................................................................................121
TMC30: 8-bit timer mode control register 30 .....................................................................................................138
TMC40: 8-bit timer mode control register 40 .....................................................................................................139
TXS20: Transmit shift register 20 .....................................................................................................................192
[W]
WDCS: Watchdog timer clock select register ...................................................................................................176
WDTM: Watchdog timer mode register.............................................................................................................177
WTM: Watch timer mode control register .......................................................................................................171
User’s Manual U14800EJ3V0UD 327
APPENDIX D REVISION HISTORY
D.1 Major Revisions in This Edition
Page Description
pp.17, 18, 20-22,
24
CHAPTER 1 GENERAL (
µ
PD789306 SUBSERIES)
• Addition of lead-free products
µ
PD789304GK-×××-9ET-A,
µ
PD789304GC-×××-8BS-A,
µ
PD789306GK-×××-9ET-A,
µ
PD789306GC-×××-8BS-A,
µ
PD78F9306GK-9ET-A,
µ
PD78F9306GC-8BS-A
• Update of 1.5 78K/0S Series Lineup to latest version
• Addition of package (GC-8BS) in 1.7 Overview of Functions
pp.27, 28, 30-32,
34
CHAPTER 2 GENERAL (
µ
PD789316 SUBSERIES)
• Addition of lead-free products
µ
PD789314GK-×××-9ET-A,
µ
PD789314GC-×××-8BS-A,
µ
PD789316GK-×××-9ET-A,
µ
PD789316GC-×××-8BS-A,
µ
PD78F9316GK-9ET-A,
µ
PD78F9316GC-8BS-A
• Update of 2.5 78K/0S Series Lineup to latest version
• Addition of package (GC-8BS) in 2.7 Overview of Functions
p.149
CHAPTER 10 8-BIT TIMER 30, 40
• Modification of Figure 10-14. Timing of Operation of External Event Counter with 8-Bit Resolution
p.222, 224, 227
CHAPTER 15 LCD CONTROLLER/DRIVER
• Modification of Figure 15-2. Block Diagram of LCD Controller/Driver
• Modification of Caution in Figure 15-3. Format of LCD Display Mode Register 0
• Modification of 15.4 Setting LCD Controller/Driver
p.302 CHAPTER 22 ELECTRICAL SPECIFICATIONS
• Correction of note in LCD Characteristics
p.307
CHAPTER 24 PACKAGE DRAWINGS
• Addition of package drawing of 64-pin plastic LQFP (GC-8BS)
p.312 CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS
• Addition of soldering conditions of lead-free products in Table 25-1. Surface Mounting Type Soldering
Conditions
pp. 315, 316, 318 APPENDIX A DEVELOPMENT TOOLS
• Correction of device file name from DF789316 to DF789306
APPENDIX D REVISION HISTORY
User’s Manual U14800EJ3V0UD
328
D.2 Revision History of Previous Editions
The revision history is described below. The “Applied to:” column indicates the chapterin each edition.
(1/2)
Edition Major Revision from Previous Edition Applied to:
Modification of pin handling in 3.2.15 VPP (
µ
PD78F9306 only) and 4.2.15 VPP
(
µ
PD78F9316 only)
CHAPTER 3
PIN FUNCTIONS
(
µ
PD789306 SUBSERIES)
Modification of Table 3-1 and Table 4-1 Types of Pin Input/Output Circuits CHAPTER 3
PIN FUNCTIONS
(
µ
PD789306 SUBSERIES)
CHAPTER 4
PIN FUNCTIONS
(
µ
PD789316 SUBSERIES)
Correction of interrupt request neme in Table 5-2. Vector Table
Modification of descriptions about Symbol in 5.2.3 Special function registers
(SFRs)
CHAPTER 5
CPU ARCHITECTURE
Correction of Figure 6-3. Block Diagram of P10 to P13 CHAPTER 6
PORT FUNCTIONS
Addition of note about Feedback resistor in Figure 7-3 and Figure 8-3 CHAPTER 7
CLOCK GENERATOR
(
µ
PD789306 SUBSERIES)
CHAPTER 8
CLOCK GENERATOR
(
µ
PD789316 SUBSERIES)
Modification of descriptions in 9.4.1 Operation as timer interrupt and 9.4.2
Operation as timer output
Addition of 9.5 Cautions on Using 16-Bit Timer 20
CHAPTER 9
16-BIT TIMER 20
10.2 8-Bit Timer 30, 40 Configuration
• Modification of Figure 10-3. Block Diagram of Output Controller (Timer 40)
• Modification of cautions in (1) 8-bit compare register 30 (CR30)
• Addition of descriptions in (2) 8-bit compare register 40 (CR40)
• Addition of descriptions in (3) 8-bit compare register H40 (CRH40)
Addition of cautions in Figure 10-6. Format of Carrier Generator Output Control
Register 40
Addition of descriptions and cautions in 10.4.3 Operation as carrier generator
2nd
10.5 Notes on Using 8-Bit Timer 30, 40
• Modification of descriptions in (1) Error on starting timer
• Addition of (2) Count value if external clock input from TMI40 pin is selected
CHAPTER 10
8-BIT TIMER 30, 40
APPENDIX D REVISION HISTORY
User’s Manual U14800EJ3V0UD 329
(2/2)
Edition Description Applied to:
Modification of Figure 14-1. Block Diagram of Serial Interface 20
Modification of description about PE flag in Figure 14-5. Format of Asynchronous
Serial Interface Status Register 20
Modification of cautions in Figure 14-6. Format of Baud Rate Generator Control
Register 20
Addition of description about reading receive data in 14.4.2 Asynchronous serial
interface (UART) mode
Division of Figure 14-11. 3-Wire Serial I/O Mode Timing into Master operation and
Slave operation.
CHAPTER 14
SERIAL INTERFACE 20
Addition of Figure 15-1. Correspondence with LCD Display RAM
Modification of Figure 15-2. Block Diagram of LCD Controller/Driver
15.3 Registers Controlling LCD Controller/Driver
• Modification of description about LCDON0, VAON0 in (1) LCD display mode
register 0 (LCDM0)
• Addition of description about frame frequencie in (2) LCD clock control register 0
(LCDC0)
• Modification of description about GAIN in (3) LCD voltage amplification control
register 0 (LCDVA0)
Addition of 15.8 Supplying LCD Drive Voltages VLC0, VLC1, and VLC2
CHAPTER 15
LCD CONTROLLER/DRIVER
Addition of cautions in Figure 16-2. Format of Interrupt Request Flag Registers
Addition of cautions in Figure 16-7. Format of Key Return Mode Register 00
CHAPTER 16
INTERRUPT FUNCTIONS
Overall revision of contents related to flash memory programming as 19.1 Flash
Memory Characteristics
CHAPTER 19
FLASH MEMORY
Addition of electrical specifications CHAPTER 22
ELECTRICAL
SPECIFICATIONS
Addition of characteristics curves of LCD comtroller/driver (reference values) CHAPTER 23
CHARACTERISTICS
CURVES OF LCD
CONTROLLER/DRIVER
(REFERENCE VALUES)
Addition of package drawings CHAPTER 24
PACKAGE DRAWINGS
Addition of recommended soldering conditions CHAPTER 25
RECOMMENDED
SOLDERING CONDITIONS
Overall revision of contents of APPENDIX A DEVELOPMENT TOOLS
Deletion of embedded software
APPENDIX A
DEVELOPMENT TOOLS
Addition of cautions on designing target system APPENDIX B
CAUTIONS ON DESIGNING
TARGET SYSTEM
2nd
Addition of revision history APPENDIX D
REVISION HISTORY
