2003 Microchip Technology Inc. DS30235J
PIC16C62X
Data Sheet
EPROM-Based 8-Bit
CMOS Microcontrollers
DS30235J - page ii 2003 Microchip Technology Inc.
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© 2003, Microchip Technology Incorporated, Printed in the
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Printed on recycled paper.
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design and wafer fabrication facilities in
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and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
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Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
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Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
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2003 Microchip Technology Inc. DS30235J-page 1
PIC16C62X
Devices included in this data sheet:
Referred to collectively as PIC16C62X.
PIC16C620 PIC16C620A
PIC16C621 PIC16C621A
PIC16C622 PIC16C622A
PIC16CR620A
High Performance RISC CPU:
Only 35 instructions to learn
All single cycle instructions (200 ns), except for
program branches which are two-cycle
Operating speed:
- DC - 40 MHz clock input
- DC - 100 ns instruction cycle
Interrupt capability
16 special function hardware registers
8-level deep hardware stack
Direct, Indirect and Relative addressing modes
Peripheral Features:
13 I/O pins with individual direction control
High current sink/source for direct LED drive
Analog comparator module with:
- Two analog comparators
- Programmable on-chip voltage reference
(VREF) module
- Programmable input multiplexing from device
inputs and internal voltage reference
- Comparator outputs can be output signals
Timer0: 8-bit timer/counter with 8-bit
programmable prescaler
Pin Diagrams
Special Microcontroller Features:
Power-on Reset (POR)
Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
Brown-out Reset
Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
Programmable code protection
Power saving SLEEP mode
Selectable oscillator options
Serial in-circuit programming (via two pins)
Four user programmable ID locations
CMOS Technology:
Low power, high speed CMOS EPROM
technology
Fully static design
Wide operating range
- 2.5V to 5.5V
Commercial, industrial and extended tempera-
ture range
Low power consumption
- < 2.0 mA @ 5.0V, 4.0 MHz
-15 µA typical @ 3.0V, 32 kHz
-< 1.0 µA typical standby current @ 3.0V
Device Program
Memory
Data
Memory
PIC16C620 512 80
PIC16C620A 512 96
PIC16CR620A 512 96
PIC16C621 1K 80
PIC16C621A 1K 96
PIC16C622 2K 128
PIC16C622A 2K 128
RA1/AN1
RA0/AN0
OSC2/CLKOUT
VDD
RB7
RB6
RB5
RB4
OSC1/CLKIN
RA2/AN2/VREF
RA3/AN3
MCLR/VPP
VSS
RB0/INT
RB1
RB2
RB3
RA4/T0CKI
PIC16C62X
RA1/AN1
RA0/AN0
OSC2/CLKOUT
VDD
RB7
RB6
RB5
RB4
OSC1/CLKIN
RA2/AN2/VREF
RA3/AN3
MCLR/VPP
VSS
VSS
RB0/INT
RB1
RB2
RA4/T0CKI
RB3RB3
VDD
PDIP, SOIC, Windowed CERDIP
SSOP
2
3
4
5
6
7
8
9
10
•1
2
3
4
5
6
7
8
9
•1
19
18
16
15
14
13
12
11
17
18
17
15
14
13
12
11
10
16
20
PIC16C62X
EPROM-Based 8-Bit CMOS Microcontrollers
PIC16C62X
DS30235J-page 2 2003 Microchip Technology Inc.
Device Differences
Note 1: If you change from this device to another device, please verify oscillator characteristics in your application.
2: For ROM parts, operation from 2.5V - 3.0V will require the PIC16LCR62X parts.
3: For OTP parts, operation from 2.5V - 3.0V will require the PIC16LC62X parts.
4: For OTP parts, operations from 2.7V - 3.0V will require the PIC16LC62XA parts.
Device Voltage Range Oscillator Process Technology
(Microns)
PIC16C620(3) 2.5 - 6.0 See Note 1 0.9
PIC16C621(3) 2.5 - 6.0 See Note 1 0.9
PIC16C622(3) 2.5 - 6.0 See Note 1 0.9
PIC16C620A(4) 2.7 - 5.5 See Note 1 0.7
PIC16CR620A(2) 2.5 - 5.5 See Note 1 0.7
PIC16C621A(4) 2.7 - 5.5 See Note 1 0.7
PIC16C622A(4) 2.7 - 5.5 See Note 1 0.7
2003 Microchip Technology Inc. DS30235J-page 3
PIC16C62X
Table of Contents
1.0 General Description .................................................................................................................................................................. 5
2.0 PIC16C62X Device Varieties.................................................................................................................................................... 7
3.0 Architectural Overview.............................................................................................................................................................. 9
4.0 Memory Organization ............................................................................................................................................................. 13
5.0 I/O Ports.................................................................................................................................................................................. 25
6.0 Timer0 Module........................................................................................................................................................................ 31
7.0 Comparator Module ................................................................................................................................................................ 37
8.0 Voltage Reference Module ..................................................................................................................................................... 43
9.0 Special Features of the CPU .................................................................................................................................................. 45
10.0 Instruction Set Summary ........................................................................................................................................................ 61
11.0 Development Support ............................................................................................................................................................. 75
12.0 Electrical Specifications .......................................................................................................................................................... 81
13.0 Device Characterization Information ..................................................................................................................................... 109
14.0 Packaging Information .......................................................................................................................................................... 113
Appendix A: Enhancements.............................................................................................................................................................. 119
Appendix B: Compatibility ................................................................................................................................................................. 119
Index ............................................................................................................................................................................................... 121
On-Line Support ................................................................................................................................................................................ 123
Systems Information and Upgrade Hot Line ..................................................................................................................................... 123
Reader Response ............................................................................................................................................................................. 124
Product Identification System ........................................................................................................................................................... 125
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PIC16C62X
DS30235J-page 4 2003 Microchip Technology Inc.
NOTES:
2003 Microchip Technology Inc. DS30235J-page 5
PIC16C62X
1.0 GENERAL DESCRIPTION
The PIC16C62X devices are 18 and 20-Pin ROM/
EPROM-based members of the versatile PICmicro®
family of low cost, high performance, CMOS, fully-
static, 8-bit microcontrollers.
All PICmicro microcontrollers employ an advanced
RISC architecture. The PIC16C62X devices have
enhanced core features, eight-level deep stack, and
multiple internal and external interrupt sources. The
separate instruction and data buses of the Harvard
architecture allow a 14-bit wide instruction word with
the separate 8-bit wide data. The two-stage instruction
pipeline allows all instructions to execute in a single
cycle, except for program branches (which require two
cycles). A total of 35 instructions (reduced instruction
set) are available. Additionally, a large register set
gives some of the architectural innovations used to
achieve a very high performance.
PIC16C62X microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.
The PIC16C620A, PIC16C621A and PIC16CR620A
have 96 bytes of RAM. The PIC16C622(A) has 128
bytes of RAM. Each device has 13 I/O pins and an 8-
bit timer/counter with an 8-bit programmable prescaler.
In addition, the PIC16C62X adds two analog compara-
tors with a programmable on-chip voltage reference
module. The comparator module is ideally suited for
applications requiring a low cost analog interface (e.g.,
battery chargers, threshold detectors, white goods
controllers, etc).
PIC16C62X devices have special features to reduce
external components, thus reducing system cost,
enhancing system reliability and reducing power con-
sumption. There are four oscillator options, of which the
single pin RC oscillator provides a low cost solution, the
LP oscillator minimizes power consumption, XT is a
standard crystal, and the HS is for High Speed crystals.
The SLEEP (Power-down) mode offers power savings.
The user can wake-up the chip from SLEEP through
several external and internal interrupts and RESET.
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software
lock- up.
A UV-erasable CERDIP-packaged version is ideal for
code development while the cost effective One-Time-
Programmable (OTP) version is suitable for production
in any volume.
Table 1-1 shows the features of the PIC16C62X mid-
range microcontroller families.
A simplified block diagram of the PIC16C62X is shown
in Figure 3-1.
The PIC16C62X series fits perfectly in applications
ranging from battery chargers to low power remote
sensors. The EPROM technology makes
customization of application programs (detection
levels, pulse generation, timers, etc.) extremely fast
and convenient. The small footprint packages make
this microcontroller series perfect for all applications
with space limitations. Low cost, low power, high
performance, ease of use and I/O flexibility make the
PIC16C62X very versatile.
1.1 Family and Upward Compatibility
Those users familiar with the PIC16C5X family of
microcontrollers will realize that this is an enhanced
version of the PIC16C5X architecture. Please refer to
Appendix A for a detailed list of enhancements. Code
written for the PIC16C5X can be easily ported to
PIC16C62X family of devices (Appendix B). The
PIC16C62X family fills the niche for users wanting to
migrate up from the PIC16C5X family and not needing
various peripheral features of other members of the
PIC16XX mid-range microcontroller family.
1.2 Development Support
The PIC16C62X family is supported by a full-featured
macro assembler, a software simulator, an in-circuit
emulator, a low cost development programmer and a
full-featured programmer. Third Party “C” compilers are
also available.
PIC16C62X
DS30235J-page 6 2003 Microchip Technology Inc.
TABLE 1-1: PIC16C62X FAMILY OF DEVICES
PIC16C620(3) PIC16C620A(1)(4) PIC16CR620A(2) PIC16C621(3) PIC16C621A(1)(4) PIC16C622(3) PIC16C622A(1)(4)
Clock Maximum Frequency
of Operation (MHz)
20 40 20 20 40 20 40
Memory EPROM Program
Memory
(x14 words)
512 512 512 1K 1K 2K 2K
Data Memory (bytes) 80 96 96 80 96 128 128
Peripherals Timer Module(s) TMR0 TMR0 TMRO TMR0 TMR0 TMR0 TMR0
Comparators(s) 2 2 2 2 2 2 2
Internal Reference
Voltage
Yes Yes Yes Yes Yes Yes Yes
Features Interrupt Sources 4 4 4 4 4 4 4
I/O Pins 13 13 13 13 13 13 13
Voltage Range (Volts) 2.5-6.0 2.7-5.5 2.5-5.5 2.5-6.0 2.7-5.5 2.5-6.0 2.7-5.5
Brown-out Reset Yes Yes Yes Yes Yes Yes Yes
Packages 18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
All PICmicro® Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high
I/O current capability. All PIC16C62X Family devices use serial programming with clock pin RB6 and data pin RB7.
Note 1: If you change from this device to another device, please verify oscillator characteristics in your application.
2: For ROM parts, operation from 2.0V - 2.5V will require the PIC16LCR62XA parts.
3: For OTP parts, operation from 2.5V - 3.0V will require the PIC16LC62X part.
4: For OTP parts, operation from 2.7V - 3.0V will require the PIC16LC62XA part.
2003 Microchip Technology Inc. DS30235J-page 7
PIC16C62X
2.0 PIC16C62X DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC16C62X Product
Identification System section at the end of this data
sheet. When placing orders, please use this page of
the data sheet to specify the correct part number.
2.1 UV Erasable Devices
The UV erasable version, offered in CERDIP package,
is optimal for prototype development and pilot
programs. This version can be erased and
reprogrammed to any of the Oscillator modes.
Microchip's PICSTART and PRO MATE
programmers both support programming of the
PIC16C62X.
2.2 One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications. In addition to
the program memory, the configuration bits must also
be programmed.
2.3 Quick-Turnaround-Production
(QTP) Devices
Microchip offers a QTP programming service for
factory production orders. This service is made
available for users who chose not to program a medium
to high quantity of units and whose code patterns have
stabilized. The devices are identical to the OTP
devices, but with all EPROM locations and configura-
tion options already programmed by the factory.
Certain code and prototype verification procedures
apply before production shipments are available.
Please contact your Microchip Technology sales office
for more details.
2.4 Serialized Quick-Turnaround-
ProductionSM (SQTPSM) Devices
Microchip offers a unique programming service where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number, which can serve as an entry-code,
password or ID number.
Note: Microchip does not recommend code
protecting windowed devices.
PIC16C62X
DS30235J-page 8 2003 Microchip Technology Inc.
NOTES:
2003 Microchip Technology Inc. DS30235J-page 9
PIC16C62X
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16C62X family can be
attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC16C62X uses a Harvard architecture, in
which, program and data are accessed from separate
memories using separate busses. This improves
bandwidth over traditional von Neumann architecture,
where program and data are fetched from the same
memory. Separating program and data memory further
allows instructions to be sized differently than 8-bit
wide data word. Instruction opcodes are 14-bits wide
making it possible to have all single word instructions.
A 14-bit wide program memory access bus fetches a
14-bit instruction in a single cycle. A two-stage pipeline
overlaps fetch and execution of instructions.
Consequently, all instructions (35) execute in a single
cycle (200 ns @ 20 MHz) except for program branches.
The PIC16C620(A) and PIC16CR620A address
512 x 14 on-chip program memory. The PIC16C621(A)
addresses 1K x 14 program memory. The
PIC16C622(A) addresses 2K x 14 program memory.
All program memory is internal.
The PIC16C62X can directly or indirectly address its
register files or data memory. All special function
registers including the program counter are mapped in
the data memory. The PIC16C62X has an orthogonal
(symmetrical) instruction set that makes it possible to
carry out any operation on any register using any
Addressing mode. This symmetrical nature and lack of
‘special optimal situations’ make programming with the
PIC16C62X simple yet efficient. In addition, the
learning curve is reduced significantly.
The PIC16C62X devices contain an 8-bit ALU and
working register. The ALU is a general purpose
arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.
The ALU is 8-bits wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the working register
(W register). The other operand is a file register or an
immediate constant. In single operand instructions, the
operand is either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a Borrow and Digit Borrow out bit,
respectively, bit in subtraction. See the SUBLW and
SUBWF instructions for examples.
A simplified block diagram is shown in Figure 3-1, with
a description of the device pins in Table 3-1.
PIC16C62X
DS30235J-page 10 2003 Microchip Technology Inc.
FIGURE 3-1: BLOCK DIAGRAM
EPROM
Program
Memory
13 Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8-Level Stack
(13-bit)
RAM
File
Registers
Direct Addr 7
RAM Addr (1) 9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MCLR VDD, VSS
Voltage
Brown-out
Reset
Note 1: Higher order bits are from the STATUS register.
Device Program
Memory
Data Memory
(RAM)
PIC16C620
PIC16C620A
PIC16CR620A
PIC16C621
PIC16C621A
PIC16C622
PIC16C622A
512 x 14
512 x 14
512 x 14
1K x 14
1K x 14
2K x 14
2K x 14
80 x 8
96 x 8
96 x 8
80 x 8
96 x 8
128 x 8
128 x 8
8
3
TMR0
I/O Ports
PORTB
Comparator
RA3/AN3
RA2/AN2/VREF
RA1/AN1
RA0/AN0
Reference
RA4/T0CKI
+
-
+
-
2003 Microchip Technology Inc. DS30235J-page 11
PIC16C62X
TABLE 3-1: PIC16C62X PINOUT DESCRIPTION
Name DIP/SOIC
Pin #
SSOP
Pin # I/O/P Type Buffer
Type Description
OSC1/CLKIN 16 18 IST/CMOS Oscillator crystal input/external clock source input.
OSC2/CLKOUT
15 17 O
Oscillator crystal output. Connects to crystal or resonator
in Crystal Oscillator mode. In RC mode, OSC2 pin out-
puts CLKOUT, which has 1/4 the frequency of OSC1
and denotes the instruction cycle rate.
MCLR/VPP
4 4 I/P ST Master Clear (Reset) input/programming voltage input.
This pin is an Active Low Reset to the device.
PORTA is a bi-directional I/O port.
RA0/AN0 17 19 I/O ST Analog comparator input
RA1/AN1 18 20 I/O ST Analog comparator input
RA2/AN2/VREF 1 1 I/O ST Analog comparator input or VREF output
RA3/AN3 2 2 I/O ST Analog comparator input /output
RA4/T0CKI
3 3 I/O ST
Can be selected to be the clock input to the Timer0
timer/counter or a comparator output. Output is
open drain type.
PORTB is a bi-directional I/O port. PORTB can be
software programmed for internal weak pull-up on all
inputs.
RB0/INT 6 7 I/O TTL/ST(1) RB0/INT can also be selected as an external
interrupt pin.
RB1 7 8 I/O TTL
RB2 8 9 I/O TTL
RB3 910 I/O TTL
RB4 10 11 I/O TTL Interrupt-on-change pin.
RB5 11 12 I/O TTL Interrupt-on-change pin.
RB6 12 13 I/O TTL/ST(2) Interrupt-on-change pin. Serial programming clock.
RB7 13 14 I/O TTL/ST(2) Interrupt-on-change pin. Serial programming data.
VSS 55,6 P Ground reference for logic and I/O pins.
VDD 14 15,16 P Positive supply for logic and I/O pins.
Legend: O = output I/O = input/output P = power
— = Not used I = Input ST = Schmitt Trigger input
TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
PIC16C62X
DS30235J-page 12 2003 Microchip Technology Inc.
3.1 Clocking Scheme/Instruction
Cycle
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the
program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The
instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 3-2.
3.2 Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
PC PC+1 PC+2
Fetch INST (PC)
Execute INST (PC-1) Fetch INST (PC+1)
Execute INST (PC) Fetch INST (PC+2)
Execute INST (PC+1)
Internal
phase
clock
Note: All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
1. MOVLW 55h Fetch 1 Execute 1
2. MOVWF PORTB Fetch 2 Execute 2
3. CALL SUB_1 Fetch 3 Execute 3
4. BSF PORTA, BIT3 Fetch 4 Flush
Fetch SUB_1 Execute SUB_1
2003 Microchip Technology Inc. DS30235J-page 13
PIC16C62X
4.0 MEMORY ORGANIZATION
4.1 Program Memory Organization
The PIC16C62X has a 13-bit program counter capable
of addressing an 8K x 14 program memory space. Only
the first 512 x 14 (0000h - 01FFh) for the
PIC16C620(A) and PIC16CR620, 1K x 14 (0000h -
03FFh) for the PIC16C621(A) and 2K x 14 (0000h -
07FFh) for the PIC16C622(A) are physically
implemented. Accessing a location above these
boundaries will cause a wrap-around within the first
512 x 14 space (PIC16C(R)620(A)) or 1K x 14 space
(PIC16C621(A)) or 2K x 14 space (PIC16C622(A)).
The RESET vector is at 0000h and the interrupt vector
is at 0004h (Figure 4-1, Figure 4-2, Figure 4-3).
FIGURE 4-1: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16C620/PIC16C620A/
PIC16CR620A
FIGURE 4-2: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16C621/PIC16C621A
FIGURE 4-3: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16C622/PIC16C622A
PC<12:0>
13
000h
0004
0005
01FFh
0200h
1FFFh
Stack Level 1
Stack Level 8
RESET Vector
Interrupt Vector
On-Chip Program
Memory
CALL, RETURN
RETFIE, RETLW
Stack Level 2
PC<12:0>
13
000h
0004
0005
03FFh
0400h
1FFFh
Stack Level 1
Stack Level 8
RESET Vector
Interrupt Vector
On-Chip Program
Memory
CALL, RETURN
RETFIE, RETLW
Stack Level 2
PC<12:0>
13
000h
0004
0005
07FFh
0800h
1FFFh
Stack Level 1
Stack Level 8
RESET Vector
Interrupt Vector
On-Chip Program
Memory
CALL, RETURN
RETFIE, RETLW
Stack Level 2
PIC16C62X
DS30235J-page 14 2003 Microchip Technology Inc.
4.2 Data Memory Organization
The data memory (Figure 4-4, Figure 4-5, Figure 4-6
and Figure 4-7) is partitioned into two banks, which
contain the General Purpose Registers and the Special
Function Registers. Bank 0 is selected when the RP0
bit is cleared. Bank 1 is selected when the RP0 bit
(STATUS <5>) is set. The Special Function Registers
are located in the first 32 locations of each bank.
Register locations 20-7Fh (Bank0) on the
PIC16C620A/CR620A/621A and 20-7Fh (Bank0) and
A0-BFh (Bank1) on the PIC16C622 and PIC16C622A
are General Purpose Registers implemented as static
RAM. Some Special Purpose Registers are mapped in
Bank 1.
Addresses F0h-FFh of bank1 are implemented as
common ram and mapped back to addresses 70h-7Fh
in bank0 on the PIC16C620A/621A/622A/CR620A.
4.2.1 GENERAL PURPOSE REGISTER
FILE
The register file is organized as 80 x 8 in the
PIC16C620/621, 96 x 8 in the PIC16C620A/621A/
CR620A and 128 x 8 in the PIC16C622(A). Each is
accessed either directly or indirectly through the File
Select Register FSR (Section 4.4).
2003 Microchip Technology Inc. DS30235J-page 15
PIC16C62X
FIGURE 4-4: DATA MEMORY MAP FOR
THE PIC16C620/621
FIGURE 4-5: DATA MEMORY MAP FOR
THE PIC16C622
INDF(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
CMCON
INDF(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIE1
PCON
VRCON
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h A0h
General
Purpose
Register
7Fh FFh
Bank 0 Bank 1
File
Address
6Fh
70h
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
File
Address
INDF(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
CMCON
INDF(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIE1
PCON
VRCON
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h A0h
General
Purpose
Register
7Fh FFh
Bank 0 Bank 1
File
Address
BFh
C0h
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
File
Address
General
Purpose
Register
PIC16C62X
DS30235J-page 16 2003 Microchip Technology Inc.
FIGURE 4-6: DATA MEMORY MAP FOR THE
PIC16C620A/CR620A/621A
FIGURE 4-7: DATA MEMORY MAP FOR
THE PIC16C622A
INDF(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
CMCON
INDF(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIE1
PCON
VRCON
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h A0h
General
Purpose
Register
7Fh FFh
Bank 0 Bank 1
File
Address
6Fh
70h
File
Address
Accesses
70h-7Fh
F0h
General
Purpose
Register
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
INDF(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
CMCON
INDF(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIE1
PCON
VRCON
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h A0h
General
Purpose
Register
7Fh FFh
Bank 0 Bank 1
File
Address
BFh
C0h
File
Address
General
Purpose
Register
Accesses
70h-7Fh
F0h
6Fh
70h General
Purpose
Register
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
2003 Microchip Technology Inc. DS30235J-page 17
PIC16C62X
4.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and Peripheral functions for controlling the
desired operation of the device (Table 4-1). These
registers are static RAM.
The Special Function Registers can be classified into
two sets (core and peripheral). The Special Function
Registers associated with the “core” functions are
described in this section. Those related to the operation
of the peripheral features are described in the section
of that peripheral feature.
TABLE 4-1: SPECIAL REGISTERS FOR THE PIC16C62X
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR Reset
Value on all
other
RESETS(1)
Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical
register)
xxxx xxxx xxxx xxxx
01h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu
02h PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
03h STATUS IRP(2) RP1(2) RP0 TO PD Z DC C0001 1xxx 000q quuu
04h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
05h PORTA RA4 RA3 RA2 RA1 RA0 ---x 0000 ---u 0000
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
07h-09h Unimplemented
0Ah PCLATH Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000
0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 CMIF -0-- ---- -0-- ----
0Dh-1Eh Unimplemented
1Fh CMCON C2OUT C1OUT CIS CM2 CM1 CM0 00-- 0000 00-- 0000
Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical
register) xxxx xxxx xxxx xxxx
81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
83h STATUS IRP(2) RP1(2) RP0 TO PD Z DC C0001 1xxx 000q quuu
84h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
85h TRISA TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
87h-89h Unimplemented
8Ah PCLATH Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000
8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Ch PIE1 CMIE -0-- ---- -0-- ----
8Dh Unimplemented
8Eh PCON POR BOR ---- --0x ---- --uq
8Fh-9Eh Unimplemented
9Fh VRCON VREN VROE VRR VR3 VR2 VR1 VR0 000- 0000 000- 0000
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown,
q = value depends on condition, shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Reset and Watchdog Timer Reset during
normal operation.
2: IRP & RP1 bits are reserved; always maintain these bits clear.
PIC16C62X
DS30235J-page 18 2003 Microchip Technology Inc.
4.2.2.1 STATUS Register
The STATUS register, shown in Register 4-1, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000uu1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any STATUS bit. For other instructions not
affecting any STATUS bits, see the “Instruction Set
Summary”.
REGISTER 4-1: STATUS REGISTER (ADDRESS 03H OR 83H)
Note 1: The IRP and RP1 bits (STATUS<7:6>)
are not used by the PIC16C62X and
should be programmed as ’0'. Use of
these bits as general purpose R/W bits is
NOT recommended, since this may affect
upward compatibility with future products.
2: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD ZDCC
bit 7 bit 0
bit 7 IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
The IRP bit is reserved on the PIC16C62X; always maintain this bit clear.
bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes. The RP1 bit is reserved on the PIC16C62X; always maintain this bit
clear.
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(for borrow the polarity
is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0 C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2003 Microchip Technology Inc. DS30235J-page 19
PIC16C62X
4.2.2.2 OPTION Register
The OPTION register is a readable and writable
register, which contains various control bits to configure
the TMR0/WDT prescaler, the external RB0/INT
interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 4-2: OPTION REGISTER (ADDRESS 81H)
Note: To achieve a 1:1 prescaler assignment for
TMR0, assign the prescaler to the WDT
(PSA = 1).
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
bit 7 RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate
PIC16C62X
DS30235J-page 20 2003 Microchip Technology Inc.
4.2.2.3 INTCON Register
The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for all interrupt sources except the comparator module.
See Section 4.2.2.4 and Section 4.2.2.5 for a
description of the comparator enable and flag bits.
REGISTER 4-3: INTCON REGISTER (ADDRESS 0BH OR 8BH)
Note: Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF
bit 7 bit 0
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4 INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit
1 = When at least one of the RB<7:4> pins changed state (must be cleared in software)
0 = None of the RB<7:4> pins have changed state
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2003 Microchip Technology Inc. DS30235J-page 21
PIC16C62X
4.2.2.4 PIE1 Register
This register contains the individual enable bit for the
comparator interrupt.
REGISTER 4-4: PIE1 REGISTER (ADDRESS 8CH)
4.2.2.5 PIR1 Register
This register contains the individual flag bit for the
comparator interrupt.
REGISTER 4-5: PIR1 REGISTER (ADDRESS 0CH)
U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0
CMIE
bit 7 bit 0
bit 7 Unimplemented: Read as '0'
bit 6 CMIE: Comparator Interrupt Enable bit
1 = Enables the Comparator interrupt
0 = Disables the Comparator interrupt
bit 5-0 Unimplemented: Read as '0'
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Note: Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0
CMIF
bit 7 bit 0
bit 7 Unimplemented: Read as '0'
bit 6 CMIF: Comparator Interrupt Flag bit
1 = Comparator input has changed
0 = Comparator input has not changed
bit 5-0 Unimplemented: Read as '0'
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC16C62X
DS30235J-page 22 2003 Microchip Technology Inc.
4.2.2.6 PCON Register
The PCON register contains flag bits to differentiate
between a Power-on Reset, an external MCLR Reset,
WDT Reset or a Brown-out Reset.
REGISTER 4-6: PCON REGISTER (ADDRESS 8Eh)
Note: BOR is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent RESETS to see if BOR is
cleared, indicating a brown-out has
occurred. The BOR STATUS bit is a "don't
care" and is not necessarily predictable if
the brown-out circuit is disabled (by
programming BODEN bit in the
Configuration word).
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
—PORBOR
bit 7 bit 0
bit 7-2 Unimplemented: Read as '0'
bit 1 POR: Power-on Reset STATUS bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset STATUS bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2003 Microchip Technology Inc. DS30235J-page 23
PIC16C62X
4.3 PCL and PCLATH
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not
directly readable or writable and comes from PCLATH.
On any RESET, the PC is cleared. Figure 4-8 shows
the two situations for the loading of the PC. The upper
example in the figure shows how the PC is loaded on a
write to PCL (PCLATH<4:0> PCH). The lower
example in the figure shows how the PC is loaded
during a CALL or GOTO instruction (PCLATH<4:3>
PCH).
FIGURE 4-8: LOADING OF PC IN
DIFFERENT SITUATIONS
4.3.1 COMPUTED GOTO
A computed GOTO is accomplished by adding an
offset to the program counter (ADDWF PCL). When
doing a table read using a computed GOTO method,
care should be exercised if the table location crosses a
PCL memory boundary (each 256 byte block). Refer to
the application note, “Implementing a Table Read"
(AN556).
4.3.2 STACK
The PIC16C62X family has an 8-level deep x 13-bit
wide hardware stack (Figure 4-2 and Figure 4-3). The
stack space is not part of either program or data space
and the stack pointer is not readable or writable. The
PC is PUSHed onto the stack when a CALL instruction
is executed or an interrupt causes a branch. The stack
is POPed in the event of a RETURN, RETLW or a
RETFIE instruction execution. PCLATH is not affected
by a PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
PC
12 8 7 0
5PCLATH<4:0>
PCLATH
Instruction with
ALU result
GOTO,CALL
Opcode <10:0>
8
PC
12 11 10 0
11
PCLATH<4:3>
PCH PCL
87
2
PCLATH
PCH PCL
PCL as
Destination
Note 1: There are no STATUS bits to indicate
stack overflow or stack underflow
conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an
interrupt address.