ICS9DB102
IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 852 REV P 05/24/12
Two Output Differential Buffer for PCIe Gen1 & Gen2
DATASHEET
1
SPREAD
COMPATIBLE
PLL
CONTROL
LOGIC
SMBDAT
SMBCLK
CLK_INT
CLK_INC
PLL_BW
IREF
PCIEX0
PCIEX1
CLKREQ1#
CLKREQ0#
Description
Output Features
The ICS9DB102 zero-delay buffer supports PCI Express
clocking requirements. The ICS9DB102 is driven by a differential
SRC output pair from an ICS CK410/CK505-compliant main
clock. It attenuates jitter on the input clock and has a selectable
PLL Band Width to maximize performance in systems with or
without Spread-Spectrum clocking.
• 2 - 0.7V current mode differential output pairs (HCSL)
Functional Block Diagram
Key Specifications
• Cycle-to-cycle jitter < 35ps
• Output-to-output skew < 25ps
Features/Benefits
• CLKREQ# pin for outputs 1 and 4/output enable for Express
Card applications
• PLL or bypass mode/PLL can dejitter incoming clock
• Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL’s
• Spread Spectrum Compatible/tracks spreading input clock
for low EMI
• SMBus Interface/unused outputs can be disabled
• Industrial temperature range available
IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 852 REV P 05/24/12
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
2
Pin Configuration
20-pin SSOP & TSSOP
VDD GND
5,9,12,16 6,15 PCI Express Outputs
96 SMBUS
20 19 IREF
20 19 Analog VDD & GND for PLL core
Description
Pin Number
Power Groups
Pin Description
PLL_BW 1 20 VDDA
CLK_INT 2 19 GNDA
CLK_INC 3 18 IREF
vCLKREQ0# 4 17 vCLKREQ1#
VDD 5 16 VDD
GND 6 15 GND
PCIEXT0 7 14 PCIEXT1
PCIEXC0 8 13 PCIEXC1
VDD 9 12 VDD
SMBDAT 10 11 SMBCLK
ICS9DB102
Note: Pins preceeded by ' v ' have internal
120K ohm pull down resistors
PIN # PIN NAME PIN TYPE DESCRIPTION
1 PLL_BW IN 3.3V input for se lecting PLL Band Width
0 = low, 1= hi
g
h
2
CLK_INT IN True In
p
ut for differential reference clock.
3 CLK_INC IN Complementary Input for differential reference clock.
4 v CLKR EQ0 # IN Output enable for PCI Express output pair 0.
0 = enabled, 1 =disabled
5
VDD PWR Power su
pp
l
y
, nominal 3.3V
6
GND PWR Ground
p
in.
7 PCIEXT0 OUT True clock of differential PCI_Ex
p
ress
p
air.
8 PCIEXC0 OUT Complementary clock of differential PCI_Express pair.
9 VDD PWR Power supply, nominal 3.3V
10 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant
11 SMBC LK IN C lock
p
in of SMBUS circuitr
y
, 5V tolerant
12 VDD PWR Power su
pp
l
y
, nominal 3.3V
13 PCIEXC1 OUT Com
lementar
clock of differential PCI_Ex
ress
air.
14 PCIEXT1 OUT True clock of differential PCI_Express pair.
15 GND PWR Ground pin.
16 VDD PWR Power supply, nominal 3.3V
17 v CLKR EQ1 # IN Output enable for PCI Express output pair 1.
0 = enabled, 1 =disabled
18 IR EF OU T
This pin establishes the reference for the differential current-mode
output pairs. It requires a fixed precision resistor to ground. 475ohm is
the standard value for 100ohm differential impedance. Other
im
p
edanc es r e
q
uire different values. See data sheet.
19 GNDA PWR Ground pin for the PLL core.
20 VDDA PWR 3.3V power for the PLL core.
Pins preceeded by ' v ' have internal 120K ohm pull down resistors
Note:
IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 852 REV P 05/24/12
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
3
Absolute Max
Symbol Parameter Min Max Units
VDDA 3.3V Core Supply Voltage VDD + 0.5V V
VDD 3.3V Output Supply Voltage GND - 0.5 VDD + 0.5V V
Ts Storage Temperature -65 150 °C
Tcase Case Temperature 115 °C
ESD prot
Input ESD protection
human body model 2000 V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = -40 - 85°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input High Voltage VIH 3.3 V +/-5% 2 VDD + 0.3 V 1
Input Low Voltage VIL 3.3 V +/-5% VSS - 0.3 0.8 V 1
Input High Current IIH VIN = VD
D
-5 5 uA 1
IIL1
VIN = 0 V; Inputs with no pull-
up resistors -5 uA 1
IIL2
VIN = 0 V; Inputs with pull-up
resistors -200 uA 1
Full Active, CL = Full load; 75 100 mA 1
all differential pairs tri-stated 27 50 mA 1
Input Frequency3FiVD
D
= 3.3 V 99 100 101 MHz 1
Pin Inductance1L
p
in 7nH1
CIN Logic Inputs 5 pF 1
COUT Output pin capacitance 4.5 pF 1
Clk Stabilization1,2 TSTAB
From VDD Power-Up to 1st
clock 1.8 ms 1
Modulation Frequency Triangular Modulation 30 33 kHz 1
Spread Spectrum Modulation
Frequency fMOD Lexmark Modulation 25 45 KHz 1
OE# Latency tLATOE#
DIF start after OE# assertion
DIF stop after OE#
deassertion
1 3 cycles 1,2
PLL Bandwidth when
PLL_BW=0 400 KHz 1
PLL Bandwidth when
PLL_BW=1 1.2 MHz 1
SMBus Voltage VD
D
2.7 5.5 V 1
Low-level Output Voltage VOLSMBUS @ IPULLUP 0.4 V 1
Current sinking at VOL = 0.4 V IPULLUP SMBus SDATA pin 4 mA 1
SCLK/SDATA
Clock/Data Rise Time TRI2C (Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA
Clock/Data Fall Time TFI2C (Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
1Guaranteed by design and characterization, not 100% tested in production.
2Time from deassertion until outputs are >200mV
PLL Bandwidth BW
Input Low Current
Input Capacitance1
Operating Supply Current IDD3. 3OP
IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 852 REV P 05/24/12
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
4
Electrical Characteristics - PCIEX 0.7V Current Mode Differential Pair
TA = Tambient; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, IREF = 475Ω
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Current Source Output
Impedance Zo VO = Vx3000 Ω1
Voltage High VHigh 660 850 1,3
Voltage Low VLow -150 150 1,3
Max Volta
g
e Vovs 1150 1,3
Min Voltage Vuds -300 1,3
Crossing Voltage (abs) Vcross(abs) 250 350 550 mV 1,3
Crossing Voltage (var) d-Vcross Variation of crossing over all
edges 12 140 mV 1,3
Long Accuracy ppm see Tperiod min-max values 0 ppm 1,2
100.00MHz nominal 9.9970 10.0030 ns 2
100.00MHz spread 9.9970 10.0533 ns 2
Absolute min period Tabsmin 100.00MHz nominal/spread 9.8720 ns 1,2
Rise Time trVOL = 0.175V, VOH = 0.525V 175 700 ps 1
Fall Time tfVOH = 0.525V VOL = 0.175V 175 700 ps 1
Rise Time Variation d-tr30 125 ps 1
Fall Time Variation d-tf30 125 ps 1
t
p
dPLL Mode. 0 150 ps 1
t
p
db
yp
Bypass mode 3.7 4.2 ns 1
Duty Cycle dt3
Measurement from differential
wavefrom 45 55 % 1
Output-to-Output Skew tsk3 VT = 50% 25 ps 1
tjcyc-cyc
PLL mode. Measurement from
differential wavefrom 35 ps 1
tjcyc-cycbyp Additve Jitter in Bypass Mode 30 ps 1
1Guaranteed b
y
desi
g
n, not 100% tested in production. .
3IRE
F
= VDD/(3xR
R
). For R
R
= 475Ω (1%), IRE
F
= 2.32mA. IOH = 6 x IRE
F
and VOH = 0.7V @ ZO=50Ω.
2 The 9DB102 does not add a ppm error to the input clock
Input to Output Delay
Jitter, Cycle to cycle
mV
Measurement on single ended
signal using absolute value. mV
Average period Tperiod
Statistical measurement on
single ended signal using
IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 852 REV P 05/24/12
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
5
Electrical Characteristics - PLL Parameters
TA = Tambient; Supply Voltage VDD = 3.3 V +/-5%
Grou
p
Parameter Descri
p
tion Min T
yp
Max Units Notes
PLL Jitter Peaking jpeak-hibw (PLL_BW = 1) 0 1 2.5 dB 1,4
PLL Jitter Peaking jpeak-lobw (PLL_BW = 0) 0 1 2 dB 1,4
PLL Bandwidth pllHI BW (PLL_BW = 1) 2 2.5 3 MHz 1,5
PLL Bandwidth pllLOB
W
(PLL_BW = 0) 0.4 0.5 1 MHz 1,5
PCIe Gen 1 phase jitter
(1.5 - 22 MHz) 40 108 ps 1,2,3
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz
(PLL_BW=1)
2.7 3.1 ps rms 1,2,3
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz
(PLL_BW=0)
2.2 3.1 ps rms 1,2,3
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Lo-Band <1.5MHz 1.3 3 ps rms 1,2,3
NOTES:
1. Guaranteed by design and characterization, not 100% tested in production.
2. See http://www.pcisig.com for complete specs
3. Device driven by 932S421BGLF or equivalent
4. Measured as maximum pass band gain. At frequencies w ithin the loop BW, highest point of magnification is called PLL jitter peaking.
5. Measured at 3 db dow n or half pow er point.
Jitter, Phase tjphasePLL
IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 852 REV P 05/24/12
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
6
Common Recommendations for Differential Routing Dimension or Value Unit Figure
L1 length, route as non-coupled 50ohm trace 0.5 max inch 1
L2 length, route as non-coupled 50ohm trace 0.2 max inch 1
L3 length, route as non-coupled 50ohm trace 0.2 max inch 1
Rs 33 ohm 1
Rt 49.9 ohm 1
Down Device Differential Routing
L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max inch 1
L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch 1
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max inch 2
L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch 2
S R C Refer en c e Cloc k
HCSL Output Buffer
L1
L1'
Rs
L2
L2'
Rs
L4'
L4
L3L3'
Rt Rt PCI Express
Down Device
REF_CLK Input
Figure 1: Down Device Routing
HCSL Output Buffer
L1
L1'
Rs
L2
L2'
Rs
L4'
L4
L3L3'
Rt Rt PCI Express
Add-in Board
REF_CLK Input
Figure 2: PCI Express Connector Routing
IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 852 REV P 05/24/12
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
7
Vdiff Vp-p Vcm R1 R2 R3 R4 Note
0.45v 0.22v 1.08 33 150 100 100
0.58 0.28 0.6 33 78.7 137 100
0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible
0.60 0.3 1.2 33 174 140 100 Standard LVDS
R1a = R1b = R1
R2a = R2b = R2
Al ternative Term i nation for LVDS a nd othe r Com m on Di fferential S i gna l s (fi gure 3)
HCSL Output Buffer
L1
L1'
R1b
L2
L2'
R1a
L4'
L4
L3
R2a R2b Down Device
REF_CLK Input
Figure 3
L3'
R3 R4
Component Value Note
R5a, R5b 8.2K 5%
R6a, R6b 1K 5%
Cc 0.1 µF
Vcm 0.350 volts
Cabl e Conne cted AC Coupl ed Appli ca ti on (fi gure 4)
PCIe Device
REF_CLK Input
Figure 4
R5a
L4'
L4
3.3 Volts
R5b
R6a R6b
Cc
Cc
IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 852 REV P 05/24/12
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
8
General SMBus serial interface information for the ICS9DB102
How to Write:
•Controller (host) sends a start bit.
• Controller (host) sends the write address D4 (h)
• IDT clock will
acknowledge
acknowledge
acknowledge
Byte N through
Byte N + X -1
acknowledge one at a time
How to Read:
(h)
• IDT clock will
acknowledge
acknowledge
(h)
• IDT clock will
acknowledge
Byte N + X -1
Byte 0 through byte X (if X
(h)
was written to byte 8)
.
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
IDT (Sla ve /Re ce ive r)
T
WR
ACK
ACK
ACK
ACK
ACK
PstoP bit
X Byte
Index Bl ock Writ e O perati on
Slave Address D4(h)
Beginning Byte = N
WRite
starT bit
Control l er (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T starT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
Slave Address D5(h)
Index Block Read Operati on
Slave Address D4(h)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
IDT (Slave /Re ceive r)
Con troller (Host)
X Byte
ACK
ACK
IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 852 REV P 05/24/12
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
9
SMBus Table: Device Control Register, READ/WRITE ADDRESS (D4/D5)
Pin # Name Control Function Type 0 1 PWD
Bit 7 SW_EN Enables SMBus
Control RW
Functions
controlled by
SMBus
re
g
isters
Functions
controlled by
device pins
1
Bit 6 RW X
Bit 5 RW X
Bit 4 RW X
Bit 3 RW X
Bit 2 RW X
Bit 1 PLL BW #adjust Selects PLL
Bandwidth RW Low BW High BW 1
Bit 0 PLL Enable Bypasses PLL for
board test RW PLL bypassed
(fan out mode)
PLL enabled
(ZDB mode) 1
SMBus Table: Output Enable Register
Pin # Name Control Function Type 0 1 PWD
Bit 7 RW X
Bit 6 RW X
Bit 5 RW X
Bit 4 RW X
Bit 3 RW X
Bit 2 RW X
Bit 1 RW X
Bit 0 RW X
SMBus Table: Function Select Re
g
iste
r
Pin # Name Control Function Type 0 1 PWD
Bit 7 R
W
X
Bit 6 R
W
X
Bit 5 R
W
X
Bit 4 R
W
X
Bit 3 R
W
X
Bit 2 R
W
X
Bit 1 R
W
X
Bit 0 RW X
SMBus Table: Vendor & Revision ID Register
Pin # Name Control Function Type 0 1 PWD
Bit 7 RID3 R - - 0
Bit 6 RID2 R - - 0
Bit 5 RID1 R - - 0
Bit 4 RID0 R - - 1
Bit 3 VID 3 R - - 0
Bit 2 VID 2 R - - 0
Bit 1 VID 1 R - - 0
Bit 0 VID 0 R - - 1
RESERVED -
-
RESERVED -
RESERVED
-
-
-
-
-
-
-
-
-
Byte 3
-
-
-
-
-
-
Byte 2
RESERVED -
RESERVED -
-
-
-
-
-
-
- RESERVED
-
RESERVED
-
-
Byte 1
-
RESERVED -
-
RESERVED
REVISION ID
VENDOR ID
Byte 0
-
- RESERVED
- RESERVED -
-
-
RESERVED -
RESERVED
RESERVED -
RESERVED -
RESERVED
-
-
-
RESERVED -
RESERVED
-
-
RESERVED -
RESERVED
RESERVED -
-
IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 852 REV P 05/24/12
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
10
SMBus Table: DEVICE ID
Pin # Name Control Function T
yp
e0 1PWD
Bit 7 R 0
Bit 6 R 0
Bit 5 R 0
Bit 4 R 0
Bit 3 R 0
Bit 2 R 1
Bit 1 R 1
Bit 0 R 0
SMBus Table: Byte Count Register
Pin # Name Control
Function Type 0 1 PWD
Bit 7 BC7 RW - - 0
Bit 6 BC6 RW - - 0
Bit 5 BC5 RW - - 0
Bit 4 BC4 R
W
--0
Bit 3 BC3 RW - - 0
Bit 2 BC2 RW - - 1
Bit 1 BC1 R
W
--1
Bit 0 BC0 RW - - 0
-
-
-
-
Byte 5
-
Writing to this
register will
configure how
many bytes will be
read back, default
is 06 = 6 bytes.
-
-
-
-
-
-
-
B
y
te 4
-
-
-
-
-
-
-
-
-
-
Device ID
= 06 Hex
-
-
IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 852 REV P 05/24/12
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
11
MIN MAX MIN MAX
A 1.35 1.75 .053 .069
A1 0.10 0.25 .004 .010
A2 -- 1.50 -- .059
b 0.20 0.30 .008 .012
c 0.18 0.25 .007 .010
D 8.558.75.337.344
E 5.80 6.20 .228 .244
E1 3.80 4.00 .150 .157
e
L 0.40 1.27 .016 .050
N
a 0°8°0°8°
ZD
20-Lead, 150 mil SSOP
(
QSOP
)
1.47 .058
20 20
SYMBOL
In Millimeters In Inches
COMMON DIMENSIONS
0.635 BASIC 0.025 BASIC
COMMON DIMENSIONS
20-Pin SSOP Package Drawing and Dimensions
IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 852 REV P 05/24/12
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
12
INDEX
AREA
INDEX
AREA
12
1 2
N
D
E1 E
α
SEATING
PLANE
SEATING
PLANE
A1
A
A2
e
-C-
- C -
b
c
L
aaa C
MINMAX MINMAX
A -- 1.20 -- .047
A1 0.05 0.15 .002 .006
A2 0.80 1.05 .032 .041
b 0.19 0.30 .007 .012
c 0.09 0.20 .0035 .008
D 6.40 6.60 .252 .260
E
E1 4.30 4.50 .169 .177
e
L 0.45 0.75 .018 .030
N
a 0°8°0°8°
aaa -- 0.10 -- .004
10-0035
0.65 BASIC
Reference Doc.: JEDEC Publication 95, MO-153
20 20
20-Lead, 4.40 mm. Body, 0.65 mm. Pitch TSSOP
6.40 BASIC 0.252 BASIC
0.0256 BASIC
COMMON DIMENSIONS
In Millimeters In Inches
COMMON DIMENSIONS
(173 mil) (25.6 mil)
SYMBOL
20-Pin TSSOP Package Drawing and Dimensions
Orderi ng Informati o n
Part / Orde r Number Shi ppi ng P ackagi ng Packa ge Te m perature
9DB102BFLF Tubes 20-pin SSOP 0 to +70°C
9DB102BFLFT Tape and Reel 20-pin SSOP 0 to +70°C
9DB102BFILF Tubes 20-pin SSOP -40 to +85°C
9DB102BFILFT Tape and Reel 20-pin SSOP -40 to +85°C
9DB102BGLF Tubes 20-pin TSSOP 0 to +70°C
9DB102BGLFT Tape and Reel 20-pin TSSOP 0 to +70°C
9DB102BGILF Tubes 20-pin TSSOP -40 to +85°C
9DB102BGILFT Tape and Reel 20-pin TSSOP -40 to +85°C
"LF" after the packa ge code are the P b-Free configura tion and are RoHS com pli ant.
"B" is the device re vision designator (w ill not corre la te to the data she e t revision).
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
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www.IDT.com
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Phone: 44-1372-363339
Fax: 44-1372-378851
© 2012 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks
are or may be trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
Revision History
Rev. Originator Issue Date Description Page #
F 8/6/2007
1. Added Phase Noise Parameters, Updated input to output delay values.
2. PLL BW moved to PLL parameters table.
3. Added terminations tables. Various
G 12/14/2007 Updated General SMBus Interface Information. 8
H 10/29/2008 Corrected "HCSL" t
y
pos. 1, 6, 7
J 1/15/2010
1. Added I-temp electricals
2. Changed datasheet title
3. Updated Input Frequency parameter
4. Updated orderin
g
information
Various
K RW 4/1/2010 Updated ordering info for Rev B
L DC 9/28/2010 Updated package dimension tables 11, 12
M RDW 1/27/2011 Updated Termination Figure 4. 7
N RDW 4/20/2011
Changed pulldown indicator on CLKREQ# pins to correct pin description of
those pins.
P AT 5/24/2012 Added OE# Latency spec to Common Input/Output Parameters table 3