PCI 6254 Data Book v2.1
2003 PLX Technology, Inc. All rights reserved. 15
1 Register Index
When looking up registers, please also check registers below preceded with “Primary” or “Secondary”.
Arbiter Control Register .............................................................. 49
Non-transparent, Primary ..................................................... 175
Bridge Control Register....................................................... 46, 141
Cache Line Size Register ........................................................... 43
Non-transparent, Primary ..................................................... 138
Capability Identifier ................................................................... 163
Non-transparent, Primary ..... 69, 70, 71, 72, 176, 177, 178, 179
Chip Control Register
Non-transparent, Primary ............................... 48, 153, 154, 174
Class Code Register ................................................................... 43
Non-transparent, Primary ..................................................... 138
Clkrun Register ........................................................................... 64
Device ID Register ...................................................................... 42
Non-transparent, Primary ..................................................... 136
Diagnostic Control Register ........................................................ 49
Non-transparent, Primary ..................................................... 175
Downstream BAR 0 Translation Address
Non-transparent, Primary ..................................................... 171
Downstream BAR 0 Translation Mask
Non-transparent, Primary ..................................................... 172
Downstream BAR 1 Translation Address
Non-transparent, Primary ..................................................... 171
Downstream BAR 2 Translation Address
Non-transparent, Primary ..................................................... 171
Downstream I/O or Memory BAR 0
Non-transparent, Primary ..................................................... 139
Downstream Memory BAR 1
Non-transparent, Primary ..................................................... 139
Downstream Memory BAR 2
Non-transparent, Primary ..................................................... 139
ECP Pointer ................................................................................ 46
Non-transparent, Primary ..................................................... 140
EEPROM Address .............................................................. 59, 152
EEPROM Control.................................................. 58, 59, 151, 152
GPIO Input Data Register ........................................................... 61
Non-transparent, Primary ....................................... 66, 158, 160
Non-transparent, Primary ............................................... 67, 160
GPIO Output Data Register ........................................................ 61
Non-transparent, Primary ....................................... 66, 158, 159
Non-transparent, Primary ............................................... 67, 160
GPIO Output Enable Register..................................................... 61
Non-transparent, Primary ....................................... 66, 158, 159
Non-transparent, Primary ............................................... 67, 160
Header Type Register................................................................. 44
Non-transparent, Primary ..................................................... 139
Hot Swap Register
Non-transparent, Primary ............................................... 71, 178
Hot Swap Switch
Non-transparent, Primary ............................................... 65, 159
I/O Base Address Upper 16 Bits Register................................... 46
I/O Base Register........................................................................ 44
I/O Limit Address Upper 16 Bits Register ................................... 46
I/O Limit Register ........................................................................ 44
Internal Arbiter Control Register ......................................... 57, 150
Interrupt Pin Register .................................................................. 46
Non-transparent, Primary ..................................................... 140
Memory Base Register ......................................................... 45, 65
Memory Limit Register .......................................................... 45, 65
Message Address
Non-transparent, MSI ........................................................... 163
Message Data
Non-transparent, MSI ........................................................... 163
Message Interrupt Status
Non-transparent, Primary ............... 68, 164, 165, 166, 167, 168
Message Upper Address
Non-transparent, MSI............................................................163
Miscellaneous Options ........................................................52, 145
Next Item Pointer.......................................................................163
Non-transparent, Primary....................69, 71, 72, 176, 178, 179
P_SERR_L Event Disable Register ............................................60
Non-transparent, Primary......................................................156
P_SERR_L Status Register ........................................................63
Non-transparent, Primary......................................................157
PMCSR Bridge Support
Non-transparent, Primary................................................70, 177
Power Management Capabilities
Non-transparent, Primary................................................69, 176
Power Management Control/ Status
Non-transparent, Primary................................................70, 176
Power Up Status Register ...................................................66, 160
Prefetchable Memory Base Register...........................................45
Prefetchable Memory Base Register Upper 32 Bits..............45, 65
Prefetchable Memory Limit Register ...........................................45
Prefetchable Memory Limit Register Upper 32 Bits ..............46, 65
Primary Bus Number Register.....................................................44
Primary Command Register ........................................................42
Non-transparent, Primary......................................................136
Primary Flow Through Control Register ..............................50, 143
Primary Latency Timer Register..................................................43
Non-transparent, Primary......................................................139
Primary Side Incremental Prefetch Count ...........................54, 147
Primary Side Maximum Prefetch Count ..............................55, 148
Primary Side Prefetch Line Count .......................................54, 147
Primary Status Register ..............................................................43
Non-transparent, Primary......................................................138
Revision ID Register....................................................................43
Non-transparent, Primary......................................................138
Secondary Bus Number Register................................................44
Secondary Clock Control Register ..............................................62
Non-transparent, Primary......................................................154
Secondary Flow Through Control Register .........................56, 149
Secondary Latency Timer ...........................................................44
Secondary Message Register
Non-transparent, Primary..............................................161, 162
Secondary Side Incremental Prefetch Count ......................55, 148
Secondary Side Maximum Prefetch Count .........................55, 148
Secondary Side Prefetch Line Count ..................................54, 147
Secondary Status Register..........................................................45
Software Register
Non-transparent, Primary......................................................153
Subordinate Bus Number Register..............................................44
Subsystem Vendor ID
Non-transparent, Primary......................................................140
Timeout Control Register ...................................................51, 144
Upstream BAR 0 Translation Address
Non-transparent, Primary......................................................169
Upstream BAR 0 Translation Mask
Non-transparent, Primary......................................................170
Upstream BAR 1 Translation Address
Non-transparent, Primary......................................................169
Upstream BAR 2 Translation Address
Non-transparent, Primary......................................................169
Vendor ID Register......................................................................42
Non-transparent, Primary......................................................136
VPD Data Register
Non-transparent, Primary................................................72, 179
VPD Register
Non-transparent, Primary................................................72, 179