TJA1043 High-speed CAN transceiver Rev. 4 -- 19 January 2015 Product data sheet 1. General description The TJA1043 high-speed CAN transceiver provides an interface between a Controller Area Network (CAN) protocol controller and the physical two-wire CAN bus. The transceiver is designed for high-speed CAN applications in the automotive industry, providing differential transmit and receive capability to (a microcontroller with) a CAN protocol controller. The TJA1043 belongs to the third generation of high-speed CAN transceivers from NXP Semiconductors, offering significant improvements over first- and second-generation devices such as the TJA1041A. It offers improved ElectroMagnetic Compatibility (EMC) and ElectroMagnetic Discharge (ESD) performance, very low power consumption, and passive behavior when the supply voltage is turned off. Advanced features include: * Low-power management controls the power supply throughout the node while supporting local and remote wake-up with wake-up source recognition * Several protection and diagnostic functions including bus line short-circuit detection and battery connection detection * Can be interfaced directly to microcontrollers with supply voltages from 3 V to 5 V The TJA1043 implements the CAN physical layer as defined in the current ISO11898 standard (ISO11898-2:2003, ISO11898-5:2007). Pending the release of the updated version of ISO11898-2 including CAN FD, additional timing parameters defining loop delay symmetry are specified. This implementation enables reliable communication in the CAN FD fast phase at data rates up to 2 Mbit/s. These features make the TJA1043 the ideal choice for high speed CAN networks containing nodes that need to be available all times, even when the internal VIO and VCC supplies are switched off. 2. Features and benefits 2.1 General Fully ISO 11898-2:2003 and ISO 11898-5:2007 compliant Loop delay symmetry timing enables reliable communication at data rates up to 2 Mbit/s in the CAN FD fast phase Suitable for 12 V and 24 V systems Low ElectroMagnetic Emission (EME) and high ElectroMagnetic Immunity (EMI) VIO input allows for direct interfacing with 3 V and 5 V microcontrollers SPLIT voltage output for stabilizing the recessive bus level Listen-only mode for node diagnosis and failure containment TJA1043 NXP Semiconductors High-speed CAN transceiver Available in SO14 and HVSON14 packages Leadless HVSON14 package (3.0 mm 4.5 mm) with improved Automated Optical Inspection (AOI) capability AEC-Q100 qualified Dark green product (halogen free and Restriction of Hazardous Substances (RoHS) compliant) 2.2 Low-power management Very low current Standby and Sleep modes, with local and remote wake-up Capability to power down the entire node while supporting local, remote and host wake-up Wake-up source recognition Transceiver disengages from the bus (zero load) when VBAT absent Functional behavior predictable under all supply conditions 2.3 Protection and diagnosis (detection and signalling) High ESD handling capability on the bus pins Bus pins and VBAT protected against transients in automotive environments Transmit Data (TXD) dominant time-out function with diagnosis TXD-to-RXD short-circuit handler with diagnosis Thermal protection with diagnosis Undervoltage detection and recovery on pins VCC, VIO and VBAT Bus line short-circuit diagnosis Bus dominant clamping diagnosis Cold start diagnosis (first battery connection) 3. Quick reference data Table 1. Quick reference data Symbol Parameter VCC Min Typ Max Unit supply voltage 4.5 - 5.5 V VIO supply voltage on pin VIO 2.8 - 5.5 V Vuvd(VCC) undervoltage detection voltage on pin VCC 3 3.5 4.3 V Vuvd(VIO) undervoltage detection voltage on pin VIO VBAT or VCC > 4.5 V 0.8 1.8 2.5 V ICC supply current Normal mode; bus dominant 30 48 65 mA Normal or Listen-only mode; bus recessive 3 6 9 mA Standby or Sleep mode 0 0.75 2 A IIO VESD Conditions supply current on pin VIO electrostatic discharge voltage TJA1043 Product data sheet Normal mode; VTXD = 0 V (dominant) - 150 500 A Normal or Listen-only mode; VTXD = VIO (recessive) 0 1 4 A Standby or Sleep mode 0 1 4 A IEC 61000-4-2 at pins CANH and CANL 8 - +8 kV All information provided in this document is subject to legal disclaimers. Rev. 4 -- 19 January 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 2 of 29 TJA1043 NXP Semiconductors High-speed CAN transceiver Table 1. Quick reference data ...continued Symbol Parameter Min Typ Max Unit VCANH voltage on pin CANH Conditions 58 - +58 V VCANL voltage on pin CANL 58 - +58 V Tvj virtual junction temperature 40 - +150 C 4. Ordering information Table 2. Ordering information Type number Package Name Description Version TJA1043T SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 TJA1043TK HVSON14 plastic, thermal enhanced very thin small outline package; no leads; 14 terminals; body 3 4.5 0.85 mm TJA1043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 19 January 2015 SOT1086-2 (c) NXP Semiconductors N.V. 2015. All rights reserved. 3 of 29 TJA1043 NXP Semiconductors High-speed CAN transceiver 5. Block diagram VIO VCC 5 3 VBAT 10 VCC TJA1043 TEMPERATURE PROTECTION 13 VIO TXD 1 TIME-OUT SLOPE CONTROL + DRIVER 12 CANH CANL VBAT WAKE ERR_N STB_N 9 8 14 11 MODE CONTROL + WAKE-UP CONTROL + ERROR DETECTION SPLIT SPLIT VBAT 7 EN RXD INH 6 4 MUX + DRIVER WAKE-UP FILTER 2 GND Fig 1. 015aaa061 Block diagram TJA1043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 19 January 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 4 of 29 TJA1043 NXP Semiconductors High-speed CAN transceiver 6. Pinning information 6.1 Pinning terminal 1 index area TXD 1 14 STB_N TXD 1 14 STB_N GND 2 13 CANH GND 2 13 CANH VCC 3 12 CANL VCC 3 12 CANL RXD 4 11 SPLIT RXD 4 VIO 5 10 VBAT VIO 5 10 VBAT EN 6 9 WAKE EN 6 9 WAKE INH 7 8 ERR_N INH 7 8 ERR_N TJA1043T TJA1043TK 015aaa376 015aaa062 Fig 2. 11 SPLIT Pin configuration diagram: SO14 Fig 3. Pin configuration diagram: HVSON14 6.2 Pin description Table 3. Pin description Symbol Pin Description TXD 1 transmit data input GND[1] 2 ground supply VCC 3 transceiver supply voltage RXD 4 receive data output; reads out data from the bus lines VIO 5 supply voltage for I/O level adaptor EN 6 enable control input INH 7 inhibit output for switching external voltage regulators ERR_N 8 error and power-on indication output (active LOW) WAKE 9 local wake-up input VBAT 10 battery supply voltage SPLIT 11 common-mode stabilization output CANL 12 LOW-level CAN bus line CANH 13 HIGH-level CAN bus line STB_N 14 standby control input (active LOW) [1] For enhanced thermal and electrical performance, the exposed center pad of the HVSON14 package should be soldered to board ground. 7. Functional description The TJA1043 is a stand-alone high-speed CAN transceiver with a number of operating modes, fail-safe features and diagnostic features that offer enhanced system reliability and advanced power management. The transceiver combines the functionality of the TJA1043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 19 January 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 5 of 29 TJA1043 NXP Semiconductors High-speed CAN transceiver TJA1041A with improved EMC and ESD capability and quiescent current performance. Improved slope control and high DC handling capability on the bus pins provide additional application flexibility. 7.1 Operating modes The TJA1043 supports five operating modes. Control pins STB_N and EN are used to select the operating mode. Switching between modes allows access to a number of diagnostics flags via pin ERR_N. Table 4 describes how to switch between modes. Figure 4 illustrates the mode transitions when VCC, VIO and VBAT are valid. Table 4. Operating mode selection Internal flags UVNOM[1] Control pins UVBAT Wake[2] STB_N[3] Operating mode Pin INH EN From Normal, Listen-only, Standby and Go-to-Sleep modes set X X X X Sleep mode floating cleared set X HIGH X Standby mode HIGH cleared X set LOW X Standby mode HIGH cleared X cleared LOW LOW Standby mode HIGH cleared X cleared LOW HIGH Go-to-Sleep mode[4] HIGH[4] cleared cleared X HIGH LOW Listen-only mode HIGH cleared cleared X HIGH HIGH Normal mode HIGH From Sleep mode TJA1043 Product data sheet set X X X X Sleep mode floating cleared set X HIGH X Standby mode HIGH cleared X set LOW X Standby mode HIGH cleared X cleared LOW X Sleep mode floating cleared cleared X HIGH LOW Listen-only mode HIGH cleared cleared X HIGH HIGH Normal mode HIGH [1] Setting the UVNOM flag will clear the WAKE flag. [2] Setting the Wake flag will clear the UVNOM flag. [3] A LOW-to-HIGH transition on pin STB_N will clear the UVNOM flag [4] After the minimum hold time, in Go-to-Sleep mode, th(min), the transceiver will enter Sleep mode and pin INH will be set floating. All information provided in this document is subject to legal disclaimers. Rev. 4 -- 19 January 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 6 of 29 TJA1043 NXP Semiconductors High-speed CAN transceiver STB_N = H and EN = H STB_N = H and EN = L LISTENONLY MODE STB_N = H and EN = H STB_N = H and EN = L STB_N = H and EN = L NORMAL MODE STB_N = H and EN = H STB_N = L and (EN = L or Wake flag set) STB_N = L and EN = H and Wake flag cleared STB_N = L and EN = H STB_N = L and EN = L STB_N = L and EN = H and Wake flag cleared STANDBY MODE GO-TO-SLEEP MODE STB_N = L and (EN = L or Wake flag set) STB_N = H and EN = L Wake flag cleared and t > th(min) STB_N = L and Wake flag set STB_N = H and EN = H SLEEP MODE LEGEND: = H, = L Fig 4. logical state of pin 015aaa063 Mode transitions when valid VCC, VIO and VBAT voltages are present 7.1.1 Normal mode In Normal mode, the transceiver can transmit and receive data via the bus lines CANH and CANL (see Figure 1 for the block diagram). The differential receiver converts the analog data on the bus lines into digital data which is output to pin RXD. The slopes of the output signals on the bus lines are controlled internally and are optimized in a way that guarantees the lowest possible EME. The bus pins are biased to 0.5VCC (via Ri). Pin INH is active, so voltage regulators controlled by pin INH (see Figure 8) will be active too. 7.1.2 Listen-only mode In Listen-only mode, the transceiver's transmitter is disabled, effectively providing a transceiver listen-only feature. The receiver will still convert the analog bus signal on pins CANH and CANL into digital data, available for output on pin RXD. As in Normal mode, the bus pins are biased at 0.5VCC and pin INH remains active. TJA1043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 19 January 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 7 of 29 TJA1043 NXP Semiconductors High-speed CAN transceiver 7.1.3 Standby mode Standby mode is the TJA1043's first-level power saving mode, offering reduced current consumption. In Standby mode, the transceiver is unable to transmit or receive data and the low-power receiver is activated to monitor bus activity. The bus pins are biased at ground level (via Ri). Pin INH is still active, so voltage regulators controlled by this pin will also be active. Pins RXD and ERR_N will reflect any active wake-up requests (provided that VIO and VBAT are present). 7.1.4 Go-to-Sleep mode Go-to-Sleep mode is the controlled route for entering Sleep mode. In Go-to-Sleep mode, the transceiver behaves as in Standby mode, with the addition that a go-to-sleep command is issued to the transceiver. The transceiver will remain in Go-to-Sleep mode for the minimum hold time (th(min)) before entering Sleep mode. The transceiver will not enter Sleep mode if the state of pin STB_N or pin EN is changed or if the Wake flag is set before th(min) has elapsed. 7.1.5 Sleep mode Sleep mode is the TJA1043's second-level power saving mode. Sleep mode is entered via Go-to-Sleep mode, and also when the undervoltage detection time on either VCC or VIO elapses before the relevant voltage level has recovered. In Sleep mode, the transceiver behaves as described for Standby mode, with the exception that pin INH is set floating. Voltage regulators controlled by this pin will be switched off, and the current into pin VBAT will be reduced to a minimum. Pins STB_N, EN and the Wake flag can be used to wake up a node from Sleep mode (see Table 4). 7.2 Internal flags The TJA1043 makes use of seven internal flags for its fail-safe fallback mode control and system diagnosis support. Five of these flags can be polled by the controller via pin ERR_N. Which flag is available on pin ERR_N at any time depends on the active operating mode and on a number of other conditions. Table 5 describes how to access these flags. Table 5. TJA1043 Product data sheet Accessing internal flags via pin ERR_N Internal flag Flag is available on pin ERR_N[1] Flag is cleared UVNOM no by setting the Pwon or Wake flags, by a LOW-to-HIGH transition on STB_N or when both VIO and VBAT have recovered. UVBAT no when VBAT has recovered Pwon in Listen-only mode (coming from Standby on entering Normal mode mode, Go-to-Sleep mode, or Sleep mode) Wake in Standby mode, Go-to-Sleep mode, and Sleep mode (provided that VIO and VBAT are present) All information provided in this document is subject to legal disclaimers. Rev. 4 -- 19 January 2015 on entering Normal mode or by setting the UVNOM flag (c) NXP Semiconductors N.V. 2015. All rights reserved. 8 of 29 TJA1043 NXP Semiconductors High-speed CAN transceiver Table 5. Accessing internal flags via pin ERR_N ...continued Internal flag Flag is available on pin ERR_N[1] Wake-up source in Normal mode (before the fourth on leaving Normal mode dominant-to-recessive edge on pin TXD[2]) Bus failure on re-entering Normal mode or by in Normal mode (after the fourth dominant-to-recessive edge on pin TXD[2]) setting the Pwon flag Local failure in Listen-only mode (coming from Normal mode) Flag is cleared on entering Normal mode or when RXD is dominant while TXD is recessive (provided that all local failures are resolved) or by setting the Pwon flag [1] Pin ERR_N is an active-LOW output, so a LOW-level indicates a set flag and a HIGH-level indicates a cleared flag. Allow pin ERR_N to stabilize for at least 8 s after changing operating modes. [2] Allow for a TXD dominant time of at least 4 s per dominant-recessive cycle. 7.2.1 UVNOM flag UVNOM is the VCC and VIO undervoltage detection flag. The flag is set when the voltage on pin VCC drops below the VCC undervoltage detection voltage, Vuvd(VCC), for longer than the undervoltage detection time, tdet(uv), or when the voltage on pin VIO drops below Vuvd(VIO) for longer than tdet(uv). When the UVNOM flag is set, the transceiver enters Sleep mode to save power and to ensure the bus is not disturbed. In Sleep mode the voltage regulators connected to pin INH are disabled, avoiding any extra power consumption that might be generated as a result of a short-circuit condition. Any wake-up request, setting the Pwon flag or a LOW-to-HIGH transition on STB_N will clear UVNOM and the timers, allowing the voltage regulators to be reactivated (at least until UVNOM is set again). UVNOM will also be cleared if both VCC and VIO recover for longer than the undervoltage recovery time, trec(uv). The transceiver will then switch to the operating mode indicated by the logic levels on pins STB_N and EN (see Table 4). 7.2.2 UVBAT flag UVBAT is the VBAT undervoltage detection flag. This flag is set when the voltage on pin VBAT drops below Vuvd(VBAT). When UVBAT is set, the transceiver will try to enter Standby mode to save power and will disengage from the bus (zero load). UVBAT is cleared when the voltage on pin VBAT recovers. The transceiver will then switch to the operating mode indicated by the logic levels on pins STB_N and EN (see Table 4). 7.2.3 Pwon flag Pwon is the VBAT power-on flag. This flag is set when the voltage on pin VBAT recovers after previously dropping below Vuvd(VBAT) (usually because the battery was disconnected). Setting the Pwon flag clears the UVNOM flag and timers. The Wake and Wake-up source flags are set to ensure consistent system power-up under all supply conditions. In Listen-only mode the Pwon flag can be polled via pin ERR_N (see Table 5). The flag is cleared when the transceiver enters Normal mode. 7.2.4 Wake flag The Wake flag is set when the transceiver detects a local or remote wake-up request. A local wake-up request is detected when the logic level on pin WAKE changes, and the new level remains stable for at least twake. A remote wake-up request is triggered by two bus dominant states of at least twake(busdom), with the first dominant state followed by a TJA1043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 19 January 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 9 of 29 TJA1043 NXP Semiconductors High-speed CAN transceiver recessive state of at least twake(busrec) (provided the complete dominant-recessive-dominant pattern is completed within tto(wake)bus). The Wake flag can be set in Standby mode, Go-to-Sleep mode or Sleep mode. Setting the Wake flag clears the UVNOM flag and timers. Once set, the Wake flag status is immediately available on pins ERR_N and RXD (provided VIO and VBAT are present). This flag is also set at power-on and cleared when the UVNOM flag is set or the transceiver enters Normal mode. 7.2.5 Wake-up source flag Wake-up source recognition is provided via the Wake-up source flag, which is set when the Wake flag is set by a local wake-up request via the WAKE pin. The Wake-up source flag can be polled via the ERR_N pin in Normal mode (see Table 5). This flag is also set at power-on and cleared when the transceiver leaves Normal mode. 7.2.6 Bus failure flag The Bus failure flag is set if the transceiver detects a bus line short-circuit condition to VBAT, VCC or GND during four consecutive dominant-recessive cycles on pin TXD, while trying to drive the bus lines dominant. The Bus failure flag can be polled via the ERR_N pin in Normal mode (see Table 5). This flag is cleared at power-on or when the transceiver re-enters Normal mode. 7.2.7 Local failure flag In Normal and Listen-only modes, the transceiver can distinguish four different local failure events, any of which will cause the Local failure flag to be set. The four local failure events are: TXD dominant clamping, TXD-to-RXD short circuit, bus dominant clamping and an overtemperature event. The nature and detection of these local failures is described in Section 7.3. The Local failure flag can be polled via the ERR_N pin in Listen-only mode (see Table 5). This flag is cleared at power-on, when entering Normal mode or when RXD is dominant while TXD is recessive, provided that all local failures have been resolved. 7.3 Local failures The TJA1043 can detect four different local failure conditions. Any of these failures will set the Local failure flag, and in most cases the transmitter of the transceiver will be disabled. 7.3.1 TXD dominant clamping detection A permanent LOW level on pin TXD (due to a hardware or software application failure) would drive the CAN bus into a permanent dominant state, blocking all network communications. The TXD dominant time-out function prevents such a network lock-up by disabling the transmitter if pin TXD remains LOW for longer than the TXD dominant time-out time tto(dom)TXD. The tto(dom)TXD timer defines the minimum possible bit rate of 40 kbit/s. The transmitter remains disabled until the Local failure flag has been cleared. 7.3.2 TXD-to-RXD short-circuit detection A short-circuit between pins RXD and TXD would lock the bus in a permanent dominant state once it had been driven dominant, because the low-side driver of RXD is typically stronger than the high-side driver of the controller connected to TXD. TXD-to-RXD short-circuit detection prevents such a network lock-up by disabling the transmitter. The transmitter remains disabled until the Local failure flag has been cleared. TJA1043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 19 January 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 10 of 29 TJA1043 NXP Semiconductors High-speed CAN transceiver 7.3.3 Bus dominant clamping detection A CAN bus short circuit (to VBAT, VCC or GND) or a failure in one of the other network nodes could result in a differential voltage on the bus high enough to represent a bus dominant state. Because a node will not start transmission if the bus is dominant, the normal bus failure detection will not detect this failure, but the bus dominant clamping detection will. The Local failure flag is set if the dominant state on the bus persists for longer than tto(dom)bus. By checking this flag, the controller can determine if a clamped bus is blocking network communications. There is no need to disable the transmitter. Note that the Local failure flag does not retain a bus dominant clamping failure, and is released as soon as the bus returns to recessive state. 7.3.4 Overtemperature detection If the junction temperature becomes excessive, the transmitter will shut down in time to protect the output drivers from overheating without compromising the maximum operating temperature. The transmitter will remain disabled until the Local failure flag has been cleared. 7.4 SPLIT pin Using the SPLIT pin on the TJA1043 in conjunction with a split termination network (see Figure 5 and Figure 8) can help to stabilize the recessive voltage level on the bus. This will reduce EME in networks with DC leakage to ground (e.g. from deactivated nodes with poor bus leakage performance). In Normal and Listen-only modes, pin SPLIT delivers a DC output voltage of 0.5VCC. In Standby, Go-to-Sleep and Sleep modes, pin SPLIT is floating. VCC TJA1043 CANH VSPLIT = 0.5VCC in normal mode and pwon/listen-only mode; otherwise floating 60 R VSPLIT SPLIT 60 R CANL GND 015aaa064 Fig 5. Stabilization circuit and application 7.5 VIO supply pin Pin VIO should be connected to the microcontroller supply voltage (see Figure 8). This will cause the signal levels of pins TXD, RXD, STB_N, EN and ERR_N to be adjusted to the I/O levels of the microcontroller, facilitating direct interfacing without the need for glue logic. TJA1043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 19 January 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 11 of 29 TJA1043 NXP Semiconductors High-speed CAN transceiver 7.6 WAKE pin A local wake-up event is triggered by a LOW-to-HIGH or HIGH-to-LOW transition on the WAKE pin, allowing for maximum flexibility when designing a local wake-up circuit.To minimize current consumption, the internal bias voltage will follow the logic state on the pin after a delay of twake. A HIGH level on pin WAKE is followed by an internal pull-up to VBAT. A LOW level on pin WAKE is followed by an internal pull-down towards GND. In applications that don't make use of the local wake-up facility, it is recommended that the WAKE pin be connected to VBAT or GND to ensure optimal EMI performance. TJA1043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 19 January 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 12 of 29 TJA1043 NXP Semiconductors High-speed CAN transceiver 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VBAT battery supply voltage Vx voltage on pin x IWAKE Vtrt VESD Conditions Min Max Unit 0.3 +58 V load dump - 58 V on pins CANH, CANL and SPLIT 58 +58 V on pins INH and WAKE 0.3 +58 V on pins VCC, VIO, TXD, RXD, STB_N, EN, ERR_N 0.3 +7 V - 15 mA 200 +200 V 8 +8 kV 8 +8 kV 4 +4 kV 300 +300 V at corner pins 750 +750 V at any pin 500 +500 V 40 +150 C 55 +150 C current on pin WAKE transient voltage on pins CANH, CANL, SPLIT and VBAT [1] electrostatic discharge voltage IEC 61000-4-2 (150 pF, 330 ) [2] at pins CANH and CANL Human Body Model (HBM); 100 pF, 1.5 k [3] at pins CANH and CANL at any other pin Machine Model (MM); 200 pF, 0.75 H, 10 [4] at any pin Charged Device Model (CDM); field Induced charge; 4 pF Tvj virtual junction temperature Tstg storage temperature [5] [6] [1] Verified by an external test house to ensure pins CANH, CANL, SPLIT and VBAT can withstand ISO 7637 part 3 automotive transient test pulses 1, 2a, 3a and 3b. [2] According to IEC TS 62228 (2007), Section 4.3; DIN EN 61000-4-2. [3] According to AEC-Q100-002. [4] According to AEC-Q100-003. [5] According to AEC-Q100-011 Rev-C1. The classification level is C4B. [6] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj = Tamb + P Rth(vj-a), where Rth(vj-a) is a fixed value to be used for the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb). 9. Thermal characteristics Table 7. Thermal characteristics Value determined for free convection conditions on a JEDEC 2S2P board. Symbol Parameter Conditions Typ Unit Rth(vj-a) thermal resistance from virtual junction to ambient SO14 package; in free air 68 K/W HVSON14 package; in free air 44 K/W TJA1043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 19 January 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 13 of 29 TJA1043 NXP Semiconductors High-speed CAN transceiver 10. Static characteristics Table 8. Static characteristics VCC = 4.5 V to 5.5 V; VIO = 2.8 V to VCC; VBAT = 4.5 V to 40 V; RL = 60 ; Tvj = 40 C to +150 C; unless otherwise specified; all voltages are defined with respect to ground; positive currents flow into the device [1]. Symbol Parameter Conditions Min Typ Max Unit 4.5 - 5.5 V Supply pin VCC VCC supply voltage Vuvd(VCC) undervoltage detection voltage on pin VCC VBAT > 4.5 V 3 3.5 4.3 V ICC supply current Normal mode; VTXD = 0 V (dominant) 30 48 65 mA Normal or Listen-only mode; VTXD = VIO (recessive) 3 6 9 mA Standby or Sleep mode; VBAT > VCC 0 0.75 2 A 2.8 - 5.5 V I/O level adapter supply; pin VIO VIO supply voltage on pin VIO Vuvd(VIO) undervoltage detection voltage on pin VIO VBAT or VCC > 4.5 V 0.8 1.8 2.5 V IIO supply current on pin VIO Normal mode; VTXD = 0 V (dominant) - 150 500 A Normal or Listen-only mode; VTXD = VIO (recessive) 0 1 4 A Standby or Sleep mode 0 1 4 A Supply pin VBAT VBAT battery supply voltage 4.5 - 40 V Vuvd(VBAT) undervoltage detection voltage on pin VBAT 3 3.5 4.3 V IBAT battery supply current Normal or Listen-only mode 15 40 70 A Standby mode; VCC > 4.5 V VINH = VWAKE = VBAT 5 18 30 A Sleep mode; VINH = VCC = VIO = 0 V; VWAKE = VBAT 5 18 30 A CAN transmit data input; pin TXD VIH HIGH-level input voltage 0.7VIO - VIO + 0.3 V VIL LOW-level input voltage 0.3 - +0.3VIO V IIH HIGH-level input current VTXD = VIO 5 0 +5 A IIL LOW-level input current Normal mode; VTXD = 0 V 300 200 30 A Ci input capacitance not tested - 5 10 pF CAN receive data output; pin RXD IOH HIGH-level output current VRXD = VIO 0.4 V; VIO = VCC 12 6 1 mA IOL LOW-level output current VRXD = 0.4 V; VTXD = VIO; bus dominant 2 6 14 mA Standby and enable control inputs; pins STB_N and EN VIH HIGH-level input voltage 0.7VIO - VIO + 0.3 V VIL LOW-level input voltage 0.3 - 0.3VIO V IIH HIGH-level input current 1 4 10 A TJA1043 Product data sheet VSTB_N or VEN 0.7VIO All information provided in this document is subject to legal disclaimers. Rev. 4 -- 19 January 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 14 of 29 TJA1043 NXP Semiconductors High-speed CAN transceiver Table 8. Static characteristics ...continued VCC = 4.5 V to 5.5 V; VIO = 2.8 V to VCC; VBAT = 4.5 V to 40 V; RL = 60 ; Tvj = 40 C to +150 C; unless otherwise specified; all voltages are defined with respect to ground; positive currents flow into the device [1]. Symbol Parameter Conditions Min Typ Max Unit IIL LOW-level input current VSTB_N = VEN = 0 V 1 0 +1 A Error and power-on indication output; pin ERR_N IOH HIGH-level output current VERR_N = VIO 0.4 V; VIO = VCC 50 20 4 A IOL LOW-level output current VERR_N = 0.4 V 0.1 0.5 2 mA Local wake-up input; pin WAKE IIH HIGH-level input current VWAKE = VBAT 1.9 V 10 5 1 A IIL LOW-level input current VWAKE = VBAT 3.1 V 1 5 10 A Vth threshold voltage VSTB_N = 0 V VBAT 3 VBAT 2.5 VBAT 2 V Inhibit output; pin INH VH HIGH-level voltage drop IINH = 0.18 mA 0 0.25 0.8 V IL leakage current Sleep mode 2 0 +2 A pin CANH 2.75 3.5 4.5 V pin CANL 0.5 1.5 2.25 V Bus lines; pins CANH and CANL VO(dom) dominant output voltage VTXD = 0 V; t < tto(dom)TXD Vdom(TX)sym transmitter dominant voltage symmetry Vdom(TX)sym = VCC VCANH VCANL 400 - +400 mV VO(dif)bus bus differential output voltage VTXD = 0 V; VCC = 4.75 V to 5.25 V; 45 < RL < 65 ; dominant 1.5 - 3.0 V VTXD = VIO; recessive; no load 50 - +50 mV Normal or Listen-only mode; VTXD = VIO; no load 2 0.5VCC 3 V Standby or Sleep mode; no load 0.1 0 +0.1 V pin CANH; VCANH = 0 V 100 70 40 mA pin CANL; VCANL = 40 V 40 70 100 mA 3 - +3 mA VO(rec) recessive output voltage dominant short-circuit output current VTXD = 0 V (dominant); VCC = 5 V IO(sc)rec recessive short-circuit output current Normal mode; VTXD = VIO; VCANH = VCANL = 27 V to +32 V Vth(RX)dif differential receiver threshold voltage Vcm(CAN) = 30 V to +30 V IO(sc)dom [2] Normal or Listen-only mode 0.5 0.7 0.9 V Standby or Sleep mode 0.4 0.7 1.15 V 50 120 400 mV [2] Vhys(RX)dif differential receiver hysteresis voltage Normal or Listen-only mode Vcm(CAN) = 30 V to +30 V ILI input leakage current VCC = 0 V; VCANH = VCANL = 5 V 100 170 250 A VBAT = 0 V; VCANH = VCANL = 5 V 2 - +2 A 9 15 28 k 3 0 +3 % 19 30 52 k - - 20 pF Ri input resistance Ri input resistance deviation Ri(dif) differential input resistance Ci(cm) common-mode input capacitance TJA1043 Product data sheet between VCANH and VCANL VTXD = VCC [3] All information provided in this document is subject to legal disclaimers. Rev. 4 -- 19 January 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 15 of 29 TJA1043 NXP Semiconductors High-speed CAN transceiver Table 8. Static characteristics ...continued VCC = 4.5 V to 5.5 V; VIO = 2.8 V to VCC; VBAT = 4.5 V to 40 V; RL = 60 ; Tvj = 40 C to +150 C; unless otherwise specified; all voltages are defined with respect to ground; positive currents flow into the device [1]. Symbol Ci(dif) Parameter differential input capacitance Conditions Min Typ Max Unit - - 10 pF Normal or Listen-only mode; 500 A < ISPLIT < 500 A 0.3VCC 0.5VCC 0.7VCC V Normal or Listen-only mode RL = 1 M 0.45VCC 0.5VCC 0.55VCC V Standby or Sleep mode; 58 V < VSPLIT < +58 V 3 0 +3 A - 190 - C VTXD = VCC [3] Common-mode stabilization output; pin SPLIT output voltage VO leakage current IL Temperature detection Tj(sd) [3] shutdown junction temperature [1] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to cover the specified temperature and power supply voltage range. [2] Vcm(CAN) is the common mode voltage of CANH and CANL. [3] Not tested in production; guaranteed by design. TJA1043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 19 January 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 16 of 29 TJA1043 NXP Semiconductors High-speed CAN transceiver 11. Dynamic characteristics Table 9. Dynamic characteristics; VCC = 4.5 V to 5.5 V; VIO = 2.8 V to VCC; VBAT = 4.5 V to 40 V; RL = 60 ; Tvj = 40 C to +150 C; unless otherwise specified; all voltages are defined with respect to ground; positive currents flow into the device[1]. Symbol Parameter Conditions Min Typ Max Unit Timing characteristics; Figure 6 td(TXD-busdom) delay time from TXD to bus dominant Normal mode - 70 - ns td(TXD-busrec) delay time from TXD to bus recessive Normal mode - 90 - ns td(busdom-RXD) delay time from bus dominant to RXD Normal or Listen-only mode - 60 - ns td(busrec-RXD) delay time from bus recessive to RXD Normal or Listen-only mode - 70 - ns tPD(TXD-RXD) propagation delay from TXD to RXD Normal mode 40 - 240 ns tdet(uv) undervoltage detection time 100 - 350 ms trec(uv) undervoltage recovery time tbit(RXD) bit time on pin RXD tbit(TXD) = 500 ns tto(dom)TXD TXD dominant time-out time tto(dom)bus 1 - 5 ms 400 - 550 ns VTXD = 0 V 0.3 0.6 1.5 ms bus dominant time-out time VO(dif)(bus) > 0.9 V 0.3 0.6 1.5 ms th hold time from issuing go-to-sleep command to entering Sleep mode 20 35 50 s twake(busdom) bus dominant wake-up time Standby or Sleep mode; VBAT = 12 V 0.5 1.75 5 s twake(busrec) bus recessive wake-up time Standby or Sleep mode; VBAT = 12 V 0.5 1.75 5 s tto(wake)bus bus wake-up time-out time 0.5 - 2 ms twake wake-up time 5 25 50 s in response to a falling or rising edge on pin WAKE; Standby or Sleep mode [2] [1] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to cover the specified temperature and power supply voltage range. [2] See Figure 7. TJA1043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 19 January 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 17 of 29 TJA1043 NXP Semiconductors High-speed CAN transceiver HIGH TXD LOW CANH CANL dominant 0.9 V VO(dif)(bus) 0.5 V recessive HIGH 0.7VIO RXD 0.3VIO LOW td(TXD-busrec) td(TXD-busdom) td(busrec-RXD) td(busdom-RXD) tPD(TXD-RXD) Fig 6. tPD(TXD-RXD) 015aaa025 CAN transceiver timing diagram 7;' [WELW 7;' WELW 7;' 5;' WELW 5;' DDD Fig 7. TJA1043 Product data sheet Loop delay symmetry timing diagram All information provided in this document is subject to legal disclaimers. Rev. 4 -- 19 January 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 18 of 29 TJA1043 NXP Semiconductors High-speed CAN transceiver 12. Application information 12.1 Application diagram 3V 5V BAT VBAT 10 WAKE VCC INH 7 VIO 3 5 14 9 6 8 TJA1043 GND 4 2 13 CANH 11 SPLIT 12 CANL CAN bus wires Fig 8. 1 VCC STB_N EN Port x, y, z ERR_N RXD TXD MICROCONTROLLER RXD TXD 015aaa060 Typical application with 3 V microcontroller 12.2 Application hints Further information on the application of the TJA1043 can be found in NXP application hints AH1014 Application Hints - Standalone high speed CAN transceiver TJA1042/TJA1043/TJA1048/TJA1051. TJA1043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 19 January 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 19 of 29 TJA1043 NXP Semiconductors High-speed CAN transceiver 13. Test information 95;' +,*+ /2: K\VWHUHVLV 9L GLI EXV 9 PJV Fig 9. Hysteresis of the receiver +12 V +5 V 47 F 100 nF 5 TXD EN STB_N WAKE VCC VIO 3 10 1 13 6 11 14 9 10 F VBAT 12 TJA1043 8 7 4 2 CANH SPLIT RL 100 pF CANL ERR_N INH RXD 15 pF GND 015aaa163 Fig 10. Test circuit for timing characteristics 13.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q100 Rev-G - Failure mechanism based stress test qualification for integrated circuits, and is suitable for use in automotive applications. TJA1043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 19 January 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 20 of 29 TJA1043 NXP Semiconductors High-speed CAN transceiver 14. Package outline 62SODVWLFVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627 ' ( $ ; F \ +( Y 0 $ = 4 $ $ $ $ SLQLQGH[ /S / H GHWDLO; Z 0 ES PP VFDOH ',0(16,216 LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = PP LQFKHV R R 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPP LQFK PD[LPXPSHUVLGHDUHQRWLQFOXGHG 5()(5(1&(6 287/,1( 9(56,21 ,(& -('(& 627 ( 06 -(,7$ (8523($1 352-(&7,21 ,668('$7( Fig 11. Package outline SOT108-1 (SO14) TJA1043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 19 January 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 21 of 29 TJA1043 NXP Semiconductors High-speed CAN transceiver +9621SODVWLFWKHUPDOHQKDQFHGYHU\WKLQVPDOORXWOLQHSDFNDJHQROHDGV WHUPLQDOVERG\[[PP 627 ; % ' $ $ ( $ F WHUPLQDO LQGH[DUHD GHWDLO; H WHUPLQDO LQGH[DUHD H Y Z E & & $ % & \ & \ / N (K 'K 'LPHQVLRQV 8QLW PP PP VFDOH $ $ E F PD[ QRP PLQ ' 'K ( (K H H N / Y Z \ \ VRW 5HIHUHQFHV 2XWOLQH YHUVLRQ ,(& -('(& -(,7$ 627 02 (XURSHDQ SURMHFWLRQ ,VVXHGDWH Fig 12. Package outline SOT1086 (HVSON14) TJA1043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 19 January 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 22 of 29 TJA1043 NXP Semiconductors High-speed CAN transceiver 15. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 16. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description". 16.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 16.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: * Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: * * * * * * Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 16.3 Wave soldering Key characteristics in wave soldering are: TJA1043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 19 January 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 23 of 29 TJA1043 NXP Semiconductors High-speed CAN transceiver * Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave * Solder bath specifications, including temperature and impurities 16.4 Reflow soldering Key characteristics in reflow soldering are: * Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 13) than a SnPb process, thus reducing the process window * Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board * Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 10 and 11 Table 10. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 < 2.5 235 220 2.5 220 220 Table 11. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 13. TJA1043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 19 January 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 24 of 29 TJA1043 NXP Semiconductors High-speed CAN transceiver maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 13. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description". 17. Soldering of HVSON packages Section 16 contains a brief introduction to the techniques most commonly used to solder Surface Mounted Devices (SMD). A more detailed discussion on soldering HVSON leadless package ICs can found in the following application notes: * AN10365 `Surface mount reflow soldering description" * AN10366 "HVQFN application information" TJA1043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 19 January 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 25 of 29 TJA1043 NXP Semiconductors High-speed CAN transceiver 18. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes TJA1043 v.4 20150119 Product data sheet - TJA1043 v.3 Modifications: * * * * * * * * Section 1: text revised (1st paragraph); paragraph added * Table 9: measurements conditions changed (tPD(TXD-RXD)); parameter tbit(RXD) added; Table note 2 and Figure 7 added * * Section 12.2 "Application hints": added Section 2: minor amendments to text Section 2.1: features added Table 1: added parameters VIO, Vuvd(VIO) and IIO; measurements conditions changed: VCANH, VCANL Table 3: Table note 1: text revised Section 7.1.1: minor changes to text Table 6: measurements conditions changed: VBAT, Vx, IWAKE, VESD; table note section revised Table 8: parameter values/conditions changed: IOH and IOL for pin RXD, IIH for pins STB_N and EN; parameters renamed: IO(sc)dom and IO(sc)rec Section 19.3: `Translations' disclaimer added TJA1043 v.3 20130424 Product data sheet - TJA1043 v.2 TJA1043 v.2 20110620 Product data sheet - TJA1043 v.1 TJA1043 v.1 20100330 Product data sheet - - TJA1043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 19 January 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 26 of 29 TJA1043 NXP Semiconductors High-speed CAN transceiver 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 19.3 Disclaimers Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. TJA1043 Product data sheet Suitability for use in automotive applications -- This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 4 -- 19 January 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 27 of 29 TJA1043 NXP Semiconductors High-speed CAN transceiver No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations -- A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 19.4 Trademarks Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 20. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com TJA1043 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 19 January 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 28 of 29 TJA1043 NXP Semiconductors High-speed CAN transceiver 21. Contents 1 2 2.1 2.2 2.3 3 4 5 6 6.1 6.2 7 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.4 7.5 7.6 8 9 10 11 12 12.1 12.2 13 13.1 14 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Low-power management . . . . . . . . . . . . . . . . . 2 Protection and diagnosis (detection and signalling) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 5 Operating modes . . . . . . . . . . . . . . . . . . . . . . . 6 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Listen-only mode . . . . . . . . . . . . . . . . . . . . . . . 7 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Go-to-Sleep mode . . . . . . . . . . . . . . . . . . . . . . 8 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Internal flags . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 UVNOM flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 UVBAT flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pwon flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Wake flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Wake-up source flag. . . . . . . . . . . . . . . . . . . . 10 Bus failure flag . . . . . . . . . . . . . . . . . . . . . . . . 10 Local failure flag . . . . . . . . . . . . . . . . . . . . . . . 10 Local failures . . . . . . . . . . . . . . . . . . . . . . . . . 10 TXD dominant clamping detection . . . . . . . . . 10 TXD-to-RXD short-circuit detection . . . . . . . . 10 Bus dominant clamping detection. . . . . . . . . . 11 Overtemperature detection . . . . . . . . . . . . . . . 11 SPLIT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VIO supply pin . . . . . . . . . . . . . . . . . . . . . . . . . 11 WAKE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13 Thermal characteristics . . . . . . . . . . . . . . . . . 13 Static characteristics. . . . . . . . . . . . . . . . . . . . 14 Dynamic characteristics . . . . . . . . . . . . . . . . . 17 Application information. . . . . . . . . . . . . . . . . . 19 Application diagram . . . . . . . . . . . . . . . . . . . . 19 Application hints . . . . . . . . . . . . . . . . . . . . . . . 19 Test information . . . . . . . . . . . . . . . . . . . . . . . . 20 Quality information . . . . . . . . . . . . . . . . . . . . . 20 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21 15 16 16.1 16.2 16.3 16.4 17 18 19 19.1 19.2 19.3 19.4 20 21 Handling information . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering. . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . Soldering of HVSON packages . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 23 23 23 23 24 25 26 27 27 27 27 28 28 29 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP Semiconductors N.V. 2015. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 19 January 2015 Document identifier: TJA1043 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: NXP: TJA1043T,112 TJA1043T,118 TJA1043TK/1Y TJA1043TKY TJA1043T/1J