1. General description
The TJA1043 high-speed CAN transceiver provides an interface between a Controller
Area Network (CAN) protocol controller and the physical two-wire CAN bus. The
transceiver is designed for high-speed CAN applications in the automotive industry,
providing differential transmit and receive capability to (a microcontroller with) a CAN
protocol cont ro ller.
The TJA1043 belongs to the third generation of high-speed CAN transceive rs from NXP
Semiconductors, offering significant improvements over first- and second-generation
devices such as the TJA1041A. It offers improved ElectroMagnetic Comp atibility (EMC)
and ElectroMagnetic Discharge (ESD) performance, very low power consumption, and
passive behavior when the supply voltage is turned off. Advanced features include:
•Low-power management controls the power supply throughout the node while
supporting local and remote wake-up with wake-up source recognition
•Several protection and diagnostic functions including bus line short-circuit detectio n
and battery connection detection
•Can be interfaced directly to microcontrollers with supply voltages from 3 V to 5 V
The TJA1043 implem en ts the CAN physic al laye r as def ine d in th e cur re n t ISO11898
standard (ISO11898-2:2003, ISO11898-5:2007). Pending the release of the updated
version of ISO11898-2 including CAN FD, additional timing parameters defining loop
delay symmetry are specified. This imple ment ation enables reliable co mmunication in the
CAN FD fast phase at data rates up to 2 Mbit/s.
These features make the TJA1043 the ideal choice for high speed CAN networks
containing nodes that need to be available all times, even when the inte rnal VIO and VCC
supplies are switched off.
2. Features and benefits
2.1 General
Fully ISO 11898-2:2003 and ISO 11898-5:2007 compliant
Loop delay symmetry timing enables reliable communication at data rates up to
2 Mbit/s in the CAN FD fast phase
Suitable for 12 V and 24 V systems
Low ElectroMagnetic Emission (EME) and high ElectroMagnetic Immunity (EMI)
VIO input allows for direct interfacing with 3 V and 5 V micr oc on tr olle rs
SPLIT voltage output for stabilizing the recessive bus level
Listen-only mode for node diagnosis and failure containment
TJA1043
High-speed CAN transceiver
Rev. 4 — 19 January 2015 Product data sheet
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Product data sheet Rev. 4 — 19 January 2015 2 of 29
NXP Semiconductors TJA1043
High-speed CAN transceiver
Available in SO14 and HVSON14 packages
Leadless HVSON14 package (3.0 mm 4.5 mm) with improved Automated Optical
Inspection (AOI) capability
AEC-Q100 qualified
Dark green product (halogen free and Restriction of Hazardous Subst ances (RoHS)
compliant)
2.2 Low-power management
Very low current Standby and Sleep modes, with local and remote wake-up
Capability to power down the entire node while supporting local, remote and host
wake-up
Wake-up source recognition
Transceiver disengages from the bus (zero load) when V BAT absent
Functional behavior predictable under all supply conditions
2.3 Protection and diagnosis (detection and signalling)
High ESD handling capability on the bus pins
Bus pins and VBAT protected against transients in automotive environments
Transmit Data (TXD) dominant time-out function with diagnosis
TXD-to-RXD short-circuit handler with diagnosis
Thermal protection with diagnosis
Undervoltage detection and recovery on pins VCC, VIO and VBAT
Bus line short-circuit dia g nosis
Bus dominant clamping diagnosis
Cold start diagnosis (first battery connection)
3. Quick reference data
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 4.5 - 5.5 V
VIO supply voltage on pin VIO 2.8 - 5.5 V
Vuvd(VCC) undervoltage detection voltage on
pin VCC
33.54.3V
Vuvd(VIO) undervoltage detection voltage on
pin VIO
VBAT or VCC > 4.5 V 0.8 1.8 2.5 V
ICC supply current Normal mode; bus dominant 30 48 65 mA
Normal or Listen-only mode; bus recessive 3 6 9 mA
Standby or Sleep mode 0 0.75 2 A
IIO supply current on pin VIO Normal mode; VTXD = 0 V (dominant) - 150 500 A
Normal or Listen-only mode; VTXD =V
IO
(recessive) 014A
Standby or Sleep mode 0 1 4 A
VESD electrostatic discharge voltage IEC 61000-4-2 at pins CANH and CANL 8- +8kV
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Product data sheet Rev. 4 — 19 January 2015 3 of 29
NXP Semiconductors TJA1043
High-speed CAN transceiver
4. Ordering information
VCANH voltage on pin CANH 58 - +58 V
VCANL voltage on pin CANL 58 - +58 V
Tvj virtual junction temperature 40 - +150 C
Table 1. Quick reference data …continued
Symbol Parameter Conditions Min Typ Max Unit
Table 2. Ordering information
Type number Package
Name Description Version
TJA1043T SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
TJA1043TK HVSON14 plastic, thermal enhanced very thin sma ll outline package; no leads;
14 terminals; body 3 4.5 0.85 mm SOT1086-2
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Product data sheet Rev. 4 — 19 January 2015 4 of 29
NXP Semiconductors TJA1043
High-speed CAN transceiver
5. Block diagram
Fig 1. Block diagram
TEMPERATURE
PROTECTION
TIME-OUT
MODE
CONTROL
+
WAKE-UP
CONTROL
+
ERROR
DETECTION
MUX
+
DRIVER
TXD 1
V
IO
RXD 4
SLOPE
CONTROL
+
DRIVER
V
CC
CANH
CANL
13
12
53
2
GND
TJA1043
SPLIT SPLIT
11
WAKE-UP
FILTER
015aaa061
10
V
CC
V
IO
V
BAT
14
STB_N
6
EN
ERR_N 8
V
BAT
9
WAKE
V
BAT
INH
7
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Product data sheet Rev. 4 — 19 January 2015 5 of 29
NXP Semiconductors TJA1043
High-speed CAN transceiver
6. Pinning information
6.1 Pinning
6.2 Pin description
[1] For enhanced thermal and electrical performance, the exposed center pad of the HVSON14 package
should be soldered to board ground.
7. Functional description
The TJA1043 is a stand-alone high-speed CAN transceiver with a number of operating
modes, fail-safe features and diagnostic features that offer enhanced system reliability
and advanced power management. The transceiver combines the functionality of the
Fig 2. Pin configuration diagram: SO14 Fig 3. Pin configuration diagram: HVSON14
TJA1043T
TXD STB_N
GND CANH
VCC CANL
RXD SPLIT
VIO VBAT
EN WAKE
INH ERR_N
015aaa062
1
2
3
4
5
6
7 8
10
9
12
11
14
13
terminal 1
index area
TJA1043TK
TXD 1
GND 2
RXD 4
V
IO
5
EN 6
INH 7
STB_N14
CANH13
CANL12
SPLIT11
V
BAT
10
WAKE9
ERR_N8
3
V
CC
015aaa376
Table 3. Pin description
Symbol Pin Description
TXD 1 transmit data input
GND[1] 2 ground supply
VCC 3 transceiver supply voltage
RXD 4 receive data output; reads ou t data from the bus lines
VIO 5 supply voltage for I/O level adaptor
EN 6 enable control input
INH 7 inhibit output for switching external voltage regulators
ERR_N 8 error and power-on indication output (active LOW)
WAKE 9 local wake-up input
VBAT 10 battery supply voltage
SPLIT 11 common-mode stabilization output
CANL 12 LOW-level CAN bus line
CANH 13 HIGH-level CAN bus line
STB_N 14 standby control input (active LOW)
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Product data sheet Rev. 4 — 19 January 2015 6 of 29
NXP Semiconductors TJA1043
High-speed CAN transceiver
TJA1041A with improved EMC and ESD capability and quiescent current performance.
Improved slope control and high DC handling capability on the bus pins provide additional
application flexibility.
7.1 Operati ng modes
The TJA1043 supports five operating modes. Control pins STB_N and EN are used to
select the operating mode. Switching between modes allows access to a number of
diagnostics flag s via pin ERR_ N. Table 4 describes how to switch between modes.
Figure 4 illustrates the mode transitions when VCC, VIO and VBAT are valid.
[1] Setting the UVNOM flag will clear the WAKE flag.
[2] Setting the Wake flag will clear the UVNOM flag.
[3] A LOW-to-HIGH transition on pin STB_N will clear the UVNOM flag
[4] After the minimum hold time, in Go-to-Sleep mode, th(min), the transceiver will enter Sleep mode and pin
INH will be set floating.
Table 4. Operating mo de selection
Internal flags Control pins Operating mode Pin INH
UVNOM[1] UVBAT Wake[2] STB_N[3] EN
From Normal, Listen-only, Standby and Go-to-Sleep modes
set X X X X Sleep mode floating
cleared set X HIGH X S tandby mode HIGH
cleared X set LOW X S tandby mode HIGH
cleared X cleared LOW LOW Standby mode HIGH
cleared X cleared LOW HIGH Go-to-Sleep mode[4] HIGH[4]
cleared cleared X HIGH LOW Listen-only mode HIGH
cleared cleared X HIGH HIGH Normal mode HIGH
From Sleep mode
set X X X X Sleep mode floating
cleared set X HIGH X S tandby mode HIGH
cleared X set LOW X S tandby mode HIGH
cleared X cleared LOW X Sleep mode floating
cleared cleared X HIGH LOW Listen-only mode HIGH
cleared cleared X HIGH HIGH Normal mode HIGH
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High-speed CAN transceiver
7.1.1 Normal mode
In Normal mode, the transceiver can transmit and receive data via the bus lines CANH
and CANL (see Figure 1 for the block diagram). The differential receiver converts the
analog dat a on the bus lines into digit al data which is output to pin RXD. The slopes of the
output signals on the bus lines are controlled internally and are optimized in a way that
guarantees the lowest possible EME. The bus pins are biased to 0.5VCC (via Ri). Pin INH
is active, so voltage regulators controlled by pin INH (see Figure 8) will be active too.
7.1.2 Listen-only mode
In Listen-only mode, the transceiver’s transmitter is disabled, effectively providing a
transceiver listen-only feature. The receiver will still convert the analog bus signal on
pins CANH and CAN L into digital data, available for output on pin RXD. As in Normal
mode, the bus pins are biased at 0.5VCC and pin INH remains active.
Fig 4. Mode transitions when valid VCC, VIO and VBAT voltages are present
015aaa063
STANDBY
MODE
NORMAL
MODE
GO-TO-SLEEP
MODE
LEGEND:
= H, = L logical state of pin
SLEEP
MODE
LISTEN-
ONLY MODE
Wake flag cleared
and
t > t
h(min)
STB_N = H and EN = H
STB_N = H and EN = L
STB_N = L
and
Wake flag set
STB_N = L
and
(EN = L or Wake flag set)
STB_N = L and EN = H
and
Wake flag cleared
STB_N = H
and
EN = H
STB_N = H
and
EN = L
STB_N = L
and
(EN = L or Wake flag set) STB_N = L and EN = H
and
Wake flag cleared
STB_N = L
and
EN = H
STB_N = H
and
EN = H
STB_N = L
and
EN = L
STB_N = H
and
EN = L
STB_N = H
and
EN = H
STB_N = H
and
EN = L
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High-speed CAN transceiver
7.1.3 Standby mode
Standby mode is the TJA1043’s first-level power saving mode, offering reduced current
consumption. In Standby mode, the transceiver is unable to tran smit or receive data and
the low-power receiver is activated to monitor bus activity. The bus pins are biased at
ground level (via Ri). Pin INH is still active, so voltage regulators controlled by this pin will
also be active.
Pins RXD a nd ERR_N will reflect any active wake-up requests (provided that VIO and
VBAT are present).
7.1.4 Go-to-Sleep mode
Go-to-Sleep mode is the controlled route for enter ing Sleep mode. In Go-to-Sleep mode,
the transceiver behaves as in Standby mode, with the addition that a go-to-sleep
command is issued to the transceiver . The transceiver will remain in Go-to-Sleep mode for
the minimum hold time (th(min)) be fore en terin g Slee p mo de. The tra nsceiver wil l not e nter
Sleep mode if the state of pin STB_N or p i n EN is changed or if the Wake flag is set
before th(min) has elapsed.
7.1.5 Sleep mode
Sleep mode is the TJA1043’s second-level power saving mode. Sleep mode is entered
via Go-to-Sleep mode, and also when the undervoltage detection time on either VCC or
VIO elapses before the relevant voltage level has recovered. In Sleep mode, the
transceiver behaves as described for S tandby mod e, with the exception that pin INH is set
floating. Voltage regulators controlled by this pin will be switched off, and the current into
pin VBAT will be reduced to a minimum. Pins STB_N, EN and the Wake flag can be used to
wake up a node from Sleep mode (see Table 4).
7.2 Internal flags
The TJA1043 makes use of seven internal flags for its fail-safe fallback mode control and
system diagnosis support. Five of these flags can be polled by the controller via pin
ERR_N. Which flag is available on pin ERR_N at any time depends on the active
operating mode and on a number of other conditions. Table 5 describes how to access
these flags.
Table 5. Accessing internal flags via pin ERR_N
Internal
flag Flag is available on pin ERR_N[1] Flag is cleared
UVNOM no by setting the Pwon or Wake flags, by a
LOW-to-HIGH transition on STB_N or
when both VIO and VBAT have
recovered.
UVBAT no when VBAT has recovered
Pwon in Listen-only mode (coming from S t andby
mode, Go-to-Sleep mode, or Sleep mode) on entering Normal mode
Wake in Standby mode, Go-to-Sleep mode, and
Sleep mode (provided that VIO and VBAT
are present)
on entering Normal mode or by setting
the UVNOM fla g
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High-speed CAN transceiver
[1] Pin ERR_N is an active-LOW output, so a LOW-level indicates a set flag and a HIGH-level indicates a
cleared flag. Allow pin ERR_N to stabilize for at least 8 s after changing operating modes.
[2] Allow for a TXD dominant time of at least 4 s per dominant-recessive cycle.
7.2.1 UVNOM flag
UVNOM is the VCC and VIO undervolta ge detection flag. The flag is set when the vo ltage on
pin VCC drop s below the VCC undervoltag e detection voltage, Vuvd(VCC), for longer than the
undervoltage detection time, tdet(uv), or when th e vo ltage on pin VIO drops below Vuvd(VIO)
for longer than tdet(uv). When the UVNOM flag is set, the transce iver enters Sleep mode to
save power and to ensure the bus is not disturbed. In Sleep mode the voltage regulators
connected to pin INH are disab led , av oid i ng any extra power consumption that might be
generated as a result of a short-circuit condition.
Any wake-up request, setting the Pwon flag or a LOW-to-HIGH transition on STB_N will
clear UVNOM and the timers, allowing the voltage regulator s to be reactivated (at least until
UVNOM is set again). UVNOM will also be cleared if both VCC and VIO recover for longer
than the undervoltage recovery time, trec(uv). The transceiver will then switch to the
operating mode indicated by the logic levels on pins STB_N and EN (see Table 4).
7.2.2 UVBAT flag
UVBAT is the VBAT undervoltage detection flag. This flag is set when the voltage on
pin VBAT drops below Vuvd(VBAT). When UVBAT is set, the transceiver will try to enter
Standby mode to save power and will disengage from the bus (zero load). UVBAT is
cleared when the voltage on pin VBAT recovers. The transceiver will then switch to the
operating mode indicated by the logic levels on pins STB_N and EN (see Table 4).
7.2.3 Pwon flag
Pwon is the VBAT power-on flag. This flag is set when the voltage on pin VBAT recovers
after previously dropping below Vuvd(VBAT) (usually because the battery was
disconnected). Setting the Pwon flag clears the UVNOM flag and timers. The Wake and
Wake-up source flags are set to ensure consistent system power-up under all supply
conditions. In Listen-only mode th e Pwon flag can be polled via pin ERR_N (see Table 5).
The flag is cleared when the transceiver enters Normal mode.
7.2.4 Wake flag
The Wake flag is set when the transceiver detects a local or remote wake-up request. A
local wake-up request is detected when the logic level on pin WAKE changes, and the
new level remains stable for at least twake. A remote wake-up request is triggered by two
bus dominan t states of at leas t twake(busdom), with the first dominant state followed by a
Wake-up
source in Normal mode (before the fourth
dominant-to-recessive edge on pin TXD[2])on leaving Normal mode
Bus failure in Normal mode (after the fourth
dominant-to-recessive edge on pin TXD[2])on re-entering Normal mode or by
setting the Pwon flag
Local failure in Listen-only mode (coming from Normal
mode) on entering Normal mode or when RXD
is dominant while TXD is recessive
(provided that all local failures are
resolved) or by setting the Pwon flag
Table 5. Accessing internal flags via pin ERR_N …continued
Internal
flag Flag is available on pin ERR_N[1] Flag is cleared
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Product data sheet Rev. 4 — 19 January 2015 10 of 29
NXP Semiconductors TJA1043
High-speed CAN transceiver
recessive state of at least twake(busrec) (provided the complete
dominant-recessive-dominant pattern is completed within tto(wake)bus). The Wake flag can
be set in Standby mode, Go-to-Sleep mode or Sleep mode. Setting the Wake flag clears
the UVNOM flag and timers. Once set, the Wake fl ag status is immediately available on
pins ERR_N and RXD (provided VIO and VBAT are present). This flag is also set at
power-on and cleared when the UVNOM flag is set or the transceiver enters Normal mode.
7.2.5 Wake-up source flag
Wake-up source re co gn itio n is provid e d via th e Wake-up source flag, whic h is set wh en
the Wake flag is set by a local wake-up request via the WAKE pin. The Wake-up source
flag can be polled via the ERR_N pin in Normal mode (see Table 5). This flag is also set at
power-on and cleared when the transceiver leaves Normal mode.
7.2.6 Bus failure flag
The Bus failure flag is set if the transceiver detects a bus line short-circuit condition to
VBAT, VCC or GND during four consecutive dominant-recessive cycles on pin TXD, while
trying to drive the bus lines dominant. The Bus failure flag can be polled via the ERR_N
pin in Normal mode (see Table 5). This flag is cleared at p ower-on or when the transceiver
re-enters Normal mode.
7.2.7 Local failure flag
In Normal and Listen-only modes, the transceiver can distinguish four di fferent local
failure events, any of which will cause the Local failure flag to be set. The four local failure
events are: TXD dominant clamping, TXD-to-R XD short circuit, bus dominant clamping
and an overtemperature event. The nature and detection of these local failures is
described in Section 7.3. The Local failure flag can be polled via the ERR_N pin in
Listen-only mode (see Table 5). This flag is cleared at power-on, when entering Normal
mode or when RXD is dominant while TXD is recessive, provided that all local failures
have been resolved.
7.3 Local failures
The TJA1043 can detect fo ur differen t local failure conditions. Any of these failures will set
the Local failure flag, and in most cases the transmitter of the transceiver will be disabled.
7.3.1 TXD dominant clamping detection
A permanent LOW level on pin TXD (due to a hardware or software application failure)
would drive the CAN bus into a permanent dominant state, blocking all network
communications. The TXD dom inant time-out function prevent s such a network lock-up by
disabling the transmitter if pin TXD remains LOW fo r longer than the TXD dominant
time-out time tto(dom)TXD. The tto(dom)TXD timer defines th e minimum possible bit rate of
40 kbit/s. The transmitter remain s disabled until the Local failure flag has been cleared.
7.3.2 TXD-to-RXD short-circuit detection
A short-circuit between pins RXD and TXD would lock the bus in a permanent dominant
state once it had been driven dominant, because the low-side driver of RXD is typically
stronger than th e hig h- sid e dr ive r of the con tr olle r co nn e cte d to TXD. T XD-t o- RXD
short-circuit detection prevents such a network lock-up by disabling the tran sm itte r. The
transmitter remains disabled until the Local failure flag has been cleared.
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High-speed CAN transceiver
7.3.3 Bus dominant clamping detection
A CAN bus short circuit (to VBAT, VCC or GND) or a failure in one of the other networ k
nodes could result in a differential voltage on the bus high enough to represent a bus
dominant state. Because a node will not start transmission if the bus is dominant, the
normal bus failure detection will not detect this failure, but the bus dominant clamping
detection will. The Local failure flag is set if the dominant state on the bus persists for
longer than tto(dom)bus. By checking this flag, the controller can determine if a clamp ed bus
is blocking network communications. Th ere is no need to disable th e transmitter . No te that
the Local failure flag does not retain a bus dominant clamping failure, and is released as
soon as the bus returns to recessive state.
7.3.4 Overtemperature detection
If the junction temperature becomes excessive, the transmitter will shut down in time to
protect the output dr ivers from overheatin g without compromi sing the maximum operating
temperature. The transmitter will remain disabled until the Local failure flag has been
cleared.
7.4 SPLIT pin
Using the SPLIT pin on the TJA1043 in conjunction with a split termination network (see
Figure 5 and Figure 8) can help to stabilize the recessive voltage level on the bus. This
will reduce EME in networks with DC leakage to ground (e.g. from deactivated nodes with
poor bus leakage performance). In Normal and Listen-only modes, pin SPLIT delivers a
DC output voltage of 0.5VCC. In Standby, Go-to-Sleep and Sleep modes, pin SPLIT is
floating.
7.5 VIO supply pin
Pin VIO should be connected to the m icrocontroller sup ply voltage (see Figure 8). This will
cause the signal levels of pins TXD, RXD, STB_N, EN and ERR_N to be adjusted to the
I/O levels of the microcontroller, facilitating direct interfacing without the need for glue
logic.
Fig 5. Stabilization circuit and application
GND
VCC
VSPLIT = 0.5VCC
in normal mode
and pwon/listen-only
mode;
otherwise floating
TJA1043
SPLIT
60 Ω
60 Ω
R
R
015aaa064
VSPLIT
CANH
CANL
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Product data sheet Rev. 4 — 19 January 2015 12 of 29
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High-speed CAN transceiver
7.6 WAKE pin
A local wake-up event is triggered by a LOW-to-HIGH or HIGH-to-LOW transition on the
WAKE pin, allowing for maximum flexibility when designing a local wake-up circuit.To
minimize current consumption, the internal bias voltage will follow the logic state on the
pin after a delay of twake. A HIGH level on pin WAKE is followed by an internal pull-up to
VBAT. A LOW level on pin WAKE is followed by an internal pull-down towards GND. In
applications that don’t make use of the local wake-up facility, it is recommended that the
WAKE pin be connected to VBAT or GND to ensure optimal EMI performance.
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High-speed CAN transceiver
8. Limiting values
[1] V erified by an external test house to ensure pins CANH, CANL, SPLIT and VBAT can withstand ISO 7637 part 3 automotive transient test
pulses 1, 2a, 3a and 3b.
[2] According to IEC TS 62228 (2007), Section 4.3; DIN EN 61000-4-2.
[3] According to AEC-Q100-002.
[4] According to AEC-Q100-003.
[5] According to AEC-Q100-011 Rev-C1. The classification level is C4B.
[6] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj =T
amb +PRth(vj-a), where Rth(vj-a) is a
fixed value to be used for the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient
temperature (Tamb).
9. Thermal characteristics
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VBAT battery supply voltage 0.3 +58 V
load dump - 58 V
Vxvoltage on pin x on pins CANH, CANL and SPLIT 58 +58 V
on pins INH and WAKE 0.3 +58 V
on pins VCC, VIO, TXD, RXD, STB_N, EN,
ERR_N 0.3 +7 V
IWAKE current on pin WAKE - 15 mA
Vtrt transient voltage on pins CANH, CANL, SPLIT and VBAT [1] 200 +200 V
VESD electrostatic discharge voltage IEC 61000-4-2 (150 pF, 330 )[2]
at pins CANH and CANL 8+8 kV
Human Body Model (HBM); 100 pF, 1.5 k[3]
at pins CANH and CANL 8+8 kV
at any other pin 4+4 kV
Machine Model (MM); 200 pF, 0.75 H, 10 [4]
at any pin 300 +300 V
Charged Device Model (CDM); field Induced
charge; 4 pF [5]
at corner pins 750 +750 V
at any pin 500 +500 V
Tvj virtual junction temperature [6] 40 +150 C
Tstg storage temperature 55 +150 C
Table 7. Thermal characteristics
Value determined for free convection conditions on a JEDEC 2S2P board.
Symbol Parameter Conditions Typ Unit
Rth(vj-a) thermal resistance from virtual junction to ambient SO14 package; in free air 68 K/W
HVSON14 package; in free air 44 K/W
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High-speed CAN transceiver
10. Static characteristics
Table 8. Static characteristics
VCC = 4.5 V to 5.5 V; VIO = 2.8 V to VCC; VBAT =4.5Vto40V; R
L=60
; Tvj =
40
Cto+150
C; unless otherwise
specified; all voltages are defined with respect to ground; positive currents flow into the device [1].
Symbol Parameter Conditions Min Typ Max Unit
Supply pin VCC
VCC supply voltage 4.5 - 5.5 V
Vuvd(VCC) undervoltage detection
voltage on pin VCC VBAT > 4.5 V 3 3.5 4.3 V
ICC supply current Normal mode; VTXD = 0 V (dominant) 30 48 65 mA
Normal or Listen -o n ly mode;
VTXD =V
IO (recessive) 36 9mA
Standby or Sleep mode; VBAT > VCC 00.752A
I/O level adapter supply; pin VIO
VIO supply voltage on pin VIO 2.8 - 5.5 V
Vuvd(VIO) undervoltage detection
voltage on pin VIO
VBAT or VCC > 4.5 V 0.8 1.8 2.5 V
IIO supply current on pin VIO Normal mode; VTXD = 0 V (dominant) - 150 500 A
Normal or Listen -o n ly mode;
VTXD =V
IO (recessive) 01 4A
Standby or Sleep mode 0 1 4 A
Supply pin VBAT
VBAT battery supply voltage 4.5 - 40 V
Vuvd(VBAT) undervoltage detection
voltage on pin VBAT 33.54.3V
IBAT battery supply current Normal or Listen-only mode 15 40 70 A
Standby mode; VCC >4.5V
VINH =V
WAKE =V
BAT
51830A
Sleep mode; VINH =V
CC =V
IO =0V;
VWAKE =V
BAT
51830A
CAN transmit data input; pin TXD
VIH HIGH-level input voltage 0.7VIO -V
IO +0.3 V
VIL LOW-level input voltage 0.3 - +0.3VIO V
IIH HIGH-level input current VTXD =V
IO 50 +5A
IIL LOW-level input current Normal mode; VTXD = 0 V 300 200 30 A
Ciinput capacitance not tested - 5 10 pF
CAN receive data output; pin RXD
IOH HIGH-level output current VRXD =V
IO 0.4 V; VIO =V
CC 12 61mA
IOL LOW-level output current VRXD = 0.4 V; VTXD =V
IO;
bus dominant 26 14mA
Standby and enable contr o l input s ; pins STB_N and EN
VIH HIGH-level input voltage 0.7VIO -V
IO +0.3 V
VIL LOW-level input voltage 0.3 - 0.3VIO V
IIH HIGH-level input current VSTB_N or VEN 0.7VIO 14 10A
TJA1043 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 19 January 2015 15 of 29
NXP Semiconductors TJA1043
High-speed CAN transceiver
IIL LOW-level input current VSTB_N =V
EN =0V 10 +1A
Error and power-on indi ca ti on ou tput; pin ERR_N
IOH HIGH-level output current VERR_N =V
IO 0.4 V; VIO =V
CC 50 20 4A
IOL LOW-level output current VERR_N = 0.4 V 0.1 0.5 2 mA
Local wake-up input; pin WAKE
IIH HIGH-level input current VWAKE =V
BAT 1.9 V 10 51A
IIL LOW-level input current VWAKE =V
BAT 3.1 V 1 5 10 A
Vth threshold voltage VSTB_N =0V V
BAT 3V
BAT 2.5 VBAT 2V
Inhibit output; pin INH
VHHIGH-level voltage drop IINH =0.18 mA 0 0.25 0.8 V
ILleakage current Sleep mode 20 +2A
Bus lines; pins CANH and CANL
VO(dom) dominant output voltage VTXD =0V; t<t
to(dom)TXD
pin CANH 2.75 3.5 4.5 V
pin CANL 0.5 1.5 2.25 V
Vdom(TX)sym transmitter dominant
voltage symmetry Vdom(TX)sym = VCC VCANH VCANL 400 - +400 mV
VO(dif)bus bus differential output
voltage VTXD =0V; V
CC = 4.75 V to 5.25 V;
45 <R
L<65; dominant 1.5 - 3.0 V
VTXD =V
IO; recessive; no load 50 - +50 mV
VO(rec) recessive output voltage Normal or Listen-only mo de ;
VTXD =V
IO; no load 20.5V
CC 3V
Standby or Sleep mode; no load 0.1 0 +0.1 V
IO(sc)dom dominant short-circuit
output current VTXD = 0 V (dominant); VCC =5V
pin CANH; VCANH =0V 100 70 40 mA
pin CANL; VCANL = 40 V 40 70 100 mA
IO(sc)rec recessive short-circuit
output current Normal mode; VTXD =V
IO;
VCANH =V
CANL =27 V to +32 V 3- +3mA
Vth(RX)dif differential receiver
threshold voltage Vcm(CAN) =30 V to +30 V [2]
Normal or Listen -o n ly mode 0.5 0.7 0.9 V
Standby or Sleep mode 0.4 0.7 1.15 V
Vhys(RX)dif differential receiver
hysteresis voltage Normal or Listen -o n ly mo de
Vcm(CAN) =30 V to +30 V [2] 50 120 400 mV
ILI input leakage current VCC =0V; V
CANH =V
CANL = 5 V 100 170 250 A
VBAT =0V; V
CANH =V
CANL =5V 2- +2A
Riinput resistance 9 15 28 k
Riinput resistance deviation between VCANH and VCANL 30 +3%
Ri(dif) differential input resistance 19 30 52 k
Ci(cm) common-mode input
capacitance VTXD =V
CC [3] - - 20 pF
Table 8. Static characteristics …continued
VCC = 4.5 V to 5.5 V; VIO = 2.8 V to VCC; VBAT =4.5Vto40V; R
L=60
; Tvj =
40
Cto+150
C; unless otherwise
specified; all voltages are defined with respect to ground; positive currents flow into the device [1].
Symbol Parameter Conditions Min Typ Max Unit
TJA1043 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 19 January 2015 16 of 29
NXP Semiconductors TJA1043
High-speed CAN transceiver
[1] All parameters are guaranteed over the virtual junction t emperature range by design. Factory testing uses correlated test conditions to
cover the specified temperature and power supply voltage range.
[2] Vcm(CAN) is the common mode voltage of CANH and CANL.
[3] Not tested in production; guaranteed by design.
Ci(dif) differential input
capacitance VTXD =V
CC [3] - - 10 pF
Common-mode stabilization output; pin SPLIT
VOoutput voltage Normal or Listen-only mode;
500 A<I
SPLIT < 500 A0.3VCC 0.5VCC 0.7VCC V
Normal or Listen -o n ly mode
RL=1M
0.45VCC 0.5VCC 0.55VCC V
ILleakage current Standby or Sleep mode;
58 V < VSPLIT <+58V 30 +3A
Temperatu r e de te ction
Tj(sd) shutdown junction
temperature [3] - 190 - C
Table 8. Static characteristics …continued
VCC = 4.5 V to 5.5 V; VIO = 2.8 V to VCC; VBAT =4.5Vto40V; R
L=60
; Tvj =
40
Cto+150
C; unless otherwise
specified; all voltages are defined with respect to ground; positive currents flow into the device [1].
Symbol Parameter Conditions Min Typ Max Unit
TJA1043 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 19 January 2015 17 of 29
NXP Semiconductors TJA1043
High-speed CAN transceiver
11. Dynamic characteristics
[1] All parameters are guaranteed over the virtual junction t emperature range by design. Factory testing uses correlated test conditions to
cover the specified temperature and power supply voltage range.
[2] See Figure 7.
Table 9. Dynamic characteristics;
VCC = 4.5 V to 5.5 V; VIO = 2.8 V to VCC; VBAT =4.5Vto40V; R
L=60
; Tvj =
40
Cto+150
C; unless otherwise
specified; all voltages are defined with respect to ground; positive currents flow into the device[1].
Symbol Parameter Conditions Min Typ Max Unit
Timin g characteri stics; Figure 6
td(TXD-busdom) delay time from TXD to bus dominant Normal mode - 70 - ns
td(TXD-busrec) delay time from TXD to bus recessive Normal mode - 90 - ns
td(busdom-RXD) delay time from bus dominant to RXD Normal or Listen-only mode - 60 - ns
td(busrec-RXD) delay time from bus recessive to
RXD Normal or Listen-only mode - 70 - ns
tPD(TXD-RXD) propagation delay from TXD to RXD Normal mode 40 - 240 ns
tdet(uv) undervoltage detection time 100 - 350 ms
trec(uv) undervoltage recovery time 1 - 5 ms
tbit(RXD) bit time on pin RXD tbit(TXD) = 500 ns [2] 400 - 550 ns
tto(dom)TXD TXD dominant time-out time VTXD =0V 0.3 0.6 1.5 ms
tto(dom)bus bus dominant time-out time VO(dif)(bus) > 0.9 V 0.3 0.6 1.5 ms
thhold time from issuing go-to-sleep
command to entering Sleep mode 20 35 50 s
twake(busdom) bus dominant wake-up time Standby or Sleep mode;
VBAT =12V 0.5 1.75 5 s
twake(busrec) bus recessive wake-up time Standby or Sleep mode;
VBAT =12V 0.5 1.75 5 s
tto(wake)bus bus wake-up time-out time 0.5 - 2 ms
twake wake-up time in response to a falling or rising
edge on pin WAKE; Standby or
Sleep mode
52550s
TJA1043 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 19 January 2015 18 of 29
NXP Semiconductors TJA1043
High-speed CAN transceiver
Fig 6. CAN transceiver timing diagram
Fig 7. Lo op delay symmetry timing diagram
CANH
CANL
td(TXD-busdom)
TXD
VO(dif)(bus)
RXD
HIGH
HIGH
LOW
LOW
dominant
recessive
0.9 V
0.5 V
0.3VIO
0.7VIO
td(busdom-RXD)
td(TXD-busrec)
td(busrec-RXD)
tPD(TXD-RXD)
tPD(TXD-RXD) 015aaa025
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TJA1043 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 19 January 2015 19 of 29
NXP Semiconductors TJA1043
High-speed CAN transceiver
12. Application information
12.1 Application diagram
12.2 Application hints
Further information on the application of the TJA1043 can be found in NXP application
hints AH1014 Application Hints - Standalone high speed CAN transceiver
TJA1042/TJA1043/TJA1048/TJA1051.
Fig 8. Typical application with 3 V microcontro ller
SPLIT
CAN bus wires
TJA1043 MICRO-
CONTROLLER
WAKE
VIO
INH
VBAT VCC
5710 3 VCC
Port x, y, z
RXD
TXD
STB_N
GND
9
2
CANLCANH 11 1213
015aaa060
EN
TXD
RXD
ERR_N
14
6
1
4
8
5 V
BAT
3 V
TJA1043 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 19 January 2015 20 of 29
NXP Semiconductors TJA1043
High-speed CAN transceiver
13. Test information
13.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 Rev-G - Failure mechanism based stress test qualification for
integrated circuits, and is suitable for use in automotive app licat ion s.
Fig 9. Hysteresis of the receiver
Fig 10. Test circuit for timing characteristics
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TJA1043 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 19 January 2015 21 of 29
NXP Semiconductors TJA1043
High-speed CAN transceiver
14. Package outline
Fig 11. Package outline SOT108-1 (SO14)
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TJA1043 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 19 January 2015 22 of 29
NXP Semiconductors TJA1043
High-speed CAN transceiver
Fig 12. Package outline SOT1086 (HVSON14)
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TJA1043 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 19 January 2015 23 of 29
NXP Semiconductors TJA1043
High-speed CAN transceiver
15. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate pre ca u tio ns ar e taken as
described in JESD625-A or equivalent standards.
16. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
W ave soldering is a joinin g technology in which the joint s are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
•Through-hole components
•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperatur e profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•Board specifications, including the board finish, solder masks and vias
•Package footprints, including solder thieves and orientation
•The moisture sensitivity level of the packages
•Package placement
•Inspection and repair
•Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
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Product data sheet Rev. 4 — 19 January 2015 24 of 29
NXP Semiconductors TJA1043
High-speed CAN transceiver
•Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
•Solder bath specifications, including temperature and impurities
16.4 Reflow soldering
Key characteristics in reflow soldering are:
•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to
higher minimum peak temperatures (see Figure 13) than a SnPb process, thus
reducing the process window
•Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
•Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enoug h for the solder to make reliable solder joint s (a solder paste
characteristic). In addition, the peak temperature must be low en ough that the
packages and/or boards are not damaged. Th e peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 10 and 11
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures duri ng reflow
soldering, see Figure 13.
Table 10. SnPb eutectic process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350 350
< 2.5 235 220
2.5 220 220
Table 11. Lead-free process (from J-STD-020 D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
TJA1043 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 19 January 2015 25 of 29
NXP Semiconductors TJA1043
High-speed CAN transceiver
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
17. Soldering of HVSON packages
Section 16 contains a brief intr oduction to the techniques most commonly used to solder
Surface Mounted Devices (SMD). A more detailed discussion on soldering HVSON
leadless package ICs can found in the following application notes:
•AN10365 ‘Surface mount reflow soldering description”
•AN10366 “HVQFN application information”
MSL: Moisture Sensitivity Level
Fig 13. Temperature profiles for large and small components
001aac844
temperature
time
minimum peak temperature
= minimum soldering temperature
maximum peak temperature
= MSL limit, damage level
peak
temperature
TJA1043 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 19 January 2015 26 of 29
NXP Semiconductors TJA1043
High-speed CAN transceiver
18. Revision history
Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
TJA1043 v.4 20150119 Product data sheet - TJA1043 v.3
Modifications: •Section 1: text revised (1st paragraph); paragraph added
•Section 2: minor amendments to text
•Section 2.1: features added
•Table 1: added parameters VIO, Vuvd(VIO) and IIO; measurements conditions changed: VCANH, VCANL
•Table 3: Table note 1: text revised
•Section 7.1.1: minor changes to text
•Table 6: measurements conditions changed: VBAT, Vx, IWAKE, VESD; table note section revised
•Table 8: parameter values/conditions changed: IOH and IOL for pin RXD, IIH for pins STB_N and EN;
parameters renamed: IO(sc)dom and IO(sc)rec
•Table 9: measurements conditions changed (tPD(TXD-RXD)); parameter tbit(RXD) added; Table note 2 and
Figure 7 added
•Section 12.2 “Application hints”: added
•Section 19.3: ‘Translations’ disclaimer added
TJA1043 v.3 20130424 Product data sheet - TJA1043 v.2
TJA1043 v.2 20110620 Product data sheet - TJA1043 v.1
TJA1043 v.1 20100330 Product data sheet - -
TJA1043 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 19 January 2015 27 of 29
NXP Semiconductors TJA1043
High-speed CAN transceiver
19. Legal information
19.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device (s) descr ibed in th is document m ay have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond tho se described in the
Product data sheet.
19.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggreg ate and cumulative li ability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductor s.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless ot herwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, lif e-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications an d ther efo re su ch inclusi on a nd/or use is at the cu stome r's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applicati ons or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objecti ve specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
TJA1043 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 19 January 2015 28 of 29
NXP Semiconductors TJA1043
High-speed CAN transceiver
No offer to sell or license — Nothing in this document may be interpret ed or
construed as an of fer to sell product s that is op en for accept ance or the grant ,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Quick reference data — The Quick reference dat a is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Translations — A non-English (translated) version of a docume nt is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
19.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors TJA1043
High-speed CAN transceiver
© NXP Semiconductors N.V. 2015. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 19 January 2015
Document identifier: TJA1043
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
21. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
2.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.2 Low-power management . . . . . . . . . . . . . . . . . 2
2.3 Protection and diagnosis (detection and
signalling) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7 Functional description . . . . . . . . . . . . . . . . . . . 5
7.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . 6
7.1.1 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 7
7.1.2 Listen-only mode . . . . . . . . . . . . . . . . . . . . . . . 7
7.1.3 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 8
7.1.4 Go-to-Sleep mode . . . . . . . . . . . . . . . . . . . . . . 8
7.1.5 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7.2 Internal flags. . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7.2.1 UVNOM flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7.2.2 UVBAT flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7.2.3 Pwon flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7.2.4 Wake flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7.2.5 Wake-up source flag. . . . . . . . . . . . . . . . . . . . 10
7.2.6 Bus failure flag . . . . . . . . . . . . . . . . . . . . . . . . 10
7.2.7 Local failure flag . . . . . . . . . . . . . . . . . . . . . . . 10
7.3 Local failures . . . . . . . . . . . . . . . . . . . . . . . . . 10
7.3.1 TXD dominant clamping detection . . . . . . . . . 10
7.3.2 TXD-to-RXD short-circuit de tection . . . . . . . . 10
7.3.3 Bus dominant clamping detection. . . . . . . . . . 11
7.3.4 Overtemperature detection. . . . . . . . . . . . . . . 11
7.4 SPLIT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.5 VIO supply pin. . . . . . . . . . . . . . . . . . . . . . . . . 11
7.6 WAKE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13
9 Thermal characteristics . . . . . . . . . . . . . . . . . 13
10 Static characteristics. . . . . . . . . . . . . . . . . . . . 14
11 Dynamic characteristics . . . . . . . . . . . . . . . . . 17
12 Application information. . . . . . . . . . . . . . . . . . 19
12.1 Application diagram . . . . . . . . . . . . . . . . . . . . 19
12.2 Application hints . . . . . . . . . . . . . . . . . . . . . . . 19
13 Test information. . . . . . . . . . . . . . . . . . . . . . . . 20
13.1 Quality information . . . . . . . . . . . . . . . . . . . . . 20
14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21
15 Handling information . . . . . . . . . . . . . . . . . . . 23
16 Soldering of SMD packages. . . . . . . . . . . . . . 23
16.1 Introduction to soldering. . . . . . . . . . . . . . . . . 23
16.2 Wave and reflow soldering. . . . . . . . . . . . . . . 23
16.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 23
16.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 24
17 Soldering of HVSON packages . . . . . . . . . . . 25
18 Revision history . . . . . . . . . . . . . . . . . . . . . . . 26
19 Legal information . . . . . . . . . . . . . . . . . . . . . . 27
19.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 27
19.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
19.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 27
19.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 28
20 Contact information . . . . . . . . . . . . . . . . . . . . 28
21 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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