ADUM2401XBZ - Analog Devices - Datasheet.Directory

Quad-Channel Digital Isolators, 5KV

Preliminary Technical Data

ADuM2400/ADuM2401/ADuM2402

Rev. PrD October 5, 2004

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FEATURES

Low power operation

5 V operation:

1.0 mA per channel max @ 0–2 Mbps

3.5 mA per channel max @ 10 Mbps

31 mA per channel max @ 90 Mbps

3 V operation:

0.7 mA per channel max @ 0–2 Mbps

2.1 mA per channel max @ 10 Mbps

20 mA per channel max @ 90 Mbps

Bidirectional communication

3 V/5 V level translation

High temperature operation: 105°C

High data rate: DC–90 Mbps (NRZ)

Precise timing characteristics:

2 ns max. pulsewidth distortion

2 ns max. channel-to-channel matching

High common-mode transient immunity: > 25 kV/μs

Output enable function

Wide body SOIC 16-lead package

Safety and regulatory approvals (pending)

UL recognition: 5000 V rms for 1 minute per UL 1577

CSA component acceptance notice #5A

VDE certificate of conformity

DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01

DIN EN 60950 (VDE 0805):2001-12;EN 60950:2000

VIORM = 848 V peak

IEC 60601-1

APPLICATIONS

General-purpose, high voltage, multichannel isolation

Medical Equipment

Motor Drives

Power Supplies

GENERAL DESCRIPTION

The ADuM240x are four-channel digital isolators based on

Analog Devices’ iCoupler® technology. Combining high speed

CMOS and monolithic air core transformer technology, these

isolation components provide outstanding performance

characteristics superior to alternatives such as optocoupler

devices. In comparison to the 2.5KV ADuM140x product

family, ADuM240x models have increased insulation thickness

to achieve the higher 5.0KV isolation rating.

By avoiding the use of LEDs and photodiodes, iCoupler devices

remove the design difficulties commonly associated with

optocouplers. The typical optocoupler concerns regarding

uncertain current transfer ratios, nonlinear transfer functions,

and temperature and lifetime effects are eliminated with the

simple, iCoupler digital interfaces and stable performance

characteristics. The need for external drivers and other discretes

is eliminated with these iCoupler products. Furthermore,

iCoupler devices run at one-tenth to one-sixth the power

consumption of optocouplers at comparable signal data rates.

The ADuM240x isolators provide four independent isolation

channels in a variety of channel configurations and data rates (see

Ordering Guide). All ADuM240x models operate with the supply

voltage of either side ranging from 2.7 V to 5.5 V, providing

compatibility with lower voltage systems as well as enabling a

voltage translation functionality across the isolation barrier. In

addition, the ADuM240x provides low pulse width distortion (<2

ns for CRWZ grade), and tight channel-to-channel matching (<2

ns for CRWZ grade). Unlike other optocoupler alternatives, the

ADuM240x isolators have a patented refresh feature that ensures

dc correctness in the absence of input logic transitions and during

power-up/power-down conditions.

FUNCTIONAL BLOCK DIAGRAMS

ENCODE DECODE

V

DD1

G

ND

1

V

IA

V

IB

V

IC

V

ID

NC

G

ND

1

V

DD2

GND

2

V

OA

V

OB

V

OC

V

OD

V

E2

GND

2

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

03786-0-001

Figure 1. ADuM2400 Functional Block Diagram

V

dd1

1

V

dd2

16

GND

1

2

GND

2

15

V

E1

7

V

E2

10

GND

1

8

GND

2

9

DECODE

ENCODE

3 14

V

IA

V

OA

DECODE

ENCODE

4 13

V

IB

V

OB

V

IC

5

V

OC

DECODE

ENCODE

6 11

V

OD

V

ID

ENCODE

DECODE

12

Figure 2. ADuM2401 Functional Block Diagram

DECODE

DECODE ENCODE

ENCODE

ENCODE DECODE

V

DD1

GND

1

V

IA

V

IB

V

OC

V

OD

V

E1

GND

1

V

DD2

GND

2

V

OA

V

OB

V

IC

V

ID

V

E2

GND

2

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

03786-0-003

Figure 3. ADuM2402 Functional Block Diagram

ADuM2400/ADuM2401/ADuM2402 Preliminary Technical Data

Rev. PrD| Page 2 of 23

ELECTRICAL CHARACTERISTICS—5 V OPERATION1

4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All min/max specifications apply over the entire recommended operation range, unless

otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V.

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent IDDI(Q) 0.50 0.53 mA

Output Supply Current, per Channel, Quiescent IDDO(Q) 0.19 0.21 mA

ADuM2400, Total Supply Current, Four Channels2

DC to 2 Mbps

V

DD1 Supply Current IDD1(Q) 2.2 2.8 mA DC to 1 MHz logic signal freq.

V

DD2 Supply Current IDD2(Q) 0.9 1.4 mA DC to 1 MHz logic signal freq.

10 Mbps (BRWZ and CRWZ Grades Only)

V

DD1 Supply Current IDD1(10) 8.6 10.6 mA 5 MHz logic signal freq.

V

DD2 Supply Current IDD2(10) 2.6 3.5 mA 5 MHz logic signal freq.

90 Mbps (CRWZ Grade Only)

V

DD1 Supply Current IDD1(90) 76 100 mA 45 MHz logic signal freq.

V

DD2 Supply Current IDD2(90) 21 25 mA 45 MHz logic signal freq.

ADuM2401, Total Supply Current, Four Channels2

DC to 2 Mbps

V

DD1 Supply Current IDD1(Q) 1.8 2.4 mA DC to 1 MHz logic signal freq.

V

DD2 Supply Current IDD2(Q) 1.2 1.8 mA DC to 1 MHz logic signal freq.

10 Mbps (BRWZ and CRWZ Grades Only)

V

DD1 Supply Current IDD1(10) 7.1 9.0 mA 5 MHz logic signal freq.

V

DD2 Supply Current IDD2(10) 4.1 5.0 mA 5 MHz logic signal freq.

90 Mbps (CRWZ Grade Only)

V

DD1 Supply Current IDD1(90) 62 82 mA 45 MHz logic signal freq.

V

DD2 Supply Current IDD2(90) 35 43 mA 45 MHz logic signal freq.

ADuM2402, Total Supply Current, Four Channels2

DC to 2 Mbps

V

DD1 or VDD2 Supply Current IDD1(Q),

IDD2(Q)

1.5 2.1 mA DC to 1 MHz logic signal freq.

10 Mbps (BRWZ and CRWZ Grades Only)

V

DD1 or VDD2 Supply Current IDD1(10),

IDD2(10)

5.6 7.0 mA 5 MHz logic signal freq.

90 Mbps (CRWZ Grade Only)

V

DD1 or VDD2 Supply Current IDD1(90),

IDD2(90)

49 62 mA 45 MHz logic signal freq.

For All Models

Input Currents IIA, IIB, IIC,

IID, IE1, IE2

–10 0.01 10 µA

0 ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,

0 ≤ VE1, VE2 ≤ VDD1 or VDD2

Logic High Input Threshold VIH, VEH 2.0 V

Logic Low Input Threshold VIL, VEL 0.8

VDD1, VDD2 – 0.1 5.0 V IOx = –20 µA, VIx = VIxH Logic High Output Voltages VOAH, VOBH,

VOCH, VODH VDD1, VDD2 – 0.4 4.8 V IOx = –4 mA, VIx = VIxH

0.0 0.1 V IOx = 20 µA, VIx = VIxL

0.04 0.1 V IOx = 400 µA, VIx = VIxL

Logic Low Output Voltages VOAL, VOBL,

VOCL, VODL

0.2 0.4 V IOx = 4 mA, VIx = VIxL

Preliminary Technical Data ADuM2400/ADuM2401/ADuM2402

Rev. PrD | Page 3 of 23

Parameter Symbol Min Typ Max Unit Test Conditions

SWITCHING SPECIFICATIONS

ADuM240xARW

Minimum Pulsewidth3 PW 1000 ns CL = 15 pF, CMOS signal levels

Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels

Propagation Delay5 t

PHL, tPLH 50 65 100 ns CL = 15 pF, CMOS signal levels

Pulsewidth Distortion, |tPLH-tPHL|5 PWD 40 ns CL = 15 pF, CMOS signal levels

Propagation Delay Skew6 t

PSK 50 ns CL = 15 pF, CMOS signal levels

Channel-to-Channel Matching7 t

PSKCD/OD 50 ns CL = 15 pF, CMOS signal levels

ADuM240xBRW

Minimum Pulsewidth3 PW 100 ns

Maximum Data Rate4 10 Mbps

CL = 15 pF, CMOS signal levels

Propagation Delay5 t

PHL, tPLH 20 32 50 ns CL = 15 pF, CMOS signal levels

Pulsewidth Distortion, |tPLH – tPHL|5 PWD 3 ns CL = 15 pF, CMOS signal levels

Change Versus Temperature 5 ps/°C CL = 15 pF, CMOS signal levels

Propagation Delay Skew6 t

PSK 15 ns CL = 15 pF, CMOS signal levels

Channel-to-Channel Matching, Co-Directional

Channels7

tPSKCD 3 ns CL = 15 pF, CMOS signal levels

Channel-to-Channel Matching, Opposing-Directional

Channels7

tPSKOD 6 ns CL = 15 pF, CMOS signal levels

ADuM240xCRW

Minimum Pulsewidth3 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels

Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels

Propagation Delay5 t

PHL, tPLH 18 27 32 ns CL = 15 pF, CMOS signal levels

Pulsewidth Distortion, |tPLH – tPHL|5 PWD 0.5 2 ns CL = 15 pF, CMOS signal levels

Change Versus Temperature 3 ps/°C CL = 15 pF, CMOS signal levels

Propagation Delay Skew6 t

PSK 10 ns CL = 15 pF, CMOS signal levels

Channel-to-Channel Matching, Co-Directional

Channels7

tPSKCD 2 ns CL = 15 pF, CMOS signal levels

Channel-to-Channel Matching, Opposing-Directional

Channels7

tPSKOD 5 ns CL = 15 pF, CMOS signal levels

For All Models

Output Disable Propagation Delay

(High/Low to High Impedance)

tPHZ, tPLH 6 8 ns CL = 15 pF, CMOS signal levels

Output Enable Propagation Delay

(High Impedance to High/Low)

tPZH, tPZL 6 8 ns CL = 15 pF, CMOS signal levels

Output Rise/Fall Time (10%–90%) tR/tF 2.5 ns CL = 15 pF, CMOS signal levels

Common-Mode Transient Immunity at Logic High

Output8

|CMH| 25 35 kV/µs

VIx = VDD1/DD2, VCM = 1000 V,

transient magnitude = 800 V

Common-Mode Transient Immunity at Logic Low

Output8

|CML| 25 35 kV/µs

VIx = 0 V, VCM = 1000 V,

transient magnitude = 800 V

Refresh Rate fr 1.2 Mbps

Input Dynamic Supply Current, per Channel9 I

DDI(D) 0.19 mA/Mbps

Output Dynamic Supply Current, per Channel9 I

DDO(D) 0.05 mA/Mbps

See Notes on next page.

ADuM2400/ADuM2401/ADuM2402 Preliminary Technical Data

Rev. PrD| Page 4 of 23

NOTES

1 All voltages are relative to their respective ground.

2 Supply current values are for all four channels combined running at identical data rates. Output supply current values are specified with no output load present. The

supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section on page 20 .

See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through

Figure 14 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM2400/ADuM2401/ADuM2402 channel configurations.

3 The minimum pulsewidth is the shortest pulsewidth at which the specified pulsewidth distortion is guaranteed.

4 The maximum data rate is the fastest data rate at which the specified pulsewidth distortion is guaranteed.

5 t

PHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay

is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

6 t

PSK is the magnitude of the worst-case difference in tPHL or tPLH that will be measured between units at the same operating temperature, supply voltages, and output

load within the recommended operating conditions.

7 Co-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels

with inputs on opposing sides of the isolation barrier.

8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8VDD2. CML is the maximum common-mode voltage slew rate

than can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The

transient magnitude is the range over which the common mode is slewed.

9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for

information on per-channel supply current for unloaded and loaded conditions. See Power Consumption section on page 19 for guidance on calculating per-

channel supply current for a given data rate.

Preliminary Technical Data ADuM2400/ADuM2401/ADuM2402

Rev. PrD | Page 5 of 23

ELECTRICAL CHARACTERISTICS—3 V OPERATION1

2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V. All min/max specifications apply over the entire recommended operation range, unless

otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V.

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent IDDI(Q) 0.26 0.31 mA

Output Supply Current, per Channel, Quiescent IDDO(Q) 0.11 0.14 mA

ADuM2400, Total Supply Current, Four Channels2

DC to 2 Mbps

V

DD1 Supply Current IDD1(Q) 1.2 1.9 mA DC to 1 MHz logic signal freq.

V

DD2 Supply Current IDD2(Q) 0.5 0.9 mA DC to 1 MHz logic signal freq.

10 Mbps (BRWZ and CRWZ Grades Only)

V

DD1 Supply Current IDD1(10) 4.5 6.5 mA 5 MHz logic signal freq.

V

DD2 Supply Current IDD2(10) 1.4 2.0 mA 5 MHz logic signal freq.

90 Mbps (CRWZ Grade Only)

V

DD1 Supply Current IDD1(90) 42 65 mA 45 MHz logic signal freq.

V

DD2 Supply Current IDD2(90) 11 15 mA 45 MHz logic signal freq.

ADuM2401, Total Supply Current, Four Channels2

DC to 2 Mbps

V

DD1 Supply Current IDD1(Q) 1.0 1.6 mA DC to 1 MHz logic signal freq.

V

DD2 Supply Current IDD2(Q) 0.7 1.2 mA DC to 1 MHz logic signal freq.

10 Mbps (BRWZ and CRWZ Grades Only)

V

DD1 Supply Current IDD1(10) 3.7 5.4 mA 5 MHz logic signal freq.

V

DD2 Supply Current IDD2(10) 2.2 3.0 mA 5 MHz logic signal freq.

90 Mbps (CRWZ Grade Only)

V

DD1 Supply Current IDD1(90) 34 52 mA 45 MHz logic signal freq.

V

DD2 Supply Current IDD2(90) 19 27 mA 45 MHz logic signal freq.

ADuM2402, Total Supply Current, Four Channels2

DC to 2 Mbps

V

DD1 or VDD2 Supply Current IDD1(Q),

IDD2(Q)

0.9 1.5 mA DC to 1 MHz logic signal freq.

10 Mbps (BRWZ and CRWZ Grades Only)

V

DD1 or VDD2 Supply Current IDD1(10),

IDD2(10)

3.0 4.2 mA 5 MHz logic signal freq.

90 Mbps (CRWZ Grade Only)

V

DD1 or VDD2 Supply Current IDD1(90),

IDD2(90)

27 39 mA 45 MHz logic signal freq.

For All Models

Input Currents IIA, IIB, IIC,

IID, IE1, IE2

–10 0.01 10 µA

0 ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,

0 ≤ VE1,VE2 ≤ VDD1 or VDD2

Logic High Input Threshold VIH, VEH 1.6 V

Logic Low Input Threshold VIL, VEL 0.4

VDD1, VDD2 – 0.1 3.0 V IOx = –20 µA, VIx = VIxH Logic High Output Voltages VOAH, VOBH,

VOCH, VODH VDD1, VDD2 – 0.4 2.8 V IOx = –4 mA, VIx = VIxH

0.0 0.1 V IOx = 20 µA, VIx = VIxL

0.04 0.1 V IOx = 400 µA, VIx = VIxL

Logic Low Output Voltages VOAL, VOBL,

VOCL, VODL

0.2 0.4 V IOx = 4 mA, VIx = VIxL

ADuM2400/ADuM2401/ADuM2402 Preliminary Technical Data

Rev. PrD| Page 6 of 23

Parameter Symbol Min Typ Max Unit Test Conditions

SWITCHING SPECIFICATIONS

ADuM240xARW

Minimum Pulsewidth3 PW 1000 ns CL = 15pF, CMOS signal levels

Maximum Data Rate4 1 Mbps CL = 15pF, CMOS signal levels

Propagation Delay5 t

PHL, tPLH 50 75 100 ns CL = 15pF, CMOS signal levels

Pulsewidth Distortion, |tPLH – tPHL|5 PWD 40 ns CL = 15pF, CMOS signal levels

Propagation Delay Skew6 t

PSK 50 ns CL = 15pF, CMOS signal levels

Channel-to-Channel Matching7 t

PSKCD/OD 50 ns CL = 15pF, CMOS signal levels

ADuM240xBRW

Minimum Pulsewidth3 PW 100 ns CL = 15pF, CMOS signal levels

Maximum Data Rate4 10 Mbps CL = 15pF, CMOS signal levels

Propagation Delay5 t

PHL, tPLH 20 38 50 ns CL = 15pF, CMOS signal levels

Pulsewidth Distortion, |tPLH – tPHL|5 PWD 3 ns CL = 15pF, CMOS signal levels

Change Versus Temperature 5 ps/°C CL = 15pF, CMOS signal levels

Propagation Delay Skew6 t

PSK 22 ns CL = 15pF, CMOS signal levels

Channel-to-Channel Matching, Co-Directional

Channels7

tPSKCD 3 ns CL = 15pF, CMOS signal levels

Channel-to-Channel Matching, Opposing-Directional

Channels7

tPSKOD 6 ns CL = 15pF, CMOS signal levels

ADuM240xCRW

Minimum Pulsewidth3 PW 8.3 11.1 ns CL = 15pF, CMOS signal levels

Maximum Data Rate4 90 120 Mbps CL = 15pF, CMOS signal levels

Propagation Delay5 t

PHL, tPLH 20 34 45 ns CL = 15pF, CMOS signal levels

Pulsewidth Distortion, |tPLH – tPHL|5 PWD 0.5 2 ns CL = 15pF, CMOS signal levels

Change Versus Temperature 3 ps/°C CL = 15pF, CMOS signal levels

Propagation Delay Skew6 t

PSK 16 ns CL = 15pF, CMOS signal levels

Channel-to-Channel Matching, Co-Directional

Channels7

tPSKCD 2 ns CL = 15pF, CMOS signal levels

Channel-to-Channel Matching, Opposing-Directional

Channels7

tPSKOD 5 ns CL = 15pF, CMOS signal levels

For All Models

Output Disable Propagation Delay

(High/Low to High Impedance)

tPHZ, tPLH 6 8 ns CL = 15pF, CMOS signal levels

Output Enable Propagation Delay

(High Impedance to High/Low)

tPZH, tPZL 6 8 ns CL = 15pF, CMOS signal levels

Output Rise/Fall Time (10%–90%) tR/tF 3 ns CL = 15pF, CMOS signal levels

Common Mode Transient Immunity at Logic High

Output8

|CMH| 25 35 kV/µs

VIx = VDD1/DD2, VCM = 1000 V,

transient magnitude = 800 V

Common Mode Transient Immunity at Logic Low

Output8

|CML| 25 35 kV/µs

VIx = 0 V, VCM = 1000 V,

transient magnitude = 800 V

Refresh Rate fr 1.1 Mbps

Input Dynamic Supply Current, per Channel9 I

DDI(D) 0.10 mA/Mbps

Output Dynamic Supply Current, per Channel9 I

DDO(D) 0.03 mA/Mbps

See Notes on next page.

Preliminary Technical Data ADuM2400/ADuM2401/ADuM2402

Rev. PrD | Page 7 of 23

NOTES

1 All voltages are relative to their respective ground.

2 Supply current values are for all four channels combined running at identical data rates. Output supply current values are specified with no output load present. The

supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section on page 20 .

See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through

Figure 14 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM2400/ADuM2401/ADuM2402 channel configurations.

3 The minimum pulsewidth is the shortest pulsewidth at which the specified pulsewidth distortion is guaranteed.

4 The maximum data rate is the fastest data rate at which the specified pulsewidth distortion is guaranteed.

5 t

PHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay

is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

6 t

PSK is the magnitude of the worst-case difference in tPHL or tPLH that will be measured between units at the same operating temperature, supply voltages, and output

load within the recommended operating conditions.

7 Co-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels

with inputs on opposing sides of the isolation barrier.

8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8VDD2. CML is the maximum common-mode voltage slew rate

than can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The

transient magnitude is the range over which the common mode is slewed.

9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for

information on per-channel supply current for unloaded and loaded conditions. See Power Consumption section on page 19 for guidance on calculating per-

channel supply current for a given data rate.

ADuM2400/ADuM2401/ADuM2402 Preliminary Technical Data

Rev. PrD| Page 8 of 23

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION1

5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V. 3 V/5 V operation: 2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All min/max

specifications apply over the entire recommended operation range, unless otherwise noted.

All typical specifications are at TA=25°C; VDD1 = 3.0 V, VDD2 = 5 V; or VDD1 = 5 V, VDD2 = 3.0 V.

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions

DC SPECIFICATIONS

Input Supply Current, per Channel, Quiescent IDDI(Q)

5 V/3 V Operation 0.50 0.53 mA

3 V/5 V Operation 0.26 0.31 mA

Output Supply Current, per Channel, Quiescent IDDO(Q)

5 V/3 V Operation 0.11 0.14 mA

3 V/5 V Operation 0.19 0.21 mA

ADuM2400, Total Supply Current, Four Channels2

DC to 2 Mbps

V

DD1 Supply Current IDD1(Q)

5 V/3 V Operation 2.2 2.8 mA DC to 1 MHz logic signal freq.

3 V/5 V Operation 1.2 1.9 mA DC to 1 MHz logic signal freq.

V

DD2 Supply Current IDD2(Q)

5 V/3 V Operation 0.5 0.9 mA DC to 1 MHz logic signal freq.

3 V/5 V Operation 0.9 1.4 mA DC to 1 MHz logic signal freq.

10 Mbps (BRWZ and CRWZ Grades Only)

V

DD1 Supply Current IDD1(10)

5 V/3 V Operation 8.6 10.6 mA 5 MHz logic signal freq.

3 V/5 V Operation 4.5 6.5 mA 5 MHz logic signal freq.

V

DD2 Supply Current IDD2(10)

5 V/3 V Operation 1.4 2.0 mA 5 MHz logic signal freq.

3 V/5 V Operation 2.6 3.5 mA 5 MHz logic signal freq.

90 Mbps (CRWZ Grade Only)

V

DD1 Supply Current IDD1(90)

5 V/3 V Operation 76 100 mA 45 MHz logic signal freq.

3 V/5 V Operation 42 65 mA 45 MHz logic signal freq.

V

DD2 Supply Current IDD2(90)

5 V/3 V Operation 11 15 mA 45 MHz logic signal freq.

3 V/5 V Operation 21 25 mA 45 MHz logic signal freq.

ADuM2401, Total Supply Current, Four Channels2

DC to 2 Mbps

V

DD1 Supply Current IDD1(Q)

5 V/3 V Operation 1.8 2.4 mA DC to 1 MHz logic signal freq.

3 V/5 V Operation 1.0 1.6 mA DC to 1 MHz logic signal freq.

V

DD2 Supply Current IDD2(Q)

5 V/3 V Operation 0.7 1.2 mA DC to 1 MHz logic signal freq.

3 V/5 V Operation 1.2 1.8 mA DC to 1 MHz logic signal freq.

10 Mbps (BRWZ and CRWZ Grades Only)

V

DD1 Supply Current IDD1(10)

5 V/3 V Operation 7.1 9.0 mA 5 MHz logic signal freq.

3 V/5 V Operation 3.7 5.4 mA 5 MHz logic signal freq.

V

DD2 Supply Current IDD2(10)

5 V/3 V Operation 2.2 3.0 mA 5 MHz logic signal freq.

3 V/5 V Operation 4.1 5.0 mA 5 MHz logic signal freq.

90 Mbps (CRWZ Grade Only)

V

DD1 Supply Current IDD1(90)

Preliminary Technical Data ADuM2400/ADuM2401/ADuM2402

Rev. PrD | Page 9 of 23

Parameter Symbol Min Typ Max Unit Test Conditions

5 V/3 V Operation 62 82 mA 45 MHz logic signal freq.

3 V/5 V Operation 34 52 mA 45 MHz logic signal freq.

V

DD2 Supply Current IDD2(90)

5 V/3 V Operation 19 27 mA 45 MHz logic signal freq.

3 V/5 V Operation 35 43 mA 45 MHz logic signal freq.

ADuM2402, Total Supply Current, Four Channels2

DC to 2 Mbps

V

DD1 Supply Current IDD1(Q)

5 V/3 V Operation 1.5 2.1 mA DC to 1 MHz logic signal freq.

3 V/5 V Operation 0.9 1.5 mA DC to 1 MHz logic signal freq.

V

DD2 Supply Current IDD2(Q)

5 V/3 V Operation 0.9 1.5 mA DC to 1 MHz logic signal freq.

3 V/5 V Operation 1.5 2.1 mA DC to 1 MHz logic signal freq.

10 Mbps (BRWZ and CRWZ Grades Only)

V

DD1 Supply Current IDD1(10)

5 V/3 V Operation 5.6 7.0 mA 5 MHz logic signal freq.

3 V/5 V Operation 3.0 4.2 mA 5 MHz logic signal freq.

V

DD2 Supply Current IDD2(10)

5 V/3 V Operation 3.0 4.2 mA 5 MHz logic signal freq.

3 V/5 V Operation 5.6 7.0 mA 5 MHz logic signal freq.

90 Mbps (CRWZ Grade Only)

V

DD1 Supply Current IDD1(90)

5 V/3 V Operation 49 62 mA 45 MHz logic signal freq.

3 V/5 V Operation 27 39 mA 45 MHz logic signal freq.

V

DD2 Supply Current IDD2(90)

5 V/3 V Operation 27 39 mA 45 MHz logic signal freq.

3 V/5 V Operation 49 62 mA 45 MHz logic signal freq.

For All Models

Input Currents IIA, IIB, IIC,

IID, IE1, IE2

–10 0.01 10 µA

0 ≤ VIA,VIB, VIC,VID ≤ VDD1 or VDD2,

0 ≤ VE1,VE2 ≤ VDD1 or VDD2

Logic High Input Threshold VIH, VEH

5 V/3 V Operation 2.0 V

3 V/5 V Operation 1.6 V

Logic Low Input Threshold VIL, VEL

5 V/3 V Operation 0.8 V

3 V/5 V Operation 0.4 V

VDD1/VDD2 – 0.1 VDD1/

VDD2

V IOx = –20 µA, VIx = VIxH Logic High Output Voltages VOAH, VOBH,

VOCH, VODH

VDD1/VDD2 – 0.4 VDD1/

VDD2

– 0.2

V IOx = –4 mA, VIx = VIxH

0.0 0.1 V IOx = 20 µA, VIx = VIxL

0.04 0.1 V IOx = 400 µA, VIx = VIxL

Logic Low Output Voltages VOAL, VOBL,

VOCL, VODL

0.2 0.4 V IOx = 4 mA, VIx = VIxL

SWITCHING SPECIFICATIONS

ADuM240xARW

Minimum Pulsewidth3 PW 1000 ns CL = 15pF, CMOS signal levels

Maximum Data Rate4 1 Mbps CL = 15pF, CMOS signal levels

Propagation Delay5 t

PHL, tPLH 50 70 100 ns CL = 15pF, CMOS signal levels

Pulsewidth Distortion, |tPLH – tPHL|5 PWD 40 ns CL = 15pF, CMOS signal levels

Propagation Delay Skew6 t

PSK 50 ns CL = 15pF, CMOS signal levels

Channel-to-Channel Matching7 t

PSKCD/OD 50 ns CL = 15pF, CMOS signal levels

ADuM240xBRW

ADuM2400/ADuM2401/ADuM2402 Preliminary Technical Data

Rev. PrD| Page 10 of 23

Parameter Symbol Min Typ Max Unit Test Conditions

Minimum Pulsewidth3 PW 100 ns

Maximum Data Rate4 10 Mbps

CL = 15pF,CMOS signal levels

CL = 15pF, CMOS signal levels

Propagation Delay5 t

PHL, tPLH 15 35 50 ns CL = 15pF, CMOS signal levels

Pulsewidth Distortion, |tPLH – tPHL|5 PWD 3 ns CL = 15pF, CMOS signal levels

Change Versus Temperature 5 ps/°C CL = 15pF, CMOS signal levels

Propagation Delay Skew6 t

PSK 22 ns CL = 15pF, CMOS signal levels

Channel-to-Channel Matching, Co-Directional

Channels7

tPSKCD 3 ns CL = 15pF, CMOS signal levels

Channel-to-Channel Matching, Opposing-Directional

Channels7

tPSKOD 6 ns CL = 15pF, CMOS signal levels

ADuM240xCRW

Minimum Pulsewidth3 PW 8.3 11.1 ns

Maximum Data Rate4 90 120 Mbps

CL = 15pF, CMOS signal levels

Propagation Delay5 t

PHL, tPLH 20 30 40 ns CL = 15pF, CMOS signal levels

Pulsewidth Distortion, |tPLH-tPHL|5 PWD 0.5 2 ns CL = 15pF, CMOS signal levels

Change Versus Temperature 3 ps/°C CL = 15pF, CMOS signal levels

Propagation Delay Skew6 t

PSK 14 ns CL = 15pF, CMOS signal levels

Channel-to-Channel Matching, Co-Directional

Channels7

tPSKCD 2 ns CL = 15pF, CMOS signal levels

Channel-to-Channel Matching, Opposing-Directional

Channels7

tPSKOD 5 ns CL = 15pF, CMOS signal levels

For All Models

Output Disable Propagation Delay

(High/Low to High Impedance)

tPHZ, tPLH 6 8 ns CL = 15pF, CMOS signal levels

Output Enable Propagation Delay

(High Impedance to High/Low)

tPZH, tPZL 6 8 ns CL = 15pF, CMOS signal levels

Output Rise/Fall Time (10-90%) tR/tf C

L = 15pF, CMOS signal levels

5 V/3 V Operation 3.0 ns

3 V/5 V Operation 2.5 ns

Common-Mode Transient Immunity at

Logic High Output8

|CMH| 25 35 kV/µs

VIx = VDD1/DD2, VCM = 1000 V,

transient magnitude = 800 V

Common-Mode Transient Immunity at

Logic Low Output8

|CML| 25 35 kV/µs VIx = 0 V, VCM = 1000 V,

transient magnitude = 800 V

Refresh Rate fr

5 V/3 V Operation 1.2 Mbps

3 V/5 V Operation 1.1 Mbps

Input Dynamic Supply Current, per Channel9 I

DDI(D)

5 V/3 V Operation 0.19 mA/Mbps

3 V/5 V Operation 0.10 mA/Mbps

Output Dynamic Supply Current, per Channel9 I

DDI(D)

5 V/3 V Operation 0.03 mA/Mbps

3 V/5 V Operation 0.05 mA/Mbps

See Notes on next page.

Preliminary Technical Data ADuM2400/ADuM2401/ADuM2402

Rev. PrD | Page 11 of 23

NOTES

1 All voltages are relative to their respective ground.

2 Supply current values are for all four channels combined running at identical data rates. Output supply current values are specified with no output load present. The

supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section on page 20.

See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through

Figure 14 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM2400/ADuM2401/ADuM2402 channel configurations.

3 The minimum pulsewidth is the shortest pulsewidth at which the specified pulsewidth distortion is guaranteed.

4 The maximum data rate is the fastest data rate at which the specified pulsewidth distortion is guaranteed.

5 t

PHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay

is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.

6 t

PSK is the magnitude of the worst-case difference in tPHL or tPLH that will be measured between units at the same operating temperature, supply voltages, and output

load within the recommended operating conditions.

7 Co-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of

the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels

with inputs on opposing sides of the isolation barrier.

8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8VDD2. CML is the maximum common-mode voltage slew rate

than can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The

transient magnitude is the range over which the common mode is slewed.

9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for

information on per-channel supply current for unloaded and loaded conditions. See Power Consumption section on page 19 for guidance on calculating per-

channel supply current for a given data rate.

ADuM2400/ADuM2401/ADuM2402 Preliminary Technical Data

Rev. PrD| Page 12 of 23

PACKAGE CHARACTERISTICS

Table 4.

Parameter Symbol Min Typ Max Unit Test Conditions

Resistance (Input-Output)1 R

I-O 1012 Ω

Capacitance (Input-Output)1 CI-O 2.2 pF f = 1 MHz

Input Capacitance2 C

I 4.0 pF

IC Junction-to-Case Thermal Resistance, Side 1 θjci 33 °C/W

IC Junction-to-Case Thermal Resistance, Side 2 θjco 28 °C/W

Thermocouple located

at center of package

underside

NOTES

1 Device considered a two-terminal device: Pins 1, 2, 3, 4, 5, 6, 7, and 8 shorted together and Pins 9, 10, 11, 12, 13, 14, 15, and 16 shorted together.

2 Input capacitance is from any input data pin to ground.

REGULATORY INFORMATION (PENDING)

The ADuM240x will approved upon product release by the following organizations:

Table 5.

UL1 CSA VDE2

Recognized under 1577

component recognition program1

Double insulation, 5000 V rms

isolation voltage

Approved under CSA Component

Acceptance Notice #5A

Reinforced insulation per

CSA 60950-1-03 and IEC 60950-1,

400 V rms maximum working

voltage

Approved per IEC 60601-1

Reinforced insulation, 250 V rms

maximum working voltage

Certified according to DIN EN 60747-5-2

(VDE 0884 Part 2):2003-012

Basic insulation, 848 V peak

Complies with DIN EN 60747-5-2 (VDE 0884 Part 2):2003-01,

DIN EN 60950 (VDE 0805):2001-12; EN 60950:2000

Reinforced insulation, 565 V peak

NOTES

1 In accordance with UL1577, each ADuM240x is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 5 µA).

2 In accordance with DIN EN 60747-5-2, each ADuM240x is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 second (partial discharge detection

limit = 5 pC).

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 6.

Parameter Symbol Value Unit Conditions

Rated Dielectric Insulation Voltage 5000 V rms 1 minute duration.

Minimum External Air Gap (Clearance) L(I01) 7.45 min. mm Measured from input terminals to output terminals,

shortest distance through air.

Minimum External Tracking (Creepage) L(I02) 8.10 min. mm Measured from input terminals to output terminals,

shortest distance path along body.

Minimum Internal Gap (Internal Clearance) 0.025 min. mm Insulation distance through insulation.

Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1.

Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1).

Preliminary Technical Data ADuM2400/ADuM2401/ADuM2402

Rev. PrD | Page 13 of 23

DIN EN 60747-5-2 (VDE 0884 PART 2) INSULATION CHARACTERISTICS (PENDING)

Table 7.

Description Symbol Characteristic Unit

Installation classification per DIN VDE 0110

For Rated Mains Voltage ≤ 300 V rms

For Rated Mains Voltage ≤ 600 V rms

I–IV

I–III

Climatic Classification 40/105/21

Pollution Degree (DIN VDE 0110, Table 1) 2

Maximum Working Insulation Voltage VIORM 848 V peak

Input to Output Test Voltage, Method b1

V

IORM × 1.875 = VPR, 100% Production Test,

t

m = 1 sec, Partial Discharge < 5 pC

VPR 1590 V peak

Input to Output Test Voltage, Method a

After Environmental Tests Subgroup 1)

V

IORM × 1.6 = VPR, tm = 60 sec, Partial Discharge < 5p C

After Input and/or Safety Test Subgroup 2/3)

V

IORM × 1.2 = VPR, tm = 60 sec, Partial Discharge < 5p C

VPR

1356

1018

V peak

Highest Allowable Overvoltage

(Transient Overvoltage, tTR = 10 sec)

VTR 6000 V peak

Safety-Limiting Values (Maximum value allowed in the event of a failure, also see Thermal

Derating Curve, Figure 4)

Case Temperature

Side 1 Current

Side 2 Current

TS

IS1

IS2

150

265

335

°C

mA

Insulation Resistance at TS, VIO = 500 V RS >109 Ω

This isolator is suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data shall be ensured by

means of protective circuits.

"*" marking on packages denotes DIN EN 60747-5-2 approval for 560 V peak working voltage.

CASE TEMPERATURE (°C)

SAFETY-LIMITING CURRENT (mA)

0

350

300

250

200

150

100

50

50 100 150 200

SIDE #1

SIDE #2

03787-0-003

Figure 4. Thermal Derating Curve, Dependence of Safety Limiting Values

with Case Temperature per DIN EN 60747-5-2

RECOMMENDED OPERATING CONDITIONS

Table 8.

Parameter Symbol Min Max Unit

Operating Temperature TA –40 +105 °C

Supply Voltages1 V

DD1, VDD 2 2.7 5.5 V

Input Signal Rise and Fall Times 1.0 ms

NOTE

1 All voltages are relative to their respective ground.

See the DC Correctness and Magnetic Field Immunity section on page 19

for information on immunity to external magnetic fields.

ADuM2400/ADuM2401/ADuM2402 Preliminary Technical Data

Rev. PrD| Page 14 of 23

ABSOLUTE MAXIMUM RATINGS

Table 9.

Parameter Symbol Min Max Unit

Storage Temperature TST –65 150 °C

Ambient Operating Temperature TA –40 105 °C

Supply Voltages1 V

DD1, VDD2 –0.5 7.0 V

Input Voltage1, 2 VIA, VIB, VIC, VID, VE1,VE2 –0.5 VDDI + 0.5 V

Output Voltage1, 2 VOA, VOB, VOC, VOD –0.5 VDDO + 0.5 V

Average Output Current, Per Pin3

Side 1 IO1 –18 18 mA

Side 2 IO2 –22 22 mA

Common-Mode Transients4 –100 +100 kV/µs

NOTES

1 All voltages are relative to their respective ground.

2 V

DDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See PC Board Layout section.

3 See Figure 4 for maximum rated current values for various temperatures.

4 Refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the Absolute Maximum Rating may cause latch-up or

permanent damage.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;

functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Ambient temperature =

25°C, unless otherwise noted.

Table 10. Truth Table (Positive Logic)

VIX Input1 V

EX Input VDDI State1 V

DDO State1 V

OX Output1 Note

H H or NC Powered Powered H

L H or NC Powered Powered L

X L Powered Powered Z

X H or NC Unpowered Powered H Outputs returns to input state within 1 µs of VDDI power restoration.

X L Unpowered Powered Z

X X Powered Unpowered Indeterminate Outputs returns to input state within 1 µs of VDDO power restoration if

VEX state is H or NC. Outputs returns to high impedance state within

8 ns of VDDO power restoration if VEX state is L.

NOTE

1 V

IX and VOX refer to the input and output signals of a given channel (A, B, C, or D). VEX refers to the output enable signal on the same side as the VOX outputs. VDDI and

VDDO refer to the supply voltages on the input and output sides of the given channel, respectively.

Preliminary Technical Data ADuM2400/ADuM2401/ADuM2402

Rev. PrD | Page 15 of 23

PIN CONFIGURATIONS AND PIN FUNCTION DESCRIPTIONS

PIN CONFIGURATIONS

Figure 5. ADuM2400 Pin Configuration

Figure 6. ADuM2401 Pin Configuration

Figure 7. ADuM2402 Pin Configuration

* Pins 2 and 8 are internally connected. Connecting both to GND1 is recommended. Pins 9 and 15 are internally connected. Connecting both to GND2 is recommended.

Output enable Pin 10 on the ADuM2400 may be left disconnected if outputs are to be always enabled. Output enable Pins 7 and 10 on the ADuM2401/ADuM2402

may be left disconnected if outputs are to be always enabled. In noisy environments, connecting Pin 7 (for ADuM2401 and ADuM2402) and Pin 10 (for all models) to

an external logic high or low is recommended.

NC = NO CONNECT

ADuM2400

TOP V IEW

(Not to Scale)

03786-0-005

*GND

NC = NO CONNECT

ADuM2401

TOP V IEW

(Not to Scale)

03786-0-006 NC = NO CONNECT

ADuM2402

TOP V IEW

(Not to Scale)

03786-0-007

*GND 2

3

5

16

15

14

13

12

11

10

9

V

DD2

GND

2

*

V

OA

V

OB

V

OC

V

OD

V

E2

GND

2

*

1

2

3

4

5

6

7

8

V

DD1

1

V

IA

V

IB

V

IC

V

ID

NC

1

2

3

4

5

6

7

8

VDD1

*GND1

VIA

VIB

VIC

VOD

VE1

*GND1

16

15

14

13

12

11

10

9

VDD2

GND2*

VOA

VOB

VOC

VID

VE2

GND2*

V

DD1

1

V

IA

V

IB

V

OC

V

OD

V

E1

1

*GND

16

15

14

13

12

11

10

9

VDD2

GND2*

VOA

VOB

VIC

VID

VE2

GND2*

1

4

6

7

8

ADuM2400/ADuM2401/ADuM2402 Preliminary Technical Data

Rev. PrD| Page 16 of 23

PIN FUNCTION DESCRIPTIONS

Table 11. ADuM2400 Pin Function Descriptions

No. Mnemonic Function

1 VDD1 Supply voltage for isolator Side 1, 2.7 V to 5.5 V.

2 GND1 Ground 1. Ground reference for isolator Side 1.

3 VIA Logic input A.

4 VIB Logic input B.

5 VIC Logic input C.

6 VID Logic input D.

7 NC No Connect.

8 GND1 Ground 1. Ground reference for isolator Side 1.

9 GND2 Ground 2. Ground reference for isolator Side 2.

10 VE2 Output enable 2. Active high logic input. VOA, VOB,

VOC, and VOD outputs are enabled when VE2 is high

or disconnected. VOA, VOB, VOC, and VOD outputs are

disabled when VE2 is low.

11 VOD Logic output D.

12 VOC Logic output C.

13 VOB Logic output B.

14 VOA Logic output A.

15 GND2 Ground 2. Ground reference for isolator Side 2.

16 VDD2 Supply voltage for isolator Side 2, 2.7 V to 5.5 V.

Table 12. ADuM2401 Pin Function Descriptions

No. Mnemonic Function

1 VDD1 Supply voltage for isolator Side 1, 2.7 V to 5.5 V.

2 GND1 Ground 1. Ground reference for isolator Side 1.

3 VIA Logic input A.

4 VIB Logic input B.

5 VIC Logic input C.

6 VOD Logic output D.

7 VE1 Output enable 1. Active high logic input. VOD output

is enabled when VE1 is high or disconnected. VOD is

disabled when VE1 is low.

8 GND1 Ground 1. Ground reference for isolator Side 1.

9 GND2 Ground 2. Ground reference for isolator Side 2.

10 VE2 Output enable 2. Active high logic input. VOA, VOB,

and VOC outputs are enabled when VE2 is high or

disconnected. VOA, VOB, and VOC outputs are

disabled when VE2 is low.

11 VID Logic input D.

12 VOC Logic output C.

13 VOB Logic output B.

14 VOA Logic output A.

15 GND2 Ground 2. Ground reference for isolator Side 2.

16 VDD2 Supply voltage for isolator Side 1, 2.7 V to 5.5 V.

Table 13. ADuM2402 Pin Function Descriptions

No. Mnemonic Function

1 VDD1 Supply voltage for isolator Side 1, 2.7 V to 5.5 V.

2 GND1 Ground 1. Ground reference for isolator Side 1.

3 VIA Logic input A.

4 VIB Logic input B.

5 VOC Logic output C.

6 VOD Logic output D.

7 VE1 Output enable 1. Active high logic input. VOC and

VOD outputs are enabled when VE1 is high or

disconnected. VOC and VOD outputs are disabled

when VE1 is low.

8 GND1 Ground 1. Ground reference for isolator Side 1.

9 GND2 Ground 2. Ground reference for isolator Side 2.

10 VE2 Output enable 2. Active high logic input. VOA and

VOB outputs are enabled when VE2 is high or

disconnected. VOA and VOB outputs are disabled

when VE2 is low.

11 VID Logic input D.

12 VIC Logic input C.

13 VOB Logic output B.

14 VOA Logic output A.

15 GND2 Ground 2. Ground reference for isolator Side 2.

16 VDD2 Supply voltage for isolator Side 2, 2.7 V to 5.5 V.

Preliminary Technical Data ADuM2400/ADuM2401/ADuM2402

Rev. PrD | Page 17 of 23

TYPICAL PERFORMANCE CHARACTERISTICS

04407-0-011

DATA RATE (Mbps)

CURRENT/CHANNEL (mA)

0

10

5

15

20

20 60 8040 100

5V

3V

Figure 8. Typical Input Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation

04407-0-012

DATA RATE (Mbps)

CURRENT/CHANNEL (mA)

0

3

2

1

4

5

6

20 60 8040 100

5V

3V

Figure 9. Typical Output Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation (No Output Load)

04407-0-013

DATA RATE (Mbps)

CURRENT/CHANNEL (mA)

0

6

4

2

8

10

20 60 8040 100

5V

3V

Figure 10. Typical Output Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation (15 pF Output Load)

04407-0-014

DATA RATE (Mbps)

CURRENT (mA)

0

40

50

20

10

30

60

70

80

20 60 8040 100

5V

3V

Figure 11. Typical ADuM2400 VDD1 Supply Current vs. Data Rate

for 5 V and 3 V Operation

04407-0-015

DATA RATE (Mbps)

CURRENT (mA)

0

10

5

15

20

20 60 8040 100

5V

3V

Figure 12. Typical ADuM2400 VDD2 Supply Current vs. Data Rate

for 5 V and 3 V Operation

04407-0-016

DATA RATE (Mbps)

CURRENT (mA)

0

25

20

15

10

5

30

50

20 60 8040 100

5V

3V

Figure 13. Typical ADuM2401 VDD1 Supply Current vs. Data Rate

for 5 V and 3 V Operation

ADuM2400/ADuM2401/ADuM2402 Preliminary Technical Data

Rev. PrD| Page 18 of 23

04407-0-017

DATA RATE (Mbps)

CURRENT (mA)

0

20

15

10

5

30

25

35

40

20 60 8040 100

5V

3V

Figure 14. Typical ADuM2401 VDD2 Supply Current vs. Data Rate

for 5 V and 3 V Operation

04407-0-018

DATA RATE (Mbps)

CURRENT (mA)

0

25

20

15

10

5

45

40

35

30

50

20 60 8040 100

5V

3V

Figure 15. Typical ADuM2402 VDD1 or VDD2 Supply Current vs.

Data Rate for 5 V and 3 V Operation

TEMPERATURE (°C)

PROPAGATION DELAY (ns)

–50 –25

25

30

35

40

0507525 100

03786-0-023

3V

5V

Figure 16. Propagation Delay vs. Temperature, C Grade.

Preliminary Technical Data ADuM2400/ADuM2401/ADuM2402

Rev. PrD | Page 19 of 23

APPLICATION INFORMATION

PC BOARD LAYOUT

The ADuM240x digital isolator requires no external interface

circuitry for the logic interfaces. Power supply bypassing is

strongly recommended at the input and output supply pins

(Figure 17). Bypass capacitors are most conveniently connected

between Pins 1 and 2 for VDD1 and between Pins 15 and 16 for

VDD2. The capacitor value should be between 0.01 µF and 0.1 µF.

The total lead length between both ends of the capacitor and

the input power supply pin should not exceed 20 mm.

Bypassing between Pins 1 and 8 and between Pins 9 and 16

should also be considered unless the ground pair on each

package side are connected close to the package.

VDD1

GND1

VIA

VIB

V

IC/OC

V

ID/OD

VE1

GND1

VDD2

GND2

VOA

VOB

VOC/IC

VOD/ID

VE2

GND2

03786-0-019

Figure 17. Recommended Printed Circuit Board Layout

In applications involving high common-mode transients, care

should be taken to ensure that board coupling across the

isolation barrier is minimized. Furthermore, the board layout

should be designed such that any coupling that does occur

equally affects all pins on a given component side. Failure to

ensure this could cause voltage differentials between pins

exceeding the device’s Absolute Maximum Ratings, thereby

leading to latch-up or permanent damage.

PROPAGATION DELAY-RELATED PARAMETERS

Propagation delay is a parameter that describes the length of

time it takes for a logic signal to propagate through a

component. The propagation delay to a logic low output may

differ from the propagation delay to a logic high.

INPUT (V

IX

)

OUTPUT (V

OX

)

t

PLH

t

PHL

50%

03786-0-020

Figure 18. Propagation Delay Parameters

Pulsewidth distortion is the maximum difference between these

two propagation delay values and is an indication of how

accurately the input signal’s timing is preserved.

Channel-to-channel matching refers to the maximum amount

the propagation delay differs among channels within a single

ADuM240x component.

Propagation delay skew refers to the maximum amount the

propagation delay differs among multiple ADuM240x

components operated under the same conditions.

DC CORRECTNESS AND MAGNETIC FIELD

IMMUNITY

Positive and negative logic transitions at the isolator input cause

narrow (~1 ns) pulses to be sent via the transformer to the

decoder. The decoder is bistable and is therefore either set or

reset by the pulses indicating input logic transitions. In the

absence of logic transitions at the input for more than 2 µs, a

periodic set of "refresh" pulses indicative of the correct input

state are sent to ensure "dc correctness" at the output. If the

decoder receives no pulses for more than about 5 µs, the input

side is assumed to be unpowered or nonfunctional, in which

case the isolator output is forced to a default state (see Table 10)

by the watchdog timer circuit.

The limitation on the ADuM240x’s magnetic field immunity is

set by the condition in which induced voltage in the transformer’s

“receiving” coil is sufficiently large to either falsely set or reset the

decoder. The analysis below defines the conditions under which

this may occur. The 3 V operating condition of the ADuM240x is

examined as it represents the most susceptible mode of operation.

The pulses at the transformer output have an amplitude greater than

1.0 V. The decoder has a sensing threshold at about 0.5 V, therefore

establishing a 0.5 V margin in which induced voltages can be

tolerated. The voltage induced across the “receiving” coil is given by:

V = (–dβ/dt)∑∏rn2; n = 1, 2,…, N

where:

β is magnetic flux density (gauss)

N is the number of turns in the receiving coil.

rn is the radius of the nth turn in the receiving coil (cm).

Given the geometry of the receiving coil in the ADuM240x and

an imposed requirement that the induced voltage be at most

50% of the 0.5 V margin at the decoder, a maximum allowable

magnetic field is calculated as shown in below in Figure 19.

ADuM2400/ADuM2401/ADuM2402 Preliminary Technical Data

Rev. PrD| Page 20 of 23

MAGNETIC FIELD FREQUENCY (Hz)

100

MAXIMUM ALLOWABLE MAGNETIC FLUX

DENSITY (kgauss)

0.001 1M

10

0.01

1k 10k 10M

0.1

1

100M100k

03786-0-021

Figure 19. Maximum Allowable External Magnetic Flux Density

For example, at a magnetic field frequency of 1 MHz, the

maximum allowable magnetic field of 0.2 kgauss induces a

voltage of 0.25 V at the receiving coil. This is about 50% of the

sensing threshold and will not cause a faulty output transition.

Similarly, if such an event were to occur during a transmitted

pulse (and was of the worst case polarity) it would reduce the

received pulse from > 1.0 V to 0.75 V—still well above the 0.5 V

sensing threshold of the decoder.

The preceding magnetic flux density values correspond to specific

current magnitudes at given distances away from the ADuM240x

transformers. Figure 20 expresses these allowable current

magnitudes as a function of frequency for selected distances. As can

be seen, the ADuM240x is extremely immune and can be affected

only by extremely large currents operated at high frequency and very

close to the component. For the 1 MHz example noted, one would

have to place a 0.5 kA current 5 mm away from the ADuM240x to

affect the component’s operation.

MAGNETIC FIELD FREQUENCY (Hz)

MAXIMUM ALLOWABLE CURRENT (kA)

1000

100

10

1

0.1

0.011k 10k 100M100k 1M 10M

DISTANCE = 5mm

DISTANCE = 1m

DISTANCE = 100mm

03786-0-022

Figure 20. Maximum Allowable Current

for Various Current-to-ADuM240x Spacings

Note that at combinations of strong magnetic field and high

frequency, any loops formed by printed circuit board traces

could induce sufficiently large error voltages to trigger the

thresholds of succeeding circuitry. Care should be taken in the

layout of such traces to avoid this possibility.

POWER CONSUMPTION

The supply current at a given channel of the ADuM240x

isolator is a function of the supply voltage, the channel’s data

rate, and the channel’s output load.

For each input channel, the supply current is given by:

IDDI = IDDI(Q) f ≤ 0.5fr

IDDI = IDDI(D) × (2f – fr) + IDDI(Q) f > 0.5fr

For each output channel, the supply current is given by:

IDDO = IDDO(Q) f ≤ 0.5fr

IDDO = (IDDO(D) + (0.5 x 10-3 × CLVDDO) × (2f – fr) + IDDO(Q) f > 0.5fr

where:

IDDI(D), IDDO(D) are the input and output dynamic supply currents

per channel (mA/Mbps).

CL is output load capacitance (pF).

VDDO is the output supply voltage (V).

f is the input logic signal frequency (MHz, half of the input data

rate, NRZ signaling).

fr is the input stage refresh rate (Mbps).

IDDI(Q), IDDO(Q) are the specified input and output quiescent supply

currents (mA).

To calculate the total IDD1 and IDD2 supply current, the supply

currents for each input and output channel corresponding to

IDD1 and IDD2 are calculated and totaled. Figure 8 and Figure 9

provide per-channel supply currents as a function of data rate

for an unloaded output condition. Figure 10 provides per-

channel supply current as a function of data rate for a 15 pF

output condition. Figure 11 through Figure 14 provide total IDD1

and IDD2 supply current as a function of data rate for

ADuM2400/ADuM2401/ADuM2402 channel configurations.

Preliminary Technical Data ADuM2400/ADuM2401/ADuM2402

Rev. PrD | Page 21 of 23

OUTLINE DIMENSIONS

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MS-013AA

SEATING

PLANE

0.30 (0.0118)

0.10 (0.0039)

0.51 (0.0201)

0.31 (0.0122)

2.65 (0.1043)

2.35 (0.0925)

1.27 (0.0500)

BSC

16 9

8

1

10.65 (0.4193)

10.00 (0.3937)

7.60 (0.2992)

7.40 (0.2913)

10.50 (0.4134)

10.10 (0.3976)

8°

0°

0.75 (0.0295)

0.25 (0.0098) × 45°

1.27 (0.0500)

0.40 (0.0157)

0.33 (0.0130)

0.20 (0.0079)

COPLANARITY

0.10

Figure 21. 16-Lead Standard Small Outline Package [SOIC]— Wide Body (RW-16)

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the

human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

ORDERING GUIDE

Model

Number of

Inputs,

VDD1 Side

Number of

Inputs,

VDD2 Side

Maximum

Data Rate

(Mbps)

Maximum

Propagation

Delay, 5 V (ns)

Maximum

Pulsewidth

Distortion (ns)

Channel-to-

Channel Matching,

Co-Directional

Channels (ns) Package Description

ADuM2400ARWZ* 4 0 1 100 40 40 16-Lead Wide Body SOIC,

Pb-Free

ADuM2400BRWZ* 4 0 10 50 3 3 16-Lead Wide Body SOIC,

Pb-Free

ADuM2400CRWZ* 4 0 100 32 2 2 16-Lead Wide Body SOIC,

Pb-Free

ADuM2401ARWZ* 3 1 1 100 40 40 16-Lead Wide Body SOIC,

Pb-Free

ADuM2401BRWZ* 3 1 10 50 3 3 16-Lead Wide Body SOIC,

Pb-Free

ADuM2401CRWZ* 3 1 100 32 2 2 16-Lead Wide Body SOIC,

Pb-Free

ADuM2402ARWZ* 2 2 1 100 40 40 16-Lead Wide Body SOIC,

Pb-Free

ADuM2402BRWZ* 2 2 10 50 3 3 16-Lead Wide Body SOIC,

Pb-Free

ADuM2402CRWZ* 2 2 100 32 2 2 16-Lead Wide Body SOIC,

Pb-Free

*Tape and Reel is available. The addition of an “-RL” suffix designates a 13” (1000 units) tape and reel option.

ADuM2400/ADuM2401/ADuM2402 Preliminary Technical Data

Rev. PrD| Page 22 of 23

NOTES

Preliminary Technical Data ADuM2400/ADuM2401/ADuM2402

Rev. PrD | Page 23 of 23

NOTES

registered trademarks are the property of their respective owners.

PR05007-0-10/04(PrD)